From a5578a715a095ef1b62e65a362d31c0affc11fc6 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Wed, 24 Jun 2020 21:16:57 +0100 Subject: [PATCH] Regenerate verilog --- src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkBht.v | 2 +- src_SSITH_P3/Verilog_RTL/mkCore.v | 16656 ++++++++-------- src_SSITH_P3/Verilog_RTL/mkCoreW.v | 11778 ++++++----- src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v | 2 +- .../Verilog_RTL/mkDM_Abstract_Commands.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v | 550 +- src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDebug_Module.v | 354 +- src_SSITH_P3/Verilog_RTL/mkDirPredictor.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDivExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/Verilog_RTL/mkEpochManager.v | 2 +- src_SSITH_P3/Verilog_RTL/mkFetchStage.v | 2 +- src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v | 2 +- .../Verilog_RTL/mkFpuMulDivDispToRegFifo.v | 2 +- .../Verilog_RTL/mkFpuMulDivRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSelectPred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSharePred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v | 46 +- src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkICoCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkITlb.v | 2 +- src_SSITH_P3/Verilog_RTL/mkJtagTap.v | 2 +- src_SSITH_P3/Verilog_RTL/mkL2Tlb.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLLCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLLPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMMIOInst.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemLoader.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMulExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkNullTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkP3_Core.v | 70 +- src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v | 13739 ++++++------- src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v | 2 +- src_SSITH_P3/Verilog_RTL/mkProc.v | 5784 +++--- src_SSITH_P3/Verilog_RTL/mkRFileSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRas.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v | 2 +- .../Verilog_RTL/mkReorderBufferSynth.v | 2 +- .../Verilog_RTL/mkReservationStationAlu.v | 2 +- .../mkReservationStationFpuMulDiv.v | 132 +- .../Verilog_RTL/mkReservationStationMem.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSoC_Map.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v | 2 +- .../Verilog_RTL/mkSyncBramFifo_w36_d512.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTagController.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourPred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v | 2 +- src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v | 2 +- src_SSITH_P3/Verilog_RTL/module_alu.v | 2 +- src_SSITH_P3/Verilog_RTL/module_aluBr.v | 2 +- src_SSITH_P3/Verilog_RTL/module_amoExec.v | 2 +- src_SSITH_P3/Verilog_RTL/module_basicExec.v | 2 +- src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v | 2 +- src_SSITH_P3/Verilog_RTL/module_capChecks.v | 2 +- src_SSITH_P3/Verilog_RTL/module_capInspect.v | 2 +- src_SSITH_P3/Verilog_RTL/module_capModify.v | 2 +- .../Verilog_RTL/module_checkForException.v | 2 +- src_SSITH_P3/Verilog_RTL/module_decode.v | 2 +- .../Verilog_RTL/module_decodeBrPred.v | 2 +- .../Verilog_RTL/module_execFpuSimple.v | 2 +- .../Verilog_RTL/module_prepareBoundsCheck.v | 2 +- .../Verilog_RTL/module_setBoundsALU.v | 2 +- .../Verilog_RTL/module_specialRWALU.v | 2 +- .../Verilog_RTL_sim/mkAluDispToRegFifo.v | 2 +- .../Verilog_RTL_sim/mkAluExeToFinFifo.v | 2 +- .../Verilog_RTL_sim/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkBht.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkCore.v | 16364 +++++++-------- src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v | 11778 ++++++----- .../Verilog_RTL_sim/mkDCRqMshrWrapper.v | 2 +- .../Verilog_RTL_sim/mkDM_Abstract_Commands.v | 2 +- .../Verilog_RTL_sim/mkDM_Run_Control.v | 2 +- .../Verilog_RTL_sim/mkDM_System_Bus.v | 550 +- .../Verilog_RTL_sim/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v | 354 +- src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v | 2 +- .../Verilog_RTL_sim/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v | 2 +- .../mkFpuMulDivDispToRegFifo.v | 2 +- .../Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v | 2 +- .../Verilog_RTL_sim/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v | 2 +- .../Verilog_RTL_sim/mkGShareGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v | 46 +- .../Verilog_RTL_sim/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v | 2 +- .../Verilog_RTL_sim/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkITlb.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v | 2 +- .../Verilog_RTL_sim/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v | 2 +- .../Verilog_RTL_sim/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v | 20 +- .../Verilog_RTL_sim/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v | 2 +- .../Verilog_RTL_sim/mkNullTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v | 83 +- src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v | 13739 ++++++------- src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkProc.v | 5812 +++--- src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkRas.v | 2 +- .../Verilog_RTL_sim/mkRegRenamingTable.v | 2 +- .../Verilog_RTL_sim/mkReorderBufferSynth.v | 2 +- .../Verilog_RTL_sim/mkReservationStationAlu.v | 2 +- .../mkReservationStationFpuMulDiv.v | 2 +- .../Verilog_RTL_sim/mkReservationStationMem.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v | 2 +- .../Verilog_RTL_sim/mkScoreboardAggr.v | 2 +- .../Verilog_RTL_sim/mkScoreboardCons.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v | 2 +- .../Verilog_RTL_sim/mkSpecTagManager.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v | 2 +- .../Verilog_RTL_sim/mkSplitTransCache.v | 2 +- .../Verilog_RTL_sim/mkStoreBufferEhr.v | 2 +- .../Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v | 2 +- .../Verilog_RTL_sim/mkSyncFifo_w32_d16.v | 2 +- .../Verilog_RTL_sim/mkTagController.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v | 2 +- .../Verilog_RTL_sim/mkTourPredSecure.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v | 2 +- .../Verilog_RTL_sim/mkXilinxFpDivIP.v | 2 +- .../Verilog_RTL_sim/mkXilinxFpDivSim.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v | 2 +- .../Verilog_RTL_sim/mkXilinxFpFmaIP.v | 2 +- .../Verilog_RTL_sim/mkXilinxFpFmaSim.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v | 2 +- .../Verilog_RTL_sim/mkXilinxFpSqrtIP.v | 2 +- .../Verilog_RTL_sim/mkXilinxFpSqrtSim.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_alu.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v | 2 +- .../Verilog_RTL_sim/module_basicExec.v | 2 +- .../Verilog_RTL_sim/module_brAddrCalc.v | 2 +- .../Verilog_RTL_sim/module_capChecks.v | 2 +- .../Verilog_RTL_sim/module_capInspect.v | 2 +- .../Verilog_RTL_sim/module_capModify.v | 2 +- .../module_checkForException.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_decode.v | 2 +- .../Verilog_RTL_sim/module_decodeBrPred.v | 2 +- .../Verilog_RTL_sim/module_execFpuSimple.v | 2 +- .../module_prepareBoundsCheck.v | 2 +- .../Verilog_RTL_sim/module_setBoundsALU.v | 2 +- .../Verilog_RTL_sim/module_specialRWALU.v | 2 +- .../xilinx_ip/hdl/mkAluDispToRegFifo.v | 2 +- .../xilinx_ip/hdl/mkAluExeToFinFifo.v | 2 +- .../xilinx_ip/hdl/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkBht.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkCore.v | 16656 ++++++++-------- src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v | 11778 ++++++----- .../xilinx_ip/hdl/mkDCRqMshrWrapper.v | 2 +- .../xilinx_ip/hdl/mkDM_Abstract_Commands.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v | 550 +- .../xilinx_ip/hdl/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v | 354 +- src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v | 2 +- .../xilinx_ip/hdl/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v | 2 +- .../xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v | 2 +- .../xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v | 2 +- .../xilinx_ip/hdl/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v | 46 +- .../xilinx_ip/hdl/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v | 2 +- .../xilinx_ip/hdl/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkITlb.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v | 2 +- .../xilinx_ip/hdl/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v | 2 +- .../xilinx_ip/hdl/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v | 70 +- src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v | 13739 ++++++------- src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkProc.v | 5784 +++--- src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkRas.v | 2 +- .../xilinx_ip/hdl/mkRegRenamingTable.v | 2 +- .../xilinx_ip/hdl/mkReorderBufferSynth.v | 2 +- .../xilinx_ip/hdl/mkReservationStationAlu.v | 2 +- .../hdl/mkReservationStationFpuMulDiv.v | 132 +- .../xilinx_ip/hdl/mkReservationStationMem.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v | 2 +- .../xilinx_ip/hdl/mkSplitTransCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v | 2 +- .../xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v | 2 +- .../xilinx_ip/hdl/mkSyncFifo_w32_d16.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTagController.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v | 2 +- .../xilinx_ip/hdl/mkXilinxFpSqrtSim.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_alu.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v | 2 +- .../xilinx_ip/hdl/module_brAddrCalc.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v | 2 +- .../xilinx_ip/hdl/module_capInspect.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_capModify.v | 2 +- .../xilinx_ip/hdl/module_checkForException.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_decode.v | 2 +- .../xilinx_ip/hdl/module_decodeBrPred.v | 2 +- .../xilinx_ip/hdl/module_execFpuSimple.v | 2 +- .../xilinx_ip/hdl/module_prepareBoundsCheck.v | 2 +- .../xilinx_ip/hdl/module_setBoundsALU.v | 2 +- .../xilinx_ip/hdl/module_specialRWALU.v | 2 +- 294 files changed, 77494 insertions(+), 70004 deletions(-) diff --git a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v index 6a2c0a8..3284345 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:37 BST 2020 +// On Wed Jun 24 20:34:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v index 1b9f972..1e0fd92 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:38 BST 2020 +// On Wed Jun 24 20:34:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v index 1399351..65d65b0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:38 BST 2020 +// On Wed Jun 24 20:34:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkBht.v b/src_SSITH_P3/Verilog_RTL/mkBht.v index a4c9ef0..2e6dc57 100644 --- a/src_SSITH_P3/Verilog_RTL/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 64579cd..546290c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:46:40 BST 2020 +// On Wed Jun 24 20:35:56 BST 2020 // // // Ports: @@ -3543,7 +3543,7 @@ module mkCore(CLK, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, MUX_regRenamingTable$rename_0_getRename_1__VAL_3; - wire [13 : 0] MUX_rob$setExecuted_deqLSQ_2__VAL_3, + wire [13 : 0] MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6; wire [10 : 0] MUX_csrf_mccsr_reg$write_1__VAL_1, MUX_csrf_mccsr_reg$write_1__VAL_2; @@ -3691,7 +3691,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, MUX_rg_core_run_state$write_1__SEL_4, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, @@ -3701,17 +3701,17 @@ module mkCore(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h213381; - reg [63 : 0] v__h215650; - reg [63 : 0] v__h271867; - reg [63 : 0] v__h347385; - reg [63 : 0] v__h423711; + reg [63 : 0] v__h213380; + reg [63 : 0] v__h215649; + reg [63 : 0] v__h271864; + reg [63 : 0] v__h347382; + reg [63 : 0] v__h423708; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873; - reg [65 : 0] thin_address__h857274, thin_address__h896908; + reg [65 : 0] thin_address__h857271, thin_address__h896904; reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q363, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q364, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q290, @@ -3750,33 +3750,33 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151, - addr__h505543, - addr__h843840, - addr__h886249, - data_out__h1014871, - trap_val__h994359, - x__h264659; + addr__h505540, + addr__h843837, + addr__h886245, + data_out__h1014865, + trap_val__h994354, + x__h264656; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232, - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233, - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234, - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235, - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236, - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237, - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226, - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227, - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228, - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229, - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230, - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231, - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216, - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217, - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218, - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219, - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220, - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221, + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232, + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233, + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234, + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235, + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236, + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237, + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226, + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227, + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228, + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229, + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230, + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231, + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216, + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217, + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218, + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219, + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220, + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298, @@ -3790,7 +3790,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17090; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040, - x__h264814; + x__h264811; reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q346, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q340, @@ -3801,56 +3801,56 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q362, IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d20175, IF_fetchStage_pipelines_1_first__0058_BITS_267_ETC___d21125; - reg [22 : 0] CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64, - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65, - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95, - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96, - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93, - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94, - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97, - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98, - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100, - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99, - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130, - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131, - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60, - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61, - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128, - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129, - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58, - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59, - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132, - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133, - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62, - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63, - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134, - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135, - _theResult___fst_sfd__h576364, - _theResult___fst_sfd__h585087, - _theResult___fst_sfd__h593669, - _theResult___fst_sfd__h602853, - _theResult___fst_sfd__h611489, - _theResult___fst_sfd__h622115, - _theResult___fst_sfd__h630836, - _theResult___fst_sfd__h639418, - _theResult___fst_sfd__h648602, - _theResult___fst_sfd__h657238, - _theResult___fst_sfd__h667862, - _theResult___fst_sfd__h676583, - _theResult___fst_sfd__h685165, - _theResult___fst_sfd__h694349, - _theResult___fst_sfd__h702985; - reg [17 : 0] thin_otype__h857279, thin_otype__h896913; + reg [22 : 0] CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64, + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65, + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95, + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96, + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93, + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94, + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97, + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98, + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100, + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99, + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130, + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131, + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60, + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61, + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128, + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129, + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58, + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59, + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132, + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133, + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62, + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63, + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134, + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135, + _theResult___fst_sfd__h576361, + _theResult___fst_sfd__h585084, + _theResult___fst_sfd__h593666, + _theResult___fst_sfd__h602850, + _theResult___fst_sfd__h611486, + _theResult___fst_sfd__h622112, + _theResult___fst_sfd__h630833, + _theResult___fst_sfd__h639415, + _theResult___fst_sfd__h648599, + _theResult___fst_sfd__h657235, + _theResult___fst_sfd__h667859, + _theResult___fst_sfd__h676580, + _theResult___fst_sfd__h685162, + _theResult___fst_sfd__h694346, + _theResult___fst_sfd__h702982; + reg [17 : 0] thin_otype__h857276, thin_otype__h896909; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052; - reg [13 : 0] thin_addrBits__h857275, - thin_addrBits__h896909, - thin_bounds_baseBits__h859273, - thin_bounds_baseBits__h898315, - thin_bounds_topBits__h859272, - thin_bounds_topBits__h898314; - reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337, + reg [13 : 0] thin_addrBits__h857272, + thin_addrBits__h896905, + thin_bounds_baseBits__h859270, + thin_bounds_baseBits__h898311, + thin_bounds_topBits__h859269, + thin_bounds_topBits__h898310; + reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337, + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323; reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q348, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q287, @@ -3871,24 +3871,24 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255, CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263, - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171, - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172, - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198, - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199, - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202, - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203, - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154, - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155, - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222, - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223, - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224, - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225, - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194, - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195, - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196, - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197, - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200, - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201, + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171, + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172, + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198, + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199, + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202, + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203, + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154, + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155, + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222, + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223, + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224, + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225, + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194, + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195, + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196, + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197, + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200, + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226, @@ -3898,47 +3898,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706; - reg [7 : 0] CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56, - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57, - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80, - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81, - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78, - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79, - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86, - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87, - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91, - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92, - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115, - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116, - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45, - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46, - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113, - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114, - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43, - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44, - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121, - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122, - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51, - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52, - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126, - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127, + reg [7 : 0] CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56, + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57, + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80, + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81, + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78, + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79, + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86, + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87, + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91, + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92, + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115, + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116, + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45, + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46, + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113, + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114, + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43, + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44, + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121, + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122, + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51, + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52, + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126, + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073, - _theResult___fst_exp__h576363, - _theResult___fst_exp__h585086, - _theResult___fst_exp__h593668, - _theResult___fst_exp__h602852, - _theResult___fst_exp__h611488, - _theResult___fst_exp__h622114, - _theResult___fst_exp__h630835, - _theResult___fst_exp__h639417, - _theResult___fst_exp__h648601, - _theResult___fst_exp__h657237, - _theResult___fst_exp__h667861, - _theResult___fst_exp__h676582, - _theResult___fst_exp__h685164, - _theResult___fst_exp__h694348, - _theResult___fst_exp__h702984; + _theResult___fst_exp__h576360, + _theResult___fst_exp__h585083, + _theResult___fst_exp__h593665, + _theResult___fst_exp__h602849, + _theResult___fst_exp__h611485, + _theResult___fst_exp__h622111, + _theResult___fst_exp__h630832, + _theResult___fst_exp__h639414, + _theResult___fst_exp__h648598, + _theResult___fst_exp__h657234, + _theResult___fst_exp__h667858, + _theResult___fst_exp__h676579, + _theResult___fst_exp__h685161, + _theResult___fst_exp__h694345, + _theResult___fst_exp__h702981; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q338, CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q329, @@ -3954,10 +3954,10 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q360, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q283, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332, CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23, CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q327, CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q252, @@ -3967,10 +3967,10 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_95_TO_3226_BIT_ETC__q328, IF_fetchStage_pipelines_0_first__0049_BITS_264_ETC___d21816, IF_fetchStage_pipelines_1_first__0058_BITS_264_ETC___d21961, - cause_code__h992792, - i__h992808, - t__h212809, - t__h215095; + cause_code__h992787, + i__h992803, + t__h212808, + t__h215094; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__820_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9261_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q245, @@ -3980,8 +3980,8 @@ module mkCore(CLK, CASE_IF_fetchStage_pipelines_0_first__0049_BIT_ETC__q251, CASE_IF_fetchStage_pipelines_1_first__0058_BIT_ETC__q260, CASE_checkForException_0436_BITS_4_TO_0_0_0_1__ETC__q257, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330, CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q320, IF_checkForException_0436_BITS_3_TO_0_0689_EQ__ETC___d20709, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18344, @@ -3996,9 +3996,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0058_BITS_235_ETC___d21151, IF_fetchStage_pipelines_1_first__0058_BITS_264_ETC___d21962, IF_rob_deqPort_0_deq_data__2032_BIT_294_3037_T_ETC___d23059, - i__h992982, - thin_perms_soft__h857526, - thin_perms_soft__h897088; + i__h992977, + thin_perms_soft__h857523, + thin_perms_soft__h897084; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__820_ETC__q246, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9261_ETC__q248, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q244, @@ -4028,15 +4028,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850, IF_fetchStage_pipelines_0_first__0049_BITS_231_ETC___d20230, IF_fetchStage_pipelines_1_first__0058_BITS_231_ETC___d21180, - x__h501025, - x__h508693; + x__h501022, + x__h508690; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q367, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - thin_reserved__h857278, - thin_reserved__h896912; + thin_reserved__h857275, + thin_reserved__h896908; reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161, @@ -4077,46 +4077,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266, CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q270, CASE_fetchStagepipelines_1_first_BITS_267_TO__ETC__q272, - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73, - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72, - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181, - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175, - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179, - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173, - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102, - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101, - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183, - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177, - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104, - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103, - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106, - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105, - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160, - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108, - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107, - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214, - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204, - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136, - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210, - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206, - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67, - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66, - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212, - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208, - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69, - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68, - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140, - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71, - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70, - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143, - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267, + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73, + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72, + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181, + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175, + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179, + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173, + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102, + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101, + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183, + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177, + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104, + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103, + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106, + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105, + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160, + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108, + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107, + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214, + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204, + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136, + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210, + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206, + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67, + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66, + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212, + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208, + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69, + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68, + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140, + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71, + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70, + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143, + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19008, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19044, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19053, @@ -4247,20 +4247,20 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5542; wire [128 : 0] amoExec___d4904, amoExec___d773, - new_pc__h871752, - new_pc__h909836, - next_pc__h1007609, - pc__h960829, - v__h1007648, - v__h1008101, - x__h878730, - x__h912383; + new_pc__h871748, + new_pc__h909831, + next_pc__h1007604, + pc__h960824, + v__h1007643, + v__h1008096, + x__h878726, + x__h912378; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871, coreFix_memExe_regToExeQ_first__633_BITS_139_T_ETC___d4052, - x__h183367, - x__h199219; + x__h183366, + x__h199218; wire [108 : 0] IF_fetchStage_pipelines_0_first__0049_BITS_237_ETC___d20404, IF_fetchStage_pipelines_1_first__0058_BITS_237_ETC___d21354; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3568; @@ -4284,70 +4284,70 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16238, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3036, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3405, - addTop__h239914, - addTop__h241071, - addTop__h254680, - address__h996966, - address__h997310, - address__h997623, - address__h997967, + addTop__h239913, + addTop__h241070, + addTop__h254678, + address__h996961, + address__h997305, + address__h997618, + address__h997962, coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389, coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692, - cr_address__h865497, - cr_address__h866045, - cr_address__h904119, - cr_address__h904667, - data_address__h1013598, - data_address__h1014452, - in__h239745, - in__h240902, - in__h254511, - in__h995128, - pc_address__h992211, - pointer__h1005920, - pointer__h1025233, - pointer__h242569, - res_address__h126791, - res_address__h139703, - res_address__h178866, - res_address__h197631, - res_address__h216390, - res_address__h235267, - res_address__h567273, - res_address__h568125, - res_address__h613882, - res_address__h659629, - res_address__h705438, - res_address__h706298, - res_address__h848497, - res_address__h890898, - result__h240541, - result__h241698, - result__h255307, - result_d_address__h242780, - ret__h239918, - ret__h241075, - ret__h254684, - x__h1005944, - x__h1025256, - x__h235690, - x__h239763, - x__h239911, - x__h240920, - x__h241068, - x__h248052, - x__h254529, - x__h254677, - x__h995146, - x__h997160, - x__h997464, - x__h997817, - x__h998121, - y__h239762, - y__h240919, - y__h254528, - y__h995145; + cr_address__h865494, + cr_address__h866042, + cr_address__h904115, + cr_address__h904663, + data_address__h1013592, + data_address__h1014446, + in__h239744, + in__h240901, + in__h254509, + in__h995123, + pc_address__h992206, + pointer__h1005915, + pointer__h1025227, + pointer__h242568, + res_address__h126790, + res_address__h139702, + res_address__h178865, + res_address__h197630, + res_address__h216389, + res_address__h235266, + res_address__h567269, + res_address__h568122, + res_address__h613879, + res_address__h659626, + res_address__h705435, + res_address__h706295, + res_address__h848494, + res_address__h890894, + result__h240540, + result__h241697, + result__h255305, + result_d_address__h242779, + ret__h239917, + ret__h241074, + ret__h254682, + x__h1005939, + x__h1025250, + x__h235689, + x__h239762, + x__h239910, + x__h240919, + x__h241067, + x__h248050, + x__h254527, + x__h254675, + x__h995141, + x__h997155, + x__h997459, + x__h997812, + x__h998116, + y__h239761, + y__h240918, + y__h254526, + y__h995140; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13306, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12467, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12468, @@ -4373,173 +4373,173 @@ module mkCore(CLK, SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448, _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602, _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527, - _theResult___fst__h836055, - _theResult___snd__h836056, - a___1__h835774, - a___1__h836060, - a__h835633, - addBase__h239805, - addBase__h240962, - addBase__h254571, - addr__h148408, - addr__h151984, - addr__h235261, - addr__h987208, - address__h1008563, - address__h996900, - address__h996950, - b___1__h835775, - b___1__h836105, - b__h835634, - base__h996861, - base__h996915, + _theResult___fst__h836052, + _theResult___snd__h836053, + a___1__h835771, + a___1__h836057, + a__h835630, + addBase__h239804, + addBase__h240961, + addBase__h254569, + addr__h148407, + addr__h151983, + addr__h235260, + addr__h987203, + address__h1008558, + address__h996895, + address__h996945, + b___1__h835772, + b___1__h836102, + b__h835631, + base__h996856, + base__h996910, csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592, csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515, - data___1__h705460, - data___1__h706320, - data__h567607, - data__h613367, - data__h659114, - data__h704928, - data__h705760, - data__h705791, - fcsr_csr__read__h849072, - fflags_csr__read__h849047, - frm_csr__read__h849058, - mask__h996972, - mask__h997629, - mcause_csr__read__h850488, - mcounteren_csr__read__h850309, - medeleg_csr__read__h849989, - mideleg_csr__read__h850087, - mie_csr__read__h850214, - mip_csr__read__h850727, - mstatus_csr__read__h849835, - n__read__h1008993, + data___1__h705457, + data___1__h706317, + data__h567604, + data__h613364, + data__h659111, + data__h704925, + data__h705757, + data__h705788, + fcsr_csr__read__h849069, + fflags_csr__read__h849044, + frm_csr__read__h849055, + mask__h996967, + mask__h997624, + mcause_csr__read__h850485, + mcounteren_csr__read__h850306, + medeleg_csr__read__h849986, + mideleg_csr__read__h850084, + mie_csr__read__h850211, + mip_csr__read__h850724, + mstatus_csr__read__h849832, + n__read__h1008988, n__read__h7877, - newAddrDiff__h996973, - newAddrDiff__h997317, - newAddrDiff__h997630, - newAddrDiff__h997974, - offset__h242559, - q___1__h706385, - rVal1__h714446, - rVal2__h714447, - r___1__h706411, - res_data__h568165, - res_data__h568170, - res_data__h613919, - res_data__h613924, - res_data__h659666, - res_data__h659671, - resp_addr__h509039, - rg_tdata1__read__h851828, + newAddrDiff__h996968, + newAddrDiff__h997312, + newAddrDiff__h997625, + newAddrDiff__h997969, + offset__h242558, + q___1__h706382, + rVal1__h714443, + rVal2__h714444, + r___1__h706408, + res_data__h568162, + res_data__h568167, + res_data__h613916, + res_data__h613921, + res_data__h659663, + res_data__h659668, + resp_addr__h509036, + rg_tdata1__read__h851825, robdeqPort_0_deq_data_BITS_95_TO_32__q326, - satp_csr__read__h849689, - scause_csr__read__h849486, - scounteren_csr__read__h849391, - sie_csr__read__h849338, - sip_csr__read__h849626, - sstatus_csr__read__h849268, - thin_address__h996854, - tmpAddr__h242768, - trap_val__h994512, - upd__h1009069, + satp_csr__read__h849686, + scause_csr__read__h849483, + scounteren_csr__read__h849388, + sie_csr__read__h849335, + sip_csr__read__h849623, + sstatus_csr__read__h849265, + thin_address__h996849, + tmpAddr__h242767, + trap_val__h994507, + upd__h1009064, upd__h3035, upd__h3645, upd__h7946, - value__h239635, - value__h239799, - value__h240792, - value__h240956, - value__h254401, - value__h254565, - x__h127272, - x__h140188, - x__h183449, - x__h202200, - x__h216766, - x__h239653, - x__h239655, - x__h240810, - x__h240812, - x__h242708, + value__h239634, + value__h239798, + value__h240791, + value__h240955, + value__h254399, + value__h254563, + x__h127271, + x__h140187, + x__h183448, + x__h202199, + x__h216765, + x__h239652, + x__h239654, + x__h240809, + x__h240811, + x__h242707, + x__h254417, x__h254419, - x__h254421, - x__h714355, - x__h714356, - x__h714357, - x__h865674, - x__h866222, - x__h904296, - x__h904844, - x__h992383, - x__h995059, - x__h995061, + x__h714352, + x__h714353, + x__h714354, + x__h865671, + x__h866219, + x__h904292, + x__h904840, + x__h992378, + x__h995054, + x__h995056, x_addr__h19852, x_addr__h44221, - x_addr__h535302, - x_quotient__h705674, - x_reg_ifc__read__h849177, - x_remainder__h705675, - y__h1011220, - y__h997089, - y__h997746, - y_avValue__h710401, - y_avValue__h711034, - y_avValue__h711661, - y_avValue_snd_snd_snd_snd_snd__h1010691, - y_avValue_snd_snd_snd_snd_snd__h1011273, - y_avValue_snd_snd_snd_snd_snd__h1011302; + x_addr__h535298, + x_quotient__h705671, + x_reg_ifc__read__h849174, + x_remainder__h705672, + y__h1011215, + y__h997084, + y__h997741, + y_avValue__h710398, + y_avValue__h711031, + y_avValue__h711658, + y_avValue_snd_snd_snd_snd_snd__h1010686, + y_avValue_snd_snd_snd_snd_snd__h1011268, + y_avValue_snd_snd_snd_snd_snd__h1011297; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785, - r1__read__h852705, - r1__read__h853109, - r1__read__h853619, - r1__read__h853638, - r1__read__h853871, - r1__read__h854037, - r1__read__h854130, - r1__read__h854149; - wire [61 : 0] r1__read__h852707, - r1__read__h853111, - r1__read__h853621, - r1__read__h853640, - r1__read__h853873, - r1__read__h854013, - r1__read__h854039, - r1__read__h854132, - r1__read__h854151; - wire [60 : 0] r1__read__h853875, - r1__read__h854015, - r1__read__h854041, - r1__read__h854153; - wire [59 : 0] r1__read__h852709, - r1__read__h853113, - r1__read__h853642, - r1__read__h853877, - r1__read__h854043, - r1__read__h854155; + r1__read__h852702, + r1__read__h853106, + r1__read__h853616, + r1__read__h853635, + r1__read__h853868, + r1__read__h854034, + r1__read__h854127, + r1__read__h854146; + wire [61 : 0] r1__read__h852704, + r1__read__h853108, + r1__read__h853618, + r1__read__h853637, + r1__read__h853870, + r1__read__h854010, + r1__read__h854036, + r1__read__h854129, + r1__read__h854148; + wire [60 : 0] r1__read__h853872, + r1__read__h854012, + r1__read__h854038, + r1__read__h854150; + wire [59 : 0] r1__read__h852706, + r1__read__h853110, + r1__read__h853639, + r1__read__h853874, + r1__read__h854040, + r1__read__h854152; wire [58 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5478, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5520, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6956, - r1__read__h852711, - r1__read__h853115, - r1__read__h853631, - r1__read__h853644, - r1__read__h853879, - r1__read__h854045, - r1__read__h854142, - r1__read__h854157; + r1__read__h852708, + r1__read__h853112, + r1__read__h853628, + r1__read__h853641, + r1__read__h853876, + r1__read__h854042, + r1__read__h854139, + r1__read__h854154; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7193, - r1__read__h852713, - r1__read__h853117, - r1__read__h853646, - r1__read__h853881, - r1__read__h854017, - r1__read__h854047, - r1__read__h854159, - y__h422493; + r1__read__h852710, + r1__read__h853114, + r1__read__h853643, + r1__read__h853878, + r1__read__h854014, + r1__read__h854044, + r1__read__h854156, + y__h422490; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74, @@ -4567,195 +4567,195 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663, - _theResult____h576381, - _theResult____h594020, - _theResult____h622132, - _theResult____h639769, - _theResult____h667879, - _theResult____h685516, - _theResult____h735554, - _theResult____h774407, - _theResult____h813711, - _theResult___snd__h584503, - _theResult___snd__h584514, - _theResult___snd__h584516, - _theResult___snd__h584526, - _theResult___snd__h584532, - _theResult___snd__h584555, - _theResult___snd__h593099, - _theResult___snd__h593101, - _theResult___snd__h593108, - _theResult___snd__h593114, - _theResult___snd__h593137, - _theResult___snd__h602269, - _theResult___snd__h602280, - _theResult___snd__h602282, - _theResult___snd__h602292, - _theResult___snd__h602298, - _theResult___snd__h602321, - _theResult___snd__h610889, - _theResult___snd__h610903, - _theResult___snd__h610909, - _theResult___snd__h610927, - _theResult___snd__h630252, - _theResult___snd__h630263, - _theResult___snd__h630265, - _theResult___snd__h630275, - _theResult___snd__h630281, - _theResult___snd__h630304, - _theResult___snd__h638848, - _theResult___snd__h638850, - _theResult___snd__h638857, - _theResult___snd__h638863, - _theResult___snd__h638886, - _theResult___snd__h648018, - _theResult___snd__h648029, - _theResult___snd__h648031, - _theResult___snd__h648041, - _theResult___snd__h648047, - _theResult___snd__h648070, - _theResult___snd__h656638, - _theResult___snd__h656652, - _theResult___snd__h656658, - _theResult___snd__h656676, - _theResult___snd__h675999, - _theResult___snd__h676010, - _theResult___snd__h676012, - _theResult___snd__h676022, - _theResult___snd__h676028, - _theResult___snd__h676051, - _theResult___snd__h684595, - _theResult___snd__h684597, - _theResult___snd__h684604, - _theResult___snd__h684610, - _theResult___snd__h684633, - _theResult___snd__h693765, - _theResult___snd__h693776, - _theResult___snd__h693778, - _theResult___snd__h693788, - _theResult___snd__h693794, - _theResult___snd__h693817, - _theResult___snd__h702385, - _theResult___snd__h702399, - _theResult___snd__h702405, - _theResult___snd__h702423, - _theResult___snd__h734164, - _theResult___snd__h734166, - _theResult___snd__h734173, - _theResult___snd__h734179, - _theResult___snd__h734202, - _theResult___snd__h743801, - _theResult___snd__h743812, - _theResult___snd__h743814, - _theResult___snd__h743824, - _theResult___snd__h743830, - _theResult___snd__h743853, - _theResult___snd__h752569, - _theResult___snd__h752583, - _theResult___snd__h752589, - _theResult___snd__h752607, - _theResult___snd__h773017, - _theResult___snd__h773019, - _theResult___snd__h773026, - _theResult___snd__h773032, - _theResult___snd__h773055, - _theResult___snd__h782654, - _theResult___snd__h782665, - _theResult___snd__h782667, - _theResult___snd__h782677, - _theResult___snd__h782683, - _theResult___snd__h782706, - _theResult___snd__h791422, - _theResult___snd__h791436, - _theResult___snd__h791442, - _theResult___snd__h791460, - _theResult___snd__h812321, - _theResult___snd__h812323, - _theResult___snd__h812330, - _theResult___snd__h812336, - _theResult___snd__h812359, - _theResult___snd__h821958, - _theResult___snd__h821969, - _theResult___snd__h821971, - _theResult___snd__h821981, - _theResult___snd__h821987, - _theResult___snd__h822010, - _theResult___snd__h830726, - _theResult___snd__h830740, - _theResult___snd__h830746, - _theResult___snd__h830764, - r1__read__h853883, - r1__read__h854019, - r1__read__h854049, - r1__read__h854161, - result__h594633, - result__h640382, - result__h686129, - result__h736167, - result__h775020, - result__h814324, - sfd__h568776, - sfd__h614530, - sfd__h660277, - sfd__h715187, - sfd__h754181, - sfd__h793485, - sfdin__h584486, - sfdin__h602252, - sfdin__h630235, - sfdin__h648001, - sfdin__h675982, - sfdin__h693748, - sfdin__h743784, - sfdin__h782637, - sfdin__h821941, - x__h594730, - x__h640479, - x__h686226, - x__h736262, - x__h775115, - x__h814419; + _theResult____h576378, + _theResult____h594017, + _theResult____h622129, + _theResult____h639766, + _theResult____h667876, + _theResult____h685513, + _theResult____h735551, + _theResult____h774404, + _theResult____h813708, + _theResult___snd__h584500, + _theResult___snd__h584511, + _theResult___snd__h584513, + _theResult___snd__h584523, + _theResult___snd__h584529, + _theResult___snd__h584552, + _theResult___snd__h593096, + _theResult___snd__h593098, + _theResult___snd__h593105, + _theResult___snd__h593111, + _theResult___snd__h593134, + _theResult___snd__h602266, + _theResult___snd__h602277, + _theResult___snd__h602279, + _theResult___snd__h602289, + _theResult___snd__h602295, + _theResult___snd__h602318, + _theResult___snd__h610886, + _theResult___snd__h610900, + _theResult___snd__h610906, + _theResult___snd__h610924, + _theResult___snd__h630249, + _theResult___snd__h630260, + _theResult___snd__h630262, + _theResult___snd__h630272, + _theResult___snd__h630278, + _theResult___snd__h630301, + _theResult___snd__h638845, + _theResult___snd__h638847, + _theResult___snd__h638854, + _theResult___snd__h638860, + _theResult___snd__h638883, + _theResult___snd__h648015, + _theResult___snd__h648026, + _theResult___snd__h648028, + _theResult___snd__h648038, + _theResult___snd__h648044, + _theResult___snd__h648067, + _theResult___snd__h656635, + _theResult___snd__h656649, + _theResult___snd__h656655, + _theResult___snd__h656673, + _theResult___snd__h675996, + _theResult___snd__h676007, + _theResult___snd__h676009, + _theResult___snd__h676019, + _theResult___snd__h676025, + _theResult___snd__h676048, + _theResult___snd__h684592, + _theResult___snd__h684594, + _theResult___snd__h684601, + _theResult___snd__h684607, + _theResult___snd__h684630, + _theResult___snd__h693762, + _theResult___snd__h693773, + _theResult___snd__h693775, + _theResult___snd__h693785, + _theResult___snd__h693791, + _theResult___snd__h693814, + _theResult___snd__h702382, + _theResult___snd__h702396, + _theResult___snd__h702402, + _theResult___snd__h702420, + _theResult___snd__h734161, + _theResult___snd__h734163, + _theResult___snd__h734170, + _theResult___snd__h734176, + _theResult___snd__h734199, + _theResult___snd__h743798, + _theResult___snd__h743809, + _theResult___snd__h743811, + _theResult___snd__h743821, + _theResult___snd__h743827, + _theResult___snd__h743850, + _theResult___snd__h752566, + _theResult___snd__h752580, + _theResult___snd__h752586, + _theResult___snd__h752604, + _theResult___snd__h773014, + _theResult___snd__h773016, + _theResult___snd__h773023, + _theResult___snd__h773029, + _theResult___snd__h773052, + _theResult___snd__h782651, + _theResult___snd__h782662, + _theResult___snd__h782664, + _theResult___snd__h782674, + _theResult___snd__h782680, + _theResult___snd__h782703, + _theResult___snd__h791419, + _theResult___snd__h791433, + _theResult___snd__h791439, + _theResult___snd__h791457, + _theResult___snd__h812318, + _theResult___snd__h812320, + _theResult___snd__h812327, + _theResult___snd__h812333, + _theResult___snd__h812356, + _theResult___snd__h821955, + _theResult___snd__h821966, + _theResult___snd__h821968, + _theResult___snd__h821978, + _theResult___snd__h821984, + _theResult___snd__h822007, + _theResult___snd__h830723, + _theResult___snd__h830737, + _theResult___snd__h830743, + _theResult___snd__h830761, + r1__read__h853880, + r1__read__h854016, + r1__read__h854046, + r1__read__h854158, + result__h594630, + result__h640379, + result__h686126, + result__h736164, + result__h775017, + result__h814321, + sfd__h568773, + sfd__h614527, + sfd__h660274, + sfd__h715184, + sfd__h754178, + sfd__h793482, + sfdin__h584483, + sfdin__h602249, + sfdin__h630232, + sfdin__h647998, + sfdin__h675979, + sfdin__h693745, + sfdin__h743781, + sfdin__h782634, + sfdin__h821938, + x__h594727, + x__h640476, + x__h686223, + x__h736259, + x__h775112, + x__h814416; wire [55 : 0] coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3567, - r1__read__h852715, - r1__read__h853119, - r1__read__h853648, - r1__read__h853885, - r1__read__h854051, - r1__read__h854163; + r1__read__h852712, + r1__read__h853116, + r1__read__h853645, + r1__read__h853882, + r1__read__h854048, + r1__read__h854160; wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19198, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17093, - r1__read__h852717, - r1__read__h853121, - r1__read__h853650, - r1__read__h853887, - r1__read__h854053, - r1__read__h854165; - wire [53 : 0] r1__read__h853996, - r1__read__h854021, - r1__read__h854055, - r1__read__h854167, - sfd__h734231, - sfd__h743882, - sfd__h752642, - sfd__h773084, - sfd__h782735, - sfd__h791495, - sfd__h812388, - sfd__h822039, - sfd__h830799, - value__h577003, - value__h622752, - value__h668499; + r1__read__h852714, + r1__read__h853118, + r1__read__h853647, + r1__read__h853884, + r1__read__h854050, + r1__read__h854162; + wire [53 : 0] r1__read__h853993, + r1__read__h854018, + r1__read__h854052, + r1__read__h854164, + sfd__h734228, + sfd__h743879, + sfd__h752639, + sfd__h773081, + sfd__h782732, + sfd__h791492, + sfd__h812385, + sfd__h822036, + sfd__h830796, + value__h577000, + value__h622749, + value__h668496; wire [52 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3566, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19564, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19628, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17485, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17549, - r1__read__h853889, - r1__read__h853998, - r1__read__h854023, - r1__read__h854057, - r1__read__h854169; + r1__read__h853886, + r1__read__h853995, + r1__read__h854020, + r1__read__h854054, + r1__read__h854166; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982, @@ -4777,85 +4777,85 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784, - _theResult___fst_sfd__h719141, + _theResult___fst_sfd__h719138, + _theResult___fst_sfd__h734966, _theResult___fst_sfd__h734969, - _theResult___fst_sfd__h734972, + _theResult___fst_sfd__h744617, _theResult___fst_sfd__h744620, - _theResult___fst_sfd__h744623, + _theResult___fst_sfd__h753401, _theResult___fst_sfd__h753404, - _theResult___fst_sfd__h753407, - _theResult___fst_sfd__h753416, - _theResult___fst_sfd__h753422, - _theResult___fst_sfd__h757994, + _theResult___fst_sfd__h753413, + _theResult___fst_sfd__h753419, + _theResult___fst_sfd__h757991, + _theResult___fst_sfd__h773819, _theResult___fst_sfd__h773822, - _theResult___fst_sfd__h773825, + _theResult___fst_sfd__h783470, _theResult___fst_sfd__h783473, - _theResult___fst_sfd__h783476, + _theResult___fst_sfd__h792254, _theResult___fst_sfd__h792257, - _theResult___fst_sfd__h792260, - _theResult___fst_sfd__h792269, - _theResult___fst_sfd__h792275, - _theResult___fst_sfd__h797298, + _theResult___fst_sfd__h792266, + _theResult___fst_sfd__h792272, + _theResult___fst_sfd__h797295, + _theResult___fst_sfd__h813123, _theResult___fst_sfd__h813126, - _theResult___fst_sfd__h813129, + _theResult___fst_sfd__h822774, _theResult___fst_sfd__h822777, - _theResult___fst_sfd__h822780, + _theResult___fst_sfd__h831558, _theResult___fst_sfd__h831561, - _theResult___fst_sfd__h831564, - _theResult___fst_sfd__h831573, - _theResult___fst_sfd__h831579, - _theResult___sfd__h734869, - _theResult___sfd__h744520, - _theResult___sfd__h753304, - _theResult___sfd__h773722, - _theResult___sfd__h783373, - _theResult___sfd__h792157, - _theResult___sfd__h813026, - _theResult___sfd__h822677, - _theResult___sfd__h831461, - _theResult___snd_fst_sfd__h715141, - _theResult___snd_fst_sfd__h734975, - _theResult___snd_fst_sfd__h753410, - _theResult___snd_fst_sfd__h754135, - _theResult___snd_fst_sfd__h773828, - _theResult___snd_fst_sfd__h792263, - _theResult___snd_fst_sfd__h793439, - _theResult___snd_fst_sfd__h813132, - _theResult___snd_fst_sfd__h831567, - mask__h239915, - mask__h241072, - mask__h254681, - out___1_sfd__h714889, - out___1_sfd__h753883, - out___1_sfd__h793187, - out_sfd__h734872, - out_sfd__h744523, - out_sfd__h753307, - out_sfd__h773725, - out_sfd__h783376, - out_sfd__h792160, - out_sfd__h813029, - out_sfd__h822680, - out_sfd__h831464; - wire [50 : 0] r1__read__h852719, r1__read__h853891; + _theResult___fst_sfd__h831570, + _theResult___fst_sfd__h831576, + _theResult___sfd__h734866, + _theResult___sfd__h744517, + _theResult___sfd__h753301, + _theResult___sfd__h773719, + _theResult___sfd__h783370, + _theResult___sfd__h792154, + _theResult___sfd__h813023, + _theResult___sfd__h822674, + _theResult___sfd__h831458, + _theResult___snd_fst_sfd__h715138, + _theResult___snd_fst_sfd__h734972, + _theResult___snd_fst_sfd__h753407, + _theResult___snd_fst_sfd__h754132, + _theResult___snd_fst_sfd__h773825, + _theResult___snd_fst_sfd__h792260, + _theResult___snd_fst_sfd__h793436, + _theResult___snd_fst_sfd__h813129, + _theResult___snd_fst_sfd__h831564, + mask__h239914, + mask__h241071, + mask__h254679, + out___1_sfd__h714886, + out___1_sfd__h753880, + out___1_sfd__h793184, + out_sfd__h734869, + out_sfd__h744520, + out_sfd__h753304, + out_sfd__h773722, + out_sfd__h783373, + out_sfd__h792157, + out_sfd__h813026, + out_sfd__h822677, + out_sfd__h831461; + wire [50 : 0] r1__read__h852716, r1__read__h853888; wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q5, coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3, - highOffsetBits__h242578, - mask__h239806, - mask__h240963, - mask__h254572, - r1__read__h854000, - signBits__h242575, - x__h242605; - wire [48 : 0] r1__read__h852721, r1__read__h853893, r1__read__h854002; - wire [46 : 0] r1__read__h852723, r1__read__h853895; - wire [45 : 0] r1__read__h852725, r1__read__h853897; - wire [44 : 0] r1__read__h852727, r1__read__h853899; - wire [43 : 0] r1__read__h852729, r1__read__h853901; - wire [42 : 0] r1__read__h853903; - wire [41 : 0] r1__read__h853905; - wire [40 : 0] r1__read__h853907; + highOffsetBits__h242577, + mask__h239805, + mask__h240962, + mask__h254570, + r1__read__h853997, + signBits__h242574, + x__h242604; + wire [48 : 0] r1__read__h852718, r1__read__h853890, r1__read__h853999; + wire [46 : 0] r1__read__h852720, r1__read__h853892; + wire [45 : 0] r1__read__h852722, r1__read__h853894; + wire [44 : 0] r1__read__h852724, r1__read__h853896; + wire [43 : 0] r1__read__h852726, r1__read__h853898; + wire [42 : 0] r1__read__h853900; + wire [41 : 0] r1__read__h853902; + wire [40 : 0] r1__read__h853904; wire [38 : 0] IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_c_ETC___d22659; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954, IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120, @@ -4880,16 +4880,16 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21, coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16, - data05760_BITS_31_TO_0__q25, - r1__read__h852731, - r1__read__h853909, - x__h568180, - x__h613934, + data05757_BITS_31_TO_0__q25, + r1__read__h852728, + r1__read__h853906, + x__h568177, + x__h613931, x__h65608, - x__h659681, + x__h659678, x_data__h60109; - wire [29 : 0] r1__read__h852733, r1__read__h853911; - wire [27 : 0] r1__read__h853913; + wire [29 : 0] r1__read__h852730, r1__read__h853908; + wire [27 : 0] r1__read__h853910; wire [25 : 0] IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677, IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19904, IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19935, @@ -4899,21 +4899,21 @@ module mkCore(CLK, IF_csrf_mepcc_reg_read_wget__3118_BIT_34_3127__ETC___d23135, IF_csrf_rg_dpc_read__6185_BIT_34_3810_THEN_csr_ETC___d23818, IF_csrf_sepcc_reg_read_wget__3089_BIT_34_3098__ETC___d23106; - wire [24 : 0] sfd__h584584, - sfd__h593166, - sfd__h602350, - sfd__h610962, - sfd__h630333, - sfd__h638915, - sfd__h648099, - sfd__h656711, - sfd__h676080, - sfd__h684662, - sfd__h693846, - sfd__h702458, - value__h719770, - value__h758623, - value__h797927; + wire [24 : 0] sfd__h584581, + sfd__h593163, + sfd__h602347, + sfd__h610959, + sfd__h630330, + sfd__h638912, + sfd__h648096, + sfd__h656708, + sfd__h676077, + sfd__h684659, + sfd__h693843, + sfd__h702455, + value__h719767, + value__h758620, + value__h797924; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856, @@ -4938,67 +4938,67 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129, - _theResult___fst_sfd__h585090, - _theResult___fst_sfd__h593672, - _theResult___fst_sfd__h602856, - _theResult___fst_sfd__h611492, - _theResult___fst_sfd__h611501, - _theResult___fst_sfd__h611507, - _theResult___fst_sfd__h630839, - _theResult___fst_sfd__h639421, - _theResult___fst_sfd__h648605, - _theResult___fst_sfd__h657241, - _theResult___fst_sfd__h657250, - _theResult___fst_sfd__h657256, - _theResult___fst_sfd__h676586, - _theResult___fst_sfd__h685168, - _theResult___fst_sfd__h694352, - _theResult___fst_sfd__h702988, - _theResult___fst_sfd__h702997, - _theResult___fst_sfd__h703003, - _theResult___sfd__h585009, - _theResult___sfd__h593591, - _theResult___sfd__h602775, - _theResult___sfd__h611411, - _theResult___sfd__h611513, - _theResult___sfd__h630758, - _theResult___sfd__h639340, - _theResult___sfd__h648524, - _theResult___sfd__h657160, - _theResult___sfd__h657262, - _theResult___sfd__h676505, - _theResult___sfd__h685087, - _theResult___sfd__h694271, - _theResult___sfd__h702907, - _theResult___sfd__h703009, - _theResult___snd_fst_sfd__h568726, - _theResult___snd_fst_sfd__h593675, - _theResult___snd_fst_sfd__h611495, - _theResult___snd_fst_sfd__h614480, - _theResult___snd_fst_sfd__h639424, - _theResult___snd_fst_sfd__h657244, - _theResult___snd_fst_sfd__h660227, - _theResult___snd_fst_sfd__h685171, - _theResult___snd_fst_sfd__h702991, - f1_sfd__h714826, - f2_sfd__h753820, - f3_sfd__h793124, - out_f_sfd__h611790, - out_f_sfd__h657539, - out_f_sfd__h703286, - out_sfd__h585012, - out_sfd__h593594, - out_sfd__h602778, - out_sfd__h611414, - out_sfd__h630761, - out_sfd__h639343, - out_sfd__h648527, - out_sfd__h657163, - out_sfd__h676508, - out_sfd__h685090, - out_sfd__h694274, - out_sfd__h702910; - wire [19 : 0] r1__read__h853848; + _theResult___fst_sfd__h585087, + _theResult___fst_sfd__h593669, + _theResult___fst_sfd__h602853, + _theResult___fst_sfd__h611489, + _theResult___fst_sfd__h611498, + _theResult___fst_sfd__h611504, + _theResult___fst_sfd__h630836, + _theResult___fst_sfd__h639418, + _theResult___fst_sfd__h648602, + _theResult___fst_sfd__h657238, + _theResult___fst_sfd__h657247, + _theResult___fst_sfd__h657253, + _theResult___fst_sfd__h676583, + _theResult___fst_sfd__h685165, + _theResult___fst_sfd__h694349, + _theResult___fst_sfd__h702985, + _theResult___fst_sfd__h702994, + _theResult___fst_sfd__h703000, + _theResult___sfd__h585006, + _theResult___sfd__h593588, + _theResult___sfd__h602772, + _theResult___sfd__h611408, + _theResult___sfd__h611510, + _theResult___sfd__h630755, + _theResult___sfd__h639337, + _theResult___sfd__h648521, + _theResult___sfd__h657157, + _theResult___sfd__h657259, + _theResult___sfd__h676502, + _theResult___sfd__h685084, + _theResult___sfd__h694268, + _theResult___sfd__h702904, + _theResult___sfd__h703006, + _theResult___snd_fst_sfd__h568723, + _theResult___snd_fst_sfd__h593672, + _theResult___snd_fst_sfd__h611492, + _theResult___snd_fst_sfd__h614477, + _theResult___snd_fst_sfd__h639421, + _theResult___snd_fst_sfd__h657241, + _theResult___snd_fst_sfd__h660224, + _theResult___snd_fst_sfd__h685168, + _theResult___snd_fst_sfd__h702988, + f1_sfd__h714823, + f2_sfd__h753817, + f3_sfd__h793121, + out_f_sfd__h611787, + out_f_sfd__h657536, + out_f_sfd__h703283, + out_sfd__h585009, + out_sfd__h593591, + out_sfd__h602775, + out_sfd__h611411, + out_sfd__h630758, + out_sfd__h639340, + out_sfd__h648524, + out_sfd__h657160, + out_sfd__h676505, + out_sfd__h685087, + out_sfd__h694271, + out_sfd__h702907; + wire [19 : 0] r1__read__h853845; wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, @@ -5007,8 +5007,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10, - INV_x83367_BITS_108_TO_90__q33, - INV_x99219_BITS_108_TO_90__q35; + INV_x83366_BITS_108_TO_90__q33, + INV_x99218_BITS_108_TO_90__q35; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18846, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18847, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16462, @@ -5025,23 +5025,23 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3547; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116, IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3524, - _theResult____h917995, - base__h239640, - base__h240797, - base__h254406, - base__h995046, - enabled_ints___1__h918520, - enabled_ints__h918566, - offset__h239641, - offset__h240798, - offset__h254407, - offset__h995047, - pend_ints__h917993, - x__h240013, - x__h241170, - x__h254779, - x__h894478, - y__h918532; + _theResult____h917990, + base__h239639, + base__h240796, + base__h254404, + base__h995041, + enabled_ints___1__h918515, + enabled_ints__h918561, + offset__h239640, + offset__h240797, + offset__h254405, + offset__h995042, + pend_ints__h917988, + x__h240012, + x__h241169, + x__h254777, + x__h894474, + y__h918527; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18632, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18633, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16248, @@ -5063,65 +5063,65 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16253, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3056, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3413, - b_base__h127497, - b_base__h140413, - b_base__h183674, - b_base__h202425, - b_base__h216991, - b_base__h865912, - b_base__h866460, - b_base__h904534, - b_base__h905082, - b_base__h992608, + b_base__h127496, + b_base__h140412, + b_base__h183673, + b_base__h202424, + b_base__h216990, + b_base__h865909, + b_base__h866457, + b_base__h904530, + b_base__h905078, + b_base__h992603, checkForException___d20436, checkForException___d21375, - cr_addrBits__h865498, - cr_addrBits__h866046, - cr_addrBits__h904120, - cr_addrBits__h904668, - data_addrBits__h1013599, - data_addrBits__h1014453, - pc_addrBits__h992212, - r1__read_BITS_13_TO_0___h918542, - repBoundBits__h242584, - res_addrBits__h126792, - res_addrBits__h139704, - res_addrBits__h178867, - res_addrBits__h197632, - res_addrBits__h216391, - res_addrBits__h235268, - res_addrBits__h567274, - res_addrBits__h568126, - res_addrBits__h613883, - res_addrBits__h659630, - res_addrBits__h705439, - res_addrBits__h706299, - res_addrBits__h848498, - res_addrBits__h890899, - toBoundsM1__h242588, - toBounds__h242587, - x1_avValue_new_pcc_capFat_bounds_baseBits__h998359, - x__h127470, - x__h127490, - x__h140386, - x__h140406, - x__h183647, - x__h183667, - x__h202398, - x__h202418, - x__h216964, - x__h216984, - x__h865885, - x__h865905, - x__h866433, - x__h866453, - x__h904507, - x__h904527, - x__h905055, - x__h905075, - x__h992581, - x__h992601, - x__h998356; + cr_addrBits__h865495, + cr_addrBits__h866043, + cr_addrBits__h904116, + cr_addrBits__h904664, + data_addrBits__h1013593, + data_addrBits__h1014447, + pc_addrBits__h992207, + r1__read_BITS_13_TO_0___h918537, + repBoundBits__h242583, + res_addrBits__h126791, + res_addrBits__h139703, + res_addrBits__h178866, + res_addrBits__h197631, + res_addrBits__h216390, + res_addrBits__h235267, + res_addrBits__h567270, + res_addrBits__h568123, + res_addrBits__h613880, + res_addrBits__h659627, + res_addrBits__h705436, + res_addrBits__h706296, + res_addrBits__h848495, + res_addrBits__h890895, + toBoundsM1__h242587, + toBounds__h242586, + x1_avValue_new_pcc_capFat_bounds_baseBits__h998354, + x__h127469, + x__h127489, + x__h140385, + x__h140405, + x__h183646, + x__h183666, + x__h202397, + x__h202417, + x__h216963, + x__h216983, + x__h865882, + x__h865902, + x__h866430, + x__h866450, + x__h904503, + x__h904523, + x__h905051, + x__h905071, + x__h992576, + x__h992596, + x__h998351; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4739, IF_NOT_renameStage_rg_m_halt_req_0076_BIT_4_00_ETC___d20769, IF_NOT_renameStage_rg_m_halt_req_0076_BIT_4_00_ETC___d20770, @@ -5157,45 +5157,45 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659, - b_top__h127496, - b_top__h140412, - b_top__h183673, - b_top__h202424, - b_top__h216990, - b_top__h865911, - b_top__h866459, - b_top__h904533, - b_top__h905081, - b_top__h992607, + b_top__h127495, + b_top__h140411, + b_top__h183672, + b_top__h202423, + b_top__h216989, + b_top__h865908, + b_top__h866456, + b_top__h904529, + b_top__h905077, + b_top__h992602, capChecks___d4142, - renaming_spec_bits__h966287, - result__h913573, - result__h913624, - spec_bits__h971306, - topBits__h127399, - topBits__h140315, - topBits__h183576, - topBits__h202327, - topBits__h216893, - topBits__h865813, - topBits__h866361, - topBits__h904435, - topBits__h904983, - topBits__h992510, - w__h913568, - x__h594763, - x__h640512, - x__h686259, - x__h736295, - x__h775148, - x__h814452, - x__h913572, - x__h913623, - y__h913602, - y__h971319, - y_avValue_snd_fst__h960972, - y_avValue_snd_fst__h961014, - y_avValue_snd_fst__h961056; + renaming_spec_bits__h966282, + result__h913568, + result__h913619, + spec_bits__h971301, + topBits__h127398, + topBits__h140314, + topBits__h183575, + topBits__h202326, + topBits__h216892, + topBits__h865810, + topBits__h866358, + topBits__h904431, + topBits__h904979, + topBits__h992505, + w__h913563, + x__h594760, + x__h640509, + x__h686256, + x__h736292, + x__h775145, + x__h814449, + x__h913567, + x__h913618, + y__h913597, + y__h971314, + y_avValue_snd_fst__h960967, + y_avValue_snd_fst__h961009, + y_avValue_snd_fst__h961051; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899, @@ -5219,103 +5219,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q151, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q168, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q191, - _theResult___exp__h734868, - _theResult___exp__h744519, - _theResult___exp__h753303, - _theResult___exp__h773721, - _theResult___exp__h783372, - _theResult___exp__h792156, - _theResult___exp__h813025, - _theResult___exp__h822676, - _theResult___exp__h831460, - _theResult___fst_exp__h719140, - _theResult___fst_exp__h734204, + _theResult___exp__h734865, + _theResult___exp__h744516, + _theResult___exp__h753300, + _theResult___exp__h773718, + _theResult___exp__h783369, + _theResult___exp__h792153, + _theResult___exp__h813022, + _theResult___exp__h822673, + _theResult___exp__h831457, + _theResult___fst_exp__h719137, + _theResult___fst_exp__h734201, + _theResult___fst_exp__h734207, _theResult___fst_exp__h734210, - _theResult___fst_exp__h734213, + _theResult___fst_exp__h734965, _theResult___fst_exp__h734968, - _theResult___fst_exp__h734971, - _theResult___fst_exp__h743790, - _theResult___fst_exp__h743855, + _theResult___fst_exp__h743787, + _theResult___fst_exp__h743852, + _theResult___fst_exp__h743858, _theResult___fst_exp__h743861, - _theResult___fst_exp__h743864, + _theResult___fst_exp__h744616, _theResult___fst_exp__h744619, - _theResult___fst_exp__h744622, - _theResult___fst_exp__h752575, - _theResult___fst_exp__h752614, + _theResult___fst_exp__h752572, + _theResult___fst_exp__h752611, + _theResult___fst_exp__h752617, _theResult___fst_exp__h752620, - _theResult___fst_exp__h752623, + _theResult___fst_exp__h753400, _theResult___fst_exp__h753403, - _theResult___fst_exp__h753406, + _theResult___fst_exp__h753412, _theResult___fst_exp__h753415, - _theResult___fst_exp__h753418, - _theResult___fst_exp__h757993, - _theResult___fst_exp__h773057, + _theResult___fst_exp__h757990, + _theResult___fst_exp__h773054, + _theResult___fst_exp__h773060, _theResult___fst_exp__h773063, - _theResult___fst_exp__h773066, + _theResult___fst_exp__h773818, _theResult___fst_exp__h773821, - _theResult___fst_exp__h773824, - _theResult___fst_exp__h782643, - _theResult___fst_exp__h782708, + _theResult___fst_exp__h782640, + _theResult___fst_exp__h782705, + _theResult___fst_exp__h782711, _theResult___fst_exp__h782714, - _theResult___fst_exp__h782717, + _theResult___fst_exp__h783469, _theResult___fst_exp__h783472, - _theResult___fst_exp__h783475, - _theResult___fst_exp__h791428, - _theResult___fst_exp__h791467, + _theResult___fst_exp__h791425, + _theResult___fst_exp__h791464, + _theResult___fst_exp__h791470, _theResult___fst_exp__h791473, - _theResult___fst_exp__h791476, + _theResult___fst_exp__h792253, _theResult___fst_exp__h792256, - _theResult___fst_exp__h792259, + _theResult___fst_exp__h792265, _theResult___fst_exp__h792268, - _theResult___fst_exp__h792271, - _theResult___fst_exp__h797297, - _theResult___fst_exp__h812361, + _theResult___fst_exp__h797294, + _theResult___fst_exp__h812358, + _theResult___fst_exp__h812364, _theResult___fst_exp__h812367, - _theResult___fst_exp__h812370, + _theResult___fst_exp__h813122, _theResult___fst_exp__h813125, - _theResult___fst_exp__h813128, - _theResult___fst_exp__h821947, - _theResult___fst_exp__h822012, + _theResult___fst_exp__h821944, + _theResult___fst_exp__h822009, + _theResult___fst_exp__h822015, _theResult___fst_exp__h822018, - _theResult___fst_exp__h822021, + _theResult___fst_exp__h822773, _theResult___fst_exp__h822776, - _theResult___fst_exp__h822779, - _theResult___fst_exp__h830732, - _theResult___fst_exp__h830771, + _theResult___fst_exp__h830729, + _theResult___fst_exp__h830768, + _theResult___fst_exp__h830774, _theResult___fst_exp__h830777, - _theResult___fst_exp__h830780, + _theResult___fst_exp__h831557, _theResult___fst_exp__h831560, - _theResult___fst_exp__h831563, + _theResult___fst_exp__h831569, _theResult___fst_exp__h831572, - _theResult___fst_exp__h831575, - _theResult___snd_fst_exp__h734974, - _theResult___snd_fst_exp__h753409, - _theResult___snd_fst_exp__h773827, - _theResult___snd_fst_exp__h792262, - _theResult___snd_fst_exp__h813131, - _theResult___snd_fst_exp__h831566, + _theResult___snd_fst_exp__h734971, + _theResult___snd_fst_exp__h753406, + _theResult___snd_fst_exp__h773824, + _theResult___snd_fst_exp__h792259, + _theResult___snd_fst_exp__h813128, + _theResult___snd_fst_exp__h831563, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q47, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q117, - din_inc___2_exp__h753463, - din_inc___2_exp__h753498, - din_inc___2_exp__h753524, - din_inc___2_exp__h792316, - din_inc___2_exp__h792351, - din_inc___2_exp__h792377, - din_inc___2_exp__h831620, - din_inc___2_exp__h831655, - din_inc___2_exp__h831681, - out_exp__h734871, - out_exp__h744522, - out_exp__h753306, - out_exp__h773724, - out_exp__h783375, - out_exp__h792159, - out_exp__h813028, - out_exp__h822679, - out_exp__h831463, - x__h996333; + din_inc___2_exp__h753460, + din_inc___2_exp__h753495, + din_inc___2_exp__h753521, + din_inc___2_exp__h792313, + din_inc___2_exp__h792348, + din_inc___2_exp__h792374, + din_inc___2_exp__h831617, + din_inc___2_exp__h831652, + din_inc___2_exp__h831678, + out_exp__h734868, + out_exp__h744519, + out_exp__h753303, + out_exp__h773721, + out_exp__h783372, + out_exp__h792156, + out_exp__h813025, + out_exp__h822676, + out_exp__h831460, + x__h996328; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3623; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771, @@ -5371,128 +5371,128 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q88, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q53, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q123, - _theResult___exp__h585008, - _theResult___exp__h593590, - _theResult___exp__h602774, - _theResult___exp__h611410, - _theResult___exp__h611512, - _theResult___exp__h630757, - _theResult___exp__h639339, - _theResult___exp__h648523, - _theResult___exp__h657159, - _theResult___exp__h657261, - _theResult___exp__h676504, - _theResult___exp__h685086, - _theResult___exp__h694270, - _theResult___exp__h702906, - _theResult___exp__h703008, - _theResult___fst_exp__h584492, - _theResult___fst_exp__h584557, + _theResult___exp__h585005, + _theResult___exp__h593587, + _theResult___exp__h602771, + _theResult___exp__h611407, + _theResult___exp__h611509, + _theResult___exp__h630754, + _theResult___exp__h639336, + _theResult___exp__h648520, + _theResult___exp__h657156, + _theResult___exp__h657258, + _theResult___exp__h676501, + _theResult___exp__h685083, + _theResult___exp__h694267, + _theResult___exp__h702903, + _theResult___exp__h703005, + _theResult___fst_exp__h584489, + _theResult___fst_exp__h584554, + _theResult___fst_exp__h584560, _theResult___fst_exp__h584563, - _theResult___fst_exp__h584566, - _theResult___fst_exp__h585089, - _theResult___fst_exp__h593139, + _theResult___fst_exp__h585086, + _theResult___fst_exp__h593136, + _theResult___fst_exp__h593142, _theResult___fst_exp__h593145, - _theResult___fst_exp__h593148, - _theResult___fst_exp__h593671, - _theResult___fst_exp__h602258, - _theResult___fst_exp__h602323, + _theResult___fst_exp__h593668, + _theResult___fst_exp__h602255, + _theResult___fst_exp__h602320, + _theResult___fst_exp__h602326, _theResult___fst_exp__h602329, - _theResult___fst_exp__h602332, - _theResult___fst_exp__h602855, - _theResult___fst_exp__h610895, - _theResult___fst_exp__h610934, + _theResult___fst_exp__h602852, + _theResult___fst_exp__h610892, + _theResult___fst_exp__h610931, + _theResult___fst_exp__h610937, _theResult___fst_exp__h610940, - _theResult___fst_exp__h610943, - _theResult___fst_exp__h611491, + _theResult___fst_exp__h611488, + _theResult___fst_exp__h611497, _theResult___fst_exp__h611500, - _theResult___fst_exp__h611503, - _theResult___fst_exp__h630241, - _theResult___fst_exp__h630306, + _theResult___fst_exp__h630238, + _theResult___fst_exp__h630303, + _theResult___fst_exp__h630309, _theResult___fst_exp__h630312, - _theResult___fst_exp__h630315, - _theResult___fst_exp__h630838, - _theResult___fst_exp__h638888, + _theResult___fst_exp__h630835, + _theResult___fst_exp__h638885, + _theResult___fst_exp__h638891, _theResult___fst_exp__h638894, - _theResult___fst_exp__h638897, - _theResult___fst_exp__h639420, - _theResult___fst_exp__h648007, - _theResult___fst_exp__h648072, + _theResult___fst_exp__h639417, + _theResult___fst_exp__h648004, + _theResult___fst_exp__h648069, + _theResult___fst_exp__h648075, _theResult___fst_exp__h648078, - _theResult___fst_exp__h648081, - _theResult___fst_exp__h648604, - _theResult___fst_exp__h656644, - _theResult___fst_exp__h656683, + _theResult___fst_exp__h648601, + _theResult___fst_exp__h656641, + _theResult___fst_exp__h656680, + _theResult___fst_exp__h656686, _theResult___fst_exp__h656689, - _theResult___fst_exp__h656692, - _theResult___fst_exp__h657240, + _theResult___fst_exp__h657237, + _theResult___fst_exp__h657246, _theResult___fst_exp__h657249, - _theResult___fst_exp__h657252, - _theResult___fst_exp__h675988, - _theResult___fst_exp__h676053, + _theResult___fst_exp__h675985, + _theResult___fst_exp__h676050, + _theResult___fst_exp__h676056, _theResult___fst_exp__h676059, - _theResult___fst_exp__h676062, - _theResult___fst_exp__h676585, - _theResult___fst_exp__h684635, + _theResult___fst_exp__h676582, + _theResult___fst_exp__h684632, + _theResult___fst_exp__h684638, _theResult___fst_exp__h684641, - _theResult___fst_exp__h684644, - _theResult___fst_exp__h685167, - _theResult___fst_exp__h693754, - _theResult___fst_exp__h693819, + _theResult___fst_exp__h685164, + _theResult___fst_exp__h693751, + _theResult___fst_exp__h693816, + _theResult___fst_exp__h693822, _theResult___fst_exp__h693825, - _theResult___fst_exp__h693828, - _theResult___fst_exp__h694351, - _theResult___fst_exp__h702391, - _theResult___fst_exp__h702430, + _theResult___fst_exp__h694348, + _theResult___fst_exp__h702388, + _theResult___fst_exp__h702427, + _theResult___fst_exp__h702433, _theResult___fst_exp__h702436, - _theResult___fst_exp__h702439, - _theResult___fst_exp__h702987, + _theResult___fst_exp__h702984, + _theResult___fst_exp__h702993, _theResult___fst_exp__h702996, - _theResult___fst_exp__h702999, - _theResult___snd_fst_exp__h593674, - _theResult___snd_fst_exp__h611494, - _theResult___snd_fst_exp__h639423, - _theResult___snd_fst_exp__h657243, - _theResult___snd_fst_exp__h685170, - _theResult___snd_fst_exp__h702990, - din_inc___2_exp__h611525, - din_inc___2_exp__h611549, - din_inc___2_exp__h611579, - din_inc___2_exp__h611603, - din_inc___2_exp__h657274, - din_inc___2_exp__h657298, - din_inc___2_exp__h657328, - din_inc___2_exp__h657352, - din_inc___2_exp__h703021, - din_inc___2_exp__h703045, - din_inc___2_exp__h703075, - din_inc___2_exp__h703099, - f1_exp14825_MINUS_127__q147, - f1_exp__h714825, - f2_exp53819_MINUS_127__q187, - f2_exp__h753819, - f3_exp93123_MINUS_127__q164, - f3_exp__h793123, - out_exp__h585011, - out_exp__h593593, - out_exp__h602777, - out_exp__h611413, - out_exp__h630760, - out_exp__h639342, - out_exp__h648526, - out_exp__h657162, - out_exp__h676507, - out_exp__h685089, - out_exp__h694273, - out_exp__h702909, - out_f_exp__h611789, - out_f_exp__h657538, - out_f_exp__h703285, - x__h852690; + _theResult___snd_fst_exp__h593671, + _theResult___snd_fst_exp__h611491, + _theResult___snd_fst_exp__h639420, + _theResult___snd_fst_exp__h657240, + _theResult___snd_fst_exp__h685167, + _theResult___snd_fst_exp__h702987, + din_inc___2_exp__h611522, + din_inc___2_exp__h611546, + din_inc___2_exp__h611576, + din_inc___2_exp__h611600, + din_inc___2_exp__h657271, + din_inc___2_exp__h657295, + din_inc___2_exp__h657325, + din_inc___2_exp__h657349, + din_inc___2_exp__h703018, + din_inc___2_exp__h703042, + din_inc___2_exp__h703072, + din_inc___2_exp__h703096, + f1_exp14822_MINUS_127__q147, + f1_exp__h714822, + f2_exp53816_MINUS_127__q187, + f2_exp__h753816, + f3_exp93120_MINUS_127__q164, + f3_exp__h793120, + out_exp__h585008, + out_exp__h593590, + out_exp__h602774, + out_exp__h611410, + out_exp__h630757, + out_exp__h639339, + out_exp__h648523, + out_exp__h657159, + out_exp__h676504, + out_exp__h685086, + out_exp__h694270, + out_exp__h702906, + out_f_exp__h611786, + out_f_exp__h657535, + out_f_exp__h703282, + x__h852687; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8202_BI_ETC___d19240, NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17161, - x__h244610, - x__h997059; + x__h244608, + x__h997054; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749, @@ -5519,19 +5519,19 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d23934, fetchStage_pipelines_0_first__0049_BIT_167_037_ETC___d20398, fetchStage_pipelines_1_first__0058_BIT_167_132_ETC___d21348, - x__h127310, - x__h140226, - x__h183487, - x__h202238, - x__h216804, - x__h865712, - x__h866260, - x__h904334, - x__h904882, - x__h992421, - x__h997033, - x__h997690, - x__h998377; + x__h127309, + x__h140225, + x__h183486, + x__h202237, + x__h216803, + x__h865709, + x__h866257, + x__h904330, + x__h904878, + x__h992416, + x__h997028, + x__h997685, + x__h998372; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__9739_B_ETC___d19883, IF_IF_coreFix_aluExe_0_exeToFinQ_first__9739_B_ETC___d19884, IF_IF_coreFix_aluExe_1_exeToFinQ_first__7660_B_ETC___d17805, @@ -5574,51 +5574,51 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291, - cause_code__h994330, + cause_code__h994325, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138, - fflags__h1011197, - r1__read__h854478, - res_fflags__h568166, - res_fflags__h613920, - res_fflags__h659667, + fflags__h1011192, + r1__read__h854475, + res_fflags__h568163, + res_fflags__h613917, + res_fflags__h659664, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18985, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16601, - x__h148960, - x__h152094, - x__h249407, - x__h249419, - x__h249431, - x__h249443, - x__h249455, - x__h249467, - x__h249479, - x__h249491, - x__h249503, - x__h249515, - x__h249527, - x__h249539, - x__h249551, - x__h249563, - x__h249575, - y__h249408, - y__h249420, - y__h249432, - y__h249444, - y__h249456, - y__h249468, - y__h249480, - y__h249492, - y__h249504, - y__h249516, - y__h249528, - y__h249540, - y__h249552, - y__h249564, - y__h249576, - y_avValue_snd_fst__h1010675, - y_avValue_snd_fst__h1011257, - y_avValue_snd_fst__h1011286; + x__h148959, + x__h152093, + x__h249405, + x__h249417, + x__h249429, + x__h249441, + x__h249453, + x__h249465, + x__h249477, + x__h249489, + x__h249501, + x__h249513, + x__h249525, + x__h249537, + x__h249549, + x__h249561, + x__h249573, + y__h249406, + y__h249418, + y__h249430, + y__h249442, + y__h249454, + y__h249466, + y__h249478, + y__h249490, + y__h249502, + y__h249514, + y__h249526, + y__h249538, + y__h249550, + y__h249562, + y__h249574, + y_avValue_snd_fst__h1010670, + y_avValue_snd_fst__h1011252, + y_avValue_snd_fst__h1011281; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8202__ETC___d19237, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5590__ETC___d17158, IF_IF_renameStage_rg_m_halt_req_0076_BIT_4_007_ETC___d20759, @@ -5663,7 +5663,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3378, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3421, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3620, - vm_mode_reg__read__h853854; + vm_mode_reg__read__h853851; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18892, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18893, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16508, @@ -5680,54 +5680,54 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3577, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7078, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23867, - _theResult_____2__h515296, - dcsr_cause__h991836, - next_deqP___1__h515541, - repBound__h237262, - repBound__h238947, - repBound__h248150, - repBound__h248675, - repBound__h856058, - repBound__h859402, - repBound__h859420, - repBound__h865966, - repBound__h866514, - repBound__h896085, - repBound__h898412, - repBound__h898430, - repBound__h904588, - repBound__h905136, - repBound__h995071, - repBound__h997124, - repBound__h997781, - tb__h865963, - tb__h866511, - tb__h904585, - tb__h905133, - tmp_expBotHalf__h127265, - tmp_expBotHalf__h140181, - tmp_expBotHalf__h183442, - tmp_expBotHalf__h202193, - tmp_expBotHalf__h216759, - tmp_expBotHalf__h865666, - tmp_expBotHalf__h866214, - tmp_expBotHalf__h904288, - tmp_expBotHalf__h904836, - tmp_expBotHalf__h992376, - tmp_expTopHalf__h127263, - tmp_expTopHalf__h140179, - tmp_expTopHalf__h183440, - tmp_expTopHalf__h202191, - tmp_expTopHalf__h216757, - tmp_expTopHalf__h865664, - tmp_expTopHalf__h866212, - tmp_expTopHalf__h904286, - tmp_expTopHalf__h904834, - tmp_expTopHalf__h992374, - v__h514752, - v__h514947, - x__h521603, - x_decodeInfo_frm__h923974; + _theResult_____2__h515292, + dcsr_cause__h991831, + next_deqP___1__h515537, + repBound__h237261, + repBound__h238946, + repBound__h248148, + repBound__h248673, + repBound__h856055, + repBound__h859399, + repBound__h859417, + repBound__h865963, + repBound__h866511, + repBound__h896081, + repBound__h898408, + repBound__h898426, + repBound__h904584, + repBound__h905132, + repBound__h995066, + repBound__h997119, + repBound__h997776, + tb__h865960, + tb__h866508, + tb__h904581, + tb__h905129, + tmp_expBotHalf__h127264, + tmp_expBotHalf__h140180, + tmp_expBotHalf__h183441, + tmp_expBotHalf__h202192, + tmp_expBotHalf__h216758, + tmp_expBotHalf__h865663, + tmp_expBotHalf__h866211, + tmp_expBotHalf__h904284, + tmp_expBotHalf__h904832, + tmp_expBotHalf__h992371, + tmp_expTopHalf__h127262, + tmp_expTopHalf__h140178, + tmp_expTopHalf__h183439, + tmp_expTopHalf__h202190, + tmp_expTopHalf__h216756, + tmp_expTopHalf__h865661, + tmp_expTopHalf__h866209, + tmp_expTopHalf__h904282, + tmp_expTopHalf__h904830, + tmp_expTopHalf__h992369, + v__h514748, + v__h514943, + x__h521599, + x_decodeInfo_frm__h923969; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18833, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18834, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16449, @@ -5743,108 +5743,108 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16454, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3257, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3539, - IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50, - IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167, - IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75, - IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150, - IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85, - IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110, - IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190, - IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40, - IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120, - IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125, - IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55, - IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163, - IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170, - IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146, - IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77, - IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153, - IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90, - IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186, - IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112, - IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193, - IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42, - carry_out__h127401, - carry_out__h140317, - carry_out__h183578, - carry_out__h202329, - carry_out__h216895, - carry_out__h865815, - carry_out__h866363, - carry_out__h904437, - carry_out__h904985, - carry_out__h992512, + IF_sfdin02249_BIT_33_THEN_2_ELSE_0__q50, + IF_sfdin21938_BIT_4_THEN_2_ELSE_0__q167, + IF_sfdin30232_BIT_33_THEN_2_ELSE_0__q75, + IF_sfdin43781_BIT_4_THEN_2_ELSE_0__q150, + IF_sfdin47998_BIT_33_THEN_2_ELSE_0__q85, + IF_sfdin75979_BIT_33_THEN_2_ELSE_0__q110, + IF_sfdin82634_BIT_4_THEN_2_ELSE_0__q190, + IF_sfdin84483_BIT_33_THEN_2_ELSE_0__q40, + IF_sfdin93745_BIT_33_THEN_2_ELSE_0__q120, + IF_theResult___snd02382_BIT_33_THEN_2_ELSE_0__q125, + IF_theResult___snd10886_BIT_33_THEN_2_ELSE_0__q55, + IF_theResult___snd12318_BIT_4_THEN_2_ELSE_0__q163, + IF_theResult___snd30723_BIT_4_THEN_2_ELSE_0__q170, + IF_theResult___snd34161_BIT_4_THEN_2_ELSE_0__q146, + IF_theResult___snd38845_BIT_33_THEN_2_ELSE_0__q77, + IF_theResult___snd52566_BIT_4_THEN_2_ELSE_0__q153, + IF_theResult___snd56635_BIT_33_THEN_2_ELSE_0__q90, + IF_theResult___snd73014_BIT_4_THEN_2_ELSE_0__q186, + IF_theResult___snd84592_BIT_33_THEN_2_ELSE_0__q112, + IF_theResult___snd91419_BIT_4_THEN_2_ELSE_0__q193, + IF_theResult___snd93096_BIT_33_THEN_2_ELSE_0__q42, + carry_out__h127400, + carry_out__h140316, + carry_out__h183577, + carry_out__h202328, + carry_out__h216894, + carry_out__h865812, + carry_out__h866360, + carry_out__h904433, + carry_out__h904981, + carry_out__h992507, coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, coreFix_memExe_regToExeQfirst_BITS_222_TO_221__q2, coreFix_memExe_regToExeQfirst_BITS_59_TO_58__q4, - cr_reserved__h865501, - cr_reserved__h866049, - cr_reserved__h904123, - cr_reserved__h904671, - guard__h576391, - guard__h585100, - guard__h594030, - guard__h602866, - guard__h622142, - guard__h630849, - guard__h639779, - guard__h648615, - guard__h667889, - guard__h676596, - guard__h685526, - guard__h694362, - guard__h726252, - guard__h735564, - guard__h744633, - guard__h765105, - guard__h774417, - guard__h783486, - guard__h804409, - guard__h813721, - guard__h822790, - impliedTopBits__h127403, - impliedTopBits__h140319, - impliedTopBits__h183580, - impliedTopBits__h202331, - impliedTopBits__h216897, - impliedTopBits__h865817, - impliedTopBits__h866365, - impliedTopBits__h904439, - impliedTopBits__h904987, - impliedTopBits__h992514, - len_correction__h127402, - len_correction__h140318, - len_correction__h183579, - len_correction__h202330, - len_correction__h216896, - len_correction__h865816, - len_correction__h866364, - len_correction__h904438, - len_correction__h904986, - len_correction__h992513, - prv__h1012290, - prv__h1012334, - r1__read_BITS_13_TO_12___h924176, - sbIdx__h151985, - v__h836568, - v__h836578, - v__h837213, - wordIdx__h263159, - x__h1007669, - x__h1011445, - x__h127487, - x__h140403, - x__h183664, - x__h202415, - x__h216981, - x__h865902, - x__h866450, - x__h904524, - x__h905072, - x__h992598, - y_avValue_snd_snd_snd_fst__h1010685, - y_avValue_snd_snd_snd_fst__h1011267, - y_avValue_snd_snd_snd_fst__h1011296; + cr_reserved__h865498, + cr_reserved__h866046, + cr_reserved__h904119, + cr_reserved__h904667, + guard__h576388, + guard__h585097, + guard__h594027, + guard__h602863, + guard__h622139, + guard__h630846, + guard__h639776, + guard__h648612, + guard__h667886, + guard__h676593, + guard__h685523, + guard__h694359, + guard__h726249, + guard__h735561, + guard__h744630, + guard__h765102, + guard__h774414, + guard__h783483, + guard__h804406, + guard__h813718, + guard__h822787, + impliedTopBits__h127402, + impliedTopBits__h140318, + impliedTopBits__h183579, + impliedTopBits__h202330, + impliedTopBits__h216896, + impliedTopBits__h865814, + impliedTopBits__h866362, + impliedTopBits__h904435, + impliedTopBits__h904983, + impliedTopBits__h992509, + len_correction__h127401, + len_correction__h140317, + len_correction__h183578, + len_correction__h202329, + len_correction__h216895, + len_correction__h865813, + len_correction__h866361, + len_correction__h904434, + len_correction__h904982, + len_correction__h992508, + prv__h1012285, + prv__h1012329, + r1__read_BITS_13_TO_12___h924171, + sbIdx__h151984, + v__h836565, + v__h836575, + v__h837210, + wordIdx__h263157, + x__h1007664, + x__h1011440, + x__h127486, + x__h140402, + x__h183663, + x__h202414, + x__h216980, + x__h865899, + x__h866447, + x__h904520, + x__h905068, + x__h992593, + y_avValue_snd_snd_snd_fst__h1010680, + y_avValue_snd_snd_snd_fst__h1011262, + y_avValue_snd_snd_snd_fst__h1011291; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10571, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10621, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11968, @@ -6561,12 +6561,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h526073, - _theResult_____2__h533166, - _theResult_____2__h543801, - _theResult_____2__h557634, - _theResult_____2__h561413, - cause_interrupt__h992790, + _theResult_____2__h526069, + _theResult_____2__h533162, + _theResult_____2__h543797, + _theResult_____2__h557630, + _theResult_____2__h561409, + cause_interrupt__h992785, commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22272, commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22279, commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22384, @@ -6950,10 +6950,10 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095, coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d22810, - cr_flags__h865500, - cr_flags__h866048, - cr_flags__h904122, - cr_flags__h904670, + cr_flags__h865497, + cr_flags__h866045, + cr_flags__h904118, + cr_flags__h904666, csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128, @@ -6996,27 +6996,27 @@ module mkCore(CLK, fetchStage_pipelines_1_first__0058_BITS_267_TO_ETC___d21659, fetchStage_pipelines_1_first__0058_BITS_267_TO_ETC___d21945, fetchStage_pipelines_1_first__0058_BITS_272_TO_ETC___d21670, - guard__h594628, - guard__h640377, - guard__h686124, - guard__h736162, - guard__h775015, - guard__h814319, - idx__h966426, - k__h942684, + guard__h594625, + guard__h640374, + guard__h686121, + guard__h736159, + guard__h775012, + guard__h814316, + idx__h966421, + k__h942679, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20461, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20853, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20873, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21779, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21781, - next_deqP___1__h526318, - next_deqP___1__h533596, - next_deqP___1__h544231, - next_deqP___1__h557879, - next_deqP___1__h561658, - r1__read_BIT_20___h924682, - r__h852737, - r__h854224, + next_deqP___1__h526314, + next_deqP___1__h533592, + next_deqP___1__h544227, + next_deqP___1__h557875, + next_deqP___1__h561654, + r1__read_BIT_20___h924677, + r__h852734, + r__h854221, regRenamingTable_RDY_rename_0_getRename__0810__ETC___d20821, regRenamingTable_RDY_rename_0_getRename__0810__ETC___d21625, regRenamingTable_rename_0_canRename__0933_AND__ETC___d20962, @@ -7060,20 +7060,20 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12424, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12425, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2762, - v__h516772, - v__h517152, - v__h532491, - v__h532686, - v__h534940, - v__h535135, - v__h555960, - v__h556155, - v__h559739, - v__h559934, - x__h240082, - x__h241239, - x__h254848, - x__h836069; + v__h516768, + v__h517148, + v__h532487, + v__h532682, + v__h534936, + v__h535131, + v__h555956, + v__h556151, + v__h559735, + v__h559930, + x__h240081, + x__h241238, + x__h254846, + x__h836066; // action method coreReq_start assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; @@ -11105,7 +11105,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; assign MUX_rg_core_run_state$write_1__SEL_4 = WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -11133,15 +11133,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h987208, + addr__h987203, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323, rob$deqPort_0_deq_data[501:470] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1011220 ; + commitStage_rg_serial_num + y__h1011215 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h942684 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h942679 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786) ? { fetchStage$pipelines_0_first[272:268], IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d20175, @@ -11159,7 +11159,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11267,7 +11267,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h501025 } ; + x__h501022 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7018 } ; @@ -11277,7 +11277,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h505543, + addr__h505540, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7126 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11294,12 +11294,12 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : coreFix_memExe_reqLrScAmoQ_data_0_rl ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h148960, - addr__h148408, + { x__h148959, + addr__h148407, 158'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h152094, - addr__h151984, + { x__h152093, + addr__h151983, 158'h32AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 = { 1'd1, @@ -11309,7 +11309,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h509039, + resp_addr__h509036, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11317,8 +11317,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1012334, - prv__h1012334 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1012329, + prv__h1012329 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11387,39 +11387,39 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h912383, - new_pc__h909836, + { x__h912378, + new_pc__h909831, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h912383, - new_pc__h909836, + { x__h912378, + new_pc__h909831, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h878730, - new_pc__h871752, + { x__h878726, + new_pc__h871748, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h878730, - new_pc__h871752, + { x__h878726, + new_pc__h871748, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1011197 ; + csrf_fflags_reg | fflags__h1011192 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__2032_BIT_288_2701_T_ETC___d22795 == 6'd1) ? @@ -11468,9 +11468,9 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1008993 + 64'd1 ; + n__read__h1008988 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1008993 + { 62'd0, x__h1011445 } ; + n__read__h1008988 + { 62'd0, x__h1011440 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2032_BIT_288_2701_T_ETC___d22795 == @@ -11478,11 +11478,11 @@ module mkCore(CLK, MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h994512 or trap_val__h994359) + always@(commitStage_commitTrap or trap_val__h994507 or trap_val__h994354) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994512; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994359; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994507; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994354; default: MUX_csrf_mtval_csr$write_1__VAL_2 = 64'd0; endcase end @@ -11504,7 +11504,7 @@ module mkCore(CLK, 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1007669 : + x__h1007664 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? @@ -11513,29 +11513,29 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h991836, + dcsr_cause__h991831, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = { csrf_rg_dpc[152], - pointer__h1005920, - x__h1005944[13:0], + pointer__h1005915, + x__h1005939[13:0], csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = { commitStage_commitTrap[237], - pc_address__h992211, - pc_addrBits__h992212, + pc_address__h992206, + pc_addrBits__h992207, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351, - x__h992581, - x__h992601 } ; + x__h992576, + x__h992596 } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { csrf_rg_dpc[152], - pointer__h1025233, - x__h1025256[13:0], + pointer__h1025227, + x__h1025250[13:0], csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = @@ -11546,7 +11546,7 @@ module mkCore(CLK, 6'd19) && MUX_csrf_rg_tselect$write_1__VAL_2[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1014871 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1014865 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11562,14 +11562,14 @@ module mkCore(CLK, IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677[14:3], ~IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677[2], IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677[1:0], - thin_address__h996854 } ; + thin_address__h996849 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1007609 or v__h1007648 or v__h1008101) + next_pc__h1007604 or v__h1007643 or v__h1008096) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1007648; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1008101; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1007609; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1007643; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1008096; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1007604; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11616,38 +11616,38 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h567273, - res_addrBits__h567274, + res_address__h567269, + res_addrBits__h567270, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, - res_address__h568125, - res_addrBits__h568126, + res_address__h568122, + res_addrBits__h568123, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_3 = { 1'd0, - res_address__h613882, - res_addrBits__h613883, + res_address__h613879, + res_addrBits__h613880, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_4 = { 1'd0, - res_address__h659629, - res_addrBits__h659630, + res_address__h659626, + res_addrBits__h659627, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_5 = { 1'd0, - res_address__h705438, - res_addrBits__h705439, + res_address__h705435, + res_addrBits__h705436, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_6 = { 1'd0, - res_address__h706298, - res_addrBits__h706299, + res_address__h706295, + res_addrBits__h706296, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_3_wr_2__VAL_1 = { coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h126791, - res_addrBits__h126792, + res_address__h126790, + res_addrBits__h126791, coreFix_memExe_respLrScAmoQ_data_0[127:112], coreFix_memExe_respLrScAmoQ_data_0[109], coreFix_memExe_respLrScAmoQ_data_0[111:110], @@ -11655,8 +11655,8 @@ module mkCore(CLK, IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 } ; assign MUX_rf$write_3_wr_2__VAL_2 = { mmio_dataRespQ_data_0[128], - res_address__h139703, - res_addrBits__h139704, + res_address__h139702, + res_addrBits__h139703, mmio_dataRespQ_data_0[127:112], mmio_dataRespQ_data_0[109], mmio_dataRespQ_data_0[111:110], @@ -11665,27 +11665,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h178866, - res_addrBits__h178867, - x__h183367[127:112], - x__h183367[109], - x__h183367[111:110], - ~x__h183367[108:90], + res_address__h178865, + res_addrBits__h178866, + x__h183366[127:112], + x__h183366[109], + x__h183366[111:110], + ~x__h183366[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h197631, - res_addrBits__h197632, - x__h199219[127:112], - x__h199219[109], - x__h199219[111:110], - ~x__h199219[108:90], + res_address__h197630, + res_addrBits__h197631, + x__h199218[127:112], + x__h199218[109], + x__h199218[111:110], + ~x__h199218[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h216390, - res_addrBits__h216391, + res_address__h216389, + res_addrBits__h216390, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -11693,13 +11693,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1013598, - data_addrBits__h1013599, + data_address__h1013592, + data_addrBits__h1013593, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1014452, - data_addrBits__h1014453, + data_address__h1014446, + data_addrBits__h1014447, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[590:462], @@ -11752,24 +11752,24 @@ module mkCore(CLK, fetchStage$pipelines_0_first[76:70], 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, fetchStage_pipelines_0_first__0049_BIT_167_037_ETC___d20927 } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h568166 ; + res_fflags__h568163 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h613920 ; + res_fflags__h613917 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h659667 ; + res_fflags__h659664 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12177,8 +12177,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h837213 : - v__h836568 ; + v__h837210 : + v__h836565 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -12276,7 +12276,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h515296 ; + _theResult_____2__h515292 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12295,7 +12295,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h514752 ; + v__h514748 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12337,7 +12337,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h526073 ; + _theResult_____2__h526069 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12356,7 +12356,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h516772 ; + v__h516768 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12453,7 +12453,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h533166 ; + _theResult_____2__h533162 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12469,7 +12469,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h532491 ; + v__h532487 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12489,7 +12489,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h535302, + { x_addr__h535298, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12516,7 +12516,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h543801 ; + _theResult_____2__h543797 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12535,7 +12535,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h534940 ; + v__h534936 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12611,7 +12611,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h561413 ; + _theResult_____2__h561409 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12626,7 +12626,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h559739 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h559735 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12667,7 +12667,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h557634 ; + _theResult_____2__h557630 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12682,7 +12682,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h555960 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h555956 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13042,13 +13042,13 @@ module mkCore(CLK, always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h992792 or + cause_code__h992787 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h992792; + csrf_mcause_code_reg$D_IN = cause_code__h992787; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; @@ -13068,14 +13068,14 @@ module mkCore(CLK, always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_interrupt__h992790 or + cause_interrupt__h992785 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[63]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h992790; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h992785; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; @@ -13251,7 +13251,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3035 : - n__read__h1008993 ; + n__read__h1008988 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13602,13 +13602,13 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h992792 or + cause_code__h992787 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h992792; + csrf_scause_code_reg$D_IN = cause_code__h992787; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; @@ -13628,14 +13628,14 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_interrupt__h992790 or + cause_interrupt__h992785 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[63]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h992790; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h992785; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; @@ -14802,7 +14802,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h942684 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h942679 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786) ? { fetchStage$pipelines_0_first[272:268], IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d20175, @@ -14820,7 +14820,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15299,19 +15299,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h836055 : - a__h835633 ; + _theResult___fst__h836052 : + a__h835630 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h835634 == 64'd0, - a__h835633, + { b__h835631 == 64'd0, + a__h835630, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h836069, - a__h835633[63], + x__h836066, + a__h835630[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h836056 : - b__h835634 ; + _theResult___snd__h836053 : + b__h835631 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && @@ -15372,20 +15372,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835633 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835634 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835630 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835631 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h835633 ; + a__h835630 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h835634 ; + b__h835631 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h835633 ; + a__h835630 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h835634 ; + b__h835631 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -15414,9 +15414,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q366, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h714355, - x__h714356, - x__h714357, + x__h714352, + x__h714353, + x__h714354, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19990 ; @@ -15468,7 +15468,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0058_BITS_267_ETC___d21125, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15622,7 +15622,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h501025 ; + x__h501022 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0) ? @@ -16054,7 +16054,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__0933_AND__ETC___d21830) ? specTagManager$currentSpecBits : - renaming_spec_bits__h966287 ; + renaming_spec_bits__h966282 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__0933_AND__ETC___d21839) ? @@ -16074,7 +16074,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__0933_AND__ETC___d21839) ? specTagManager$currentSpecBits : - renaming_spec_bits__h966287 ; + renaming_spec_bits__h966282 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16103,8 +16103,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h212809 : - t__h215095 ; + t__h212808 : + t__h215094 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16157,7 +16157,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[2], IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[1:0], coreFix_memExe_regToExeQ$first[217:154] } : - { pointer__h242569[3:0] == 4'd0 && + { pointer__h242568[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16327,7 +16327,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[238], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16740,9 +16740,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h871752 or + new_pc__h871748 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h909836 or + new_pc__h909831 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -16753,9 +16753,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h871752; + fetchStage$redirect_pc = new_pc__h871748; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h909836; + fetchStage$redirect_pc = new_pc__h909831; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -16945,7 +16945,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h966287 ; + renaming_spec_bits__h966282 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17222,7 +17222,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0058_BITS_264_ETC___d21959, IF_NOT_fetchStage_pipelines_1_first__0058_BITS_ETC___d22013, 7'd32, - renaming_spec_bits__h966287 } ; + renaming_spec_bits__h966282 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17232,24 +17232,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 14'd2730; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 14'd11589; @@ -17306,29 +17306,29 @@ module mkCore(CLK, always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or - data__h567607 or + data__h567604 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or - data__h613367 or + data__h613364 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or - data__h659114 or + data__h659111 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or - data__h704928 or - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705791) + data__h704925 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705788) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567607; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567604; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613367; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613364; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659114; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659111; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h704928; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h704925; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705791; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705788; default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -17497,16 +17497,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -17785,11 +17785,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h854224 }), + .amoExec_current({ 128'd0, r__h854221 }), .amoExec_inpt({ 97'd0, x__h65608 }), .amoExec(amoExec___d773)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h263159), + .amoExec_wordIdx(wordIdx__h263157), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 } }), @@ -17806,12 +17806,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h923974, - r1__read_BITS_13_TO_12___h924176 != + .checkForException_csrState({ x_decodeInfo_frm__h923969, + r1__read_BITS_13_TO_12___h924171 != 2'd0, - { prv__h1012290, + { prv__h1012285, csrf_tvm_reg, - { r1__read_BIT_20___h924682, + { r1__read_BIT_20___h924677, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17837,12 +17837,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h923974, - r1__read_BITS_13_TO_12___h924176 != + .checkForException_csrState({ x_decodeInfo_frm__h923969, + r1__read_BITS_13_TO_12___h924171 != 2'd0, - { prv__h1012290, + { prv__h1012285, csrf_tvm_reg, - { r1__read_BIT_20___h924682, + { r1__read_BIT_20___h924677, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17853,14 +17853,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h960829), + .checkForException_pcc(pc__h960824), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21375)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[383:221]), .capChecks_b(coreFix_memExe_regToExeQ$first[220:58]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h248675, + repBound__h248673, { csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 } }), @@ -17871,20 +17871,20 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[220:58]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h248675, + repBound__h248673, { csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h242768), - .prepareBoundsCheck_size(x__h249407 + - y__h249408), + .prepareBoundsCheck_vaddr(tmpAddr__h242767), + .prepareBoundsCheck_size(x__h249405 + + y__h249406), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[57:12]), .prepareBoundsCheck(prepareBoundsCheck___d4226)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q278, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h714446), - .execFpuSimple_rVal2(rVal2__h714447), + .execFpuSimple_rVal1(rVal1__h714443), + .execFpuSimple_rVal2(rVal2__h714444), .execFpuSimple(execFpuSimple___d15189)); module_basicExec instance_basicExec_8(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[821:817], CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280, @@ -17897,24 +17897,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h865497, - cr_addrBits__h865498, + { cr_address__h865494, + cr_addrBits__h865495, { coreFix_aluExe_1_regToExeQ$first[305:290], - { cr_flags__h865500, - cr_reserved__h865501 }, + { cr_flags__h865497, + cr_reserved__h865498 }, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17485 } }, - repBound__h865966, + repBound__h865963, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17492, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17493, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17505 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h866045, - cr_addrBits__h866046, + { cr_address__h866042, + cr_addrBits__h866043, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h866048, - cr_reserved__h866049 }, + { cr_flags__h866045, + cr_reserved__h866046 }, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17549 } }, - repBound__h866514, + repBound__h866511, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17556, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17557, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17569 } }), @@ -17931,24 +17931,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h904119, - cr_addrBits__h904120, + { cr_address__h904115, + cr_addrBits__h904116, { coreFix_aluExe_0_regToExeQ$first[305:290], - { cr_flags__h904122, - cr_reserved__h904123 }, + { cr_flags__h904118, + cr_reserved__h904119 }, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19564 } }, - repBound__h904588, + repBound__h904584, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19571, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19572, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19584 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h904667, - cr_addrBits__h904668, + { cr_address__h904663, + cr_addrBits__h904664, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h904670, - cr_reserved__h904671 }, + { cr_flags__h904666, + cr_reserved__h904667 }, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19628 } }, - repBound__h905136, + repBound__h905132, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19635, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19636, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19648 } }), @@ -17956,1191 +17956,1191 @@ module mkCore(CLK, .basicExec(basicExec___d19652)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148 ? - _theResult___snd__h676051 : - _theResult____h667879 ; + _theResult___snd__h676048 : + _theResult____h667876 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354 ? - _theResult___snd__h584555 : - _theResult____h576381 ; + _theResult___snd__h584552 : + _theResult____h576378 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751 ? - _theResult___snd__h630304 : - _theResult____h622132 ; + _theResult___snd__h630301 : + _theResult____h622129 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030 ? - _theResult___snd__h743853 : - _theResult____h735554 ; + _theResult___snd__h743850 : + _theResult____h735551 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745 ? - _theResult___snd__h822010 : - _theResult____h813711 ; + _theResult___snd__h822007 : + _theResult____h813708 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515 ? - _theResult___snd__h782706 : - _theResult____h774407 ; + _theResult___snd__h782703 : + _theResult____h774404 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q119 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699 ? - _theResult___snd__h693817 : - _theResult____h685516 ; + _theResult___snd__h693814 : + _theResult____h685513 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q49 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905 ? - _theResult___snd__h602321 : - _theResult____h594020 ; + _theResult___snd__h602318 : + _theResult____h594017 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q84 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302 ? - _theResult___snd__h648070 : - _theResult____h639769 ; + _theResult___snd__h648067 : + _theResult____h639766 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718 ? - _theResult___snd__h734202 : + _theResult___snd__h734199 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080 ? - _theResult___snd__h734202 : - _theResult___snd__h752607 ; + _theResult___snd__h734199 : + _theResult___snd__h752604 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448 ? - _theResult___snd__h812359 : + _theResult___snd__h812356 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795 ? - _theResult___snd__h812359 : - _theResult___snd__h830764 ; + _theResult___snd__h812356 : + _theResult___snd__h830761 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218 ? - _theResult___snd__h773055 : + _theResult___snd__h773052 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565 ? - _theResult___snd__h773055 : - _theResult___snd__h791460 ; + _theResult___snd__h773052 : + _theResult___snd__h791457 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q111 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379 ? - _theResult___snd__h684633 : + _theResult___snd__h684630 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q124 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772 ? - _theResult___snd__h684633 : - _theResult___snd__h702423 ; + _theResult___snd__h684630 : + _theResult___snd__h702420 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q41 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585 ? - _theResult___snd__h593137 : + _theResult___snd__h593134 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q54 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978 ? - _theResult___snd__h593137 : - _theResult___snd__h610927 ; + _theResult___snd__h593134 : + _theResult___snd__h610924 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q76 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982 ? - _theResult___snd__h638886 : + _theResult___snd__h638883 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q89 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375 ? - _theResult___snd__h638886 : - _theResult___snd__h656676 ; + _theResult___snd__h638883 : + _theResult___snd__h656673 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10571 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - ((_theResult___fst_exp__h630241 == 8'd255) ? + ((_theResult___fst_exp__h630238 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556) : - ((_theResult___fst_exp__h638897 == 8'd255) ? + ((_theResult___fst_exp__h638894 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10621 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - ((_theResult___fst_exp__h630241 == 8'd255) ? + ((_theResult___fst_exp__h630238 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612) : - ((_theResult___fst_exp__h638897 == 8'd255) ? + ((_theResult___fst_exp__h638894 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11968 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - ((_theResult___fst_exp__h675988 == 8'd255) ? + ((_theResult___fst_exp__h675985 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953) : - ((_theResult___fst_exp__h684644 == 8'd255) ? + ((_theResult___fst_exp__h684641 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12018 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - ((_theResult___fst_exp__h675988 == 8'd255) ? + ((_theResult___fst_exp__h675985 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009) : - ((_theResult___fst_exp__h684644 == 8'd255) ? + ((_theResult___fst_exp__h684641 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9174 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - ((_theResult___fst_exp__h584492 == 8'd255) ? + ((_theResult___fst_exp__h584489 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159) : - ((_theResult___fst_exp__h593148 == 8'd255) ? + ((_theResult___fst_exp__h593145 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9224 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - ((_theResult___fst_exp__h584492 == 8'd255) ? + ((_theResult___fst_exp__h584489 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215) : - ((_theResult___fst_exp__h593148 == 8'd255) ? + ((_theResult___fst_exp__h593145 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 = - (_theResult____h667879[56] ? + (_theResult____h667876[56] ? 6'd0 : - (_theResult____h667879[55] ? + (_theResult____h667876[55] ? 6'd1 : - (_theResult____h667879[54] ? + (_theResult____h667876[54] ? 6'd2 : - (_theResult____h667879[53] ? + (_theResult____h667876[53] ? 6'd3 : - (_theResult____h667879[52] ? + (_theResult____h667876[52] ? 6'd4 : - (_theResult____h667879[51] ? + (_theResult____h667876[51] ? 6'd5 : - (_theResult____h667879[50] ? + (_theResult____h667876[50] ? 6'd6 : - (_theResult____h667879[49] ? + (_theResult____h667876[49] ? 6'd7 : - (_theResult____h667879[48] ? + (_theResult____h667876[48] ? 6'd8 : - (_theResult____h667879[47] ? + (_theResult____h667876[47] ? 6'd9 : - (_theResult____h667879[46] ? + (_theResult____h667876[46] ? 6'd10 : - (_theResult____h667879[45] ? + (_theResult____h667876[45] ? 6'd11 : - (_theResult____h667879[44] ? + (_theResult____h667876[44] ? 6'd12 : - (_theResult____h667879[43] ? + (_theResult____h667876[43] ? 6'd13 : - (_theResult____h667879[42] ? + (_theResult____h667876[42] ? 6'd14 : - (_theResult____h667879[41] ? + (_theResult____h667876[41] ? 6'd15 : - (_theResult____h667879[40] ? + (_theResult____h667876[40] ? 6'd16 : - (_theResult____h667879[39] ? + (_theResult____h667876[39] ? 6'd17 : - (_theResult____h667879[38] ? + (_theResult____h667876[38] ? 6'd18 : - (_theResult____h667879[37] ? + (_theResult____h667876[37] ? 6'd19 : - (_theResult____h667879[36] ? + (_theResult____h667876[36] ? 6'd20 : - (_theResult____h667879[35] ? + (_theResult____h667876[35] ? 6'd21 : - (_theResult____h667879[34] ? + (_theResult____h667876[34] ? 6'd22 : - (_theResult____h667879[33] ? + (_theResult____h667876[33] ? 6'd23 : - (_theResult____h667879[32] ? + (_theResult____h667876[32] ? 6'd24 : - (_theResult____h667879[31] ? + (_theResult____h667876[31] ? 6'd25 : - (_theResult____h667879[30] ? + (_theResult____h667876[30] ? 6'd26 : - (_theResult____h667879[29] ? + (_theResult____h667876[29] ? 6'd27 : - (_theResult____h667879[28] ? + (_theResult____h667876[28] ? 6'd28 : - (_theResult____h667879[27] ? + (_theResult____h667876[27] ? 6'd29 : - (_theResult____h667879[26] ? + (_theResult____h667876[26] ? 6'd30 : - (_theResult____h667879[25] ? + (_theResult____h667876[25] ? 6'd31 : - (_theResult____h667879[24] ? + (_theResult____h667876[24] ? 6'd32 : - (_theResult____h667879[23] ? + (_theResult____h667876[23] ? 6'd33 : - (_theResult____h667879[22] ? + (_theResult____h667876[22] ? 6'd34 : - (_theResult____h667879[21] ? + (_theResult____h667876[21] ? 6'd35 : - (_theResult____h667879[20] ? + (_theResult____h667876[20] ? 6'd36 : - (_theResult____h667879[19] ? + (_theResult____h667876[19] ? 6'd37 : - (_theResult____h667879[18] ? + (_theResult____h667876[18] ? 6'd38 : - (_theResult____h667879[17] ? + (_theResult____h667876[17] ? 6'd39 : - (_theResult____h667879[16] ? + (_theResult____h667876[16] ? 6'd40 : - (_theResult____h667879[15] ? + (_theResult____h667876[15] ? 6'd41 : - (_theResult____h667879[14] ? + (_theResult____h667876[14] ? 6'd42 : - (_theResult____h667879[13] ? + (_theResult____h667876[13] ? 6'd43 : - (_theResult____h667879[12] ? + (_theResult____h667876[12] ? 6'd44 : - (_theResult____h667879[11] ? + (_theResult____h667876[11] ? 6'd45 : - (_theResult____h667879[10] ? + (_theResult____h667876[10] ? 6'd46 : - (_theResult____h667879[9] ? + (_theResult____h667876[9] ? 6'd47 : - (_theResult____h667879[8] ? + (_theResult____h667876[8] ? 6'd48 : - (_theResult____h667879[7] ? + (_theResult____h667876[7] ? 6'd49 : - (_theResult____h667879[6] ? + (_theResult____h667876[6] ? 6'd50 : - (_theResult____h667879[5] ? + (_theResult____h667876[5] ? 6'd51 : - (_theResult____h667879[4] ? + (_theResult____h667876[4] ? 6'd52 : - (_theResult____h667879[3] ? + (_theResult____h667876[3] ? 6'd53 : - (_theResult____h667879[2] ? + (_theResult____h667876[2] ? 6'd54 : - (_theResult____h667879[1] ? + (_theResult____h667876[1] ? 6'd55 : - (_theResult____h667879[0] ? + (_theResult____h667876[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 = - (_theResult____h576381[56] ? + (_theResult____h576378[56] ? 6'd0 : - (_theResult____h576381[55] ? + (_theResult____h576378[55] ? 6'd1 : - (_theResult____h576381[54] ? + (_theResult____h576378[54] ? 6'd2 : - (_theResult____h576381[53] ? + (_theResult____h576378[53] ? 6'd3 : - (_theResult____h576381[52] ? + (_theResult____h576378[52] ? 6'd4 : - (_theResult____h576381[51] ? + (_theResult____h576378[51] ? 6'd5 : - (_theResult____h576381[50] ? + (_theResult____h576378[50] ? 6'd6 : - (_theResult____h576381[49] ? + (_theResult____h576378[49] ? 6'd7 : - (_theResult____h576381[48] ? + (_theResult____h576378[48] ? 6'd8 : - (_theResult____h576381[47] ? + (_theResult____h576378[47] ? 6'd9 : - (_theResult____h576381[46] ? + (_theResult____h576378[46] ? 6'd10 : - (_theResult____h576381[45] ? + (_theResult____h576378[45] ? 6'd11 : - (_theResult____h576381[44] ? + (_theResult____h576378[44] ? 6'd12 : - (_theResult____h576381[43] ? + (_theResult____h576378[43] ? 6'd13 : - (_theResult____h576381[42] ? + (_theResult____h576378[42] ? 6'd14 : - (_theResult____h576381[41] ? + (_theResult____h576378[41] ? 6'd15 : - (_theResult____h576381[40] ? + (_theResult____h576378[40] ? 6'd16 : - (_theResult____h576381[39] ? + (_theResult____h576378[39] ? 6'd17 : - (_theResult____h576381[38] ? + (_theResult____h576378[38] ? 6'd18 : - (_theResult____h576381[37] ? + (_theResult____h576378[37] ? 6'd19 : - (_theResult____h576381[36] ? + (_theResult____h576378[36] ? 6'd20 : - (_theResult____h576381[35] ? + (_theResult____h576378[35] ? 6'd21 : - (_theResult____h576381[34] ? + (_theResult____h576378[34] ? 6'd22 : - (_theResult____h576381[33] ? + (_theResult____h576378[33] ? 6'd23 : - (_theResult____h576381[32] ? + (_theResult____h576378[32] ? 6'd24 : - (_theResult____h576381[31] ? + (_theResult____h576378[31] ? 6'd25 : - (_theResult____h576381[30] ? + (_theResult____h576378[30] ? 6'd26 : - (_theResult____h576381[29] ? + (_theResult____h576378[29] ? 6'd27 : - (_theResult____h576381[28] ? + (_theResult____h576378[28] ? 6'd28 : - (_theResult____h576381[27] ? + (_theResult____h576378[27] ? 6'd29 : - (_theResult____h576381[26] ? + (_theResult____h576378[26] ? 6'd30 : - (_theResult____h576381[25] ? + (_theResult____h576378[25] ? 6'd31 : - (_theResult____h576381[24] ? + (_theResult____h576378[24] ? 6'd32 : - (_theResult____h576381[23] ? + (_theResult____h576378[23] ? 6'd33 : - (_theResult____h576381[22] ? + (_theResult____h576378[22] ? 6'd34 : - (_theResult____h576381[21] ? + (_theResult____h576378[21] ? 6'd35 : - (_theResult____h576381[20] ? + (_theResult____h576378[20] ? 6'd36 : - (_theResult____h576381[19] ? + (_theResult____h576378[19] ? 6'd37 : - (_theResult____h576381[18] ? + (_theResult____h576378[18] ? 6'd38 : - (_theResult____h576381[17] ? + (_theResult____h576378[17] ? 6'd39 : - (_theResult____h576381[16] ? + (_theResult____h576378[16] ? 6'd40 : - (_theResult____h576381[15] ? + (_theResult____h576378[15] ? 6'd41 : - (_theResult____h576381[14] ? + (_theResult____h576378[14] ? 6'd42 : - (_theResult____h576381[13] ? + (_theResult____h576378[13] ? 6'd43 : - (_theResult____h576381[12] ? + (_theResult____h576378[12] ? 6'd44 : - (_theResult____h576381[11] ? + (_theResult____h576378[11] ? 6'd45 : - (_theResult____h576381[10] ? + (_theResult____h576378[10] ? 6'd46 : - (_theResult____h576381[9] ? + (_theResult____h576378[9] ? 6'd47 : - (_theResult____h576381[8] ? + (_theResult____h576378[8] ? 6'd48 : - (_theResult____h576381[7] ? + (_theResult____h576378[7] ? 6'd49 : - (_theResult____h576381[6] ? + (_theResult____h576378[6] ? 6'd50 : - (_theResult____h576381[5] ? + (_theResult____h576378[5] ? 6'd51 : - (_theResult____h576381[4] ? + (_theResult____h576378[4] ? 6'd52 : - (_theResult____h576381[3] ? + (_theResult____h576378[3] ? 6'd53 : - (_theResult____h576381[2] ? + (_theResult____h576378[2] ? 6'd54 : - (_theResult____h576381[1] ? + (_theResult____h576378[1] ? 6'd55 : - (_theResult____h576381[0] ? + (_theResult____h576378[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 = - (_theResult____h622132[56] ? + (_theResult____h622129[56] ? 6'd0 : - (_theResult____h622132[55] ? + (_theResult____h622129[55] ? 6'd1 : - (_theResult____h622132[54] ? + (_theResult____h622129[54] ? 6'd2 : - (_theResult____h622132[53] ? + (_theResult____h622129[53] ? 6'd3 : - (_theResult____h622132[52] ? + (_theResult____h622129[52] ? 6'd4 : - (_theResult____h622132[51] ? + (_theResult____h622129[51] ? 6'd5 : - (_theResult____h622132[50] ? + (_theResult____h622129[50] ? 6'd6 : - (_theResult____h622132[49] ? + (_theResult____h622129[49] ? 6'd7 : - (_theResult____h622132[48] ? + (_theResult____h622129[48] ? 6'd8 : - (_theResult____h622132[47] ? + (_theResult____h622129[47] ? 6'd9 : - (_theResult____h622132[46] ? + (_theResult____h622129[46] ? 6'd10 : - (_theResult____h622132[45] ? + (_theResult____h622129[45] ? 6'd11 : - (_theResult____h622132[44] ? + (_theResult____h622129[44] ? 6'd12 : - (_theResult____h622132[43] ? + (_theResult____h622129[43] ? 6'd13 : - (_theResult____h622132[42] ? + (_theResult____h622129[42] ? 6'd14 : - (_theResult____h622132[41] ? + (_theResult____h622129[41] ? 6'd15 : - (_theResult____h622132[40] ? + (_theResult____h622129[40] ? 6'd16 : - (_theResult____h622132[39] ? + (_theResult____h622129[39] ? 6'd17 : - (_theResult____h622132[38] ? + (_theResult____h622129[38] ? 6'd18 : - (_theResult____h622132[37] ? + (_theResult____h622129[37] ? 6'd19 : - (_theResult____h622132[36] ? + (_theResult____h622129[36] ? 6'd20 : - (_theResult____h622132[35] ? + (_theResult____h622129[35] ? 6'd21 : - (_theResult____h622132[34] ? + (_theResult____h622129[34] ? 6'd22 : - (_theResult____h622132[33] ? + (_theResult____h622129[33] ? 6'd23 : - (_theResult____h622132[32] ? + (_theResult____h622129[32] ? 6'd24 : - (_theResult____h622132[31] ? + (_theResult____h622129[31] ? 6'd25 : - (_theResult____h622132[30] ? + (_theResult____h622129[30] ? 6'd26 : - (_theResult____h622132[29] ? + (_theResult____h622129[29] ? 6'd27 : - (_theResult____h622132[28] ? + (_theResult____h622129[28] ? 6'd28 : - (_theResult____h622132[27] ? + (_theResult____h622129[27] ? 6'd29 : - (_theResult____h622132[26] ? + (_theResult____h622129[26] ? 6'd30 : - (_theResult____h622132[25] ? + (_theResult____h622129[25] ? 6'd31 : - (_theResult____h622132[24] ? + (_theResult____h622129[24] ? 6'd32 : - (_theResult____h622132[23] ? + (_theResult____h622129[23] ? 6'd33 : - (_theResult____h622132[22] ? + (_theResult____h622129[22] ? 6'd34 : - (_theResult____h622132[21] ? + (_theResult____h622129[21] ? 6'd35 : - (_theResult____h622132[20] ? + (_theResult____h622129[20] ? 6'd36 : - (_theResult____h622132[19] ? + (_theResult____h622129[19] ? 6'd37 : - (_theResult____h622132[18] ? + (_theResult____h622129[18] ? 6'd38 : - (_theResult____h622132[17] ? + (_theResult____h622129[17] ? 6'd39 : - (_theResult____h622132[16] ? + (_theResult____h622129[16] ? 6'd40 : - (_theResult____h622132[15] ? + (_theResult____h622129[15] ? 6'd41 : - (_theResult____h622132[14] ? + (_theResult____h622129[14] ? 6'd42 : - (_theResult____h622132[13] ? + (_theResult____h622129[13] ? 6'd43 : - (_theResult____h622132[12] ? + (_theResult____h622129[12] ? 6'd44 : - (_theResult____h622132[11] ? + (_theResult____h622129[11] ? 6'd45 : - (_theResult____h622132[10] ? + (_theResult____h622129[10] ? 6'd46 : - (_theResult____h622132[9] ? + (_theResult____h622129[9] ? 6'd47 : - (_theResult____h622132[8] ? + (_theResult____h622129[8] ? 6'd48 : - (_theResult____h622132[7] ? + (_theResult____h622129[7] ? 6'd49 : - (_theResult____h622132[6] ? + (_theResult____h622129[6] ? 6'd50 : - (_theResult____h622132[5] ? + (_theResult____h622129[5] ? 6'd51 : - (_theResult____h622132[4] ? + (_theResult____h622129[4] ? 6'd52 : - (_theResult____h622132[3] ? + (_theResult____h622129[3] ? 6'd53 : - (_theResult____h622132[2] ? + (_theResult____h622129[2] ? 6'd54 : - (_theResult____h622132[1] ? + (_theResult____h622129[1] ? 6'd55 : - (_theResult____h622132[0] ? + (_theResult____h622129[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 = - (_theResult____h735554[56] ? + (_theResult____h735551[56] ? 6'd0 : - (_theResult____h735554[55] ? + (_theResult____h735551[55] ? 6'd1 : - (_theResult____h735554[54] ? + (_theResult____h735551[54] ? 6'd2 : - (_theResult____h735554[53] ? + (_theResult____h735551[53] ? 6'd3 : - (_theResult____h735554[52] ? + (_theResult____h735551[52] ? 6'd4 : - (_theResult____h735554[51] ? + (_theResult____h735551[51] ? 6'd5 : - (_theResult____h735554[50] ? + (_theResult____h735551[50] ? 6'd6 : - (_theResult____h735554[49] ? + (_theResult____h735551[49] ? 6'd7 : - (_theResult____h735554[48] ? + (_theResult____h735551[48] ? 6'd8 : - (_theResult____h735554[47] ? + (_theResult____h735551[47] ? 6'd9 : - (_theResult____h735554[46] ? + (_theResult____h735551[46] ? 6'd10 : - (_theResult____h735554[45] ? + (_theResult____h735551[45] ? 6'd11 : - (_theResult____h735554[44] ? + (_theResult____h735551[44] ? 6'd12 : - (_theResult____h735554[43] ? + (_theResult____h735551[43] ? 6'd13 : - (_theResult____h735554[42] ? + (_theResult____h735551[42] ? 6'd14 : - (_theResult____h735554[41] ? + (_theResult____h735551[41] ? 6'd15 : - (_theResult____h735554[40] ? + (_theResult____h735551[40] ? 6'd16 : - (_theResult____h735554[39] ? + (_theResult____h735551[39] ? 6'd17 : - (_theResult____h735554[38] ? + (_theResult____h735551[38] ? 6'd18 : - (_theResult____h735554[37] ? + (_theResult____h735551[37] ? 6'd19 : - (_theResult____h735554[36] ? + (_theResult____h735551[36] ? 6'd20 : - (_theResult____h735554[35] ? + (_theResult____h735551[35] ? 6'd21 : - (_theResult____h735554[34] ? + (_theResult____h735551[34] ? 6'd22 : - (_theResult____h735554[33] ? + (_theResult____h735551[33] ? 6'd23 : - (_theResult____h735554[32] ? + (_theResult____h735551[32] ? 6'd24 : - (_theResult____h735554[31] ? + (_theResult____h735551[31] ? 6'd25 : - (_theResult____h735554[30] ? + (_theResult____h735551[30] ? 6'd26 : - (_theResult____h735554[29] ? + (_theResult____h735551[29] ? 6'd27 : - (_theResult____h735554[28] ? + (_theResult____h735551[28] ? 6'd28 : - (_theResult____h735554[27] ? + (_theResult____h735551[27] ? 6'd29 : - (_theResult____h735554[26] ? + (_theResult____h735551[26] ? 6'd30 : - (_theResult____h735554[25] ? + (_theResult____h735551[25] ? 6'd31 : - (_theResult____h735554[24] ? + (_theResult____h735551[24] ? 6'd32 : - (_theResult____h735554[23] ? + (_theResult____h735551[23] ? 6'd33 : - (_theResult____h735554[22] ? + (_theResult____h735551[22] ? 6'd34 : - (_theResult____h735554[21] ? + (_theResult____h735551[21] ? 6'd35 : - (_theResult____h735554[20] ? + (_theResult____h735551[20] ? 6'd36 : - (_theResult____h735554[19] ? + (_theResult____h735551[19] ? 6'd37 : - (_theResult____h735554[18] ? + (_theResult____h735551[18] ? 6'd38 : - (_theResult____h735554[17] ? + (_theResult____h735551[17] ? 6'd39 : - (_theResult____h735554[16] ? + (_theResult____h735551[16] ? 6'd40 : - (_theResult____h735554[15] ? + (_theResult____h735551[15] ? 6'd41 : - (_theResult____h735554[14] ? + (_theResult____h735551[14] ? 6'd42 : - (_theResult____h735554[13] ? + (_theResult____h735551[13] ? 6'd43 : - (_theResult____h735554[12] ? + (_theResult____h735551[12] ? 6'd44 : - (_theResult____h735554[11] ? + (_theResult____h735551[11] ? 6'd45 : - (_theResult____h735554[10] ? + (_theResult____h735551[10] ? 6'd46 : - (_theResult____h735554[9] ? + (_theResult____h735551[9] ? 6'd47 : - (_theResult____h735554[8] ? + (_theResult____h735551[8] ? 6'd48 : - (_theResult____h735554[7] ? + (_theResult____h735551[7] ? 6'd49 : - (_theResult____h735554[6] ? + (_theResult____h735551[6] ? 6'd50 : - (_theResult____h735554[5] ? + (_theResult____h735551[5] ? 6'd51 : - (_theResult____h735554[4] ? + (_theResult____h735551[4] ? 6'd52 : - (_theResult____h735554[3] ? + (_theResult____h735551[3] ? 6'd53 : - (_theResult____h735554[2] ? + (_theResult____h735551[2] ? 6'd54 : - (_theResult____h735554[1] ? + (_theResult____h735551[1] ? 6'd55 : - (_theResult____h735554[0] ? + (_theResult____h735551[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 = - (_theResult____h813711[56] ? + (_theResult____h813708[56] ? 6'd0 : - (_theResult____h813711[55] ? + (_theResult____h813708[55] ? 6'd1 : - (_theResult____h813711[54] ? + (_theResult____h813708[54] ? 6'd2 : - (_theResult____h813711[53] ? + (_theResult____h813708[53] ? 6'd3 : - (_theResult____h813711[52] ? + (_theResult____h813708[52] ? 6'd4 : - (_theResult____h813711[51] ? + (_theResult____h813708[51] ? 6'd5 : - (_theResult____h813711[50] ? + (_theResult____h813708[50] ? 6'd6 : - (_theResult____h813711[49] ? + (_theResult____h813708[49] ? 6'd7 : - (_theResult____h813711[48] ? + (_theResult____h813708[48] ? 6'd8 : - (_theResult____h813711[47] ? + (_theResult____h813708[47] ? 6'd9 : - (_theResult____h813711[46] ? + (_theResult____h813708[46] ? 6'd10 : - (_theResult____h813711[45] ? + (_theResult____h813708[45] ? 6'd11 : - (_theResult____h813711[44] ? + (_theResult____h813708[44] ? 6'd12 : - (_theResult____h813711[43] ? + (_theResult____h813708[43] ? 6'd13 : - (_theResult____h813711[42] ? + (_theResult____h813708[42] ? 6'd14 : - (_theResult____h813711[41] ? + (_theResult____h813708[41] ? 6'd15 : - (_theResult____h813711[40] ? + (_theResult____h813708[40] ? 6'd16 : - (_theResult____h813711[39] ? + (_theResult____h813708[39] ? 6'd17 : - (_theResult____h813711[38] ? + (_theResult____h813708[38] ? 6'd18 : - (_theResult____h813711[37] ? + (_theResult____h813708[37] ? 6'd19 : - (_theResult____h813711[36] ? + (_theResult____h813708[36] ? 6'd20 : - (_theResult____h813711[35] ? + (_theResult____h813708[35] ? 6'd21 : - (_theResult____h813711[34] ? + (_theResult____h813708[34] ? 6'd22 : - (_theResult____h813711[33] ? + (_theResult____h813708[33] ? 6'd23 : - (_theResult____h813711[32] ? + (_theResult____h813708[32] ? 6'd24 : - (_theResult____h813711[31] ? + (_theResult____h813708[31] ? 6'd25 : - (_theResult____h813711[30] ? + (_theResult____h813708[30] ? 6'd26 : - (_theResult____h813711[29] ? + (_theResult____h813708[29] ? 6'd27 : - (_theResult____h813711[28] ? + (_theResult____h813708[28] ? 6'd28 : - (_theResult____h813711[27] ? + (_theResult____h813708[27] ? 6'd29 : - (_theResult____h813711[26] ? + (_theResult____h813708[26] ? 6'd30 : - (_theResult____h813711[25] ? + (_theResult____h813708[25] ? 6'd31 : - (_theResult____h813711[24] ? + (_theResult____h813708[24] ? 6'd32 : - (_theResult____h813711[23] ? + (_theResult____h813708[23] ? 6'd33 : - (_theResult____h813711[22] ? + (_theResult____h813708[22] ? 6'd34 : - (_theResult____h813711[21] ? + (_theResult____h813708[21] ? 6'd35 : - (_theResult____h813711[20] ? + (_theResult____h813708[20] ? 6'd36 : - (_theResult____h813711[19] ? + (_theResult____h813708[19] ? 6'd37 : - (_theResult____h813711[18] ? + (_theResult____h813708[18] ? 6'd38 : - (_theResult____h813711[17] ? + (_theResult____h813708[17] ? 6'd39 : - (_theResult____h813711[16] ? + (_theResult____h813708[16] ? 6'd40 : - (_theResult____h813711[15] ? + (_theResult____h813708[15] ? 6'd41 : - (_theResult____h813711[14] ? + (_theResult____h813708[14] ? 6'd42 : - (_theResult____h813711[13] ? + (_theResult____h813708[13] ? 6'd43 : - (_theResult____h813711[12] ? + (_theResult____h813708[12] ? 6'd44 : - (_theResult____h813711[11] ? + (_theResult____h813708[11] ? 6'd45 : - (_theResult____h813711[10] ? + (_theResult____h813708[10] ? 6'd46 : - (_theResult____h813711[9] ? + (_theResult____h813708[9] ? 6'd47 : - (_theResult____h813711[8] ? + (_theResult____h813708[8] ? 6'd48 : - (_theResult____h813711[7] ? + (_theResult____h813708[7] ? 6'd49 : - (_theResult____h813711[6] ? + (_theResult____h813708[6] ? 6'd50 : - (_theResult____h813711[5] ? + (_theResult____h813708[5] ? 6'd51 : - (_theResult____h813711[4] ? + (_theResult____h813708[4] ? 6'd52 : - (_theResult____h813711[3] ? + (_theResult____h813708[3] ? 6'd53 : - (_theResult____h813711[2] ? + (_theResult____h813708[2] ? 6'd54 : - (_theResult____h813711[1] ? + (_theResult____h813708[1] ? 6'd55 : - (_theResult____h813711[0] ? + (_theResult____h813708[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 = - (_theResult____h774407[56] ? + (_theResult____h774404[56] ? 6'd0 : - (_theResult____h774407[55] ? + (_theResult____h774404[55] ? 6'd1 : - (_theResult____h774407[54] ? + (_theResult____h774404[54] ? 6'd2 : - (_theResult____h774407[53] ? + (_theResult____h774404[53] ? 6'd3 : - (_theResult____h774407[52] ? + (_theResult____h774404[52] ? 6'd4 : - (_theResult____h774407[51] ? + (_theResult____h774404[51] ? 6'd5 : - (_theResult____h774407[50] ? + (_theResult____h774404[50] ? 6'd6 : - (_theResult____h774407[49] ? + (_theResult____h774404[49] ? 6'd7 : - (_theResult____h774407[48] ? + (_theResult____h774404[48] ? 6'd8 : - (_theResult____h774407[47] ? + (_theResult____h774404[47] ? 6'd9 : - (_theResult____h774407[46] ? + (_theResult____h774404[46] ? 6'd10 : - (_theResult____h774407[45] ? + (_theResult____h774404[45] ? 6'd11 : - (_theResult____h774407[44] ? + (_theResult____h774404[44] ? 6'd12 : - (_theResult____h774407[43] ? + (_theResult____h774404[43] ? 6'd13 : - (_theResult____h774407[42] ? + (_theResult____h774404[42] ? 6'd14 : - (_theResult____h774407[41] ? + (_theResult____h774404[41] ? 6'd15 : - (_theResult____h774407[40] ? + (_theResult____h774404[40] ? 6'd16 : - (_theResult____h774407[39] ? + (_theResult____h774404[39] ? 6'd17 : - (_theResult____h774407[38] ? + (_theResult____h774404[38] ? 6'd18 : - (_theResult____h774407[37] ? + (_theResult____h774404[37] ? 6'd19 : - (_theResult____h774407[36] ? + (_theResult____h774404[36] ? 6'd20 : - (_theResult____h774407[35] ? + (_theResult____h774404[35] ? 6'd21 : - (_theResult____h774407[34] ? + (_theResult____h774404[34] ? 6'd22 : - (_theResult____h774407[33] ? + (_theResult____h774404[33] ? 6'd23 : - (_theResult____h774407[32] ? + (_theResult____h774404[32] ? 6'd24 : - (_theResult____h774407[31] ? + (_theResult____h774404[31] ? 6'd25 : - (_theResult____h774407[30] ? + (_theResult____h774404[30] ? 6'd26 : - (_theResult____h774407[29] ? + (_theResult____h774404[29] ? 6'd27 : - (_theResult____h774407[28] ? + (_theResult____h774404[28] ? 6'd28 : - (_theResult____h774407[27] ? + (_theResult____h774404[27] ? 6'd29 : - (_theResult____h774407[26] ? + (_theResult____h774404[26] ? 6'd30 : - (_theResult____h774407[25] ? + (_theResult____h774404[25] ? 6'd31 : - (_theResult____h774407[24] ? + (_theResult____h774404[24] ? 6'd32 : - (_theResult____h774407[23] ? + (_theResult____h774404[23] ? 6'd33 : - (_theResult____h774407[22] ? + (_theResult____h774404[22] ? 6'd34 : - (_theResult____h774407[21] ? + (_theResult____h774404[21] ? 6'd35 : - (_theResult____h774407[20] ? + (_theResult____h774404[20] ? 6'd36 : - (_theResult____h774407[19] ? + (_theResult____h774404[19] ? 6'd37 : - (_theResult____h774407[18] ? + (_theResult____h774404[18] ? 6'd38 : - (_theResult____h774407[17] ? + (_theResult____h774404[17] ? 6'd39 : - (_theResult____h774407[16] ? + (_theResult____h774404[16] ? 6'd40 : - (_theResult____h774407[15] ? + (_theResult____h774404[15] ? 6'd41 : - (_theResult____h774407[14] ? + (_theResult____h774404[14] ? 6'd42 : - (_theResult____h774407[13] ? + (_theResult____h774404[13] ? 6'd43 : - (_theResult____h774407[12] ? + (_theResult____h774404[12] ? 6'd44 : - (_theResult____h774407[11] ? + (_theResult____h774404[11] ? 6'd45 : - (_theResult____h774407[10] ? + (_theResult____h774404[10] ? 6'd46 : - (_theResult____h774407[9] ? + (_theResult____h774404[9] ? 6'd47 : - (_theResult____h774407[8] ? + (_theResult____h774404[8] ? 6'd48 : - (_theResult____h774407[7] ? + (_theResult____h774404[7] ? 6'd49 : - (_theResult____h774407[6] ? + (_theResult____h774404[6] ? 6'd50 : - (_theResult____h774407[5] ? + (_theResult____h774404[5] ? 6'd51 : - (_theResult____h774407[4] ? + (_theResult____h774404[4] ? 6'd52 : - (_theResult____h774407[3] ? + (_theResult____h774404[3] ? 6'd53 : - (_theResult____h774407[2] ? + (_theResult____h774404[2] ? 6'd54 : - (_theResult____h774407[1] ? + (_theResult____h774404[1] ? 6'd55 : - (_theResult____h774407[0] ? + (_theResult____h774404[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 = - (_theResult____h639769[56] ? + (_theResult____h639766[56] ? 6'd0 : - (_theResult____h639769[55] ? + (_theResult____h639766[55] ? 6'd1 : - (_theResult____h639769[54] ? + (_theResult____h639766[54] ? 6'd2 : - (_theResult____h639769[53] ? + (_theResult____h639766[53] ? 6'd3 : - (_theResult____h639769[52] ? + (_theResult____h639766[52] ? 6'd4 : - (_theResult____h639769[51] ? + (_theResult____h639766[51] ? 6'd5 : - (_theResult____h639769[50] ? + (_theResult____h639766[50] ? 6'd6 : - (_theResult____h639769[49] ? + (_theResult____h639766[49] ? 6'd7 : - (_theResult____h639769[48] ? + (_theResult____h639766[48] ? 6'd8 : - (_theResult____h639769[47] ? + (_theResult____h639766[47] ? 6'd9 : - (_theResult____h639769[46] ? + (_theResult____h639766[46] ? 6'd10 : - (_theResult____h639769[45] ? + (_theResult____h639766[45] ? 6'd11 : - (_theResult____h639769[44] ? + (_theResult____h639766[44] ? 6'd12 : - (_theResult____h639769[43] ? + (_theResult____h639766[43] ? 6'd13 : - (_theResult____h639769[42] ? + (_theResult____h639766[42] ? 6'd14 : - (_theResult____h639769[41] ? + (_theResult____h639766[41] ? 6'd15 : - (_theResult____h639769[40] ? + (_theResult____h639766[40] ? 6'd16 : - (_theResult____h639769[39] ? + (_theResult____h639766[39] ? 6'd17 : - (_theResult____h639769[38] ? + (_theResult____h639766[38] ? 6'd18 : - (_theResult____h639769[37] ? + (_theResult____h639766[37] ? 6'd19 : - (_theResult____h639769[36] ? + (_theResult____h639766[36] ? 6'd20 : - (_theResult____h639769[35] ? + (_theResult____h639766[35] ? 6'd21 : - (_theResult____h639769[34] ? + (_theResult____h639766[34] ? 6'd22 : - (_theResult____h639769[33] ? + (_theResult____h639766[33] ? 6'd23 : - (_theResult____h639769[32] ? + (_theResult____h639766[32] ? 6'd24 : - (_theResult____h639769[31] ? + (_theResult____h639766[31] ? 6'd25 : - (_theResult____h639769[30] ? + (_theResult____h639766[30] ? 6'd26 : - (_theResult____h639769[29] ? + (_theResult____h639766[29] ? 6'd27 : - (_theResult____h639769[28] ? + (_theResult____h639766[28] ? 6'd28 : - (_theResult____h639769[27] ? + (_theResult____h639766[27] ? 6'd29 : - (_theResult____h639769[26] ? + (_theResult____h639766[26] ? 6'd30 : - (_theResult____h639769[25] ? + (_theResult____h639766[25] ? 6'd31 : - (_theResult____h639769[24] ? + (_theResult____h639766[24] ? 6'd32 : - (_theResult____h639769[23] ? + (_theResult____h639766[23] ? 6'd33 : - (_theResult____h639769[22] ? + (_theResult____h639766[22] ? 6'd34 : - (_theResult____h639769[21] ? + (_theResult____h639766[21] ? 6'd35 : - (_theResult____h639769[20] ? + (_theResult____h639766[20] ? 6'd36 : - (_theResult____h639769[19] ? + (_theResult____h639766[19] ? 6'd37 : - (_theResult____h639769[18] ? + (_theResult____h639766[18] ? 6'd38 : - (_theResult____h639769[17] ? + (_theResult____h639766[17] ? 6'd39 : - (_theResult____h639769[16] ? + (_theResult____h639766[16] ? 6'd40 : - (_theResult____h639769[15] ? + (_theResult____h639766[15] ? 6'd41 : - (_theResult____h639769[14] ? + (_theResult____h639766[14] ? 6'd42 : - (_theResult____h639769[13] ? + (_theResult____h639766[13] ? 6'd43 : - (_theResult____h639769[12] ? + (_theResult____h639766[12] ? 6'd44 : - (_theResult____h639769[11] ? + (_theResult____h639766[11] ? 6'd45 : - (_theResult____h639769[10] ? + (_theResult____h639766[10] ? 6'd46 : - (_theResult____h639769[9] ? + (_theResult____h639766[9] ? 6'd47 : - (_theResult____h639769[8] ? + (_theResult____h639766[8] ? 6'd48 : - (_theResult____h639769[7] ? + (_theResult____h639766[7] ? 6'd49 : - (_theResult____h639769[6] ? + (_theResult____h639766[6] ? 6'd50 : - (_theResult____h639769[5] ? + (_theResult____h639766[5] ? 6'd51 : - (_theResult____h639769[4] ? + (_theResult____h639766[4] ? 6'd52 : - (_theResult____h639769[3] ? + (_theResult____h639766[3] ? 6'd53 : - (_theResult____h639769[2] ? + (_theResult____h639766[2] ? 6'd54 : - (_theResult____h639769[1] ? + (_theResult____h639766[1] ? 6'd55 : - (_theResult____h639769[0] ? + (_theResult____h639766[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 = - (_theResult____h685516[56] ? + (_theResult____h685513[56] ? 6'd0 : - (_theResult____h685516[55] ? + (_theResult____h685513[55] ? 6'd1 : - (_theResult____h685516[54] ? + (_theResult____h685513[54] ? 6'd2 : - (_theResult____h685516[53] ? + (_theResult____h685513[53] ? 6'd3 : - (_theResult____h685516[52] ? + (_theResult____h685513[52] ? 6'd4 : - (_theResult____h685516[51] ? + (_theResult____h685513[51] ? 6'd5 : - (_theResult____h685516[50] ? + (_theResult____h685513[50] ? 6'd6 : - (_theResult____h685516[49] ? + (_theResult____h685513[49] ? 6'd7 : - (_theResult____h685516[48] ? + (_theResult____h685513[48] ? 6'd8 : - (_theResult____h685516[47] ? + (_theResult____h685513[47] ? 6'd9 : - (_theResult____h685516[46] ? + (_theResult____h685513[46] ? 6'd10 : - (_theResult____h685516[45] ? + (_theResult____h685513[45] ? 6'd11 : - (_theResult____h685516[44] ? + (_theResult____h685513[44] ? 6'd12 : - (_theResult____h685516[43] ? + (_theResult____h685513[43] ? 6'd13 : - (_theResult____h685516[42] ? + (_theResult____h685513[42] ? 6'd14 : - (_theResult____h685516[41] ? + (_theResult____h685513[41] ? 6'd15 : - (_theResult____h685516[40] ? + (_theResult____h685513[40] ? 6'd16 : - (_theResult____h685516[39] ? + (_theResult____h685513[39] ? 6'd17 : - (_theResult____h685516[38] ? + (_theResult____h685513[38] ? 6'd18 : - (_theResult____h685516[37] ? + (_theResult____h685513[37] ? 6'd19 : - (_theResult____h685516[36] ? + (_theResult____h685513[36] ? 6'd20 : - (_theResult____h685516[35] ? + (_theResult____h685513[35] ? 6'd21 : - (_theResult____h685516[34] ? + (_theResult____h685513[34] ? 6'd22 : - (_theResult____h685516[33] ? + (_theResult____h685513[33] ? 6'd23 : - (_theResult____h685516[32] ? + (_theResult____h685513[32] ? 6'd24 : - (_theResult____h685516[31] ? + (_theResult____h685513[31] ? 6'd25 : - (_theResult____h685516[30] ? + (_theResult____h685513[30] ? 6'd26 : - (_theResult____h685516[29] ? + (_theResult____h685513[29] ? 6'd27 : - (_theResult____h685516[28] ? + (_theResult____h685513[28] ? 6'd28 : - (_theResult____h685516[27] ? + (_theResult____h685513[27] ? 6'd29 : - (_theResult____h685516[26] ? + (_theResult____h685513[26] ? 6'd30 : - (_theResult____h685516[25] ? + (_theResult____h685513[25] ? 6'd31 : - (_theResult____h685516[24] ? + (_theResult____h685513[24] ? 6'd32 : - (_theResult____h685516[23] ? + (_theResult____h685513[23] ? 6'd33 : - (_theResult____h685516[22] ? + (_theResult____h685513[22] ? 6'd34 : - (_theResult____h685516[21] ? + (_theResult____h685513[21] ? 6'd35 : - (_theResult____h685516[20] ? + (_theResult____h685513[20] ? 6'd36 : - (_theResult____h685516[19] ? + (_theResult____h685513[19] ? 6'd37 : - (_theResult____h685516[18] ? + (_theResult____h685513[18] ? 6'd38 : - (_theResult____h685516[17] ? + (_theResult____h685513[17] ? 6'd39 : - (_theResult____h685516[16] ? + (_theResult____h685513[16] ? 6'd40 : - (_theResult____h685516[15] ? + (_theResult____h685513[15] ? 6'd41 : - (_theResult____h685516[14] ? + (_theResult____h685513[14] ? 6'd42 : - (_theResult____h685516[13] ? + (_theResult____h685513[13] ? 6'd43 : - (_theResult____h685516[12] ? + (_theResult____h685513[12] ? 6'd44 : - (_theResult____h685516[11] ? + (_theResult____h685513[11] ? 6'd45 : - (_theResult____h685516[10] ? + (_theResult____h685513[10] ? 6'd46 : - (_theResult____h685516[9] ? + (_theResult____h685513[9] ? 6'd47 : - (_theResult____h685516[8] ? + (_theResult____h685513[8] ? 6'd48 : - (_theResult____h685516[7] ? + (_theResult____h685513[7] ? 6'd49 : - (_theResult____h685516[6] ? + (_theResult____h685513[6] ? 6'd50 : - (_theResult____h685516[5] ? + (_theResult____h685513[5] ? 6'd51 : - (_theResult____h685516[4] ? + (_theResult____h685513[4] ? 6'd52 : - (_theResult____h685516[3] ? + (_theResult____h685513[3] ? 6'd53 : - (_theResult____h685516[2] ? + (_theResult____h685513[2] ? 6'd54 : - (_theResult____h685516[1] ? + (_theResult____h685513[1] ? 6'd55 : - (_theResult____h685516[0] ? + (_theResult____h685513[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 = - (_theResult____h594020[56] ? + (_theResult____h594017[56] ? 6'd0 : - (_theResult____h594020[55] ? + (_theResult____h594017[55] ? 6'd1 : - (_theResult____h594020[54] ? + (_theResult____h594017[54] ? 6'd2 : - (_theResult____h594020[53] ? + (_theResult____h594017[53] ? 6'd3 : - (_theResult____h594020[52] ? + (_theResult____h594017[52] ? 6'd4 : - (_theResult____h594020[51] ? + (_theResult____h594017[51] ? 6'd5 : - (_theResult____h594020[50] ? + (_theResult____h594017[50] ? 6'd6 : - (_theResult____h594020[49] ? + (_theResult____h594017[49] ? 6'd7 : - (_theResult____h594020[48] ? + (_theResult____h594017[48] ? 6'd8 : - (_theResult____h594020[47] ? + (_theResult____h594017[47] ? 6'd9 : - (_theResult____h594020[46] ? + (_theResult____h594017[46] ? 6'd10 : - (_theResult____h594020[45] ? + (_theResult____h594017[45] ? 6'd11 : - (_theResult____h594020[44] ? + (_theResult____h594017[44] ? 6'd12 : - (_theResult____h594020[43] ? + (_theResult____h594017[43] ? 6'd13 : - (_theResult____h594020[42] ? + (_theResult____h594017[42] ? 6'd14 : - (_theResult____h594020[41] ? + (_theResult____h594017[41] ? 6'd15 : - (_theResult____h594020[40] ? + (_theResult____h594017[40] ? 6'd16 : - (_theResult____h594020[39] ? + (_theResult____h594017[39] ? 6'd17 : - (_theResult____h594020[38] ? + (_theResult____h594017[38] ? 6'd18 : - (_theResult____h594020[37] ? + (_theResult____h594017[37] ? 6'd19 : - (_theResult____h594020[36] ? + (_theResult____h594017[36] ? 6'd20 : - (_theResult____h594020[35] ? + (_theResult____h594017[35] ? 6'd21 : - (_theResult____h594020[34] ? + (_theResult____h594017[34] ? 6'd22 : - (_theResult____h594020[33] ? + (_theResult____h594017[33] ? 6'd23 : - (_theResult____h594020[32] ? + (_theResult____h594017[32] ? 6'd24 : - (_theResult____h594020[31] ? + (_theResult____h594017[31] ? 6'd25 : - (_theResult____h594020[30] ? + (_theResult____h594017[30] ? 6'd26 : - (_theResult____h594020[29] ? + (_theResult____h594017[29] ? 6'd27 : - (_theResult____h594020[28] ? + (_theResult____h594017[28] ? 6'd28 : - (_theResult____h594020[27] ? + (_theResult____h594017[27] ? 6'd29 : - (_theResult____h594020[26] ? + (_theResult____h594017[26] ? 6'd30 : - (_theResult____h594020[25] ? + (_theResult____h594017[25] ? 6'd31 : - (_theResult____h594020[24] ? + (_theResult____h594017[24] ? 6'd32 : - (_theResult____h594020[23] ? + (_theResult____h594017[23] ? 6'd33 : - (_theResult____h594020[22] ? + (_theResult____h594017[22] ? 6'd34 : - (_theResult____h594020[21] ? + (_theResult____h594017[21] ? 6'd35 : - (_theResult____h594020[20] ? + (_theResult____h594017[20] ? 6'd36 : - (_theResult____h594020[19] ? + (_theResult____h594017[19] ? 6'd37 : - (_theResult____h594020[18] ? + (_theResult____h594017[18] ? 6'd38 : - (_theResult____h594020[17] ? + (_theResult____h594017[17] ? 6'd39 : - (_theResult____h594020[16] ? + (_theResult____h594017[16] ? 6'd40 : - (_theResult____h594020[15] ? + (_theResult____h594017[15] ? 6'd41 : - (_theResult____h594020[14] ? + (_theResult____h594017[14] ? 6'd42 : - (_theResult____h594020[13] ? + (_theResult____h594017[13] ? 6'd43 : - (_theResult____h594020[12] ? + (_theResult____h594017[12] ? 6'd44 : - (_theResult____h594020[11] ? + (_theResult____h594017[11] ? 6'd45 : - (_theResult____h594020[10] ? + (_theResult____h594017[10] ? 6'd46 : - (_theResult____h594020[9] ? + (_theResult____h594017[9] ? 6'd47 : - (_theResult____h594020[8] ? + (_theResult____h594017[8] ? 6'd48 : - (_theResult____h594020[7] ? + (_theResult____h594017[7] ? 6'd49 : - (_theResult____h594020[6] ? + (_theResult____h594017[6] ? 6'd50 : - (_theResult____h594020[5] ? + (_theResult____h594017[5] ? 6'd51 : - (_theResult____h594020[4] ? + (_theResult____h594017[4] ? 6'd52 : - (_theResult____h594020[3] ? + (_theResult____h594017[3] ? 6'd53 : - (_theResult____h594020[2] ? + (_theResult____h594017[2] ? 6'd54 : - (_theResult____h594020[1] ? + (_theResult____h594017[1] ? 6'd55 : - (_theResult____h594020[0] ? + (_theResult____h594017[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13072 = - (_theResult___fst_exp__h743790 == 11'd2047) ? + (_theResult___fst_exp__h743787 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19148,10 +19148,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13787 = - (_theResult___fst_exp__h821947 == 11'd2047) ? + (_theResult___fst_exp__h821944 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19159,10 +19159,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 : + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14055 = - (_theResult___fst_exp__h821947 == 11'd2047) ? + (_theResult___fst_exp__h821944 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19170,10 +19170,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 : + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14557 = - (_theResult___fst_exp__h782643 == 11'd2047) ? + (_theResult___fst_exp__h782640 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19181,10 +19181,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 : + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14824 = - (_theResult___fst_exp__h782643 == 11'd2047) ? + (_theResult___fst_exp__h782640 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19192,404 +19192,404 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 : + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459 = - (guard__h622142 == 2'b0 || + (guard__h622139 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h630235[56:34] : - _theResult___sfd__h630758 ; + sfdin__h630232[56:34] : + _theResult___sfd__h630755 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461 = - (guard__h622142 == 2'b0) ? - sfdin__h630235[56:34] : + (guard__h622139 == 2'b0) ? + sfdin__h630232[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h630758 : - sfdin__h630235[56:34]) ; + _theResult___sfd__h630755 : + sfdin__h630232[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209 = - (guard__h667889 == 2'b0 || + (guard__h667886 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h675988 : - _theResult___exp__h676504 ; + _theResult___fst_exp__h675985 : + _theResult___exp__h676501 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212 = - (guard__h667889 == 2'b0) ? - _theResult___fst_exp__h675988 : + (guard__h667886 == 2'b0) ? + _theResult___fst_exp__h675985 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h676504 : - _theResult___fst_exp__h675988) ; + _theResult___exp__h676501 : + _theResult___fst_exp__h675985) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856 = - (guard__h667889 == 2'b0 || + (guard__h667886 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h675982[56:34] : - _theResult___sfd__h676505 ; + sfdin__h675979[56:34] : + _theResult___sfd__h676502 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858 = - (guard__h667889 == 2'b0) ? - sfdin__h675982[56:34] : + (guard__h667886 == 2'b0) ? + sfdin__h675979[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h676505 : - sfdin__h675982[56:34]) ; + _theResult___sfd__h676502 : + sfdin__h675979[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415 = - (guard__h576391 == 2'b0 || + (guard__h576388 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h584492 : - _theResult___exp__h585008 ; + _theResult___fst_exp__h584489 : + _theResult___exp__h585005 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418 = - (guard__h576391 == 2'b0) ? - _theResult___fst_exp__h584492 : + (guard__h576388 == 2'b0) ? + _theResult___fst_exp__h584489 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h585008 : - _theResult___fst_exp__h584492) ; + _theResult___exp__h585005 : + _theResult___fst_exp__h584489) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062 = - (guard__h576391 == 2'b0 || + (guard__h576388 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h584486[56:34] : - _theResult___sfd__h585009 ; + sfdin__h584483[56:34] : + _theResult___sfd__h585006 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064 = - (guard__h576391 == 2'b0) ? - sfdin__h584486[56:34] : + (guard__h576388 == 2'b0) ? + sfdin__h584483[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h585009 : - sfdin__h584486[56:34]) ; + _theResult___sfd__h585006 : + sfdin__h584483[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812 = - (guard__h622142 == 2'b0 || + (guard__h622139 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h630241 : - _theResult___exp__h630757 ; + _theResult___fst_exp__h630238 : + _theResult___exp__h630754 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815 = - (guard__h622142 == 2'b0) ? - _theResult___fst_exp__h630241 : + (guard__h622139 == 2'b0) ? + _theResult___fst_exp__h630238 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h630757 : - _theResult___fst_exp__h630241) ; + _theResult___exp__h630754 : + _theResult___fst_exp__h630238) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189 = - (guard__h735564 == 2'b0 || + (guard__h735561 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h743790 : - _theResult___exp__h744519 ; + _theResult___fst_exp__h743787 : + _theResult___exp__h744516 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191 = - (guard__h735564 == 2'b0) ? - _theResult___fst_exp__h743790 : + (guard__h735561 == 2'b0) ? + _theResult___fst_exp__h743787 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h744519 : - _theResult___fst_exp__h743790) ; + _theResult___exp__h744516 : + _theResult___fst_exp__h743787) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273 = - (guard__h735564 == 2'b0 || + (guard__h735561 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h743784[56:5] : - _theResult___sfd__h744520 ; + sfdin__h743781[56:5] : + _theResult___sfd__h744517 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275 = - (guard__h735564 == 2'b0) ? - sfdin__h743784[56:5] : + (guard__h735561 == 2'b0) ? + sfdin__h743781[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h744520 : - sfdin__h743784[56:5]) ; + _theResult___sfd__h744517 : + sfdin__h743781[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899 = - (guard__h813721 == 2'b0 || + (guard__h813718 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h821947 : - _theResult___exp__h822676 ; + _theResult___fst_exp__h821944 : + _theResult___exp__h822673 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901 = - (guard__h813721 == 2'b0) ? - _theResult___fst_exp__h821947 : + (guard__h813718 == 2'b0) ? + _theResult___fst_exp__h821944 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h822676 : - _theResult___fst_exp__h821947) ; + _theResult___exp__h822673 : + _theResult___fst_exp__h821944) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982 = - (guard__h813721 == 2'b0 || + (guard__h813718 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h821941[56:5] : - _theResult___sfd__h822677 ; + sfdin__h821938[56:5] : + _theResult___sfd__h822674 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984 = - (guard__h813721 == 2'b0) ? - sfdin__h821941[56:5] : + (guard__h813718 == 2'b0) ? + sfdin__h821938[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h822677 : - sfdin__h821941[56:5]) ; + _theResult___sfd__h822674 : + sfdin__h821938[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669 = - (guard__h774417 == 2'b0 || + (guard__h774414 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h782643 : - _theResult___exp__h783372 ; + _theResult___fst_exp__h782640 : + _theResult___exp__h783369 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671 = - (guard__h774417 == 2'b0) ? - _theResult___fst_exp__h782643 : + (guard__h774414 == 2'b0) ? + _theResult___fst_exp__h782640 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h783372 : - _theResult___fst_exp__h782643) ; + _theResult___exp__h783369 : + _theResult___fst_exp__h782640) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752 = - (guard__h774417 == 2'b0 || + (guard__h774414 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h782637[56:5] : - _theResult___sfd__h783373 ; + sfdin__h782634[56:5] : + _theResult___sfd__h783370 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754 = - (guard__h774417 == 2'b0) ? - sfdin__h782637[56:5] : + (guard__h774414 == 2'b0) ? + sfdin__h782634[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h783373 : - sfdin__h782637[56:5]) ; + _theResult___sfd__h783370 : + sfdin__h782634[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359 = - (guard__h639779 == 2'b0 || + (guard__h639776 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h648007 : - _theResult___exp__h648523 ; + _theResult___fst_exp__h648004 : + _theResult___exp__h648520 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361 = - (guard__h639779 == 2'b0) ? - _theResult___fst_exp__h648007 : + (guard__h639776 == 2'b0) ? + _theResult___fst_exp__h648004 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h648523 : - _theResult___fst_exp__h648007) ; + _theResult___exp__h648520 : + _theResult___fst_exp__h648004) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 = - (guard__h639779 == 2'b0 || + (guard__h639776 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h648001[56:34] : - _theResult___sfd__h648524 ; + sfdin__h647998[56:34] : + _theResult___sfd__h648521 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 = - (guard__h639779 == 2'b0) ? - sfdin__h648001[56:34] : + (guard__h639776 == 2'b0) ? + sfdin__h647998[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h648524 : - sfdin__h648001[56:34]) ; + _theResult___sfd__h648521 : + sfdin__h647998[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756 = - (guard__h685526 == 2'b0 || + (guard__h685523 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h693754 : - _theResult___exp__h694270 ; + _theResult___fst_exp__h693751 : + _theResult___exp__h694267 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758 = - (guard__h685526 == 2'b0) ? - _theResult___fst_exp__h693754 : + (guard__h685523 == 2'b0) ? + _theResult___fst_exp__h693751 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h694270 : - _theResult___fst_exp__h693754) ; + _theResult___exp__h694267 : + _theResult___fst_exp__h693751) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902 = - (guard__h685526 == 2'b0 || + (guard__h685523 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h693748[56:34] : - _theResult___sfd__h694271 ; + sfdin__h693745[56:34] : + _theResult___sfd__h694268 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904 = - (guard__h685526 == 2'b0) ? - sfdin__h693748[56:34] : + (guard__h685523 == 2'b0) ? + sfdin__h693745[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h694271 : - sfdin__h693748[56:34]) ; + _theResult___sfd__h694268 : + sfdin__h693745[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962 = - (guard__h594030 == 2'b0 || + (guard__h594027 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h602258 : - _theResult___exp__h602774 ; + _theResult___fst_exp__h602255 : + _theResult___exp__h602771 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964 = - (guard__h594030 == 2'b0) ? - _theResult___fst_exp__h602258 : + (guard__h594027 == 2'b0) ? + _theResult___fst_exp__h602255 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h602774 : - _theResult___fst_exp__h602258) ; + _theResult___exp__h602771 : + _theResult___fst_exp__h602255) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108 = - (guard__h594030 == 2'b0 || + (guard__h594027 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h602252[56:34] : - _theResult___sfd__h602775 ; + sfdin__h602249[56:34] : + _theResult___sfd__h602772 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110 = - (guard__h594030 == 2'b0) ? - sfdin__h602252[56:34] : + (guard__h594027 == 2'b0) ? + sfdin__h602249[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h602775 : - sfdin__h602252[56:34]) ; + _theResult___sfd__h602772 : + sfdin__h602249[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146 = - (guard__h726252 == 2'b0 || + (guard__h726249 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h734213 : - _theResult___exp__h734868 ; + _theResult___fst_exp__h734210 : + _theResult___exp__h734865 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148 = - (guard__h726252 == 2'b0) ? - _theResult___fst_exp__h734213 : + (guard__h726249 == 2'b0) ? + _theResult___fst_exp__h734210 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h734868 : - _theResult___fst_exp__h734213) ; + _theResult___exp__h734865 : + _theResult___fst_exp__h734210) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220 = - (guard__h744633 == 2'b0 || + (guard__h744630 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h752623 : - _theResult___exp__h753303 ; + _theResult___fst_exp__h752620 : + _theResult___exp__h753300 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222 = - (guard__h744633 == 2'b0) ? - _theResult___fst_exp__h752623 : + (guard__h744630 == 2'b0) ? + _theResult___fst_exp__h752620 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h753303 : - _theResult___fst_exp__h752623) ; + _theResult___exp__h753300 : + _theResult___fst_exp__h752620) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246 = - (guard__h726252 == 2'b0 || + (guard__h726249 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h734164[56:5] : - _theResult___sfd__h734869 ; + _theResult___snd__h734161[56:5] : + _theResult___sfd__h734866 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248 = - (guard__h726252 == 2'b0) ? - _theResult___snd__h734164[56:5] : + (guard__h726249 == 2'b0) ? + _theResult___snd__h734161[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h734869 : - _theResult___snd__h734164[56:5]) ; + _theResult___sfd__h734866 : + _theResult___snd__h734161[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292 = - (guard__h744633 == 2'b0 || + (guard__h744630 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h752569[56:5] : - _theResult___sfd__h753304 ; + _theResult___snd__h752566[56:5] : + _theResult___sfd__h753301 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294 = - (guard__h744633 == 2'b0) ? - _theResult___snd__h752569[56:5] : + (guard__h744630 == 2'b0) ? + _theResult___snd__h752566[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h753304 : - _theResult___snd__h752569[56:5]) ; + _theResult___sfd__h753301 : + _theResult___snd__h752566[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861 = - (guard__h804409 == 2'b0 || + (guard__h804406 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h812370 : - _theResult___exp__h813025 ; + _theResult___fst_exp__h812367 : + _theResult___exp__h813022 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863 = - (guard__h804409 == 2'b0) ? - _theResult___fst_exp__h812370 : + (guard__h804406 == 2'b0) ? + _theResult___fst_exp__h812367 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h813025 : - _theResult___fst_exp__h812370) ; + _theResult___exp__h813022 : + _theResult___fst_exp__h812367) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930 = - (guard__h822790 == 2'b0 || + (guard__h822787 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h830780 : - _theResult___exp__h831460 ; + _theResult___fst_exp__h830777 : + _theResult___exp__h831457 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932 = - (guard__h822790 == 2'b0) ? - _theResult___fst_exp__h830780 : + (guard__h822787 == 2'b0) ? + _theResult___fst_exp__h830777 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h831460 : - _theResult___fst_exp__h830780) ; + _theResult___exp__h831457 : + _theResult___fst_exp__h830777) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956 = - (guard__h804409 == 2'b0 || + (guard__h804406 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h812321[56:5] : - _theResult___sfd__h813026 ; + _theResult___snd__h812318[56:5] : + _theResult___sfd__h813023 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958 = - (guard__h804409 == 2'b0) ? - _theResult___snd__h812321[56:5] : + (guard__h804406 == 2'b0) ? + _theResult___snd__h812318[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h813026 : - _theResult___snd__h812321[56:5]) ; + _theResult___sfd__h813023 : + _theResult___snd__h812318[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001 = - (guard__h822790 == 2'b0 || + (guard__h822787 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h830726[56:5] : - _theResult___sfd__h831461 ; + _theResult___snd__h830723[56:5] : + _theResult___sfd__h831458 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003 = - (guard__h822790 == 2'b0) ? - _theResult___snd__h830726[56:5] : + (guard__h822787 == 2'b0) ? + _theResult___snd__h830723[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h831461 : - _theResult___snd__h830726[56:5]) ; + _theResult___sfd__h831458 : + _theResult___snd__h830723[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631 = - (guard__h765105 == 2'b0 || + (guard__h765102 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h773066 : - _theResult___exp__h773721 ; + _theResult___fst_exp__h773063 : + _theResult___exp__h773718 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633 = - (guard__h765105 == 2'b0) ? - _theResult___fst_exp__h773066 : + (guard__h765102 == 2'b0) ? + _theResult___fst_exp__h773063 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h773721 : - _theResult___fst_exp__h773066) ; + _theResult___exp__h773718 : + _theResult___fst_exp__h773063) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700 = - (guard__h783486 == 2'b0 || + (guard__h783483 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h791476 : - _theResult___exp__h792156 ; + _theResult___fst_exp__h791473 : + _theResult___exp__h792153 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702 = - (guard__h783486 == 2'b0) ? - _theResult___fst_exp__h791476 : + (guard__h783483 == 2'b0) ? + _theResult___fst_exp__h791473 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h792156 : - _theResult___fst_exp__h791476) ; + _theResult___exp__h792153 : + _theResult___fst_exp__h791473) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726 = - (guard__h765105 == 2'b0 || + (guard__h765102 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h773017[56:5] : - _theResult___sfd__h773722 ; + _theResult___snd__h773014[56:5] : + _theResult___sfd__h773719 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728 = - (guard__h765105 == 2'b0) ? - _theResult___snd__h773017[56:5] : + (guard__h765102 == 2'b0) ? + _theResult___snd__h773014[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h773722 : - _theResult___snd__h773017[56:5]) ; + _theResult___sfd__h773719 : + _theResult___snd__h773014[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771 = - (guard__h783486 == 2'b0 || + (guard__h783483 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h791422[56:5] : - _theResult___sfd__h792157 ; + _theResult___snd__h791419[56:5] : + _theResult___sfd__h792154 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773 = - (guard__h783486 == 2'b0) ? - _theResult___snd__h791422[56:5] : + (guard__h783483 == 2'b0) ? + _theResult___snd__h791419[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h792157 : - _theResult___snd__h791422[56:5]) ; + _theResult___sfd__h792154 : + _theResult___snd__h791419[56:5]) ; assign IF_IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_ETC___d20711 = (IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[0] || IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[1] || @@ -19801,139 +19801,139 @@ module mkCore(CLK, IF_checkForException_0436_BITS_3_TO_0_0689_EQ__ETC___d20709 == 4'd9 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034 = - (guard__h630849 == 2'b0 || + (guard__h630846 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h638897 : - _theResult___exp__h639339 ; + _theResult___fst_exp__h638894 : + _theResult___exp__h639336 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036 = - (guard__h630849 == 2'b0) ? - _theResult___fst_exp__h638897 : + (guard__h630846 == 2'b0) ? + _theResult___fst_exp__h638894 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h639339 : - _theResult___fst_exp__h638897) ; + _theResult___exp__h639336 : + _theResult___fst_exp__h638894) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428 = - (guard__h648615 == 2'b0 || + (guard__h648612 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h656692 : - _theResult___exp__h657159 ; + _theResult___fst_exp__h656689 : + _theResult___exp__h657156 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430 = - (guard__h648615 == 2'b0) ? - _theResult___fst_exp__h656692 : + (guard__h648612 == 2'b0) ? + _theResult___fst_exp__h656689 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h657159 : - _theResult___fst_exp__h656692) ; + _theResult___exp__h657156 : + _theResult___fst_exp__h656689) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478 = - (guard__h630849 == 2'b0 || + (guard__h630846 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h638848[56:34] : - _theResult___sfd__h639340 ; + _theResult___snd__h638845[56:34] : + _theResult___sfd__h639337 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480 = - (guard__h630849 == 2'b0) ? - _theResult___snd__h638848[56:34] : + (guard__h630846 == 2'b0) ? + _theResult___snd__h638845[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h639340 : - _theResult___snd__h638848[56:34]) ; + _theResult___sfd__h639337 : + _theResult___snd__h638845[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524 = - (guard__h648615 == 2'b0 || + (guard__h648612 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h656638[56:34] : - _theResult___sfd__h657160 ; + _theResult___snd__h656635[56:34] : + _theResult___sfd__h657157 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526 = - (guard__h648615 == 2'b0) ? - _theResult___snd__h656638[56:34] : + (guard__h648612 == 2'b0) ? + _theResult___snd__h656635[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h657160 : - _theResult___snd__h656638[56:34]) ; + _theResult___sfd__h657157 : + _theResult___snd__h656635[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431 = - (guard__h676596 == 2'b0 || + (guard__h676593 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h684644 : - _theResult___exp__h685086 ; + _theResult___fst_exp__h684641 : + _theResult___exp__h685083 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433 = - (guard__h676596 == 2'b0) ? - _theResult___fst_exp__h684644 : + (guard__h676593 == 2'b0) ? + _theResult___fst_exp__h684641 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h685086 : - _theResult___fst_exp__h684644) ; + _theResult___exp__h685083 : + _theResult___fst_exp__h684641) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825 = - (guard__h694362 == 2'b0 || + (guard__h694359 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h702439 : - _theResult___exp__h702906 ; + _theResult___fst_exp__h702436 : + _theResult___exp__h702903 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827 = - (guard__h694362 == 2'b0) ? - _theResult___fst_exp__h702439 : + (guard__h694359 == 2'b0) ? + _theResult___fst_exp__h702436 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h702906 : - _theResult___fst_exp__h702439) ; + _theResult___exp__h702903 : + _theResult___fst_exp__h702436) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875 = - (guard__h676596 == 2'b0 || + (guard__h676593 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h684595[56:34] : - _theResult___sfd__h685087 ; + _theResult___snd__h684592[56:34] : + _theResult___sfd__h685084 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877 = - (guard__h676596 == 2'b0) ? - _theResult___snd__h684595[56:34] : + (guard__h676593 == 2'b0) ? + _theResult___snd__h684592[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h685087 : - _theResult___snd__h684595[56:34]) ; + _theResult___sfd__h685084 : + _theResult___snd__h684592[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921 = - (guard__h694362 == 2'b0 || + (guard__h694359 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h702385[56:34] : - _theResult___sfd__h702907 ; + _theResult___snd__h702382[56:34] : + _theResult___sfd__h702904 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923 = - (guard__h694362 == 2'b0) ? - _theResult___snd__h702385[56:34] : + (guard__h694359 == 2'b0) ? + _theResult___snd__h702382[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h702907 : - _theResult___snd__h702385[56:34]) ; + _theResult___sfd__h702904 : + _theResult___snd__h702382[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637 = - (guard__h585100 == 2'b0 || + (guard__h585097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h593148 : - _theResult___exp__h593590 ; + _theResult___fst_exp__h593145 : + _theResult___exp__h593587 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639 = - (guard__h585100 == 2'b0) ? - _theResult___fst_exp__h593148 : + (guard__h585097 == 2'b0) ? + _theResult___fst_exp__h593145 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h593590 : - _theResult___fst_exp__h593148) ; + _theResult___exp__h593587 : + _theResult___fst_exp__h593145) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031 = - (guard__h602866 == 2'b0 || + (guard__h602863 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h610943 : - _theResult___exp__h611410 ; + _theResult___fst_exp__h610940 : + _theResult___exp__h611407 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033 = - (guard__h602866 == 2'b0) ? - _theResult___fst_exp__h610943 : + (guard__h602863 == 2'b0) ? + _theResult___fst_exp__h610940 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h611410 : - _theResult___fst_exp__h610943) ; + _theResult___exp__h611407 : + _theResult___fst_exp__h610940) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081 = - (guard__h585100 == 2'b0 || + (guard__h585097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h593099[56:34] : - _theResult___sfd__h593591 ; + _theResult___snd__h593096[56:34] : + _theResult___sfd__h593588 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083 = - (guard__h585100 == 2'b0) ? - _theResult___snd__h593099[56:34] : + (guard__h585097 == 2'b0) ? + _theResult___snd__h593096[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h593591 : - _theResult___snd__h593099[56:34]) ; + _theResult___sfd__h593588 : + _theResult___snd__h593096[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127 = - (guard__h602866 == 2'b0 || + (guard__h602863 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h610889[56:34] : - _theResult___sfd__h611411 ; + _theResult___snd__h610886[56:34] : + _theResult___sfd__h611408 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129 = - (guard__h602866 == 2'b0) ? - _theResult___snd__h610889[56:34] : + (guard__h602863 == 2'b0) ? + _theResult___snd__h610886[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h611411 : - _theResult___snd__h610889[56:34]) ; + _theResult___sfd__h611408 : + _theResult___snd__h610886[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13118 = - (_theResult___fst_exp__h752623 == 11'd2047) ? + (_theResult___fst_exp__h752620 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19941,10 +19941,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 : + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13833 = - (_theResult___fst_exp__h830780 == 11'd2047) ? + (_theResult___fst_exp__h830777 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19952,10 +19952,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 : + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14040 = - (_theResult___fst_exp__h812370 == 11'd2047) ? + (_theResult___fst_exp__h812367 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19963,10 +19963,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 : + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14067 = - (_theResult___fst_exp__h830780 == 11'd2047) ? + (_theResult___fst_exp__h830777 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19974,10 +19974,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 : + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14603 = - (_theResult___fst_exp__h791476 == 11'd2047) ? + (_theResult___fst_exp__h791473 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19985,10 +19985,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 : + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14809 = - (_theResult___fst_exp__h773066 == 11'd2047) ? + (_theResult___fst_exp__h773063 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19996,10 +19996,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 : + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14836 = - (_theResult___fst_exp__h791476 == 11'd2047) ? + (_theResult___fst_exp__h791473 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20007,14 +20007,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 : + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213) ; assign IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116 = - (_theResult____h917995 == 16'd0 && + (_theResult____h917990 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h918566 : - _theResult____h917995 ; + enabled_ints__h918561 : + _theResult____h917990 ; assign IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20458 = IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[0] || IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[1] || @@ -20459,148 +20459,148 @@ module mkCore(CLK, 5'd0 : IF_IF_coreFix_aluExe_1_exeToFinQ_first__7660_B_ETC___d17805 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 = - ((f1_exp__h714825 == 8'd0) ? - (f1_sfd__h714826[22] ? + ((f1_exp__h714822 == 8'd0) ? + (f1_sfd__h714823[22] ? 6'd2 : - (f1_sfd__h714826[21] ? + (f1_sfd__h714823[21] ? 6'd3 : - (f1_sfd__h714826[20] ? + (f1_sfd__h714823[20] ? 6'd4 : - (f1_sfd__h714826[19] ? + (f1_sfd__h714823[19] ? 6'd5 : - (f1_sfd__h714826[18] ? + (f1_sfd__h714823[18] ? 6'd6 : - (f1_sfd__h714826[17] ? + (f1_sfd__h714823[17] ? 6'd7 : - (f1_sfd__h714826[16] ? + (f1_sfd__h714823[16] ? 6'd8 : - (f1_sfd__h714826[15] ? + (f1_sfd__h714823[15] ? 6'd9 : - (f1_sfd__h714826[14] ? + (f1_sfd__h714823[14] ? 6'd10 : - (f1_sfd__h714826[13] ? + (f1_sfd__h714823[13] ? 6'd11 : - (f1_sfd__h714826[12] ? + (f1_sfd__h714823[12] ? 6'd12 : - (f1_sfd__h714826[11] ? + (f1_sfd__h714823[11] ? 6'd13 : - (f1_sfd__h714826[10] ? + (f1_sfd__h714823[10] ? 6'd14 : - (f1_sfd__h714826[9] ? + (f1_sfd__h714823[9] ? 6'd15 : - (f1_sfd__h714826[8] ? + (f1_sfd__h714823[8] ? 6'd16 : - (f1_sfd__h714826[7] ? + (f1_sfd__h714823[7] ? 6'd17 : - (f1_sfd__h714826[6] ? + (f1_sfd__h714823[6] ? 6'd18 : - (f1_sfd__h714826[5] ? + (f1_sfd__h714823[5] ? 6'd19 : - (f1_sfd__h714826[4] ? + (f1_sfd__h714823[4] ? 6'd20 : - (f1_sfd__h714826[3] ? + (f1_sfd__h714823[3] ? 6'd21 : - (f1_sfd__h714826[2] ? + (f1_sfd__h714823[2] ? 6'd22 : - (f1_sfd__h714826[1] ? + (f1_sfd__h714823[1] ? 6'd23 : - (f1_sfd__h714826[0] ? + (f1_sfd__h714823[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13122 = - (f1_exp__h714825 == 8'd255 && f1_sfd__h714826 != 23'd0 || - (f1_exp__h714825 == 8'd255 || f1_exp__h714825 == 8'd0) && - f1_sfd__h714826 == 23'd0) ? + (f1_exp__h714822 == 8'd255 && f1_sfd__h714823 != 23'd0 || + (f1_exp__h714822 == 8'd255 || f1_exp__h714822 == 8'd0) && + f1_sfd__h714823 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h714825 == 8'd0) ? + ((f1_exp__h714822 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12777 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13120) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305 = - (f1_exp__h714825 == 8'd255 && f1_sfd__h714826 != 23'd0) ? - _theResult___snd_fst_sfd__h715141 : - _theResult___fst_sfd__h753422 ; + (f1_exp__h714822 == 8'd255 && f1_sfd__h714823 != 23'd0) ? + _theResult___snd_fst_sfd__h715138 : + _theResult___fst_sfd__h753419 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13306 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13122, - (f1_exp__h714825 == 8'd255) ? + (f1_exp__h714822 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h753418, + _theResult___fst_exp__h753415, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 = - ((f3_exp__h793123 == 8'd0) ? - (f3_sfd__h793124[22] ? + ((f3_exp__h793120 == 8'd0) ? + (f3_sfd__h793121[22] ? 6'd2 : - (f3_sfd__h793124[21] ? + (f3_sfd__h793121[21] ? 6'd3 : - (f3_sfd__h793124[20] ? + (f3_sfd__h793121[20] ? 6'd4 : - (f3_sfd__h793124[19] ? + (f3_sfd__h793121[19] ? 6'd5 : - (f3_sfd__h793124[18] ? + (f3_sfd__h793121[18] ? 6'd6 : - (f3_sfd__h793124[17] ? + (f3_sfd__h793121[17] ? 6'd7 : - (f3_sfd__h793124[16] ? + (f3_sfd__h793121[16] ? 6'd8 : - (f3_sfd__h793124[15] ? + (f3_sfd__h793121[15] ? 6'd9 : - (f3_sfd__h793124[14] ? + (f3_sfd__h793121[14] ? 6'd10 : - (f3_sfd__h793124[13] ? + (f3_sfd__h793121[13] ? 6'd11 : - (f3_sfd__h793124[12] ? + (f3_sfd__h793121[12] ? 6'd12 : - (f3_sfd__h793124[11] ? + (f3_sfd__h793121[11] ? 6'd13 : - (f3_sfd__h793124[10] ? + (f3_sfd__h793121[10] ? 6'd14 : - (f3_sfd__h793124[9] ? + (f3_sfd__h793121[9] ? 6'd15 : - (f3_sfd__h793124[8] ? + (f3_sfd__h793121[8] ? 6'd16 : - (f3_sfd__h793124[7] ? + (f3_sfd__h793121[7] ? 6'd17 : - (f3_sfd__h793124[6] ? + (f3_sfd__h793121[6] ? 6'd18 : - (f3_sfd__h793124[5] ? + (f3_sfd__h793121[5] ? 6'd19 : - (f3_sfd__h793124[4] ? + (f3_sfd__h793121[4] ? 6'd20 : - (f3_sfd__h793124[3] ? + (f3_sfd__h793121[3] ? 6'd21 : - (f3_sfd__h793124[2] ? + (f3_sfd__h793121[2] ? 6'd22 : - (f3_sfd__h793124[1] ? + (f3_sfd__h793121[1] ? 6'd23 : - (f3_sfd__h793124[0] ? + (f3_sfd__h793121[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13837 = - (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0 || - (f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && - f3_sfd__h793124 == 23'd0) ? + (f3_exp__h793120 == 8'd255 && f3_sfd__h793121 != 23'd0 || + (f3_exp__h793120 == 8'd255 || f3_exp__h793120 == 8'd0) && + f3_sfd__h793121 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h793123 == 8'd0) ? + ((f3_exp__h793120 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13492 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13835) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014 = - (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0) ? - _theResult___snd_fst_sfd__h793439 : - _theResult___fst_sfd__h831579 ; + (f3_exp__h793120 == 8'd255 && f3_sfd__h793121 != 23'd0) ? + _theResult___snd_fst_sfd__h793436 : + _theResult___fst_sfd__h831576 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015 = - { (f3_exp__h793123 == 8'd255) ? + { (f3_exp__h793120 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h831575, + _theResult___fst_exp__h831572, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14070 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -20610,85 +20610,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14042) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14069 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14071 = - (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0 || - (f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && - f3_sfd__h793124 == 23'd0) ? + (f3_exp__h793120 == 8'd255 && f3_sfd__h793121 != 23'd0 || + (f3_exp__h793120 == 8'd255 || f3_exp__h793120 == 8'd0) && + f3_sfd__h793121 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14070 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 = - ((f2_exp__h753819 == 8'd0) ? - (f2_sfd__h753820[22] ? + ((f2_exp__h753816 == 8'd0) ? + (f2_sfd__h753817[22] ? 6'd2 : - (f2_sfd__h753820[21] ? + (f2_sfd__h753817[21] ? 6'd3 : - (f2_sfd__h753820[20] ? + (f2_sfd__h753817[20] ? 6'd4 : - (f2_sfd__h753820[19] ? + (f2_sfd__h753817[19] ? 6'd5 : - (f2_sfd__h753820[18] ? + (f2_sfd__h753817[18] ? 6'd6 : - (f2_sfd__h753820[17] ? + (f2_sfd__h753817[17] ? 6'd7 : - (f2_sfd__h753820[16] ? + (f2_sfd__h753817[16] ? 6'd8 : - (f2_sfd__h753820[15] ? + (f2_sfd__h753817[15] ? 6'd9 : - (f2_sfd__h753820[14] ? + (f2_sfd__h753817[14] ? 6'd10 : - (f2_sfd__h753820[13] ? + (f2_sfd__h753817[13] ? 6'd11 : - (f2_sfd__h753820[12] ? + (f2_sfd__h753817[12] ? 6'd12 : - (f2_sfd__h753820[11] ? + (f2_sfd__h753817[11] ? 6'd13 : - (f2_sfd__h753820[10] ? + (f2_sfd__h753817[10] ? 6'd14 : - (f2_sfd__h753820[9] ? + (f2_sfd__h753817[9] ? 6'd15 : - (f2_sfd__h753820[8] ? + (f2_sfd__h753817[8] ? 6'd16 : - (f2_sfd__h753820[7] ? + (f2_sfd__h753817[7] ? 6'd17 : - (f2_sfd__h753820[6] ? + (f2_sfd__h753817[6] ? 6'd18 : - (f2_sfd__h753820[5] ? + (f2_sfd__h753817[5] ? 6'd19 : - (f2_sfd__h753820[4] ? + (f2_sfd__h753817[4] ? 6'd20 : - (f2_sfd__h753820[3] ? + (f2_sfd__h753817[3] ? 6'd21 : - (f2_sfd__h753820[2] ? + (f2_sfd__h753817[2] ? 6'd22 : - (f2_sfd__h753820[1] ? + (f2_sfd__h753817[1] ? 6'd23 : - (f2_sfd__h753820[0] ? + (f2_sfd__h753817[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14607 = - (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0 || - (f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && - f2_sfd__h753820 == 23'd0) ? + (f2_exp__h753816 == 8'd255 && f2_sfd__h753817 != 23'd0 || + (f2_exp__h753816 == 8'd255 || f2_exp__h753816 == 8'd0) && + f2_sfd__h753817 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h753819 == 8'd0) ? + ((f2_exp__h753816 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14262 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14605) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784 = - (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0) ? - _theResult___snd_fst_sfd__h754135 : - _theResult___fst_sfd__h792275 ; + (f2_exp__h753816 == 8'd255 && f2_sfd__h753817 != 23'd0) ? + _theResult___snd_fst_sfd__h754132 : + _theResult___fst_sfd__h792272 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785 = - { (f2_exp__h753819 == 8'd255) ? + { (f2_exp__h753816 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h792271, + _theResult___fst_exp__h792268, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14839 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20698,15 +20698,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14811) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14838 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14840 = - (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0 || - (f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && - f2_sfd__h753820 == 23'd0) ? + (f2_exp__h753816 == 8'd255 && f2_sfd__h753817 != 23'd0 || + (f2_exp__h753816 == 8'd255 || f2_exp__h753816 == 8'd0) && + f2_sfd__h753817 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14839 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14895 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[4] : @@ -20714,7 +20714,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14936 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[4] : @@ -20722,7 +20722,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14980 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[4] : @@ -20730,7 +20730,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14995 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[3] : @@ -20738,7 +20738,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15005 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[3] : @@ -20746,7 +20746,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15016 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[3] : @@ -20754,70 +20754,70 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15035 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15033 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15049 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15047 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15064 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15062 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15081 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15079 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15093 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15091 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15106 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15104 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15123 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15121 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15135 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15133 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15148 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15146 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231 = - _theResult_____2__h515296 == v__h514752 ; + _theResult_____2__h515292 == v__h514748 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7239 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 || @@ -20832,7 +20832,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7222 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322 = - _theResult_____2__h526073 == v__h516772 ; + _theResult_____2__h526069 == v__h516768 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7331 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 || @@ -20861,9 +20861,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h521603 } ; + x__h521599 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482 = - _theResult_____2__h533166 == v__h532491 ; + _theResult_____2__h533162 == v__h532487 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7490 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 || @@ -20878,7 +20878,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7475 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566 = - _theResult_____2__h543801 == v__h534940 ; + _theResult_____2__h543797 == v__h534936 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7574 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 || @@ -21275,7 +21275,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852 = - _theResult_____2__h561413 == v__h559739 ; + _theResult_____2__h561409 == v__h559735 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7860 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 || @@ -21290,7 +21290,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7846 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770 = - _theResult_____2__h557634 == v__h555960 ; + _theResult_____2__h557630 == v__h555956 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7778 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 || @@ -21308,12 +21308,12 @@ module mkCore(CLK, (csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h998356[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h998359 } : - { x__h998356[11:3], - x__h998377[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h998359[13:3], - x__h998377[2:0] } ; + { x__h998351[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h998354 } : + { x__h998351[11:3], + x__h998372[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h998354[13:3], + x__h998372[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0049_BITS__ETC___d21013 = IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d21004 ? !csrf_rg_dcsr[2] && @@ -21554,27 +21554,27 @@ module mkCore(CLK, 4'd0 : IF_IF_renameStage_rg_m_halt_req_0076_BIT_4_007_ETC___d20766 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 = - { INV_x83367_BITS_108_TO_90__q33[0] ? x__h183487 : 6'd0, - x__h183647, - x__h183667 } ; + { INV_x83366_BITS_108_TO_90__q33[0] ? x__h183486 : 6'd0, + x__h183646, + x__h183666 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 = - { INV_x99219_BITS_108_TO_90__q35[0] ? x__h202238 : 6'd0, - x__h202398, - x__h202418 } ; + { INV_x99218_BITS_108_TO_90__q35[0] ? x__h202237 : 6'd0, + x__h202397, + x__h202417 } ; assign IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h992421 : + x__h992416 : 6'd0 ; assign IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22432 = - x__h992601[13:11] < repBound__h995071 ; + x__h992596[13:11] < repBound__h995066 ; assign IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22434 = - pc_addrBits__h992212[13:11] < repBound__h995071 ; + pc_addrBits__h992207[13:11] < repBound__h995066 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19571 = - tb__h904585 < repBound__h904588 ; + tb__h904581 < repBound__h904584 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19572 = - x__h904527[13:11] < repBound__h904588 ; + x__h904523[13:11] < repBound__h904584 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19574 = - cr_addrBits__h904120[13:11] < repBound__h904588 ; + cr_addrBits__h904116[13:11] < repBound__h904584 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19584 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19574, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19571 == @@ -21592,11 +21592,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19635 = - tb__h905133 < repBound__h905136 ; + tb__h905129 < repBound__h905132 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19636 = - x__h905075[13:11] < repBound__h905136 ; + x__h905071[13:11] < repBound__h905132 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19638 = - cr_addrBits__h904668[13:11] < repBound__h905136 ; + cr_addrBits__h904664[13:11] < repBound__h905132 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19648 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19638, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19635 == @@ -21614,11 +21614,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17492 = - tb__h865963 < repBound__h865966 ; + tb__h865960 < repBound__h865963 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17493 = - x__h865905[13:11] < repBound__h865966 ; + x__h865902[13:11] < repBound__h865963 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17495 = - cr_addrBits__h865498[13:11] < repBound__h865966 ; + cr_addrBits__h865495[13:11] < repBound__h865963 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17505 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17495, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17492 == @@ -21636,11 +21636,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17556 = - tb__h866511 < repBound__h866514 ; + tb__h866508 < repBound__h866511 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17557 = - x__h866453[13:11] < repBound__h866514 ; + x__h866450[13:11] < repBound__h866511 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17559 = - cr_addrBits__h866046[13:11] < repBound__h866514 ; + cr_addrBits__h866043[13:11] < repBound__h866511 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17569 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17559, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17556 == @@ -21659,26 +21659,26 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? - x__h216804 : + x__h216803 : 6'd0, - x__h216964, - x__h216984 } ; + x__h216963, + x__h216983 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127310 : + x__h127309 : 6'd0, - x__h127470, - x__h127490 } ; + x__h127469, + x__h127489 } ; assign IF_INV_mmio_dataRespQ_data_0_389_BITS_108_TO_9_ETC___d1433 = { INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? - x__h140226 : + x__h140225 : 6'd0, - x__h140386, - x__h140406 } ; + x__h140385, + x__h140405 } ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12777 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 || - _theResult___fst_exp__h734213 == 11'd2047) ? + _theResult___fst_exp__h734210 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21686,12 +21686,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13492 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 || - _theResult___fst_exp__h812370 == 11'd2047) ? + _theResult___fst_exp__h812367 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21699,12 +21699,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 : + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14262 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 || - _theResult___fst_exp__h773066 == 11'd2047) ? + _theResult___fst_exp__h773063 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21712,7 +21712,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 : + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3__ETC___d20687 = IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[0] ? @@ -23436,48 +23436,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15033 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[2] : - _theResult___fst_exp__h753406 == 11'd2047 && - _theResult___fst_sfd__h753407 == 52'd0 ; + _theResult___fst_exp__h753403 == 11'd2047 && + _theResult___fst_sfd__h753404 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15047 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[2] : - _theResult___fst_exp__h792259 == 11'd2047 && - _theResult___fst_sfd__h792260 == 52'd0 ; + _theResult___fst_exp__h792256 == 11'd2047 && + _theResult___fst_sfd__h792257 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15062 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[2] : - _theResult___fst_exp__h831563 == 11'd2047 && - _theResult___fst_sfd__h831564 == 52'd0 ; + _theResult___fst_exp__h831560 == 11'd2047 && + _theResult___fst_sfd__h831561 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15079 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[1] : - _theResult___fst_exp__h752623 == 11'd0 && - guard__h744633 != 2'b0 ; + _theResult___fst_exp__h752620 == 11'd0 && + guard__h744630 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15091 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[1] : - _theResult___fst_exp__h791476 == 11'd0 && - guard__h783486 != 2'b0 ; + _theResult___fst_exp__h791473 == 11'd0 && + guard__h783483 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15104 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[1] : - _theResult___fst_exp__h830780 == 11'd0 && - guard__h822790 != 2'b0 ; + _theResult___fst_exp__h830777 == 11'd0 && + guard__h822787 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15121 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[0] : - _theResult___fst_exp__h752623 != 11'd2047 && - guard__h744633 != 2'b0 ; + _theResult___fst_exp__h752620 != 11'd2047 && + guard__h744630 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15133 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[0] : - _theResult___fst_exp__h791476 != 11'd2047 && - guard__h783486 != 2'b0 ; + _theResult___fst_exp__h791473 != 11'd2047 && + guard__h783483 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15146 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[0] : - _theResult___fst_exp__h830780 != 11'd2047 && - guard__h822790 != 2'b0 ; + _theResult___fst_exp__h830777 != 11'd2047 && + guard__h822787 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] == 8'd0) ? @@ -23487,35 +23487,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10601 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - ((_theResult___fst_exp__h648007 == 8'd255) ? + ((_theResult___fst_exp__h648004 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586) : - ((_theResult___fst_exp__h656692 == 8'd255) ? + ((_theResult___fst_exp__h656689 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10638 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - ((_theResult___fst_exp__h648007 == 8'd255) ? + ((_theResult___fst_exp__h648004 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629) : - ((_theResult___fst_exp__h656692 == 8'd255) ? + ((_theResult___fst_exp__h656689 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10734 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[2] : - _theResult___fst_exp__h657240 == 8'd255 && - _theResult___fst_sfd__h657241 == 23'd0 ; + _theResult___fst_exp__h657237 == 8'd255 && + _theResult___fst_sfd__h657238 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10747 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[1] : - _theResult___fst_exp__h656692 == 8'd0 && - guard__h648615 != 2'b0 ; + _theResult___fst_exp__h656689 == 8'd0 && + guard__h648612 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10760 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[0] : - _theResult___fst_exp__h656692 != 8'd255 && - guard__h648615 != 2'b0 ; + _theResult___fst_exp__h656689 != 8'd255 && + guard__h648612 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] == 8'd0) ? @@ -23525,35 +23525,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11998 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - ((_theResult___fst_exp__h693754 == 8'd255) ? + ((_theResult___fst_exp__h693751 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983) : - ((_theResult___fst_exp__h702439 == 8'd255) ? + ((_theResult___fst_exp__h702436 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12035 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - ((_theResult___fst_exp__h693754 == 8'd255) ? + ((_theResult___fst_exp__h693751 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026) : - ((_theResult___fst_exp__h702439 == 8'd255) ? + ((_theResult___fst_exp__h702436 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12131 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[2] : - _theResult___fst_exp__h702987 == 8'd255 && - _theResult___fst_sfd__h702988 == 23'd0 ; + _theResult___fst_exp__h702984 == 8'd255 && + _theResult___fst_sfd__h702985 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12144 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[1] : - _theResult___fst_exp__h702439 == 8'd0 && - guard__h694362 != 2'b0 ; + _theResult___fst_exp__h702436 == 8'd0 && + guard__h694359 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12157 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[0] : - _theResult___fst_exp__h702439 != 8'd255 && - guard__h694362 != 2'b0 ; + _theResult___fst_exp__h702436 != 8'd255 && + guard__h694359 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] == 8'd0) ? @@ -23563,41 +23563,41 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9204 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - ((_theResult___fst_exp__h602258 == 8'd255) ? + ((_theResult___fst_exp__h602255 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189) : - ((_theResult___fst_exp__h610943 == 8'd255) ? + ((_theResult___fst_exp__h610940 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9241 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - ((_theResult___fst_exp__h602258 == 8'd255) ? + ((_theResult___fst_exp__h602255 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232) : - ((_theResult___fst_exp__h610943 == 8'd255) ? + ((_theResult___fst_exp__h610940 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9337 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[2] : - _theResult___fst_exp__h611491 == 8'd255 && - _theResult___fst_sfd__h611492 == 23'd0 ; + _theResult___fst_exp__h611488 == 8'd255 && + _theResult___fst_sfd__h611489 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9350 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[1] : - _theResult___fst_exp__h610943 == 8'd0 && - guard__h602866 != 2'b0 ; + _theResult___fst_exp__h610940 == 8'd0 && + guard__h602863 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9363 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[0] : - _theResult___fst_exp__h610943 != 8'd255 && - guard__h602866 != 2'b0 ; + _theResult___fst_exp__h610940 != 8'd255 && + guard__h602863 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__633_BI_ETC___d4077 = - offset__h242559[63] ? - x__h242708[13:0] >= toBounds__h242587 && - repBoundBits__h242584 != + offset__h242558[63] ? + x__h242707[13:0] >= toBounds__h242586 && + repBoundBits__h242583 != coreFix_memExe_regToExeQ$first[316:303] : - x__h242708[13:0] < toBoundsM1__h242588 ; + x__h242707[13:0] < toBoundsM1__h242587 ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8201_ETC___d18233 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && @@ -23673,24 +23673,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18416 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18624 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h890898 : + res_address__h890894 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18622 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18639 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h890899 : + res_addrBits__h890895 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18637 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19198 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h896912 : + thin_reserved__h896908 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h896913 : + thin_otype__h896909 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19186, @@ -23699,7 +23699,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19199 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h897088 : + thin_perms_soft__h897084 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19044, @@ -23730,18 +23730,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19198 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19200 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h896908 : + thin_address__h896904 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h896909 : + thin_addrBits__h896905 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19199 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19221 = - thin_bounds_topBits__h898314[13:11] < repBound__h898430 ; + thin_bounds_topBits__h898310[13:11] < repBound__h898426 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19223 = - thin_bounds_baseBits__h898315[13:11] < repBound__h898430 ; + thin_bounds_baseBits__h898311[13:11] < repBound__h898426 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19226 = - thin_addrBits__h896909[13:11] < repBound__h898430 ; + thin_addrBits__h896905[13:11] < repBound__h898426 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19885 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -23954,24 +23954,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15804 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16240 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h848497 : + res_address__h848494 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16238 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16255 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h848498 : + res_addrBits__h848495 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16253 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17093 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h857278 : + thin_reserved__h857275 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h857279 : + thin_otype__h857276 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17068, @@ -23980,7 +23980,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17094 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h857526 : + thin_perms_soft__h857523 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16731, @@ -24011,18 +24011,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17093 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17095 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h857274 : + thin_address__h857271 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h857275 : + thin_addrBits__h857272 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17094 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17142 = - thin_bounds_topBits__h859272[13:11] < repBound__h859420 ; + thin_bounds_topBits__h859269[13:11] < repBound__h859417 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144 = - thin_bounds_baseBits__h859273[13:11] < repBound__h859420 ; + thin_bounds_baseBits__h859270[13:11] < repBound__h859417 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17147 = - thin_addrBits__h857275[13:11] < repBound__h859420 ; + thin_addrBits__h857272[13:11] < repBound__h859417 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17807 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -24784,8 +24784,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19990 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h913573 : - w__h913568 ; + result__h913568 : + w__h913563 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d4993 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25259,15 +25259,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__680_BIT_1_ETC___d3622 } ; assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3058 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h235268 : + res_addrBits__h235267 : ((coreFix_memExe_dispToRegQ$first[109] && coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3056 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3303 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h235267 : - x__h235690, + res_address__h235266 : + x__h235689, IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3058, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25406,13 +25406,13 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4231 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h242569[3:0] != 4'd0 : + pointer__h242568[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h242569[2:0] != 3'd0 : + pointer__h242568[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h242569[1:0] != 2'd0 : + pointer__h242568[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h242569[0])), + pointer__h242568[0])), capChecks___d4142[11:5], CASE_capChecks_142_BITS_4_TO_0_0_capChecks_142_ETC__q289, prepareBoundsCheck___d4226 } ; @@ -25534,7 +25534,7 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22623 = - ((newAddrDiff__h997630 == 64'd0) ? + ((newAddrDiff__h997625 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22599 ? 2'd3 : @@ -25551,12 +25551,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22626 = IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22623 && - (newAddrDiff__h997630 == 64'd0 || + (newAddrDiff__h997625 == 64'd0 || csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22599 || - newAddrDiff__h997630 == + newAddrDiff__h997625 == _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602) ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22648 = - ((newAddrDiff__h997974 == 64'd0) ? + ((newAddrDiff__h997969 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22632 ? 2'd3 : @@ -25573,12 +25573,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22651 = IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22648 && - (newAddrDiff__h997974 == 64'd0 || + (newAddrDiff__h997969 == 64'd0 || csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22632 || - newAddrDiff__h997974 == + newAddrDiff__h997969 == _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602) ; assign IF_csrf_mtcc_reg_read__6627_BIT_86_2584_AND_NO_ETC___d22654 = - (csrf_mtcc_reg[86] && cause_interrupt__h992790) ? + (csrf_mtcc_reg[86] && cause_interrupt__h992785) ? (NOT_csrf_mtcc_reg_read__6627_BITS_33_TO_28_258_ETC___d22588 || IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22626) && csrf_mtcc_reg[152] : @@ -25586,9 +25586,9 @@ module mkCore(CLK, IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22651) && csrf_mtcc_reg[152] ; assign IF_csrf_mtcc_reg_read__6627_BIT_86_2584_AND_NO_ETC___d22688 = - (csrf_mtcc_reg[86] && cause_interrupt__h992790) ? - address__h996950 : - base__h996915 ; + (csrf_mtcc_reg[86] && cause_interrupt__h992785) ? + address__h996945 : + base__h996910 ; assign IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_c_ETC___d22659 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? { IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22579, @@ -25708,7 +25708,7 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22548 = - ((newAddrDiff__h996973 == 64'd0) ? + ((newAddrDiff__h996968 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22524 ? 2'd3 : @@ -25725,12 +25725,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22551 = IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22548 && - (newAddrDiff__h996973 == 64'd0 || + (newAddrDiff__h996968 == 64'd0 || csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22524 || - newAddrDiff__h996973 == + newAddrDiff__h996968 == _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527) ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22573 = - ((newAddrDiff__h997317 == 64'd0) ? + ((newAddrDiff__h997312 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22557 ? 2'd3 : @@ -25747,12 +25747,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22576 = IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22573 && - (newAddrDiff__h997317 == 64'd0 || + (newAddrDiff__h997312 == 64'd0 || csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22557 || - newAddrDiff__h997317 == + newAddrDiff__h997312 == _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527) ; assign IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22579 = - (csrf_stcc_reg[86] && cause_interrupt__h992790) ? + (csrf_stcc_reg[86] && cause_interrupt__h992785) ? (NOT_csrf_stcc_reg_read__6618_BITS_33_TO_28_250_ETC___d22511 || IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22551) && csrf_stcc_reg[152] : @@ -25760,9 +25760,9 @@ module mkCore(CLK, IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22576) && csrf_stcc_reg[152] ; assign IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22687 = - (csrf_stcc_reg[86] && cause_interrupt__h992790) ? - address__h996900 : - base__h996861 ; + (csrf_stcc_reg[86] && cause_interrupt__h992785) ? + address__h996895 : + base__h996856 ; assign IF_fetchStage_RDY_pipelines_0_first__0046_AND__ETC___d20968 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[267:265] != 3'd1 || @@ -26168,13 +26168,13 @@ module mkCore(CLK, 2'd3) } ; assign IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1010691 : + y_avValue_snd_snd_snd_snd_snd__h1010686 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1010675 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1010670 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1010685 : + y_avValue_snd_snd_snd_fst__h1010680 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__3175_THEN_IF_NOT_rob__ETC___d23412 = rob$deqPort_1_canDeq ? @@ -26308,7 +26308,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18875) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18897 = sbCons$lazyLookup_0_get[3] ? - repBound__h896085 : + repBound__h896081 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8222_8_ETC___d18249 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18893) ; @@ -26339,7 +26339,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19000 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h898412, + repBound__h898408, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18972, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18973, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18985 } : @@ -26474,7 +26474,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16491) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16513 = sbCons$lazyLookup_1_get[3] ? - repBound__h856058 : + repBound__h856055 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16509) ; @@ -26505,7 +26505,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16616 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h859402, + repBound__h859399, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16589, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16601 } : @@ -26640,7 +26640,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3293) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3315 = sbCons$lazyLookup_3_get[3] ? - repBound__h237262 : + repBound__h237261 : (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3311) ; @@ -26796,7 +26796,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3560) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3577 = sbCons$lazyLookup_3_get[2] ? - repBound__h238947 : + repBound__h238946 : (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3573) ; @@ -26824,64 +26824,64 @@ module mkCore(CLK, (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? coreFix_aluExe_0_bypassWire_3$wget[3:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3616) ; - assign IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50 = - sfdin__h602252[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167 = - sfdin__h821941[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75 = - sfdin__h630235[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150 = - sfdin__h743784[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85 = - sfdin__h648001[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110 = - sfdin__h675982[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190 = - sfdin__h782637[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40 = - sfdin__h584486[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120 = - sfdin__h693748[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125 = - _theResult___snd__h702385[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55 = - _theResult___snd__h610889[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163 = - _theResult___snd__h812321[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170 = - _theResult___snd__h830726[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146 = - _theResult___snd__h734164[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77 = - _theResult___snd__h638848[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153 = - _theResult___snd__h752569[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90 = - _theResult___snd__h656638[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186 = - _theResult___snd__h773017[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112 = - _theResult___snd__h684595[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193 = - _theResult___snd__h791422[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42 = - _theResult___snd__h593099[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin02249_BIT_33_THEN_2_ELSE_0__q50 = + sfdin__h602249[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin21938_BIT_4_THEN_2_ELSE_0__q167 = + sfdin__h821938[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin30232_BIT_33_THEN_2_ELSE_0__q75 = + sfdin__h630232[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin43781_BIT_4_THEN_2_ELSE_0__q150 = + sfdin__h743781[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin47998_BIT_33_THEN_2_ELSE_0__q85 = + sfdin__h647998[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin75979_BIT_33_THEN_2_ELSE_0__q110 = + sfdin__h675979[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin82634_BIT_4_THEN_2_ELSE_0__q190 = + sfdin__h782634[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin84483_BIT_33_THEN_2_ELSE_0__q40 = + sfdin__h584483[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin93745_BIT_33_THEN_2_ELSE_0__q120 = + sfdin__h693745[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02382_BIT_33_THEN_2_ELSE_0__q125 = + _theResult___snd__h702382[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd10886_BIT_33_THEN_2_ELSE_0__q55 = + _theResult___snd__h610886[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12318_BIT_4_THEN_2_ELSE_0__q163 = + _theResult___snd__h812318[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30723_BIT_4_THEN_2_ELSE_0__q170 = + _theResult___snd__h830723[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd34161_BIT_4_THEN_2_ELSE_0__q146 = + _theResult___snd__h734161[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd38845_BIT_33_THEN_2_ELSE_0__q77 = + _theResult___snd__h638845[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd52566_BIT_4_THEN_2_ELSE_0__q153 = + _theResult___snd__h752566[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56635_BIT_33_THEN_2_ELSE_0__q90 = + _theResult___snd__h656635[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd73014_BIT_4_THEN_2_ELSE_0__q186 = + _theResult___snd__h773014[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84592_BIT_33_THEN_2_ELSE_0__q112 = + _theResult___snd__h684592[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd91419_BIT_4_THEN_2_ELSE_0__q193 = + _theResult___snd__h791419[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd93096_BIT_33_THEN_2_ELSE_0__q42 = + _theResult___snd__h593096[33] ? 2'd2 : 2'd0 ; assign INV_commitStage_commitTrap_BITS_217_TO_199__q15 = ~commitStage_commitTrap[217:199] ; assign INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19564 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h904334 : + x__h904330 : 6'd0, - x__h904507, - x__h904527 } ; + x__h904503, + x__h904523 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19628 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h904882 : + x__h904878 : 6'd0, - x__h905055, - x__h905075 } ; + x__h905051, + x__h905071 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -26889,17 +26889,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17485 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h865712 : + x__h865709 : 6'd0, - x__h865885, - x__h865905 } ; + x__h865882, + x__h865902 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17549 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h866260 : + x__h866257 : 6'd0, - x__h866433, - x__h866453 } ; + x__h866430, + x__h866450 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -26910,8 +26910,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x83367_BITS_108_TO_90__q33 = ~x__h183367[108:90] ; - assign INV_x99219_BITS_108_TO_90__q35 = ~x__h199219[108:90] ; + assign INV_x83366_BITS_108_TO_90__q33 = ~x__h183366[108:90] ; + assign INV_x99218_BITS_108_TO_90__q35 = ~x__h199218[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10728 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? @@ -27000,130 +27000,130 @@ module mkCore(CLK, !checkForException___d21375[13] && NOT_csrf_fs_reg_read__5969_EQ_0_0422_0423_OR_N_ETC___d21400 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__3171_3172_OR__ETC___d23417 = - (fflags__h1011197 & csrf_fflags_reg) != fflags__h1011197 || - !r__h852737 && + (fflags__h1011192 & csrf_fflags_reg) != fflags__h1011192 || + !r__h852734 && (IF_rob_deqPort_1_canDeq__3175_THEN_IF_NOT_rob__ETC___d23412 || - fflags__h1011197 != 5'd0) ; + fflags__h1011192 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 = - !f1_sfd__h714826[21] && !f1_sfd__h714826[20] && - !f1_sfd__h714826[19] && - !f1_sfd__h714826[18] && - !f1_sfd__h714826[17] && - !f1_sfd__h714826[16] && - !f1_sfd__h714826[15] && - !f1_sfd__h714826[14] && - !f1_sfd__h714826[13] && - !f1_sfd__h714826[12] && - !f1_sfd__h714826[11] && - !f1_sfd__h714826[10] && - !f1_sfd__h714826[9] && - !f1_sfd__h714826[8] && - !f1_sfd__h714826[7] && - !f1_sfd__h714826[6] && - !f1_sfd__h714826[5] && - !f1_sfd__h714826[4] && - !f1_sfd__h714826[3] && - !f1_sfd__h714826[2] && - !f1_sfd__h714826[1] && - !f1_sfd__h714826[0] ; + !f1_sfd__h714823[21] && !f1_sfd__h714823[20] && + !f1_sfd__h714823[19] && + !f1_sfd__h714823[18] && + !f1_sfd__h714823[17] && + !f1_sfd__h714823[16] && + !f1_sfd__h714823[15] && + !f1_sfd__h714823[14] && + !f1_sfd__h714823[13] && + !f1_sfd__h714823[12] && + !f1_sfd__h714823[11] && + !f1_sfd__h714823[10] && + !f1_sfd__h714823[9] && + !f1_sfd__h714823[8] && + !f1_sfd__h714823[7] && + !f1_sfd__h714823[6] && + !f1_sfd__h714823[5] && + !f1_sfd__h714823[4] && + !f1_sfd__h714823[3] && + !f1_sfd__h714823[2] && + !f1_sfd__h714823[1] && + !f1_sfd__h714823[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 = - !f3_sfd__h793124[21] && !f3_sfd__h793124[20] && - !f3_sfd__h793124[19] && - !f3_sfd__h793124[18] && - !f3_sfd__h793124[17] && - !f3_sfd__h793124[16] && - !f3_sfd__h793124[15] && - !f3_sfd__h793124[14] && - !f3_sfd__h793124[13] && - !f3_sfd__h793124[12] && - !f3_sfd__h793124[11] && - !f3_sfd__h793124[10] && - !f3_sfd__h793124[9] && - !f3_sfd__h793124[8] && - !f3_sfd__h793124[7] && - !f3_sfd__h793124[6] && - !f3_sfd__h793124[5] && - !f3_sfd__h793124[4] && - !f3_sfd__h793124[3] && - !f3_sfd__h793124[2] && - !f3_sfd__h793124[1] && - !f3_sfd__h793124[0] ; + !f3_sfd__h793121[21] && !f3_sfd__h793121[20] && + !f3_sfd__h793121[19] && + !f3_sfd__h793121[18] && + !f3_sfd__h793121[17] && + !f3_sfd__h793121[16] && + !f3_sfd__h793121[15] && + !f3_sfd__h793121[14] && + !f3_sfd__h793121[13] && + !f3_sfd__h793121[12] && + !f3_sfd__h793121[11] && + !f3_sfd__h793121[10] && + !f3_sfd__h793121[9] && + !f3_sfd__h793121[8] && + !f3_sfd__h793121[7] && + !f3_sfd__h793121[6] && + !f3_sfd__h793121[5] && + !f3_sfd__h793121[4] && + !f3_sfd__h793121[3] && + !f3_sfd__h793121[2] && + !f3_sfd__h793121[1] && + !f3_sfd__h793121[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 = - !f2_sfd__h753820[21] && !f2_sfd__h753820[20] && - !f2_sfd__h753820[19] && - !f2_sfd__h753820[18] && - !f2_sfd__h753820[17] && - !f2_sfd__h753820[16] && - !f2_sfd__h753820[15] && - !f2_sfd__h753820[14] && - !f2_sfd__h753820[13] && - !f2_sfd__h753820[12] && - !f2_sfd__h753820[11] && - !f2_sfd__h753820[10] && - !f2_sfd__h753820[9] && - !f2_sfd__h753820[8] && - !f2_sfd__h753820[7] && - !f2_sfd__h753820[6] && - !f2_sfd__h753820[5] && - !f2_sfd__h753820[4] && - !f2_sfd__h753820[3] && - !f2_sfd__h753820[2] && - !f2_sfd__h753820[1] && - !f2_sfd__h753820[0] ; + !f2_sfd__h753817[21] && !f2_sfd__h753817[20] && + !f2_sfd__h753817[19] && + !f2_sfd__h753817[18] && + !f2_sfd__h753817[17] && + !f2_sfd__h753817[16] && + !f2_sfd__h753817[15] && + !f2_sfd__h753817[14] && + !f2_sfd__h753817[13] && + !f2_sfd__h753817[12] && + !f2_sfd__h753817[11] && + !f2_sfd__h753817[10] && + !f2_sfd__h753817[9] && + !f2_sfd__h753817[8] && + !f2_sfd__h753817[7] && + !f2_sfd__h753817[6] && + !f2_sfd__h753817[5] && + !f2_sfd__h753817[4] && + !f2_sfd__h753817[3] && + !f2_sfd__h753817[2] && + !f2_sfd__h753817[1] && + !f2_sfd__h753817[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14895 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14936) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14995 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15005) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15035 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15049) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15081 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15093) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15123 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15135) ; assign NOT_commitStage_commitTrap_2039_BITS_44_TO_43__ETC___d22305 = commitStage_commitTrap[44:43] != 2'd0 && @@ -28280,7 +28280,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q312, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7119, - x__h508693 } ; + x__h508690 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d23934 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314, @@ -28303,8 +28303,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q307 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 = - { {4{f1_exp14825_MINUS_127__q147[7]}}, - f1_exp14825_MINUS_127__q147 } ; + { {4{f1_exp14822_MINUS_127__q147[7]}}, + f1_exp14822_MINUS_127__q147 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 ^ 12'h800) <= @@ -28314,8 +28314,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 = - { {4{f3_exp93123_MINUS_127__q164[7]}}, - f3_exp93123_MINUS_127__q164 } ; + { {4{f3_exp93120_MINUS_127__q164[7]}}, + f3_exp93120_MINUS_127__q164 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 ^ 12'h800) <= @@ -28325,8 +28325,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 = - { {4{f2_exp53819_MINUS_127__q187[7]}}, - f2_exp53819_MINUS_127__q187 } ; + { {4{f2_exp53816_MINUS_127__q187[7]}}, + f2_exp53816_MINUS_127__q187 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 ^ 12'h800) <= @@ -28354,11 +28354,11 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863 = - { {64{x__h264659[63]}}, x__h264659 } ; + { {64{x__h264656[63]}}, x__h264656 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871 = - { {96{x__h264814[31]}}, x__h264814 } ; + { {96{x__h264811[31]}}, x__h264811 } ; assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448 = - x__h995059 | in__h995128[63:0] ; + x__h995054 | in__h995123[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82 } ; @@ -28412,15 +28412,15 @@ module mkCore(CLK, 8'd127 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676 = { 3'd0, - _theResult___fst_exp__h630241 == 8'd0 && - (sfdin__h630235[56:34] == 23'd0 || guard__h622142 != 2'b0), + _theResult___fst_exp__h630238 == 8'd0 && + (sfdin__h630232[56:34] == 23'd0 || guard__h622139 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h630838 == 8'd255 && - _theResult___fst_sfd__h630839 == 23'd0, + _theResult___fst_exp__h630835 == 8'd255 && + _theResult___fst_sfd__h630836 == 23'd0, 1'd0, - _theResult___fst_exp__h630241 != 8'd255 && - guard__h622142 != 2'b0 } ; + _theResult___fst_exp__h630238 != 8'd255 && + guard__h622139 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 } ^ @@ -28428,15 +28428,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073 = { 3'd0, - _theResult___fst_exp__h675988 == 8'd0 && - (sfdin__h675982[56:34] == 23'd0 || guard__h667889 != 2'b0), + _theResult___fst_exp__h675985 == 8'd0 && + (sfdin__h675979[56:34] == 23'd0 || guard__h667886 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h676585 == 8'd255 && - _theResult___fst_sfd__h676586 == 23'd0, + _theResult___fst_exp__h676582 == 8'd255 && + _theResult___fst_sfd__h676583 == 23'd0, 1'd0, - _theResult___fst_exp__h675988 != 8'd255 && - guard__h667889 != 2'b0 } ; + _theResult___fst_exp__h675985 != 8'd255 && + guard__h667886 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 } ^ @@ -28444,15 +28444,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279 = { 3'd0, - _theResult___fst_exp__h584492 == 8'd0 && - (sfdin__h584486[56:34] == 23'd0 || guard__h576391 != 2'b0), + _theResult___fst_exp__h584489 == 8'd0 && + (sfdin__h584483[56:34] == 23'd0 || guard__h576388 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h585089 == 8'd255 && - _theResult___fst_sfd__h585090 == 23'd0, + _theResult___fst_exp__h585086 == 8'd255 && + _theResult___fst_sfd__h585087 == 23'd0, 1'd0, - _theResult___fst_exp__h584492 != 8'd255 && - guard__h576391 != 2'b0 } ; + _theResult___fst_exp__h584489 != 8'd255 && + guard__h576388 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 } ^ @@ -28475,37 +28475,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891 = { 3'd0, - _theResult___fst_exp__h743790 == 11'd0 && - (sfdin__h743784[56:5] == 52'd0 || guard__h735564 != 2'b0), + _theResult___fst_exp__h743787 == 11'd0 && + (sfdin__h743781[56:5] == 52'd0 || guard__h735561 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h744622 == 11'd2047 && - _theResult___fst_sfd__h744623 == 52'd0, + _theResult___fst_exp__h744619 == 11'd2047 && + _theResult___fst_sfd__h744620 == 52'd0, 1'd0, - _theResult___fst_exp__h743790 != 11'd2047 && - guard__h735564 != 2'b0 } ; + _theResult___fst_exp__h743787 != 11'd2047 && + guard__h735561 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932 = { 3'd0, - _theResult___fst_exp__h782643 == 11'd0 && - (sfdin__h782637[56:5] == 52'd0 || guard__h774417 != 2'b0), + _theResult___fst_exp__h782640 == 11'd0 && + (sfdin__h782634[56:5] == 52'd0 || guard__h774414 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h783475 == 11'd2047 && - _theResult___fst_sfd__h783476 == 52'd0, + _theResult___fst_exp__h783472 == 11'd2047 && + _theResult___fst_sfd__h783473 == 52'd0, 1'd0, - _theResult___fst_exp__h782643 != 11'd2047 && - guard__h774417 != 2'b0 } ; + _theResult___fst_exp__h782640 != 11'd2047 && + guard__h774414 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976 = { 3'd0, - _theResult___fst_exp__h821947 == 11'd0 && - (sfdin__h821941[56:5] == 52'd0 || guard__h813721 != 2'b0), + _theResult___fst_exp__h821944 == 11'd0 && + (sfdin__h821938[56:5] == 52'd0 || guard__h813718 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h822779 == 11'd2047 && - _theResult___fst_sfd__h822780 == 52'd0, + _theResult___fst_exp__h822776 == 11'd2047 && + _theResult___fst_sfd__h822777 == 52'd0, 1'd0, - _theResult___fst_exp__h821947 != 11'd2047 && - guard__h813721 != 2'b0 } ; + _theResult___fst_exp__h821944 != 11'd2047 && + guard__h813718 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 } ^ @@ -28513,15 +28513,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705 = { 3'd0, - _theResult___fst_exp__h648007 == 8'd0 && - (sfdin__h648001[56:34] == 23'd0 || guard__h639779 != 2'b0), + _theResult___fst_exp__h648004 == 8'd0 && + (sfdin__h647998[56:34] == 23'd0 || guard__h639776 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h648604 == 8'd255 && - _theResult___fst_sfd__h648605 == 23'd0, + _theResult___fst_exp__h648601 == 8'd255 && + _theResult___fst_sfd__h648602 == 23'd0, 1'd0, - _theResult___fst_exp__h648007 != 8'd255 && - guard__h639779 != 2'b0 } ; + _theResult___fst_exp__h648004 != 8'd255 && + guard__h639776 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 } ^ @@ -28529,15 +28529,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102 = { 3'd0, - _theResult___fst_exp__h693754 == 8'd0 && - (sfdin__h693748[56:34] == 23'd0 || guard__h685526 != 2'b0), + _theResult___fst_exp__h693751 == 8'd0 && + (sfdin__h693745[56:34] == 23'd0 || guard__h685523 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h694351 == 8'd255 && - _theResult___fst_sfd__h694352 == 23'd0, + _theResult___fst_exp__h694348 == 8'd255 && + _theResult___fst_sfd__h694349 == 23'd0, 1'd0, - _theResult___fst_exp__h693754 != 8'd255 && - guard__h685526 != 2'b0 } ; + _theResult___fst_exp__h693751 != 8'd255 && + guard__h685523 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 } ^ @@ -28545,15 +28545,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308 = { 3'd0, - _theResult___fst_exp__h602258 == 8'd0 && - (sfdin__h602252[56:34] == 23'd0 || guard__h594030 != 2'b0), + _theResult___fst_exp__h602255 == 8'd0 && + (sfdin__h602249[56:34] == 23'd0 || guard__h594027 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h602855 == 8'd255 && - _theResult___fst_sfd__h602856 == 23'd0, + _theResult___fst_exp__h602852 == 8'd255 && + _theResult___fst_sfd__h602853 == 23'd0, 1'd0, - _theResult___fst_exp__h602258 != 8'd255 && - guard__h594030 != 2'b0 } ; + _theResult___fst_exp__h602255 != 8'd255 && + guard__h594027 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ^ @@ -28589,37 +28589,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874 = { 3'd0, - _theResult___fst_exp__h734213 == 11'd0 && - guard__h726252 != 2'b0, + _theResult___fst_exp__h734210 == 11'd0 && + guard__h726249 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h734971 == 11'd2047 && - _theResult___fst_sfd__h734972 == 52'd0, + _theResult___fst_exp__h734968 == 11'd2047 && + _theResult___fst_sfd__h734969 == 52'd0, 1'd0, - _theResult___fst_exp__h734213 != 11'd2047 && - guard__h726252 != 2'b0 } ; + _theResult___fst_exp__h734210 != 11'd2047 && + guard__h726249 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915 = { 3'd0, - _theResult___fst_exp__h773066 == 11'd0 && - guard__h765105 != 2'b0, + _theResult___fst_exp__h773063 == 11'd0 && + guard__h765102 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h773824 == 11'd2047 && - _theResult___fst_sfd__h773825 == 52'd0, + _theResult___fst_exp__h773821 == 11'd2047 && + _theResult___fst_sfd__h773822 == 52'd0, 1'd0, - _theResult___fst_exp__h773066 != 11'd2047 && - guard__h765105 != 2'b0 } ; + _theResult___fst_exp__h773063 != 11'd2047 && + guard__h765102 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959 = { 3'd0, - _theResult___fst_exp__h812370 == 11'd0 && - guard__h804409 != 2'b0, + _theResult___fst_exp__h812367 == 11'd0 && + guard__h804406 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h813128 == 11'd2047 && - _theResult___fst_sfd__h813129 == 52'd0, + _theResult___fst_exp__h813125 == 11'd2047 && + _theResult___fst_sfd__h813126 == 52'd0, 1'd0, - _theResult___fst_exp__h812370 != 11'd2047 && - guard__h804409 != 2'b0 } ; + _theResult___fst_exp__h812367 != 11'd2047 && + guard__h804406 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ^ @@ -28628,15 +28628,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688 = { 3'd0, - _theResult___fst_exp__h638897 == 8'd0 && - guard__h630849 != 2'b0, + _theResult___fst_exp__h638894 == 8'd0 && + guard__h630846 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h639420 == 8'd255 && - _theResult___fst_sfd__h639421 == 23'd0, + _theResult___fst_exp__h639417 == 8'd255 && + _theResult___fst_sfd__h639418 == 23'd0, 1'd0, - _theResult___fst_exp__h638897 != 8'd255 && - guard__h630849 != 2'b0 } ; + _theResult___fst_exp__h638894 != 8'd255 && + guard__h630846 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ^ @@ -28650,15 +28650,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085 = { 3'd0, - _theResult___fst_exp__h684644 == 8'd0 && - guard__h676596 != 2'b0, + _theResult___fst_exp__h684641 == 8'd0 && + guard__h676593 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h685167 == 8'd255 && - _theResult___fst_sfd__h685168 == 23'd0, + _theResult___fst_exp__h685164 == 8'd255 && + _theResult___fst_sfd__h685165 == 23'd0, 1'd0, - _theResult___fst_exp__h684644 != 8'd255 && - guard__h676596 != 2'b0 } ; + _theResult___fst_exp__h684641 != 8'd255 && + guard__h676593 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ^ @@ -28672,15 +28672,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291 = { 3'd0, - _theResult___fst_exp__h593148 == 8'd0 && - guard__h585100 != 2'b0, + _theResult___fst_exp__h593145 == 8'd0 && + guard__h585097 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h593671 == 8'd255 && - _theResult___fst_sfd__h593672 == 23'd0, + _theResult___fst_exp__h593668 == 8'd255 && + _theResult___fst_sfd__h593669 == 23'd0, 1'd0, - _theResult___fst_exp__h593148 != 8'd255 && - guard__h585100 != 2'b0 } ; + _theResult___fst_exp__h593145 != 8'd255 && + guard__h585097 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ^ @@ -28706,17 +28706,17 @@ module mkCore(CLK, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; assign _0_CONCAT_csrf_mtcc_reg_read__6627_BITS_149_TO__ETC___d22614 = - x__h997817[13:11] < repBound__h997781 ; + x__h997812[13:11] < repBound__h997776 ; assign _0_CONCAT_csrf_mtcc_reg_read__6627_BITS_149_TO__ETC___d22640 = - x__h998121[13:11] < repBound__h997781 ; + x__h998116[13:11] < repBound__h997776 ; assign _0_CONCAT_csrf_stcc_reg_read__6618_BITS_149_TO__ETC___d22539 = - x__h997160[13:11] < repBound__h997124 ; + x__h997155[13:11] < repBound__h997119 ; assign _0_CONCAT_csrf_stcc_reg_read__6618_BITS_149_TO__ETC___d22565 = - x__h997464[13:11] < repBound__h997124 ; + x__h997459[13:11] < repBound__h997119 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0049_BI_ETC___d21612 = (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 ; + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0058_BI_ETC___d21510 = (fetchStage$pipelines_1_first[267:265] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -28730,37 +28730,37 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__0047_AND_N_ETC__q269 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786 = - sfd__h715187 >> + sfd__h715184 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501 = - sfd__h793485 >> + sfd__h793482 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271 = - sfd__h754181 >> + sfd__h754178 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060 = - sfd__h614530 >> + sfd__h614527 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457 = - sfd__h660277 >> + sfd__h660274 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663 = - sfd__h568776 >> + sfd__h568773 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659) ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__6063_6064_ETC___d22413 = - medeleg_csr__read__h849989[i__h992808] ; + medeleg_csr__read__h849986[i__h992803] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22415 = - mideleg_csr__read__h850087[i__h992982] ; + mideleg_csr__read__h850084[i__h992977] ; assign _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602 = - mask__h997629 ^ y__h997746 ; + mask__h997624 ^ y__h997741 ; assign _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527 = - mask__h996972 ^ y__h997089 ; + mask__h996967 ^ y__h997084 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10691 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? @@ -29166,51 +29166,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12642 = 12'd3970 - { 7'd0, - f1_sfd__h714826[22] ? + f1_sfd__h714823[22] ? 5'd0 : - (f1_sfd__h714826[21] ? + (f1_sfd__h714823[21] ? 5'd1 : - (f1_sfd__h714826[20] ? + (f1_sfd__h714823[20] ? 5'd2 : - (f1_sfd__h714826[19] ? + (f1_sfd__h714823[19] ? 5'd3 : - (f1_sfd__h714826[18] ? + (f1_sfd__h714823[18] ? 5'd4 : - (f1_sfd__h714826[17] ? + (f1_sfd__h714823[17] ? 5'd5 : - (f1_sfd__h714826[16] ? + (f1_sfd__h714823[16] ? 5'd6 : - (f1_sfd__h714826[15] ? + (f1_sfd__h714823[15] ? 5'd7 : - (f1_sfd__h714826[14] ? + (f1_sfd__h714823[14] ? 5'd8 : - (f1_sfd__h714826[13] ? + (f1_sfd__h714823[13] ? 5'd9 : - (f1_sfd__h714826[12] ? + (f1_sfd__h714823[12] ? 5'd10 : - (f1_sfd__h714826[11] ? + (f1_sfd__h714823[11] ? 5'd11 : - (f1_sfd__h714826[10] ? + (f1_sfd__h714823[10] ? 5'd12 : - (f1_sfd__h714826[9] ? + (f1_sfd__h714823[9] ? 5'd13 : - (f1_sfd__h714826[8] ? + (f1_sfd__h714823[8] ? 5'd14 : - (f1_sfd__h714826[7] ? + (f1_sfd__h714823[7] ? 5'd15 : - (f1_sfd__h714826[6] ? + (f1_sfd__h714823[6] ? 5'd16 : - (f1_sfd__h714826[5] ? + (f1_sfd__h714823[5] ? 5'd17 : - (f1_sfd__h714826[4] ? + (f1_sfd__h714823[4] ? 5'd18 : - (f1_sfd__h714826[3] ? + (f1_sfd__h714823[3] ? 5'd19 : - (f1_sfd__h714826[2] ? + (f1_sfd__h714823[2] ? 5'd20 : - (f1_sfd__h714826[1] ? + (f1_sfd__h714823[1] ? 5'd21 : - (f1_sfd__h714826[0] ? + (f1_sfd__h714823[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 = @@ -29224,51 +29224,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13372 = 12'd3970 - { 7'd0, - f3_sfd__h793124[22] ? + f3_sfd__h793121[22] ? 5'd0 : - (f3_sfd__h793124[21] ? + (f3_sfd__h793121[21] ? 5'd1 : - (f3_sfd__h793124[20] ? + (f3_sfd__h793121[20] ? 5'd2 : - (f3_sfd__h793124[19] ? + (f3_sfd__h793121[19] ? 5'd3 : - (f3_sfd__h793124[18] ? + (f3_sfd__h793121[18] ? 5'd4 : - (f3_sfd__h793124[17] ? + (f3_sfd__h793121[17] ? 5'd5 : - (f3_sfd__h793124[16] ? + (f3_sfd__h793121[16] ? 5'd6 : - (f3_sfd__h793124[15] ? + (f3_sfd__h793121[15] ? 5'd7 : - (f3_sfd__h793124[14] ? + (f3_sfd__h793121[14] ? 5'd8 : - (f3_sfd__h793124[13] ? + (f3_sfd__h793121[13] ? 5'd9 : - (f3_sfd__h793124[12] ? + (f3_sfd__h793121[12] ? 5'd10 : - (f3_sfd__h793124[11] ? + (f3_sfd__h793121[11] ? 5'd11 : - (f3_sfd__h793124[10] ? + (f3_sfd__h793121[10] ? 5'd12 : - (f3_sfd__h793124[9] ? + (f3_sfd__h793121[9] ? 5'd13 : - (f3_sfd__h793124[8] ? + (f3_sfd__h793121[8] ? 5'd14 : - (f3_sfd__h793124[7] ? + (f3_sfd__h793121[7] ? 5'd15 : - (f3_sfd__h793124[6] ? + (f3_sfd__h793121[6] ? 5'd16 : - (f3_sfd__h793124[5] ? + (f3_sfd__h793121[5] ? 5'd17 : - (f3_sfd__h793124[4] ? + (f3_sfd__h793121[4] ? 5'd18 : - (f3_sfd__h793124[3] ? + (f3_sfd__h793121[3] ? 5'd19 : - (f3_sfd__h793124[2] ? + (f3_sfd__h793121[2] ? 5'd20 : - (f3_sfd__h793124[1] ? + (f3_sfd__h793121[1] ? 5'd21 : - (f3_sfd__h793124[0] ? + (f3_sfd__h793121[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 = @@ -29282,51 +29282,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14142 = 12'd3970 - { 7'd0, - f2_sfd__h753820[22] ? + f2_sfd__h753817[22] ? 5'd0 : - (f2_sfd__h753820[21] ? + (f2_sfd__h753817[21] ? 5'd1 : - (f2_sfd__h753820[20] ? + (f2_sfd__h753817[20] ? 5'd2 : - (f2_sfd__h753820[19] ? + (f2_sfd__h753817[19] ? 5'd3 : - (f2_sfd__h753820[18] ? + (f2_sfd__h753817[18] ? 5'd4 : - (f2_sfd__h753820[17] ? + (f2_sfd__h753817[17] ? 5'd5 : - (f2_sfd__h753820[16] ? + (f2_sfd__h753817[16] ? 5'd6 : - (f2_sfd__h753820[15] ? + (f2_sfd__h753817[15] ? 5'd7 : - (f2_sfd__h753820[14] ? + (f2_sfd__h753817[14] ? 5'd8 : - (f2_sfd__h753820[13] ? + (f2_sfd__h753817[13] ? 5'd9 : - (f2_sfd__h753820[12] ? + (f2_sfd__h753817[12] ? 5'd10 : - (f2_sfd__h753820[11] ? + (f2_sfd__h753817[11] ? 5'd11 : - (f2_sfd__h753820[10] ? + (f2_sfd__h753817[10] ? 5'd12 : - (f2_sfd__h753820[9] ? + (f2_sfd__h753817[9] ? 5'd13 : - (f2_sfd__h753820[8] ? + (f2_sfd__h753817[8] ? 5'd14 : - (f2_sfd__h753820[7] ? + (f2_sfd__h753817[7] ? 5'd15 : - (f2_sfd__h753820[6] ? + (f2_sfd__h753817[6] ? 5'd16 : - (f2_sfd__h753820[5] ? + (f2_sfd__h753817[5] ? 5'd17 : - (f2_sfd__h753820[4] ? + (f2_sfd__h753817[4] ? 5'd18 : - (f2_sfd__h753820[3] ? + (f2_sfd__h753817[3] ? 5'd19 : - (f2_sfd__h753820[2] ? + (f2_sfd__h753817[2] ? 5'd20 : - (f2_sfd__h753820[1] ? + (f2_sfd__h753817[1] ? 5'd21 : - (f2_sfd__h753820[0] ? + (f2_sfd__h753817[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 = @@ -29367,7 +29367,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[237:236] != 2'd1 && fetchStage_pipelines_1_first__0058_BITS_267_TO_ETC___d21945 ; assign _dfoo16 = - k__h942684 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h942679 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786 || (fetchStage_pipelines_0_canDeq__0047_AND_NOT_fe_ETC___d21871 || NOT_fetchStage_pipelines_0_canDeq__0047_0048_O_ETC___d21884) == @@ -29375,7 +29375,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0047_0048_O_ETC___d21889 && NOT_fetchStage_pipelines_1_first__0058_BITS_26_ETC___d21901 ; assign _dfoo18 = - k__h942684 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h942679 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786 || (fetchStage_pipelines_0_canDeq__0047_AND_NOT_fe_ETC___d21871 || NOT_fetchStage_pipelines_0_canDeq__0047_0048_O_ETC___d21884) == @@ -29482,1415 +29482,1415 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h515296 = + assign _theResult_____2__h515292 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7222 ? - next_deqP___1__h515541 : + next_deqP___1__h515537 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h526073 = + assign _theResult_____2__h526069 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7316 ? - next_deqP___1__h526318 : + next_deqP___1__h526314 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h533166 = + assign _theResult_____2__h533162 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7475 ? - next_deqP___1__h533596 : + next_deqP___1__h533592 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h543801 = + assign _theResult_____2__h543797 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7559 ? - next_deqP___1__h544231 : + next_deqP___1__h544227 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h557634 = + assign _theResult_____2__h557630 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7764 ? - next_deqP___1__h557879 : + next_deqP___1__h557875 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h561413 = + assign _theResult_____2__h561409 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7846 ? - next_deqP___1__h561658 : + next_deqP___1__h561654 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h576381 = - (value__h577003 == 54'd0) ? sfd__h568776 : 57'd1 ; - assign _theResult____h594020 = + assign _theResult____h576378 = + (value__h577000 == 54'd0) ? sfd__h568773 : 57'd1 ; + assign _theResult____h594017 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659 ^ 12'h800) < 12'd2105) ? - result__h594633 : - _theResult____h576381 ; - assign _theResult____h622132 = - (value__h622752 == 54'd0) ? sfd__h614530 : 57'd1 ; - assign _theResult____h639769 = + result__h594630 : + _theResult____h576378 ; + assign _theResult____h622129 = + (value__h622749 == 54'd0) ? sfd__h614527 : 57'd1 ; + assign _theResult____h639766 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056 ^ 12'h800) < 12'd2105) ? - result__h640382 : - _theResult____h622132 ; - assign _theResult____h667879 = - (value__h668499 == 54'd0) ? sfd__h660277 : 57'd1 ; - assign _theResult____h685516 = + result__h640379 : + _theResult____h622129 ; + assign _theResult____h667876 = + (value__h668496 == 54'd0) ? sfd__h660274 : 57'd1 ; + assign _theResult____h685513 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453 ^ 12'h800) < 12'd2105) ? - result__h686129 : - _theResult____h667879 ; - assign _theResult____h735554 = + result__h686126 : + _theResult____h667876 ; + assign _theResult____h735551 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ^ 12'h800) < 12'd2105) ? - result__h736167 : - ((value__h719770 == 25'd0) ? sfd__h715187 : 57'd1) ; - assign _theResult____h774407 = + result__h736164 : + ((value__h719767 == 25'd0) ? sfd__h715184 : 57'd1) ; + assign _theResult____h774404 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ^ 12'h800) < 12'd2105) ? - result__h775020 : - ((value__h758623 == 25'd0) ? sfd__h754181 : 57'd1) ; - assign _theResult____h813711 = + result__h775017 : + ((value__h758620 == 25'd0) ? sfd__h754178 : 57'd1) ; + assign _theResult____h813708 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ^ 12'h800) < 12'd2105) ? - result__h814324 : - ((value__h797927 == 25'd0) ? sfd__h793485 : 57'd1) ; - assign _theResult____h917995 = + result__h814321 : + ((value__h797924 == 25'd0) ? sfd__h793482 : 57'd1) ; + assign _theResult____h917990 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h918520 : + enabled_ints___1__h918515 : 16'd0 ; - assign _theResult___exp__h585008 = - sfd__h584584[24] ? - ((_theResult___fst_exp__h584492 == 8'd254) ? + assign _theResult___exp__h585005 = + sfd__h584581[24] ? + ((_theResult___fst_exp__h584489 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611525) : - ((_theResult___fst_exp__h584492 == 8'd0 && - sfd__h584584[24:23] == 2'b01) ? + din_inc___2_exp__h611522) : + ((_theResult___fst_exp__h584489 == 8'd0 && + sfd__h584581[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h584492) ; - assign _theResult___exp__h593590 = - sfd__h593166[24] ? - ((_theResult___fst_exp__h593148 == 8'd254) ? + _theResult___fst_exp__h584489) ; + assign _theResult___exp__h593587 = + sfd__h593163[24] ? + ((_theResult___fst_exp__h593145 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611549) : - ((_theResult___fst_exp__h593148 == 8'd0 && - sfd__h593166[24:23] == 2'b01) ? + din_inc___2_exp__h611546) : + ((_theResult___fst_exp__h593145 == 8'd0 && + sfd__h593163[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h593148) ; - assign _theResult___exp__h602774 = - sfd__h602350[24] ? - ((_theResult___fst_exp__h602258 == 8'd254) ? + _theResult___fst_exp__h593145) ; + assign _theResult___exp__h602771 = + sfd__h602347[24] ? + ((_theResult___fst_exp__h602255 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611579) : - ((_theResult___fst_exp__h602258 == 8'd0 && - sfd__h602350[24:23] == 2'b01) ? + din_inc___2_exp__h611576) : + ((_theResult___fst_exp__h602255 == 8'd0 && + sfd__h602347[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h602258) ; - assign _theResult___exp__h611410 = - sfd__h610962[24] ? - ((_theResult___fst_exp__h610943 == 8'd254) ? + _theResult___fst_exp__h602255) ; + assign _theResult___exp__h611407 = + sfd__h610959[24] ? + ((_theResult___fst_exp__h610940 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611603) : - ((_theResult___fst_exp__h610943 == 8'd0 && - sfd__h610962[24:23] == 2'b01) ? + din_inc___2_exp__h611600) : + ((_theResult___fst_exp__h610940 == 8'd0 && + sfd__h610959[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h610943) ; - assign _theResult___exp__h611512 = + _theResult___fst_exp__h610940) ; + assign _theResult___exp__h611509 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611503 ; - assign _theResult___exp__h630757 = - sfd__h630333[24] ? - ((_theResult___fst_exp__h630241 == 8'd254) ? + _theResult___fst_exp__h611500 ; + assign _theResult___exp__h630754 = + sfd__h630330[24] ? + ((_theResult___fst_exp__h630238 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657274) : - ((_theResult___fst_exp__h630241 == 8'd0 && - sfd__h630333[24:23] == 2'b01) ? + din_inc___2_exp__h657271) : + ((_theResult___fst_exp__h630238 == 8'd0 && + sfd__h630330[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h630241) ; - assign _theResult___exp__h639339 = - sfd__h638915[24] ? - ((_theResult___fst_exp__h638897 == 8'd254) ? + _theResult___fst_exp__h630238) ; + assign _theResult___exp__h639336 = + sfd__h638912[24] ? + ((_theResult___fst_exp__h638894 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657298) : - ((_theResult___fst_exp__h638897 == 8'd0 && - sfd__h638915[24:23] == 2'b01) ? + din_inc___2_exp__h657295) : + ((_theResult___fst_exp__h638894 == 8'd0 && + sfd__h638912[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h638897) ; - assign _theResult___exp__h648523 = - sfd__h648099[24] ? - ((_theResult___fst_exp__h648007 == 8'd254) ? + _theResult___fst_exp__h638894) ; + assign _theResult___exp__h648520 = + sfd__h648096[24] ? + ((_theResult___fst_exp__h648004 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657328) : - ((_theResult___fst_exp__h648007 == 8'd0 && - sfd__h648099[24:23] == 2'b01) ? + din_inc___2_exp__h657325) : + ((_theResult___fst_exp__h648004 == 8'd0 && + sfd__h648096[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h648007) ; - assign _theResult___exp__h657159 = - sfd__h656711[24] ? - ((_theResult___fst_exp__h656692 == 8'd254) ? + _theResult___fst_exp__h648004) ; + assign _theResult___exp__h657156 = + sfd__h656708[24] ? + ((_theResult___fst_exp__h656689 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657352) : - ((_theResult___fst_exp__h656692 == 8'd0 && - sfd__h656711[24:23] == 2'b01) ? + din_inc___2_exp__h657349) : + ((_theResult___fst_exp__h656689 == 8'd0 && + sfd__h656708[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h656692) ; - assign _theResult___exp__h657261 = + _theResult___fst_exp__h656689) ; + assign _theResult___exp__h657258 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657252 ; - assign _theResult___exp__h676504 = - sfd__h676080[24] ? - ((_theResult___fst_exp__h675988 == 8'd254) ? + _theResult___fst_exp__h657249 ; + assign _theResult___exp__h676501 = + sfd__h676077[24] ? + ((_theResult___fst_exp__h675985 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703021) : - ((_theResult___fst_exp__h675988 == 8'd0 && - sfd__h676080[24:23] == 2'b01) ? + din_inc___2_exp__h703018) : + ((_theResult___fst_exp__h675985 == 8'd0 && + sfd__h676077[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h675988) ; - assign _theResult___exp__h685086 = - sfd__h684662[24] ? - ((_theResult___fst_exp__h684644 == 8'd254) ? + _theResult___fst_exp__h675985) ; + assign _theResult___exp__h685083 = + sfd__h684659[24] ? + ((_theResult___fst_exp__h684641 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703045) : - ((_theResult___fst_exp__h684644 == 8'd0 && - sfd__h684662[24:23] == 2'b01) ? + din_inc___2_exp__h703042) : + ((_theResult___fst_exp__h684641 == 8'd0 && + sfd__h684659[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h684644) ; - assign _theResult___exp__h694270 = - sfd__h693846[24] ? - ((_theResult___fst_exp__h693754 == 8'd254) ? + _theResult___fst_exp__h684641) ; + assign _theResult___exp__h694267 = + sfd__h693843[24] ? + ((_theResult___fst_exp__h693751 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703075) : - ((_theResult___fst_exp__h693754 == 8'd0 && - sfd__h693846[24:23] == 2'b01) ? + din_inc___2_exp__h703072) : + ((_theResult___fst_exp__h693751 == 8'd0 && + sfd__h693843[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h693754) ; - assign _theResult___exp__h702906 = - sfd__h702458[24] ? - ((_theResult___fst_exp__h702439 == 8'd254) ? + _theResult___fst_exp__h693751) ; + assign _theResult___exp__h702903 = + sfd__h702455[24] ? + ((_theResult___fst_exp__h702436 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703099) : - ((_theResult___fst_exp__h702439 == 8'd0 && - sfd__h702458[24:23] == 2'b01) ? + din_inc___2_exp__h703096) : + ((_theResult___fst_exp__h702436 == 8'd0 && + sfd__h702455[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h702439) ; - assign _theResult___exp__h703008 = + _theResult___fst_exp__h702436) ; + assign _theResult___exp__h703005 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h702999 ; - assign _theResult___exp__h734868 = - sfd__h734231[53] ? - ((_theResult___fst_exp__h734213 == 11'd2046) ? + _theResult___fst_exp__h702996 ; + assign _theResult___exp__h734865 = + sfd__h734228[53] ? + ((_theResult___fst_exp__h734210 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753463) : - ((_theResult___fst_exp__h734213 == 11'd0 && - sfd__h734231[53:52] == 2'b01) ? + din_inc___2_exp__h753460) : + ((_theResult___fst_exp__h734210 == 11'd0 && + sfd__h734228[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h734213) ; - assign _theResult___exp__h744519 = - sfd__h743882[53] ? - ((_theResult___fst_exp__h743790 == 11'd2046) ? + _theResult___fst_exp__h734210) ; + assign _theResult___exp__h744516 = + sfd__h743879[53] ? + ((_theResult___fst_exp__h743787 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753498) : - ((_theResult___fst_exp__h743790 == 11'd0 && - sfd__h743882[53:52] == 2'b01) ? + din_inc___2_exp__h753495) : + ((_theResult___fst_exp__h743787 == 11'd0 && + sfd__h743879[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h743790) ; - assign _theResult___exp__h753303 = - sfd__h752642[53] ? - ((_theResult___fst_exp__h752623 == 11'd2046) ? + _theResult___fst_exp__h743787) ; + assign _theResult___exp__h753300 = + sfd__h752639[53] ? + ((_theResult___fst_exp__h752620 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753524) : - ((_theResult___fst_exp__h752623 == 11'd0 && - sfd__h752642[53:52] == 2'b01) ? + din_inc___2_exp__h753521) : + ((_theResult___fst_exp__h752620 == 11'd0 && + sfd__h752639[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h752623) ; - assign _theResult___exp__h773721 = - sfd__h773084[53] ? - ((_theResult___fst_exp__h773066 == 11'd2046) ? + _theResult___fst_exp__h752620) ; + assign _theResult___exp__h773718 = + sfd__h773081[53] ? + ((_theResult___fst_exp__h773063 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792316) : - ((_theResult___fst_exp__h773066 == 11'd0 && - sfd__h773084[53:52] == 2'b01) ? + din_inc___2_exp__h792313) : + ((_theResult___fst_exp__h773063 == 11'd0 && + sfd__h773081[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h773066) ; - assign _theResult___exp__h783372 = - sfd__h782735[53] ? - ((_theResult___fst_exp__h782643 == 11'd2046) ? + _theResult___fst_exp__h773063) ; + assign _theResult___exp__h783369 = + sfd__h782732[53] ? + ((_theResult___fst_exp__h782640 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792351) : - ((_theResult___fst_exp__h782643 == 11'd0 && - sfd__h782735[53:52] == 2'b01) ? + din_inc___2_exp__h792348) : + ((_theResult___fst_exp__h782640 == 11'd0 && + sfd__h782732[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h782643) ; - assign _theResult___exp__h792156 = - sfd__h791495[53] ? - ((_theResult___fst_exp__h791476 == 11'd2046) ? + _theResult___fst_exp__h782640) ; + assign _theResult___exp__h792153 = + sfd__h791492[53] ? + ((_theResult___fst_exp__h791473 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792377) : - ((_theResult___fst_exp__h791476 == 11'd0 && - sfd__h791495[53:52] == 2'b01) ? + din_inc___2_exp__h792374) : + ((_theResult___fst_exp__h791473 == 11'd0 && + sfd__h791492[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h791476) ; - assign _theResult___exp__h813025 = - sfd__h812388[53] ? - ((_theResult___fst_exp__h812370 == 11'd2046) ? + _theResult___fst_exp__h791473) ; + assign _theResult___exp__h813022 = + sfd__h812385[53] ? + ((_theResult___fst_exp__h812367 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831620) : - ((_theResult___fst_exp__h812370 == 11'd0 && - sfd__h812388[53:52] == 2'b01) ? + din_inc___2_exp__h831617) : + ((_theResult___fst_exp__h812367 == 11'd0 && + sfd__h812385[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h812370) ; - assign _theResult___exp__h822676 = - sfd__h822039[53] ? - ((_theResult___fst_exp__h821947 == 11'd2046) ? + _theResult___fst_exp__h812367) ; + assign _theResult___exp__h822673 = + sfd__h822036[53] ? + ((_theResult___fst_exp__h821944 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831655) : - ((_theResult___fst_exp__h821947 == 11'd0 && - sfd__h822039[53:52] == 2'b01) ? + din_inc___2_exp__h831652) : + ((_theResult___fst_exp__h821944 == 11'd0 && + sfd__h822036[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h821947) ; - assign _theResult___exp__h831460 = - sfd__h830799[53] ? - ((_theResult___fst_exp__h830780 == 11'd2046) ? + _theResult___fst_exp__h821944) ; + assign _theResult___exp__h831457 = + sfd__h830796[53] ? + ((_theResult___fst_exp__h830777 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831681) : - ((_theResult___fst_exp__h830780 == 11'd0 && - sfd__h830799[53:52] == 2'b01) ? + din_inc___2_exp__h831678) : + ((_theResult___fst_exp__h830777 == 11'd0 && + sfd__h830796[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h830780) ; - assign _theResult___fst__h836055 = - a__h835633[63] ? a___1__h836060 : a__h835633 ; - assign _theResult___fst_exp__h584492 = - _theResult____h576381[56] ? + _theResult___fst_exp__h830777) ; + assign _theResult___fst__h836052 = + a__h835630[63] ? a___1__h836057 : a__h835630 ; + assign _theResult___fst_exp__h584489 = + _theResult____h576378[56] ? 8'd2 : - _theResult___fst_exp__h584566 ; - assign _theResult___fst_exp__h584557 = + _theResult___fst_exp__h584563 ; + assign _theResult___fst_exp__h584554 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 } ; - assign _theResult___fst_exp__h584563 = - (!_theResult____h576381[56] && !_theResult____h576381[55] && - !_theResult____h576381[54] && - !_theResult____h576381[53] && - !_theResult____h576381[52] && - !_theResult____h576381[51] && - !_theResult____h576381[50] && - !_theResult____h576381[49] && - !_theResult____h576381[48] && - !_theResult____h576381[47] && - !_theResult____h576381[46] && - !_theResult____h576381[45] && - !_theResult____h576381[44] && - !_theResult____h576381[43] && - !_theResult____h576381[42] && - !_theResult____h576381[41] && - !_theResult____h576381[40] && - !_theResult____h576381[39] && - !_theResult____h576381[38] && - !_theResult____h576381[37] && - !_theResult____h576381[36] && - !_theResult____h576381[35] && - !_theResult____h576381[34] && - !_theResult____h576381[33] && - !_theResult____h576381[32] && - !_theResult____h576381[31] && - !_theResult____h576381[30] && - !_theResult____h576381[29] && - !_theResult____h576381[28] && - !_theResult____h576381[27] && - !_theResult____h576381[26] && - !_theResult____h576381[25] && - !_theResult____h576381[24] && - !_theResult____h576381[23] && - !_theResult____h576381[22] && - !_theResult____h576381[21] && - !_theResult____h576381[20] && - !_theResult____h576381[19] && - !_theResult____h576381[18] && - !_theResult____h576381[17] && - !_theResult____h576381[16] && - !_theResult____h576381[15] && - !_theResult____h576381[14] && - !_theResult____h576381[13] && - !_theResult____h576381[12] && - !_theResult____h576381[11] && - !_theResult____h576381[10] && - !_theResult____h576381[9] && - !_theResult____h576381[8] && - !_theResult____h576381[7] && - !_theResult____h576381[6] && - !_theResult____h576381[5] && - !_theResult____h576381[4] && - !_theResult____h576381[3] && - !_theResult____h576381[2] && - !_theResult____h576381[1] && - !_theResult____h576381[0] || + assign _theResult___fst_exp__h584560 = + (!_theResult____h576378[56] && !_theResult____h576378[55] && + !_theResult____h576378[54] && + !_theResult____h576378[53] && + !_theResult____h576378[52] && + !_theResult____h576378[51] && + !_theResult____h576378[50] && + !_theResult____h576378[49] && + !_theResult____h576378[48] && + !_theResult____h576378[47] && + !_theResult____h576378[46] && + !_theResult____h576378[45] && + !_theResult____h576378[44] && + !_theResult____h576378[43] && + !_theResult____h576378[42] && + !_theResult____h576378[41] && + !_theResult____h576378[40] && + !_theResult____h576378[39] && + !_theResult____h576378[38] && + !_theResult____h576378[37] && + !_theResult____h576378[36] && + !_theResult____h576378[35] && + !_theResult____h576378[34] && + !_theResult____h576378[33] && + !_theResult____h576378[32] && + !_theResult____h576378[31] && + !_theResult____h576378[30] && + !_theResult____h576378[29] && + !_theResult____h576378[28] && + !_theResult____h576378[27] && + !_theResult____h576378[26] && + !_theResult____h576378[25] && + !_theResult____h576378[24] && + !_theResult____h576378[23] && + !_theResult____h576378[22] && + !_theResult____h576378[21] && + !_theResult____h576378[20] && + !_theResult____h576378[19] && + !_theResult____h576378[18] && + !_theResult____h576378[17] && + !_theResult____h576378[16] && + !_theResult____h576378[15] && + !_theResult____h576378[14] && + !_theResult____h576378[13] && + !_theResult____h576378[12] && + !_theResult____h576378[11] && + !_theResult____h576378[10] && + !_theResult____h576378[9] && + !_theResult____h576378[8] && + !_theResult____h576378[7] && + !_theResult____h576378[6] && + !_theResult____h576378[5] && + !_theResult____h576378[4] && + !_theResult____h576378[3] && + !_theResult____h576378[2] && + !_theResult____h576378[1] && + !_theResult____h576378[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354) ? 8'd0 : - _theResult___fst_exp__h584557 ; - assign _theResult___fst_exp__h584566 = - (!_theResult____h576381[56] && _theResult____h576381[55]) ? + _theResult___fst_exp__h584554 ; + assign _theResult___fst_exp__h584563 = + (!_theResult____h576378[56] && _theResult____h576378[55]) ? 8'd1 : - _theResult___fst_exp__h584563 ; - assign _theResult___fst_exp__h585089 = - (_theResult___fst_exp__h584492 == 8'd255) ? - _theResult___fst_exp__h584492 : - _theResult___fst_exp__h585086 ; - assign _theResult___fst_exp__h593139 = + _theResult___fst_exp__h584560 ; + assign _theResult___fst_exp__h585086 = + (_theResult___fst_exp__h584489 == 8'd255) ? + _theResult___fst_exp__h584489 : + _theResult___fst_exp__h585083 ; + assign _theResult___fst_exp__h593136 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ; - assign _theResult___fst_exp__h593145 = + assign _theResult___fst_exp__h593142 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585) ? 8'd0 : - _theResult___fst_exp__h593139 ; - assign _theResult___fst_exp__h593148 = + _theResult___fst_exp__h593136 ; + assign _theResult___fst_exp__h593145 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h593145 : + _theResult___fst_exp__h593142 : 8'd129 ; - assign _theResult___fst_exp__h593671 = - (_theResult___fst_exp__h593148 == 8'd255) ? - _theResult___fst_exp__h593148 : - _theResult___fst_exp__h593668 ; - assign _theResult___fst_exp__h602258 = - _theResult____h594020[56] ? + assign _theResult___fst_exp__h593668 = + (_theResult___fst_exp__h593145 == 8'd255) ? + _theResult___fst_exp__h593145 : + _theResult___fst_exp__h593665 ; + assign _theResult___fst_exp__h602255 = + _theResult____h594017[56] ? 8'd2 : - _theResult___fst_exp__h602332 ; - assign _theResult___fst_exp__h602323 = + _theResult___fst_exp__h602329 ; + assign _theResult___fst_exp__h602320 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 } ; - assign _theResult___fst_exp__h602329 = - (!_theResult____h594020[56] && !_theResult____h594020[55] && - !_theResult____h594020[54] && - !_theResult____h594020[53] && - !_theResult____h594020[52] && - !_theResult____h594020[51] && - !_theResult____h594020[50] && - !_theResult____h594020[49] && - !_theResult____h594020[48] && - !_theResult____h594020[47] && - !_theResult____h594020[46] && - !_theResult____h594020[45] && - !_theResult____h594020[44] && - !_theResult____h594020[43] && - !_theResult____h594020[42] && - !_theResult____h594020[41] && - !_theResult____h594020[40] && - !_theResult____h594020[39] && - !_theResult____h594020[38] && - !_theResult____h594020[37] && - !_theResult____h594020[36] && - !_theResult____h594020[35] && - !_theResult____h594020[34] && - !_theResult____h594020[33] && - !_theResult____h594020[32] && - !_theResult____h594020[31] && - !_theResult____h594020[30] && - !_theResult____h594020[29] && - !_theResult____h594020[28] && - !_theResult____h594020[27] && - !_theResult____h594020[26] && - !_theResult____h594020[25] && - !_theResult____h594020[24] && - !_theResult____h594020[23] && - !_theResult____h594020[22] && - !_theResult____h594020[21] && - !_theResult____h594020[20] && - !_theResult____h594020[19] && - !_theResult____h594020[18] && - !_theResult____h594020[17] && - !_theResult____h594020[16] && - !_theResult____h594020[15] && - !_theResult____h594020[14] && - !_theResult____h594020[13] && - !_theResult____h594020[12] && - !_theResult____h594020[11] && - !_theResult____h594020[10] && - !_theResult____h594020[9] && - !_theResult____h594020[8] && - !_theResult____h594020[7] && - !_theResult____h594020[6] && - !_theResult____h594020[5] && - !_theResult____h594020[4] && - !_theResult____h594020[3] && - !_theResult____h594020[2] && - !_theResult____h594020[1] && - !_theResult____h594020[0] || + assign _theResult___fst_exp__h602326 = + (!_theResult____h594017[56] && !_theResult____h594017[55] && + !_theResult____h594017[54] && + !_theResult____h594017[53] && + !_theResult____h594017[52] && + !_theResult____h594017[51] && + !_theResult____h594017[50] && + !_theResult____h594017[49] && + !_theResult____h594017[48] && + !_theResult____h594017[47] && + !_theResult____h594017[46] && + !_theResult____h594017[45] && + !_theResult____h594017[44] && + !_theResult____h594017[43] && + !_theResult____h594017[42] && + !_theResult____h594017[41] && + !_theResult____h594017[40] && + !_theResult____h594017[39] && + !_theResult____h594017[38] && + !_theResult____h594017[37] && + !_theResult____h594017[36] && + !_theResult____h594017[35] && + !_theResult____h594017[34] && + !_theResult____h594017[33] && + !_theResult____h594017[32] && + !_theResult____h594017[31] && + !_theResult____h594017[30] && + !_theResult____h594017[29] && + !_theResult____h594017[28] && + !_theResult____h594017[27] && + !_theResult____h594017[26] && + !_theResult____h594017[25] && + !_theResult____h594017[24] && + !_theResult____h594017[23] && + !_theResult____h594017[22] && + !_theResult____h594017[21] && + !_theResult____h594017[20] && + !_theResult____h594017[19] && + !_theResult____h594017[18] && + !_theResult____h594017[17] && + !_theResult____h594017[16] && + !_theResult____h594017[15] && + !_theResult____h594017[14] && + !_theResult____h594017[13] && + !_theResult____h594017[12] && + !_theResult____h594017[11] && + !_theResult____h594017[10] && + !_theResult____h594017[9] && + !_theResult____h594017[8] && + !_theResult____h594017[7] && + !_theResult____h594017[6] && + !_theResult____h594017[5] && + !_theResult____h594017[4] && + !_theResult____h594017[3] && + !_theResult____h594017[2] && + !_theResult____h594017[1] && + !_theResult____h594017[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905) ? 8'd0 : - _theResult___fst_exp__h602323 ; - assign _theResult___fst_exp__h602332 = - (!_theResult____h594020[56] && _theResult____h594020[55]) ? + _theResult___fst_exp__h602320 ; + assign _theResult___fst_exp__h602329 = + (!_theResult____h594017[56] && _theResult____h594017[55]) ? 8'd1 : - _theResult___fst_exp__h602329 ; - assign _theResult___fst_exp__h602855 = - (_theResult___fst_exp__h602258 == 8'd255) ? - _theResult___fst_exp__h602258 : - _theResult___fst_exp__h602852 ; - assign _theResult___fst_exp__h610895 = + _theResult___fst_exp__h602326 ; + assign _theResult___fst_exp__h602852 = + (_theResult___fst_exp__h602255 == 8'd255) ? + _theResult___fst_exp__h602255 : + _theResult___fst_exp__h602849 ; + assign _theResult___fst_exp__h610892 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] ; - assign _theResult___fst_exp__h610934 = + assign _theResult___fst_exp__h610931 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ; - assign _theResult___fst_exp__h610940 = + assign _theResult___fst_exp__h610937 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978) ? 8'd0 : - _theResult___fst_exp__h610934 ; - assign _theResult___fst_exp__h610943 = + _theResult___fst_exp__h610931 ; + assign _theResult___fst_exp__h610940 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h610937 : + _theResult___fst_exp__h610892 ; + assign _theResult___fst_exp__h611488 = + (_theResult___fst_exp__h610940 == 8'd255) ? _theResult___fst_exp__h610940 : - _theResult___fst_exp__h610895 ; - assign _theResult___fst_exp__h611491 = - (_theResult___fst_exp__h610943 == 8'd255) ? - _theResult___fst_exp__h610943 : - _theResult___fst_exp__h611488 ; - assign _theResult___fst_exp__h611500 = + _theResult___fst_exp__h611485 ; + assign _theResult___fst_exp__h611497 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? - _theResult___snd_fst_exp__h593674 : - _theResult___fst_exp__h576363) : + _theResult___snd_fst_exp__h593671 : + _theResult___fst_exp__h576360) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? - _theResult___snd_fst_exp__h611494 : - _theResult___fst_exp__h576363) ; - assign _theResult___fst_exp__h611503 = + _theResult___snd_fst_exp__h611491 : + _theResult___fst_exp__h576360) ; + assign _theResult___fst_exp__h611500 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h611500 ; - assign _theResult___fst_exp__h630241 = - _theResult____h622132[56] ? + _theResult___fst_exp__h611497 ; + assign _theResult___fst_exp__h630238 = + _theResult____h622129[56] ? 8'd2 : - _theResult___fst_exp__h630315 ; - assign _theResult___fst_exp__h630306 = + _theResult___fst_exp__h630312 ; + assign _theResult___fst_exp__h630303 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 } ; - assign _theResult___fst_exp__h630312 = - (!_theResult____h622132[56] && !_theResult____h622132[55] && - !_theResult____h622132[54] && - !_theResult____h622132[53] && - !_theResult____h622132[52] && - !_theResult____h622132[51] && - !_theResult____h622132[50] && - !_theResult____h622132[49] && - !_theResult____h622132[48] && - !_theResult____h622132[47] && - !_theResult____h622132[46] && - !_theResult____h622132[45] && - !_theResult____h622132[44] && - !_theResult____h622132[43] && - !_theResult____h622132[42] && - !_theResult____h622132[41] && - !_theResult____h622132[40] && - !_theResult____h622132[39] && - !_theResult____h622132[38] && - !_theResult____h622132[37] && - !_theResult____h622132[36] && - !_theResult____h622132[35] && - !_theResult____h622132[34] && - !_theResult____h622132[33] && - !_theResult____h622132[32] && - !_theResult____h622132[31] && - !_theResult____h622132[30] && - !_theResult____h622132[29] && - !_theResult____h622132[28] && - !_theResult____h622132[27] && - !_theResult____h622132[26] && - !_theResult____h622132[25] && - !_theResult____h622132[24] && - !_theResult____h622132[23] && - !_theResult____h622132[22] && - !_theResult____h622132[21] && - !_theResult____h622132[20] && - !_theResult____h622132[19] && - !_theResult____h622132[18] && - !_theResult____h622132[17] && - !_theResult____h622132[16] && - !_theResult____h622132[15] && - !_theResult____h622132[14] && - !_theResult____h622132[13] && - !_theResult____h622132[12] && - !_theResult____h622132[11] && - !_theResult____h622132[10] && - !_theResult____h622132[9] && - !_theResult____h622132[8] && - !_theResult____h622132[7] && - !_theResult____h622132[6] && - !_theResult____h622132[5] && - !_theResult____h622132[4] && - !_theResult____h622132[3] && - !_theResult____h622132[2] && - !_theResult____h622132[1] && - !_theResult____h622132[0] || + assign _theResult___fst_exp__h630309 = + (!_theResult____h622129[56] && !_theResult____h622129[55] && + !_theResult____h622129[54] && + !_theResult____h622129[53] && + !_theResult____h622129[52] && + !_theResult____h622129[51] && + !_theResult____h622129[50] && + !_theResult____h622129[49] && + !_theResult____h622129[48] && + !_theResult____h622129[47] && + !_theResult____h622129[46] && + !_theResult____h622129[45] && + !_theResult____h622129[44] && + !_theResult____h622129[43] && + !_theResult____h622129[42] && + !_theResult____h622129[41] && + !_theResult____h622129[40] && + !_theResult____h622129[39] && + !_theResult____h622129[38] && + !_theResult____h622129[37] && + !_theResult____h622129[36] && + !_theResult____h622129[35] && + !_theResult____h622129[34] && + !_theResult____h622129[33] && + !_theResult____h622129[32] && + !_theResult____h622129[31] && + !_theResult____h622129[30] && + !_theResult____h622129[29] && + !_theResult____h622129[28] && + !_theResult____h622129[27] && + !_theResult____h622129[26] && + !_theResult____h622129[25] && + !_theResult____h622129[24] && + !_theResult____h622129[23] && + !_theResult____h622129[22] && + !_theResult____h622129[21] && + !_theResult____h622129[20] && + !_theResult____h622129[19] && + !_theResult____h622129[18] && + !_theResult____h622129[17] && + !_theResult____h622129[16] && + !_theResult____h622129[15] && + !_theResult____h622129[14] && + !_theResult____h622129[13] && + !_theResult____h622129[12] && + !_theResult____h622129[11] && + !_theResult____h622129[10] && + !_theResult____h622129[9] && + !_theResult____h622129[8] && + !_theResult____h622129[7] && + !_theResult____h622129[6] && + !_theResult____h622129[5] && + !_theResult____h622129[4] && + !_theResult____h622129[3] && + !_theResult____h622129[2] && + !_theResult____h622129[1] && + !_theResult____h622129[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751) ? 8'd0 : - _theResult___fst_exp__h630306 ; - assign _theResult___fst_exp__h630315 = - (!_theResult____h622132[56] && _theResult____h622132[55]) ? + _theResult___fst_exp__h630303 ; + assign _theResult___fst_exp__h630312 = + (!_theResult____h622129[56] && _theResult____h622129[55]) ? 8'd1 : - _theResult___fst_exp__h630312 ; - assign _theResult___fst_exp__h630838 = - (_theResult___fst_exp__h630241 == 8'd255) ? - _theResult___fst_exp__h630241 : - _theResult___fst_exp__h630835 ; - assign _theResult___fst_exp__h638888 = + _theResult___fst_exp__h630309 ; + assign _theResult___fst_exp__h630835 = + (_theResult___fst_exp__h630238 == 8'd255) ? + _theResult___fst_exp__h630238 : + _theResult___fst_exp__h630832 ; + assign _theResult___fst_exp__h638885 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ; - assign _theResult___fst_exp__h638894 = + assign _theResult___fst_exp__h638891 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982) ? 8'd0 : - _theResult___fst_exp__h638888 ; - assign _theResult___fst_exp__h638897 = + _theResult___fst_exp__h638885 ; + assign _theResult___fst_exp__h638894 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h638894 : + _theResult___fst_exp__h638891 : 8'd129 ; - assign _theResult___fst_exp__h639420 = - (_theResult___fst_exp__h638897 == 8'd255) ? - _theResult___fst_exp__h638897 : - _theResult___fst_exp__h639417 ; - assign _theResult___fst_exp__h648007 = - _theResult____h639769[56] ? + assign _theResult___fst_exp__h639417 = + (_theResult___fst_exp__h638894 == 8'd255) ? + _theResult___fst_exp__h638894 : + _theResult___fst_exp__h639414 ; + assign _theResult___fst_exp__h648004 = + _theResult____h639766[56] ? 8'd2 : - _theResult___fst_exp__h648081 ; - assign _theResult___fst_exp__h648072 = + _theResult___fst_exp__h648078 ; + assign _theResult___fst_exp__h648069 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 } ; - assign _theResult___fst_exp__h648078 = - (!_theResult____h639769[56] && !_theResult____h639769[55] && - !_theResult____h639769[54] && - !_theResult____h639769[53] && - !_theResult____h639769[52] && - !_theResult____h639769[51] && - !_theResult____h639769[50] && - !_theResult____h639769[49] && - !_theResult____h639769[48] && - !_theResult____h639769[47] && - !_theResult____h639769[46] && - !_theResult____h639769[45] && - !_theResult____h639769[44] && - !_theResult____h639769[43] && - !_theResult____h639769[42] && - !_theResult____h639769[41] && - !_theResult____h639769[40] && - !_theResult____h639769[39] && - !_theResult____h639769[38] && - !_theResult____h639769[37] && - !_theResult____h639769[36] && - !_theResult____h639769[35] && - !_theResult____h639769[34] && - !_theResult____h639769[33] && - !_theResult____h639769[32] && - !_theResult____h639769[31] && - !_theResult____h639769[30] && - !_theResult____h639769[29] && - !_theResult____h639769[28] && - !_theResult____h639769[27] && - !_theResult____h639769[26] && - !_theResult____h639769[25] && - !_theResult____h639769[24] && - !_theResult____h639769[23] && - !_theResult____h639769[22] && - !_theResult____h639769[21] && - !_theResult____h639769[20] && - !_theResult____h639769[19] && - !_theResult____h639769[18] && - !_theResult____h639769[17] && - !_theResult____h639769[16] && - !_theResult____h639769[15] && - !_theResult____h639769[14] && - !_theResult____h639769[13] && - !_theResult____h639769[12] && - !_theResult____h639769[11] && - !_theResult____h639769[10] && - !_theResult____h639769[9] && - !_theResult____h639769[8] && - !_theResult____h639769[7] && - !_theResult____h639769[6] && - !_theResult____h639769[5] && - !_theResult____h639769[4] && - !_theResult____h639769[3] && - !_theResult____h639769[2] && - !_theResult____h639769[1] && - !_theResult____h639769[0] || + assign _theResult___fst_exp__h648075 = + (!_theResult____h639766[56] && !_theResult____h639766[55] && + !_theResult____h639766[54] && + !_theResult____h639766[53] && + !_theResult____h639766[52] && + !_theResult____h639766[51] && + !_theResult____h639766[50] && + !_theResult____h639766[49] && + !_theResult____h639766[48] && + !_theResult____h639766[47] && + !_theResult____h639766[46] && + !_theResult____h639766[45] && + !_theResult____h639766[44] && + !_theResult____h639766[43] && + !_theResult____h639766[42] && + !_theResult____h639766[41] && + !_theResult____h639766[40] && + !_theResult____h639766[39] && + !_theResult____h639766[38] && + !_theResult____h639766[37] && + !_theResult____h639766[36] && + !_theResult____h639766[35] && + !_theResult____h639766[34] && + !_theResult____h639766[33] && + !_theResult____h639766[32] && + !_theResult____h639766[31] && + !_theResult____h639766[30] && + !_theResult____h639766[29] && + !_theResult____h639766[28] && + !_theResult____h639766[27] && + !_theResult____h639766[26] && + !_theResult____h639766[25] && + !_theResult____h639766[24] && + !_theResult____h639766[23] && + !_theResult____h639766[22] && + !_theResult____h639766[21] && + !_theResult____h639766[20] && + !_theResult____h639766[19] && + !_theResult____h639766[18] && + !_theResult____h639766[17] && + !_theResult____h639766[16] && + !_theResult____h639766[15] && + !_theResult____h639766[14] && + !_theResult____h639766[13] && + !_theResult____h639766[12] && + !_theResult____h639766[11] && + !_theResult____h639766[10] && + !_theResult____h639766[9] && + !_theResult____h639766[8] && + !_theResult____h639766[7] && + !_theResult____h639766[6] && + !_theResult____h639766[5] && + !_theResult____h639766[4] && + !_theResult____h639766[3] && + !_theResult____h639766[2] && + !_theResult____h639766[1] && + !_theResult____h639766[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302) ? 8'd0 : - _theResult___fst_exp__h648072 ; - assign _theResult___fst_exp__h648081 = - (!_theResult____h639769[56] && _theResult____h639769[55]) ? + _theResult___fst_exp__h648069 ; + assign _theResult___fst_exp__h648078 = + (!_theResult____h639766[56] && _theResult____h639766[55]) ? 8'd1 : - _theResult___fst_exp__h648078 ; - assign _theResult___fst_exp__h648604 = - (_theResult___fst_exp__h648007 == 8'd255) ? - _theResult___fst_exp__h648007 : - _theResult___fst_exp__h648601 ; - assign _theResult___fst_exp__h656644 = + _theResult___fst_exp__h648075 ; + assign _theResult___fst_exp__h648601 = + (_theResult___fst_exp__h648004 == 8'd255) ? + _theResult___fst_exp__h648004 : + _theResult___fst_exp__h648598 ; + assign _theResult___fst_exp__h656641 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] ; - assign _theResult___fst_exp__h656683 = + assign _theResult___fst_exp__h656680 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ; - assign _theResult___fst_exp__h656689 = + assign _theResult___fst_exp__h656686 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375) ? 8'd0 : - _theResult___fst_exp__h656683 ; - assign _theResult___fst_exp__h656692 = + _theResult___fst_exp__h656680 ; + assign _theResult___fst_exp__h656689 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h656686 : + _theResult___fst_exp__h656641 ; + assign _theResult___fst_exp__h657237 = + (_theResult___fst_exp__h656689 == 8'd255) ? _theResult___fst_exp__h656689 : - _theResult___fst_exp__h656644 ; - assign _theResult___fst_exp__h657240 = - (_theResult___fst_exp__h656692 == 8'd255) ? - _theResult___fst_exp__h656692 : - _theResult___fst_exp__h657237 ; - assign _theResult___fst_exp__h657249 = + _theResult___fst_exp__h657234 ; + assign _theResult___fst_exp__h657246 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? - _theResult___snd_fst_exp__h639423 : - _theResult___fst_exp__h622114) : + _theResult___snd_fst_exp__h639420 : + _theResult___fst_exp__h622111) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? - _theResult___snd_fst_exp__h657243 : - _theResult___fst_exp__h622114) ; - assign _theResult___fst_exp__h657252 = + _theResult___snd_fst_exp__h657240 : + _theResult___fst_exp__h622111) ; + assign _theResult___fst_exp__h657249 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h657249 ; - assign _theResult___fst_exp__h675988 = - _theResult____h667879[56] ? + _theResult___fst_exp__h657246 ; + assign _theResult___fst_exp__h675985 = + _theResult____h667876[56] ? 8'd2 : - _theResult___fst_exp__h676062 ; - assign _theResult___fst_exp__h676053 = + _theResult___fst_exp__h676059 ; + assign _theResult___fst_exp__h676050 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 } ; - assign _theResult___fst_exp__h676059 = - (!_theResult____h667879[56] && !_theResult____h667879[55] && - !_theResult____h667879[54] && - !_theResult____h667879[53] && - !_theResult____h667879[52] && - !_theResult____h667879[51] && - !_theResult____h667879[50] && - !_theResult____h667879[49] && - !_theResult____h667879[48] && - !_theResult____h667879[47] && - !_theResult____h667879[46] && - !_theResult____h667879[45] && - !_theResult____h667879[44] && - !_theResult____h667879[43] && - !_theResult____h667879[42] && - !_theResult____h667879[41] && - !_theResult____h667879[40] && - !_theResult____h667879[39] && - !_theResult____h667879[38] && - !_theResult____h667879[37] && - !_theResult____h667879[36] && - !_theResult____h667879[35] && - !_theResult____h667879[34] && - !_theResult____h667879[33] && - !_theResult____h667879[32] && - !_theResult____h667879[31] && - !_theResult____h667879[30] && - !_theResult____h667879[29] && - !_theResult____h667879[28] && - !_theResult____h667879[27] && - !_theResult____h667879[26] && - !_theResult____h667879[25] && - !_theResult____h667879[24] && - !_theResult____h667879[23] && - !_theResult____h667879[22] && - !_theResult____h667879[21] && - !_theResult____h667879[20] && - !_theResult____h667879[19] && - !_theResult____h667879[18] && - !_theResult____h667879[17] && - !_theResult____h667879[16] && - !_theResult____h667879[15] && - !_theResult____h667879[14] && - !_theResult____h667879[13] && - !_theResult____h667879[12] && - !_theResult____h667879[11] && - !_theResult____h667879[10] && - !_theResult____h667879[9] && - !_theResult____h667879[8] && - !_theResult____h667879[7] && - !_theResult____h667879[6] && - !_theResult____h667879[5] && - !_theResult____h667879[4] && - !_theResult____h667879[3] && - !_theResult____h667879[2] && - !_theResult____h667879[1] && - !_theResult____h667879[0] || + assign _theResult___fst_exp__h676056 = + (!_theResult____h667876[56] && !_theResult____h667876[55] && + !_theResult____h667876[54] && + !_theResult____h667876[53] && + !_theResult____h667876[52] && + !_theResult____h667876[51] && + !_theResult____h667876[50] && + !_theResult____h667876[49] && + !_theResult____h667876[48] && + !_theResult____h667876[47] && + !_theResult____h667876[46] && + !_theResult____h667876[45] && + !_theResult____h667876[44] && + !_theResult____h667876[43] && + !_theResult____h667876[42] && + !_theResult____h667876[41] && + !_theResult____h667876[40] && + !_theResult____h667876[39] && + !_theResult____h667876[38] && + !_theResult____h667876[37] && + !_theResult____h667876[36] && + !_theResult____h667876[35] && + !_theResult____h667876[34] && + !_theResult____h667876[33] && + !_theResult____h667876[32] && + !_theResult____h667876[31] && + !_theResult____h667876[30] && + !_theResult____h667876[29] && + !_theResult____h667876[28] && + !_theResult____h667876[27] && + !_theResult____h667876[26] && + !_theResult____h667876[25] && + !_theResult____h667876[24] && + !_theResult____h667876[23] && + !_theResult____h667876[22] && + !_theResult____h667876[21] && + !_theResult____h667876[20] && + !_theResult____h667876[19] && + !_theResult____h667876[18] && + !_theResult____h667876[17] && + !_theResult____h667876[16] && + !_theResult____h667876[15] && + !_theResult____h667876[14] && + !_theResult____h667876[13] && + !_theResult____h667876[12] && + !_theResult____h667876[11] && + !_theResult____h667876[10] && + !_theResult____h667876[9] && + !_theResult____h667876[8] && + !_theResult____h667876[7] && + !_theResult____h667876[6] && + !_theResult____h667876[5] && + !_theResult____h667876[4] && + !_theResult____h667876[3] && + !_theResult____h667876[2] && + !_theResult____h667876[1] && + !_theResult____h667876[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148) ? 8'd0 : - _theResult___fst_exp__h676053 ; - assign _theResult___fst_exp__h676062 = - (!_theResult____h667879[56] && _theResult____h667879[55]) ? + _theResult___fst_exp__h676050 ; + assign _theResult___fst_exp__h676059 = + (!_theResult____h667876[56] && _theResult____h667876[55]) ? 8'd1 : - _theResult___fst_exp__h676059 ; - assign _theResult___fst_exp__h676585 = - (_theResult___fst_exp__h675988 == 8'd255) ? - _theResult___fst_exp__h675988 : - _theResult___fst_exp__h676582 ; - assign _theResult___fst_exp__h684635 = + _theResult___fst_exp__h676056 ; + assign _theResult___fst_exp__h676582 = + (_theResult___fst_exp__h675985 == 8'd255) ? + _theResult___fst_exp__h675985 : + _theResult___fst_exp__h676579 ; + assign _theResult___fst_exp__h684632 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ; - assign _theResult___fst_exp__h684641 = + assign _theResult___fst_exp__h684638 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379) ? 8'd0 : - _theResult___fst_exp__h684635 ; - assign _theResult___fst_exp__h684644 = + _theResult___fst_exp__h684632 ; + assign _theResult___fst_exp__h684641 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h684641 : + _theResult___fst_exp__h684638 : 8'd129 ; - assign _theResult___fst_exp__h685167 = - (_theResult___fst_exp__h684644 == 8'd255) ? - _theResult___fst_exp__h684644 : - _theResult___fst_exp__h685164 ; - assign _theResult___fst_exp__h693754 = - _theResult____h685516[56] ? + assign _theResult___fst_exp__h685164 = + (_theResult___fst_exp__h684641 == 8'd255) ? + _theResult___fst_exp__h684641 : + _theResult___fst_exp__h685161 ; + assign _theResult___fst_exp__h693751 = + _theResult____h685513[56] ? 8'd2 : - _theResult___fst_exp__h693828 ; - assign _theResult___fst_exp__h693819 = + _theResult___fst_exp__h693825 ; + assign _theResult___fst_exp__h693816 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 } ; - assign _theResult___fst_exp__h693825 = - (!_theResult____h685516[56] && !_theResult____h685516[55] && - !_theResult____h685516[54] && - !_theResult____h685516[53] && - !_theResult____h685516[52] && - !_theResult____h685516[51] && - !_theResult____h685516[50] && - !_theResult____h685516[49] && - !_theResult____h685516[48] && - !_theResult____h685516[47] && - !_theResult____h685516[46] && - !_theResult____h685516[45] && - !_theResult____h685516[44] && - !_theResult____h685516[43] && - !_theResult____h685516[42] && - !_theResult____h685516[41] && - !_theResult____h685516[40] && - !_theResult____h685516[39] && - !_theResult____h685516[38] && - !_theResult____h685516[37] && - !_theResult____h685516[36] && - !_theResult____h685516[35] && - !_theResult____h685516[34] && - !_theResult____h685516[33] && - !_theResult____h685516[32] && - !_theResult____h685516[31] && - !_theResult____h685516[30] && - !_theResult____h685516[29] && - !_theResult____h685516[28] && - !_theResult____h685516[27] && - !_theResult____h685516[26] && - !_theResult____h685516[25] && - !_theResult____h685516[24] && - !_theResult____h685516[23] && - !_theResult____h685516[22] && - !_theResult____h685516[21] && - !_theResult____h685516[20] && - !_theResult____h685516[19] && - !_theResult____h685516[18] && - !_theResult____h685516[17] && - !_theResult____h685516[16] && - !_theResult____h685516[15] && - !_theResult____h685516[14] && - !_theResult____h685516[13] && - !_theResult____h685516[12] && - !_theResult____h685516[11] && - !_theResult____h685516[10] && - !_theResult____h685516[9] && - !_theResult____h685516[8] && - !_theResult____h685516[7] && - !_theResult____h685516[6] && - !_theResult____h685516[5] && - !_theResult____h685516[4] && - !_theResult____h685516[3] && - !_theResult____h685516[2] && - !_theResult____h685516[1] && - !_theResult____h685516[0] || + assign _theResult___fst_exp__h693822 = + (!_theResult____h685513[56] && !_theResult____h685513[55] && + !_theResult____h685513[54] && + !_theResult____h685513[53] && + !_theResult____h685513[52] && + !_theResult____h685513[51] && + !_theResult____h685513[50] && + !_theResult____h685513[49] && + !_theResult____h685513[48] && + !_theResult____h685513[47] && + !_theResult____h685513[46] && + !_theResult____h685513[45] && + !_theResult____h685513[44] && + !_theResult____h685513[43] && + !_theResult____h685513[42] && + !_theResult____h685513[41] && + !_theResult____h685513[40] && + !_theResult____h685513[39] && + !_theResult____h685513[38] && + !_theResult____h685513[37] && + !_theResult____h685513[36] && + !_theResult____h685513[35] && + !_theResult____h685513[34] && + !_theResult____h685513[33] && + !_theResult____h685513[32] && + !_theResult____h685513[31] && + !_theResult____h685513[30] && + !_theResult____h685513[29] && + !_theResult____h685513[28] && + !_theResult____h685513[27] && + !_theResult____h685513[26] && + !_theResult____h685513[25] && + !_theResult____h685513[24] && + !_theResult____h685513[23] && + !_theResult____h685513[22] && + !_theResult____h685513[21] && + !_theResult____h685513[20] && + !_theResult____h685513[19] && + !_theResult____h685513[18] && + !_theResult____h685513[17] && + !_theResult____h685513[16] && + !_theResult____h685513[15] && + !_theResult____h685513[14] && + !_theResult____h685513[13] && + !_theResult____h685513[12] && + !_theResult____h685513[11] && + !_theResult____h685513[10] && + !_theResult____h685513[9] && + !_theResult____h685513[8] && + !_theResult____h685513[7] && + !_theResult____h685513[6] && + !_theResult____h685513[5] && + !_theResult____h685513[4] && + !_theResult____h685513[3] && + !_theResult____h685513[2] && + !_theResult____h685513[1] && + !_theResult____h685513[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699) ? 8'd0 : - _theResult___fst_exp__h693819 ; - assign _theResult___fst_exp__h693828 = - (!_theResult____h685516[56] && _theResult____h685516[55]) ? + _theResult___fst_exp__h693816 ; + assign _theResult___fst_exp__h693825 = + (!_theResult____h685513[56] && _theResult____h685513[55]) ? 8'd1 : - _theResult___fst_exp__h693825 ; - assign _theResult___fst_exp__h694351 = - (_theResult___fst_exp__h693754 == 8'd255) ? - _theResult___fst_exp__h693754 : - _theResult___fst_exp__h694348 ; - assign _theResult___fst_exp__h702391 = + _theResult___fst_exp__h693822 ; + assign _theResult___fst_exp__h694348 = + (_theResult___fst_exp__h693751 == 8'd255) ? + _theResult___fst_exp__h693751 : + _theResult___fst_exp__h694345 ; + assign _theResult___fst_exp__h702388 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] ; - assign _theResult___fst_exp__h702430 = + assign _theResult___fst_exp__h702427 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ; - assign _theResult___fst_exp__h702436 = + assign _theResult___fst_exp__h702433 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772) ? 8'd0 : - _theResult___fst_exp__h702430 ; - assign _theResult___fst_exp__h702439 = + _theResult___fst_exp__h702427 ; + assign _theResult___fst_exp__h702436 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h702433 : + _theResult___fst_exp__h702388 ; + assign _theResult___fst_exp__h702984 = + (_theResult___fst_exp__h702436 == 8'd255) ? _theResult___fst_exp__h702436 : - _theResult___fst_exp__h702391 ; - assign _theResult___fst_exp__h702987 = - (_theResult___fst_exp__h702439 == 8'd255) ? - _theResult___fst_exp__h702439 : - _theResult___fst_exp__h702984 ; - assign _theResult___fst_exp__h702996 = + _theResult___fst_exp__h702981 ; + assign _theResult___fst_exp__h702993 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? - _theResult___snd_fst_exp__h685170 : - _theResult___fst_exp__h667861) : + _theResult___snd_fst_exp__h685167 : + _theResult___fst_exp__h667858) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? - _theResult___snd_fst_exp__h702990 : - _theResult___fst_exp__h667861) ; - assign _theResult___fst_exp__h702999 = + _theResult___snd_fst_exp__h702987 : + _theResult___fst_exp__h667858) ; + assign _theResult___fst_exp__h702996 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h702996 ; - assign _theResult___fst_exp__h719140 = + _theResult___fst_exp__h702993 ; + assign _theResult___fst_exp__h719137 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26 ; - assign _theResult___fst_exp__h734204 = + assign _theResult___fst_exp__h734201 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ; - assign _theResult___fst_exp__h734210 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___fst_exp__h734207 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718) ? 11'd0 : - _theResult___fst_exp__h734204 ; - assign _theResult___fst_exp__h734213 = - (f1_exp__h714825 == 8'd0) ? - _theResult___fst_exp__h734210 : + _theResult___fst_exp__h734201 ; + assign _theResult___fst_exp__h734210 = + (f1_exp__h714822 == 8'd0) ? + _theResult___fst_exp__h734207 : 11'd897 ; - assign _theResult___fst_exp__h734968 = + assign _theResult___fst_exp__h734965 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 : + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 ; - assign _theResult___fst_exp__h734971 = - (_theResult___fst_exp__h734213 == 11'd2047) ? - _theResult___fst_exp__h734213 : - _theResult___fst_exp__h734968 ; - assign _theResult___fst_exp__h743790 = - _theResult____h735554[56] ? + assign _theResult___fst_exp__h734968 = + (_theResult___fst_exp__h734210 == 11'd2047) ? + _theResult___fst_exp__h734210 : + _theResult___fst_exp__h734965 ; + assign _theResult___fst_exp__h743787 = + _theResult____h735551[56] ? 11'd2 : - _theResult___fst_exp__h743864 ; - assign _theResult___fst_exp__h743855 = + _theResult___fst_exp__h743861 ; + assign _theResult___fst_exp__h743852 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 } ; - assign _theResult___fst_exp__h743861 = - (!_theResult____h735554[56] && !_theResult____h735554[55] && - !_theResult____h735554[54] && - !_theResult____h735554[53] && - !_theResult____h735554[52] && - !_theResult____h735554[51] && - !_theResult____h735554[50] && - !_theResult____h735554[49] && - !_theResult____h735554[48] && - !_theResult____h735554[47] && - !_theResult____h735554[46] && - !_theResult____h735554[45] && - !_theResult____h735554[44] && - !_theResult____h735554[43] && - !_theResult____h735554[42] && - !_theResult____h735554[41] && - !_theResult____h735554[40] && - !_theResult____h735554[39] && - !_theResult____h735554[38] && - !_theResult____h735554[37] && - !_theResult____h735554[36] && - !_theResult____h735554[35] && - !_theResult____h735554[34] && - !_theResult____h735554[33] && - !_theResult____h735554[32] && - !_theResult____h735554[31] && - !_theResult____h735554[30] && - !_theResult____h735554[29] && - !_theResult____h735554[28] && - !_theResult____h735554[27] && - !_theResult____h735554[26] && - !_theResult____h735554[25] && - !_theResult____h735554[24] && - !_theResult____h735554[23] && - !_theResult____h735554[22] && - !_theResult____h735554[21] && - !_theResult____h735554[20] && - !_theResult____h735554[19] && - !_theResult____h735554[18] && - !_theResult____h735554[17] && - !_theResult____h735554[16] && - !_theResult____h735554[15] && - !_theResult____h735554[14] && - !_theResult____h735554[13] && - !_theResult____h735554[12] && - !_theResult____h735554[11] && - !_theResult____h735554[10] && - !_theResult____h735554[9] && - !_theResult____h735554[8] && - !_theResult____h735554[7] && - !_theResult____h735554[6] && - !_theResult____h735554[5] && - !_theResult____h735554[4] && - !_theResult____h735554[3] && - !_theResult____h735554[2] && - !_theResult____h735554[1] && - !_theResult____h735554[0] || + assign _theResult___fst_exp__h743858 = + (!_theResult____h735551[56] && !_theResult____h735551[55] && + !_theResult____h735551[54] && + !_theResult____h735551[53] && + !_theResult____h735551[52] && + !_theResult____h735551[51] && + !_theResult____h735551[50] && + !_theResult____h735551[49] && + !_theResult____h735551[48] && + !_theResult____h735551[47] && + !_theResult____h735551[46] && + !_theResult____h735551[45] && + !_theResult____h735551[44] && + !_theResult____h735551[43] && + !_theResult____h735551[42] && + !_theResult____h735551[41] && + !_theResult____h735551[40] && + !_theResult____h735551[39] && + !_theResult____h735551[38] && + !_theResult____h735551[37] && + !_theResult____h735551[36] && + !_theResult____h735551[35] && + !_theResult____h735551[34] && + !_theResult____h735551[33] && + !_theResult____h735551[32] && + !_theResult____h735551[31] && + !_theResult____h735551[30] && + !_theResult____h735551[29] && + !_theResult____h735551[28] && + !_theResult____h735551[27] && + !_theResult____h735551[26] && + !_theResult____h735551[25] && + !_theResult____h735551[24] && + !_theResult____h735551[23] && + !_theResult____h735551[22] && + !_theResult____h735551[21] && + !_theResult____h735551[20] && + !_theResult____h735551[19] && + !_theResult____h735551[18] && + !_theResult____h735551[17] && + !_theResult____h735551[16] && + !_theResult____h735551[15] && + !_theResult____h735551[14] && + !_theResult____h735551[13] && + !_theResult____h735551[12] && + !_theResult____h735551[11] && + !_theResult____h735551[10] && + !_theResult____h735551[9] && + !_theResult____h735551[8] && + !_theResult____h735551[7] && + !_theResult____h735551[6] && + !_theResult____h735551[5] && + !_theResult____h735551[4] && + !_theResult____h735551[3] && + !_theResult____h735551[2] && + !_theResult____h735551[1] && + !_theResult____h735551[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030) ? 11'd0 : - _theResult___fst_exp__h743855 ; - assign _theResult___fst_exp__h743864 = - (!_theResult____h735554[56] && _theResult____h735554[55]) ? + _theResult___fst_exp__h743852 ; + assign _theResult___fst_exp__h743861 = + (!_theResult____h735551[56] && _theResult____h735551[55]) ? 11'd1 : - _theResult___fst_exp__h743861 ; - assign _theResult___fst_exp__h744619 = + _theResult___fst_exp__h743858 ; + assign _theResult___fst_exp__h744616 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 : + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 ; - assign _theResult___fst_exp__h744622 = - (_theResult___fst_exp__h743790 == 11'd2047) ? - _theResult___fst_exp__h743790 : - _theResult___fst_exp__h744619 ; - assign _theResult___fst_exp__h752575 = + assign _theResult___fst_exp__h744619 = + (_theResult___fst_exp__h743787 == 11'd2047) ? + _theResult___fst_exp__h743787 : + _theResult___fst_exp__h744616 ; + assign _theResult___fst_exp__h752572 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] ; - assign _theResult___fst_exp__h752614 = + assign _theResult___fst_exp__h752611 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ; - assign _theResult___fst_exp__h752620 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___fst_exp__h752617 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080) ? 11'd0 : - _theResult___fst_exp__h752614 ; - assign _theResult___fst_exp__h752623 = - (f1_exp__h714825 == 8'd0) ? - _theResult___fst_exp__h752620 : - _theResult___fst_exp__h752575 ; - assign _theResult___fst_exp__h753403 = + _theResult___fst_exp__h752611 ; + assign _theResult___fst_exp__h752620 = + (f1_exp__h714822 == 8'd0) ? + _theResult___fst_exp__h752617 : + _theResult___fst_exp__h752572 ; + assign _theResult___fst_exp__h753400 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 : + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 ; - assign _theResult___fst_exp__h753406 = - (_theResult___fst_exp__h752623 == 11'd2047) ? - _theResult___fst_exp__h752623 : - _theResult___fst_exp__h753403 ; - assign _theResult___fst_exp__h753415 = - (f1_exp__h714825 == 8'd0) ? + assign _theResult___fst_exp__h753403 = + (_theResult___fst_exp__h752620 == 11'd2047) ? + _theResult___fst_exp__h752620 : + _theResult___fst_exp__h753400 ; + assign _theResult___fst_exp__h753412 = + (f1_exp__h714822 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 ? - _theResult___snd_fst_exp__h734974 : - _theResult___fst_exp__h719140) : + _theResult___snd_fst_exp__h734971 : + _theResult___fst_exp__h719137) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 ? - _theResult___snd_fst_exp__h753409 : - _theResult___fst_exp__h719140) ; - assign _theResult___fst_exp__h753418 = - (f1_exp__h714825 == 8'd0 && f1_sfd__h714826 == 23'd0) ? + _theResult___snd_fst_exp__h753406 : + _theResult___fst_exp__h719137) ; + assign _theResult___fst_exp__h753415 = + (f1_exp__h714822 == 8'd0 && f1_sfd__h714823 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h753415 ; - assign _theResult___fst_exp__h757993 = + _theResult___fst_exp__h753412 ; + assign _theResult___fst_exp__h757990 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 ; - assign _theResult___fst_exp__h773057 = + assign _theResult___fst_exp__h773054 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ; - assign _theResult___fst_exp__h773063 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___fst_exp__h773060 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218) ? 11'd0 : - _theResult___fst_exp__h773057 ; - assign _theResult___fst_exp__h773066 = - (f2_exp__h753819 == 8'd0) ? - _theResult___fst_exp__h773063 : + _theResult___fst_exp__h773054 ; + assign _theResult___fst_exp__h773063 = + (f2_exp__h753816 == 8'd0) ? + _theResult___fst_exp__h773060 : 11'd897 ; - assign _theResult___fst_exp__h773821 = + assign _theResult___fst_exp__h773818 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 : + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 ; - assign _theResult___fst_exp__h773824 = - (_theResult___fst_exp__h773066 == 11'd2047) ? - _theResult___fst_exp__h773066 : - _theResult___fst_exp__h773821 ; - assign _theResult___fst_exp__h782643 = - _theResult____h774407[56] ? + assign _theResult___fst_exp__h773821 = + (_theResult___fst_exp__h773063 == 11'd2047) ? + _theResult___fst_exp__h773063 : + _theResult___fst_exp__h773818 ; + assign _theResult___fst_exp__h782640 = + _theResult____h774404[56] ? 11'd2 : - _theResult___fst_exp__h782717 ; - assign _theResult___fst_exp__h782708 = + _theResult___fst_exp__h782714 ; + assign _theResult___fst_exp__h782705 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 } ; - assign _theResult___fst_exp__h782714 = - (!_theResult____h774407[56] && !_theResult____h774407[55] && - !_theResult____h774407[54] && - !_theResult____h774407[53] && - !_theResult____h774407[52] && - !_theResult____h774407[51] && - !_theResult____h774407[50] && - !_theResult____h774407[49] && - !_theResult____h774407[48] && - !_theResult____h774407[47] && - !_theResult____h774407[46] && - !_theResult____h774407[45] && - !_theResult____h774407[44] && - !_theResult____h774407[43] && - !_theResult____h774407[42] && - !_theResult____h774407[41] && - !_theResult____h774407[40] && - !_theResult____h774407[39] && - !_theResult____h774407[38] && - !_theResult____h774407[37] && - !_theResult____h774407[36] && - !_theResult____h774407[35] && - !_theResult____h774407[34] && - !_theResult____h774407[33] && - !_theResult____h774407[32] && - !_theResult____h774407[31] && - !_theResult____h774407[30] && - !_theResult____h774407[29] && - !_theResult____h774407[28] && - !_theResult____h774407[27] && - !_theResult____h774407[26] && - !_theResult____h774407[25] && - !_theResult____h774407[24] && - !_theResult____h774407[23] && - !_theResult____h774407[22] && - !_theResult____h774407[21] && - !_theResult____h774407[20] && - !_theResult____h774407[19] && - !_theResult____h774407[18] && - !_theResult____h774407[17] && - !_theResult____h774407[16] && - !_theResult____h774407[15] && - !_theResult____h774407[14] && - !_theResult____h774407[13] && - !_theResult____h774407[12] && - !_theResult____h774407[11] && - !_theResult____h774407[10] && - !_theResult____h774407[9] && - !_theResult____h774407[8] && - !_theResult____h774407[7] && - !_theResult____h774407[6] && - !_theResult____h774407[5] && - !_theResult____h774407[4] && - !_theResult____h774407[3] && - !_theResult____h774407[2] && - !_theResult____h774407[1] && - !_theResult____h774407[0] || + assign _theResult___fst_exp__h782711 = + (!_theResult____h774404[56] && !_theResult____h774404[55] && + !_theResult____h774404[54] && + !_theResult____h774404[53] && + !_theResult____h774404[52] && + !_theResult____h774404[51] && + !_theResult____h774404[50] && + !_theResult____h774404[49] && + !_theResult____h774404[48] && + !_theResult____h774404[47] && + !_theResult____h774404[46] && + !_theResult____h774404[45] && + !_theResult____h774404[44] && + !_theResult____h774404[43] && + !_theResult____h774404[42] && + !_theResult____h774404[41] && + !_theResult____h774404[40] && + !_theResult____h774404[39] && + !_theResult____h774404[38] && + !_theResult____h774404[37] && + !_theResult____h774404[36] && + !_theResult____h774404[35] && + !_theResult____h774404[34] && + !_theResult____h774404[33] && + !_theResult____h774404[32] && + !_theResult____h774404[31] && + !_theResult____h774404[30] && + !_theResult____h774404[29] && + !_theResult____h774404[28] && + !_theResult____h774404[27] && + !_theResult____h774404[26] && + !_theResult____h774404[25] && + !_theResult____h774404[24] && + !_theResult____h774404[23] && + !_theResult____h774404[22] && + !_theResult____h774404[21] && + !_theResult____h774404[20] && + !_theResult____h774404[19] && + !_theResult____h774404[18] && + !_theResult____h774404[17] && + !_theResult____h774404[16] && + !_theResult____h774404[15] && + !_theResult____h774404[14] && + !_theResult____h774404[13] && + !_theResult____h774404[12] && + !_theResult____h774404[11] && + !_theResult____h774404[10] && + !_theResult____h774404[9] && + !_theResult____h774404[8] && + !_theResult____h774404[7] && + !_theResult____h774404[6] && + !_theResult____h774404[5] && + !_theResult____h774404[4] && + !_theResult____h774404[3] && + !_theResult____h774404[2] && + !_theResult____h774404[1] && + !_theResult____h774404[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515) ? 11'd0 : - _theResult___fst_exp__h782708 ; - assign _theResult___fst_exp__h782717 = - (!_theResult____h774407[56] && _theResult____h774407[55]) ? + _theResult___fst_exp__h782705 ; + assign _theResult___fst_exp__h782714 = + (!_theResult____h774404[56] && _theResult____h774404[55]) ? 11'd1 : - _theResult___fst_exp__h782714 ; - assign _theResult___fst_exp__h783472 = + _theResult___fst_exp__h782711 ; + assign _theResult___fst_exp__h783469 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 : + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 ; - assign _theResult___fst_exp__h783475 = - (_theResult___fst_exp__h782643 == 11'd2047) ? - _theResult___fst_exp__h782643 : - _theResult___fst_exp__h783472 ; - assign _theResult___fst_exp__h791428 = + assign _theResult___fst_exp__h783472 = + (_theResult___fst_exp__h782640 == 11'd2047) ? + _theResult___fst_exp__h782640 : + _theResult___fst_exp__h783469 ; + assign _theResult___fst_exp__h791425 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] ; - assign _theResult___fst_exp__h791467 = + assign _theResult___fst_exp__h791464 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ; - assign _theResult___fst_exp__h791473 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___fst_exp__h791470 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565) ? 11'd0 : - _theResult___fst_exp__h791467 ; - assign _theResult___fst_exp__h791476 = - (f2_exp__h753819 == 8'd0) ? - _theResult___fst_exp__h791473 : - _theResult___fst_exp__h791428 ; - assign _theResult___fst_exp__h792256 = + _theResult___fst_exp__h791464 ; + assign _theResult___fst_exp__h791473 = + (f2_exp__h753816 == 8'd0) ? + _theResult___fst_exp__h791470 : + _theResult___fst_exp__h791425 ; + assign _theResult___fst_exp__h792253 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 : + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 ; - assign _theResult___fst_exp__h792259 = - (_theResult___fst_exp__h791476 == 11'd2047) ? - _theResult___fst_exp__h791476 : - _theResult___fst_exp__h792256 ; - assign _theResult___fst_exp__h792268 = - (f2_exp__h753819 == 8'd0) ? + assign _theResult___fst_exp__h792256 = + (_theResult___fst_exp__h791473 == 11'd2047) ? + _theResult___fst_exp__h791473 : + _theResult___fst_exp__h792253 ; + assign _theResult___fst_exp__h792265 = + (f2_exp__h753816 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? - _theResult___snd_fst_exp__h773827 : - _theResult___fst_exp__h757993) : + _theResult___snd_fst_exp__h773824 : + _theResult___fst_exp__h757990) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? - _theResult___snd_fst_exp__h792262 : - _theResult___fst_exp__h757993) ; - assign _theResult___fst_exp__h792271 = - (f2_exp__h753819 == 8'd0 && f2_sfd__h753820 == 23'd0) ? + _theResult___snd_fst_exp__h792259 : + _theResult___fst_exp__h757990) ; + assign _theResult___fst_exp__h792268 = + (f2_exp__h753816 == 8'd0 && f2_sfd__h753817 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h792268 ; - assign _theResult___fst_exp__h797297 = + _theResult___fst_exp__h792265 ; + assign _theResult___fst_exp__h797294 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 ; - assign _theResult___fst_exp__h812361 = + assign _theResult___fst_exp__h812358 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ; - assign _theResult___fst_exp__h812367 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___fst_exp__h812364 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448) ? 11'd0 : - _theResult___fst_exp__h812361 ; - assign _theResult___fst_exp__h812370 = - (f3_exp__h793123 == 8'd0) ? - _theResult___fst_exp__h812367 : + _theResult___fst_exp__h812358 ; + assign _theResult___fst_exp__h812367 = + (f3_exp__h793120 == 8'd0) ? + _theResult___fst_exp__h812364 : 11'd897 ; - assign _theResult___fst_exp__h813125 = + assign _theResult___fst_exp__h813122 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 : + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 ; - assign _theResult___fst_exp__h813128 = - (_theResult___fst_exp__h812370 == 11'd2047) ? - _theResult___fst_exp__h812370 : - _theResult___fst_exp__h813125 ; - assign _theResult___fst_exp__h821947 = - _theResult____h813711[56] ? + assign _theResult___fst_exp__h813125 = + (_theResult___fst_exp__h812367 == 11'd2047) ? + _theResult___fst_exp__h812367 : + _theResult___fst_exp__h813122 ; + assign _theResult___fst_exp__h821944 = + _theResult____h813708[56] ? 11'd2 : - _theResult___fst_exp__h822021 ; - assign _theResult___fst_exp__h822012 = + _theResult___fst_exp__h822018 ; + assign _theResult___fst_exp__h822009 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 } ; - assign _theResult___fst_exp__h822018 = - (!_theResult____h813711[56] && !_theResult____h813711[55] && - !_theResult____h813711[54] && - !_theResult____h813711[53] && - !_theResult____h813711[52] && - !_theResult____h813711[51] && - !_theResult____h813711[50] && - !_theResult____h813711[49] && - !_theResult____h813711[48] && - !_theResult____h813711[47] && - !_theResult____h813711[46] && - !_theResult____h813711[45] && - !_theResult____h813711[44] && - !_theResult____h813711[43] && - !_theResult____h813711[42] && - !_theResult____h813711[41] && - !_theResult____h813711[40] && - !_theResult____h813711[39] && - !_theResult____h813711[38] && - !_theResult____h813711[37] && - !_theResult____h813711[36] && - !_theResult____h813711[35] && - !_theResult____h813711[34] && - !_theResult____h813711[33] && - !_theResult____h813711[32] && - !_theResult____h813711[31] && - !_theResult____h813711[30] && - !_theResult____h813711[29] && - !_theResult____h813711[28] && - !_theResult____h813711[27] && - !_theResult____h813711[26] && - !_theResult____h813711[25] && - !_theResult____h813711[24] && - !_theResult____h813711[23] && - !_theResult____h813711[22] && - !_theResult____h813711[21] && - !_theResult____h813711[20] && - !_theResult____h813711[19] && - !_theResult____h813711[18] && - !_theResult____h813711[17] && - !_theResult____h813711[16] && - !_theResult____h813711[15] && - !_theResult____h813711[14] && - !_theResult____h813711[13] && - !_theResult____h813711[12] && - !_theResult____h813711[11] && - !_theResult____h813711[10] && - !_theResult____h813711[9] && - !_theResult____h813711[8] && - !_theResult____h813711[7] && - !_theResult____h813711[6] && - !_theResult____h813711[5] && - !_theResult____h813711[4] && - !_theResult____h813711[3] && - !_theResult____h813711[2] && - !_theResult____h813711[1] && - !_theResult____h813711[0] || + assign _theResult___fst_exp__h822015 = + (!_theResult____h813708[56] && !_theResult____h813708[55] && + !_theResult____h813708[54] && + !_theResult____h813708[53] && + !_theResult____h813708[52] && + !_theResult____h813708[51] && + !_theResult____h813708[50] && + !_theResult____h813708[49] && + !_theResult____h813708[48] && + !_theResult____h813708[47] && + !_theResult____h813708[46] && + !_theResult____h813708[45] && + !_theResult____h813708[44] && + !_theResult____h813708[43] && + !_theResult____h813708[42] && + !_theResult____h813708[41] && + !_theResult____h813708[40] && + !_theResult____h813708[39] && + !_theResult____h813708[38] && + !_theResult____h813708[37] && + !_theResult____h813708[36] && + !_theResult____h813708[35] && + !_theResult____h813708[34] && + !_theResult____h813708[33] && + !_theResult____h813708[32] && + !_theResult____h813708[31] && + !_theResult____h813708[30] && + !_theResult____h813708[29] && + !_theResult____h813708[28] && + !_theResult____h813708[27] && + !_theResult____h813708[26] && + !_theResult____h813708[25] && + !_theResult____h813708[24] && + !_theResult____h813708[23] && + !_theResult____h813708[22] && + !_theResult____h813708[21] && + !_theResult____h813708[20] && + !_theResult____h813708[19] && + !_theResult____h813708[18] && + !_theResult____h813708[17] && + !_theResult____h813708[16] && + !_theResult____h813708[15] && + !_theResult____h813708[14] && + !_theResult____h813708[13] && + !_theResult____h813708[12] && + !_theResult____h813708[11] && + !_theResult____h813708[10] && + !_theResult____h813708[9] && + !_theResult____h813708[8] && + !_theResult____h813708[7] && + !_theResult____h813708[6] && + !_theResult____h813708[5] && + !_theResult____h813708[4] && + !_theResult____h813708[3] && + !_theResult____h813708[2] && + !_theResult____h813708[1] && + !_theResult____h813708[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745) ? 11'd0 : - _theResult___fst_exp__h822012 ; - assign _theResult___fst_exp__h822021 = - (!_theResult____h813711[56] && _theResult____h813711[55]) ? + _theResult___fst_exp__h822009 ; + assign _theResult___fst_exp__h822018 = + (!_theResult____h813708[56] && _theResult____h813708[55]) ? 11'd1 : - _theResult___fst_exp__h822018 ; - assign _theResult___fst_exp__h822776 = + _theResult___fst_exp__h822015 ; + assign _theResult___fst_exp__h822773 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 : + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 ; - assign _theResult___fst_exp__h822779 = - (_theResult___fst_exp__h821947 == 11'd2047) ? - _theResult___fst_exp__h821947 : - _theResult___fst_exp__h822776 ; - assign _theResult___fst_exp__h830732 = + assign _theResult___fst_exp__h822776 = + (_theResult___fst_exp__h821944 == 11'd2047) ? + _theResult___fst_exp__h821944 : + _theResult___fst_exp__h822773 ; + assign _theResult___fst_exp__h830729 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] ; - assign _theResult___fst_exp__h830771 = + assign _theResult___fst_exp__h830768 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ; - assign _theResult___fst_exp__h830777 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___fst_exp__h830774 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795) ? 11'd0 : - _theResult___fst_exp__h830771 ; - assign _theResult___fst_exp__h830780 = - (f3_exp__h793123 == 8'd0) ? - _theResult___fst_exp__h830777 : - _theResult___fst_exp__h830732 ; - assign _theResult___fst_exp__h831560 = + _theResult___fst_exp__h830768 ; + assign _theResult___fst_exp__h830777 = + (f3_exp__h793120 == 8'd0) ? + _theResult___fst_exp__h830774 : + _theResult___fst_exp__h830729 ; + assign _theResult___fst_exp__h831557 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 : + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 ; - assign _theResult___fst_exp__h831563 = - (_theResult___fst_exp__h830780 == 11'd2047) ? - _theResult___fst_exp__h830780 : - _theResult___fst_exp__h831560 ; - assign _theResult___fst_exp__h831572 = - (f3_exp__h793123 == 8'd0) ? + assign _theResult___fst_exp__h831560 = + (_theResult___fst_exp__h830777 == 11'd2047) ? + _theResult___fst_exp__h830777 : + _theResult___fst_exp__h831557 ; + assign _theResult___fst_exp__h831569 = + (f3_exp__h793120 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? - _theResult___snd_fst_exp__h813131 : - _theResult___fst_exp__h797297) : + _theResult___snd_fst_exp__h813128 : + _theResult___fst_exp__h797294) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? - _theResult___snd_fst_exp__h831566 : - _theResult___fst_exp__h797297) ; - assign _theResult___fst_exp__h831575 = - (f3_exp__h793123 == 8'd0 && f3_sfd__h793124 == 23'd0) ? + _theResult___snd_fst_exp__h831563 : + _theResult___fst_exp__h797294) ; + assign _theResult___fst_exp__h831572 = + (f3_exp__h793120 == 8'd0 && f3_sfd__h793121 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h831572 ; - assign _theResult___fst_sfd__h585090 = - (_theResult___fst_exp__h584492 == 8'd255) ? - sfdin__h584486[56:34] : - _theResult___fst_sfd__h585087 ; - assign _theResult___fst_sfd__h593672 = - (_theResult___fst_exp__h593148 == 8'd255) ? - _theResult___snd__h593099[56:34] : - _theResult___fst_sfd__h593669 ; - assign _theResult___fst_sfd__h602856 = - (_theResult___fst_exp__h602258 == 8'd255) ? - sfdin__h602252[56:34] : - _theResult___fst_sfd__h602853 ; - assign _theResult___fst_sfd__h611492 = - (_theResult___fst_exp__h610943 == 8'd255) ? - _theResult___snd__h610889[56:34] : - _theResult___fst_sfd__h611489 ; - assign _theResult___fst_sfd__h611501 = + _theResult___fst_exp__h831569 ; + assign _theResult___fst_sfd__h585087 = + (_theResult___fst_exp__h584489 == 8'd255) ? + sfdin__h584483[56:34] : + _theResult___fst_sfd__h585084 ; + assign _theResult___fst_sfd__h593669 = + (_theResult___fst_exp__h593145 == 8'd255) ? + _theResult___snd__h593096[56:34] : + _theResult___fst_sfd__h593666 ; + assign _theResult___fst_sfd__h602853 = + (_theResult___fst_exp__h602255 == 8'd255) ? + sfdin__h602249[56:34] : + _theResult___fst_sfd__h602850 ; + assign _theResult___fst_sfd__h611489 = + (_theResult___fst_exp__h610940 == 8'd255) ? + _theResult___snd__h610886[56:34] : + _theResult___fst_sfd__h611486 ; + assign _theResult___fst_sfd__h611498 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? - _theResult___snd_fst_sfd__h593675 : - _theResult___fst_sfd__h576364) : + _theResult___snd_fst_sfd__h593672 : + _theResult___fst_sfd__h576361) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? - _theResult___snd_fst_sfd__h611495 : - _theResult___fst_sfd__h576364) ; - assign _theResult___fst_sfd__h611507 = + _theResult___snd_fst_sfd__h611492 : + _theResult___fst_sfd__h576361) ; + assign _theResult___fst_sfd__h611504 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -30898,33 +30898,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h611501 ; - assign _theResult___fst_sfd__h630839 = - (_theResult___fst_exp__h630241 == 8'd255) ? - sfdin__h630235[56:34] : - _theResult___fst_sfd__h630836 ; - assign _theResult___fst_sfd__h639421 = - (_theResult___fst_exp__h638897 == 8'd255) ? - _theResult___snd__h638848[56:34] : - _theResult___fst_sfd__h639418 ; - assign _theResult___fst_sfd__h648605 = - (_theResult___fst_exp__h648007 == 8'd255) ? - sfdin__h648001[56:34] : - _theResult___fst_sfd__h648602 ; - assign _theResult___fst_sfd__h657241 = - (_theResult___fst_exp__h656692 == 8'd255) ? - _theResult___snd__h656638[56:34] : - _theResult___fst_sfd__h657238 ; - assign _theResult___fst_sfd__h657250 = + _theResult___fst_sfd__h611498 ; + assign _theResult___fst_sfd__h630836 = + (_theResult___fst_exp__h630238 == 8'd255) ? + sfdin__h630232[56:34] : + _theResult___fst_sfd__h630833 ; + assign _theResult___fst_sfd__h639418 = + (_theResult___fst_exp__h638894 == 8'd255) ? + _theResult___snd__h638845[56:34] : + _theResult___fst_sfd__h639415 ; + assign _theResult___fst_sfd__h648602 = + (_theResult___fst_exp__h648004 == 8'd255) ? + sfdin__h647998[56:34] : + _theResult___fst_sfd__h648599 ; + assign _theResult___fst_sfd__h657238 = + (_theResult___fst_exp__h656689 == 8'd255) ? + _theResult___snd__h656635[56:34] : + _theResult___fst_sfd__h657235 ; + assign _theResult___fst_sfd__h657247 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? - _theResult___snd_fst_sfd__h639424 : - _theResult___fst_sfd__h622115) : + _theResult___snd_fst_sfd__h639421 : + _theResult___fst_sfd__h622112) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? - _theResult___snd_fst_sfd__h657244 : - _theResult___fst_sfd__h622115) ; - assign _theResult___fst_sfd__h657256 = + _theResult___snd_fst_sfd__h657241 : + _theResult___fst_sfd__h622112) ; + assign _theResult___fst_sfd__h657253 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -30932,33 +30932,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h657250 ; - assign _theResult___fst_sfd__h676586 = - (_theResult___fst_exp__h675988 == 8'd255) ? - sfdin__h675982[56:34] : - _theResult___fst_sfd__h676583 ; - assign _theResult___fst_sfd__h685168 = - (_theResult___fst_exp__h684644 == 8'd255) ? - _theResult___snd__h684595[56:34] : - _theResult___fst_sfd__h685165 ; - assign _theResult___fst_sfd__h694352 = - (_theResult___fst_exp__h693754 == 8'd255) ? - sfdin__h693748[56:34] : - _theResult___fst_sfd__h694349 ; - assign _theResult___fst_sfd__h702988 = - (_theResult___fst_exp__h702439 == 8'd255) ? - _theResult___snd__h702385[56:34] : - _theResult___fst_sfd__h702985 ; - assign _theResult___fst_sfd__h702997 = + _theResult___fst_sfd__h657247 ; + assign _theResult___fst_sfd__h676583 = + (_theResult___fst_exp__h675985 == 8'd255) ? + sfdin__h675979[56:34] : + _theResult___fst_sfd__h676580 ; + assign _theResult___fst_sfd__h685165 = + (_theResult___fst_exp__h684641 == 8'd255) ? + _theResult___snd__h684592[56:34] : + _theResult___fst_sfd__h685162 ; + assign _theResult___fst_sfd__h694349 = + (_theResult___fst_exp__h693751 == 8'd255) ? + sfdin__h693745[56:34] : + _theResult___fst_sfd__h694346 ; + assign _theResult___fst_sfd__h702985 = + (_theResult___fst_exp__h702436 == 8'd255) ? + _theResult___snd__h702382[56:34] : + _theResult___fst_sfd__h702982 ; + assign _theResult___fst_sfd__h702994 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? - _theResult___snd_fst_sfd__h685171 : - _theResult___fst_sfd__h667862) : + _theResult___snd_fst_sfd__h685168 : + _theResult___fst_sfd__h667859) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? - _theResult___snd_fst_sfd__h702991 : - _theResult___fst_sfd__h667862) ; - assign _theResult___fst_sfd__h703003 = + _theResult___snd_fst_sfd__h702988 : + _theResult___fst_sfd__h667859) ; + assign _theResult___fst_sfd__h703000 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -30966,1426 +30966,1426 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h702997 ; - assign _theResult___fst_sfd__h719141 = + _theResult___fst_sfd__h702994 ; + assign _theResult___fst_sfd__h719138 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 ; - assign _theResult___fst_sfd__h734969 = + assign _theResult___fst_sfd__h734966 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 : + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 ; - assign _theResult___fst_sfd__h734972 = - (_theResult___fst_exp__h734213 == 11'd2047) ? - _theResult___snd__h734164[56:5] : - _theResult___fst_sfd__h734969 ; - assign _theResult___fst_sfd__h744620 = + assign _theResult___fst_sfd__h734969 = + (_theResult___fst_exp__h734210 == 11'd2047) ? + _theResult___snd__h734161[56:5] : + _theResult___fst_sfd__h734966 ; + assign _theResult___fst_sfd__h744617 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 : + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 ; - assign _theResult___fst_sfd__h744623 = - (_theResult___fst_exp__h743790 == 11'd2047) ? - sfdin__h743784[56:5] : - _theResult___fst_sfd__h744620 ; - assign _theResult___fst_sfd__h753404 = + assign _theResult___fst_sfd__h744620 = + (_theResult___fst_exp__h743787 == 11'd2047) ? + sfdin__h743781[56:5] : + _theResult___fst_sfd__h744617 ; + assign _theResult___fst_sfd__h753401 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 : + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 ; - assign _theResult___fst_sfd__h753407 = - (_theResult___fst_exp__h752623 == 11'd2047) ? - _theResult___snd__h752569[56:5] : - _theResult___fst_sfd__h753404 ; - assign _theResult___fst_sfd__h753416 = - (f1_exp__h714825 == 8'd0) ? + assign _theResult___fst_sfd__h753404 = + (_theResult___fst_exp__h752620 == 11'd2047) ? + _theResult___snd__h752566[56:5] : + _theResult___fst_sfd__h753401 ; + assign _theResult___fst_sfd__h753413 = + (f1_exp__h714822 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 ? - _theResult___snd_fst_sfd__h734975 : - _theResult___fst_sfd__h719141) : + _theResult___snd_fst_sfd__h734972 : + _theResult___fst_sfd__h719138) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 ? - _theResult___snd_fst_sfd__h753410 : - _theResult___fst_sfd__h719141) ; - assign _theResult___fst_sfd__h753422 = - ((f1_exp__h714825 == 8'd255 || f1_exp__h714825 == 8'd0) && - f1_sfd__h714826 == 23'd0) ? + _theResult___snd_fst_sfd__h753407 : + _theResult___fst_sfd__h719138) ; + assign _theResult___fst_sfd__h753419 = + ((f1_exp__h714822 == 8'd255 || f1_exp__h714822 == 8'd0) && + f1_sfd__h714823 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h753416 ; - assign _theResult___fst_sfd__h757994 = + _theResult___fst_sfd__h753413 ; + assign _theResult___fst_sfd__h757991 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 ; - assign _theResult___fst_sfd__h773822 = + assign _theResult___fst_sfd__h773819 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 : + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 ; - assign _theResult___fst_sfd__h773825 = - (_theResult___fst_exp__h773066 == 11'd2047) ? - _theResult___snd__h773017[56:5] : - _theResult___fst_sfd__h773822 ; - assign _theResult___fst_sfd__h783473 = + assign _theResult___fst_sfd__h773822 = + (_theResult___fst_exp__h773063 == 11'd2047) ? + _theResult___snd__h773014[56:5] : + _theResult___fst_sfd__h773819 ; + assign _theResult___fst_sfd__h783470 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 : + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 ; - assign _theResult___fst_sfd__h783476 = - (_theResult___fst_exp__h782643 == 11'd2047) ? - sfdin__h782637[56:5] : - _theResult___fst_sfd__h783473 ; - assign _theResult___fst_sfd__h792257 = + assign _theResult___fst_sfd__h783473 = + (_theResult___fst_exp__h782640 == 11'd2047) ? + sfdin__h782634[56:5] : + _theResult___fst_sfd__h783470 ; + assign _theResult___fst_sfd__h792254 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 : + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 ; - assign _theResult___fst_sfd__h792260 = - (_theResult___fst_exp__h791476 == 11'd2047) ? - _theResult___snd__h791422[56:5] : - _theResult___fst_sfd__h792257 ; - assign _theResult___fst_sfd__h792269 = - (f2_exp__h753819 == 8'd0) ? + assign _theResult___fst_sfd__h792257 = + (_theResult___fst_exp__h791473 == 11'd2047) ? + _theResult___snd__h791419[56:5] : + _theResult___fst_sfd__h792254 ; + assign _theResult___fst_sfd__h792266 = + (f2_exp__h753816 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? - _theResult___snd_fst_sfd__h773828 : - _theResult___fst_sfd__h757994) : + _theResult___snd_fst_sfd__h773825 : + _theResult___fst_sfd__h757991) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? - _theResult___snd_fst_sfd__h792263 : - _theResult___fst_sfd__h757994) ; - assign _theResult___fst_sfd__h792275 = - ((f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && - f2_sfd__h753820 == 23'd0) ? + _theResult___snd_fst_sfd__h792260 : + _theResult___fst_sfd__h757991) ; + assign _theResult___fst_sfd__h792272 = + ((f2_exp__h753816 == 8'd255 || f2_exp__h753816 == 8'd0) && + f2_sfd__h753817 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h792269 ; - assign _theResult___fst_sfd__h797298 = + _theResult___fst_sfd__h792266 ; + assign _theResult___fst_sfd__h797295 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 ; - assign _theResult___fst_sfd__h813126 = + assign _theResult___fst_sfd__h813123 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 : + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 ; - assign _theResult___fst_sfd__h813129 = - (_theResult___fst_exp__h812370 == 11'd2047) ? - _theResult___snd__h812321[56:5] : - _theResult___fst_sfd__h813126 ; - assign _theResult___fst_sfd__h822777 = + assign _theResult___fst_sfd__h813126 = + (_theResult___fst_exp__h812367 == 11'd2047) ? + _theResult___snd__h812318[56:5] : + _theResult___fst_sfd__h813123 ; + assign _theResult___fst_sfd__h822774 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 : + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 ; - assign _theResult___fst_sfd__h822780 = - (_theResult___fst_exp__h821947 == 11'd2047) ? - sfdin__h821941[56:5] : - _theResult___fst_sfd__h822777 ; - assign _theResult___fst_sfd__h831561 = + assign _theResult___fst_sfd__h822777 = + (_theResult___fst_exp__h821944 == 11'd2047) ? + sfdin__h821938[56:5] : + _theResult___fst_sfd__h822774 ; + assign _theResult___fst_sfd__h831558 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 : + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 ; - assign _theResult___fst_sfd__h831564 = - (_theResult___fst_exp__h830780 == 11'd2047) ? - _theResult___snd__h830726[56:5] : - _theResult___fst_sfd__h831561 ; - assign _theResult___fst_sfd__h831573 = - (f3_exp__h793123 == 8'd0) ? + assign _theResult___fst_sfd__h831561 = + (_theResult___fst_exp__h830777 == 11'd2047) ? + _theResult___snd__h830723[56:5] : + _theResult___fst_sfd__h831558 ; + assign _theResult___fst_sfd__h831570 = + (f3_exp__h793120 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? - _theResult___snd_fst_sfd__h813132 : - _theResult___fst_sfd__h797298) : + _theResult___snd_fst_sfd__h813129 : + _theResult___fst_sfd__h797295) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? - _theResult___snd_fst_sfd__h831567 : - _theResult___fst_sfd__h797298) ; - assign _theResult___fst_sfd__h831579 = - ((f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && - f3_sfd__h793124 == 23'd0) ? + _theResult___snd_fst_sfd__h831564 : + _theResult___fst_sfd__h797295) ; + assign _theResult___fst_sfd__h831576 = + ((f3_exp__h793120 == 8'd255 || f3_exp__h793120 == 8'd0) && + f3_sfd__h793121 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h831573 ; - assign _theResult___sfd__h585009 = - sfd__h584584[24] ? - ((_theResult___fst_exp__h584492 == 8'd254) ? + _theResult___fst_sfd__h831570 ; + assign _theResult___sfd__h585006 = + sfd__h584581[24] ? + ((_theResult___fst_exp__h584489 == 8'd254) ? 23'd0 : - sfd__h584584[23:1]) : - sfd__h584584[22:0] ; - assign _theResult___sfd__h593591 = - sfd__h593166[24] ? - ((_theResult___fst_exp__h593148 == 8'd254) ? + sfd__h584581[23:1]) : + sfd__h584581[22:0] ; + assign _theResult___sfd__h593588 = + sfd__h593163[24] ? + ((_theResult___fst_exp__h593145 == 8'd254) ? 23'd0 : - sfd__h593166[23:1]) : - sfd__h593166[22:0] ; - assign _theResult___sfd__h602775 = - sfd__h602350[24] ? - ((_theResult___fst_exp__h602258 == 8'd254) ? + sfd__h593163[23:1]) : + sfd__h593163[22:0] ; + assign _theResult___sfd__h602772 = + sfd__h602347[24] ? + ((_theResult___fst_exp__h602255 == 8'd254) ? 23'd0 : - sfd__h602350[23:1]) : - sfd__h602350[22:0] ; - assign _theResult___sfd__h611411 = - sfd__h610962[24] ? - ((_theResult___fst_exp__h610943 == 8'd254) ? + sfd__h602347[23:1]) : + sfd__h602347[22:0] ; + assign _theResult___sfd__h611408 = + sfd__h610959[24] ? + ((_theResult___fst_exp__h610940 == 8'd254) ? 23'd0 : - sfd__h610962[23:1]) : - sfd__h610962[22:0] ; - assign _theResult___sfd__h611513 = + sfd__h610959[23:1]) : + sfd__h610959[22:0] ; + assign _theResult___sfd__h611510 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h568726 : - _theResult___fst_sfd__h611507 ; - assign _theResult___sfd__h630758 = - sfd__h630333[24] ? - ((_theResult___fst_exp__h630241 == 8'd254) ? + _theResult___snd_fst_sfd__h568723 : + _theResult___fst_sfd__h611504 ; + assign _theResult___sfd__h630755 = + sfd__h630330[24] ? + ((_theResult___fst_exp__h630238 == 8'd254) ? 23'd0 : - sfd__h630333[23:1]) : - sfd__h630333[22:0] ; - assign _theResult___sfd__h639340 = - sfd__h638915[24] ? - ((_theResult___fst_exp__h638897 == 8'd254) ? + sfd__h630330[23:1]) : + sfd__h630330[22:0] ; + assign _theResult___sfd__h639337 = + sfd__h638912[24] ? + ((_theResult___fst_exp__h638894 == 8'd254) ? 23'd0 : - sfd__h638915[23:1]) : - sfd__h638915[22:0] ; - assign _theResult___sfd__h648524 = - sfd__h648099[24] ? - ((_theResult___fst_exp__h648007 == 8'd254) ? + sfd__h638912[23:1]) : + sfd__h638912[22:0] ; + assign _theResult___sfd__h648521 = + sfd__h648096[24] ? + ((_theResult___fst_exp__h648004 == 8'd254) ? 23'd0 : - sfd__h648099[23:1]) : - sfd__h648099[22:0] ; - assign _theResult___sfd__h657160 = - sfd__h656711[24] ? - ((_theResult___fst_exp__h656692 == 8'd254) ? + sfd__h648096[23:1]) : + sfd__h648096[22:0] ; + assign _theResult___sfd__h657157 = + sfd__h656708[24] ? + ((_theResult___fst_exp__h656689 == 8'd254) ? 23'd0 : - sfd__h656711[23:1]) : - sfd__h656711[22:0] ; - assign _theResult___sfd__h657262 = + sfd__h656708[23:1]) : + sfd__h656708[22:0] ; + assign _theResult___sfd__h657259 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h614480 : - _theResult___fst_sfd__h657256 ; - assign _theResult___sfd__h676505 = - sfd__h676080[24] ? - ((_theResult___fst_exp__h675988 == 8'd254) ? + _theResult___snd_fst_sfd__h614477 : + _theResult___fst_sfd__h657253 ; + assign _theResult___sfd__h676502 = + sfd__h676077[24] ? + ((_theResult___fst_exp__h675985 == 8'd254) ? 23'd0 : - sfd__h676080[23:1]) : - sfd__h676080[22:0] ; - assign _theResult___sfd__h685087 = - sfd__h684662[24] ? - ((_theResult___fst_exp__h684644 == 8'd254) ? + sfd__h676077[23:1]) : + sfd__h676077[22:0] ; + assign _theResult___sfd__h685084 = + sfd__h684659[24] ? + ((_theResult___fst_exp__h684641 == 8'd254) ? 23'd0 : - sfd__h684662[23:1]) : - sfd__h684662[22:0] ; - assign _theResult___sfd__h694271 = - sfd__h693846[24] ? - ((_theResult___fst_exp__h693754 == 8'd254) ? + sfd__h684659[23:1]) : + sfd__h684659[22:0] ; + assign _theResult___sfd__h694268 = + sfd__h693843[24] ? + ((_theResult___fst_exp__h693751 == 8'd254) ? 23'd0 : - sfd__h693846[23:1]) : - sfd__h693846[22:0] ; - assign _theResult___sfd__h702907 = - sfd__h702458[24] ? - ((_theResult___fst_exp__h702439 == 8'd254) ? + sfd__h693843[23:1]) : + sfd__h693843[22:0] ; + assign _theResult___sfd__h702904 = + sfd__h702455[24] ? + ((_theResult___fst_exp__h702436 == 8'd254) ? 23'd0 : - sfd__h702458[23:1]) : - sfd__h702458[22:0] ; - assign _theResult___sfd__h703009 = + sfd__h702455[23:1]) : + sfd__h702455[22:0] ; + assign _theResult___sfd__h703006 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h660227 : - _theResult___fst_sfd__h703003 ; - assign _theResult___sfd__h734869 = - sfd__h734231[53] ? - ((_theResult___fst_exp__h734213 == 11'd2046) ? + _theResult___snd_fst_sfd__h660224 : + _theResult___fst_sfd__h703000 ; + assign _theResult___sfd__h734866 = + sfd__h734228[53] ? + ((_theResult___fst_exp__h734210 == 11'd2046) ? 52'd0 : - sfd__h734231[52:1]) : - sfd__h734231[51:0] ; - assign _theResult___sfd__h744520 = - sfd__h743882[53] ? - ((_theResult___fst_exp__h743790 == 11'd2046) ? + sfd__h734228[52:1]) : + sfd__h734228[51:0] ; + assign _theResult___sfd__h744517 = + sfd__h743879[53] ? + ((_theResult___fst_exp__h743787 == 11'd2046) ? 52'd0 : - sfd__h743882[52:1]) : - sfd__h743882[51:0] ; - assign _theResult___sfd__h753304 = - sfd__h752642[53] ? - ((_theResult___fst_exp__h752623 == 11'd2046) ? + sfd__h743879[52:1]) : + sfd__h743879[51:0] ; + assign _theResult___sfd__h753301 = + sfd__h752639[53] ? + ((_theResult___fst_exp__h752620 == 11'd2046) ? 52'd0 : - sfd__h752642[52:1]) : - sfd__h752642[51:0] ; - assign _theResult___sfd__h773722 = - sfd__h773084[53] ? - ((_theResult___fst_exp__h773066 == 11'd2046) ? + sfd__h752639[52:1]) : + sfd__h752639[51:0] ; + assign _theResult___sfd__h773719 = + sfd__h773081[53] ? + ((_theResult___fst_exp__h773063 == 11'd2046) ? 52'd0 : - sfd__h773084[52:1]) : - sfd__h773084[51:0] ; - assign _theResult___sfd__h783373 = - sfd__h782735[53] ? - ((_theResult___fst_exp__h782643 == 11'd2046) ? + sfd__h773081[52:1]) : + sfd__h773081[51:0] ; + assign _theResult___sfd__h783370 = + sfd__h782732[53] ? + ((_theResult___fst_exp__h782640 == 11'd2046) ? 52'd0 : - sfd__h782735[52:1]) : - sfd__h782735[51:0] ; - assign _theResult___sfd__h792157 = - sfd__h791495[53] ? - ((_theResult___fst_exp__h791476 == 11'd2046) ? + sfd__h782732[52:1]) : + sfd__h782732[51:0] ; + assign _theResult___sfd__h792154 = + sfd__h791492[53] ? + ((_theResult___fst_exp__h791473 == 11'd2046) ? 52'd0 : - sfd__h791495[52:1]) : - sfd__h791495[51:0] ; - assign _theResult___sfd__h813026 = - sfd__h812388[53] ? - ((_theResult___fst_exp__h812370 == 11'd2046) ? + sfd__h791492[52:1]) : + sfd__h791492[51:0] ; + assign _theResult___sfd__h813023 = + sfd__h812385[53] ? + ((_theResult___fst_exp__h812367 == 11'd2046) ? 52'd0 : - sfd__h812388[52:1]) : - sfd__h812388[51:0] ; - assign _theResult___sfd__h822677 = - sfd__h822039[53] ? - ((_theResult___fst_exp__h821947 == 11'd2046) ? + sfd__h812385[52:1]) : + sfd__h812385[51:0] ; + assign _theResult___sfd__h822674 = + sfd__h822036[53] ? + ((_theResult___fst_exp__h821944 == 11'd2046) ? 52'd0 : - sfd__h822039[52:1]) : - sfd__h822039[51:0] ; - assign _theResult___sfd__h831461 = - sfd__h830799[53] ? - ((_theResult___fst_exp__h830780 == 11'd2046) ? + sfd__h822036[52:1]) : + sfd__h822036[51:0] ; + assign _theResult___sfd__h831458 = + sfd__h830796[53] ? + ((_theResult___fst_exp__h830777 == 11'd2046) ? 52'd0 : - sfd__h830799[52:1]) : - sfd__h830799[51:0] ; - assign _theResult___snd__h584503 = { _theResult____h576381[55:0], 1'd0 } ; - assign _theResult___snd__h584514 = - (!_theResult____h576381[56] && _theResult____h576381[55]) ? - _theResult___snd__h584516 : - _theResult___snd__h584526 ; - assign _theResult___snd__h584516 = { _theResult____h576381[54:0], 2'd0 } ; - assign _theResult___snd__h584526 = - (!_theResult____h576381[56] && !_theResult____h576381[55] && - !_theResult____h576381[54] && - !_theResult____h576381[53] && - !_theResult____h576381[52] && - !_theResult____h576381[51] && - !_theResult____h576381[50] && - !_theResult____h576381[49] && - !_theResult____h576381[48] && - !_theResult____h576381[47] && - !_theResult____h576381[46] && - !_theResult____h576381[45] && - !_theResult____h576381[44] && - !_theResult____h576381[43] && - !_theResult____h576381[42] && - !_theResult____h576381[41] && - !_theResult____h576381[40] && - !_theResult____h576381[39] && - !_theResult____h576381[38] && - !_theResult____h576381[37] && - !_theResult____h576381[36] && - !_theResult____h576381[35] && - !_theResult____h576381[34] && - !_theResult____h576381[33] && - !_theResult____h576381[32] && - !_theResult____h576381[31] && - !_theResult____h576381[30] && - !_theResult____h576381[29] && - !_theResult____h576381[28] && - !_theResult____h576381[27] && - !_theResult____h576381[26] && - !_theResult____h576381[25] && - !_theResult____h576381[24] && - !_theResult____h576381[23] && - !_theResult____h576381[22] && - !_theResult____h576381[21] && - !_theResult____h576381[20] && - !_theResult____h576381[19] && - !_theResult____h576381[18] && - !_theResult____h576381[17] && - !_theResult____h576381[16] && - !_theResult____h576381[15] && - !_theResult____h576381[14] && - !_theResult____h576381[13] && - !_theResult____h576381[12] && - !_theResult____h576381[11] && - !_theResult____h576381[10] && - !_theResult____h576381[9] && - !_theResult____h576381[8] && - !_theResult____h576381[7] && - !_theResult____h576381[6] && - !_theResult____h576381[5] && - !_theResult____h576381[4] && - !_theResult____h576381[3] && - !_theResult____h576381[2] && - !_theResult____h576381[1] && - !_theResult____h576381[0]) ? - _theResult____h576381 : - _theResult___snd__h584532 ; - assign _theResult___snd__h584532 = + sfd__h830796[52:1]) : + sfd__h830796[51:0] ; + assign _theResult___snd__h584500 = { _theResult____h576378[55:0], 1'd0 } ; + assign _theResult___snd__h584511 = + (!_theResult____h576378[56] && _theResult____h576378[55]) ? + _theResult___snd__h584513 : + _theResult___snd__h584523 ; + assign _theResult___snd__h584513 = { _theResult____h576378[54:0], 2'd0 } ; + assign _theResult___snd__h584523 = + (!_theResult____h576378[56] && !_theResult____h576378[55] && + !_theResult____h576378[54] && + !_theResult____h576378[53] && + !_theResult____h576378[52] && + !_theResult____h576378[51] && + !_theResult____h576378[50] && + !_theResult____h576378[49] && + !_theResult____h576378[48] && + !_theResult____h576378[47] && + !_theResult____h576378[46] && + !_theResult____h576378[45] && + !_theResult____h576378[44] && + !_theResult____h576378[43] && + !_theResult____h576378[42] && + !_theResult____h576378[41] && + !_theResult____h576378[40] && + !_theResult____h576378[39] && + !_theResult____h576378[38] && + !_theResult____h576378[37] && + !_theResult____h576378[36] && + !_theResult____h576378[35] && + !_theResult____h576378[34] && + !_theResult____h576378[33] && + !_theResult____h576378[32] && + !_theResult____h576378[31] && + !_theResult____h576378[30] && + !_theResult____h576378[29] && + !_theResult____h576378[28] && + !_theResult____h576378[27] && + !_theResult____h576378[26] && + !_theResult____h576378[25] && + !_theResult____h576378[24] && + !_theResult____h576378[23] && + !_theResult____h576378[22] && + !_theResult____h576378[21] && + !_theResult____h576378[20] && + !_theResult____h576378[19] && + !_theResult____h576378[18] && + !_theResult____h576378[17] && + !_theResult____h576378[16] && + !_theResult____h576378[15] && + !_theResult____h576378[14] && + !_theResult____h576378[13] && + !_theResult____h576378[12] && + !_theResult____h576378[11] && + !_theResult____h576378[10] && + !_theResult____h576378[9] && + !_theResult____h576378[8] && + !_theResult____h576378[7] && + !_theResult____h576378[6] && + !_theResult____h576378[5] && + !_theResult____h576378[4] && + !_theResult____h576378[3] && + !_theResult____h576378[2] && + !_theResult____h576378[1] && + !_theResult____h576378[0]) ? + _theResult____h576378 : + _theResult___snd__h584529 ; + assign _theResult___snd__h584529 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39[54:0], 2'd0 } ; - assign _theResult___snd__h584555 = - _theResult____h576381 << + assign _theResult___snd__h584552 = + _theResult____h576378 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 ; - assign _theResult___snd__h593099 = + assign _theResult___snd__h593096 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h593108 : - _theResult___snd__h593101 ; - assign _theResult___snd__h593101 = + _theResult___snd__h593105 : + _theResult___snd__h593098 ; + assign _theResult___snd__h593098 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h593108 = + assign _theResult___snd__h593105 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528) ? - sfd__h568776 : - _theResult___snd__h593114 ; - assign _theResult___snd__h593114 = + sfd__h568773 : + _theResult___snd__h593111 ; + assign _theResult___snd__h593111 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q41[54:0], 2'd0 } ; - assign _theResult___snd__h593137 = - sfd__h568776 << + assign _theResult___snd__h593134 = + sfd__h568773 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 ; - assign _theResult___snd__h602269 = { _theResult____h594020[55:0], 1'd0 } ; - assign _theResult___snd__h602280 = - (!_theResult____h594020[56] && _theResult____h594020[55]) ? - _theResult___snd__h602282 : - _theResult___snd__h602292 ; - assign _theResult___snd__h602282 = { _theResult____h594020[54:0], 2'd0 } ; - assign _theResult___snd__h602292 = - (!_theResult____h594020[56] && !_theResult____h594020[55] && - !_theResult____h594020[54] && - !_theResult____h594020[53] && - !_theResult____h594020[52] && - !_theResult____h594020[51] && - !_theResult____h594020[50] && - !_theResult____h594020[49] && - !_theResult____h594020[48] && - !_theResult____h594020[47] && - !_theResult____h594020[46] && - !_theResult____h594020[45] && - !_theResult____h594020[44] && - !_theResult____h594020[43] && - !_theResult____h594020[42] && - !_theResult____h594020[41] && - !_theResult____h594020[40] && - !_theResult____h594020[39] && - !_theResult____h594020[38] && - !_theResult____h594020[37] && - !_theResult____h594020[36] && - !_theResult____h594020[35] && - !_theResult____h594020[34] && - !_theResult____h594020[33] && - !_theResult____h594020[32] && - !_theResult____h594020[31] && - !_theResult____h594020[30] && - !_theResult____h594020[29] && - !_theResult____h594020[28] && - !_theResult____h594020[27] && - !_theResult____h594020[26] && - !_theResult____h594020[25] && - !_theResult____h594020[24] && - !_theResult____h594020[23] && - !_theResult____h594020[22] && - !_theResult____h594020[21] && - !_theResult____h594020[20] && - !_theResult____h594020[19] && - !_theResult____h594020[18] && - !_theResult____h594020[17] && - !_theResult____h594020[16] && - !_theResult____h594020[15] && - !_theResult____h594020[14] && - !_theResult____h594020[13] && - !_theResult____h594020[12] && - !_theResult____h594020[11] && - !_theResult____h594020[10] && - !_theResult____h594020[9] && - !_theResult____h594020[8] && - !_theResult____h594020[7] && - !_theResult____h594020[6] && - !_theResult____h594020[5] && - !_theResult____h594020[4] && - !_theResult____h594020[3] && - !_theResult____h594020[2] && - !_theResult____h594020[1] && - !_theResult____h594020[0]) ? - _theResult____h594020 : - _theResult___snd__h602298 ; - assign _theResult___snd__h602298 = + assign _theResult___snd__h602266 = { _theResult____h594017[55:0], 1'd0 } ; + assign _theResult___snd__h602277 = + (!_theResult____h594017[56] && _theResult____h594017[55]) ? + _theResult___snd__h602279 : + _theResult___snd__h602289 ; + assign _theResult___snd__h602279 = { _theResult____h594017[54:0], 2'd0 } ; + assign _theResult___snd__h602289 = + (!_theResult____h594017[56] && !_theResult____h594017[55] && + !_theResult____h594017[54] && + !_theResult____h594017[53] && + !_theResult____h594017[52] && + !_theResult____h594017[51] && + !_theResult____h594017[50] && + !_theResult____h594017[49] && + !_theResult____h594017[48] && + !_theResult____h594017[47] && + !_theResult____h594017[46] && + !_theResult____h594017[45] && + !_theResult____h594017[44] && + !_theResult____h594017[43] && + !_theResult____h594017[42] && + !_theResult____h594017[41] && + !_theResult____h594017[40] && + !_theResult____h594017[39] && + !_theResult____h594017[38] && + !_theResult____h594017[37] && + !_theResult____h594017[36] && + !_theResult____h594017[35] && + !_theResult____h594017[34] && + !_theResult____h594017[33] && + !_theResult____h594017[32] && + !_theResult____h594017[31] && + !_theResult____h594017[30] && + !_theResult____h594017[29] && + !_theResult____h594017[28] && + !_theResult____h594017[27] && + !_theResult____h594017[26] && + !_theResult____h594017[25] && + !_theResult____h594017[24] && + !_theResult____h594017[23] && + !_theResult____h594017[22] && + !_theResult____h594017[21] && + !_theResult____h594017[20] && + !_theResult____h594017[19] && + !_theResult____h594017[18] && + !_theResult____h594017[17] && + !_theResult____h594017[16] && + !_theResult____h594017[15] && + !_theResult____h594017[14] && + !_theResult____h594017[13] && + !_theResult____h594017[12] && + !_theResult____h594017[11] && + !_theResult____h594017[10] && + !_theResult____h594017[9] && + !_theResult____h594017[8] && + !_theResult____h594017[7] && + !_theResult____h594017[6] && + !_theResult____h594017[5] && + !_theResult____h594017[4] && + !_theResult____h594017[3] && + !_theResult____h594017[2] && + !_theResult____h594017[1] && + !_theResult____h594017[0]) ? + _theResult____h594017 : + _theResult___snd__h602295 ; + assign _theResult___snd__h602295 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q49[54:0], 2'd0 } ; - assign _theResult___snd__h602321 = - _theResult____h594020 << + assign _theResult___snd__h602318 = + _theResult____h594017 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 ; - assign _theResult___snd__h610889 = + assign _theResult___snd__h610886 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h610903 : - _theResult___snd__h593101 ; - assign _theResult___snd__h610903 = + _theResult___snd__h610900 : + _theResult___snd__h593098 ; + assign _theResult___snd__h610900 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528) ? - sfd__h568776 : - _theResult___snd__h610909 ; - assign _theResult___snd__h610909 = + sfd__h568773 : + _theResult___snd__h610906 ; + assign _theResult___snd__h610906 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q54[54:0], 2'd0 } ; - assign _theResult___snd__h610927 = - sfd__h568776 << + assign _theResult___snd__h610924 = + sfd__h568773 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977) ; - assign _theResult___snd__h630252 = { _theResult____h622132[55:0], 1'd0 } ; - assign _theResult___snd__h630263 = - (!_theResult____h622132[56] && _theResult____h622132[55]) ? - _theResult___snd__h630265 : - _theResult___snd__h630275 ; - assign _theResult___snd__h630265 = { _theResult____h622132[54:0], 2'd0 } ; - assign _theResult___snd__h630275 = - (!_theResult____h622132[56] && !_theResult____h622132[55] && - !_theResult____h622132[54] && - !_theResult____h622132[53] && - !_theResult____h622132[52] && - !_theResult____h622132[51] && - !_theResult____h622132[50] && - !_theResult____h622132[49] && - !_theResult____h622132[48] && - !_theResult____h622132[47] && - !_theResult____h622132[46] && - !_theResult____h622132[45] && - !_theResult____h622132[44] && - !_theResult____h622132[43] && - !_theResult____h622132[42] && - !_theResult____h622132[41] && - !_theResult____h622132[40] && - !_theResult____h622132[39] && - !_theResult____h622132[38] && - !_theResult____h622132[37] && - !_theResult____h622132[36] && - !_theResult____h622132[35] && - !_theResult____h622132[34] && - !_theResult____h622132[33] && - !_theResult____h622132[32] && - !_theResult____h622132[31] && - !_theResult____h622132[30] && - !_theResult____h622132[29] && - !_theResult____h622132[28] && - !_theResult____h622132[27] && - !_theResult____h622132[26] && - !_theResult____h622132[25] && - !_theResult____h622132[24] && - !_theResult____h622132[23] && - !_theResult____h622132[22] && - !_theResult____h622132[21] && - !_theResult____h622132[20] && - !_theResult____h622132[19] && - !_theResult____h622132[18] && - !_theResult____h622132[17] && - !_theResult____h622132[16] && - !_theResult____h622132[15] && - !_theResult____h622132[14] && - !_theResult____h622132[13] && - !_theResult____h622132[12] && - !_theResult____h622132[11] && - !_theResult____h622132[10] && - !_theResult____h622132[9] && - !_theResult____h622132[8] && - !_theResult____h622132[7] && - !_theResult____h622132[6] && - !_theResult____h622132[5] && - !_theResult____h622132[4] && - !_theResult____h622132[3] && - !_theResult____h622132[2] && - !_theResult____h622132[1] && - !_theResult____h622132[0]) ? - _theResult____h622132 : - _theResult___snd__h630281 ; - assign _theResult___snd__h630281 = + assign _theResult___snd__h630249 = { _theResult____h622129[55:0], 1'd0 } ; + assign _theResult___snd__h630260 = + (!_theResult____h622129[56] && _theResult____h622129[55]) ? + _theResult___snd__h630262 : + _theResult___snd__h630272 ; + assign _theResult___snd__h630262 = { _theResult____h622129[54:0], 2'd0 } ; + assign _theResult___snd__h630272 = + (!_theResult____h622129[56] && !_theResult____h622129[55] && + !_theResult____h622129[54] && + !_theResult____h622129[53] && + !_theResult____h622129[52] && + !_theResult____h622129[51] && + !_theResult____h622129[50] && + !_theResult____h622129[49] && + !_theResult____h622129[48] && + !_theResult____h622129[47] && + !_theResult____h622129[46] && + !_theResult____h622129[45] && + !_theResult____h622129[44] && + !_theResult____h622129[43] && + !_theResult____h622129[42] && + !_theResult____h622129[41] && + !_theResult____h622129[40] && + !_theResult____h622129[39] && + !_theResult____h622129[38] && + !_theResult____h622129[37] && + !_theResult____h622129[36] && + !_theResult____h622129[35] && + !_theResult____h622129[34] && + !_theResult____h622129[33] && + !_theResult____h622129[32] && + !_theResult____h622129[31] && + !_theResult____h622129[30] && + !_theResult____h622129[29] && + !_theResult____h622129[28] && + !_theResult____h622129[27] && + !_theResult____h622129[26] && + !_theResult____h622129[25] && + !_theResult____h622129[24] && + !_theResult____h622129[23] && + !_theResult____h622129[22] && + !_theResult____h622129[21] && + !_theResult____h622129[20] && + !_theResult____h622129[19] && + !_theResult____h622129[18] && + !_theResult____h622129[17] && + !_theResult____h622129[16] && + !_theResult____h622129[15] && + !_theResult____h622129[14] && + !_theResult____h622129[13] && + !_theResult____h622129[12] && + !_theResult____h622129[11] && + !_theResult____h622129[10] && + !_theResult____h622129[9] && + !_theResult____h622129[8] && + !_theResult____h622129[7] && + !_theResult____h622129[6] && + !_theResult____h622129[5] && + !_theResult____h622129[4] && + !_theResult____h622129[3] && + !_theResult____h622129[2] && + !_theResult____h622129[1] && + !_theResult____h622129[0]) ? + _theResult____h622129 : + _theResult___snd__h630278 ; + assign _theResult___snd__h630278 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74[54:0], 2'd0 } ; - assign _theResult___snd__h630304 = - _theResult____h622132 << + assign _theResult___snd__h630301 = + _theResult____h622129 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 ; - assign _theResult___snd__h638848 = + assign _theResult___snd__h638845 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h638857 : - _theResult___snd__h638850 ; - assign _theResult___snd__h638850 = + _theResult___snd__h638854 : + _theResult___snd__h638847 ; + assign _theResult___snd__h638847 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h638857 = + assign _theResult___snd__h638854 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925) ? - sfd__h614530 : - _theResult___snd__h638863 ; - assign _theResult___snd__h638863 = + sfd__h614527 : + _theResult___snd__h638860 ; + assign _theResult___snd__h638860 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q76[54:0], 2'd0 } ; - assign _theResult___snd__h638886 = - sfd__h614530 << + assign _theResult___snd__h638883 = + sfd__h614527 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 ; - assign _theResult___snd__h648018 = { _theResult____h639769[55:0], 1'd0 } ; - assign _theResult___snd__h648029 = - (!_theResult____h639769[56] && _theResult____h639769[55]) ? - _theResult___snd__h648031 : - _theResult___snd__h648041 ; - assign _theResult___snd__h648031 = { _theResult____h639769[54:0], 2'd0 } ; - assign _theResult___snd__h648041 = - (!_theResult____h639769[56] && !_theResult____h639769[55] && - !_theResult____h639769[54] && - !_theResult____h639769[53] && - !_theResult____h639769[52] && - !_theResult____h639769[51] && - !_theResult____h639769[50] && - !_theResult____h639769[49] && - !_theResult____h639769[48] && - !_theResult____h639769[47] && - !_theResult____h639769[46] && - !_theResult____h639769[45] && - !_theResult____h639769[44] && - !_theResult____h639769[43] && - !_theResult____h639769[42] && - !_theResult____h639769[41] && - !_theResult____h639769[40] && - !_theResult____h639769[39] && - !_theResult____h639769[38] && - !_theResult____h639769[37] && - !_theResult____h639769[36] && - !_theResult____h639769[35] && - !_theResult____h639769[34] && - !_theResult____h639769[33] && - !_theResult____h639769[32] && - !_theResult____h639769[31] && - !_theResult____h639769[30] && - !_theResult____h639769[29] && - !_theResult____h639769[28] && - !_theResult____h639769[27] && - !_theResult____h639769[26] && - !_theResult____h639769[25] && - !_theResult____h639769[24] && - !_theResult____h639769[23] && - !_theResult____h639769[22] && - !_theResult____h639769[21] && - !_theResult____h639769[20] && - !_theResult____h639769[19] && - !_theResult____h639769[18] && - !_theResult____h639769[17] && - !_theResult____h639769[16] && - !_theResult____h639769[15] && - !_theResult____h639769[14] && - !_theResult____h639769[13] && - !_theResult____h639769[12] && - !_theResult____h639769[11] && - !_theResult____h639769[10] && - !_theResult____h639769[9] && - !_theResult____h639769[8] && - !_theResult____h639769[7] && - !_theResult____h639769[6] && - !_theResult____h639769[5] && - !_theResult____h639769[4] && - !_theResult____h639769[3] && - !_theResult____h639769[2] && - !_theResult____h639769[1] && - !_theResult____h639769[0]) ? - _theResult____h639769 : - _theResult___snd__h648047 ; - assign _theResult___snd__h648047 = + assign _theResult___snd__h648015 = { _theResult____h639766[55:0], 1'd0 } ; + assign _theResult___snd__h648026 = + (!_theResult____h639766[56] && _theResult____h639766[55]) ? + _theResult___snd__h648028 : + _theResult___snd__h648038 ; + assign _theResult___snd__h648028 = { _theResult____h639766[54:0], 2'd0 } ; + assign _theResult___snd__h648038 = + (!_theResult____h639766[56] && !_theResult____h639766[55] && + !_theResult____h639766[54] && + !_theResult____h639766[53] && + !_theResult____h639766[52] && + !_theResult____h639766[51] && + !_theResult____h639766[50] && + !_theResult____h639766[49] && + !_theResult____h639766[48] && + !_theResult____h639766[47] && + !_theResult____h639766[46] && + !_theResult____h639766[45] && + !_theResult____h639766[44] && + !_theResult____h639766[43] && + !_theResult____h639766[42] && + !_theResult____h639766[41] && + !_theResult____h639766[40] && + !_theResult____h639766[39] && + !_theResult____h639766[38] && + !_theResult____h639766[37] && + !_theResult____h639766[36] && + !_theResult____h639766[35] && + !_theResult____h639766[34] && + !_theResult____h639766[33] && + !_theResult____h639766[32] && + !_theResult____h639766[31] && + !_theResult____h639766[30] && + !_theResult____h639766[29] && + !_theResult____h639766[28] && + !_theResult____h639766[27] && + !_theResult____h639766[26] && + !_theResult____h639766[25] && + !_theResult____h639766[24] && + !_theResult____h639766[23] && + !_theResult____h639766[22] && + !_theResult____h639766[21] && + !_theResult____h639766[20] && + !_theResult____h639766[19] && + !_theResult____h639766[18] && + !_theResult____h639766[17] && + !_theResult____h639766[16] && + !_theResult____h639766[15] && + !_theResult____h639766[14] && + !_theResult____h639766[13] && + !_theResult____h639766[12] && + !_theResult____h639766[11] && + !_theResult____h639766[10] && + !_theResult____h639766[9] && + !_theResult____h639766[8] && + !_theResult____h639766[7] && + !_theResult____h639766[6] && + !_theResult____h639766[5] && + !_theResult____h639766[4] && + !_theResult____h639766[3] && + !_theResult____h639766[2] && + !_theResult____h639766[1] && + !_theResult____h639766[0]) ? + _theResult____h639766 : + _theResult___snd__h648044 ; + assign _theResult___snd__h648044 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q84[54:0], 2'd0 } ; - assign _theResult___snd__h648070 = - _theResult____h639769 << + assign _theResult___snd__h648067 = + _theResult____h639766 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 ; - assign _theResult___snd__h656638 = + assign _theResult___snd__h656635 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h656652 : - _theResult___snd__h638850 ; - assign _theResult___snd__h656652 = + _theResult___snd__h656649 : + _theResult___snd__h638847 ; + assign _theResult___snd__h656649 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925) ? - sfd__h614530 : - _theResult___snd__h656658 ; - assign _theResult___snd__h656658 = + sfd__h614527 : + _theResult___snd__h656655 ; + assign _theResult___snd__h656655 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q89[54:0], 2'd0 } ; - assign _theResult___snd__h656676 = - sfd__h614530 << + assign _theResult___snd__h656673 = + sfd__h614527 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374) ; - assign _theResult___snd__h675999 = { _theResult____h667879[55:0], 1'd0 } ; - assign _theResult___snd__h676010 = - (!_theResult____h667879[56] && _theResult____h667879[55]) ? - _theResult___snd__h676012 : - _theResult___snd__h676022 ; - assign _theResult___snd__h676012 = { _theResult____h667879[54:0], 2'd0 } ; - assign _theResult___snd__h676022 = - (!_theResult____h667879[56] && !_theResult____h667879[55] && - !_theResult____h667879[54] && - !_theResult____h667879[53] && - !_theResult____h667879[52] && - !_theResult____h667879[51] && - !_theResult____h667879[50] && - !_theResult____h667879[49] && - !_theResult____h667879[48] && - !_theResult____h667879[47] && - !_theResult____h667879[46] && - !_theResult____h667879[45] && - !_theResult____h667879[44] && - !_theResult____h667879[43] && - !_theResult____h667879[42] && - !_theResult____h667879[41] && - !_theResult____h667879[40] && - !_theResult____h667879[39] && - !_theResult____h667879[38] && - !_theResult____h667879[37] && - !_theResult____h667879[36] && - !_theResult____h667879[35] && - !_theResult____h667879[34] && - !_theResult____h667879[33] && - !_theResult____h667879[32] && - !_theResult____h667879[31] && - !_theResult____h667879[30] && - !_theResult____h667879[29] && - !_theResult____h667879[28] && - !_theResult____h667879[27] && - !_theResult____h667879[26] && - !_theResult____h667879[25] && - !_theResult____h667879[24] && - !_theResult____h667879[23] && - !_theResult____h667879[22] && - !_theResult____h667879[21] && - !_theResult____h667879[20] && - !_theResult____h667879[19] && - !_theResult____h667879[18] && - !_theResult____h667879[17] && - !_theResult____h667879[16] && - !_theResult____h667879[15] && - !_theResult____h667879[14] && - !_theResult____h667879[13] && - !_theResult____h667879[12] && - !_theResult____h667879[11] && - !_theResult____h667879[10] && - !_theResult____h667879[9] && - !_theResult____h667879[8] && - !_theResult____h667879[7] && - !_theResult____h667879[6] && - !_theResult____h667879[5] && - !_theResult____h667879[4] && - !_theResult____h667879[3] && - !_theResult____h667879[2] && - !_theResult____h667879[1] && - !_theResult____h667879[0]) ? - _theResult____h667879 : - _theResult___snd__h676028 ; - assign _theResult___snd__h676028 = + assign _theResult___snd__h675996 = { _theResult____h667876[55:0], 1'd0 } ; + assign _theResult___snd__h676007 = + (!_theResult____h667876[56] && _theResult____h667876[55]) ? + _theResult___snd__h676009 : + _theResult___snd__h676019 ; + assign _theResult___snd__h676009 = { _theResult____h667876[54:0], 2'd0 } ; + assign _theResult___snd__h676019 = + (!_theResult____h667876[56] && !_theResult____h667876[55] && + !_theResult____h667876[54] && + !_theResult____h667876[53] && + !_theResult____h667876[52] && + !_theResult____h667876[51] && + !_theResult____h667876[50] && + !_theResult____h667876[49] && + !_theResult____h667876[48] && + !_theResult____h667876[47] && + !_theResult____h667876[46] && + !_theResult____h667876[45] && + !_theResult____h667876[44] && + !_theResult____h667876[43] && + !_theResult____h667876[42] && + !_theResult____h667876[41] && + !_theResult____h667876[40] && + !_theResult____h667876[39] && + !_theResult____h667876[38] && + !_theResult____h667876[37] && + !_theResult____h667876[36] && + !_theResult____h667876[35] && + !_theResult____h667876[34] && + !_theResult____h667876[33] && + !_theResult____h667876[32] && + !_theResult____h667876[31] && + !_theResult____h667876[30] && + !_theResult____h667876[29] && + !_theResult____h667876[28] && + !_theResult____h667876[27] && + !_theResult____h667876[26] && + !_theResult____h667876[25] && + !_theResult____h667876[24] && + !_theResult____h667876[23] && + !_theResult____h667876[22] && + !_theResult____h667876[21] && + !_theResult____h667876[20] && + !_theResult____h667876[19] && + !_theResult____h667876[18] && + !_theResult____h667876[17] && + !_theResult____h667876[16] && + !_theResult____h667876[15] && + !_theResult____h667876[14] && + !_theResult____h667876[13] && + !_theResult____h667876[12] && + !_theResult____h667876[11] && + !_theResult____h667876[10] && + !_theResult____h667876[9] && + !_theResult____h667876[8] && + !_theResult____h667876[7] && + !_theResult____h667876[6] && + !_theResult____h667876[5] && + !_theResult____h667876[4] && + !_theResult____h667876[3] && + !_theResult____h667876[2] && + !_theResult____h667876[1] && + !_theResult____h667876[0]) ? + _theResult____h667876 : + _theResult___snd__h676025 ; + assign _theResult___snd__h676025 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109[54:0], 2'd0 } ; - assign _theResult___snd__h676051 = - _theResult____h667879 << + assign _theResult___snd__h676048 = + _theResult____h667876 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 ; - assign _theResult___snd__h684595 = + assign _theResult___snd__h684592 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h684604 : - _theResult___snd__h684597 ; - assign _theResult___snd__h684597 = + _theResult___snd__h684601 : + _theResult___snd__h684594 ; + assign _theResult___snd__h684594 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h684604 = + assign _theResult___snd__h684601 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322) ? - sfd__h660277 : - _theResult___snd__h684610 ; - assign _theResult___snd__h684610 = + sfd__h660274 : + _theResult___snd__h684607 ; + assign _theResult___snd__h684607 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q111[54:0], 2'd0 } ; - assign _theResult___snd__h684633 = - sfd__h660277 << + assign _theResult___snd__h684630 = + sfd__h660274 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 ; - assign _theResult___snd__h693765 = { _theResult____h685516[55:0], 1'd0 } ; - assign _theResult___snd__h693776 = - (!_theResult____h685516[56] && _theResult____h685516[55]) ? - _theResult___snd__h693778 : - _theResult___snd__h693788 ; - assign _theResult___snd__h693778 = { _theResult____h685516[54:0], 2'd0 } ; - assign _theResult___snd__h693788 = - (!_theResult____h685516[56] && !_theResult____h685516[55] && - !_theResult____h685516[54] && - !_theResult____h685516[53] && - !_theResult____h685516[52] && - !_theResult____h685516[51] && - !_theResult____h685516[50] && - !_theResult____h685516[49] && - !_theResult____h685516[48] && - !_theResult____h685516[47] && - !_theResult____h685516[46] && - !_theResult____h685516[45] && - !_theResult____h685516[44] && - !_theResult____h685516[43] && - !_theResult____h685516[42] && - !_theResult____h685516[41] && - !_theResult____h685516[40] && - !_theResult____h685516[39] && - !_theResult____h685516[38] && - !_theResult____h685516[37] && - !_theResult____h685516[36] && - !_theResult____h685516[35] && - !_theResult____h685516[34] && - !_theResult____h685516[33] && - !_theResult____h685516[32] && - !_theResult____h685516[31] && - !_theResult____h685516[30] && - !_theResult____h685516[29] && - !_theResult____h685516[28] && - !_theResult____h685516[27] && - !_theResult____h685516[26] && - !_theResult____h685516[25] && - !_theResult____h685516[24] && - !_theResult____h685516[23] && - !_theResult____h685516[22] && - !_theResult____h685516[21] && - !_theResult____h685516[20] && - !_theResult____h685516[19] && - !_theResult____h685516[18] && - !_theResult____h685516[17] && - !_theResult____h685516[16] && - !_theResult____h685516[15] && - !_theResult____h685516[14] && - !_theResult____h685516[13] && - !_theResult____h685516[12] && - !_theResult____h685516[11] && - !_theResult____h685516[10] && - !_theResult____h685516[9] && - !_theResult____h685516[8] && - !_theResult____h685516[7] && - !_theResult____h685516[6] && - !_theResult____h685516[5] && - !_theResult____h685516[4] && - !_theResult____h685516[3] && - !_theResult____h685516[2] && - !_theResult____h685516[1] && - !_theResult____h685516[0]) ? - _theResult____h685516 : - _theResult___snd__h693794 ; - assign _theResult___snd__h693794 = + assign _theResult___snd__h693762 = { _theResult____h685513[55:0], 1'd0 } ; + assign _theResult___snd__h693773 = + (!_theResult____h685513[56] && _theResult____h685513[55]) ? + _theResult___snd__h693775 : + _theResult___snd__h693785 ; + assign _theResult___snd__h693775 = { _theResult____h685513[54:0], 2'd0 } ; + assign _theResult___snd__h693785 = + (!_theResult____h685513[56] && !_theResult____h685513[55] && + !_theResult____h685513[54] && + !_theResult____h685513[53] && + !_theResult____h685513[52] && + !_theResult____h685513[51] && + !_theResult____h685513[50] && + !_theResult____h685513[49] && + !_theResult____h685513[48] && + !_theResult____h685513[47] && + !_theResult____h685513[46] && + !_theResult____h685513[45] && + !_theResult____h685513[44] && + !_theResult____h685513[43] && + !_theResult____h685513[42] && + !_theResult____h685513[41] && + !_theResult____h685513[40] && + !_theResult____h685513[39] && + !_theResult____h685513[38] && + !_theResult____h685513[37] && + !_theResult____h685513[36] && + !_theResult____h685513[35] && + !_theResult____h685513[34] && + !_theResult____h685513[33] && + !_theResult____h685513[32] && + !_theResult____h685513[31] && + !_theResult____h685513[30] && + !_theResult____h685513[29] && + !_theResult____h685513[28] && + !_theResult____h685513[27] && + !_theResult____h685513[26] && + !_theResult____h685513[25] && + !_theResult____h685513[24] && + !_theResult____h685513[23] && + !_theResult____h685513[22] && + !_theResult____h685513[21] && + !_theResult____h685513[20] && + !_theResult____h685513[19] && + !_theResult____h685513[18] && + !_theResult____h685513[17] && + !_theResult____h685513[16] && + !_theResult____h685513[15] && + !_theResult____h685513[14] && + !_theResult____h685513[13] && + !_theResult____h685513[12] && + !_theResult____h685513[11] && + !_theResult____h685513[10] && + !_theResult____h685513[9] && + !_theResult____h685513[8] && + !_theResult____h685513[7] && + !_theResult____h685513[6] && + !_theResult____h685513[5] && + !_theResult____h685513[4] && + !_theResult____h685513[3] && + !_theResult____h685513[2] && + !_theResult____h685513[1] && + !_theResult____h685513[0]) ? + _theResult____h685513 : + _theResult___snd__h693791 ; + assign _theResult___snd__h693791 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q119[54:0], 2'd0 } ; - assign _theResult___snd__h693817 = - _theResult____h685516 << + assign _theResult___snd__h693814 = + _theResult____h685513 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 ; - assign _theResult___snd__h702385 = + assign _theResult___snd__h702382 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h702399 : - _theResult___snd__h684597 ; - assign _theResult___snd__h702399 = + _theResult___snd__h702396 : + _theResult___snd__h684594 ; + assign _theResult___snd__h702396 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322) ? - sfd__h660277 : - _theResult___snd__h702405 ; - assign _theResult___snd__h702405 = + sfd__h660274 : + _theResult___snd__h702402 ; + assign _theResult___snd__h702402 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q124[54:0], 2'd0 } ; - assign _theResult___snd__h702423 = - sfd__h660277 << + assign _theResult___snd__h702420 = + sfd__h660274 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771) ; - assign _theResult___snd__h734164 = - (f1_exp__h714825 == 8'd0) ? - _theResult___snd__h734173 : - _theResult___snd__h734166 ; - assign _theResult___snd__h734166 = { f1_sfd__h714826, 34'd0 } ; - assign _theResult___snd__h734173 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___snd__h734161 = + (f1_exp__h714822 == 8'd0) ? + _theResult___snd__h734170 : + _theResult___snd__h734163 ; + assign _theResult___snd__h734163 = { f1_sfd__h714823, 34'd0 } ; + assign _theResult___snd__h734170 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689) ? - sfd__h715187 : - _theResult___snd__h734179 ; - assign _theResult___snd__h734179 = + sfd__h715184 : + _theResult___snd__h734176 ; + assign _theResult___snd__h734176 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145[54:0], 2'd0 } ; - assign _theResult___snd__h734202 = - sfd__h715187 << + assign _theResult___snd__h734199 = + sfd__h715184 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 ; - assign _theResult___snd__h743801 = { _theResult____h735554[55:0], 1'd0 } ; - assign _theResult___snd__h743812 = - (!_theResult____h735554[56] && _theResult____h735554[55]) ? - _theResult___snd__h743814 : - _theResult___snd__h743824 ; - assign _theResult___snd__h743814 = { _theResult____h735554[54:0], 2'd0 } ; - assign _theResult___snd__h743824 = - (!_theResult____h735554[56] && !_theResult____h735554[55] && - !_theResult____h735554[54] && - !_theResult____h735554[53] && - !_theResult____h735554[52] && - !_theResult____h735554[51] && - !_theResult____h735554[50] && - !_theResult____h735554[49] && - !_theResult____h735554[48] && - !_theResult____h735554[47] && - !_theResult____h735554[46] && - !_theResult____h735554[45] && - !_theResult____h735554[44] && - !_theResult____h735554[43] && - !_theResult____h735554[42] && - !_theResult____h735554[41] && - !_theResult____h735554[40] && - !_theResult____h735554[39] && - !_theResult____h735554[38] && - !_theResult____h735554[37] && - !_theResult____h735554[36] && - !_theResult____h735554[35] && - !_theResult____h735554[34] && - !_theResult____h735554[33] && - !_theResult____h735554[32] && - !_theResult____h735554[31] && - !_theResult____h735554[30] && - !_theResult____h735554[29] && - !_theResult____h735554[28] && - !_theResult____h735554[27] && - !_theResult____h735554[26] && - !_theResult____h735554[25] && - !_theResult____h735554[24] && - !_theResult____h735554[23] && - !_theResult____h735554[22] && - !_theResult____h735554[21] && - !_theResult____h735554[20] && - !_theResult____h735554[19] && - !_theResult____h735554[18] && - !_theResult____h735554[17] && - !_theResult____h735554[16] && - !_theResult____h735554[15] && - !_theResult____h735554[14] && - !_theResult____h735554[13] && - !_theResult____h735554[12] && - !_theResult____h735554[11] && - !_theResult____h735554[10] && - !_theResult____h735554[9] && - !_theResult____h735554[8] && - !_theResult____h735554[7] && - !_theResult____h735554[6] && - !_theResult____h735554[5] && - !_theResult____h735554[4] && - !_theResult____h735554[3] && - !_theResult____h735554[2] && - !_theResult____h735554[1] && - !_theResult____h735554[0]) ? - _theResult____h735554 : - _theResult___snd__h743830 ; - assign _theResult___snd__h743830 = + assign _theResult___snd__h743798 = { _theResult____h735551[55:0], 1'd0 } ; + assign _theResult___snd__h743809 = + (!_theResult____h735551[56] && _theResult____h735551[55]) ? + _theResult___snd__h743811 : + _theResult___snd__h743821 ; + assign _theResult___snd__h743811 = { _theResult____h735551[54:0], 2'd0 } ; + assign _theResult___snd__h743821 = + (!_theResult____h735551[56] && !_theResult____h735551[55] && + !_theResult____h735551[54] && + !_theResult____h735551[53] && + !_theResult____h735551[52] && + !_theResult____h735551[51] && + !_theResult____h735551[50] && + !_theResult____h735551[49] && + !_theResult____h735551[48] && + !_theResult____h735551[47] && + !_theResult____h735551[46] && + !_theResult____h735551[45] && + !_theResult____h735551[44] && + !_theResult____h735551[43] && + !_theResult____h735551[42] && + !_theResult____h735551[41] && + !_theResult____h735551[40] && + !_theResult____h735551[39] && + !_theResult____h735551[38] && + !_theResult____h735551[37] && + !_theResult____h735551[36] && + !_theResult____h735551[35] && + !_theResult____h735551[34] && + !_theResult____h735551[33] && + !_theResult____h735551[32] && + !_theResult____h735551[31] && + !_theResult____h735551[30] && + !_theResult____h735551[29] && + !_theResult____h735551[28] && + !_theResult____h735551[27] && + !_theResult____h735551[26] && + !_theResult____h735551[25] && + !_theResult____h735551[24] && + !_theResult____h735551[23] && + !_theResult____h735551[22] && + !_theResult____h735551[21] && + !_theResult____h735551[20] && + !_theResult____h735551[19] && + !_theResult____h735551[18] && + !_theResult____h735551[17] && + !_theResult____h735551[16] && + !_theResult____h735551[15] && + !_theResult____h735551[14] && + !_theResult____h735551[13] && + !_theResult____h735551[12] && + !_theResult____h735551[11] && + !_theResult____h735551[10] && + !_theResult____h735551[9] && + !_theResult____h735551[8] && + !_theResult____h735551[7] && + !_theResult____h735551[6] && + !_theResult____h735551[5] && + !_theResult____h735551[4] && + !_theResult____h735551[3] && + !_theResult____h735551[2] && + !_theResult____h735551[1] && + !_theResult____h735551[0]) ? + _theResult____h735551 : + _theResult___snd__h743827 ; + assign _theResult___snd__h743827 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149[54:0], 2'd0 } ; - assign _theResult___snd__h743853 = - _theResult____h735554 << + assign _theResult___snd__h743850 = + _theResult____h735551 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 ; - assign _theResult___snd__h752569 = - (f1_exp__h714825 == 8'd0) ? - _theResult___snd__h752583 : - _theResult___snd__h734166 ; - assign _theResult___snd__h752583 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___snd__h752566 = + (f1_exp__h714822 == 8'd0) ? + _theResult___snd__h752580 : + _theResult___snd__h734163 ; + assign _theResult___snd__h752580 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689) ? - sfd__h715187 : - _theResult___snd__h752589 ; - assign _theResult___snd__h752589 = + sfd__h715184 : + _theResult___snd__h752586 ; + assign _theResult___snd__h752586 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152[54:0], 2'd0 } ; - assign _theResult___snd__h752607 = - sfd__h715187 << + assign _theResult___snd__h752604 = + sfd__h715184 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13079 ; - assign _theResult___snd__h773017 = - (f2_exp__h753819 == 8'd0) ? - _theResult___snd__h773026 : - _theResult___snd__h773019 ; - assign _theResult___snd__h773019 = { f2_sfd__h753820, 34'd0 } ; - assign _theResult___snd__h773026 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___snd__h773014 = + (f2_exp__h753816 == 8'd0) ? + _theResult___snd__h773023 : + _theResult___snd__h773016 ; + assign _theResult___snd__h773016 = { f2_sfd__h753817, 34'd0 } ; + assign _theResult___snd__h773023 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189) ? - sfd__h754181 : - _theResult___snd__h773032 ; - assign _theResult___snd__h773032 = + sfd__h754178 : + _theResult___snd__h773029 ; + assign _theResult___snd__h773029 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185[54:0], 2'd0 } ; - assign _theResult___snd__h773055 = - sfd__h754181 << + assign _theResult___snd__h773052 = + sfd__h754178 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 ; - assign _theResult___snd__h782654 = { _theResult____h774407[55:0], 1'd0 } ; - assign _theResult___snd__h782665 = - (!_theResult____h774407[56] && _theResult____h774407[55]) ? - _theResult___snd__h782667 : - _theResult___snd__h782677 ; - assign _theResult___snd__h782667 = { _theResult____h774407[54:0], 2'd0 } ; - assign _theResult___snd__h782677 = - (!_theResult____h774407[56] && !_theResult____h774407[55] && - !_theResult____h774407[54] && - !_theResult____h774407[53] && - !_theResult____h774407[52] && - !_theResult____h774407[51] && - !_theResult____h774407[50] && - !_theResult____h774407[49] && - !_theResult____h774407[48] && - !_theResult____h774407[47] && - !_theResult____h774407[46] && - !_theResult____h774407[45] && - !_theResult____h774407[44] && - !_theResult____h774407[43] && - !_theResult____h774407[42] && - !_theResult____h774407[41] && - !_theResult____h774407[40] && - !_theResult____h774407[39] && - !_theResult____h774407[38] && - !_theResult____h774407[37] && - !_theResult____h774407[36] && - !_theResult____h774407[35] && - !_theResult____h774407[34] && - !_theResult____h774407[33] && - !_theResult____h774407[32] && - !_theResult____h774407[31] && - !_theResult____h774407[30] && - !_theResult____h774407[29] && - !_theResult____h774407[28] && - !_theResult____h774407[27] && - !_theResult____h774407[26] && - !_theResult____h774407[25] && - !_theResult____h774407[24] && - !_theResult____h774407[23] && - !_theResult____h774407[22] && - !_theResult____h774407[21] && - !_theResult____h774407[20] && - !_theResult____h774407[19] && - !_theResult____h774407[18] && - !_theResult____h774407[17] && - !_theResult____h774407[16] && - !_theResult____h774407[15] && - !_theResult____h774407[14] && - !_theResult____h774407[13] && - !_theResult____h774407[12] && - !_theResult____h774407[11] && - !_theResult____h774407[10] && - !_theResult____h774407[9] && - !_theResult____h774407[8] && - !_theResult____h774407[7] && - !_theResult____h774407[6] && - !_theResult____h774407[5] && - !_theResult____h774407[4] && - !_theResult____h774407[3] && - !_theResult____h774407[2] && - !_theResult____h774407[1] && - !_theResult____h774407[0]) ? - _theResult____h774407 : - _theResult___snd__h782683 ; - assign _theResult___snd__h782683 = + assign _theResult___snd__h782651 = { _theResult____h774404[55:0], 1'd0 } ; + assign _theResult___snd__h782662 = + (!_theResult____h774404[56] && _theResult____h774404[55]) ? + _theResult___snd__h782664 : + _theResult___snd__h782674 ; + assign _theResult___snd__h782664 = { _theResult____h774404[54:0], 2'd0 } ; + assign _theResult___snd__h782674 = + (!_theResult____h774404[56] && !_theResult____h774404[55] && + !_theResult____h774404[54] && + !_theResult____h774404[53] && + !_theResult____h774404[52] && + !_theResult____h774404[51] && + !_theResult____h774404[50] && + !_theResult____h774404[49] && + !_theResult____h774404[48] && + !_theResult____h774404[47] && + !_theResult____h774404[46] && + !_theResult____h774404[45] && + !_theResult____h774404[44] && + !_theResult____h774404[43] && + !_theResult____h774404[42] && + !_theResult____h774404[41] && + !_theResult____h774404[40] && + !_theResult____h774404[39] && + !_theResult____h774404[38] && + !_theResult____h774404[37] && + !_theResult____h774404[36] && + !_theResult____h774404[35] && + !_theResult____h774404[34] && + !_theResult____h774404[33] && + !_theResult____h774404[32] && + !_theResult____h774404[31] && + !_theResult____h774404[30] && + !_theResult____h774404[29] && + !_theResult____h774404[28] && + !_theResult____h774404[27] && + !_theResult____h774404[26] && + !_theResult____h774404[25] && + !_theResult____h774404[24] && + !_theResult____h774404[23] && + !_theResult____h774404[22] && + !_theResult____h774404[21] && + !_theResult____h774404[20] && + !_theResult____h774404[19] && + !_theResult____h774404[18] && + !_theResult____h774404[17] && + !_theResult____h774404[16] && + !_theResult____h774404[15] && + !_theResult____h774404[14] && + !_theResult____h774404[13] && + !_theResult____h774404[12] && + !_theResult____h774404[11] && + !_theResult____h774404[10] && + !_theResult____h774404[9] && + !_theResult____h774404[8] && + !_theResult____h774404[7] && + !_theResult____h774404[6] && + !_theResult____h774404[5] && + !_theResult____h774404[4] && + !_theResult____h774404[3] && + !_theResult____h774404[2] && + !_theResult____h774404[1] && + !_theResult____h774404[0]) ? + _theResult____h774404 : + _theResult___snd__h782680 ; + assign _theResult___snd__h782680 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189[54:0], 2'd0 } ; - assign _theResult___snd__h782706 = - _theResult____h774407 << + assign _theResult___snd__h782703 = + _theResult____h774404 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 ; - assign _theResult___snd__h791422 = - (f2_exp__h753819 == 8'd0) ? - _theResult___snd__h791436 : - _theResult___snd__h773019 ; - assign _theResult___snd__h791436 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___snd__h791419 = + (f2_exp__h753816 == 8'd0) ? + _theResult___snd__h791433 : + _theResult___snd__h773016 ; + assign _theResult___snd__h791433 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189) ? - sfd__h754181 : - _theResult___snd__h791442 ; - assign _theResult___snd__h791442 = + sfd__h754178 : + _theResult___snd__h791439 ; + assign _theResult___snd__h791439 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192[54:0], 2'd0 } ; - assign _theResult___snd__h791460 = - sfd__h754181 << + assign _theResult___snd__h791457 = + sfd__h754178 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14564 ; - assign _theResult___snd__h812321 = - (f3_exp__h793123 == 8'd0) ? - _theResult___snd__h812330 : - _theResult___snd__h812323 ; - assign _theResult___snd__h812323 = { f3_sfd__h793124, 34'd0 } ; - assign _theResult___snd__h812330 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___snd__h812318 = + (f3_exp__h793120 == 8'd0) ? + _theResult___snd__h812327 : + _theResult___snd__h812320 ; + assign _theResult___snd__h812320 = { f3_sfd__h793121, 34'd0 } ; + assign _theResult___snd__h812327 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419) ? - sfd__h793485 : - _theResult___snd__h812336 ; - assign _theResult___snd__h812336 = + sfd__h793482 : + _theResult___snd__h812333 ; + assign _theResult___snd__h812333 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162[54:0], 2'd0 } ; - assign _theResult___snd__h812359 = - sfd__h793485 << + assign _theResult___snd__h812356 = + sfd__h793482 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 ; - assign _theResult___snd__h821958 = { _theResult____h813711[55:0], 1'd0 } ; - assign _theResult___snd__h821969 = - (!_theResult____h813711[56] && _theResult____h813711[55]) ? - _theResult___snd__h821971 : - _theResult___snd__h821981 ; - assign _theResult___snd__h821971 = { _theResult____h813711[54:0], 2'd0 } ; - assign _theResult___snd__h821981 = - (!_theResult____h813711[56] && !_theResult____h813711[55] && - !_theResult____h813711[54] && - !_theResult____h813711[53] && - !_theResult____h813711[52] && - !_theResult____h813711[51] && - !_theResult____h813711[50] && - !_theResult____h813711[49] && - !_theResult____h813711[48] && - !_theResult____h813711[47] && - !_theResult____h813711[46] && - !_theResult____h813711[45] && - !_theResult____h813711[44] && - !_theResult____h813711[43] && - !_theResult____h813711[42] && - !_theResult____h813711[41] && - !_theResult____h813711[40] && - !_theResult____h813711[39] && - !_theResult____h813711[38] && - !_theResult____h813711[37] && - !_theResult____h813711[36] && - !_theResult____h813711[35] && - !_theResult____h813711[34] && - !_theResult____h813711[33] && - !_theResult____h813711[32] && - !_theResult____h813711[31] && - !_theResult____h813711[30] && - !_theResult____h813711[29] && - !_theResult____h813711[28] && - !_theResult____h813711[27] && - !_theResult____h813711[26] && - !_theResult____h813711[25] && - !_theResult____h813711[24] && - !_theResult____h813711[23] && - !_theResult____h813711[22] && - !_theResult____h813711[21] && - !_theResult____h813711[20] && - !_theResult____h813711[19] && - !_theResult____h813711[18] && - !_theResult____h813711[17] && - !_theResult____h813711[16] && - !_theResult____h813711[15] && - !_theResult____h813711[14] && - !_theResult____h813711[13] && - !_theResult____h813711[12] && - !_theResult____h813711[11] && - !_theResult____h813711[10] && - !_theResult____h813711[9] && - !_theResult____h813711[8] && - !_theResult____h813711[7] && - !_theResult____h813711[6] && - !_theResult____h813711[5] && - !_theResult____h813711[4] && - !_theResult____h813711[3] && - !_theResult____h813711[2] && - !_theResult____h813711[1] && - !_theResult____h813711[0]) ? - _theResult____h813711 : - _theResult___snd__h821987 ; - assign _theResult___snd__h821987 = + assign _theResult___snd__h821955 = { _theResult____h813708[55:0], 1'd0 } ; + assign _theResult___snd__h821966 = + (!_theResult____h813708[56] && _theResult____h813708[55]) ? + _theResult___snd__h821968 : + _theResult___snd__h821978 ; + assign _theResult___snd__h821968 = { _theResult____h813708[54:0], 2'd0 } ; + assign _theResult___snd__h821978 = + (!_theResult____h813708[56] && !_theResult____h813708[55] && + !_theResult____h813708[54] && + !_theResult____h813708[53] && + !_theResult____h813708[52] && + !_theResult____h813708[51] && + !_theResult____h813708[50] && + !_theResult____h813708[49] && + !_theResult____h813708[48] && + !_theResult____h813708[47] && + !_theResult____h813708[46] && + !_theResult____h813708[45] && + !_theResult____h813708[44] && + !_theResult____h813708[43] && + !_theResult____h813708[42] && + !_theResult____h813708[41] && + !_theResult____h813708[40] && + !_theResult____h813708[39] && + !_theResult____h813708[38] && + !_theResult____h813708[37] && + !_theResult____h813708[36] && + !_theResult____h813708[35] && + !_theResult____h813708[34] && + !_theResult____h813708[33] && + !_theResult____h813708[32] && + !_theResult____h813708[31] && + !_theResult____h813708[30] && + !_theResult____h813708[29] && + !_theResult____h813708[28] && + !_theResult____h813708[27] && + !_theResult____h813708[26] && + !_theResult____h813708[25] && + !_theResult____h813708[24] && + !_theResult____h813708[23] && + !_theResult____h813708[22] && + !_theResult____h813708[21] && + !_theResult____h813708[20] && + !_theResult____h813708[19] && + !_theResult____h813708[18] && + !_theResult____h813708[17] && + !_theResult____h813708[16] && + !_theResult____h813708[15] && + !_theResult____h813708[14] && + !_theResult____h813708[13] && + !_theResult____h813708[12] && + !_theResult____h813708[11] && + !_theResult____h813708[10] && + !_theResult____h813708[9] && + !_theResult____h813708[8] && + !_theResult____h813708[7] && + !_theResult____h813708[6] && + !_theResult____h813708[5] && + !_theResult____h813708[4] && + !_theResult____h813708[3] && + !_theResult____h813708[2] && + !_theResult____h813708[1] && + !_theResult____h813708[0]) ? + _theResult____h813708 : + _theResult___snd__h821984 ; + assign _theResult___snd__h821984 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h822010 = - _theResult____h813711 << + assign _theResult___snd__h822007 = + _theResult____h813708 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 ; - assign _theResult___snd__h830726 = - (f3_exp__h793123 == 8'd0) ? - _theResult___snd__h830740 : - _theResult___snd__h812323 ; - assign _theResult___snd__h830740 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___snd__h830723 = + (f3_exp__h793120 == 8'd0) ? + _theResult___snd__h830737 : + _theResult___snd__h812320 ; + assign _theResult___snd__h830737 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419) ? - sfd__h793485 : - _theResult___snd__h830746 ; - assign _theResult___snd__h830746 = + sfd__h793482 : + _theResult___snd__h830743 ; + assign _theResult___snd__h830743 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169[54:0], 2'd0 } ; - assign _theResult___snd__h830764 = - sfd__h793485 << + assign _theResult___snd__h830761 = + sfd__h793482 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13794 ; - assign _theResult___snd__h836056 = - b__h835634[63] ? b___1__h836105 : b__h835634 ; - assign _theResult___snd_fst_exp__h593674 = + assign _theResult___snd__h836053 = + b__h835631[63] ? b___1__h836102 : b__h835631 ; + assign _theResult___snd_fst_exp__h593671 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - _theResult___fst_exp__h585089 : - _theResult___fst_exp__h593671 ; - assign _theResult___snd_fst_exp__h611494 = + _theResult___fst_exp__h585086 : + _theResult___fst_exp__h593668 ; + assign _theResult___snd_fst_exp__h611491 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - _theResult___fst_exp__h602855 : - _theResult___fst_exp__h611491 ; - assign _theResult___snd_fst_exp__h639423 = + _theResult___fst_exp__h602852 : + _theResult___fst_exp__h611488 ; + assign _theResult___snd_fst_exp__h639420 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - _theResult___fst_exp__h630838 : - _theResult___fst_exp__h639420 ; - assign _theResult___snd_fst_exp__h657243 = + _theResult___fst_exp__h630835 : + _theResult___fst_exp__h639417 ; + assign _theResult___snd_fst_exp__h657240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - _theResult___fst_exp__h648604 : - _theResult___fst_exp__h657240 ; - assign _theResult___snd_fst_exp__h685170 = + _theResult___fst_exp__h648601 : + _theResult___fst_exp__h657237 ; + assign _theResult___snd_fst_exp__h685167 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - _theResult___fst_exp__h676585 : - _theResult___fst_exp__h685167 ; - assign _theResult___snd_fst_exp__h702990 = + _theResult___fst_exp__h676582 : + _theResult___fst_exp__h685164 ; + assign _theResult___snd_fst_exp__h702987 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - _theResult___fst_exp__h694351 : - _theResult___fst_exp__h702987 ; - assign _theResult___snd_fst_exp__h734974 = + _theResult___fst_exp__h694348 : + _theResult___fst_exp__h702984 ; + assign _theResult___snd_fst_exp__h734971 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 ? 11'd0 : - _theResult___fst_exp__h734971 ; - assign _theResult___snd_fst_exp__h753409 = + _theResult___fst_exp__h734968 ; + assign _theResult___snd_fst_exp__h753406 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? - _theResult___fst_exp__h744622 : - _theResult___fst_exp__h753406 ; - assign _theResult___snd_fst_exp__h773827 = + _theResult___fst_exp__h744619 : + _theResult___fst_exp__h753403 ; + assign _theResult___snd_fst_exp__h773824 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? 11'd0 : - _theResult___fst_exp__h773824 ; - assign _theResult___snd_fst_exp__h792262 = + _theResult___fst_exp__h773821 ; + assign _theResult___snd_fst_exp__h792259 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? - _theResult___fst_exp__h783475 : - _theResult___fst_exp__h792259 ; - assign _theResult___snd_fst_exp__h813131 = + _theResult___fst_exp__h783472 : + _theResult___fst_exp__h792256 ; + assign _theResult___snd_fst_exp__h813128 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? 11'd0 : - _theResult___fst_exp__h813128 ; - assign _theResult___snd_fst_exp__h831566 = + _theResult___fst_exp__h813125 ; + assign _theResult___snd_fst_exp__h831563 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? - _theResult___fst_exp__h822779 : - _theResult___fst_exp__h831563 ; - assign _theResult___snd_fst_sfd__h568726 = + _theResult___fst_exp__h822776 : + _theResult___fst_exp__h831560 ; + assign _theResult___snd_fst_sfd__h568723 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h593675 = + assign _theResult___snd_fst_sfd__h593672 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - _theResult___fst_sfd__h585090 : - _theResult___fst_sfd__h593672 ; - assign _theResult___snd_fst_sfd__h611495 = + _theResult___fst_sfd__h585087 : + _theResult___fst_sfd__h593669 ; + assign _theResult___snd_fst_sfd__h611492 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - _theResult___fst_sfd__h602856 : - _theResult___fst_sfd__h611492 ; - assign _theResult___snd_fst_sfd__h614480 = + _theResult___fst_sfd__h602853 : + _theResult___fst_sfd__h611489 ; + assign _theResult___snd_fst_sfd__h614477 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h639424 = + assign _theResult___snd_fst_sfd__h639421 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - _theResult___fst_sfd__h630839 : - _theResult___fst_sfd__h639421 ; - assign _theResult___snd_fst_sfd__h657244 = + _theResult___fst_sfd__h630836 : + _theResult___fst_sfd__h639418 ; + assign _theResult___snd_fst_sfd__h657241 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - _theResult___fst_sfd__h648605 : - _theResult___fst_sfd__h657241 ; - assign _theResult___snd_fst_sfd__h660227 = + _theResult___fst_sfd__h648602 : + _theResult___fst_sfd__h657238 ; + assign _theResult___snd_fst_sfd__h660224 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h685171 = + assign _theResult___snd_fst_sfd__h685168 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - _theResult___fst_sfd__h676586 : - _theResult___fst_sfd__h685168 ; - assign _theResult___snd_fst_sfd__h702991 = + _theResult___fst_sfd__h676583 : + _theResult___fst_sfd__h685165 ; + assign _theResult___snd_fst_sfd__h702988 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - _theResult___fst_sfd__h694352 : - _theResult___fst_sfd__h702988 ; - assign _theResult___snd_fst_sfd__h715141 = - (f1_sfd__h714826 == 23'd0) ? + _theResult___fst_sfd__h694349 : + _theResult___fst_sfd__h702985 ; + assign _theResult___snd_fst_sfd__h715138 = + (f1_sfd__h714823 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h714889 ; - assign _theResult___snd_fst_sfd__h734975 = + out___1_sfd__h714886 ; + assign _theResult___snd_fst_sfd__h734972 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 ? 52'd0 : - _theResult___fst_sfd__h734972 ; - assign _theResult___snd_fst_sfd__h753410 = + _theResult___fst_sfd__h734969 ; + assign _theResult___snd_fst_sfd__h753407 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? - _theResult___fst_sfd__h744623 : - _theResult___fst_sfd__h753407 ; - assign _theResult___snd_fst_sfd__h754135 = - (f2_sfd__h753820 == 23'd0) ? + _theResult___fst_sfd__h744620 : + _theResult___fst_sfd__h753404 ; + assign _theResult___snd_fst_sfd__h754132 = + (f2_sfd__h753817 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h753883 ; - assign _theResult___snd_fst_sfd__h773828 = + out___1_sfd__h753880 ; + assign _theResult___snd_fst_sfd__h773825 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? 52'd0 : - _theResult___fst_sfd__h773825 ; - assign _theResult___snd_fst_sfd__h792263 = + _theResult___fst_sfd__h773822 ; + assign _theResult___snd_fst_sfd__h792260 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? - _theResult___fst_sfd__h783476 : - _theResult___fst_sfd__h792260 ; - assign _theResult___snd_fst_sfd__h793439 = - (f3_sfd__h793124 == 23'd0) ? + _theResult___fst_sfd__h783473 : + _theResult___fst_sfd__h792257 ; + assign _theResult___snd_fst_sfd__h793436 = + (f3_sfd__h793121 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h793187 ; - assign _theResult___snd_fst_sfd__h813132 = + out___1_sfd__h793184 ; + assign _theResult___snd_fst_sfd__h813129 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? 52'd0 : - _theResult___fst_sfd__h813129 ; - assign _theResult___snd_fst_sfd__h831567 = + _theResult___fst_sfd__h813126 ; + assign _theResult___snd_fst_sfd__h831564 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? - _theResult___fst_sfd__h822780 : - _theResult___fst_sfd__h831564 ; - assign a___1__h835774 = + _theResult___fst_sfd__h822777 : + _theResult___fst_sfd__h831561 ; + assign a___1__h835771 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21 } ; - assign a___1__h836060 = 64'd0 - a__h835633 ; - assign a__h835633 = + assign a___1__h836057 = 64'd0 - a__h835630 ; + assign a__h835630 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h835774 : + a___1__h835771 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h239805 = - { {48{base__h239640[15]}}, base__h239640 } << + assign addBase__h239804 = + { {48{base__h239639[15]}}, base__h239639 } << coreFix_memExe_regToExeQ$first[264:259] ; - assign addBase__h240962 = - { {48{base__h240797[15]}}, base__h240797 } << + assign addBase__h240961 = + { {48{base__h240796[15]}}, base__h240796 } << coreFix_memExe_regToExeQ$first[101:96] ; - assign addBase__h254571 = - { {48{base__h254406[15]}}, base__h254406 } << + assign addBase__h254569 = + { {48{base__h254404[15]}}, base__h254404 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h239914 = - { {50{x__h240013[15]}}, x__h240013 } << + assign addTop__h239913 = + { {50{x__h240012[15]}}, x__h240012 } << coreFix_memExe_regToExeQ$first[264:259] ; - assign addTop__h241071 = - { {50{x__h241170[15]}}, x__h241170 } << + assign addTop__h241070 = + { {50{x__h241169[15]}}, x__h241169 } << coreFix_memExe_regToExeQ$first[101:96] ; - assign addTop__h254680 = - { {50{x__h254779[15]}}, x__h254779 } << + assign addTop__h254678 = + { {50{x__h254777[15]}}, x__h254777 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addr__h148408 = + assign addr__h148407 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0] ; - assign addr__h151984 = + assign addr__h151983 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h235261 = x__h235690[63:0] + csrf_ddc_reg[149:86] ; - assign addr__h987208 = + assign addr__h235260 = x__h235689[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h987203 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign address__h1008563 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h996900 = base__h996861 + { 57'd0, x__h997059 } ; - assign address__h996950 = base__h996915 + { 57'd0, x__h997059 } ; - assign address__h996966 = { 2'd0, address__h996900 } ; - assign address__h997310 = { 2'd0, base__h996861 } ; - assign address__h997623 = { 2'd0, address__h996950 } ; - assign address__h997967 = { 2'd0, base__h996915 } ; - assign b___1__h835775 = + assign address__h1008558 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h996895 = base__h996856 + { 57'd0, x__h997054 } ; + assign address__h996945 = base__h996910 + { 57'd0, x__h997054 } ; + assign address__h996961 = { 2'd0, address__h996895 } ; + assign address__h997305 = { 2'd0, base__h996856 } ; + assign address__h997618 = { 2'd0, address__h996945 } ; + assign address__h997962 = { 2'd0, base__h996910 } ; + assign b___1__h835772 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h836105 = 64'd0 - b__h835634 ; - assign b__h835634 = + assign b___1__h836102 = 64'd0 - b__h835631 ; + assign b__h835631 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h835775 : + b___1__h835772 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b_base__h127497 = + assign b_base__h127496 = { coreFix_memExe_respLrScAmoQ_data_0[77:67], ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign b_base__h140413 = + assign b_base__h140412 = { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h183674 = - { x__h183367[77:67], ~x__h183367[66], x__h183367[65:64] } ; - assign b_base__h202425 = - { x__h199219[77:67], ~x__h199219[66], x__h199219[65:64] } ; - assign b_base__h216991 = + assign b_base__h183673 = + { x__h183366[77:67], ~x__h183366[66], x__h183366[65:64] } ; + assign b_base__h202424 = + { x__h199218[77:67], ~x__h199218[66], x__h199218[65:64] } ; + assign b_base__h216990 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h865912 = + assign b_base__h865909 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h866460 = + assign b_base__h866457 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h904534 = + assign b_base__h904530 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h905082 = + assign b_base__h905078 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_base__h992608 = + assign b_base__h992603 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign b_top__h127496 = + assign b_top__h127495 = { coreFix_memExe_respLrScAmoQ_data_0[89:81], ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign b_top__h140412 = + assign b_top__h140411 = { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h183673 = - { x__h183367[89:81], ~x__h183367[80:79], x__h183367[78] } ; - assign b_top__h202424 = - { x__h199219[89:81], ~x__h199219[80:79], x__h199219[78] } ; - assign b_top__h216990 = + assign b_top__h183672 = + { x__h183366[89:81], ~x__h183366[80:79], x__h183366[78] } ; + assign b_top__h202423 = + { x__h199218[89:81], ~x__h199218[80:79], x__h199218[78] } ; + assign b_top__h216989 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h865911 = + assign b_top__h865908 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h866459 = + assign b_top__h866456 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h904533 = + assign b_top__h904529 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h905081 = + assign b_top__h905077 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign b_top__h992607 = + assign b_top__h992602 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign base__h239640 = + assign base__h239639 = { coreFix_memExe_regToExeQ$first[222:221], coreFix_memExe_regToExeQ$first[244:231] } ; - assign base__h240797 = + assign base__h240796 = { coreFix_memExe_regToExeQ$first[59:58], coreFix_memExe_regToExeQ$first[81:68] } ; - assign base__h254406 = + assign base__h254404 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h995046 = + assign base__h995041 = { (IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22432 == IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22434) ? 2'd0 : @@ -32393,31 +32393,31 @@ module mkCore(CLK, !IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22434) ? 2'd1 : 2'd3), - x__h992601 } ; - assign base__h996861 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h996915 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign carry_out__h127401 = - (topBits__h127399 < x__h127490[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h140317 = - (topBits__h140315 < x__h140406[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h183578 = - (topBits__h183576 < x__h183667[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h202329 = - (topBits__h202327 < x__h202418[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h216895 = - (topBits__h216893 < x__h216984[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h865815 = - (topBits__h865813 < x__h865905[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h866363 = - (topBits__h866361 < x__h866453[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h904437 = - (topBits__h904435 < x__h904527[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h904985 = - (topBits__h904983 < x__h905075[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h992512 = - (topBits__h992510 < x__h992601[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h994330 = { 1'd0, i__h992982 } ; - assign cause_interrupt__h992790 = + x__h992596 } ; + assign base__h996856 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h996910 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign carry_out__h127400 = + (topBits__h127398 < x__h127489[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h140316 = + (topBits__h140314 < x__h140405[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h183577 = + (topBits__h183575 < x__h183666[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h202328 = + (topBits__h202326 < x__h202417[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h216894 = + (topBits__h216892 < x__h216983[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h865812 = + (topBits__h865810 < x__h865902[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h866360 = + (topBits__h866358 < x__h866450[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h904433 = + (topBits__h904431 < x__h904523[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h904981 = + (topBits__h904979 < x__h905071[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h992507 = + (topBits__h992505 < x__h992596[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h994325 = { 1'd0, i__h992977 } ; + assign cause_interrupt__h992785 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22272 = @@ -32482,7 +32482,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19008, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19200, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h898430 : + repBound__h898426 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8202_BI_ETC___d19240 } ; assign coreFix_aluExe_0_dispToRegQ_first__8202_BIT_13_ETC___d18287 = @@ -32533,7 +32533,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16643, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17095, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h859420 : + repBound__h859417 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17161 } ; assign coreFix_aluExe_1_dispToRegQ_first__5590_BIT_13_ETC___d15675 = @@ -32638,9 +32638,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14980) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15021 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32648,9 +32648,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15016) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15069 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32658,9 +32658,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15064) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15111 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32668,9 +32668,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15106) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15153 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32678,9 +32678,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15148) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -32719,7 +32719,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h422493 ; + y__h422490 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5614 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -34899,12 +34899,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__239_BITS_334_TO__ETC___d4402 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64:63] - - { 1'd0, x__h254848 } > + { 1'd0, x__h254846 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h254681, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h254679, 14'd0 } + - addTop__h254680 ; + addTop__h254678 ; assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4539 = coreFix_memExe_dTlb$procResp[560:500] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4540 = @@ -34950,15 +34950,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3568 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4232 = - { coreFix_memExe_lsq$getOrigBE << pointer__h242569[3:0], - (highOffsetBits__h242578 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h242568[3:0], + (highOffsetBits__h242577 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__633_BI_ETC___d4077 || coreFix_memExe_regToExeQ$first[264:259] >= 6'd50) && coreFix_memExe_regToExeQ$first[383], - result_d_address__h242780, - x__h248052[13:0], + result_d_address__h242779, + x__h248050[13:0], coreFix_memExe_regToExeQ$first[302:231], - repBound__h248150, + repBound__h248148, coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092, coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105, @@ -34966,7 +34966,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__633_BITS_101_T_ETC___d3767 = coreFix_memExe_regToExeQ$first[101:96] < 6'd51 && coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64:63] - - { 1'd0, x__h241239 } > + { 1'd0, x__h241238 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__633_BITS_139_T_ETC___d4052 = { coreFix_memExe_regToExeQ$first[139:124], @@ -34979,26 +34979,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[2], IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[1:0], coreFix_memExe_regToExeQ$first[217:154] } << - x__h244610 ; + x__h244608 ; assign coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754 = - { coreFix_memExe_regToExeQ$first[219:168] & mask__h241072, + { coreFix_memExe_regToExeQ$first[219:168] & mask__h241071, 14'd0 } + - addTop__h241071 ; + addTop__h241070 ; assign coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093 = - coreFix_memExe_regToExeQ$first[244:242] < repBound__h248150 ; + coreFix_memExe_regToExeQ$first[244:242] < repBound__h248148 ; assign coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092 = - coreFix_memExe_regToExeQ$first[258:256] < repBound__h248150 ; + coreFix_memExe_regToExeQ$first[258:256] < repBound__h248148 ; assign coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705 = coreFix_memExe_regToExeQ$first[264:259] < 6'd51 && coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64:63] - - { 1'd0, x__h240082 } > + { 1'd0, x__h240081 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692 = - { coreFix_memExe_regToExeQ$first[382:331] & mask__h239915, + { coreFix_memExe_regToExeQ$first[382:331] & mask__h239914, 14'd0 } + - addTop__h239914 ; + addTop__h239913 ; assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095 = - x__h248052[13:11] < repBound__h248150 ; + x__h248050[13:11] < repBound__h248148 ; assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105 = { coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095, (coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092 == @@ -35039,44 +35039,44 @@ module mkCore(CLK, fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__2032_BITS_469_TO_4_ETC___d22805 ; - assign cr_addrBits__h865498 = + assign cr_addrBits__h865495 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h865674[13:0] : + x__h865671[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h866046 = + assign cr_addrBits__h866043 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h866222[13:0] : + x__h866219[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h904120 = + assign cr_addrBits__h904116 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h904296[13:0] : + x__h904292[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h904668 = + assign cr_addrBits__h904664 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h904844[13:0] : + x__h904840[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h865497 = + assign cr_address__h865494 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h866045 = + assign cr_address__h866042 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h904119 = + assign cr_address__h904115 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h904667 = + assign cr_address__h904663 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h865500 = coreFix_aluExe_1_regToExeQ$first[287] ; - assign cr_flags__h866048 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h904122 = coreFix_aluExe_0_regToExeQ$first[287] ; - assign cr_flags__h904670 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h865501 = coreFix_aluExe_1_regToExeQ$first[289:288] ; - assign cr_reserved__h866049 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h904123 = coreFix_aluExe_0_regToExeQ$first[289:288] ; - assign cr_reserved__h904671 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h865497 = coreFix_aluExe_1_regToExeQ$first[287] ; + assign cr_flags__h866045 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h904118 = coreFix_aluExe_0_regToExeQ$first[287] ; + assign cr_flags__h904666 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h865498 = coreFix_aluExe_1_regToExeQ$first[289:288] ; + assign cr_reserved__h866046 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h904119 = coreFix_aluExe_0_regToExeQ$first[289:288] ; + assign cr_reserved__h904667 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126 = - csrf_ddc_reg[13:11] < repBound__h248675 ; + csrf_ddc_reg[13:11] < repBound__h248673 ; assign csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125 = - csrf_ddc_reg[27:25] < repBound__h248675 ; + csrf_ddc_reg[27:25] < repBound__h248673 ; assign csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128 = - csrf_ddc_reg[85:83] < repBound__h248675 ; + csrf_ddc_reg[85:83] < repBound__h248673 ; assign csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 = { csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128, (csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125 == @@ -35133,13 +35133,13 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592 = - csrf_mtcc_reg[149:86] & mask__h997629 ; + csrf_mtcc_reg[149:86] & mask__h997624 ; assign csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22599 = - newAddrDiff__h997630 == mask__h997629 ; + newAddrDiff__h997625 == mask__h997624 ; assign csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22632 = - newAddrDiff__h997974 == mask__h997629 ; + newAddrDiff__h997969 == mask__h997624 ; assign csrf_mtcc_reg_read__6627_BITS_85_TO_83_2607_UL_ETC___d22610 = - csrf_mtcc_reg[85:83] < repBound__h997781 ; + csrf_mtcc_reg[85:83] < repBound__h997776 ; assign csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 = csrf_prv_reg_read__0079_ULE_1___d22385 && ((commitStage_commitTrap[44:43] == 2'd1) ? @@ -35148,50 +35148,50 @@ module mkCore(CLK, _0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22415) ; assign csrf_prv_reg_read__0079_ULE_1___d22385 = csrf_prv_reg <= 2'd1 ; assign csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515 = - csrf_stcc_reg[149:86] & mask__h996972 ; + csrf_stcc_reg[149:86] & mask__h996967 ; assign csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22524 = - newAddrDiff__h996973 == mask__h996972 ; + newAddrDiff__h996968 == mask__h996967 ; assign csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22557 = - newAddrDiff__h997317 == mask__h996972 ; + newAddrDiff__h997312 == mask__h996967 ; assign csrf_stcc_reg_read__6618_BITS_85_TO_83_2532_UL_ETC___d22535 = - csrf_stcc_reg[85:83] < repBound__h997124 ; - assign data05760_BITS_31_TO_0__q25 = data__h705760[31:0] ; - assign data___1__h705460 = + csrf_stcc_reg[85:83] < repBound__h997119 ; + assign data05757_BITS_31_TO_0__q25 = data__h705757[31:0] ; + assign data___1__h705457 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144 } ; - assign data___1__h706320 = - { {32{data05760_BITS_31_TO_0__q25[31]}}, - data05760_BITS_31_TO_0__q25 } ; - assign data__h567607 = + assign data___1__h706317 = + { {32{data05757_BITS_31_TO_0__q25[31]}}, + data05757_BITS_31_TO_0__q25 } ; + assign data__h567604 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h568170 : - res_data__h568165 ; - assign data__h613367 = + res_data__h568167 : + res_data__h568162 ; + assign data__h613364 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h613924 : - res_data__h613919 ; - assign data__h659114 = + res_data__h613921 : + res_data__h613916 ; + assign data__h659111 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h659671 : - res_data__h659666 ; - assign data__h704928 = + res_data__h659668 : + res_data__h659663 ; + assign data__h704925 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h705460 : + data___1__h705457 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12190 ; - assign data__h705760 = + assign data__h705757 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h705674 : - x_remainder__h705675 ; - assign data__h705791 = + x_quotient__h705671 : + x_remainder__h705672 ; + assign data__h705788 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h706320 : - data__h705760 ; - assign data_addrBits__h1013599 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1014453 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1013598 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1014452 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h991836 = + data___1__h706317 : + data__h705757 ; + assign data_addrBits__h1013593 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1014447 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1013592 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1014446 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h991831 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -35210,59 +35210,59 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h611525 = _theResult___fst_exp__h584492 + 8'd1 ; - assign din_inc___2_exp__h611549 = _theResult___fst_exp__h593148 + 8'd1 ; - assign din_inc___2_exp__h611579 = _theResult___fst_exp__h602258 + 8'd1 ; - assign din_inc___2_exp__h611603 = _theResult___fst_exp__h610943 + 8'd1 ; - assign din_inc___2_exp__h657274 = _theResult___fst_exp__h630241 + 8'd1 ; - assign din_inc___2_exp__h657298 = _theResult___fst_exp__h638897 + 8'd1 ; - assign din_inc___2_exp__h657328 = _theResult___fst_exp__h648007 + 8'd1 ; - assign din_inc___2_exp__h657352 = _theResult___fst_exp__h656692 + 8'd1 ; - assign din_inc___2_exp__h703021 = _theResult___fst_exp__h675988 + 8'd1 ; - assign din_inc___2_exp__h703045 = _theResult___fst_exp__h684644 + 8'd1 ; - assign din_inc___2_exp__h703075 = _theResult___fst_exp__h693754 + 8'd1 ; - assign din_inc___2_exp__h703099 = _theResult___fst_exp__h702439 + 8'd1 ; - assign din_inc___2_exp__h753463 = _theResult___fst_exp__h734213 + 11'd1 ; - assign din_inc___2_exp__h753498 = _theResult___fst_exp__h743790 + 11'd1 ; - assign din_inc___2_exp__h753524 = _theResult___fst_exp__h752623 + 11'd1 ; - assign din_inc___2_exp__h792316 = _theResult___fst_exp__h773066 + 11'd1 ; - assign din_inc___2_exp__h792351 = _theResult___fst_exp__h782643 + 11'd1 ; - assign din_inc___2_exp__h792377 = _theResult___fst_exp__h791476 + 11'd1 ; - assign din_inc___2_exp__h831620 = _theResult___fst_exp__h812370 + 11'd1 ; - assign din_inc___2_exp__h831655 = _theResult___fst_exp__h821947 + 11'd1 ; - assign din_inc___2_exp__h831681 = _theResult___fst_exp__h830780 + 11'd1 ; - assign enabled_ints___1__h918520 = pend_ints__h917993 & y__h918532 ; - assign enabled_ints__h918566 = - pend_ints__h917993 & - { r1__read_BITS_13_TO_0___h918542, csrf_mideleg_1_0_reg } ; - assign f1_exp14825_MINUS_127__q147 = f1_exp__h714825 - 8'd127 ; - assign f1_exp__h714825 = + assign din_inc___2_exp__h611522 = _theResult___fst_exp__h584489 + 8'd1 ; + assign din_inc___2_exp__h611546 = _theResult___fst_exp__h593145 + 8'd1 ; + assign din_inc___2_exp__h611576 = _theResult___fst_exp__h602255 + 8'd1 ; + assign din_inc___2_exp__h611600 = _theResult___fst_exp__h610940 + 8'd1 ; + assign din_inc___2_exp__h657271 = _theResult___fst_exp__h630238 + 8'd1 ; + assign din_inc___2_exp__h657295 = _theResult___fst_exp__h638894 + 8'd1 ; + assign din_inc___2_exp__h657325 = _theResult___fst_exp__h648004 + 8'd1 ; + assign din_inc___2_exp__h657349 = _theResult___fst_exp__h656689 + 8'd1 ; + assign din_inc___2_exp__h703018 = _theResult___fst_exp__h675985 + 8'd1 ; + assign din_inc___2_exp__h703042 = _theResult___fst_exp__h684641 + 8'd1 ; + assign din_inc___2_exp__h703072 = _theResult___fst_exp__h693751 + 8'd1 ; + assign din_inc___2_exp__h703096 = _theResult___fst_exp__h702436 + 8'd1 ; + assign din_inc___2_exp__h753460 = _theResult___fst_exp__h734210 + 11'd1 ; + assign din_inc___2_exp__h753495 = _theResult___fst_exp__h743787 + 11'd1 ; + assign din_inc___2_exp__h753521 = _theResult___fst_exp__h752620 + 11'd1 ; + assign din_inc___2_exp__h792313 = _theResult___fst_exp__h773063 + 11'd1 ; + assign din_inc___2_exp__h792348 = _theResult___fst_exp__h782640 + 11'd1 ; + assign din_inc___2_exp__h792374 = _theResult___fst_exp__h791473 + 11'd1 ; + assign din_inc___2_exp__h831617 = _theResult___fst_exp__h812367 + 11'd1 ; + assign din_inc___2_exp__h831652 = _theResult___fst_exp__h821944 + 11'd1 ; + assign din_inc___2_exp__h831678 = _theResult___fst_exp__h830777 + 11'd1 ; + assign enabled_ints___1__h918515 = pend_ints__h917988 & y__h918527 ; + assign enabled_ints__h918561 = + pend_ints__h917988 & + { r1__read_BITS_13_TO_0___h918537, csrf_mideleg_1_0_reg } ; + assign f1_exp14822_MINUS_127__q147 = f1_exp__h714822 - 8'd127 ; + assign f1_exp__h714822 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h714826 = + assign f1_sfd__h714823 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp53819_MINUS_127__q187 = f2_exp__h753819 - 8'd127 ; - assign f2_exp__h753819 = + assign f2_exp53816_MINUS_127__q187 = f2_exp__h753816 - 8'd127 ; + assign f2_exp__h753816 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h753820 = + assign f2_sfd__h753817 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp93123_MINUS_127__q164 = f3_exp__h793123 - 8'd127 ; - assign f3_exp__h793123 = + assign f3_exp93120_MINUS_127__q164 = f3_exp__h793120 - 8'd127 ; + assign f3_exp__h793120 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h793124 = + assign f3_sfd__h793121 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; @@ -35272,7 +35272,7 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h849072 = { 56'd0, x__h852690 } ; + assign fcsr_csr__read__h849069 = { 56'd0, x__h852687 } ; assign fetchStage_RDY_pipelines_0_first__0046_AND_fet_ETC___d21036 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[267:265] == 3'd1 && @@ -35546,83 +35546,83 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0058_BIT_180_122_ETC___d21324 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q258 } ; - assign fflags__h1011197 = + assign fflags__h1011192 = NOT_rob_deqPort_0_canDeq__3171_3172_OR_rob_deq_ETC___d23391 ? - y_avValue_snd_fst__h1011257 : + y_avValue_snd_fst__h1011252 : IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 ; - assign fflags_csr__read__h849047 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h849058 = { 61'd0, csrf_frm_reg } ; - assign guard__h576391 = - { IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40[1], - { sfdin__h584486[32:0], 23'd0 } != 56'd0 } ; - assign guard__h585100 = - { IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42[1], - { _theResult___snd__h593099[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594030 = - { IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50[1], - { sfdin__h602252[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594628 = x__h594730 != 57'd0 ; - assign guard__h602866 = - { IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55[1], - { _theResult___snd__h610889[32:0], 23'd0 } != 56'd0 } ; - assign guard__h622142 = - { IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75[1], - { sfdin__h630235[32:0], 23'd0 } != 56'd0 } ; - assign guard__h630849 = - { IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77[1], - { _theResult___snd__h638848[32:0], 23'd0 } != 56'd0 } ; - assign guard__h639779 = - { IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85[1], - { sfdin__h648001[32:0], 23'd0 } != 56'd0 } ; - assign guard__h640377 = x__h640479 != 57'd0 ; - assign guard__h648615 = - { IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90[1], - { _theResult___snd__h656638[32:0], 23'd0 } != 56'd0 } ; - assign guard__h667889 = - { IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110[1], - { sfdin__h675982[32:0], 23'd0 } != 56'd0 } ; - assign guard__h676596 = - { IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112[1], - { _theResult___snd__h684595[32:0], 23'd0 } != 56'd0 } ; - assign guard__h685526 = - { IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120[1], - { sfdin__h693748[32:0], 23'd0 } != 56'd0 } ; - assign guard__h686124 = x__h686226 != 57'd0 ; - assign guard__h694362 = - { IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125[1], - { _theResult___snd__h702385[32:0], 23'd0 } != 56'd0 } ; - assign guard__h726252 = - { IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146[1], - { _theResult___snd__h734164[3:0], 52'd0 } != 56'd0 } ; - assign guard__h735564 = - { IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150[1], - { sfdin__h743784[3:0], 52'd0 } != 56'd0 } ; - assign guard__h736162 = x__h736262 != 57'd0 ; - assign guard__h744633 = - { IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153[1], - { _theResult___snd__h752569[3:0], 52'd0 } != 56'd0 } ; - assign guard__h765105 = - { IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186[1], - { _theResult___snd__h773017[3:0], 52'd0 } != 56'd0 } ; - assign guard__h774417 = - { IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190[1], - { sfdin__h782637[3:0], 52'd0 } != 56'd0 } ; - assign guard__h775015 = x__h775115 != 57'd0 ; - assign guard__h783486 = - { IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193[1], - { _theResult___snd__h791422[3:0], 52'd0 } != 56'd0 } ; - assign guard__h804409 = - { IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163[1], - { _theResult___snd__h812321[3:0], 52'd0 } != 56'd0 } ; - assign guard__h813721 = - { IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167[1], - { sfdin__h821941[3:0], 52'd0 } != 56'd0 } ; - assign guard__h814319 = x__h814419 != 57'd0 ; - assign guard__h822790 = - { IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170[1], - { _theResult___snd__h830726[3:0], 52'd0 } != 56'd0 } ; - assign highOffsetBits__h242578 = x__h242605 & mask__h239806 ; - assign idx__h966426 = + assign fflags_csr__read__h849044 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h849055 = { 61'd0, csrf_frm_reg } ; + assign guard__h576388 = + { IF_sfdin84483_BIT_33_THEN_2_ELSE_0__q40[1], + { sfdin__h584483[32:0], 23'd0 } != 56'd0 } ; + assign guard__h585097 = + { IF_theResult___snd93096_BIT_33_THEN_2_ELSE_0__q42[1], + { _theResult___snd__h593096[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594027 = + { IF_sfdin02249_BIT_33_THEN_2_ELSE_0__q50[1], + { sfdin__h602249[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594625 = x__h594727 != 57'd0 ; + assign guard__h602863 = + { IF_theResult___snd10886_BIT_33_THEN_2_ELSE_0__q55[1], + { _theResult___snd__h610886[32:0], 23'd0 } != 56'd0 } ; + assign guard__h622139 = + { IF_sfdin30232_BIT_33_THEN_2_ELSE_0__q75[1], + { sfdin__h630232[32:0], 23'd0 } != 56'd0 } ; + assign guard__h630846 = + { IF_theResult___snd38845_BIT_33_THEN_2_ELSE_0__q77[1], + { _theResult___snd__h638845[32:0], 23'd0 } != 56'd0 } ; + assign guard__h639776 = + { IF_sfdin47998_BIT_33_THEN_2_ELSE_0__q85[1], + { sfdin__h647998[32:0], 23'd0 } != 56'd0 } ; + assign guard__h640374 = x__h640476 != 57'd0 ; + assign guard__h648612 = + { IF_theResult___snd56635_BIT_33_THEN_2_ELSE_0__q90[1], + { _theResult___snd__h656635[32:0], 23'd0 } != 56'd0 } ; + assign guard__h667886 = + { IF_sfdin75979_BIT_33_THEN_2_ELSE_0__q110[1], + { sfdin__h675979[32:0], 23'd0 } != 56'd0 } ; + assign guard__h676593 = + { IF_theResult___snd84592_BIT_33_THEN_2_ELSE_0__q112[1], + { _theResult___snd__h684592[32:0], 23'd0 } != 56'd0 } ; + assign guard__h685523 = + { IF_sfdin93745_BIT_33_THEN_2_ELSE_0__q120[1], + { sfdin__h693745[32:0], 23'd0 } != 56'd0 } ; + assign guard__h686121 = x__h686223 != 57'd0 ; + assign guard__h694359 = + { IF_theResult___snd02382_BIT_33_THEN_2_ELSE_0__q125[1], + { _theResult___snd__h702382[32:0], 23'd0 } != 56'd0 } ; + assign guard__h726249 = + { IF_theResult___snd34161_BIT_4_THEN_2_ELSE_0__q146[1], + { _theResult___snd__h734161[3:0], 52'd0 } != 56'd0 } ; + assign guard__h735561 = + { IF_sfdin43781_BIT_4_THEN_2_ELSE_0__q150[1], + { sfdin__h743781[3:0], 52'd0 } != 56'd0 } ; + assign guard__h736159 = x__h736259 != 57'd0 ; + assign guard__h744630 = + { IF_theResult___snd52566_BIT_4_THEN_2_ELSE_0__q153[1], + { _theResult___snd__h752566[3:0], 52'd0 } != 56'd0 } ; + assign guard__h765102 = + { IF_theResult___snd73014_BIT_4_THEN_2_ELSE_0__q186[1], + { _theResult___snd__h773014[3:0], 52'd0 } != 56'd0 } ; + assign guard__h774414 = + { IF_sfdin82634_BIT_4_THEN_2_ELSE_0__q190[1], + { sfdin__h782634[3:0], 52'd0 } != 56'd0 } ; + assign guard__h775012 = x__h775112 != 57'd0 ; + assign guard__h783483 = + { IF_theResult___snd91419_BIT_4_THEN_2_ELSE_0__q193[1], + { _theResult___snd__h791419[3:0], 52'd0 } != 56'd0 } ; + assign guard__h804406 = + { IF_theResult___snd12318_BIT_4_THEN_2_ELSE_0__q163[1], + { _theResult___snd__h812318[3:0], 52'd0 } != 56'd0 } ; + assign guard__h813718 = + { IF_sfdin21938_BIT_4_THEN_2_ELSE_0__q167[1], + { sfdin__h821938[3:0], 52'd0 } != 56'd0 } ; + assign guard__h814316 = x__h814416 != 57'd0 ; + assign guard__h822787 = + { IF_theResult___snd30723_BIT_4_THEN_2_ELSE_0__q170[1], + { _theResult___snd__h830723[3:0], 52'd0 } != 56'd0 } ; + assign highOffsetBits__h242577 = x__h242604 & mask__h239805 ; + assign idx__h966421 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21423 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -35630,82 +35630,82 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0049_BITS_267_TO_ETC___d21446) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__0978__ETC___d20980 ; - assign impliedTopBits__h127403 = x__h127487 + len_correction__h127402 ; - assign impliedTopBits__h140319 = x__h140403 + len_correction__h140318 ; - assign impliedTopBits__h183580 = x__h183664 + len_correction__h183579 ; - assign impliedTopBits__h202331 = x__h202415 + len_correction__h202330 ; - assign impliedTopBits__h216897 = x__h216981 + len_correction__h216896 ; - assign impliedTopBits__h865817 = x__h865902 + len_correction__h865816 ; - assign impliedTopBits__h866365 = x__h866450 + len_correction__h866364 ; - assign impliedTopBits__h904439 = x__h904524 + len_correction__h904438 ; - assign impliedTopBits__h904987 = x__h905072 + len_correction__h904986 ; - assign impliedTopBits__h992514 = x__h992598 + len_correction__h992513 ; - assign in__h239745 = coreFix_memExe_regToExeQ$first[382:317] & y__h239762 ; - assign in__h240902 = coreFix_memExe_regToExeQ$first[219:154] & y__h240919 ; - assign in__h254511 = coreFix_memExe_dTlb$procResp[452:387] & y__h254528 ; - assign in__h995128 = pc_address__h992211 & y__h995145 ; - assign k__h942684 = + assign impliedTopBits__h127402 = x__h127486 + len_correction__h127401 ; + assign impliedTopBits__h140318 = x__h140402 + len_correction__h140317 ; + assign impliedTopBits__h183579 = x__h183663 + len_correction__h183578 ; + assign impliedTopBits__h202330 = x__h202414 + len_correction__h202329 ; + assign impliedTopBits__h216896 = x__h216980 + len_correction__h216895 ; + assign impliedTopBits__h865814 = x__h865899 + len_correction__h865813 ; + assign impliedTopBits__h866362 = x__h866447 + len_correction__h866361 ; + assign impliedTopBits__h904435 = x__h904520 + len_correction__h904434 ; + assign impliedTopBits__h904983 = x__h905068 + len_correction__h904982 ; + assign impliedTopBits__h992509 = x__h992593 + len_correction__h992508 ; + assign in__h239744 = coreFix_memExe_regToExeQ$first[382:317] & y__h239761 ; + assign in__h240901 = coreFix_memExe_regToExeQ$first[219:154] & y__h240918 ; + assign in__h254509 = coreFix_memExe_dTlb$procResp[452:387] & y__h254526 ; + assign in__h995123 = pc_address__h992206 & y__h995140 ; + assign k__h942679 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__0978__ETC___d20980 ; - assign len_correction__h127402 = + assign len_correction__h127401 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? 2'b01 : 2'b0 ; - assign len_correction__h140318 = + assign len_correction__h140317 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h183579 = - INV_x83367_BITS_108_TO_90__q33[0] ? 2'b01 : 2'b0 ; - assign len_correction__h202330 = - INV_x99219_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; - assign len_correction__h216896 = + assign len_correction__h183578 = + INV_x83366_BITS_108_TO_90__q33[0] ? 2'b01 : 2'b0 ; + assign len_correction__h202329 = + INV_x99218_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; + assign len_correction__h216895 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h865816 = + assign len_correction__h865813 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h866364 = + assign len_correction__h866361 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h904438 = + assign len_correction__h904434 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h904986 = + assign len_correction__h904982 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign len_correction__h992513 = + assign len_correction__h992508 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? 2'b01 : 2'b0 ; - assign mask__h239806 = + assign mask__h239805 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign mask__h239915 = + assign mask__h239914 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign mask__h240963 = + assign mask__h240962 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign mask__h241072 = + assign mask__h241071 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign mask__h254572 = + assign mask__h254570 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h254681 = + assign mask__h254679 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h996972 = 64'hFFFFFFFFFFFFFFFF << x__h997033 ; - assign mask__h997629 = 64'hFFFFFFFFFFFFFFFF << x__h997690 ; - assign mcause_csr__read__h850488 = - { r1__read__h854142, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h850309 = - { r1__read__h854130, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h849989 = - { r1__read__h853996, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h850087 = - { r1__read__h854013, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h850214 = { r1__read__h854037, 1'b0 } ; - assign mip_csr__read__h850727 = { r1__read__h854149, 1'b0 } ; + assign mask__h996967 = 64'hFFFFFFFFFFFFFFFF << x__h997028 ; + assign mask__h997624 = 64'hFFFFFFFFFFFFFFFF << x__h997685 ; + assign mcause_csr__read__h850485 = + { r1__read__h854139, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h850306 = + { r1__read__h854127, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h849986 = + { r1__read__h853993, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h850084 = + { r1__read__h854010, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h850211 = { r1__read__h854034, 1'b0 } ; + assign mip_csr__read__h850724 = { r1__read__h854146, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20461 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -35747,28 +35747,28 @@ module mkCore(CLK, fetchStage$pipelines_0_first[272:268] != 5'd24 && fetchStage$pipelines_0_first[272:268] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h849835 = { r1__read__h853871, csrf_ie_vec_0 } ; - assign n__read__h1008993 = + assign mstatus_csr__read__h849832 = { r1__read__h853868, csrf_ie_vec_0 } ; + assign n__read__h1008988 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1009069 : + upd__h1009064 : csrf_minstret_ehr_data_rl ; assign n__read__h7877 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7946 : csrf_mcycle_ehr_data_rl ; - assign newAddrDiff__h996973 = + assign newAddrDiff__h996968 = csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515 - - (address__h996900 & mask__h996972) ; - assign newAddrDiff__h997317 = + (address__h996895 & mask__h996967) ; + assign newAddrDiff__h997312 = csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515 - - (base__h996861 & mask__h996972) ; - assign newAddrDiff__h997630 = + (base__h996856 & mask__h996967) ; + assign newAddrDiff__h997625 = csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592 - - (address__h996950 & mask__h997629) ; - assign newAddrDiff__h997974 = + (address__h996945 & mask__h997624) ; + assign newAddrDiff__h997969 = csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592 - - (base__h996915 & mask__h997629) ; - assign new_pc__h871752 = + (base__h996910 & mask__h997624) ; + assign new_pc__h871748 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -35780,7 +35780,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17826[2], IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17826[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h909836 = + assign new_pc__h909831 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -35792,266 +35792,266 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19904[2], IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19904[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h515541 = + assign next_deqP___1__h515537 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h526318 = + assign next_deqP___1__h526314 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h533596 = + assign next_deqP___1__h533592 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h544231 = + assign next_deqP___1__h544227 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h557879 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h561658 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1007609 = + assign next_deqP___1__h557875 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h561654 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1007604 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1008563 } ; - assign offset__h239641 = + { rob$deqPort_0_deq_data[630:566], address__h1008558 } ; + assign offset__h239640 = { 2'd0, coreFix_memExe_regToExeQ$first[316:303] } - - base__h239640 ; - assign offset__h240798 = + base__h239639 ; + assign offset__h240797 = { 2'd0, coreFix_memExe_regToExeQ$first[153:140] } - - base__h240797 ; - assign offset__h242559 = + base__h240796 ; + assign offset__h242558 = { {32{coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16[31]}}, coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16 } ; - assign offset__h254407 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254406 ; - assign offset__h995047 = { 2'd0, pc_addrBits__h992212 } - base__h995046 ; - assign out___1_sfd__h714889 = { f1_sfd__h714826, 29'd0 } ; - assign out___1_sfd__h753883 = { f2_sfd__h753820, 29'd0 } ; - assign out___1_sfd__h793187 = { f3_sfd__h793124, 29'd0 } ; - assign out_exp__h585011 = - sfdin__h584486[34] ? - _theResult___exp__h585008 : - _theResult___fst_exp__h584492 ; - assign out_exp__h593593 = - _theResult___snd__h593099[34] ? - _theResult___exp__h593590 : - _theResult___fst_exp__h593148 ; - assign out_exp__h602777 = - sfdin__h602252[34] ? - _theResult___exp__h602774 : - _theResult___fst_exp__h602258 ; - assign out_exp__h611413 = - _theResult___snd__h610889[34] ? - _theResult___exp__h611410 : - _theResult___fst_exp__h610943 ; - assign out_exp__h630760 = - sfdin__h630235[34] ? - _theResult___exp__h630757 : - _theResult___fst_exp__h630241 ; - assign out_exp__h639342 = - _theResult___snd__h638848[34] ? - _theResult___exp__h639339 : - _theResult___fst_exp__h638897 ; - assign out_exp__h648526 = - sfdin__h648001[34] ? - _theResult___exp__h648523 : - _theResult___fst_exp__h648007 ; - assign out_exp__h657162 = - _theResult___snd__h656638[34] ? - _theResult___exp__h657159 : - _theResult___fst_exp__h656692 ; - assign out_exp__h676507 = - sfdin__h675982[34] ? - _theResult___exp__h676504 : - _theResult___fst_exp__h675988 ; - assign out_exp__h685089 = - _theResult___snd__h684595[34] ? - _theResult___exp__h685086 : - _theResult___fst_exp__h684644 ; - assign out_exp__h694273 = - sfdin__h693748[34] ? - _theResult___exp__h694270 : - _theResult___fst_exp__h693754 ; - assign out_exp__h702909 = - _theResult___snd__h702385[34] ? - _theResult___exp__h702906 : - _theResult___fst_exp__h702439 ; - assign out_exp__h734871 = - _theResult___snd__h734164[5] ? - _theResult___exp__h734868 : - _theResult___fst_exp__h734213 ; - assign out_exp__h744522 = - sfdin__h743784[5] ? - _theResult___exp__h744519 : - _theResult___fst_exp__h743790 ; - assign out_exp__h753306 = - _theResult___snd__h752569[5] ? - _theResult___exp__h753303 : - _theResult___fst_exp__h752623 ; - assign out_exp__h773724 = - _theResult___snd__h773017[5] ? - _theResult___exp__h773721 : - _theResult___fst_exp__h773066 ; - assign out_exp__h783375 = - sfdin__h782637[5] ? - _theResult___exp__h783372 : - _theResult___fst_exp__h782643 ; - assign out_exp__h792159 = - _theResult___snd__h791422[5] ? - _theResult___exp__h792156 : - _theResult___fst_exp__h791476 ; - assign out_exp__h813028 = - _theResult___snd__h812321[5] ? - _theResult___exp__h813025 : - _theResult___fst_exp__h812370 ; - assign out_exp__h822679 = - sfdin__h821941[5] ? - _theResult___exp__h822676 : - _theResult___fst_exp__h821947 ; - assign out_exp__h831463 = - _theResult___snd__h830726[5] ? - _theResult___exp__h831460 : - _theResult___fst_exp__h830780 ; - assign out_f_exp__h611789 = - (_theResult___exp__h611512 == 8'd255 && - _theResult___sfd__h611513 != 23'd0 || + assign offset__h254405 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254404 ; + assign offset__h995042 = { 2'd0, pc_addrBits__h992207 } - base__h995041 ; + assign out___1_sfd__h714886 = { f1_sfd__h714823, 29'd0 } ; + assign out___1_sfd__h753880 = { f2_sfd__h753817, 29'd0 } ; + assign out___1_sfd__h793184 = { f3_sfd__h793121, 29'd0 } ; + assign out_exp__h585008 = + sfdin__h584483[34] ? + _theResult___exp__h585005 : + _theResult___fst_exp__h584489 ; + assign out_exp__h593590 = + _theResult___snd__h593096[34] ? + _theResult___exp__h593587 : + _theResult___fst_exp__h593145 ; + assign out_exp__h602774 = + sfdin__h602249[34] ? + _theResult___exp__h602771 : + _theResult___fst_exp__h602255 ; + assign out_exp__h611410 = + _theResult___snd__h610886[34] ? + _theResult___exp__h611407 : + _theResult___fst_exp__h610940 ; + assign out_exp__h630757 = + sfdin__h630232[34] ? + _theResult___exp__h630754 : + _theResult___fst_exp__h630238 ; + assign out_exp__h639339 = + _theResult___snd__h638845[34] ? + _theResult___exp__h639336 : + _theResult___fst_exp__h638894 ; + assign out_exp__h648523 = + sfdin__h647998[34] ? + _theResult___exp__h648520 : + _theResult___fst_exp__h648004 ; + assign out_exp__h657159 = + _theResult___snd__h656635[34] ? + _theResult___exp__h657156 : + _theResult___fst_exp__h656689 ; + assign out_exp__h676504 = + sfdin__h675979[34] ? + _theResult___exp__h676501 : + _theResult___fst_exp__h675985 ; + assign out_exp__h685086 = + _theResult___snd__h684592[34] ? + _theResult___exp__h685083 : + _theResult___fst_exp__h684641 ; + assign out_exp__h694270 = + sfdin__h693745[34] ? + _theResult___exp__h694267 : + _theResult___fst_exp__h693751 ; + assign out_exp__h702906 = + _theResult___snd__h702382[34] ? + _theResult___exp__h702903 : + _theResult___fst_exp__h702436 ; + assign out_exp__h734868 = + _theResult___snd__h734161[5] ? + _theResult___exp__h734865 : + _theResult___fst_exp__h734210 ; + assign out_exp__h744519 = + sfdin__h743781[5] ? + _theResult___exp__h744516 : + _theResult___fst_exp__h743787 ; + assign out_exp__h753303 = + _theResult___snd__h752566[5] ? + _theResult___exp__h753300 : + _theResult___fst_exp__h752620 ; + assign out_exp__h773721 = + _theResult___snd__h773014[5] ? + _theResult___exp__h773718 : + _theResult___fst_exp__h773063 ; + assign out_exp__h783372 = + sfdin__h782634[5] ? + _theResult___exp__h783369 : + _theResult___fst_exp__h782640 ; + assign out_exp__h792156 = + _theResult___snd__h791419[5] ? + _theResult___exp__h792153 : + _theResult___fst_exp__h791473 ; + assign out_exp__h813025 = + _theResult___snd__h812318[5] ? + _theResult___exp__h813022 : + _theResult___fst_exp__h812367 ; + assign out_exp__h822676 = + sfdin__h821938[5] ? + _theResult___exp__h822673 : + _theResult___fst_exp__h821944 ; + assign out_exp__h831460 = + _theResult___snd__h830723[5] ? + _theResult___exp__h831457 : + _theResult___fst_exp__h830777 ; + assign out_f_exp__h611786 = + (_theResult___exp__h611509 == 8'd255 && + _theResult___sfd__h611510 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611503 ; - assign out_f_exp__h657538 = - (_theResult___exp__h657261 == 8'd255 && - _theResult___sfd__h657262 != 23'd0 || + _theResult___fst_exp__h611500 ; + assign out_f_exp__h657535 = + (_theResult___exp__h657258 == 8'd255 && + _theResult___sfd__h657259 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657252 ; - assign out_f_exp__h703285 = - (_theResult___exp__h703008 == 8'd255 && - _theResult___sfd__h703009 != 23'd0 || + _theResult___fst_exp__h657249 ; + assign out_f_exp__h703282 = + (_theResult___exp__h703005 == 8'd255 && + _theResult___sfd__h703006 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h702999 ; - assign out_f_sfd__h611790 = - (_theResult___exp__h611512 == 8'd255 && - _theResult___sfd__h611513 != 23'd0) ? + _theResult___fst_exp__h702996 ; + assign out_f_sfd__h611787 = + (_theResult___exp__h611509 == 8'd255 && + _theResult___sfd__h611510 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h611513 ; - assign out_f_sfd__h657539 = - (_theResult___exp__h657261 == 8'd255 && - _theResult___sfd__h657262 != 23'd0) ? + _theResult___sfd__h611510 ; + assign out_f_sfd__h657536 = + (_theResult___exp__h657258 == 8'd255 && + _theResult___sfd__h657259 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h657262 ; - assign out_f_sfd__h703286 = - (_theResult___exp__h703008 == 8'd255 && - _theResult___sfd__h703009 != 23'd0) ? + _theResult___sfd__h657259 ; + assign out_f_sfd__h703283 = + (_theResult___exp__h703005 == 8'd255 && + _theResult___sfd__h703006 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h703009 ; - assign out_sfd__h585012 = - sfdin__h584486[34] ? - _theResult___sfd__h585009 : - sfdin__h584486[56:34] ; - assign out_sfd__h593594 = - _theResult___snd__h593099[34] ? - _theResult___sfd__h593591 : - _theResult___snd__h593099[56:34] ; - assign out_sfd__h602778 = - sfdin__h602252[34] ? - _theResult___sfd__h602775 : - sfdin__h602252[56:34] ; - assign out_sfd__h611414 = - _theResult___snd__h610889[34] ? - _theResult___sfd__h611411 : - _theResult___snd__h610889[56:34] ; - assign out_sfd__h630761 = - sfdin__h630235[34] ? - _theResult___sfd__h630758 : - sfdin__h630235[56:34] ; - assign out_sfd__h639343 = - _theResult___snd__h638848[34] ? - _theResult___sfd__h639340 : - _theResult___snd__h638848[56:34] ; - assign out_sfd__h648527 = - sfdin__h648001[34] ? - _theResult___sfd__h648524 : - sfdin__h648001[56:34] ; - assign out_sfd__h657163 = - _theResult___snd__h656638[34] ? - _theResult___sfd__h657160 : - _theResult___snd__h656638[56:34] ; - assign out_sfd__h676508 = - sfdin__h675982[34] ? - _theResult___sfd__h676505 : - sfdin__h675982[56:34] ; - assign out_sfd__h685090 = - _theResult___snd__h684595[34] ? - _theResult___sfd__h685087 : - _theResult___snd__h684595[56:34] ; - assign out_sfd__h694274 = - sfdin__h693748[34] ? - _theResult___sfd__h694271 : - sfdin__h693748[56:34] ; - assign out_sfd__h702910 = - _theResult___snd__h702385[34] ? - _theResult___sfd__h702907 : - _theResult___snd__h702385[56:34] ; - assign out_sfd__h734872 = - _theResult___snd__h734164[5] ? - _theResult___sfd__h734869 : - _theResult___snd__h734164[56:5] ; - assign out_sfd__h744523 = - sfdin__h743784[5] ? - _theResult___sfd__h744520 : - sfdin__h743784[56:5] ; - assign out_sfd__h753307 = - _theResult___snd__h752569[5] ? - _theResult___sfd__h753304 : - _theResult___snd__h752569[56:5] ; - assign out_sfd__h773725 = - _theResult___snd__h773017[5] ? - _theResult___sfd__h773722 : - _theResult___snd__h773017[56:5] ; - assign out_sfd__h783376 = - sfdin__h782637[5] ? - _theResult___sfd__h783373 : - sfdin__h782637[56:5] ; - assign out_sfd__h792160 = - _theResult___snd__h791422[5] ? - _theResult___sfd__h792157 : - _theResult___snd__h791422[56:5] ; - assign out_sfd__h813029 = - _theResult___snd__h812321[5] ? - _theResult___sfd__h813026 : - _theResult___snd__h812321[56:5] ; - assign out_sfd__h822680 = - sfdin__h821941[5] ? - _theResult___sfd__h822677 : - sfdin__h821941[56:5] ; - assign out_sfd__h831464 = - _theResult___snd__h830726[5] ? - _theResult___sfd__h831461 : - _theResult___snd__h830726[56:5] ; - assign pc__h960829 = fetchStage$pipelines_1_first[590:462] ; - assign pc_addrBits__h992212 = + _theResult___sfd__h703006 ; + assign out_sfd__h585009 = + sfdin__h584483[34] ? + _theResult___sfd__h585006 : + sfdin__h584483[56:34] ; + assign out_sfd__h593591 = + _theResult___snd__h593096[34] ? + _theResult___sfd__h593588 : + _theResult___snd__h593096[56:34] ; + assign out_sfd__h602775 = + sfdin__h602249[34] ? + _theResult___sfd__h602772 : + sfdin__h602249[56:34] ; + assign out_sfd__h611411 = + _theResult___snd__h610886[34] ? + _theResult___sfd__h611408 : + _theResult___snd__h610886[56:34] ; + assign out_sfd__h630758 = + sfdin__h630232[34] ? + _theResult___sfd__h630755 : + sfdin__h630232[56:34] ; + assign out_sfd__h639340 = + _theResult___snd__h638845[34] ? + _theResult___sfd__h639337 : + _theResult___snd__h638845[56:34] ; + assign out_sfd__h648524 = + sfdin__h647998[34] ? + _theResult___sfd__h648521 : + sfdin__h647998[56:34] ; + assign out_sfd__h657160 = + _theResult___snd__h656635[34] ? + _theResult___sfd__h657157 : + _theResult___snd__h656635[56:34] ; + assign out_sfd__h676505 = + sfdin__h675979[34] ? + _theResult___sfd__h676502 : + sfdin__h675979[56:34] ; + assign out_sfd__h685087 = + _theResult___snd__h684592[34] ? + _theResult___sfd__h685084 : + _theResult___snd__h684592[56:34] ; + assign out_sfd__h694271 = + sfdin__h693745[34] ? + _theResult___sfd__h694268 : + sfdin__h693745[56:34] ; + assign out_sfd__h702907 = + _theResult___snd__h702382[34] ? + _theResult___sfd__h702904 : + _theResult___snd__h702382[56:34] ; + assign out_sfd__h734869 = + _theResult___snd__h734161[5] ? + _theResult___sfd__h734866 : + _theResult___snd__h734161[56:5] ; + assign out_sfd__h744520 = + sfdin__h743781[5] ? + _theResult___sfd__h744517 : + sfdin__h743781[56:5] ; + assign out_sfd__h753304 = + _theResult___snd__h752566[5] ? + _theResult___sfd__h753301 : + _theResult___snd__h752566[56:5] ; + assign out_sfd__h773722 = + _theResult___snd__h773014[5] ? + _theResult___sfd__h773719 : + _theResult___snd__h773014[56:5] ; + assign out_sfd__h783373 = + sfdin__h782634[5] ? + _theResult___sfd__h783370 : + sfdin__h782634[56:5] ; + assign out_sfd__h792157 = + _theResult___snd__h791419[5] ? + _theResult___sfd__h792154 : + _theResult___snd__h791419[56:5] ; + assign out_sfd__h813026 = + _theResult___snd__h812318[5] ? + _theResult___sfd__h813023 : + _theResult___snd__h812318[56:5] ; + assign out_sfd__h822677 = + sfdin__h821938[5] ? + _theResult___sfd__h822674 : + sfdin__h821938[56:5] ; + assign out_sfd__h831461 = + _theResult___snd__h830723[5] ? + _theResult___sfd__h831458 : + _theResult___snd__h830723[56:5] ; + assign pc__h960824 = fetchStage$pipelines_1_first[590:462] ; + assign pc_addrBits__h992207 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h992383[13:0] : + x__h992378[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h992211 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h917993 = + assign pc_address__h992206 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h917988 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6082_ETC___d20090, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h1005920 = { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign pointer__h1025233 = { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign pointer__h242569 = + assign pointer__h1005915 = { 2'd0, rob$deqPort_0_deq_data[95:32] } ; + assign pointer__h1025227 = { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign pointer__h242568 = coreFix_memExe_regToExeQ$first[382:317] + - { 2'd0, offset__h242559 } ; - assign prv__h1012290 = csrf_prv_reg ; - assign prv__h1012334 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h706385 = + { 2'd0, offset__h242558 } ; + assign prv__h1012285 = csrf_prv_reg ; + assign prv__h1012329 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h706382 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h918542 = + assign r1__read_BITS_13_TO_0___h918537 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -36059,117 +36059,117 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h924176 = csrf_fs_reg ; - assign r1__read_BIT_20___h924682 = csrf_tw_reg ; - assign r1__read__h852705 = { r1__read__h852707, csrf_ie_vec_1 } ; - assign r1__read__h852707 = { r1__read__h852709, 2'b0 } ; - assign r1__read__h852709 = { r1__read__h852711, csrf_prev_ie_vec_0 } ; - assign r1__read__h852711 = { r1__read__h852713, csrf_prev_ie_vec_1 } ; - assign r1__read__h852713 = { r1__read__h852715, 2'b0 } ; - assign r1__read__h852715 = { r1__read__h852717, csrf_spp_reg } ; - assign r1__read__h852717 = { r1__read__h852719, 4'b0 } ; - assign r1__read__h852719 = { r1__read__h852721, csrf_fs_reg } ; - assign r1__read__h852721 = { r1__read__h852723, 2'd0 } ; - assign r1__read__h852723 = { r1__read__h852725, 1'b0 } ; - assign r1__read__h852725 = { r1__read__h852727, csrf_sum_reg } ; - assign r1__read__h852727 = { r1__read__h852729, csrf_mxr_reg } ; - assign r1__read__h852729 = { r1__read__h852731, 12'b0 } ; - assign r1__read__h852731 = { r1__read__h852733, 2'b10 } ; - assign r1__read__h852733 = { r__h852737, 29'b0 } ; - assign r1__read__h853109 = - { r1__read__h853111, csrf_software_int_en_vec_1 } ; - assign r1__read__h853111 = { r1__read__h853113, 2'b0 } ; - assign r1__read__h853113 = { r1__read__h853115, 1'b0 } ; - assign r1__read__h853115 = { r1__read__h853117, csrf_timer_int_en_vec_1 } ; - assign r1__read__h853117 = { r1__read__h853119, 2'b0 } ; - assign r1__read__h853119 = { r1__read__h853121, 1'b0 } ; - assign r1__read__h853121 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h853619 = { r1__read__h853621, csrf_scounteren_tm_reg } ; - assign r1__read__h853621 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h853631 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h853638 = - { r1__read__h853640, csrf_software_int_pend_vec_1 } ; - assign r1__read__h853640 = { r1__read__h853642, 2'b0 } ; - assign r1__read__h853642 = { r1__read__h853644, 1'b0 } ; - assign r1__read__h853644 = - { r1__read__h853646, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h853646 = { r1__read__h853648, 2'b0 } ; - assign r1__read__h853648 = { r1__read__h853650, 1'b0 } ; - assign r1__read__h853650 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h853848 = { vm_mode_reg__read__h853854, 16'd0 } ; - assign r1__read__h853871 = { r1__read__h853873, csrf_ie_vec_1 } ; - assign r1__read__h853873 = { r1__read__h853875, 1'b0 } ; - assign r1__read__h853875 = { r1__read__h853877, csrf_ie_vec_3 } ; - assign r1__read__h853877 = { r1__read__h853879, csrf_prev_ie_vec_0 } ; - assign r1__read__h853879 = { r1__read__h853881, csrf_prev_ie_vec_1 } ; - assign r1__read__h853881 = { r1__read__h853883, 1'b0 } ; - assign r1__read__h853883 = { r1__read__h853885, csrf_prev_ie_vec_3 } ; - assign r1__read__h853885 = { r1__read__h853887, csrf_spp_reg } ; - assign r1__read__h853887 = { r1__read__h853889, 2'b0 } ; - assign r1__read__h853889 = { r1__read__h853891, csrf_mpp_reg } ; - assign r1__read__h853891 = { r1__read__h853893, csrf_fs_reg } ; - assign r1__read__h853893 = { r1__read__h853895, 2'd0 } ; - assign r1__read__h853895 = { r1__read__h853897, csrf_mprv_reg } ; - assign r1__read__h853897 = { r1__read__h853899, csrf_sum_reg } ; - assign r1__read__h853899 = { r1__read__h853901, csrf_mxr_reg } ; - assign r1__read__h853901 = { r1__read__h853903, csrf_tvm_reg } ; - assign r1__read__h853903 = { r1__read__h853905, csrf_tw_reg } ; - assign r1__read__h853905 = { r1__read__h853907, csrf_tsr_reg } ; - assign r1__read__h853907 = { r1__read__h853909, 9'b0 } ; - assign r1__read__h853909 = { r1__read__h853911, 2'b10 } ; - assign r1__read__h853911 = { r1__read__h853913, 2'b10 } ; - assign r1__read__h853913 = { r__h852737, 27'b0 } ; - assign r1__read__h853996 = { r1__read__h853998, 1'b0 } ; - assign r1__read__h853998 = { r1__read__h854000, csrf_medeleg_13_11_reg } ; - assign r1__read__h854000 = { r1__read__h854002, 1'b0 } ; - assign r1__read__h854002 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h854013 = { r1__read__h854015, 1'b0 } ; - assign r1__read__h854015 = { r1__read__h854017, csrf_mideleg_5_3_reg } ; - assign r1__read__h854017 = { r1__read__h854019, 1'b0 } ; - assign r1__read__h854019 = { r1__read__h854021, csrf_mideleg_9_7_reg } ; - assign r1__read__h854021 = { r1__read__h854023, 1'b0 } ; - assign r1__read__h854023 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h854037 = - { r1__read__h854039, csrf_software_int_en_vec_1 } ; - assign r1__read__h854039 = { r1__read__h854041, 1'b0 } ; - assign r1__read__h854041 = - { r1__read__h854043, csrf_software_int_en_vec_3 } ; - assign r1__read__h854043 = { r1__read__h854045, 1'b0 } ; - assign r1__read__h854045 = { r1__read__h854047, csrf_timer_int_en_vec_1 } ; - assign r1__read__h854047 = { r1__read__h854049, 1'b0 } ; - assign r1__read__h854049 = { r1__read__h854051, csrf_timer_int_en_vec_3 } ; - assign r1__read__h854051 = { r1__read__h854053, 1'b0 } ; - assign r1__read__h854053 = - { r1__read__h854055, csrf_external_int_en_vec_1 } ; - assign r1__read__h854055 = { r1__read__h854057, 1'b0 } ; - assign r1__read__h854057 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h854130 = { r1__read__h854132, csrf_mcounteren_tm_reg } ; - assign r1__read__h854132 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h854142 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h854149 = - { r1__read__h854151, csrf_software_int_pend_vec_1 } ; - assign r1__read__h854151 = { r1__read__h854153, 1'b0 } ; - assign r1__read__h854153 = - { r1__read__h854155, csrf_software_int_pend_vec_3 } ; - assign r1__read__h854155 = { r1__read__h854157, 1'b0 } ; - assign r1__read__h854157 = - { r1__read__h854159, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h854159 = { r1__read__h854161, 1'b0 } ; - assign r1__read__h854161 = - { r1__read__h854163, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h854163 = { r1__read__h854165, 1'b0 } ; - assign r1__read__h854165 = - { r1__read__h854167, csrf_external_int_pend_vec_1 } ; - assign r1__read__h854167 = { r1__read__h854169, 1'b0 } ; - assign r1__read__h854169 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h854478 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h714446 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h714447 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h706411 = + assign r1__read_BITS_13_TO_12___h924171 = csrf_fs_reg ; + assign r1__read_BIT_20___h924677 = csrf_tw_reg ; + assign r1__read__h852702 = { r1__read__h852704, csrf_ie_vec_1 } ; + assign r1__read__h852704 = { r1__read__h852706, 2'b0 } ; + assign r1__read__h852706 = { r1__read__h852708, csrf_prev_ie_vec_0 } ; + assign r1__read__h852708 = { r1__read__h852710, csrf_prev_ie_vec_1 } ; + assign r1__read__h852710 = { r1__read__h852712, 2'b0 } ; + assign r1__read__h852712 = { r1__read__h852714, csrf_spp_reg } ; + assign r1__read__h852714 = { r1__read__h852716, 4'b0 } ; + assign r1__read__h852716 = { r1__read__h852718, csrf_fs_reg } ; + assign r1__read__h852718 = { r1__read__h852720, 2'd0 } ; + assign r1__read__h852720 = { r1__read__h852722, 1'b0 } ; + assign r1__read__h852722 = { r1__read__h852724, csrf_sum_reg } ; + assign r1__read__h852724 = { r1__read__h852726, csrf_mxr_reg } ; + assign r1__read__h852726 = { r1__read__h852728, 12'b0 } ; + assign r1__read__h852728 = { r1__read__h852730, 2'b10 } ; + assign r1__read__h852730 = { r__h852734, 29'b0 } ; + assign r1__read__h853106 = + { r1__read__h853108, csrf_software_int_en_vec_1 } ; + assign r1__read__h853108 = { r1__read__h853110, 2'b0 } ; + assign r1__read__h853110 = { r1__read__h853112, 1'b0 } ; + assign r1__read__h853112 = { r1__read__h853114, csrf_timer_int_en_vec_1 } ; + assign r1__read__h853114 = { r1__read__h853116, 2'b0 } ; + assign r1__read__h853116 = { r1__read__h853118, 1'b0 } ; + assign r1__read__h853118 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h853616 = { r1__read__h853618, csrf_scounteren_tm_reg } ; + assign r1__read__h853618 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h853628 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h853635 = + { r1__read__h853637, csrf_software_int_pend_vec_1 } ; + assign r1__read__h853637 = { r1__read__h853639, 2'b0 } ; + assign r1__read__h853639 = { r1__read__h853641, 1'b0 } ; + assign r1__read__h853641 = + { r1__read__h853643, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h853643 = { r1__read__h853645, 2'b0 } ; + assign r1__read__h853645 = { r1__read__h853647, 1'b0 } ; + assign r1__read__h853647 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h853845 = { vm_mode_reg__read__h853851, 16'd0 } ; + assign r1__read__h853868 = { r1__read__h853870, csrf_ie_vec_1 } ; + assign r1__read__h853870 = { r1__read__h853872, 1'b0 } ; + assign r1__read__h853872 = { r1__read__h853874, csrf_ie_vec_3 } ; + assign r1__read__h853874 = { r1__read__h853876, csrf_prev_ie_vec_0 } ; + assign r1__read__h853876 = { r1__read__h853878, csrf_prev_ie_vec_1 } ; + assign r1__read__h853878 = { r1__read__h853880, 1'b0 } ; + assign r1__read__h853880 = { r1__read__h853882, csrf_prev_ie_vec_3 } ; + assign r1__read__h853882 = { r1__read__h853884, csrf_spp_reg } ; + assign r1__read__h853884 = { r1__read__h853886, 2'b0 } ; + assign r1__read__h853886 = { r1__read__h853888, csrf_mpp_reg } ; + assign r1__read__h853888 = { r1__read__h853890, csrf_fs_reg } ; + assign r1__read__h853890 = { r1__read__h853892, 2'd0 } ; + assign r1__read__h853892 = { r1__read__h853894, csrf_mprv_reg } ; + assign r1__read__h853894 = { r1__read__h853896, csrf_sum_reg } ; + assign r1__read__h853896 = { r1__read__h853898, csrf_mxr_reg } ; + assign r1__read__h853898 = { r1__read__h853900, csrf_tvm_reg } ; + assign r1__read__h853900 = { r1__read__h853902, csrf_tw_reg } ; + assign r1__read__h853902 = { r1__read__h853904, csrf_tsr_reg } ; + assign r1__read__h853904 = { r1__read__h853906, 9'b0 } ; + assign r1__read__h853906 = { r1__read__h853908, 2'b10 } ; + assign r1__read__h853908 = { r1__read__h853910, 2'b10 } ; + assign r1__read__h853910 = { r__h852734, 27'b0 } ; + assign r1__read__h853993 = { r1__read__h853995, 1'b0 } ; + assign r1__read__h853995 = { r1__read__h853997, csrf_medeleg_13_11_reg } ; + assign r1__read__h853997 = { r1__read__h853999, 1'b0 } ; + assign r1__read__h853999 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h854010 = { r1__read__h854012, 1'b0 } ; + assign r1__read__h854012 = { r1__read__h854014, csrf_mideleg_5_3_reg } ; + assign r1__read__h854014 = { r1__read__h854016, 1'b0 } ; + assign r1__read__h854016 = { r1__read__h854018, csrf_mideleg_9_7_reg } ; + assign r1__read__h854018 = { r1__read__h854020, 1'b0 } ; + assign r1__read__h854020 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h854034 = + { r1__read__h854036, csrf_software_int_en_vec_1 } ; + assign r1__read__h854036 = { r1__read__h854038, 1'b0 } ; + assign r1__read__h854038 = + { r1__read__h854040, csrf_software_int_en_vec_3 } ; + assign r1__read__h854040 = { r1__read__h854042, 1'b0 } ; + assign r1__read__h854042 = { r1__read__h854044, csrf_timer_int_en_vec_1 } ; + assign r1__read__h854044 = { r1__read__h854046, 1'b0 } ; + assign r1__read__h854046 = { r1__read__h854048, csrf_timer_int_en_vec_3 } ; + assign r1__read__h854048 = { r1__read__h854050, 1'b0 } ; + assign r1__read__h854050 = + { r1__read__h854052, csrf_external_int_en_vec_1 } ; + assign r1__read__h854052 = { r1__read__h854054, 1'b0 } ; + assign r1__read__h854054 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h854127 = { r1__read__h854129, csrf_mcounteren_tm_reg } ; + assign r1__read__h854129 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h854139 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h854146 = + { r1__read__h854148, csrf_software_int_pend_vec_1 } ; + assign r1__read__h854148 = { r1__read__h854150, 1'b0 } ; + assign r1__read__h854150 = + { r1__read__h854152, csrf_software_int_pend_vec_3 } ; + assign r1__read__h854152 = { r1__read__h854154, 1'b0 } ; + assign r1__read__h854154 = + { r1__read__h854156, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h854156 = { r1__read__h854158, 1'b0 } ; + assign r1__read__h854158 = + { r1__read__h854160, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h854160 = { r1__read__h854162, 1'b0 } ; + assign r1__read__h854162 = + { r1__read__h854164, csrf_external_int_pend_vec_1 } ; + assign r1__read__h854164 = { r1__read__h854166, 1'b0 } ; + assign r1__read__h854166 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h854475 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h714443 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h714444 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h706408 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h852737 = csrf_fs_reg == 2'b11 ; - assign r__h854224 = csrf_software_int_pend_vec_3 ; + assign r__h852734 = csrf_fs_reg == 2'b11 ; + assign r__h854221 = csrf_software_int_pend_vec_3 ; assign regRenamingTable_RDY_rename_0_getRename__0810__ETC___d20821 = regRenamingTable$RDY_rename_0_getRename && rob$RDY_enqPort_0_enq && @@ -36372,78 +36372,78 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20436[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h966287 = + assign renaming_spec_bits__h966282 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h960972 : + y_avValue_snd_fst__h960967 : specTagManager$currentSpecBits ; - assign repBoundBits__h242584 = + assign repBoundBits__h242583 = { coreFix_memExe_regToExeQ$first[230:228], 11'd0 } ; - assign repBound__h237262 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h238947 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h248150 = + assign repBound__h237261 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h238946 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h248148 = coreFix_memExe_regToExeQ$first[244:242] - 3'b001 ; - assign repBound__h248675 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h856058 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h859402 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h859420 = thin_bounds_baseBits__h859273[13:11] - 3'b001 ; - assign repBound__h865966 = x__h865905[13:11] - 3'b001 ; - assign repBound__h866514 = x__h866453[13:11] - 3'b001 ; - assign repBound__h896085 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h898412 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h898430 = thin_bounds_baseBits__h898315[13:11] - 3'b001 ; - assign repBound__h904588 = x__h904527[13:11] - 3'b001 ; - assign repBound__h905136 = x__h905075[13:11] - 3'b001 ; - assign repBound__h995071 = x__h992601[13:11] - 3'b001 ; - assign repBound__h997124 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h997781 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign res_addrBits__h126792 = + assign repBound__h248673 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h856055 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h859399 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h859417 = thin_bounds_baseBits__h859270[13:11] - 3'b001 ; + assign repBound__h865963 = x__h865902[13:11] - 3'b001 ; + assign repBound__h866511 = x__h866450[13:11] - 3'b001 ; + assign repBound__h896081 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h898408 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h898426 = thin_bounds_baseBits__h898311[13:11] - 3'b001 ; + assign repBound__h904584 = x__h904523[13:11] - 3'b001 ; + assign repBound__h905132 = x__h905071[13:11] - 3'b001 ; + assign repBound__h995066 = x__h992596[13:11] - 3'b001 ; + assign repBound__h997119 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h997776 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign res_addrBits__h126791 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127272[13:0] : + x__h127271[13:0] : coreFix_memExe_respLrScAmoQ_data_0[13:0] ; - assign res_addrBits__h139704 = + assign res_addrBits__h139703 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? - x__h140188[13:0] : + x__h140187[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h178867 = - INV_x83367_BITS_108_TO_90__q33[0] ? - x__h183449[13:0] : - x__h183367[13:0] ; - assign res_addrBits__h197632 = - INV_x99219_BITS_108_TO_90__q35[0] ? - x__h202200[13:0] : - x__h199219[13:0] ; - assign res_addrBits__h216391 = + assign res_addrBits__h178866 = + INV_x83366_BITS_108_TO_90__q33[0] ? + x__h183448[13:0] : + x__h183366[13:0] ; + assign res_addrBits__h197631 = + INV_x99218_BITS_108_TO_90__q35[0] ? + x__h202199[13:0] : + x__h199218[13:0] ; + assign res_addrBits__h216390 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? - x__h216766[13:0] : + x__h216765[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h235268 = { 2'b0, addr__h235261[63:52] } ; - assign res_addrBits__h567274 = + assign res_addrBits__h235267 = { 2'b0, addr__h235260[63:52] } ; + assign res_addrBits__h567270 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; - assign res_addrBits__h568126 = { 2'b0, data__h567607[63:52] } ; - assign res_addrBits__h613883 = { 2'b0, data__h613367[63:52] } ; - assign res_addrBits__h659630 = { 2'b0, data__h659114[63:52] } ; - assign res_addrBits__h705439 = { 2'b0, data__h704928[63:52] } ; - assign res_addrBits__h706299 = { 2'b0, data__h705791[63:52] } ; - assign res_addrBits__h848498 = { 2'b0, addr__h843840[63:52] } ; - assign res_addrBits__h890899 = { 2'b0, addr__h886249[63:52] } ; - assign res_address__h126791 = + assign res_addrBits__h568123 = { 2'b0, data__h567604[63:52] } ; + assign res_addrBits__h613880 = { 2'b0, data__h613364[63:52] } ; + assign res_addrBits__h659627 = { 2'b0, data__h659111[63:52] } ; + assign res_addrBits__h705436 = { 2'b0, data__h704925[63:52] } ; + assign res_addrBits__h706296 = { 2'b0, data__h705788[63:52] } ; + assign res_addrBits__h848495 = { 2'b0, addr__h843837[63:52] } ; + assign res_addrBits__h890895 = { 2'b0, addr__h886245[63:52] } ; + assign res_address__h126790 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; - assign res_address__h139703 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h178866 = { 2'd0, x__h183367[63:0] } ; - assign res_address__h197631 = { 2'd0, x__h199219[63:0] } ; - assign res_address__h216390 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h235267 = { 2'd0, addr__h235261 } ; - assign res_address__h567273 = + assign res_address__h139702 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; + assign res_address__h178865 = { 2'd0, x__h183366[63:0] } ; + assign res_address__h197630 = { 2'd0, x__h199218[63:0] } ; + assign res_address__h216389 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h235266 = { 2'd0, addr__h235260 } ; + assign res_address__h567269 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; - assign res_address__h568125 = { 2'd0, data__h567607 } ; - assign res_address__h613882 = { 2'd0, data__h613367 } ; - assign res_address__h659629 = { 2'd0, data__h659114 } ; - assign res_address__h705438 = { 2'd0, data__h704928 } ; - assign res_address__h706298 = { 2'd0, data__h705791 } ; - assign res_address__h848497 = { 2'd0, addr__h843840 } ; - assign res_address__h890898 = { 2'd0, addr__h886249 } ; - assign res_data__h568165 = { 32'hFFFFFFFF, x__h568180 } ; - assign res_data__h568170 = + assign res_address__h568122 = { 2'd0, data__h567604 } ; + assign res_address__h613879 = { 2'd0, data__h613364 } ; + assign res_address__h659626 = { 2'd0, data__h659111 } ; + assign res_address__h705435 = { 2'd0, data__h704925 } ; + assign res_address__h706295 = { 2'd0, data__h705788 } ; + assign res_address__h848494 = { 2'd0, addr__h843837 } ; + assign res_address__h890894 = { 2'd0, addr__h886245 } ; + assign res_data__h568162 = { 32'hFFFFFFFF, x__h568177 } ; + assign res_data__h568167 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -36456,8 +36456,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h613919 = { 32'hFFFFFFFF, x__h613934 } ; - assign res_data__h613924 = + assign res_data__h613916 = { 32'hFFFFFFFF, x__h613931 } ; + assign res_data__h613921 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -36470,8 +36470,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h659666 = { 32'hFFFFFFFF, x__h659681 } ; - assign res_data__h659671 = + assign res_data__h659663 = { 32'hFFFFFFFF, x__h659678 } ; + assign res_data__h659668 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -36484,7 +36484,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h568166 = + assign res_fflags__h568163 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -36552,7 +36552,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9365 } ; - assign res_fflags__h613920 = + assign res_fflags__h613917 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -36620,7 +36620,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10762 } ; - assign res_fflags__h659667 = + assign res_fflags__h659664 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -36688,69 +36688,69 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12159 } ; - assign resp_addr__h509039 = + assign resp_addr__h509036 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[53:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[168:158] } ; - assign result__h240541 = + assign result__h240540 = { 1'd0, ~coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64], coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[63:0] } ; - assign result__h241698 = + assign result__h241697 = { 1'd0, ~coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64], coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[63:0] } ; - assign result__h255307 = + assign result__h255305 = { 1'd0, ~coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64], coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[63:0] } ; - assign result__h594633 = + assign result__h594630 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663[0] | - guard__h594628 } ; - assign result__h640382 = + guard__h594625 } ; + assign result__h640379 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060[0] | - guard__h640377 } ; - assign result__h686129 = + guard__h640374 } ; + assign result__h686126 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457[0] | - guard__h686124 } ; - assign result__h736167 = + guard__h686121 } ; + assign result__h736164 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786[0] | - guard__h736162 } ; - assign result__h775020 = + guard__h736159 } ; + assign result__h775017 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271[0] | - guard__h775015 } ; - assign result__h814324 = + guard__h775012 } ; + assign result__h814321 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501[0] | - guard__h814319 } ; - assign result__h913573 = w__h913568 & y__h913602 ; - assign result__h913624 = ~x__h913623 ; - assign result_d_address__h242780 = { 2'd0, pointer__h242569[63:0] } ; - assign ret__h239918 = + guard__h814316 } ; + assign result__h913568 = w__h913563 & y__h913597 ; + assign result__h913619 = ~x__h913618 ; + assign result_d_address__h242779 = { 2'd0, pointer__h242568[63:0] } ; + assign ret__h239917 = { 1'd0, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64:0] } ; - assign ret__h241075 = + assign ret__h241074 = { 1'd0, coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64:0] } ; - assign ret__h254684 = + assign ret__h254682 = { 1'd0, coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18901 = - rf$read_0_rd1[27:25] < repBound__h896085 ; + rf$read_0_rd1[27:25] < repBound__h896081 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18914 = - rf$read_0_rd1[13:11] < repBound__h896085 ; + rf$read_0_rd1[13:11] < repBound__h896081 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18928 = - rf$read_0_rd1[85:83] < repBound__h896085 ; + rf$read_0_rd1[85:83] < repBound__h896081 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18972 = - rf$read_0_rd2[27:25] < repBound__h898412 ; + rf$read_0_rd2[27:25] < repBound__h898408 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18973 = - rf$read_0_rd2[13:11] < repBound__h898412 ; + rf$read_0_rd2[13:11] < repBound__h898408 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18975 = - rf$read_0_rd2[85:83] < repBound__h898412 ; + rf$read_0_rd2[85:83] < repBound__h898408 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18985 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18975, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18972 == @@ -36768,17 +36768,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16517 = - rf$read_1_rd1[27:25] < repBound__h856058 ; + rf$read_1_rd1[27:25] < repBound__h856055 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16530 = - rf$read_1_rd1[13:11] < repBound__h856058 ; + rf$read_1_rd1[13:11] < repBound__h856055 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16544 = - rf$read_1_rd1[85:83] < repBound__h856058 ; + rf$read_1_rd1[85:83] < repBound__h856055 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588 = - rf$read_1_rd2[27:25] < repBound__h859402 ; + rf$read_1_rd2[27:25] < repBound__h859399 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16589 = - rf$read_1_rd2[13:11] < repBound__h859402 ; + rf$read_1_rd2[13:11] < repBound__h859399 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16591 = - rf$read_1_rd2[85:83] < repBound__h859402 ; + rf$read_1_rd2[85:83] < repBound__h859399 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16601 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16591, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588 == @@ -36796,25 +36796,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3319 = - rf$read_3_rd1[27:25] < repBound__h237262 ; + rf$read_3_rd1[27:25] < repBound__h237261 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3332 = - rf$read_3_rd1[13:11] < repBound__h237262 ; + rf$read_3_rd1[13:11] < repBound__h237261 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346 = - rf$read_3_rd1[85:83] < repBound__h237262 ; + rf$read_3_rd1[85:83] < repBound__h237261 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3580 = - rf$read_3_rd2[27:25] < repBound__h238947 ; + rf$read_3_rd2[27:25] < repBound__h238946 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3588 = - rf$read_3_rd2[13:11] < repBound__h238947 ; + rf$read_3_rd2[13:11] < repBound__h238946 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597 = - rf$read_3_rd2[85:83] < repBound__h238947 ; + rf$read_3_rd2[85:83] < repBound__h238946 ; assign rg_core_run_state_read__0464_EQ_2_0465_AND_NOT_ETC___d23466 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h851828 = - { r1__read__h854478, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h851825 = + { r1__read__h854475, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1405_AND_epochManager_ch_ETC___d21410 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -36824,7 +36824,7 @@ module mkCore(CLK, IF_IF_fetchStage_pipelines_0_first__0049_BITS__ETC___d21013) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q326 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h849689 = { r1__read__h853848, csrf_ppn_reg } ; + assign satp_csr__read__h849686 = { r1__read__h853845, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12424 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12380 && @@ -36844,272 +36844,272 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__679_AN_ETC___d2742 && IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2759) ; - assign sbIdx__h151985 = + assign sbIdx__h151984 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h849486 = - { r1__read__h853631, csrf_scause_code_reg } ; - assign scounteren_csr__read__h849391 = - { r1__read__h853619, csrf_scounteren_cy_reg } ; - assign sfd__h568776 = { value__h577003, 3'd0 } ; - assign sfd__h584584 = + assign scause_csr__read__h849483 = + { r1__read__h853628, csrf_scause_code_reg } ; + assign scounteren_csr__read__h849388 = + { r1__read__h853616, csrf_scounteren_cy_reg } ; + assign sfd__h568773 = { value__h577000, 3'd0 } ; + assign sfd__h584581 = { 1'b0, - _theResult___fst_exp__h584492 != 8'd0, - sfdin__h584486[56:34] } + + _theResult___fst_exp__h584489 != 8'd0, + sfdin__h584483[56:34] } + 25'd1 ; - assign sfd__h593166 = + assign sfd__h593163 = { 1'b0, - _theResult___fst_exp__h593148 != 8'd0, - _theResult___snd__h593099[56:34] } + + _theResult___fst_exp__h593145 != 8'd0, + _theResult___snd__h593096[56:34] } + 25'd1 ; - assign sfd__h602350 = + assign sfd__h602347 = { 1'b0, - _theResult___fst_exp__h602258 != 8'd0, - sfdin__h602252[56:34] } + + _theResult___fst_exp__h602255 != 8'd0, + sfdin__h602249[56:34] } + 25'd1 ; - assign sfd__h610962 = + assign sfd__h610959 = { 1'b0, - _theResult___fst_exp__h610943 != 8'd0, - _theResult___snd__h610889[56:34] } + + _theResult___fst_exp__h610940 != 8'd0, + _theResult___snd__h610886[56:34] } + 25'd1 ; - assign sfd__h614530 = { value__h622752, 3'd0 } ; - assign sfd__h630333 = + assign sfd__h614527 = { value__h622749, 3'd0 } ; + assign sfd__h630330 = { 1'b0, - _theResult___fst_exp__h630241 != 8'd0, - sfdin__h630235[56:34] } + + _theResult___fst_exp__h630238 != 8'd0, + sfdin__h630232[56:34] } + 25'd1 ; - assign sfd__h638915 = + assign sfd__h638912 = { 1'b0, - _theResult___fst_exp__h638897 != 8'd0, - _theResult___snd__h638848[56:34] } + + _theResult___fst_exp__h638894 != 8'd0, + _theResult___snd__h638845[56:34] } + 25'd1 ; - assign sfd__h648099 = + assign sfd__h648096 = { 1'b0, - _theResult___fst_exp__h648007 != 8'd0, - sfdin__h648001[56:34] } + + _theResult___fst_exp__h648004 != 8'd0, + sfdin__h647998[56:34] } + 25'd1 ; - assign sfd__h656711 = + assign sfd__h656708 = { 1'b0, - _theResult___fst_exp__h656692 != 8'd0, - _theResult___snd__h656638[56:34] } + + _theResult___fst_exp__h656689 != 8'd0, + _theResult___snd__h656635[56:34] } + 25'd1 ; - assign sfd__h660277 = { value__h668499, 3'd0 } ; - assign sfd__h676080 = + assign sfd__h660274 = { value__h668496, 3'd0 } ; + assign sfd__h676077 = { 1'b0, - _theResult___fst_exp__h675988 != 8'd0, - sfdin__h675982[56:34] } + + _theResult___fst_exp__h675985 != 8'd0, + sfdin__h675979[56:34] } + 25'd1 ; - assign sfd__h684662 = + assign sfd__h684659 = { 1'b0, - _theResult___fst_exp__h684644 != 8'd0, - _theResult___snd__h684595[56:34] } + + _theResult___fst_exp__h684641 != 8'd0, + _theResult___snd__h684592[56:34] } + 25'd1 ; - assign sfd__h693846 = + assign sfd__h693843 = { 1'b0, - _theResult___fst_exp__h693754 != 8'd0, - sfdin__h693748[56:34] } + + _theResult___fst_exp__h693751 != 8'd0, + sfdin__h693745[56:34] } + 25'd1 ; - assign sfd__h702458 = + assign sfd__h702455 = { 1'b0, - _theResult___fst_exp__h702439 != 8'd0, - _theResult___snd__h702385[56:34] } + + _theResult___fst_exp__h702436 != 8'd0, + _theResult___snd__h702382[56:34] } + 25'd1 ; - assign sfd__h715187 = { value__h719770, 32'd0 } ; - assign sfd__h734231 = + assign sfd__h715184 = { value__h719767, 32'd0 } ; + assign sfd__h734228 = { 1'b0, - _theResult___fst_exp__h734213 != 11'd0, - _theResult___snd__h734164[56:5] } + + _theResult___fst_exp__h734210 != 11'd0, + _theResult___snd__h734161[56:5] } + 54'd1 ; - assign sfd__h743882 = + assign sfd__h743879 = { 1'b0, - _theResult___fst_exp__h743790 != 11'd0, - sfdin__h743784[56:5] } + + _theResult___fst_exp__h743787 != 11'd0, + sfdin__h743781[56:5] } + 54'd1 ; - assign sfd__h752642 = + assign sfd__h752639 = { 1'b0, - _theResult___fst_exp__h752623 != 11'd0, - _theResult___snd__h752569[56:5] } + + _theResult___fst_exp__h752620 != 11'd0, + _theResult___snd__h752566[56:5] } + 54'd1 ; - assign sfd__h754181 = { value__h758623, 32'd0 } ; - assign sfd__h773084 = + assign sfd__h754178 = { value__h758620, 32'd0 } ; + assign sfd__h773081 = { 1'b0, - _theResult___fst_exp__h773066 != 11'd0, - _theResult___snd__h773017[56:5] } + + _theResult___fst_exp__h773063 != 11'd0, + _theResult___snd__h773014[56:5] } + 54'd1 ; - assign sfd__h782735 = + assign sfd__h782732 = { 1'b0, - _theResult___fst_exp__h782643 != 11'd0, - sfdin__h782637[56:5] } + + _theResult___fst_exp__h782640 != 11'd0, + sfdin__h782634[56:5] } + 54'd1 ; - assign sfd__h791495 = + assign sfd__h791492 = { 1'b0, - _theResult___fst_exp__h791476 != 11'd0, - _theResult___snd__h791422[56:5] } + + _theResult___fst_exp__h791473 != 11'd0, + _theResult___snd__h791419[56:5] } + 54'd1 ; - assign sfd__h793485 = { value__h797927, 32'd0 } ; - assign sfd__h812388 = + assign sfd__h793482 = { value__h797924, 32'd0 } ; + assign sfd__h812385 = { 1'b0, - _theResult___fst_exp__h812370 != 11'd0, - _theResult___snd__h812321[56:5] } + + _theResult___fst_exp__h812367 != 11'd0, + _theResult___snd__h812318[56:5] } + 54'd1 ; - assign sfd__h822039 = + assign sfd__h822036 = { 1'b0, - _theResult___fst_exp__h821947 != 11'd0, - sfdin__h821941[56:5] } + + _theResult___fst_exp__h821944 != 11'd0, + sfdin__h821938[56:5] } + 54'd1 ; - assign sfd__h830799 = + assign sfd__h830796 = { 1'b0, - _theResult___fst_exp__h830780 != 11'd0, - _theResult___snd__h830726[56:5] } + + _theResult___fst_exp__h830777 != 11'd0, + _theResult___snd__h830723[56:5] } + 54'd1 ; - assign sfdin__h584486 = - _theResult____h576381[56] ? - _theResult___snd__h584503 : - _theResult___snd__h584514 ; - assign sfdin__h602252 = - _theResult____h594020[56] ? - _theResult___snd__h602269 : - _theResult___snd__h602280 ; - assign sfdin__h630235 = - _theResult____h622132[56] ? - _theResult___snd__h630252 : - _theResult___snd__h630263 ; - assign sfdin__h648001 = - _theResult____h639769[56] ? - _theResult___snd__h648018 : - _theResult___snd__h648029 ; - assign sfdin__h675982 = - _theResult____h667879[56] ? - _theResult___snd__h675999 : - _theResult___snd__h676010 ; - assign sfdin__h693748 = - _theResult____h685516[56] ? - _theResult___snd__h693765 : - _theResult___snd__h693776 ; - assign sfdin__h743784 = - _theResult____h735554[56] ? - _theResult___snd__h743801 : - _theResult___snd__h743812 ; - assign sfdin__h782637 = - _theResult____h774407[56] ? - _theResult___snd__h782654 : - _theResult___snd__h782665 ; - assign sfdin__h821941 = - _theResult____h813711[56] ? - _theResult___snd__h821958 : - _theResult___snd__h821969 ; - assign sie_csr__read__h849338 = { r1__read__h853109, 1'b0 } ; - assign signBits__h242575 = {50{offset__h242559[63]}} ; - assign sip_csr__read__h849626 = { r1__read__h853638, 1'b0 } ; - assign spec_bits__h971306 = specTagManager$currentSpecBits | y__h971319 ; - assign sstatus_csr__read__h849268 = { r1__read__h852705, csrf_ie_vec_0 } ; - assign tb__h865963 = { impliedTopBits__h865817, topBits__h865813[11] } ; - assign tb__h866511 = { impliedTopBits__h866365, topBits__h866361[11] } ; - assign tb__h904585 = { impliedTopBits__h904439, topBits__h904435[11] } ; - assign tb__h905133 = { impliedTopBits__h904987, topBits__h904983[11] } ; - assign thin_address__h996854 = + assign sfdin__h584483 = + _theResult____h576378[56] ? + _theResult___snd__h584500 : + _theResult___snd__h584511 ; + assign sfdin__h602249 = + _theResult____h594017[56] ? + _theResult___snd__h602266 : + _theResult___snd__h602277 ; + assign sfdin__h630232 = + _theResult____h622129[56] ? + _theResult___snd__h630249 : + _theResult___snd__h630260 ; + assign sfdin__h647998 = + _theResult____h639766[56] ? + _theResult___snd__h648015 : + _theResult___snd__h648026 ; + assign sfdin__h675979 = + _theResult____h667876[56] ? + _theResult___snd__h675996 : + _theResult___snd__h676007 ; + assign sfdin__h693745 = + _theResult____h685513[56] ? + _theResult___snd__h693762 : + _theResult___snd__h693773 ; + assign sfdin__h743781 = + _theResult____h735551[56] ? + _theResult___snd__h743798 : + _theResult___snd__h743809 ; + assign sfdin__h782634 = + _theResult____h774404[56] ? + _theResult___snd__h782651 : + _theResult___snd__h782662 ; + assign sfdin__h821938 = + _theResult____h813708[56] ? + _theResult___snd__h821955 : + _theResult___snd__h821966 ; + assign sie_csr__read__h849335 = { r1__read__h853106, 1'b0 } ; + assign signBits__h242574 = {50{offset__h242558[63]}} ; + assign sip_csr__read__h849623 = { r1__read__h853635, 1'b0 } ; + assign spec_bits__h971301 = specTagManager$currentSpecBits | y__h971314 ; + assign sstatus_csr__read__h849265 = { r1__read__h852702, csrf_ie_vec_0 } ; + assign tb__h865960 = { impliedTopBits__h865814, topBits__h865810[11] } ; + assign tb__h866508 = { impliedTopBits__h866362, topBits__h866358[11] } ; + assign tb__h904581 = { impliedTopBits__h904435, topBits__h904431[11] } ; + assign tb__h905129 = { impliedTopBits__h904983, topBits__h904979[11] } ; + assign thin_address__h996849 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22687 : IF_csrf_mtcc_reg_read__6627_BIT_86_2584_AND_NO_ETC___d22688 ; - assign tmpAddr__h242768 = pointer__h242569[63:0] ; - assign tmp_expBotHalf__h127265 = + assign tmpAddr__h242767 = pointer__h242568[63:0] ; + assign tmp_expBotHalf__h127264 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign tmp_expBotHalf__h140181 = + assign tmp_expBotHalf__h140180 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h183442 = { ~x__h183367[66], x__h183367[65:64] } ; - assign tmp_expBotHalf__h202193 = { ~x__h199219[66], x__h199219[65:64] } ; - assign tmp_expBotHalf__h216759 = + assign tmp_expBotHalf__h183441 = { ~x__h183366[66], x__h183366[65:64] } ; + assign tmp_expBotHalf__h202192 = { ~x__h199218[66], x__h199218[65:64] } ; + assign tmp_expBotHalf__h216758 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h865666 = + assign tmp_expBotHalf__h865663 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h866214 = + assign tmp_expBotHalf__h866211 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h904288 = + assign tmp_expBotHalf__h904284 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h904836 = + assign tmp_expBotHalf__h904832 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h992376 = + assign tmp_expBotHalf__h992371 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign tmp_expTopHalf__h127263 = + assign tmp_expTopHalf__h127262 = { ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign tmp_expTopHalf__h140179 = + assign tmp_expTopHalf__h140178 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h183440 = { ~x__h183367[80:79], x__h183367[78] } ; - assign tmp_expTopHalf__h202191 = { ~x__h199219[80:79], x__h199219[78] } ; - assign tmp_expTopHalf__h216757 = + assign tmp_expTopHalf__h183439 = { ~x__h183366[80:79], x__h183366[78] } ; + assign tmp_expTopHalf__h202190 = { ~x__h199218[80:79], x__h199218[78] } ; + assign tmp_expTopHalf__h216756 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h865664 = + assign tmp_expTopHalf__h865661 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h866212 = + assign tmp_expTopHalf__h866209 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h904286 = + assign tmp_expTopHalf__h904282 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h904834 = + assign tmp_expTopHalf__h904830 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h992374 = + assign tmp_expTopHalf__h992369 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign toBoundsM1__h242588 = - repBoundBits__h242584 + + assign toBoundsM1__h242587 = + repBoundBits__h242583 + ~coreFix_memExe_regToExeQ$first[316:303] ; - assign toBounds__h242587 = - repBoundBits__h242584 - coreFix_memExe_regToExeQ$first[316:303] ; - assign topBits__h127399 = + assign toBounds__h242586 = + repBoundBits__h242583 - coreFix_memExe_regToExeQ$first[316:303] ; + assign topBits__h127398 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : - b_top__h127496 ; - assign topBits__h140315 = + b_top__h127495 ; + assign topBits__h140314 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : - b_top__h140412 ; - assign topBits__h183576 = - INV_x83367_BITS_108_TO_90__q33[0] ? - { x__h183367[89:81], 3'd0 } : - b_top__h183673 ; - assign topBits__h202327 = - INV_x99219_BITS_108_TO_90__q35[0] ? - { x__h199219[89:81], 3'd0 } : - b_top__h202424 ; - assign topBits__h216893 = + b_top__h140411 ; + assign topBits__h183575 = + INV_x83366_BITS_108_TO_90__q33[0] ? + { x__h183366[89:81], 3'd0 } : + b_top__h183672 ; + assign topBits__h202326 = + INV_x99218_BITS_108_TO_90__q35[0] ? + { x__h199218[89:81], 3'd0 } : + b_top__h202423 ; + assign topBits__h216892 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h216990 ; - assign topBits__h865813 = + b_top__h216989 ; + assign topBits__h865810 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h865911 ; - assign topBits__h866361 = + b_top__h865908 ; + assign topBits__h866358 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h866459 ; - assign topBits__h904435 = + b_top__h866456 ; + assign topBits__h904431 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h904533 ; - assign topBits__h904983 = + b_top__h904529 ; + assign topBits__h904979 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h905081 ; - assign topBits__h992510 = + b_top__h905077 ; + assign topBits__h992505 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h992607 ; - assign trap_val__h994512 = { 53'd0, x__h996333 } ; - assign upd__h1009069 = + b_top__h992602 ; + assign trap_val__h994507 = { 53'd0, x__h996328 } ; + assign upd__h1009064 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -37122,7 +37122,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1007648 = + assign v__h1007643 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], @@ -37134,7 +37134,7 @@ module mkCore(CLK, ~IF_csrf_sepcc_reg_read_wget__3089_BIT_34_3098__ETC___d23106[2], IF_csrf_sepcc_reg_read_wget__3089_BIT_34_3098__ETC___d23106[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1008101 = + assign v__h1008096 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], @@ -37146,308 +37146,308 @@ module mkCore(CLK, ~IF_csrf_mepcc_reg_read_wget__3118_BIT_34_3127__ETC___d23135[2], IF_csrf_mepcc_reg_read_wget__3118_BIT_34_3127__ETC___d23135[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h514752 = + assign v__h514748 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ? - v__h514947 : + v__h514943 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h514947 = + assign v__h514943 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h516772 = + assign v__h516768 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 ? - v__h517152 : + v__h517148 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h517152 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h532491 = + assign v__h517148 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h532487 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 ? - v__h532686 : + v__h532682 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h532686 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h534940 = + assign v__h532682 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h534936 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 ? - v__h535135 : + v__h535131 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h535135 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h555960 = + assign v__h535131 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h555956 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 ? - v__h556155 : + v__h556151 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h556155 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h559739 = + assign v__h556151 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h559735 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 ? - v__h559934 : + v__h559930 : coreFix_memExe_forwardQ_enqP ; - assign v__h559934 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h836568 = + assign v__h559930 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h836565 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h836578 : + v__h836575 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h836578 = + assign v__h836575 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h837213 = v__h836568 - 2'd1 ; - assign value__h239635 = x__h239653 | in__h239745[63:0] ; - assign value__h239799 = - { coreFix_memExe_regToExeQ$first[380:331] & mask__h239806, + assign v__h837210 = v__h836565 - 2'd1 ; + assign value__h239634 = x__h239652 | in__h239744[63:0] ; + assign value__h239798 = + { coreFix_memExe_regToExeQ$first[380:331] & mask__h239805, 14'd0 } + - addBase__h239805 ; - assign value__h240792 = x__h240810 | in__h240902[63:0] ; - assign value__h240956 = - { coreFix_memExe_regToExeQ$first[217:168] & mask__h240963, + addBase__h239804 ; + assign value__h240791 = x__h240809 | in__h240901[63:0] ; + assign value__h240955 = + { coreFix_memExe_regToExeQ$first[217:168] & mask__h240962, 14'd0 } + - addBase__h240962 ; - assign value__h254401 = x__h254419 | in__h254511[63:0] ; - assign value__h254565 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h254572, + addBase__h240961 ; + assign value__h254399 = x__h254417 | in__h254509[63:0] ; + assign value__h254563 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h254570, 14'd0 } + - addBase__h254571 ; - assign value__h577003 = + addBase__h254569 ; + assign value__h577000 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h622752 = + assign value__h622749 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h668499 = + assign value__h668496 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h719770 = { 1'b0, f1_exp__h714825 != 8'd0, f1_sfd__h714826 } ; - assign value__h758623 = { 1'b0, f2_exp__h753819 != 8'd0, f2_sfd__h753820 } ; - assign value__h797927 = { 1'b0, f3_exp__h793123 != 8'd0, f3_sfd__h793124 } ; - assign vm_mode_reg__read__h853854 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h913568 = + assign value__h719767 = { 1'b0, f1_exp__h714822 != 8'd0, f1_sfd__h714823 } ; + assign value__h758620 = { 1'b0, f2_exp__h753816 != 8'd0, f2_sfd__h753817 } ; + assign value__h797924 = { 1'b0, f3_exp__h793120 != 8'd0, f3_sfd__h793121 } ; + assign vm_mode_reg__read__h853851 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h913563 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h913624 : + result__h913619 : 12'd4095 ; - assign wordIdx__h263159 = + assign wordIdx__h263157 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h998359 = + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h998354 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1005944 = pointer__h1005920 >> csrf_rg_dpc[33:28] ; - assign x__h1007669 = { 1'b0, csrf_spp_reg } ; - assign x__h1011445 = + assign x__h1005939 = pointer__h1005915 >> csrf_rg_dpc[33:28] ; + assign x__h1007664 = { 1'b0, csrf_spp_reg } ; + assign x__h1011440 = NOT_rob_deqPort_0_canDeq__3171_3172_OR_rob_deq_ETC___d23391 ? - y_avValue_snd_snd_snd_fst__h1011267 : + y_avValue_snd_snd_snd_fst__h1011262 : IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 ; - assign x__h1025256 = pointer__h1025233 >> csrf_rg_dpc[33:28] ; - assign x__h127272 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127310 ; - assign x__h127310 = { tmp_expTopHalf__h127263, tmp_expBotHalf__h127265 } ; - assign x__h127470 = { impliedTopBits__h127403, topBits__h127399 } ; - assign x__h127487 = x__h127490[13:12] + carry_out__h127401 ; - assign x__h127490 = + assign x__h1025250 = pointer__h1025227 >> csrf_rg_dpc[33:28] ; + assign x__h127271 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127309 ; + assign x__h127309 = { tmp_expTopHalf__h127262, tmp_expBotHalf__h127264 } ; + assign x__h127469 = { impliedTopBits__h127402, topBits__h127398 } ; + assign x__h127486 = x__h127489[13:12] + carry_out__h127400 ; + assign x__h127489 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[77:67], 3'd0 } : - b_base__h127497 ; - assign x__h140188 = mmio_dataRespQ_data_0[63:0] >> x__h140226 ; - assign x__h140226 = { tmp_expTopHalf__h140179, tmp_expBotHalf__h140181 } ; - assign x__h140386 = { impliedTopBits__h140319, topBits__h140315 } ; - assign x__h140403 = x__h140406[13:12] + carry_out__h140317 ; - assign x__h140406 = + b_base__h127496 ; + assign x__h140187 = mmio_dataRespQ_data_0[63:0] >> x__h140225 ; + assign x__h140225 = { tmp_expTopHalf__h140178, tmp_expBotHalf__h140180 } ; + assign x__h140385 = { impliedTopBits__h140318, topBits__h140314 } ; + assign x__h140402 = x__h140405[13:12] + carry_out__h140316 ; + assign x__h140405 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? { mmio_dataRespQ_data_0[77:67], 3'd0 } : - b_base__h140413 ; - assign x__h148960 = + b_base__h140412 ; + assign x__h148959 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; - assign x__h152094 = { 3'd0, sbIdx__h151985 } ; - assign x__h183367 = + assign x__h152093 = { 3'd0, sbIdx__h151984 } ; + assign x__h183366 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 } ; - assign x__h183449 = x__h183367[63:0] >> x__h183487 ; - assign x__h183487 = { tmp_expTopHalf__h183440, tmp_expBotHalf__h183442 } ; - assign x__h183647 = { impliedTopBits__h183580, topBits__h183576 } ; - assign x__h183664 = x__h183667[13:12] + carry_out__h183578 ; - assign x__h183667 = - INV_x83367_BITS_108_TO_90__q33[0] ? - { x__h183367[77:67], 3'd0 } : - b_base__h183674 ; - assign x__h199219 = + assign x__h183448 = x__h183366[63:0] >> x__h183486 ; + assign x__h183486 = { tmp_expTopHalf__h183439, tmp_expBotHalf__h183441 } ; + assign x__h183646 = { impliedTopBits__h183579, topBits__h183575 } ; + assign x__h183663 = x__h183666[13:12] + carry_out__h183577 ; + assign x__h183666 = + INV_x83366_BITS_108_TO_90__q33[0] ? + { x__h183366[77:67], 3'd0 } : + b_base__h183673 ; + assign x__h199218 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 } ; - assign x__h202200 = x__h199219[63:0] >> x__h202238 ; - assign x__h202238 = { tmp_expTopHalf__h202191, tmp_expBotHalf__h202193 } ; - assign x__h202398 = { impliedTopBits__h202331, topBits__h202327 } ; - assign x__h202415 = x__h202418[13:12] + carry_out__h202329 ; - assign x__h202418 = - INV_x99219_BITS_108_TO_90__q35[0] ? - { x__h199219[77:67], 3'd0 } : - b_base__h202425 ; - assign x__h216766 = coreFix_memExe_lsq$respLd[63:0] >> x__h216804 ; - assign x__h216804 = { tmp_expTopHalf__h216757, tmp_expBotHalf__h216759 } ; - assign x__h216964 = { impliedTopBits__h216897, topBits__h216893 } ; - assign x__h216981 = x__h216984[13:12] + carry_out__h216895 ; - assign x__h216984 = + assign x__h202199 = x__h199218[63:0] >> x__h202237 ; + assign x__h202237 = { tmp_expTopHalf__h202190, tmp_expBotHalf__h202192 } ; + assign x__h202397 = { impliedTopBits__h202330, topBits__h202326 } ; + assign x__h202414 = x__h202417[13:12] + carry_out__h202328 ; + assign x__h202417 = + INV_x99218_BITS_108_TO_90__q35[0] ? + { x__h199218[77:67], 3'd0 } : + b_base__h202424 ; + assign x__h216765 = coreFix_memExe_lsq$respLd[63:0] >> x__h216803 ; + assign x__h216803 = { tmp_expTopHalf__h216756, tmp_expBotHalf__h216758 } ; + assign x__h216963 = { impliedTopBits__h216896, topBits__h216892 } ; + assign x__h216980 = x__h216983[13:12] + carry_out__h216894 ; + assign x__h216983 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h216991 ; - assign x__h235690 = + b_base__h216990 ; + assign x__h235689 = (coreFix_memExe_dispToRegQ$first[109] && coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3036 : 66'd0 ; - assign x__h239653 = x__h239655 << coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h239655 = { {48{offset__h239641[15]}}, offset__h239641 } ; - assign x__h239763 = + assign x__h239652 = x__h239654 << coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h239654 = { {48{offset__h239640[15]}}, offset__h239640 } ; + assign x__h239762 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h239911 = + assign x__h239910 = coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705 ? - result__h240541 : - ret__h239918 ; - assign x__h240013 = + result__h240540 : + ret__h239917 ; + assign x__h240012 = { coreFix_memExe_regToExeQ$first[224:223], coreFix_memExe_regToExeQ$first[258:245] } ; - assign x__h240082 = + assign x__h240081 = (coreFix_memExe_regToExeQ$first[264:259] == 6'd50) ? coreFix_memExe_regToExeQ$first[244] : coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3[49] ; - assign x__h240810 = x__h240812 << coreFix_memExe_regToExeQ$first[101:96] ; - assign x__h240812 = { {48{offset__h240798[15]}}, offset__h240798 } ; - assign x__h240920 = + assign x__h240809 = x__h240811 << coreFix_memExe_regToExeQ$first[101:96] ; + assign x__h240811 = { {48{offset__h240797[15]}}, offset__h240797 } ; + assign x__h240919 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign x__h241068 = + assign x__h241067 = coreFix_memExe_regToExeQ_first__633_BITS_101_T_ETC___d3767 ? - result__h241698 : - ret__h241075 ; - assign x__h241170 = + result__h241697 : + ret__h241074 ; + assign x__h241169 = { coreFix_memExe_regToExeQ$first[61:60], coreFix_memExe_regToExeQ$first[95:82] } ; - assign x__h241239 = + assign x__h241238 = (coreFix_memExe_regToExeQ$first[101:96] == 6'd50) ? coreFix_memExe_regToExeQ$first[81] : coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q5[49] ; - assign x__h242605 = offset__h242559[63:14] ^ signBits__h242575 ; - assign x__h242708 = - offset__h242559 >> coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h244610 = { pointer__h242569[3:0], 3'b0 } ; - assign x__h248052 = - pointer__h242569 >> coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h249407 = x__h249419 + y__h249420 ; - assign x__h249419 = x__h249431 + y__h249432 ; - assign x__h249431 = x__h249443 + y__h249444 ; - assign x__h249443 = x__h249455 + y__h249456 ; - assign x__h249455 = x__h249467 + y__h249468 ; - assign x__h249467 = x__h249479 + y__h249480 ; - assign x__h249479 = x__h249491 + y__h249492 ; - assign x__h249491 = x__h249503 + y__h249504 ; - assign x__h249503 = x__h249515 + y__h249516 ; - assign x__h249515 = x__h249527 + y__h249528 ; - assign x__h249527 = x__h249539 + y__h249540 ; - assign x__h249539 = x__h249551 + y__h249552 ; - assign x__h249551 = x__h249563 + y__h249564 ; - assign x__h249563 = x__h249575 + y__h249576 ; - assign x__h249575 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h254419 = x__h254421 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254421 = { {48{offset__h254407[15]}}, offset__h254407 } ; - assign x__h254529 = + assign x__h242604 = offset__h242558[63:14] ^ signBits__h242574 ; + assign x__h242707 = + offset__h242558 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h244608 = { pointer__h242568[3:0], 3'b0 } ; + assign x__h248050 = + pointer__h242568 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h249405 = x__h249417 + y__h249418 ; + assign x__h249417 = x__h249429 + y__h249430 ; + assign x__h249429 = x__h249441 + y__h249442 ; + assign x__h249441 = x__h249453 + y__h249454 ; + assign x__h249453 = x__h249465 + y__h249466 ; + assign x__h249465 = x__h249477 + y__h249478 ; + assign x__h249477 = x__h249489 + y__h249490 ; + assign x__h249489 = x__h249501 + y__h249502 ; + assign x__h249501 = x__h249513 + y__h249514 ; + assign x__h249513 = x__h249525 + y__h249526 ; + assign x__h249525 = x__h249537 + y__h249538 ; + assign x__h249537 = x__h249549 + y__h249550 ; + assign x__h249549 = x__h249561 + y__h249562 ; + assign x__h249561 = x__h249573 + y__h249574 ; + assign x__h249573 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h254417 = x__h254419 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254419 = { {48{offset__h254405[15]}}, offset__h254405 } ; + assign x__h254527 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254677 = + assign x__h254675 = coreFix_memExe_dTlb_procResp__239_BITS_334_TO__ETC___d4402 ? - result__h255307 : - ret__h254684 ; - assign x__h254779 = + result__h255305 : + ret__h254682 ; + assign x__h254777 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h254848 = + assign x__h254846 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h521603 = + assign x__h521599 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h568180 = - { (_theResult___exp__h611512 != 8'd255 || - _theResult___sfd__h611513 == 23'd0) && + assign x__h568177 = + { (_theResult___exp__h611509 != 8'd255 || + _theResult___sfd__h611510 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9245, - out_f_exp__h611789, - out_f_sfd__h611790 } ; - assign x__h594730 = - sfd__h568776 << (x__h594763[11] ? 12'hAAA : x__h594763) ; - assign x__h594763 = + out_f_exp__h611786, + out_f_sfd__h611787 } ; + assign x__h594727 = + sfd__h568773 << (x__h594760[11] ? 12'hAAA : x__h594760) ; + assign x__h594760 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659 ; - assign x__h613934 = - { (_theResult___exp__h657261 != 8'd255 || - _theResult___sfd__h657262 == 23'd0) && + assign x__h613931 = + { (_theResult___exp__h657258 != 8'd255 || + _theResult___sfd__h657259 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10642, - out_f_exp__h657538, - out_f_sfd__h657539 } ; - assign x__h640479 = - sfd__h614530 << (x__h640512[11] ? 12'hAAA : x__h640512) ; - assign x__h640512 = + out_f_exp__h657535, + out_f_sfd__h657536 } ; + assign x__h640476 = + sfd__h614527 << (x__h640509[11] ? 12'hAAA : x__h640509) ; + assign x__h640509 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056 ; assign x__h65608 = mmio_pRqQ_data_0[31:0] ; - assign x__h659681 = - { (_theResult___exp__h703008 != 8'd255 || - _theResult___sfd__h703009 == 23'd0) && + assign x__h659678 = + { (_theResult___exp__h703005 != 8'd255 || + _theResult___sfd__h703006 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12039, - out_f_exp__h703285, - out_f_sfd__h703286 } ; - assign x__h686226 = - sfd__h660277 << (x__h686259[11] ? 12'hAAA : x__h686259) ; - assign x__h686259 = + out_f_exp__h703282, + out_f_sfd__h703283 } ; + assign x__h686223 = + sfd__h660274 << (x__h686256[11] ? 12'hAAA : x__h686256) ; + assign x__h686256 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453 ; - assign x__h714355 = + assign x__h714352 = sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1[149:86] : - y_avValue__h710401 ; - assign x__h714356 = + y_avValue__h710398 ; + assign x__h714353 = sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2[149:86] : - y_avValue__h711034 ; - assign x__h714357 = + y_avValue__h711031 ; + assign x__h714354 = sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3[149:86] : - y_avValue__h711661 ; - assign x__h736262 = sfd__h715187 << x__h736295 ; - assign x__h736295 = + y_avValue__h711658 ; + assign x__h736259 = sfd__h715184 << x__h736292 ; + assign x__h736292 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ; - assign x__h775115 = sfd__h754181 << x__h775148 ; - assign x__h775148 = + assign x__h775112 = sfd__h754178 << x__h775145 ; + assign x__h775145 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ; - assign x__h814419 = sfd__h793485 << x__h814452 ; - assign x__h814452 = + assign x__h814416 = sfd__h793482 << x__h814449 ; + assign x__h814449 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ; - assign x__h836069 = a__h835633[63] ^ b__h835634[63] ; - assign x__h852690 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h865674 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h865712 ; - assign x__h865712 = { tmp_expTopHalf__h865664, tmp_expBotHalf__h865666 } ; - assign x__h865885 = { impliedTopBits__h865817, topBits__h865813 } ; - assign x__h865902 = x__h865905[13:12] + carry_out__h865815 ; - assign x__h865905 = + assign x__h836066 = a__h835630[63] ^ b__h835631[63] ; + assign x__h852687 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h865671 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h865709 ; + assign x__h865709 = { tmp_expTopHalf__h865661, tmp_expBotHalf__h865663 } ; + assign x__h865882 = { impliedTopBits__h865814, topBits__h865810 } ; + assign x__h865899 = x__h865902[13:12] + carry_out__h865812 ; + assign x__h865902 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h865912 ; - assign x__h866222 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h866260 ; - assign x__h866260 = { tmp_expTopHalf__h866212, tmp_expBotHalf__h866214 } ; - assign x__h866433 = { impliedTopBits__h866365, topBits__h866361 } ; - assign x__h866450 = x__h866453[13:12] + carry_out__h866363 ; - assign x__h866453 = + b_base__h865909 ; + assign x__h866219 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h866257 ; + assign x__h866257 = { tmp_expTopHalf__h866209, tmp_expBotHalf__h866211 } ; + assign x__h866430 = { impliedTopBits__h866362, topBits__h866358 } ; + assign x__h866447 = x__h866450[13:12] + carry_out__h866360 ; + assign x__h866450 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h866460 ; - assign x__h878730 = + b_base__h866457 ; + assign x__h878726 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -37459,28 +37459,28 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17857[2], IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17857[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h894478 = + assign x__h894474 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23, 5'd3 } ; - assign x__h904296 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h904334 ; - assign x__h904334 = { tmp_expTopHalf__h904286, tmp_expBotHalf__h904288 } ; - assign x__h904507 = { impliedTopBits__h904439, topBits__h904435 } ; - assign x__h904524 = x__h904527[13:12] + carry_out__h904437 ; - assign x__h904527 = + assign x__h904292 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h904330 ; + assign x__h904330 = { tmp_expTopHalf__h904282, tmp_expBotHalf__h904284 } ; + assign x__h904503 = { impliedTopBits__h904435, topBits__h904431 } ; + assign x__h904520 = x__h904523[13:12] + carry_out__h904433 ; + assign x__h904523 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h904534 ; - assign x__h904844 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h904882 ; - assign x__h904882 = { tmp_expTopHalf__h904834, tmp_expBotHalf__h904836 } ; - assign x__h905055 = { impliedTopBits__h904987, topBits__h904983 } ; - assign x__h905072 = x__h905075[13:12] + carry_out__h904985 ; - assign x__h905075 = + b_base__h904530 ; + assign x__h904840 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h904878 ; + assign x__h904878 = { tmp_expTopHalf__h904830, tmp_expBotHalf__h904832 } ; + assign x__h905051 = { impliedTopBits__h904983, topBits__h904979 } ; + assign x__h905068 = x__h905071[13:12] + carry_out__h904981 ; + assign x__h905071 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h905082 ; - assign x__h912383 = + b_base__h905078 ; + assign x__h912378 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -37492,38 +37492,38 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19935[2], IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19935[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h913572 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h913623 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h992383 = commitStage_commitTrap[172:109] >> x__h992421 ; - assign x__h992421 = { tmp_expTopHalf__h992374, tmp_expBotHalf__h992376 } ; - assign x__h992581 = { impliedTopBits__h992514, topBits__h992510 } ; - assign x__h992598 = x__h992601[13:12] + carry_out__h992512 ; - assign x__h992601 = + assign x__h913567 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h913618 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h992378 = commitStage_commitTrap[172:109] >> x__h992416 ; + assign x__h992416 = { tmp_expTopHalf__h992369, tmp_expBotHalf__h992371 } ; + assign x__h992576 = { impliedTopBits__h992509, topBits__h992505 } ; + assign x__h992593 = x__h992596[13:12] + carry_out__h992507 ; + assign x__h992596 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h992608 ; - assign x__h995059 = - x__h995061 << + b_base__h992603 ; + assign x__h995054 = + x__h995056 << IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351 ; - assign x__h995061 = { {48{offset__h995047[15]}}, offset__h995047 } ; - assign x__h995146 = + assign x__h995056 = { {48{offset__h995042[15]}}, offset__h995042 } ; + assign x__h995141 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351 ; - assign x__h996333 = + assign x__h996328 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q24 } ; - assign x__h997033 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h997059 = { cause_code__h992792, 2'b0 } ; - assign x__h997160 = address__h996966 >> csrf_stcc_reg[33:28] ; - assign x__h997464 = address__h997310 >> csrf_stcc_reg[33:28] ; - assign x__h997690 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h997817 = address__h997623 >> csrf_mtcc_reg[33:28] ; - assign x__h998121 = address__h997967 >> csrf_mtcc_reg[33:28] ; - assign x__h998356 = + assign x__h997028 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h997054 = { cause_code__h992787, 2'b0 } ; + assign x__h997155 = address__h996961 >> csrf_stcc_reg[33:28] ; + assign x__h997459 = address__h997305 >> csrf_stcc_reg[33:28] ; + assign x__h997685 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h997812 = address__h997618 >> csrf_mtcc_reg[33:28] ; + assign x__h998116 = address__h997962 >> csrf_mtcc_reg[33:28] ; + assign x__h998351 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h998377 = + assign x__h998372 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; @@ -37535,7 +37535,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h535302 = + assign x_addr__h535298 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -37543,49 +37543,49 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h923974 = csrf_frm_reg ; - assign x_quotient__h705674 = + assign x_decodeInfo_frm__h923969 = csrf_frm_reg ; + assign x_quotient__h705671 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h706385 : + q___1__h706382 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h849177 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h705675 = + assign x_reg_ifc__read__h849174 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h705672 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h706411 : + r___1__h706408 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h1011220 = + assign y__h1011215 = NOT_rob_deqPort_0_canDeq__3171_3172_OR_rob_deq_ETC___d23391 ? - y_avValue_snd_snd_snd_snd_snd__h1011273 : + y_avValue_snd_snd_snd_snd_snd__h1011268 : IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 ; - assign y__h239762 = ~x__h239763 ; - assign y__h240919 = ~x__h240920 ; - assign y__h249408 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h249420 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h249432 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h249444 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h249456 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h249468 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h249480 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h249492 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h249504 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h249516 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h249528 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h249540 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h249552 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h249564 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h249576 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h254528 = ~x__h254529 ; - assign y__h422493 = + assign y__h239761 = ~x__h239762 ; + assign y__h240918 = ~x__h240919 ; + assign y__h249406 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h249418 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h249430 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h249442 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h249454 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h249466 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h249478 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h249490 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h249502 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h249514 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h249526 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h249538 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h249550 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h249562 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h249574 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h254526 = ~x__h254527 ; + assign y__h422490 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[168:164] } ; - assign y__h913602 = ~x__h913572 ; - assign y__h918532 = + assign y__h913597 = ~x__h913567 ; + assign y__h918527 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -37594,23 +37594,23 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h971319 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h995145 = ~x__h995146 ; - assign y__h997089 = { mask__h996972[62:0], 1'd0 } ; - assign y__h997746 = { mask__h997629[62:0], 1'd0 } ; - assign y_avValue__h710401 = + assign y__h971314 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h995140 = ~x__h995141 ; + assign y__h997084 = { mask__h996967[62:0], 1'd0 } ; + assign y__h997741 = { mask__h997624[62:0], 1'd0 } ; + assign y_avValue__h710398 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12363 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12468 ; - assign y_avValue__h711034 = + assign y_avValue__h711031 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12390 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12480 ; - assign y_avValue__h711661 = + assign y_avValue__h711658 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12414 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12492 ; - assign y_avValue_snd_fst__h1010675 = + assign y_avValue_snd_fst__h1010670 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -37625,7 +37625,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1011257 = + assign y_avValue_snd_fst__h1011252 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -37639,25 +37639,25 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 : - y_avValue_snd_fst__h1011286 ; - assign y_avValue_snd_fst__h1011286 = + y_avValue_snd_fst__h1011281 ; + assign y_avValue_snd_fst__h1011281 = IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h960972 = + assign y_avValue_snd_fst__h960967 = ((fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__0933_AND__ETC___d20962) ? - y_avValue_snd_fst__h961014 : + y_avValue_snd_fst__h961009 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h961014 = + assign y_avValue_snd_fst__h961009 = IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d21004 ? - y_avValue_snd_fst__h961056 : + y_avValue_snd_fst__h961051 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h961056 = + assign y_avValue_snd_fst__h961051 = (fetchStage$pipelines_0_first[267:265] == 3'd1) ? - spec_bits__h971306 : + spec_bits__h971301 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1010685 = + assign y_avValue_snd_snd_snd_fst__h1010680 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -37672,7 +37672,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1011267 = + assign y_avValue_snd_snd_snd_fst__h1011262 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -37686,11 +37686,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 : - y_avValue_snd_snd_snd_fst__h1011296 ; - assign y_avValue_snd_snd_snd_fst__h1011296 = + y_avValue_snd_snd_snd_fst__h1011291 ; + assign y_avValue_snd_snd_snd_fst__h1011291 = IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1010691 = + assign y_avValue_snd_snd_snd_snd_snd__h1010686 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -37705,7 +37705,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1011273 = + assign y_avValue_snd_snd_snd_snd_snd__h1011268 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -37719,8 +37719,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 : - y_avValue_snd_snd_snd_snd_snd__h1011302 ; - assign y_avValue_snd_snd_snd_snd_snd__h1011302 = + y_avValue_snd_snd_snd_snd_snd__h1011297 ; + assign y_avValue_snd_snd_snd_snd_snd__h1011297 = IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -37746,28 +37746,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -37777,10 +37777,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h505543 = + addr__h505540 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h505543 = + addr__h505540 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; endcase end @@ -37789,16 +37789,16 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h212809 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h212809 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h212808 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h212808 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h215095 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h215095 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h215094 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h215094 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -37857,16 +37857,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17; 2'd1: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd2: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd3: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; endcase end @@ -37874,8 +37874,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h992982 = commitStage_commitTrap[35:32]; - default: i__h992982 = 4'd15; + i__h992977 = commitStage_commitTrap[35:32]; + default: i__h992977 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -37948,340 +37948,340 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h508693 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h508690 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h508693 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h508690 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h849047 or - frm_csr__read__h849058 or - fcsr_csr__read__h849072 or - sstatus_csr__read__h849268 or - sie_csr__read__h849338 or - scounteren_csr__read__h849391 or + fflags_csr__read__h849044 or + frm_csr__read__h849055 or + fcsr_csr__read__h849069 or + sstatus_csr__read__h849265 or + sie_csr__read__h849335 or + scounteren_csr__read__h849388 or csrf_sscratch_csr or - scause_csr__read__h849486 or + scause_csr__read__h849483 or csrf_stval_csr or - sip_csr__read__h849626 or - satp_csr__read__h849689 or - mstatus_csr__read__h849835 or - medeleg_csr__read__h849989 or - mideleg_csr__read__h850087 or - mie_csr__read__h850214 or - mcounteren_csr__read__h850309 or + sip_csr__read__h849623 or + satp_csr__read__h849686 or + mstatus_csr__read__h849832 or + medeleg_csr__read__h849986 or + mideleg_csr__read__h850084 or + mie_csr__read__h850211 or + mcounteren_csr__read__h850306 or csrf_mscratch_csr or - mcause_csr__read__h850488 or + mcause_csr__read__h850485 or csrf_mtval_csr or - mip_csr__read__h850727 or + mip_csr__read__h850724 or csrf_rg_tselect or - rg_tdata1__read__h851828 or + rg_tdata1__read__h851825 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849177 or + x_reg_ifc__read__h849174 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h894478 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h894474 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1014871 = fflags_csr__read__h849047; - 12'd2: data_out__h1014871 = frm_csr__read__h849058; - 12'd3: data_out__h1014871 = fcsr_csr__read__h849072; - 12'd256: data_out__h1014871 = sstatus_csr__read__h849268; - 12'd260: data_out__h1014871 = sie_csr__read__h849338; - 12'd262: data_out__h1014871 = scounteren_csr__read__h849391; - 12'd320: data_out__h1014871 = csrf_sscratch_csr; - 12'd322: data_out__h1014871 = scause_csr__read__h849486; - 12'd323: data_out__h1014871 = csrf_stval_csr; - 12'd324: data_out__h1014871 = sip_csr__read__h849626; - 12'd384: data_out__h1014871 = satp_csr__read__h849689; - 12'd768: data_out__h1014871 = mstatus_csr__read__h849835; - 12'd769: data_out__h1014871 = 64'h800000000014112D; - 12'd770: data_out__h1014871 = medeleg_csr__read__h849989; - 12'd771: data_out__h1014871 = mideleg_csr__read__h850087; - 12'd772: data_out__h1014871 = mie_csr__read__h850214; - 12'd774: data_out__h1014871 = mcounteren_csr__read__h850309; - 12'd832: data_out__h1014871 = csrf_mscratch_csr; - 12'd834: data_out__h1014871 = mcause_csr__read__h850488; - 12'd835: data_out__h1014871 = csrf_mtval_csr; - 12'd836: data_out__h1014871 = mip_csr__read__h850727; - 12'd1952: data_out__h1014871 = csrf_rg_tselect; - 12'd1953: data_out__h1014871 = rg_tdata1__read__h851828; - 12'd1954: data_out__h1014871 = csrf_rg_tdata2; - 12'd1955: data_out__h1014871 = csrf_rg_tdata3; - 12'd1968: data_out__h1014871 = csrf_rg_dcsr; - 12'd1969: data_out__h1014871 = csrf_rg_dpc[149:86]; - 12'd1970: data_out__h1014871 = csrf_rg_dscratch0; - 12'd1971: data_out__h1014871 = csrf_rg_dscratch1; + 12'd1: data_out__h1014865 = fflags_csr__read__h849044; + 12'd2: data_out__h1014865 = frm_csr__read__h849055; + 12'd3: data_out__h1014865 = fcsr_csr__read__h849069; + 12'd256: data_out__h1014865 = sstatus_csr__read__h849265; + 12'd260: data_out__h1014865 = sie_csr__read__h849335; + 12'd262: data_out__h1014865 = scounteren_csr__read__h849388; + 12'd320: data_out__h1014865 = csrf_sscratch_csr; + 12'd322: data_out__h1014865 = scause_csr__read__h849483; + 12'd323: data_out__h1014865 = csrf_stval_csr; + 12'd324: data_out__h1014865 = sip_csr__read__h849623; + 12'd384: data_out__h1014865 = satp_csr__read__h849686; + 12'd768: data_out__h1014865 = mstatus_csr__read__h849832; + 12'd769: data_out__h1014865 = 64'h800000000014112D; + 12'd770: data_out__h1014865 = medeleg_csr__read__h849986; + 12'd771: data_out__h1014865 = mideleg_csr__read__h850084; + 12'd772: data_out__h1014865 = mie_csr__read__h850211; + 12'd774: data_out__h1014865 = mcounteren_csr__read__h850306; + 12'd832: data_out__h1014865 = csrf_mscratch_csr; + 12'd834: data_out__h1014865 = mcause_csr__read__h850485; + 12'd835: data_out__h1014865 = csrf_mtval_csr; + 12'd836: data_out__h1014865 = mip_csr__read__h850724; + 12'd1952: data_out__h1014865 = csrf_rg_tselect; + 12'd1953: data_out__h1014865 = rg_tdata1__read__h851825; + 12'd1954: data_out__h1014865 = csrf_rg_tdata2; + 12'd1955: data_out__h1014865 = csrf_rg_tdata3; + 12'd1968: data_out__h1014865 = csrf_rg_dcsr; + 12'd1969: data_out__h1014865 = csrf_rg_dpc[149:86]; + 12'd1970: data_out__h1014865 = csrf_rg_dscratch0; + 12'd1971: data_out__h1014865 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1014871 = 64'd0; - 12'd2049: data_out__h1014871 = x_reg_ifc__read__h849177; - 12'd2816, 12'd3072: data_out__h1014871 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1014871 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1014871 = { 48'd0, x__h894478 }; - 12'd3073: data_out__h1014871 = csrf_time_reg; - default: data_out__h1014871 = 64'b0; + data_out__h1014865 = 64'd0; + 12'd2049: data_out__h1014865 = x_reg_ifc__read__h849174; + 12'd2816, 12'd3072: data_out__h1014865 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1014865 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1014865 = { 48'd0, x__h894474 }; + 12'd3073: data_out__h1014865 = csrf_time_reg; + default: data_out__h1014865 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h849047 or - frm_csr__read__h849058 or - fcsr_csr__read__h849072 or - sstatus_csr__read__h849268 or - sie_csr__read__h849338 or - scounteren_csr__read__h849391 or + fflags_csr__read__h849044 or + frm_csr__read__h849055 or + fcsr_csr__read__h849069 or + sstatus_csr__read__h849265 or + sie_csr__read__h849335 or + scounteren_csr__read__h849388 or csrf_sscratch_csr or - scause_csr__read__h849486 or + scause_csr__read__h849483 or csrf_stval_csr or - sip_csr__read__h849626 or - satp_csr__read__h849689 or - mstatus_csr__read__h849835 or - medeleg_csr__read__h849989 or - mideleg_csr__read__h850087 or - mie_csr__read__h850214 or - mcounteren_csr__read__h850309 or + sip_csr__read__h849623 or + satp_csr__read__h849686 or + mstatus_csr__read__h849832 or + medeleg_csr__read__h849986 or + mideleg_csr__read__h850084 or + mie_csr__read__h850211 or + mcounteren_csr__read__h850306 or csrf_mscratch_csr or - mcause_csr__read__h850488 or + mcause_csr__read__h850485 or csrf_mtval_csr or - mip_csr__read__h850727 or + mip_csr__read__h850724 or csrf_rg_tselect or - rg_tdata1__read__h851828 or + rg_tdata1__read__h851825 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849177 or + x_reg_ifc__read__h849174 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h894478 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h894474 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h843840 = fflags_csr__read__h849047; - 12'd2: addr__h843840 = frm_csr__read__h849058; - 12'd3: addr__h843840 = fcsr_csr__read__h849072; - 12'd256: addr__h843840 = sstatus_csr__read__h849268; - 12'd260: addr__h843840 = sie_csr__read__h849338; - 12'd262: addr__h843840 = scounteren_csr__read__h849391; - 12'd320: addr__h843840 = csrf_sscratch_csr; - 12'd322: addr__h843840 = scause_csr__read__h849486; - 12'd323: addr__h843840 = csrf_stval_csr; - 12'd324: addr__h843840 = sip_csr__read__h849626; - 12'd384: addr__h843840 = satp_csr__read__h849689; - 12'd768: addr__h843840 = mstatus_csr__read__h849835; - 12'd769: addr__h843840 = 64'h800000000014112D; - 12'd770: addr__h843840 = medeleg_csr__read__h849989; - 12'd771: addr__h843840 = mideleg_csr__read__h850087; - 12'd772: addr__h843840 = mie_csr__read__h850214; - 12'd774: addr__h843840 = mcounteren_csr__read__h850309; - 12'd832: addr__h843840 = csrf_mscratch_csr; - 12'd834: addr__h843840 = mcause_csr__read__h850488; - 12'd835: addr__h843840 = csrf_mtval_csr; - 12'd836: addr__h843840 = mip_csr__read__h850727; - 12'd1952: addr__h843840 = csrf_rg_tselect; - 12'd1953: addr__h843840 = rg_tdata1__read__h851828; - 12'd1954: addr__h843840 = csrf_rg_tdata2; - 12'd1955: addr__h843840 = csrf_rg_tdata3; - 12'd1968: addr__h843840 = csrf_rg_dcsr; - 12'd1969: addr__h843840 = csrf_rg_dpc[149:86]; - 12'd1970: addr__h843840 = csrf_rg_dscratch0; - 12'd1971: addr__h843840 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843840 = 64'd0; - 12'd2049: addr__h843840 = x_reg_ifc__read__h849177; - 12'd2816, 12'd3072: addr__h843840 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h843840 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h843840 = { 48'd0, x__h894478 }; - 12'd3073: addr__h843840 = csrf_time_reg; - default: addr__h843840 = 64'b0; + 12'd1: addr__h843837 = fflags_csr__read__h849044; + 12'd2: addr__h843837 = frm_csr__read__h849055; + 12'd3: addr__h843837 = fcsr_csr__read__h849069; + 12'd256: addr__h843837 = sstatus_csr__read__h849265; + 12'd260: addr__h843837 = sie_csr__read__h849335; + 12'd262: addr__h843837 = scounteren_csr__read__h849388; + 12'd320: addr__h843837 = csrf_sscratch_csr; + 12'd322: addr__h843837 = scause_csr__read__h849483; + 12'd323: addr__h843837 = csrf_stval_csr; + 12'd324: addr__h843837 = sip_csr__read__h849623; + 12'd384: addr__h843837 = satp_csr__read__h849686; + 12'd768: addr__h843837 = mstatus_csr__read__h849832; + 12'd769: addr__h843837 = 64'h800000000014112D; + 12'd770: addr__h843837 = medeleg_csr__read__h849986; + 12'd771: addr__h843837 = mideleg_csr__read__h850084; + 12'd772: addr__h843837 = mie_csr__read__h850211; + 12'd774: addr__h843837 = mcounteren_csr__read__h850306; + 12'd832: addr__h843837 = csrf_mscratch_csr; + 12'd834: addr__h843837 = mcause_csr__read__h850485; + 12'd835: addr__h843837 = csrf_mtval_csr; + 12'd836: addr__h843837 = mip_csr__read__h850724; + 12'd1952: addr__h843837 = csrf_rg_tselect; + 12'd1953: addr__h843837 = rg_tdata1__read__h851825; + 12'd1954: addr__h843837 = csrf_rg_tdata2; + 12'd1955: addr__h843837 = csrf_rg_tdata3; + 12'd1968: addr__h843837 = csrf_rg_dcsr; + 12'd1969: addr__h843837 = csrf_rg_dpc[149:86]; + 12'd1970: addr__h843837 = csrf_rg_dscratch0; + 12'd1971: addr__h843837 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843837 = 64'd0; + 12'd2049: addr__h843837 = x_reg_ifc__read__h849174; + 12'd2816, 12'd3072: addr__h843837 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h843837 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h843837 = { 48'd0, x__h894474 }; + 12'd3073: addr__h843837 = csrf_time_reg; + default: addr__h843837 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h849047 or - frm_csr__read__h849058 or - fcsr_csr__read__h849072 or - sstatus_csr__read__h849268 or - sie_csr__read__h849338 or - scounteren_csr__read__h849391 or + fflags_csr__read__h849044 or + frm_csr__read__h849055 or + fcsr_csr__read__h849069 or + sstatus_csr__read__h849265 or + sie_csr__read__h849335 or + scounteren_csr__read__h849388 or csrf_sscratch_csr or - scause_csr__read__h849486 or + scause_csr__read__h849483 or csrf_stval_csr or - sip_csr__read__h849626 or - satp_csr__read__h849689 or - mstatus_csr__read__h849835 or - medeleg_csr__read__h849989 or - mideleg_csr__read__h850087 or - mie_csr__read__h850214 or - mcounteren_csr__read__h850309 or + sip_csr__read__h849623 or + satp_csr__read__h849686 or + mstatus_csr__read__h849832 or + medeleg_csr__read__h849986 or + mideleg_csr__read__h850084 or + mie_csr__read__h850211 or + mcounteren_csr__read__h850306 or csrf_mscratch_csr or - mcause_csr__read__h850488 or + mcause_csr__read__h850485 or csrf_mtval_csr or - mip_csr__read__h850727 or + mip_csr__read__h850724 or csrf_rg_tselect or - rg_tdata1__read__h851828 or + rg_tdata1__read__h851825 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849177 or + x_reg_ifc__read__h849174 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h894478 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h894474 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h886249 = fflags_csr__read__h849047; - 12'd2: addr__h886249 = frm_csr__read__h849058; - 12'd3: addr__h886249 = fcsr_csr__read__h849072; - 12'd256: addr__h886249 = sstatus_csr__read__h849268; - 12'd260: addr__h886249 = sie_csr__read__h849338; - 12'd262: addr__h886249 = scounteren_csr__read__h849391; - 12'd320: addr__h886249 = csrf_sscratch_csr; - 12'd322: addr__h886249 = scause_csr__read__h849486; - 12'd323: addr__h886249 = csrf_stval_csr; - 12'd324: addr__h886249 = sip_csr__read__h849626; - 12'd384: addr__h886249 = satp_csr__read__h849689; - 12'd768: addr__h886249 = mstatus_csr__read__h849835; - 12'd769: addr__h886249 = 64'h800000000014112D; - 12'd770: addr__h886249 = medeleg_csr__read__h849989; - 12'd771: addr__h886249 = mideleg_csr__read__h850087; - 12'd772: addr__h886249 = mie_csr__read__h850214; - 12'd774: addr__h886249 = mcounteren_csr__read__h850309; - 12'd832: addr__h886249 = csrf_mscratch_csr; - 12'd834: addr__h886249 = mcause_csr__read__h850488; - 12'd835: addr__h886249 = csrf_mtval_csr; - 12'd836: addr__h886249 = mip_csr__read__h850727; - 12'd1952: addr__h886249 = csrf_rg_tselect; - 12'd1953: addr__h886249 = rg_tdata1__read__h851828; - 12'd1954: addr__h886249 = csrf_rg_tdata2; - 12'd1955: addr__h886249 = csrf_rg_tdata3; - 12'd1968: addr__h886249 = csrf_rg_dcsr; - 12'd1969: addr__h886249 = csrf_rg_dpc[149:86]; - 12'd1970: addr__h886249 = csrf_rg_dscratch0; - 12'd1971: addr__h886249 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h886249 = 64'd0; - 12'd2049: addr__h886249 = x_reg_ifc__read__h849177; - 12'd2816, 12'd3072: addr__h886249 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h886249 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h886249 = { 48'd0, x__h894478 }; - 12'd3073: addr__h886249 = csrf_time_reg; - default: addr__h886249 = 64'b0; + 12'd1: addr__h886245 = fflags_csr__read__h849044; + 12'd2: addr__h886245 = frm_csr__read__h849055; + 12'd3: addr__h886245 = fcsr_csr__read__h849069; + 12'd256: addr__h886245 = sstatus_csr__read__h849265; + 12'd260: addr__h886245 = sie_csr__read__h849335; + 12'd262: addr__h886245 = scounteren_csr__read__h849388; + 12'd320: addr__h886245 = csrf_sscratch_csr; + 12'd322: addr__h886245 = scause_csr__read__h849483; + 12'd323: addr__h886245 = csrf_stval_csr; + 12'd324: addr__h886245 = sip_csr__read__h849623; + 12'd384: addr__h886245 = satp_csr__read__h849686; + 12'd768: addr__h886245 = mstatus_csr__read__h849832; + 12'd769: addr__h886245 = 64'h800000000014112D; + 12'd770: addr__h886245 = medeleg_csr__read__h849986; + 12'd771: addr__h886245 = mideleg_csr__read__h850084; + 12'd772: addr__h886245 = mie_csr__read__h850211; + 12'd774: addr__h886245 = mcounteren_csr__read__h850306; + 12'd832: addr__h886245 = csrf_mscratch_csr; + 12'd834: addr__h886245 = mcause_csr__read__h850485; + 12'd835: addr__h886245 = csrf_mtval_csr; + 12'd836: addr__h886245 = mip_csr__read__h850724; + 12'd1952: addr__h886245 = csrf_rg_tselect; + 12'd1953: addr__h886245 = rg_tdata1__read__h851825; + 12'd1954: addr__h886245 = csrf_rg_tdata2; + 12'd1955: addr__h886245 = csrf_rg_tdata3; + 12'd1968: addr__h886245 = csrf_rg_dcsr; + 12'd1969: addr__h886245 = csrf_rg_dpc[149:86]; + 12'd1970: addr__h886245 = csrf_rg_dscratch0; + 12'd1971: addr__h886245 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h886245 = 64'd0; + 12'd2049: addr__h886245 = x_reg_ifc__read__h849174; + 12'd2816, 12'd3072: addr__h886245 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h886245 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h886245 = { 48'd0, x__h894474 }; + 12'd3073: addr__h886245 = csrf_time_reg; + default: addr__h886245 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h576363 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h576360 = 8'd255; 3'd2: - _theResult___fst_exp__h576363 = + _theResult___fst_exp__h576360 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h576363 = + _theResult___fst_exp__h576360 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h576363 = 8'd254; - default: _theResult___fst_exp__h576363 = 8'd0; + 3'd4: _theResult___fst_exp__h576360 = 8'd254; + default: _theResult___fst_exp__h576360 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h576364 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h576361 = 23'd0; 3'd2: - _theResult___fst_sfd__h576364 = + _theResult___fst_sfd__h576361 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h576364 = + _theResult___fst_sfd__h576361 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h576364 = 23'd8388607; - default: _theResult___fst_sfd__h576364 = 23'd0; + 3'd4: _theResult___fst_sfd__h576361 = 23'd8388607; + default: _theResult___fst_sfd__h576361 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h622114 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h622111 = 8'd255; 3'd2: - _theResult___fst_exp__h622114 = + _theResult___fst_exp__h622111 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h622114 = + _theResult___fst_exp__h622111 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h622114 = 8'd254; - default: _theResult___fst_exp__h622114 = 8'd0; + 3'd4: _theResult___fst_exp__h622111 = 8'd254; + default: _theResult___fst_exp__h622111 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h622115 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h622112 = 23'd0; 3'd2: - _theResult___fst_sfd__h622115 = + _theResult___fst_sfd__h622112 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h622115 = + _theResult___fst_sfd__h622112 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h622115 = 23'd8388607; - default: _theResult___fst_sfd__h622115 = 23'd0; + 3'd4: _theResult___fst_sfd__h622112 = 23'd8388607; + default: _theResult___fst_sfd__h622112 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h667861 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h667858 = 8'd255; 3'd2: - _theResult___fst_exp__h667861 = + _theResult___fst_exp__h667858 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h667861 = + _theResult___fst_exp__h667858 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h667861 = 8'd254; - default: _theResult___fst_exp__h667861 = 8'd0; + 3'd4: _theResult___fst_exp__h667858 = 8'd254; + default: _theResult___fst_exp__h667858 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h667862 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h667859 = 23'd0; 3'd2: - _theResult___fst_sfd__h667862 = + _theResult___fst_sfd__h667859 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h667862 = + _theResult___fst_sfd__h667859 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h667862 = 23'd8388607; - default: _theResult___fst_sfd__h667862 = 23'd0; + 3'd4: _theResult___fst_sfd__h667859 = 23'd8388607; + default: _theResult___fst_sfd__h667859 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -38433,16 +38433,16 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h992808 = commitStage_commitTrap[36:32]; - default: i__h992808 = 5'd28; + i__h992803 = commitStage_commitTrap[36:32]; + default: i__h992803 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h994330 or i__h992808) + always@(commitStage_commitTrap or cause_code__h994325 or i__h992803) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h992792 = 5'd28; - 2'd1: cause_code__h992792 = i__h992808; - default: cause_code__h992792 = cause_code__h994330; + 2'd0: cause_code__h992787 = 5'd28; + 2'd1: cause_code__h992787 = i__h992803; + default: cause_code__h992787 = cause_code__h994325; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -38732,16 +38732,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849[31:0]; 2'd1: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849[63:32]; 2'd2: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843[31:0]; 2'd3: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843[63:32]; endcase end @@ -38905,446 +38905,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[516]; endcase end - always@(guard__h585100 or - _theResult___fst_exp__h593148 or - out_exp__h593593 or _theResult___exp__h593590) + always@(guard__h585097 or + _theResult___fst_exp__h593145 or + out_exp__h593590 or _theResult___exp__h593587) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = - _theResult___fst_exp__h593148; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 = + _theResult___fst_exp__h593145; 2'b10: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = - out_exp__h593593; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 = + out_exp__h593590; 2'b11: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = - _theResult___exp__h593590; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 = + _theResult___exp__h593587; endcase end - always@(guard__h585100 or - _theResult___fst_exp__h593148 or _theResult___exp__h593590) + always@(guard__h585097 or + _theResult___fst_exp__h593145 or _theResult___exp__h593587) begin - case (guard__h585100) + case (guard__h585097) 2'b0: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 = - _theResult___fst_exp__h593148; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44 = + _theResult___fst_exp__h593145; 2'b01, 2'b10, 2'b11: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 = - _theResult___exp__h593590; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44 = + _theResult___exp__h593587; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 or - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 or + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 or + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639 or - _theResult___fst_exp__h593148) + _theResult___fst_exp__h593145) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h593668 = - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43; + _theResult___fst_exp__h593665 = + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43; 3'd1: - _theResult___fst_exp__h593668 = - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44; + _theResult___fst_exp__h593665 = + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44; 3'd2: - _theResult___fst_exp__h593668 = + _theResult___fst_exp__h593665 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637; 3'd3: - _theResult___fst_exp__h593668 = + _theResult___fst_exp__h593665 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639; - 3'd4: _theResult___fst_exp__h593668 = _theResult___fst_exp__h593148; - default: _theResult___fst_exp__h593668 = 8'd0; + 3'd4: _theResult___fst_exp__h593665 = _theResult___fst_exp__h593145; + default: _theResult___fst_exp__h593665 = 8'd0; endcase end - always@(guard__h576391 or - _theResult___fst_exp__h584492 or - out_exp__h585011 or _theResult___exp__h585008) + always@(guard__h576388 or + _theResult___fst_exp__h584489 or + out_exp__h585008 or _theResult___exp__h585005) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = - _theResult___fst_exp__h584492; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 = + _theResult___fst_exp__h584489; 2'b10: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = - out_exp__h585011; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 = + out_exp__h585008; 2'b11: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = - _theResult___exp__h585008; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 = + _theResult___exp__h585005; endcase end - always@(guard__h576391 or - _theResult___fst_exp__h584492 or _theResult___exp__h585008) + always@(guard__h576388 or + _theResult___fst_exp__h584489 or _theResult___exp__h585005) begin - case (guard__h576391) + case (guard__h576388) 2'b0: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 = - _theResult___fst_exp__h584492; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46 = + _theResult___fst_exp__h584489; 2'b01, 2'b10, 2'b11: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 = - _theResult___exp__h585008; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46 = + _theResult___exp__h585005; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 or - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 or + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 or + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418 or - _theResult___fst_exp__h584492) + _theResult___fst_exp__h584489) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h585086 = - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45; + _theResult___fst_exp__h585083 = + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45; 3'd1: - _theResult___fst_exp__h585086 = - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46; + _theResult___fst_exp__h585083 = + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46; 3'd2: - _theResult___fst_exp__h585086 = + _theResult___fst_exp__h585083 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415; 3'd3: - _theResult___fst_exp__h585086 = + _theResult___fst_exp__h585083 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418; - 3'd4: _theResult___fst_exp__h585086 = _theResult___fst_exp__h584492; - default: _theResult___fst_exp__h585086 = 8'd0; + 3'd4: _theResult___fst_exp__h585083 = _theResult___fst_exp__h584489; + default: _theResult___fst_exp__h585083 = 8'd0; endcase end - always@(guard__h594030 or - _theResult___fst_exp__h602258 or - out_exp__h602777 or _theResult___exp__h602774) + always@(guard__h594027 or + _theResult___fst_exp__h602255 or + out_exp__h602774 or _theResult___exp__h602771) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = - _theResult___fst_exp__h602258; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 = + _theResult___fst_exp__h602255; 2'b10: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = - out_exp__h602777; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 = + out_exp__h602774; 2'b11: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = - _theResult___exp__h602774; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 = + _theResult___exp__h602771; endcase end - always@(guard__h594030 or - _theResult___fst_exp__h602258 or _theResult___exp__h602774) + always@(guard__h594027 or + _theResult___fst_exp__h602255 or _theResult___exp__h602771) begin - case (guard__h594030) + case (guard__h594027) 2'b0: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 = - _theResult___fst_exp__h602258; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52 = + _theResult___fst_exp__h602255; 2'b01, 2'b10, 2'b11: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 = - _theResult___exp__h602774; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52 = + _theResult___exp__h602771; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 or - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 or + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 or + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964 or - _theResult___fst_exp__h602258) + _theResult___fst_exp__h602255) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h602852 = - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51; + _theResult___fst_exp__h602849 = + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51; 3'd1: - _theResult___fst_exp__h602852 = - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52; + _theResult___fst_exp__h602849 = + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52; 3'd2: - _theResult___fst_exp__h602852 = + _theResult___fst_exp__h602849 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962; 3'd3: - _theResult___fst_exp__h602852 = + _theResult___fst_exp__h602849 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964; - 3'd4: _theResult___fst_exp__h602852 = _theResult___fst_exp__h602258; - default: _theResult___fst_exp__h602852 = 8'd0; + 3'd4: _theResult___fst_exp__h602849 = _theResult___fst_exp__h602255; + default: _theResult___fst_exp__h602849 = 8'd0; endcase end - always@(guard__h602866 or - _theResult___fst_exp__h610943 or - out_exp__h611413 or _theResult___exp__h611410) + always@(guard__h602863 or + _theResult___fst_exp__h610940 or + out_exp__h611410 or _theResult___exp__h611407) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = - _theResult___fst_exp__h610943; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 = + _theResult___fst_exp__h610940; 2'b10: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = - out_exp__h611413; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 = + out_exp__h611410; 2'b11: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = - _theResult___exp__h611410; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 = + _theResult___exp__h611407; endcase end - always@(guard__h602866 or - _theResult___fst_exp__h610943 or _theResult___exp__h611410) + always@(guard__h602863 or + _theResult___fst_exp__h610940 or _theResult___exp__h611407) begin - case (guard__h602866) + case (guard__h602863) 2'b0: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 = - _theResult___fst_exp__h610943; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57 = + _theResult___fst_exp__h610940; 2'b01, 2'b10, 2'b11: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 = - _theResult___exp__h611410; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57 = + _theResult___exp__h611407; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 or - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 or + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 or + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033 or - _theResult___fst_exp__h610943) + _theResult___fst_exp__h610940) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h611488 = - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56; + _theResult___fst_exp__h611485 = + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56; 3'd1: - _theResult___fst_exp__h611488 = - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57; + _theResult___fst_exp__h611485 = + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57; 3'd2: - _theResult___fst_exp__h611488 = + _theResult___fst_exp__h611485 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031; 3'd3: - _theResult___fst_exp__h611488 = + _theResult___fst_exp__h611485 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033; - 3'd4: _theResult___fst_exp__h611488 = _theResult___fst_exp__h610943; - default: _theResult___fst_exp__h611488 = 8'd0; + 3'd4: _theResult___fst_exp__h611485 = _theResult___fst_exp__h610940; + default: _theResult___fst_exp__h611485 = 8'd0; endcase end - always@(guard__h585100 or - _theResult___snd__h593099 or - out_sfd__h593594 or _theResult___sfd__h593591) + always@(guard__h585097 or + _theResult___snd__h593096 or + out_sfd__h593591 or _theResult___sfd__h593588) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = - _theResult___snd__h593099[56:34]; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 = + _theResult___snd__h593096[56:34]; 2'b10: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = - out_sfd__h593594; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 = + out_sfd__h593591; 2'b11: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = - _theResult___sfd__h593591; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 = + _theResult___sfd__h593588; endcase end - always@(guard__h585100 or - _theResult___snd__h593099 or _theResult___sfd__h593591) + always@(guard__h585097 or + _theResult___snd__h593096 or _theResult___sfd__h593588) begin - case (guard__h585100) + case (guard__h585097) 2'b0: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 = - _theResult___snd__h593099[56:34]; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59 = + _theResult___snd__h593096[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 = - _theResult___sfd__h593591; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59 = + _theResult___sfd__h593588; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 or - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 or + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 or + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083 or - _theResult___snd__h593099) + _theResult___snd__h593096) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h593669 = - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58; + _theResult___fst_sfd__h593666 = + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58; 3'd1: - _theResult___fst_sfd__h593669 = - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59; + _theResult___fst_sfd__h593666 = + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59; 3'd2: - _theResult___fst_sfd__h593669 = + _theResult___fst_sfd__h593666 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081; 3'd3: - _theResult___fst_sfd__h593669 = + _theResult___fst_sfd__h593666 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083; - 3'd4: _theResult___fst_sfd__h593669 = _theResult___snd__h593099[56:34]; - default: _theResult___fst_sfd__h593669 = 23'd0; + 3'd4: _theResult___fst_sfd__h593666 = _theResult___snd__h593096[56:34]; + default: _theResult___fst_sfd__h593666 = 23'd0; endcase end - always@(guard__h576391 or - sfdin__h584486 or out_sfd__h585012 or _theResult___sfd__h585009) + always@(guard__h576388 or + sfdin__h584483 or out_sfd__h585009 or _theResult___sfd__h585006) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = - sfdin__h584486[56:34]; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 = + sfdin__h584483[56:34]; 2'b10: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = - out_sfd__h585012; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 = + out_sfd__h585009; 2'b11: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = - _theResult___sfd__h585009; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 = + _theResult___sfd__h585006; endcase end - always@(guard__h576391 or sfdin__h584486 or _theResult___sfd__h585009) + always@(guard__h576388 or sfdin__h584483 or _theResult___sfd__h585006) begin - case (guard__h576391) + case (guard__h576388) 2'b0: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 = - sfdin__h584486[56:34]; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61 = + sfdin__h584483[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 = - _theResult___sfd__h585009; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61 = + _theResult___sfd__h585006; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 or - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 or + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 or + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064 or - sfdin__h584486) + sfdin__h584483) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h585087 = - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60; + _theResult___fst_sfd__h585084 = + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60; 3'd1: - _theResult___fst_sfd__h585087 = - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61; + _theResult___fst_sfd__h585084 = + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61; 3'd2: - _theResult___fst_sfd__h585087 = + _theResult___fst_sfd__h585084 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062; 3'd3: - _theResult___fst_sfd__h585087 = + _theResult___fst_sfd__h585084 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064; - 3'd4: _theResult___fst_sfd__h585087 = sfdin__h584486[56:34]; - default: _theResult___fst_sfd__h585087 = 23'd0; + 3'd4: _theResult___fst_sfd__h585084 = sfdin__h584483[56:34]; + default: _theResult___fst_sfd__h585084 = 23'd0; endcase end - always@(guard__h594030 or - sfdin__h602252 or out_sfd__h602778 or _theResult___sfd__h602775) + always@(guard__h594027 or + sfdin__h602249 or out_sfd__h602775 or _theResult___sfd__h602772) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = - sfdin__h602252[56:34]; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 = + sfdin__h602249[56:34]; 2'b10: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = - out_sfd__h602778; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 = + out_sfd__h602775; 2'b11: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = - _theResult___sfd__h602775; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 = + _theResult___sfd__h602772; endcase end - always@(guard__h594030 or sfdin__h602252 or _theResult___sfd__h602775) + always@(guard__h594027 or sfdin__h602249 or _theResult___sfd__h602772) begin - case (guard__h594030) + case (guard__h594027) 2'b0: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 = - sfdin__h602252[56:34]; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63 = + sfdin__h602249[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 = - _theResult___sfd__h602775; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63 = + _theResult___sfd__h602772; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 or - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 or + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 or + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110 or - sfdin__h602252) + sfdin__h602249) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h602853 = - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62; + _theResult___fst_sfd__h602850 = + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62; 3'd1: - _theResult___fst_sfd__h602853 = - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63; + _theResult___fst_sfd__h602850 = + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63; 3'd2: - _theResult___fst_sfd__h602853 = + _theResult___fst_sfd__h602850 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108; 3'd3: - _theResult___fst_sfd__h602853 = + _theResult___fst_sfd__h602850 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110; - 3'd4: _theResult___fst_sfd__h602853 = sfdin__h602252[56:34]; - default: _theResult___fst_sfd__h602853 = 23'd0; + 3'd4: _theResult___fst_sfd__h602850 = sfdin__h602249[56:34]; + default: _theResult___fst_sfd__h602850 = 23'd0; endcase end - always@(guard__h602866 or - _theResult___snd__h610889 or - out_sfd__h611414 or _theResult___sfd__h611411) + always@(guard__h602863 or + _theResult___snd__h610886 or + out_sfd__h611411 or _theResult___sfd__h611408) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = - _theResult___snd__h610889[56:34]; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 = + _theResult___snd__h610886[56:34]; 2'b10: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = - out_sfd__h611414; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 = + out_sfd__h611411; 2'b11: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = - _theResult___sfd__h611411; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 = + _theResult___sfd__h611408; endcase end - always@(guard__h602866 or - _theResult___snd__h610889 or _theResult___sfd__h611411) + always@(guard__h602863 or + _theResult___snd__h610886 or _theResult___sfd__h611408) begin - case (guard__h602866) + case (guard__h602863) 2'b0: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 = - _theResult___snd__h610889[56:34]; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65 = + _theResult___snd__h610886[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 = - _theResult___sfd__h611411; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65 = + _theResult___sfd__h611408; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 or - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 or + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 or + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129 or - _theResult___snd__h610889) + _theResult___snd__h610886) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h611489 = - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64; + _theResult___fst_sfd__h611486 = + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64; 3'd1: - _theResult___fst_sfd__h611489 = - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65; + _theResult___fst_sfd__h611486 = + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65; 3'd2: - _theResult___fst_sfd__h611489 = + _theResult___fst_sfd__h611486 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127; 3'd3: - _theResult___fst_sfd__h611489 = + _theResult___fst_sfd__h611486 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129; - 3'd4: _theResult___fst_sfd__h611489 = _theResult___snd__h610889[56:34]; - default: _theResult___fst_sfd__h611489 = 23'd0; + 3'd4: _theResult___fst_sfd__h611486 = _theResult___snd__h610886[56:34]; + default: _theResult___fst_sfd__h611486 = 23'd0; endcase end - always@(guard__h576391 or + always@(guard__h576388 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01, 2'b10: - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = - guard__h576391 == 2'b11 && + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = + guard__h576388 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 or - guard__h576391) + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 or + guard__h576388) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66; + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = - (guard__h576391 == 2'b0) ? + (guard__h576388 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h576391 == 2'b01 || guard__h576391 == 2'b10 || - guard__h576391 == 2'b11) && + (guard__h576388 == 2'b01 || guard__h576388 == 2'b10 || + guard__h576388 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = @@ -39355,34 +39355,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h576391 or + always@(guard__h576388 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01, 2'b10: - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = - guard__h576391 != 2'b11 || + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = + guard__h576388 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 or - guard__h576391) + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 or + guard__h576388) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67; + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = - (guard__h576391 == 2'b0) ? + (guard__h576388 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h576391 != 2'b01 && guard__h576391 != 2'b10 && - guard__h576391 != 2'b11 || + guard__h576388 != 2'b01 && guard__h576388 != 2'b10 && + guard__h576388 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = @@ -39393,34 +39393,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585100 or + always@(guard__h585097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01, 2'b10: - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = - guard__h585100 == 2'b11 && + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = + guard__h585097 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 or - guard__h585100) + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 or + guard__h585097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68; + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = - (guard__h585100 == 2'b0) ? + (guard__h585097 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h585100 == 2'b01 || guard__h585100 == 2'b10 || - guard__h585100 == 2'b11) && + (guard__h585097 == 2'b01 || guard__h585097 == 2'b10 || + guard__h585097 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = @@ -39431,34 +39431,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585100 or + always@(guard__h585097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01, 2'b10: - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = - guard__h585100 != 2'b11 || + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = + guard__h585097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 or - guard__h585100) + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 or + guard__h585097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69; + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = - (guard__h585100 == 2'b0) ? + (guard__h585097 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h585100 != 2'b01 && guard__h585100 != 2'b10 && - guard__h585100 != 2'b11 || + guard__h585097 != 2'b01 && guard__h585097 != 2'b10 && + guard__h585097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = @@ -39469,34 +39469,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594030 or + always@(guard__h594027 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01, 2'b10: - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = - guard__h594030 == 2'b11 && + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + guard__h594027 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 or - guard__h594030) + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 or + guard__h594027) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70; + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = - (guard__h594030 == 2'b0) ? + (guard__h594027 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h594030 == 2'b01 || guard__h594030 == 2'b10 || - guard__h594030 == 2'b11) && + (guard__h594027 == 2'b01 || guard__h594027 == 2'b10 || + guard__h594027 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = @@ -39507,34 +39507,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594030 or + always@(guard__h594027 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01, 2'b10: - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = - guard__h594030 != 2'b11 || + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = + guard__h594027 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 or - guard__h594030) + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 or + guard__h594027) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71; + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = - (guard__h594030 == 2'b0) ? + (guard__h594027 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h594030 != 2'b01 && guard__h594030 != 2'b10 && - guard__h594030 != 2'b11 || + guard__h594027 != 2'b01 && guard__h594027 != 2'b10 && + guard__h594027 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = @@ -39545,34 +39545,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602866 or + always@(guard__h602863 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01, 2'b10: - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = - guard__h602866 == 2'b11 && + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = + guard__h602863 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 or - guard__h602866) + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 or + guard__h602863) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72; + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = - (guard__h602866 == 2'b0) ? + (guard__h602863 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h602866 == 2'b01 || guard__h602866 == 2'b10 || - guard__h602866 == 2'b11) && + (guard__h602863 == 2'b01 || guard__h602863 == 2'b10 || + guard__h602863 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = @@ -39583,34 +39583,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602866 or + always@(guard__h602863 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01, 2'b10: - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = - guard__h602866 != 2'b11 || + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + guard__h602863 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 or - guard__h602866) + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 or + guard__h602863) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73; + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = - (guard__h602866 == 2'b0) ? + (guard__h602863 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h602866 != 2'b01 && guard__h602866 != 2'b10 && - guard__h602866 != 2'b11 || + guard__h602863 != 2'b01 && guard__h602863 != 2'b10 && + guard__h602863 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = @@ -39647,446 +39647,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h630849 or - _theResult___fst_exp__h638897 or - out_exp__h639342 or _theResult___exp__h639339) + always@(guard__h630846 or + _theResult___fst_exp__h638894 or + out_exp__h639339 or _theResult___exp__h639336) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = - _theResult___fst_exp__h638897; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 = + _theResult___fst_exp__h638894; 2'b10: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = - out_exp__h639342; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 = + out_exp__h639339; 2'b11: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = - _theResult___exp__h639339; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 = + _theResult___exp__h639336; endcase end - always@(guard__h630849 or - _theResult___fst_exp__h638897 or _theResult___exp__h639339) + always@(guard__h630846 or + _theResult___fst_exp__h638894 or _theResult___exp__h639336) begin - case (guard__h630849) + case (guard__h630846) 2'b0: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 = - _theResult___fst_exp__h638897; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79 = + _theResult___fst_exp__h638894; 2'b01, 2'b10, 2'b11: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 = - _theResult___exp__h639339; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79 = + _theResult___exp__h639336; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 or - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 or + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 or + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036 or - _theResult___fst_exp__h638897) + _theResult___fst_exp__h638894) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h639417 = - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78; + _theResult___fst_exp__h639414 = + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78; 3'd1: - _theResult___fst_exp__h639417 = - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79; + _theResult___fst_exp__h639414 = + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79; 3'd2: - _theResult___fst_exp__h639417 = + _theResult___fst_exp__h639414 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034; 3'd3: - _theResult___fst_exp__h639417 = + _theResult___fst_exp__h639414 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036; - 3'd4: _theResult___fst_exp__h639417 = _theResult___fst_exp__h638897; - default: _theResult___fst_exp__h639417 = 8'd0; + 3'd4: _theResult___fst_exp__h639414 = _theResult___fst_exp__h638894; + default: _theResult___fst_exp__h639414 = 8'd0; endcase end - always@(guard__h622142 or - _theResult___fst_exp__h630241 or - out_exp__h630760 or _theResult___exp__h630757) + always@(guard__h622139 or + _theResult___fst_exp__h630238 or + out_exp__h630757 or _theResult___exp__h630754) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = - _theResult___fst_exp__h630241; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 = + _theResult___fst_exp__h630238; 2'b10: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = - out_exp__h630760; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 = + out_exp__h630757; 2'b11: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = - _theResult___exp__h630757; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 = + _theResult___exp__h630754; endcase end - always@(guard__h622142 or - _theResult___fst_exp__h630241 or _theResult___exp__h630757) + always@(guard__h622139 or + _theResult___fst_exp__h630238 or _theResult___exp__h630754) begin - case (guard__h622142) + case (guard__h622139) 2'b0: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 = - _theResult___fst_exp__h630241; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81 = + _theResult___fst_exp__h630238; 2'b01, 2'b10, 2'b11: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 = - _theResult___exp__h630757; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81 = + _theResult___exp__h630754; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 or - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 or + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 or + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815 or - _theResult___fst_exp__h630241) + _theResult___fst_exp__h630238) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h630835 = - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80; + _theResult___fst_exp__h630832 = + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80; 3'd1: - _theResult___fst_exp__h630835 = - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81; + _theResult___fst_exp__h630832 = + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81; 3'd2: - _theResult___fst_exp__h630835 = + _theResult___fst_exp__h630832 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812; 3'd3: - _theResult___fst_exp__h630835 = + _theResult___fst_exp__h630832 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815; - 3'd4: _theResult___fst_exp__h630835 = _theResult___fst_exp__h630241; - default: _theResult___fst_exp__h630835 = 8'd0; + 3'd4: _theResult___fst_exp__h630832 = _theResult___fst_exp__h630238; + default: _theResult___fst_exp__h630832 = 8'd0; endcase end - always@(guard__h639779 or - _theResult___fst_exp__h648007 or - out_exp__h648526 or _theResult___exp__h648523) + always@(guard__h639776 or + _theResult___fst_exp__h648004 or + out_exp__h648523 or _theResult___exp__h648520) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = - _theResult___fst_exp__h648007; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 = + _theResult___fst_exp__h648004; 2'b10: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = - out_exp__h648526; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 = + out_exp__h648523; 2'b11: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = - _theResult___exp__h648523; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 = + _theResult___exp__h648520; endcase end - always@(guard__h639779 or - _theResult___fst_exp__h648007 or _theResult___exp__h648523) + always@(guard__h639776 or + _theResult___fst_exp__h648004 or _theResult___exp__h648520) begin - case (guard__h639779) + case (guard__h639776) 2'b0: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 = - _theResult___fst_exp__h648007; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87 = + _theResult___fst_exp__h648004; 2'b01, 2'b10, 2'b11: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 = - _theResult___exp__h648523; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87 = + _theResult___exp__h648520; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 or - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 or + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 or + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361 or - _theResult___fst_exp__h648007) + _theResult___fst_exp__h648004) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h648601 = - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86; + _theResult___fst_exp__h648598 = + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86; 3'd1: - _theResult___fst_exp__h648601 = - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87; + _theResult___fst_exp__h648598 = + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87; 3'd2: - _theResult___fst_exp__h648601 = + _theResult___fst_exp__h648598 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359; 3'd3: - _theResult___fst_exp__h648601 = + _theResult___fst_exp__h648598 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361; - 3'd4: _theResult___fst_exp__h648601 = _theResult___fst_exp__h648007; - default: _theResult___fst_exp__h648601 = 8'd0; + 3'd4: _theResult___fst_exp__h648598 = _theResult___fst_exp__h648004; + default: _theResult___fst_exp__h648598 = 8'd0; endcase end - always@(guard__h648615 or - _theResult___fst_exp__h656692 or - out_exp__h657162 or _theResult___exp__h657159) + always@(guard__h648612 or + _theResult___fst_exp__h656689 or + out_exp__h657159 or _theResult___exp__h657156) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = - _theResult___fst_exp__h656692; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 = + _theResult___fst_exp__h656689; 2'b10: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = - out_exp__h657162; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 = + out_exp__h657159; 2'b11: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = - _theResult___exp__h657159; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 = + _theResult___exp__h657156; endcase end - always@(guard__h648615 or - _theResult___fst_exp__h656692 or _theResult___exp__h657159) + always@(guard__h648612 or + _theResult___fst_exp__h656689 or _theResult___exp__h657156) begin - case (guard__h648615) + case (guard__h648612) 2'b0: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 = - _theResult___fst_exp__h656692; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92 = + _theResult___fst_exp__h656689; 2'b01, 2'b10, 2'b11: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 = - _theResult___exp__h657159; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92 = + _theResult___exp__h657156; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 or - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 or + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 or + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430 or - _theResult___fst_exp__h656692) + _theResult___fst_exp__h656689) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h657237 = - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91; + _theResult___fst_exp__h657234 = + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91; 3'd1: - _theResult___fst_exp__h657237 = - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92; + _theResult___fst_exp__h657234 = + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92; 3'd2: - _theResult___fst_exp__h657237 = + _theResult___fst_exp__h657234 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428; 3'd3: - _theResult___fst_exp__h657237 = + _theResult___fst_exp__h657234 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430; - 3'd4: _theResult___fst_exp__h657237 = _theResult___fst_exp__h656692; - default: _theResult___fst_exp__h657237 = 8'd0; + 3'd4: _theResult___fst_exp__h657234 = _theResult___fst_exp__h656689; + default: _theResult___fst_exp__h657234 = 8'd0; endcase end - always@(guard__h630849 or - _theResult___snd__h638848 or - out_sfd__h639343 or _theResult___sfd__h639340) + always@(guard__h630846 or + _theResult___snd__h638845 or + out_sfd__h639340 or _theResult___sfd__h639337) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = - _theResult___snd__h638848[56:34]; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 = + _theResult___snd__h638845[56:34]; 2'b10: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = - out_sfd__h639343; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 = + out_sfd__h639340; 2'b11: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = - _theResult___sfd__h639340; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 = + _theResult___sfd__h639337; endcase end - always@(guard__h630849 or - _theResult___snd__h638848 or _theResult___sfd__h639340) + always@(guard__h630846 or + _theResult___snd__h638845 or _theResult___sfd__h639337) begin - case (guard__h630849) + case (guard__h630846) 2'b0: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 = - _theResult___snd__h638848[56:34]; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94 = + _theResult___snd__h638845[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 = - _theResult___sfd__h639340; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94 = + _theResult___sfd__h639337; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 or - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 or + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 or + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480 or - _theResult___snd__h638848) + _theResult___snd__h638845) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h639418 = - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93; + _theResult___fst_sfd__h639415 = + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93; 3'd1: - _theResult___fst_sfd__h639418 = - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94; + _theResult___fst_sfd__h639415 = + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94; 3'd2: - _theResult___fst_sfd__h639418 = + _theResult___fst_sfd__h639415 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478; 3'd3: - _theResult___fst_sfd__h639418 = + _theResult___fst_sfd__h639415 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480; - 3'd4: _theResult___fst_sfd__h639418 = _theResult___snd__h638848[56:34]; - default: _theResult___fst_sfd__h639418 = 23'd0; + 3'd4: _theResult___fst_sfd__h639415 = _theResult___snd__h638845[56:34]; + default: _theResult___fst_sfd__h639415 = 23'd0; endcase end - always@(guard__h622142 or - sfdin__h630235 or out_sfd__h630761 or _theResult___sfd__h630758) + always@(guard__h622139 or + sfdin__h630232 or out_sfd__h630758 or _theResult___sfd__h630755) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = - sfdin__h630235[56:34]; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 = + sfdin__h630232[56:34]; 2'b10: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = - out_sfd__h630761; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 = + out_sfd__h630758; 2'b11: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = - _theResult___sfd__h630758; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 = + _theResult___sfd__h630755; endcase end - always@(guard__h622142 or sfdin__h630235 or _theResult___sfd__h630758) + always@(guard__h622139 or sfdin__h630232 or _theResult___sfd__h630755) begin - case (guard__h622142) + case (guard__h622139) 2'b0: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 = - sfdin__h630235[56:34]; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96 = + sfdin__h630232[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 = - _theResult___sfd__h630758; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96 = + _theResult___sfd__h630755; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 or - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 or + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 or + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461 or - sfdin__h630235) + sfdin__h630232) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h630836 = - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95; + _theResult___fst_sfd__h630833 = + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95; 3'd1: - _theResult___fst_sfd__h630836 = - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96; + _theResult___fst_sfd__h630833 = + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96; 3'd2: - _theResult___fst_sfd__h630836 = + _theResult___fst_sfd__h630833 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459; 3'd3: - _theResult___fst_sfd__h630836 = + _theResult___fst_sfd__h630833 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461; - 3'd4: _theResult___fst_sfd__h630836 = sfdin__h630235[56:34]; - default: _theResult___fst_sfd__h630836 = 23'd0; + 3'd4: _theResult___fst_sfd__h630833 = sfdin__h630232[56:34]; + default: _theResult___fst_sfd__h630833 = 23'd0; endcase end - always@(guard__h639779 or - sfdin__h648001 or out_sfd__h648527 or _theResult___sfd__h648524) + always@(guard__h639776 or + sfdin__h647998 or out_sfd__h648524 or _theResult___sfd__h648521) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = - sfdin__h648001[56:34]; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 = + sfdin__h647998[56:34]; 2'b10: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = - out_sfd__h648527; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 = + out_sfd__h648524; 2'b11: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = - _theResult___sfd__h648524; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 = + _theResult___sfd__h648521; endcase end - always@(guard__h639779 or sfdin__h648001 or _theResult___sfd__h648524) + always@(guard__h639776 or sfdin__h647998 or _theResult___sfd__h648521) begin - case (guard__h639779) + case (guard__h639776) 2'b0: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 = - sfdin__h648001[56:34]; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98 = + sfdin__h647998[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 = - _theResult___sfd__h648524; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98 = + _theResult___sfd__h648521; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 or - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 or + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 or + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 or - sfdin__h648001) + sfdin__h647998) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h648602 = - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97; + _theResult___fst_sfd__h648599 = + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97; 3'd1: - _theResult___fst_sfd__h648602 = - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98; + _theResult___fst_sfd__h648599 = + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98; 3'd2: - _theResult___fst_sfd__h648602 = + _theResult___fst_sfd__h648599 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505; 3'd3: - _theResult___fst_sfd__h648602 = + _theResult___fst_sfd__h648599 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507; - 3'd4: _theResult___fst_sfd__h648602 = sfdin__h648001[56:34]; - default: _theResult___fst_sfd__h648602 = 23'd0; + 3'd4: _theResult___fst_sfd__h648599 = sfdin__h647998[56:34]; + default: _theResult___fst_sfd__h648599 = 23'd0; endcase end - always@(guard__h648615 or - _theResult___snd__h656638 or - out_sfd__h657163 or _theResult___sfd__h657160) + always@(guard__h648612 or + _theResult___snd__h656635 or + out_sfd__h657160 or _theResult___sfd__h657157) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = - _theResult___snd__h656638[56:34]; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 = + _theResult___snd__h656635[56:34]; 2'b10: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = - out_sfd__h657163; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 = + out_sfd__h657160; 2'b11: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = - _theResult___sfd__h657160; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 = + _theResult___sfd__h657157; endcase end - always@(guard__h648615 or - _theResult___snd__h656638 or _theResult___sfd__h657160) + always@(guard__h648612 or + _theResult___snd__h656635 or _theResult___sfd__h657157) begin - case (guard__h648615) + case (guard__h648612) 2'b0: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 = - _theResult___snd__h656638[56:34]; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100 = + _theResult___snd__h656635[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 = - _theResult___sfd__h657160; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100 = + _theResult___sfd__h657157; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 or - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 or + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 or + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526 or - _theResult___snd__h656638) + _theResult___snd__h656635) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h657238 = - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99; + _theResult___fst_sfd__h657235 = + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99; 3'd1: - _theResult___fst_sfd__h657238 = - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100; + _theResult___fst_sfd__h657235 = + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100; 3'd2: - _theResult___fst_sfd__h657238 = + _theResult___fst_sfd__h657235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524; 3'd3: - _theResult___fst_sfd__h657238 = + _theResult___fst_sfd__h657235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526; - 3'd4: _theResult___fst_sfd__h657238 = _theResult___snd__h656638[56:34]; - default: _theResult___fst_sfd__h657238 = 23'd0; + 3'd4: _theResult___fst_sfd__h657235 = _theResult___snd__h656635[56:34]; + default: _theResult___fst_sfd__h657235 = 23'd0; endcase end - always@(guard__h622142 or + always@(guard__h622139 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01, 2'b10: - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = - guard__h622142 == 2'b11 && + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = + guard__h622139 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 or - guard__h622142) + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 or + guard__h622139) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101; + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = - (guard__h622142 == 2'b0) ? + (guard__h622139 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h622142 == 2'b01 || guard__h622142 == 2'b10 || - guard__h622142 == 2'b11) && + (guard__h622139 == 2'b01 || guard__h622139 == 2'b10 || + guard__h622139 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = @@ -40097,34 +40097,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h622142 or + always@(guard__h622139 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01, 2'b10: - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = - guard__h622142 != 2'b11 || + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = + guard__h622139 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 or - guard__h622142) + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 or + guard__h622139) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102; + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = - (guard__h622142 == 2'b0) ? + (guard__h622139 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h622142 != 2'b01 && guard__h622142 != 2'b10 && - guard__h622142 != 2'b11 || + guard__h622139 != 2'b01 && guard__h622139 != 2'b10 && + guard__h622139 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = @@ -40135,34 +40135,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630849 or + always@(guard__h630846 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01, 2'b10: - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = - guard__h630849 == 2'b11 && + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = + guard__h630846 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 or - guard__h630849) + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 or + guard__h630846) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103; + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = - (guard__h630849 == 2'b0) ? + (guard__h630846 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h630849 == 2'b01 || guard__h630849 == 2'b10 || - guard__h630849 == 2'b11) && + (guard__h630846 == 2'b01 || guard__h630846 == 2'b10 || + guard__h630846 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = @@ -40173,34 +40173,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630849 or + always@(guard__h630846 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01, 2'b10: - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = - guard__h630849 != 2'b11 || + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = + guard__h630846 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 or - guard__h630849) + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 or + guard__h630846) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104; + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = - (guard__h630849 == 2'b0) ? + (guard__h630846 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h630849 != 2'b01 && guard__h630849 != 2'b10 && - guard__h630849 != 2'b11 || + guard__h630846 != 2'b01 && guard__h630846 != 2'b10 && + guard__h630846 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = @@ -40211,34 +40211,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639779 or + always@(guard__h639776 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01, 2'b10: - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = - guard__h639779 == 2'b11 && + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = + guard__h639776 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 or - guard__h639779) + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 or + guard__h639776) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105; + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = - (guard__h639779 == 2'b0) ? + (guard__h639776 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h639779 == 2'b01 || guard__h639779 == 2'b10 || - guard__h639779 == 2'b11) && + (guard__h639776 == 2'b01 || guard__h639776 == 2'b10 || + guard__h639776 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = @@ -40249,34 +40249,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639779 or + always@(guard__h639776 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01, 2'b10: - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = - guard__h639779 != 2'b11 || + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + guard__h639776 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 or - guard__h639779) + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 or + guard__h639776) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106; + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = - (guard__h639779 == 2'b0) ? + (guard__h639776 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h639779 != 2'b01 && guard__h639779 != 2'b10 && - guard__h639779 != 2'b11 || + guard__h639776 != 2'b01 && guard__h639776 != 2'b10 && + guard__h639776 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = @@ -40287,34 +40287,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648615 or + always@(guard__h648612 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01, 2'b10: - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = - guard__h648615 == 2'b11 && + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = + guard__h648612 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 or - guard__h648615) + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 or + guard__h648612) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107; + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = - (guard__h648615 == 2'b0) ? + (guard__h648612 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h648615 == 2'b01 || guard__h648615 == 2'b10 || - guard__h648615 == 2'b11) && + (guard__h648612 == 2'b01 || guard__h648612 == 2'b10 || + guard__h648612 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = @@ -40325,34 +40325,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648615 or + always@(guard__h648612 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01, 2'b10: - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = - guard__h648615 != 2'b11 || + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = + guard__h648612 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 or - guard__h648615) + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 or + guard__h648612) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108; + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = - (guard__h648615 == 2'b0) ? + (guard__h648612 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h648615 != 2'b01 && guard__h648615 != 2'b10 && - guard__h648615 != 2'b11 || + guard__h648612 != 2'b01 && guard__h648612 != 2'b10 && + guard__h648612 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = @@ -40389,446 +40389,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h676596 or - _theResult___fst_exp__h684644 or - out_exp__h685089 or _theResult___exp__h685086) + always@(guard__h676593 or + _theResult___fst_exp__h684641 or + out_exp__h685086 or _theResult___exp__h685083) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = - _theResult___fst_exp__h684644; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 = + _theResult___fst_exp__h684641; 2'b10: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = - out_exp__h685089; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 = + out_exp__h685086; 2'b11: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = - _theResult___exp__h685086; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 = + _theResult___exp__h685083; endcase end - always@(guard__h676596 or - _theResult___fst_exp__h684644 or _theResult___exp__h685086) + always@(guard__h676593 or + _theResult___fst_exp__h684641 or _theResult___exp__h685083) begin - case (guard__h676596) + case (guard__h676593) 2'b0: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 = - _theResult___fst_exp__h684644; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114 = + _theResult___fst_exp__h684641; 2'b01, 2'b10, 2'b11: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 = - _theResult___exp__h685086; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114 = + _theResult___exp__h685083; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 or - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 or + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 or + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433 or - _theResult___fst_exp__h684644) + _theResult___fst_exp__h684641) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h685164 = - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113; + _theResult___fst_exp__h685161 = + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113; 3'd1: - _theResult___fst_exp__h685164 = - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114; + _theResult___fst_exp__h685161 = + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114; 3'd2: - _theResult___fst_exp__h685164 = + _theResult___fst_exp__h685161 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431; 3'd3: - _theResult___fst_exp__h685164 = + _theResult___fst_exp__h685161 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433; - 3'd4: _theResult___fst_exp__h685164 = _theResult___fst_exp__h684644; - default: _theResult___fst_exp__h685164 = 8'd0; + 3'd4: _theResult___fst_exp__h685161 = _theResult___fst_exp__h684641; + default: _theResult___fst_exp__h685161 = 8'd0; endcase end - always@(guard__h667889 or - _theResult___fst_exp__h675988 or - out_exp__h676507 or _theResult___exp__h676504) + always@(guard__h667886 or + _theResult___fst_exp__h675985 or + out_exp__h676504 or _theResult___exp__h676501) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = - _theResult___fst_exp__h675988; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 = + _theResult___fst_exp__h675985; 2'b10: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = - out_exp__h676507; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 = + out_exp__h676504; 2'b11: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = - _theResult___exp__h676504; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 = + _theResult___exp__h676501; endcase end - always@(guard__h667889 or - _theResult___fst_exp__h675988 or _theResult___exp__h676504) + always@(guard__h667886 or + _theResult___fst_exp__h675985 or _theResult___exp__h676501) begin - case (guard__h667889) + case (guard__h667886) 2'b0: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 = - _theResult___fst_exp__h675988; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116 = + _theResult___fst_exp__h675985; 2'b01, 2'b10, 2'b11: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 = - _theResult___exp__h676504; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116 = + _theResult___exp__h676501; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 or - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 or + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 or + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212 or - _theResult___fst_exp__h675988) + _theResult___fst_exp__h675985) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h676582 = - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115; + _theResult___fst_exp__h676579 = + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115; 3'd1: - _theResult___fst_exp__h676582 = - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116; + _theResult___fst_exp__h676579 = + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116; 3'd2: - _theResult___fst_exp__h676582 = + _theResult___fst_exp__h676579 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209; 3'd3: - _theResult___fst_exp__h676582 = + _theResult___fst_exp__h676579 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212; - 3'd4: _theResult___fst_exp__h676582 = _theResult___fst_exp__h675988; - default: _theResult___fst_exp__h676582 = 8'd0; + 3'd4: _theResult___fst_exp__h676579 = _theResult___fst_exp__h675985; + default: _theResult___fst_exp__h676579 = 8'd0; endcase end - always@(guard__h685526 or - _theResult___fst_exp__h693754 or - out_exp__h694273 or _theResult___exp__h694270) + always@(guard__h685523 or + _theResult___fst_exp__h693751 or + out_exp__h694270 or _theResult___exp__h694267) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = - _theResult___fst_exp__h693754; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 = + _theResult___fst_exp__h693751; 2'b10: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = - out_exp__h694273; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 = + out_exp__h694270; 2'b11: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = - _theResult___exp__h694270; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 = + _theResult___exp__h694267; endcase end - always@(guard__h685526 or - _theResult___fst_exp__h693754 or _theResult___exp__h694270) + always@(guard__h685523 or + _theResult___fst_exp__h693751 or _theResult___exp__h694267) begin - case (guard__h685526) + case (guard__h685523) 2'b0: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 = - _theResult___fst_exp__h693754; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122 = + _theResult___fst_exp__h693751; 2'b01, 2'b10, 2'b11: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 = - _theResult___exp__h694270; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122 = + _theResult___exp__h694267; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 or - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 or + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 or + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758 or - _theResult___fst_exp__h693754) + _theResult___fst_exp__h693751) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h694348 = - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121; + _theResult___fst_exp__h694345 = + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121; 3'd1: - _theResult___fst_exp__h694348 = - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122; + _theResult___fst_exp__h694345 = + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122; 3'd2: - _theResult___fst_exp__h694348 = + _theResult___fst_exp__h694345 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756; 3'd3: - _theResult___fst_exp__h694348 = + _theResult___fst_exp__h694345 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758; - 3'd4: _theResult___fst_exp__h694348 = _theResult___fst_exp__h693754; - default: _theResult___fst_exp__h694348 = 8'd0; + 3'd4: _theResult___fst_exp__h694345 = _theResult___fst_exp__h693751; + default: _theResult___fst_exp__h694345 = 8'd0; endcase end - always@(guard__h694362 or - _theResult___fst_exp__h702439 or - out_exp__h702909 or _theResult___exp__h702906) + always@(guard__h694359 or + _theResult___fst_exp__h702436 or + out_exp__h702906 or _theResult___exp__h702903) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = - _theResult___fst_exp__h702439; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 = + _theResult___fst_exp__h702436; 2'b10: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = - out_exp__h702909; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 = + out_exp__h702906; 2'b11: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = - _theResult___exp__h702906; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 = + _theResult___exp__h702903; endcase end - always@(guard__h694362 or - _theResult___fst_exp__h702439 or _theResult___exp__h702906) + always@(guard__h694359 or + _theResult___fst_exp__h702436 or _theResult___exp__h702903) begin - case (guard__h694362) + case (guard__h694359) 2'b0: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 = - _theResult___fst_exp__h702439; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127 = + _theResult___fst_exp__h702436; 2'b01, 2'b10, 2'b11: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 = - _theResult___exp__h702906; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127 = + _theResult___exp__h702903; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 or - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 or + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 or + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827 or - _theResult___fst_exp__h702439) + _theResult___fst_exp__h702436) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h702984 = - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126; + _theResult___fst_exp__h702981 = + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126; 3'd1: - _theResult___fst_exp__h702984 = - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127; + _theResult___fst_exp__h702981 = + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127; 3'd2: - _theResult___fst_exp__h702984 = + _theResult___fst_exp__h702981 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825; 3'd3: - _theResult___fst_exp__h702984 = + _theResult___fst_exp__h702981 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827; - 3'd4: _theResult___fst_exp__h702984 = _theResult___fst_exp__h702439; - default: _theResult___fst_exp__h702984 = 8'd0; + 3'd4: _theResult___fst_exp__h702981 = _theResult___fst_exp__h702436; + default: _theResult___fst_exp__h702981 = 8'd0; endcase end - always@(guard__h676596 or - _theResult___snd__h684595 or - out_sfd__h685090 or _theResult___sfd__h685087) + always@(guard__h676593 or + _theResult___snd__h684592 or + out_sfd__h685087 or _theResult___sfd__h685084) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = - _theResult___snd__h684595[56:34]; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 = + _theResult___snd__h684592[56:34]; 2'b10: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = - out_sfd__h685090; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 = + out_sfd__h685087; 2'b11: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = - _theResult___sfd__h685087; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 = + _theResult___sfd__h685084; endcase end - always@(guard__h676596 or - _theResult___snd__h684595 or _theResult___sfd__h685087) + always@(guard__h676593 or + _theResult___snd__h684592 or _theResult___sfd__h685084) begin - case (guard__h676596) + case (guard__h676593) 2'b0: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 = - _theResult___snd__h684595[56:34]; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129 = + _theResult___snd__h684592[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 = - _theResult___sfd__h685087; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129 = + _theResult___sfd__h685084; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 or - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 or + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 or + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877 or - _theResult___snd__h684595) + _theResult___snd__h684592) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h685165 = - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128; + _theResult___fst_sfd__h685162 = + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128; 3'd1: - _theResult___fst_sfd__h685165 = - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129; + _theResult___fst_sfd__h685162 = + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129; 3'd2: - _theResult___fst_sfd__h685165 = + _theResult___fst_sfd__h685162 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875; 3'd3: - _theResult___fst_sfd__h685165 = + _theResult___fst_sfd__h685162 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877; - 3'd4: _theResult___fst_sfd__h685165 = _theResult___snd__h684595[56:34]; - default: _theResult___fst_sfd__h685165 = 23'd0; + 3'd4: _theResult___fst_sfd__h685162 = _theResult___snd__h684592[56:34]; + default: _theResult___fst_sfd__h685162 = 23'd0; endcase end - always@(guard__h667889 or - sfdin__h675982 or out_sfd__h676508 or _theResult___sfd__h676505) + always@(guard__h667886 or + sfdin__h675979 or out_sfd__h676505 or _theResult___sfd__h676502) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = - sfdin__h675982[56:34]; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 = + sfdin__h675979[56:34]; 2'b10: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = - out_sfd__h676508; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 = + out_sfd__h676505; 2'b11: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = - _theResult___sfd__h676505; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 = + _theResult___sfd__h676502; endcase end - always@(guard__h667889 or sfdin__h675982 or _theResult___sfd__h676505) + always@(guard__h667886 or sfdin__h675979 or _theResult___sfd__h676502) begin - case (guard__h667889) + case (guard__h667886) 2'b0: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 = - sfdin__h675982[56:34]; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131 = + sfdin__h675979[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 = - _theResult___sfd__h676505; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131 = + _theResult___sfd__h676502; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 or - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 or + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 or + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858 or - sfdin__h675982) + sfdin__h675979) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h676583 = - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130; + _theResult___fst_sfd__h676580 = + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130; 3'd1: - _theResult___fst_sfd__h676583 = - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131; + _theResult___fst_sfd__h676580 = + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131; 3'd2: - _theResult___fst_sfd__h676583 = + _theResult___fst_sfd__h676580 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856; 3'd3: - _theResult___fst_sfd__h676583 = + _theResult___fst_sfd__h676580 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858; - 3'd4: _theResult___fst_sfd__h676583 = sfdin__h675982[56:34]; - default: _theResult___fst_sfd__h676583 = 23'd0; + 3'd4: _theResult___fst_sfd__h676580 = sfdin__h675979[56:34]; + default: _theResult___fst_sfd__h676580 = 23'd0; endcase end - always@(guard__h685526 or - sfdin__h693748 or out_sfd__h694274 or _theResult___sfd__h694271) + always@(guard__h685523 or + sfdin__h693745 or out_sfd__h694271 or _theResult___sfd__h694268) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = - sfdin__h693748[56:34]; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 = + sfdin__h693745[56:34]; 2'b10: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = - out_sfd__h694274; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 = + out_sfd__h694271; 2'b11: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = - _theResult___sfd__h694271; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 = + _theResult___sfd__h694268; endcase end - always@(guard__h685526 or sfdin__h693748 or _theResult___sfd__h694271) + always@(guard__h685523 or sfdin__h693745 or _theResult___sfd__h694268) begin - case (guard__h685526) + case (guard__h685523) 2'b0: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 = - sfdin__h693748[56:34]; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133 = + sfdin__h693745[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h694271; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133 = + _theResult___sfd__h694268; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 or - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 or + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 or + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904 or - sfdin__h693748) + sfdin__h693745) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h694349 = - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132; + _theResult___fst_sfd__h694346 = + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132; 3'd1: - _theResult___fst_sfd__h694349 = - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133; + _theResult___fst_sfd__h694346 = + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133; 3'd2: - _theResult___fst_sfd__h694349 = + _theResult___fst_sfd__h694346 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902; 3'd3: - _theResult___fst_sfd__h694349 = + _theResult___fst_sfd__h694346 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904; - 3'd4: _theResult___fst_sfd__h694349 = sfdin__h693748[56:34]; - default: _theResult___fst_sfd__h694349 = 23'd0; + 3'd4: _theResult___fst_sfd__h694346 = sfdin__h693745[56:34]; + default: _theResult___fst_sfd__h694346 = 23'd0; endcase end - always@(guard__h694362 or - _theResult___snd__h702385 or - out_sfd__h702910 or _theResult___sfd__h702907) + always@(guard__h694359 or + _theResult___snd__h702382 or + out_sfd__h702907 or _theResult___sfd__h702904) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = - _theResult___snd__h702385[56:34]; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 = + _theResult___snd__h702382[56:34]; 2'b10: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = - out_sfd__h702910; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 = + out_sfd__h702907; 2'b11: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = - _theResult___sfd__h702907; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 = + _theResult___sfd__h702904; endcase end - always@(guard__h694362 or - _theResult___snd__h702385 or _theResult___sfd__h702907) + always@(guard__h694359 or + _theResult___snd__h702382 or _theResult___sfd__h702904) begin - case (guard__h694362) + case (guard__h694359) 2'b0: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 = - _theResult___snd__h702385[56:34]; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135 = + _theResult___snd__h702382[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 = - _theResult___sfd__h702907; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135 = + _theResult___sfd__h702904; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 or - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 or + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 or + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923 or - _theResult___snd__h702385) + _theResult___snd__h702382) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h702985 = - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134; + _theResult___fst_sfd__h702982 = + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134; 3'd1: - _theResult___fst_sfd__h702985 = - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135; + _theResult___fst_sfd__h702982 = + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135; 3'd2: - _theResult___fst_sfd__h702985 = + _theResult___fst_sfd__h702982 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921; 3'd3: - _theResult___fst_sfd__h702985 = + _theResult___fst_sfd__h702982 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923; - 3'd4: _theResult___fst_sfd__h702985 = _theResult___snd__h702385[56:34]; - default: _theResult___fst_sfd__h702985 = 23'd0; + 3'd4: _theResult___fst_sfd__h702982 = _theResult___snd__h702382[56:34]; + default: _theResult___fst_sfd__h702982 = 23'd0; endcase end - always@(guard__h667889 or + always@(guard__h667886 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01, 2'b10: - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = - guard__h667889 != 2'b11 || + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = + guard__h667886 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 or - guard__h667889) + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 or + guard__h667886) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136; + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = - (guard__h667889 == 2'b0) ? + (guard__h667886 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h667889 != 2'b01 && guard__h667889 != 2'b10 && - guard__h667889 != 2'b11 || + guard__h667886 != 2'b01 && guard__h667886 != 2'b10 && + guard__h667886 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = @@ -40839,34 +40839,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h667889 or + always@(guard__h667886 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01, 2'b10: - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = - guard__h667889 == 2'b11 && + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + guard__h667886 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or - guard__h667889) + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or + guard__h667886) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = - (guard__h667889 == 2'b0) ? + (guard__h667886 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h667889 == 2'b01 || guard__h667889 == 2'b10 || - guard__h667889 == 2'b11) && + (guard__h667886 == 2'b01 || guard__h667886 == 2'b10 || + guard__h667886 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = @@ -40877,34 +40877,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676596 or + always@(guard__h676593 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01, 2'b10: - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = - guard__h676596 == 2'b11 && + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = + guard__h676593 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or - guard__h676596) + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or + guard__h676593) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = - (guard__h676596 == 2'b0) ? + (guard__h676593 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h676596 == 2'b01 || guard__h676596 == 2'b10 || - guard__h676596 == 2'b11) && + (guard__h676593 == 2'b01 || guard__h676593 == 2'b10 || + guard__h676593 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = @@ -40915,34 +40915,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676596 or + always@(guard__h676593 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01, 2'b10: - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = - guard__h676596 != 2'b11 || + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + guard__h676593 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or - guard__h676596) + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or + guard__h676593) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = - (guard__h676596 == 2'b0) ? + (guard__h676593 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h676596 != 2'b01 && guard__h676596 != 2'b10 && - guard__h676596 != 2'b11 || + guard__h676593 != 2'b01 && guard__h676593 != 2'b10 && + guard__h676593 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = @@ -40953,34 +40953,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685526 or + always@(guard__h685523 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01, 2'b10: - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = - guard__h685526 == 2'b11 && + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = + guard__h685523 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 or - guard__h685526) + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 or + guard__h685523) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140; + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = - (guard__h685526 == 2'b0) ? + (guard__h685523 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h685526 == 2'b01 || guard__h685526 == 2'b10 || - guard__h685526 == 2'b11) && + (guard__h685523 == 2'b01 || guard__h685523 == 2'b10 || + guard__h685523 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = @@ -40991,34 +40991,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694362 or + always@(guard__h694359 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01, 2'b10: - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = - guard__h694362 == 2'b11 && + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + guard__h694359 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or - guard__h694362) + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or + guard__h694359) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = - (guard__h694362 == 2'b0) ? + (guard__h694359 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h694362 == 2'b01 || guard__h694362 == 2'b10 || - guard__h694362 == 2'b11) && + (guard__h694359 == 2'b01 || guard__h694359 == 2'b10 || + guard__h694359 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = @@ -41029,34 +41029,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685526 or + always@(guard__h685523 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01, 2'b10: - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = - guard__h685526 != 2'b11 || + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + guard__h685523 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or - guard__h685526) + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or + guard__h685523) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = - (guard__h685526 == 2'b0) ? + (guard__h685523 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h685526 != 2'b01 && guard__h685526 != 2'b10 && - guard__h685526 != 2'b11 || + guard__h685523 != 2'b01 && guard__h685523 != 2'b10 && + guard__h685523 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = @@ -41067,34 +41067,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694362 or + always@(guard__h694359 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01, 2'b10: - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = - guard__h694362 != 2'b11 || + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = + guard__h694359 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 or - guard__h694362) + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 or + guard__h694359) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143; + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = - (guard__h694362 == 2'b0) ? + (guard__h694359 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h694362 != 2'b01 && guard__h694362 != 2'b10 && - guard__h694362 != 2'b11 || + guard__h694359 != 2'b01 && guard__h694359 != 2'b10 && + guard__h694359 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = @@ -41151,28 +41151,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h726252 or - _theResult___fst_exp__h734213 or _theResult___exp__h734868) + always@(guard__h726249 or + _theResult___fst_exp__h734210 or _theResult___exp__h734865) begin - case (guard__h726252) + case (guard__h726249) 2'b0: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154 = - _theResult___fst_exp__h734213; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154 = + _theResult___fst_exp__h734210; 2'b01, 2'b10, 2'b11: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154 = - _theResult___exp__h734868; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154 = + _theResult___exp__h734865; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h734213 or + _theResult___fst_exp__h734210 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146 or - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154) + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = - _theResult___fst_exp__h734213; + _theResult___fst_exp__h734210; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148; @@ -41181,44 +41181,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = 11'd0; endcase end - always@(guard__h726252 or - _theResult___fst_exp__h734213 or - out_exp__h734871 or _theResult___exp__h734868) + always@(guard__h726249 or + _theResult___fst_exp__h734210 or + out_exp__h734868 or _theResult___exp__h734865) begin - case (guard__h726252) + case (guard__h726249) 2'b0, 2'b01: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = - _theResult___fst_exp__h734213; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 = + _theResult___fst_exp__h734210; 2'b10: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = - out_exp__h734871; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 = + out_exp__h734868; 2'b11: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = - _theResult___exp__h734868; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 = + _theResult___exp__h734865; endcase end - always@(guard__h726252 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h726249 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h726252) + case (guard__h726249) 2'b0, 2'b01, 2'b10: - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h726252 == 2'b11 && + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h726249 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726252) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726249) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41228,12 +41228,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h726252 == 2'b0) ? + (guard__h726249 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h726252 == 2'b01 || guard__h726252 == 2'b10 || - guard__h726252 == 2'b11) && + (guard__h726249 == 2'b01 || guard__h726249 == 2'b10 || + guard__h726249 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41244,23 +41244,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h735564 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h735561 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h735564) + case (guard__h735561) 2'b0, 2'b01, 2'b10: - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h735564 == 2'b11 && + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h735561 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735564) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735561) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41270,12 +41270,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h735564 == 2'b0) ? + (guard__h735561 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h735564 == 2'b01 || guard__h735564 == 2'b10 || - guard__h735564 == 2'b11) && + (guard__h735561 == 2'b01 || guard__h735561 == 2'b10 || + guard__h735561 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41286,23 +41286,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h744633 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h744630 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h744633) + case (guard__h744630) 2'b0, 2'b01, 2'b10: - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = - guard__h744633 == 2'b11 && + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + guard__h744630 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744633) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744630) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41312,12 +41312,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h744633 == 2'b0) ? + (guard__h744630 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h744633 == 2'b01 || guard__h744633 == 2'b10 || - guard__h744633 == 2'b11) && + (guard__h744630 == 2'b01 || guard__h744630 == 2'b10 || + guard__h744630 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41328,28 +41328,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h804409 or - _theResult___fst_exp__h812370 or _theResult___exp__h813025) + always@(guard__h804406 or + _theResult___fst_exp__h812367 or _theResult___exp__h813022) begin - case (guard__h804409) + case (guard__h804406) 2'b0: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171 = - _theResult___fst_exp__h812370; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171 = + _theResult___fst_exp__h812367; 2'b01, 2'b10, 2'b11: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171 = - _theResult___exp__h813025; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171 = + _theResult___exp__h813022; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h812370 or + _theResult___fst_exp__h812367 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861 or - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171) + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = - _theResult___fst_exp__h812370; + _theResult___fst_exp__h812367; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863; @@ -41358,42 +41358,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = 11'd0; endcase end - always@(guard__h804409 or - _theResult___fst_exp__h812370 or - out_exp__h813028 or _theResult___exp__h813025) + always@(guard__h804406 or + _theResult___fst_exp__h812367 or + out_exp__h813025 or _theResult___exp__h813022) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = - _theResult___fst_exp__h812370; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 = + _theResult___fst_exp__h812367; 2'b10: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = - out_exp__h813028; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 = + out_exp__h813025; 2'b11: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = - _theResult___exp__h813025; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 = + _theResult___exp__h813022; endcase end - always@(guard__h813721 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813718 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01, 2'b10: - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = - guard__h813721 == 2'b11 && + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + guard__h813718 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813721) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813718) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41402,12 +41402,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174 = - (guard__h813721 == 2'b0) ? + (guard__h813718 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h813721 == 2'b01 || guard__h813721 == 2'b10 || - guard__h813721 == 2'b11) && + (guard__h813718 == 2'b01 || guard__h813718 == 2'b10 || + guard__h813718 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41418,21 +41418,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h804409 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804406 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01, 2'b10: - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = - guard__h804409 == 2'b11 && + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + guard__h804406 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804409) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804406) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41441,12 +41441,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176 = - (guard__h804409 == 2'b0) ? + (guard__h804406 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h804409 == 2'b01 || guard__h804409 == 2'b10 || - guard__h804409 == 2'b11) && + (guard__h804406 == 2'b01 || guard__h804406 == 2'b10 || + guard__h804406 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41457,21 +41457,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822790 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822787 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01, 2'b10: - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = - guard__h822790 == 2'b11 && + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + guard__h822787 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822790) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822787) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41480,12 +41480,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178 = - (guard__h822790 == 2'b0) ? + (guard__h822787 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h822790 == 2'b01 || guard__h822790 == 2'b10 || - guard__h822790 == 2'b11) && + (guard__h822787 == 2'b01 || guard__h822787 == 2'b10 || + guard__h822787 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41496,21 +41496,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h813721 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813718 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01, 2'b10: - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = - guard__h813721 != 2'b11 || + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + guard__h813718 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813721) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813718) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41519,12 +41519,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180 = - (guard__h813721 == 2'b0) ? + (guard__h813718 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h813721 != 2'b01 && guard__h813721 != 2'b10 && - guard__h813721 != 2'b11 || + guard__h813718 != 2'b01 && guard__h813718 != 2'b10 && + guard__h813718 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41535,21 +41535,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h804409 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804406 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01, 2'b10: - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = - guard__h804409 != 2'b11 || + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + guard__h804406 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804409) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804406) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41558,12 +41558,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182 = - (guard__h804409 == 2'b0) ? + (guard__h804406 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h804409 != 2'b01 && guard__h804409 != 2'b10 && - guard__h804409 != 2'b11 || + guard__h804406 != 2'b01 && guard__h804406 != 2'b10 && + guard__h804406 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41574,21 +41574,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822790 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822787 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01, 2'b10: - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = - guard__h822790 != 2'b11 || + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + guard__h822787 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822790) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822787) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41597,12 +41597,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184 = - (guard__h822790 == 2'b0) ? + (guard__h822787 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h822790 != 2'b01 && guard__h822790 != 2'b10 && - guard__h822790 != 2'b11 || + guard__h822787 != 2'b01 && guard__h822787 != 2'b10 && + guard__h822787 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41613,28 +41613,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h765105 or - _theResult___fst_exp__h773066 or _theResult___exp__h773721) + always@(guard__h765102 or + _theResult___fst_exp__h773063 or _theResult___exp__h773718) begin - case (guard__h765105) + case (guard__h765102) 2'b0: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194 = - _theResult___fst_exp__h773066; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194 = + _theResult___fst_exp__h773063; 2'b01, 2'b10, 2'b11: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194 = - _theResult___exp__h773721; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194 = + _theResult___exp__h773718; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h773066 or + _theResult___fst_exp__h773063 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631 or - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194) + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = - _theResult___fst_exp__h773066; + _theResult___fst_exp__h773063; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633; @@ -41643,49 +41643,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = 11'd0; endcase end - always@(guard__h765105 or - _theResult___fst_exp__h773066 or - out_exp__h773724 or _theResult___exp__h773721) + always@(guard__h765102 or + _theResult___fst_exp__h773063 or + out_exp__h773721 or _theResult___exp__h773718) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = - _theResult___fst_exp__h773066; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 = + _theResult___fst_exp__h773063; 2'b10: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = - out_exp__h773724; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 = + out_exp__h773721; 2'b11: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = - _theResult___exp__h773721; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 = + _theResult___exp__h773718; endcase end - always@(guard__h774417 or - _theResult___fst_exp__h782643 or _theResult___exp__h783372) + always@(guard__h774414 or + _theResult___fst_exp__h782640 or _theResult___exp__h783369) begin - case (guard__h774417) + case (guard__h774414) 2'b0: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196 = - _theResult___fst_exp__h782643; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196 = + _theResult___fst_exp__h782640; 2'b01, 2'b10, 2'b11: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196 = - _theResult___exp__h783372; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196 = + _theResult___exp__h783369; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h782643 or + _theResult___fst_exp__h782640 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669 or - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196) + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = - _theResult___fst_exp__h782643; + _theResult___fst_exp__h782640; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671; @@ -41694,49 +41694,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = 11'd0; endcase end - always@(guard__h774417 or - _theResult___fst_exp__h782643 or - out_exp__h783375 or _theResult___exp__h783372) + always@(guard__h774414 or + _theResult___fst_exp__h782640 or + out_exp__h783372 or _theResult___exp__h783369) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = - _theResult___fst_exp__h782643; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 = + _theResult___fst_exp__h782640; 2'b10: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = - out_exp__h783375; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 = + out_exp__h783372; 2'b11: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = - _theResult___exp__h783372; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 = + _theResult___exp__h783369; endcase end - always@(guard__h813721 or - _theResult___fst_exp__h821947 or _theResult___exp__h822676) + always@(guard__h813718 or + _theResult___fst_exp__h821944 or _theResult___exp__h822673) begin - case (guard__h813721) + case (guard__h813718) 2'b0: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198 = - _theResult___fst_exp__h821947; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198 = + _theResult___fst_exp__h821944; 2'b01, 2'b10, 2'b11: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198 = - _theResult___exp__h822676; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198 = + _theResult___exp__h822673; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h821947 or + _theResult___fst_exp__h821944 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899 or - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198) + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = - _theResult___fst_exp__h821947; + _theResult___fst_exp__h821944; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901; @@ -41745,49 +41745,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = 11'd0; endcase end - always@(guard__h813721 or - _theResult___fst_exp__h821947 or - out_exp__h822679 or _theResult___exp__h822676) + always@(guard__h813718 or + _theResult___fst_exp__h821944 or + out_exp__h822676 or _theResult___exp__h822673) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 = - _theResult___fst_exp__h821947; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 = + _theResult___fst_exp__h821944; 2'b10: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 = - out_exp__h822679; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 = + out_exp__h822676; 2'b11: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 = - _theResult___exp__h822676; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 = + _theResult___exp__h822673; endcase end - always@(guard__h783486 or - _theResult___fst_exp__h791476 or _theResult___exp__h792156) + always@(guard__h783483 or + _theResult___fst_exp__h791473 or _theResult___exp__h792153) begin - case (guard__h783486) + case (guard__h783483) 2'b0: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200 = - _theResult___fst_exp__h791476; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200 = + _theResult___fst_exp__h791473; 2'b01, 2'b10, 2'b11: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200 = - _theResult___exp__h792156; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200 = + _theResult___exp__h792153; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h791476 or + _theResult___fst_exp__h791473 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700 or - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200) + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = - _theResult___fst_exp__h791476; + _theResult___fst_exp__h791473; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702; @@ -41796,49 +41796,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = 11'd0; endcase end - always@(guard__h783486 or - _theResult___fst_exp__h791476 or - out_exp__h792159 or _theResult___exp__h792156) + always@(guard__h783483 or + _theResult___fst_exp__h791473 or + out_exp__h792156 or _theResult___exp__h792153) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 = - _theResult___fst_exp__h791476; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 = + _theResult___fst_exp__h791473; 2'b10: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 = - out_exp__h792159; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 = + out_exp__h792156; 2'b11: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 = - _theResult___exp__h792156; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 = + _theResult___exp__h792153; endcase end - always@(guard__h822790 or - _theResult___fst_exp__h830780 or _theResult___exp__h831460) + always@(guard__h822787 or + _theResult___fst_exp__h830777 or _theResult___exp__h831457) begin - case (guard__h822790) + case (guard__h822787) 2'b0: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202 = - _theResult___fst_exp__h830780; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202 = + _theResult___fst_exp__h830777; 2'b01, 2'b10, 2'b11: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202 = - _theResult___exp__h831460; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202 = + _theResult___exp__h831457; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h830780 or + _theResult___fst_exp__h830777 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930 or - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202) + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = - _theResult___fst_exp__h830780; + _theResult___fst_exp__h830777; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932; @@ -41847,44 +41847,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = 11'd0; endcase end - always@(guard__h822790 or - _theResult___fst_exp__h830780 or - out_exp__h831463 or _theResult___exp__h831460) + always@(guard__h822787 or + _theResult___fst_exp__h830777 or + out_exp__h831460 or _theResult___exp__h831457) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = - _theResult___fst_exp__h830780; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 = + _theResult___fst_exp__h830777; 2'b10: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = - out_exp__h831463; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 = + out_exp__h831460; 2'b11: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = - _theResult___exp__h831460; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 = + _theResult___exp__h831457; endcase end - always@(guard__h765105 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765102 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01, 2'b10: - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = - guard__h765105 == 2'b11 && + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + guard__h765102 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765105) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765102) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41894,12 +41894,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205 = - (guard__h765105 == 2'b0) ? + (guard__h765102 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h765105 == 2'b01 || guard__h765105 == 2'b10 || - guard__h765105 == 2'b11) && + (guard__h765102 == 2'b01 || guard__h765102 == 2'b10 || + guard__h765102 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -41910,23 +41910,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774417 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774414 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01, 2'b10: - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = - guard__h774417 == 2'b11 && + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + guard__h774414 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774417) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774414) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41936,12 +41936,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207 = - (guard__h774417 == 2'b0) ? + (guard__h774414 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h774417 == 2'b01 || guard__h774417 == 2'b10 || - guard__h774417 == 2'b11) && + (guard__h774414 == 2'b01 || guard__h774414 == 2'b10 || + guard__h774414 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -41952,23 +41952,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783486 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783483 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01, 2'b10: - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = - guard__h783486 == 2'b11 && + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + guard__h783483 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783486) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783483) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41978,12 +41978,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209 = - (guard__h783486 == 2'b0) ? + (guard__h783483 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h783486 == 2'b01 || guard__h783486 == 2'b10 || - guard__h783486 == 2'b11) && + (guard__h783483 == 2'b01 || guard__h783483 == 2'b10 || + guard__h783483 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -41994,23 +41994,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774417 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774414 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01, 2'b10: - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = - guard__h774417 != 2'b11 || + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + guard__h774414 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774417) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774414) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42020,12 +42020,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211 = - (guard__h774417 == 2'b0) ? + (guard__h774414 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h774417 != 2'b01 && guard__h774417 != 2'b10 && - guard__h774417 != 2'b11 || + guard__h774414 != 2'b01 && guard__h774414 != 2'b10 && + guard__h774414 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42036,23 +42036,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783486 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783483 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01, 2'b10: - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = - guard__h783486 != 2'b11 || + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + guard__h783483 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783486) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783483) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42062,12 +42062,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213 = - (guard__h783486 == 2'b0) ? + (guard__h783483 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h783486 != 2'b01 && guard__h783486 != 2'b10 && - guard__h783486 != 2'b11 || + guard__h783483 != 2'b01 && guard__h783483 != 2'b10 && + guard__h783483 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42078,23 +42078,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765105 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765102 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01, 2'b10: - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = - guard__h765105 != 2'b11 || + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + guard__h765102 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765105) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765102) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42104,12 +42104,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215 = - (guard__h765105 == 2'b0) ? + (guard__h765102 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h765105 != 2'b01 && guard__h765105 != 2'b10 && - guard__h765105 != 2'b11 || + guard__h765102 != 2'b01 && guard__h765102 != 2'b10 && + guard__h765102 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42120,28 +42120,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765105 or - _theResult___snd__h773017 or _theResult___sfd__h773722) + always@(guard__h765102 or + _theResult___snd__h773014 or _theResult___sfd__h773719) begin - case (guard__h765105) + case (guard__h765102) 2'b0: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216 = - _theResult___snd__h773017[56:5]; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216 = + _theResult___snd__h773014[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216 = - _theResult___sfd__h773722; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216 = + _theResult___sfd__h773719; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h773017 or + _theResult___snd__h773014 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726 or - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216) + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = - _theResult___snd__h773017[56:5]; + _theResult___snd__h773014[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728; @@ -42150,48 +42150,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = 52'd0; endcase end - always@(guard__h765105 or - _theResult___snd__h773017 or - out_sfd__h773725 or _theResult___sfd__h773722) + always@(guard__h765102 or + _theResult___snd__h773014 or + out_sfd__h773722 or _theResult___sfd__h773719) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = - _theResult___snd__h773017[56:5]; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 = + _theResult___snd__h773014[56:5]; 2'b10: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = - out_sfd__h773725; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 = + out_sfd__h773722; 2'b11: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = - _theResult___sfd__h773722; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 = + _theResult___sfd__h773719; endcase end - always@(guard__h774417 or sfdin__h782637 or _theResult___sfd__h783373) + always@(guard__h774414 or sfdin__h782634 or _theResult___sfd__h783370) begin - case (guard__h774417) + case (guard__h774414) 2'b0: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h782637[56:5]; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h782634[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h783373; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h783370; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h782637 or + sfdin__h782634 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752 or - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218) + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = - sfdin__h782637[56:5]; + sfdin__h782634[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754; @@ -42200,48 +42200,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = 52'd0; endcase end - always@(guard__h774417 or - sfdin__h782637 or out_sfd__h783376 or _theResult___sfd__h783373) + always@(guard__h774414 or + sfdin__h782634 or out_sfd__h783373 or _theResult___sfd__h783370) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = - sfdin__h782637[56:5]; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h782634[56:5]; 2'b10: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = - out_sfd__h783376; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 = + out_sfd__h783373; 2'b11: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = - _theResult___sfd__h783373; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h783370; endcase end - always@(guard__h783486 or - _theResult___snd__h791422 or _theResult___sfd__h792157) + always@(guard__h783483 or + _theResult___snd__h791419 or _theResult___sfd__h792154) begin - case (guard__h783486) + case (guard__h783483) 2'b0: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220 = - _theResult___snd__h791422[56:5]; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220 = + _theResult___snd__h791419[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220 = - _theResult___sfd__h792157; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220 = + _theResult___sfd__h792154; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h791422 or + _theResult___snd__h791419 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771 or - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220) + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = - _theResult___snd__h791422[56:5]; + _theResult___snd__h791419[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773; @@ -42250,49 +42250,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = 52'd0; endcase end - always@(guard__h783486 or - _theResult___snd__h791422 or - out_sfd__h792160 or _theResult___sfd__h792157) + always@(guard__h783483 or + _theResult___snd__h791419 or + out_sfd__h792157 or _theResult___sfd__h792154) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = - _theResult___snd__h791422[56:5]; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 = + _theResult___snd__h791419[56:5]; 2'b10: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = - out_sfd__h792160; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 = + out_sfd__h792157; 2'b11: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = - _theResult___sfd__h792157; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 = + _theResult___sfd__h792154; endcase end - always@(guard__h735564 or - _theResult___fst_exp__h743790 or _theResult___exp__h744519) + always@(guard__h735561 or + _theResult___fst_exp__h743787 or _theResult___exp__h744516) begin - case (guard__h735564) + case (guard__h735561) 2'b0: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222 = - _theResult___fst_exp__h743790; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222 = + _theResult___fst_exp__h743787; 2'b01, 2'b10, 2'b11: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222 = - _theResult___exp__h744519; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222 = + _theResult___exp__h744516; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h743790 or + _theResult___fst_exp__h743787 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189 or - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222) + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = - _theResult___fst_exp__h743790; + _theResult___fst_exp__h743787; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191; @@ -42301,49 +42301,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = 11'd0; endcase end - always@(guard__h735564 or - _theResult___fst_exp__h743790 or - out_exp__h744522 or _theResult___exp__h744519) + always@(guard__h735561 or + _theResult___fst_exp__h743787 or + out_exp__h744519 or _theResult___exp__h744516) begin - case (guard__h735564) + case (guard__h735561) 2'b0, 2'b01: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = - _theResult___fst_exp__h743790; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 = + _theResult___fst_exp__h743787; 2'b10: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = - out_exp__h744522; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 = + out_exp__h744519; 2'b11: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = - _theResult___exp__h744519; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 = + _theResult___exp__h744516; endcase end - always@(guard__h744633 or - _theResult___fst_exp__h752623 or _theResult___exp__h753303) + always@(guard__h744630 or + _theResult___fst_exp__h752620 or _theResult___exp__h753300) begin - case (guard__h744633) + case (guard__h744630) 2'b0: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224 = - _theResult___fst_exp__h752623; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224 = + _theResult___fst_exp__h752620; 2'b01, 2'b10, 2'b11: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224 = - _theResult___exp__h753303; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224 = + _theResult___exp__h753300; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h752623 or + _theResult___fst_exp__h752620 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220 or - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224) + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = - _theResult___fst_exp__h752623; + _theResult___fst_exp__h752620; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222; @@ -42352,49 +42352,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = 11'd0; endcase end - always@(guard__h744633 or - _theResult___fst_exp__h752623 or - out_exp__h753306 or _theResult___exp__h753303) + always@(guard__h744630 or + _theResult___fst_exp__h752620 or + out_exp__h753303 or _theResult___exp__h753300) begin - case (guard__h744633) + case (guard__h744630) 2'b0, 2'b01: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = - _theResult___fst_exp__h752623; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 = + _theResult___fst_exp__h752620; 2'b10: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = - out_exp__h753306; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 = + out_exp__h753303; 2'b11: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = - _theResult___exp__h753303; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 = + _theResult___exp__h753300; endcase end - always@(guard__h726252 or - _theResult___snd__h734164 or _theResult___sfd__h734869) + always@(guard__h726249 or + _theResult___snd__h734161 or _theResult___sfd__h734866) begin - case (guard__h726252) + case (guard__h726249) 2'b0: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226 = - _theResult___snd__h734164[56:5]; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226 = + _theResult___snd__h734161[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226 = - _theResult___sfd__h734869; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226 = + _theResult___sfd__h734866; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h734164 or + _theResult___snd__h734161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246 or - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226) + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = - _theResult___snd__h734164[56:5]; + _theResult___snd__h734161[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248; @@ -42403,48 +42403,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = 52'd0; endcase end - always@(guard__h726252 or - _theResult___snd__h734164 or - out_sfd__h734872 or _theResult___sfd__h734869) + always@(guard__h726249 or + _theResult___snd__h734161 or + out_sfd__h734869 or _theResult___sfd__h734866) begin - case (guard__h726252) + case (guard__h726249) 2'b0, 2'b01: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = - _theResult___snd__h734164[56:5]; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 = + _theResult___snd__h734161[56:5]; 2'b10: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = - out_sfd__h734872; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 = + out_sfd__h734869; 2'b11: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = - _theResult___sfd__h734869; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 = + _theResult___sfd__h734866; endcase end - always@(guard__h735564 or sfdin__h743784 or _theResult___sfd__h744520) + always@(guard__h735561 or sfdin__h743781 or _theResult___sfd__h744517) begin - case (guard__h735564) + case (guard__h735561) 2'b0: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228 = - sfdin__h743784[56:5]; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228 = + sfdin__h743781[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228 = - _theResult___sfd__h744520; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228 = + _theResult___sfd__h744517; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h743784 or + sfdin__h743781 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273 or - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228) + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = - sfdin__h743784[56:5]; + sfdin__h743781[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275; @@ -42453,48 +42453,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = 52'd0; endcase end - always@(guard__h735564 or - sfdin__h743784 or out_sfd__h744523 or _theResult___sfd__h744520) + always@(guard__h735561 or + sfdin__h743781 or out_sfd__h744520 or _theResult___sfd__h744517) begin - case (guard__h735564) + case (guard__h735561) 2'b0, 2'b01: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 = - sfdin__h743784[56:5]; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 = + sfdin__h743781[56:5]; 2'b10: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 = - out_sfd__h744523; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 = + out_sfd__h744520; 2'b11: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 = - _theResult___sfd__h744520; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 = + _theResult___sfd__h744517; endcase end - always@(guard__h744633 or - _theResult___snd__h752569 or _theResult___sfd__h753304) + always@(guard__h744630 or + _theResult___snd__h752566 or _theResult___sfd__h753301) begin - case (guard__h744633) + case (guard__h744630) 2'b0: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230 = - _theResult___snd__h752569[56:5]; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230 = + _theResult___snd__h752566[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230 = - _theResult___sfd__h753304; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230 = + _theResult___sfd__h753301; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h752569 or + _theResult___snd__h752566 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292 or - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230) + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = - _theResult___snd__h752569[56:5]; + _theResult___snd__h752566[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294; @@ -42503,49 +42503,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = 52'd0; endcase end - always@(guard__h744633 or - _theResult___snd__h752569 or - out_sfd__h753307 or _theResult___sfd__h753304) + always@(guard__h744630 or + _theResult___snd__h752566 or + out_sfd__h753304 or _theResult___sfd__h753301) begin - case (guard__h744633) + case (guard__h744630) 2'b0, 2'b01: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 = - _theResult___snd__h752569[56:5]; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 = + _theResult___snd__h752566[56:5]; 2'b10: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 = - out_sfd__h753307; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 = + out_sfd__h753304; 2'b11: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 = - _theResult___sfd__h753304; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 = + _theResult___sfd__h753301; endcase end - always@(guard__h804409 or - _theResult___snd__h812321 or _theResult___sfd__h813026) + always@(guard__h804406 or + _theResult___snd__h812318 or _theResult___sfd__h813023) begin - case (guard__h804409) + case (guard__h804406) 2'b0: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232 = - _theResult___snd__h812321[56:5]; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232 = + _theResult___snd__h812318[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232 = - _theResult___sfd__h813026; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232 = + _theResult___sfd__h813023; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h812321 or + _theResult___snd__h812318 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956 or - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232) + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = - _theResult___snd__h812321[56:5]; + _theResult___snd__h812318[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958; @@ -42554,48 +42554,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = 52'd0; endcase end - always@(guard__h804409 or - _theResult___snd__h812321 or - out_sfd__h813029 or _theResult___sfd__h813026) + always@(guard__h804406 or + _theResult___snd__h812318 or + out_sfd__h813026 or _theResult___sfd__h813023) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = - _theResult___snd__h812321[56:5]; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 = + _theResult___snd__h812318[56:5]; 2'b10: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = - out_sfd__h813029; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 = + out_sfd__h813026; 2'b11: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = - _theResult___sfd__h813026; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 = + _theResult___sfd__h813023; endcase end - always@(guard__h813721 or sfdin__h821941 or _theResult___sfd__h822677) + always@(guard__h813718 or sfdin__h821938 or _theResult___sfd__h822674) begin - case (guard__h813721) + case (guard__h813718) 2'b0: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234 = - sfdin__h821941[56:5]; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234 = + sfdin__h821938[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234 = - _theResult___sfd__h822677; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234 = + _theResult___sfd__h822674; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h821941 or + sfdin__h821938 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982 or - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234) + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = - sfdin__h821941[56:5]; + sfdin__h821938[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984; @@ -42604,24 +42604,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = 52'd0; endcase end - always@(guard__h813721 or - sfdin__h821941 or out_sfd__h822680 or _theResult___sfd__h822677) + always@(guard__h813718 or + sfdin__h821938 or out_sfd__h822677 or _theResult___sfd__h822674) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = - sfdin__h821941[56:5]; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 = + sfdin__h821938[56:5]; 2'b10: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = - out_sfd__h822680; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 = + out_sfd__h822677; 2'b11: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = - _theResult___sfd__h822677; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 = + _theResult___sfd__h822674; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -42656,28 +42656,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d14985; endcase end - always@(guard__h822790 or - _theResult___snd__h830726 or _theResult___sfd__h831461) + always@(guard__h822787 or + _theResult___snd__h830723 or _theResult___sfd__h831458) begin - case (guard__h822790) + case (guard__h822787) 2'b0: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236 = - _theResult___snd__h830726[56:5]; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236 = + _theResult___snd__h830723[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236 = - _theResult___sfd__h831461; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236 = + _theResult___sfd__h831458; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h830726 or + _theResult___snd__h830723 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001 or - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236) + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = - _theResult___snd__h830726[56:5]; + _theResult___snd__h830723[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003; @@ -42686,25 +42686,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = 52'd0; endcase end - always@(guard__h822790 or - _theResult___snd__h830726 or - out_sfd__h831464 or _theResult___sfd__h831461) + always@(guard__h822787 or + _theResult___snd__h830723 or + out_sfd__h831461 or _theResult___sfd__h831458) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = - _theResult___snd__h830726[56:5]; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 = + _theResult___snd__h830723[56:5]; 2'b10: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = - out_sfd__h831464; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 = + out_sfd__h831461; 2'b11: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = - _theResult___sfd__h831461; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 = + _theResult___sfd__h831458; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43256,10 +43256,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h942684 or + always@(k__h942679 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h942684) + case (k__h942679) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__097_ETC___d20984 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -43279,10 +43279,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h942684 or + always@(k__h942679 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h942684) + case (k__h942679) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0973_co_ETC___d21007 = coreFix_aluExe_0_rsAlu$canEnq; @@ -43499,7 +43499,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h966426 or + always@(idx__h966421 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21423 or coreFix_aluExe_0_rsAlu$canEnq or @@ -43509,7 +43509,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0049_BITS_267_TO_ETC___d21428 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h966426) + case (idx__h966421) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0047_AN_ETC___d21451 = fetchStage$pipelines_0_canDeq && @@ -43613,15 +43613,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1068_AND__ETC___d21413; endcase end - always@(k__h942684 or + always@(k__h942679 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h942684) + case (k__h942679) 1'd0: - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -43657,7 +43657,7 @@ module mkCore(CLK, regRenamingTable_RDY_rename_0_getRename__0810__ETC___d21625; endcase end - always@(idx__h966426 or + always@(idx__h966421 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -43667,7 +43667,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21682 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h966426) + case (idx__h966421) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__004_ETC___d21687 = (!fetchStage$pipelines_0_canDeq || @@ -44039,87 +44039,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_1[63:0]; - endcase - end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_1[63:0]; - endcase - end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_1[127:64]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_1[127:64]; - endcase - end - always@(commitStage_commitTrap or - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448) - begin - case (commitStage_commitTrap[36:32]) - 5'd0, 5'd3: - trap_val__h994359 = - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448; - 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h994359 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h994359 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h994359 = 64'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = - 3'd0; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -44346,6 +44265,87 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0]; endcase end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_1[63:0]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_1[63:0]; + endcase + end + always@(commitStage_commitTrap or + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, 5'd3: + trap_val__h994354 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448; + 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: + trap_val__h994354 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h994354 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h994354 = 64'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = + 3'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -45825,17 +45825,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h857278 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h857278 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h857278 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h857278 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h857275 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h857275 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h857275 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h857275 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h857278 = + thin_reserved__h857275 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17009; - 5'd28: thin_reserved__h857278 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h857278 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h857278 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h857278 = + 5'd28: thin_reserved__h857275 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h857275 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h857275 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h857275 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17015; endcase end @@ -45849,17 +45849,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h896912 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h896912 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h896912 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h896912 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h896908 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h896908 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h896908 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h896908 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h896912 = + thin_reserved__h896908 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17009; - 5'd28: thin_reserved__h896912 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h896912 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h896912 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h896912 = + 5'd28: thin_reserved__h896908 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h896908 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h896908 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h896908 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17015; endcase end @@ -45873,17 +45873,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h857526 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h857526 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h857526 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h857526 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h857523 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h857523 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h857523 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h857523 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h857526 = + thin_perms_soft__h857523 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16695; - 5'd28: thin_perms_soft__h857526 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h857526 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h857526 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h857526 = + 5'd28: thin_perms_soft__h857523 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h857523 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h857523 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h857523 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16701; endcase end @@ -45897,17 +45897,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h897088 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h897088 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h897088 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h897088 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h897084 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h897084 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h897084 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h897084 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h897088 = + thin_perms_soft__h897084 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16695; - 5'd28: thin_perms_soft__h897088 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h897088 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h897088 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h897088 = + 5'd28: thin_perms_soft__h897084 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h897084 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h897084 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h897084 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16701; endcase end @@ -45921,17 +45921,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h857274 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h857274 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h857274 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h857274 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h857271 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h857271 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h857271 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h857271 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h857274 = + thin_address__h857271 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16651; - 5'd28: thin_address__h857274 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h857274 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h857274 = csrf_mScratchC_reg[151:86]; - default: thin_address__h857274 = + 5'd28: thin_address__h857271 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h857271 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h857271 = csrf_mScratchC_reg[151:86]; + default: thin_address__h857271 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16657; endcase end @@ -45945,17 +45945,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h896908 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h896908 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h896908 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h896908 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h896904 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h896904 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h896904 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h896904 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h896908 = + thin_address__h896904 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16651; - 5'd28: thin_address__h896908 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h896908 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h896908 = csrf_mScratchC_reg[151:86]; - default: thin_address__h896908 = + 5'd28: thin_address__h896904 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h896904 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h896904 = csrf_mScratchC_reg[151:86]; + default: thin_address__h896904 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16657; endcase end @@ -45969,17 +45969,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h859273 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h859273 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h859273 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h859273 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h859270 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h859270 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h859270 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h859270 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h859273 = + thin_bounds_baseBits__h859270 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17102; - 5'd28: thin_bounds_baseBits__h859273 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h859273 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h859273 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h859273 = + 5'd28: thin_bounds_baseBits__h859270 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h859270 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h859270 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h859270 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17108; endcase end @@ -45993,17 +45993,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h898315 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h898315 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h898315 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h898315 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h898311 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h898311 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h898311 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h898311 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h898315 = + thin_bounds_baseBits__h898311 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17102; - 5'd28: thin_bounds_baseBits__h898315 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h898315 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h898315 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h898315 = + 5'd28: thin_bounds_baseBits__h898311 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h898311 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h898311 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h898311 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17108; endcase end @@ -46017,17 +46017,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h859272 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h859272 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h859272 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h859272 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h859269 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h859269 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h859269 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h859269 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h859272 = + thin_bounds_topBits__h859269 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17126; - 5'd28: thin_bounds_topBits__h859272 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h859272 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h859272 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h859272 = + 5'd28: thin_bounds_topBits__h859269 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h859269 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h859269 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h859269 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132; endcase end @@ -46041,17 +46041,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h898314 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h898314 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h898314 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h898314 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h898310 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h898310 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h898310 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h898310 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h898314 = + thin_bounds_topBits__h898310 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17126; - 5'd28: thin_bounds_topBits__h898314 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h898314 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h898314 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h898314 = + 5'd28: thin_bounds_topBits__h898310 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h898310 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h898310 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h898310 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132; endcase end @@ -46065,17 +46065,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h857275 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h857275 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h857275 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h857275 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h857272 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h857272 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h857272 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h857272 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h857275 = + thin_addrBits__h857272 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16673; - 5'd28: thin_addrBits__h857275 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h857275 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h857275 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h857275 = + 5'd28: thin_addrBits__h857272 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h857272 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h857272 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h857272 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16679; endcase end @@ -46089,17 +46089,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h896909 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h896909 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h896909 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h896909 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h896905 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h896905 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h896905 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h896905 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h896909 = + thin_addrBits__h896905 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16673; - 5'd28: thin_addrBits__h896909 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h896909 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h896909 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h896909 = + 5'd28: thin_addrBits__h896905 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h896905 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h896905 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h896905 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16679; endcase end @@ -46683,17 +46683,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h857279 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h857279 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h857279 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h857279 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h857276 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h857276 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h857276 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h857276 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h857279 = + thin_otype__h857276 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17031; - 5'd28: thin_otype__h857279 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h857279 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h857279 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h857279 = + 5'd28: thin_otype__h857276 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h857276 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h857276 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h857276 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17037; endcase end @@ -46707,17 +46707,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h896913 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h896913 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h896913 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h896913 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h896909 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h896909 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h896909 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h896909 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h896913 = + thin_otype__h896909 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17031; - 5'd28: thin_otype__h896913 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h896913 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h896913 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h896913 = + 5'd28: thin_otype__h896909 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h896909 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h896909 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h896909 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17037; endcase end @@ -46808,99 +46808,13 @@ module mkCore(CLK, { 2'd3, mmio_dataReqQ_data_0[148:145] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 = - 4'd15; - endcase - end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[7:3]) - 5'd0, - 5'd1, - 5'd2, - 5'd3, - 5'd4, - 5'd5, - 5'd6, - 5'd7, - 5'd8, - 5'd9, - 5'd10, - 5'd11, - 5'd16, - 5'd17, - 5'd18, - 5'd19, - 5'd20, - 5'd21, - 5'd22, - 5'd23, - 5'd24, - 5'd25, - 5'd26: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 = - coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 = - 5'd27; - endcase - end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[7:3]) - 5'd0, - 5'd1, - 5'd2, - 5'd3, - 5'd4, - 5'd5, - 5'd6, - 5'd7, - 5'd8, - 5'd9, - 5'd11, - 5'd12, - 5'd13, - 5'd15: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332 = - coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332 = - 5'd28; - endcase - end - always@(coreFix_memExe_lsq$firstLd or - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332) - begin - case (coreFix_memExe_lsq$firstLd[15:14]) - 2'd0: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 = - { 2'd0, - coreFix_memExe_lsq$firstLd[13:8], - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 }; - 2'd1: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 = - { coreFix_memExe_lsq$firstLd[15:14], - 6'h2A, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332 }; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 = - { 9'd298, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 }; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 = 4'd15; endcase end @@ -46930,9 +46844,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 = 5'd27; endcase end @@ -46953,31 +46867,117 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstSt or - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336) + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332) begin case (coreFix_memExe_lsq$firstSt[12:11]) 2'd0: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = { 2'd0, coreFix_memExe_lsq$firstSt[10:5], - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 }; 2'd1: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = { coreFix_memExe_lsq$firstSt[12:11], 6'h2A, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 }; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 }; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = { 9'd298, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 }; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[7:3]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 = + coreFix_memExe_lsq$firstLd[7:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 = + 5'd27; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[7:3]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd11, + 5'd12, + 5'd13, + 5'd15: + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 = + coreFix_memExe_lsq$firstLd[7:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 = + 5'd28; + endcase + end + always@(coreFix_memExe_lsq$firstLd or + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336) + begin + case (coreFix_memExe_lsq$firstLd[15:14]) + 2'd0: + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { 2'd0, + coreFix_memExe_lsq$firstLd[13:8], + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 }; + 2'd1: + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { coreFix_memExe_lsq$firstLd[15:14], + 6'h2A, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 }; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { 9'd298, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 }; endcase end always@(mmioToPlatform_pRq_enq_x) @@ -55802,17 +55802,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254401); + $write("'h%h", value__h254399); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254565); + $write("'h%h", value__h254563); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h254677[64:0]); + $write("'h%h", x__h254675[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -57606,14 +57606,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h213381 = $time; + v__h213380 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h213381, "[doRespLdMem]", " "); + $write("%t : ", v__h213380, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212809); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212808); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -57752,15 +57752,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h215650 = $time; + v__h215649 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h215650, "[doRespLdForward]", " "); + $write("%t : ", v__h215649, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h215095); + $write("'h%h", t__h215094); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -57985,17 +57985,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239635); + $write("'h%h", value__h239634); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239799); + $write("'h%h", value__h239798); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h239911[64:0]); + $write("'h%h", x__h239910[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58035,17 +58035,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240792); + $write("'h%h", value__h240791); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240956); + $write("'h%h", value__h240955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h241068[64:0]); + $write("'h%h", x__h241067[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -66194,14 +66194,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) begin - v__h271867 = $time; + v__h271864 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) - $write("%t : [Ld resp] ", v__h271867); + $write("%t : [Ld resp] ", v__h271864); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -67841,13 +67841,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) begin - v__h347385 = $time; + v__h347382 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) - $write("%t : [Ld resp] ", v__h347385); + $write("%t : [Ld resp] ", v__h347382); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) @@ -69721,7 +69721,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h423711 = $time; + v__h423708 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -69729,7 +69729,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h423711); + $write("%t : [Ld resp] ", v__h423708); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -72133,7 +72133,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h836568 == 2'd0) + v__h836565 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index 85d3746..fb00579 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:47:29 BST 2020 +// On Wed Jun 24 20:36:49 BST 2020 // // // Ports: @@ -81,18 +81,22 @@ // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 +// cpu_imem_master_bvalid I 1 // cpu_imem_master_bid I 6 // cpu_imem_master_bresp I 2 // cpu_imem_master_arready I 1 +// cpu_imem_master_rvalid I 1 // cpu_imem_master_rid I 6 // cpu_imem_master_rdata I 64 // cpu_imem_master_rresp I 2 // cpu_imem_master_rlast I 1 // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 +// cpu_dmem_master_bvalid I 1 // cpu_dmem_master_bid I 6 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 +// cpu_dmem_master_rvalid I 1 // cpu_dmem_master_rid I 6 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg @@ -120,10 +124,6 @@ // ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 // EN_start I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_rvalid I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_rvalid I 1 // EN_dmi_read_addr I 1 // EN_dmi_write I 1 // EN_ndm_reset_client_response_put I 1 @@ -197,9 +197,9 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_imem_master_wready, + cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, - cpu_imem_master_bvalid, cpu_imem_master_bready, @@ -227,11 +227,11 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_imem_master_arready, + cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, - cpu_imem_master_rvalid, cpu_imem_master_rready, @@ -269,9 +269,9 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_dmem_master_wready, + cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, - cpu_dmem_master_bvalid, cpu_dmem_master_bready, @@ -299,11 +299,11 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_dmem_master_arready, + cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, - cpu_dmem_master_rvalid, cpu_dmem_master_rready, @@ -434,9 +434,9 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_imem_master_wready; // action method cpu_imem_master_b_bflit + input cpu_imem_master_bvalid; input [5 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; - input cpu_imem_master_bvalid; // value method cpu_imem_master_b_bready output cpu_imem_master_bready; @@ -480,11 +480,11 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_imem_master_arready; // action method cpu_imem_master_r_rflit + input cpu_imem_master_rvalid; input [5 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; - input cpu_imem_master_rvalid; // value method cpu_imem_master_r_rready output cpu_imem_master_rready; @@ -545,9 +545,9 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_dmem_master_wready; // action method cpu_dmem_master_b_bflit + input cpu_dmem_master_bvalid; input [5 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; - input cpu_dmem_master_bvalid; // value method cpu_dmem_master_b_bready output cpu_dmem_master_bready; @@ -591,11 +591,11 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_dmem_master_arready; // action method cpu_dmem_master_r_rflit + input cpu_dmem_master_rvalid; input [5 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; - input cpu_dmem_master_rvalid; // value method cpu_dmem_master_r_rready output cpu_dmem_master_rready; @@ -746,6 +746,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // inlined wires wire [172 : 0] split_0_doPut$wget, split_1_doPut$wget, split_2_doPut$wget; + wire [171 : 0] merged_0_outflit$wget, merged_1_outflit$wget; wire [99 : 0] tagController_tmp_shimMaster_arff_rv$port0__write_1, tagController_tmp_shimMaster_arff_rv$port1__read, tagController_tmp_shimMaster_arff_rv$port2__read, @@ -762,29 +763,36 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_awff_rv$port1__read, tagController_tmp_shimSlave_awff_rv$port2__read, tagController_tmp_shimSlave_awff_rv$port3__read, - ug_uncached_mem_shim_master_u_ar_peekWire$wget, - ug_uncached_mem_shim_master_u_aw_peekWire$wget; - wire [97 : 0] ssNoSynth_0_ar_buffer_enqw$wget, - ssNoSynth_1_ar_buffer_enqw$wget, - ssNoSynth_1_aw_buffer_enqw$wget, - ssNoSynth_2_ar_buffer_enqw$wget, - ssNoSynth_2_aw_buffer_enqw$wget, + uncached_mem_master_arSynth_src_peekWire$wget, + uncached_mem_master_awSynth_src_peekWire$wget; + wire [97 : 0] slave_vector_0_arSynth_snk_putWire$wget, + slave_vector_0_awSynth_snk_putWire$wget, + ssNoSynth_0_arNoSynth_buffer_enqw$wget, + ssNoSynth_1_arNoSynth_buffer_enqw$wget, + ssNoSynth_1_arNoSynth_src_peekWire$wget, + ssNoSynth_1_awNoSynth_src_peekWire$wget, + ssNoSynth_2_arNoSynth_buffer_enqw$wget, + ssNoSynth_2_arNoSynth_src_peekWire$wget, + ssNoSynth_2_awNoSynth_src_peekWire$wget, tagController_tmp_ug_slave_u_ar_putWire$wget, - tagController_tmp_ug_slave_u_aw_putWire$wget; - wire [96 : 0] ifcs_0_1_noRoute_currentReq$port0__write_1, - ifcs_0_1_noRoute_currentReq$port1__read, - ifcs_0_noRoute_inner_currentReq$port0__write_1, + tagController_tmp_ug_slave_u_aw_putWire$wget, + tmp2_arNoSynth_buffer_enqw$wget, + tmp2_awNoSynth_buffer_enqw$wget; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$port1__read, ifcs_0_noRoute_inner_currentReq$port1__read, - ifcs_1_1_noRoute_currentReq$port0__write_1, ifcs_1_1_noRoute_currentReq$port1__read, - ifcs_1_noRoute_inner_currentReq$port0__write_1, - ifcs_1_noRoute_inner_currentReq$port1__read; + ifcs_1_noRoute_inner_currentReq$port1__read, + msNoSynth_1_arNoSynth_buffer_enqw$wget, + msNoSynth_1_awNoSynth_buffer_enqw$wget; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, tagController_tmp_shimSlave_wff_rv$port1__read, tagController_tmp_shimSlave_wff_rv$port2__read, tagController_tmp_shimSlave_wff_rv$port3__read; - wire [73 : 0] ssNoSynth_1_w_buffer_enqw$wget, - ssNoSynth_2_w_buffer_enqw$wget, + wire [73 : 0] msNoSynth_1_wNoSynth_buffer_enqw$wget, + proc_uncached_wSynth_src_peekWire$wget, + slave_vector_0_wSynth_snk_putWire$wget, + ssNoSynth_1_wNoSynth_src_peekWire$wget, + ssNoSynth_2_wNoSynth_src_peekWire$wget, tagController_tmp_shimMaster_rff_rv$port0__write_1, tagController_tmp_shimMaster_rff_rv$port1__read, tagController_tmp_shimMaster_rff_rv$port2__read, @@ -797,13 +805,17 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_rff_rv$port1__read, tagController_tmp_shimSlave_rff_rv$port2__read, tagController_tmp_shimSlave_rff_rv$port3__read, - tagController_tmp_ug_slave_u_w_putWire$wget; - wire [72 : 0] tagController_tmp_ug_master_u_r_putWire$wget, - tmp2_r_buffer_enqw$wget, - ug_uncached_mem_shim_master_u_r_putWire$wget; - wire [71 : 0] msNoSynth_0_r_buffer_enqw$wget, - msNoSynth_1_r_buffer_enqw$wget, - tmp0_r_buffer_enqw$wget; + tagController_tmp_ug_slave_u_w_putWire$wget, + tmp2_wNoSynth_buffer_enqw$wget; + wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_enqw$wget, + ssNoSynth_2_rNoSynth_buffer_enqw$wget, + tagController_tmp_ug_master_u_r_putWire$wget, + tmp2_rNoSynth_src_peekWire$wget, + uncached_mem_master_rSynth_snk_putWire$wget; + wire [71 : 0] msNoSynth_0_rNoSynth_buffer_enqw$wget, + msNoSynth_1_rNoSynth_buffer_enqw$wget, + msNoSynth_1_rNoSynth_src_peekWire$wget, + proc_uncached_rSynth_snk_putWire$wget; wire [8 : 0] ifcs_0_1_noRoute_flitCount$port0__write_1, ifcs_0_1_noRoute_flitCount$port1__write_1, ifcs_0_1_noRoute_flitCount$port2__read, @@ -819,12 +831,18 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_bff_rv$port2__read, tagController_tmp_shimSlave_bff_rv$port3__read, tagController_tmp_ug_master_u_b_putWire$wget, - ug_uncached_mem_shim_master_u_b_putWire$wget; - wire [6 : 0] tmp2_b_buffer_enqw$wget; - wire [5 : 0] msNoSynth_0_b_buffer_enqw$wget, - msNoSynth_1_b_buffer_enqw$wget, - tmp0_b_buffer_enqw$wget; - wire flitToSink_0$whas, + uncached_mem_master_bSynth_snk_putWire$wget; + wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_enqw$wget, + ssNoSynth_2_bNoSynth_buffer_enqw$wget, + tmp2_bNoSynth_src_peekWire$wget; + wire [5 : 0] msNoSynth_0_bNoSynth_buffer_enqw$wget, + msNoSynth_1_bNoSynth_buffer_enqw$wget, + msNoSynth_1_bNoSynth_src_peekWire$wget, + proc_uncached_bSynth_snk_putWire$wget; + wire cached_mem_master_arSynth_src_dropWire$whas, + cached_mem_master_awSynth_src_dropWire$whas, + cached_mem_master_wSynth_src_dropWire$whas, + flitToSink_0$whas, flitToSink_1$whas, flitToSink_1_0$whas, flitToSink_1_0_1$whas, @@ -834,24 +852,22 @@ module mkCoreW(RST_N_dm_power_on_reset, flitToSink_1_1_1_1$whas, flitToSink_1_2$whas, flitToSink_2$whas, + ifcs_0_1_snk_putWire$whas, ifcs_0_noRoute_inner_currentReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$port1__read, ifcs_0_noRoute_inner_pendingReq$port2__read, + ifcs_0_snk_putWire$whas, + ifcs_1_1_snk_putWire$whas, ifcs_1_noRoute_inner_currentReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$port1__read, ifcs_1_noRoute_inner_pendingReq$port2__read, + ifcs_1_snk_putWire$whas, merged_0_doDrop$whas, merged_1_doDrop$whas, - msNoSynth_0_ar_dwReady$whas, - msNoSynth_0_b_buffer_enqw$whas, - msNoSynth_0_r_buffer_enqw$whas, - msNoSynth_0_w_dwReady$whas, - msNoSynth_1_ar_dwReady$whas, - msNoSynth_1_b_buffer_enqw$whas, - msNoSynth_1_r_buffer_enqw$whas, - msNoSynth_1_w_dwReady$whas, + msNoSynth_0_arNoSynth_buffer_dequeueing$whas, + msNoSynth_1_arNoSynth_buffer_dequeueing$whas, reqWires_0$wget, reqWires_1$wget, reqWires_1_0$wget, @@ -867,35 +883,25 @@ module mkCoreW(RST_N_dm_power_on_reset, sourceSelect_1_1$whas, sourceSelect_1_1_1$whas, sourceSelect_1_2$whas, - ssNoSynth_0_b_dwReady$whas, - ssNoSynth_0_r_dwReady$whas, - ssNoSynth_0_w_buffer_enqw$whas, - ssNoSynth_1_b_dwReady$whas, - ssNoSynth_1_r_dwReady$whas, - ssNoSynth_1_w_buffer_enqw$whas, - ssNoSynth_2_b_dwReady$whas, - ssNoSynth_2_r_dwReady$whas, - ssNoSynth_2_w_buffer_enqw$whas, + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_0_wNoSynth_buffer_enqw$whas, + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_1_wNoSynth_buffer_enqw$whas, + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_2_wNoSynth_buffer_enqw$whas, tagController_tmp_shimMaster_arff_rv$EN_port0__write, tagController_tmp_shimMaster_awff_rv$EN_port0__write, tagController_tmp_shimMaster_wff_rv$EN_port0__write, tagController_tmp_shimSlave_bff_rv$EN_port0__write, tagController_tmp_shimSlave_rff_rv$EN_port0__write, - tagController_tmp_ug_master_u_ar_dropWire$whas, - tagController_tmp_ug_master_u_aw_dropWire$whas, - tagController_tmp_ug_master_u_b_putWire$whas, - tagController_tmp_ug_master_u_r_putWire$whas, - tagController_tmp_ug_master_u_w_dropWire$whas, - tmp0_ar_dwReady$whas, - tmp0_aw_dwReady$whas, - tmp0_b_buffer_enqw$whas, - tmp0_r_buffer_enqw$whas, - tmp0_w_dwReady$whas, - ug_uncached_mem_shim_master_u_ar_dropWire$whas, - ug_uncached_mem_shim_master_u_aw_dropWire$whas, - ug_uncached_mem_shim_master_u_b_putWire$whas, - ug_uncached_mem_shim_master_u_r_putWire$whas, - ug_uncached_mem_shim_master_u_w_dropWire$whas; + uncached_mem_master_arSynth_src_dropWire$whas, + uncached_mem_master_awSynth_src_dropWire$whas, + uncached_mem_master_bSynth_snk_putWire$whas, + uncached_mem_master_rSynth_snk_putWire$whas, + uncached_mem_master_wSynth_src_dropWire$whas; // register activeSource_0 reg activeSource_0; @@ -1469,57 +1475,177 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_2_rspBack$ENQ, ifcs_2_rspBack$FULL_N; - // ports of submodule msNoSynth_0_b_buffer_ff - wire [5 : 0] msNoSynth_0_b_buffer_ff$D_IN, msNoSynth_0_b_buffer_ff$D_OUT; - wire msNoSynth_0_b_buffer_ff$CLR, - msNoSynth_0_b_buffer_ff$DEQ, - msNoSynth_0_b_buffer_ff$EMPTY_N, - msNoSynth_0_b_buffer_ff$ENQ, - msNoSynth_0_b_buffer_ff$FULL_N; + // ports of submodule merged_0_awff + wire [96 : 0] merged_0_awff$D_IN, merged_0_awff$D_OUT; + wire merged_0_awff$CLR, + merged_0_awff$DEQ, + merged_0_awff$EMPTY_N, + merged_0_awff$ENQ, + merged_0_awff$FULL_N; - // ports of submodule msNoSynth_0_b_buffer_firstValid - wire msNoSynth_0_b_buffer_firstValid$D_IN, - msNoSynth_0_b_buffer_firstValid$EN, - msNoSynth_0_b_buffer_firstValid$Q_OUT; + // ports of submodule merged_0_wff + wire [73 : 0] merged_0_wff$D_IN, merged_0_wff$D_OUT; + wire merged_0_wff$CLR, + merged_0_wff$DEQ, + merged_0_wff$EMPTY_N, + merged_0_wff$ENQ, + merged_0_wff$FULL_N; - // ports of submodule msNoSynth_0_r_buffer_ff - wire [71 : 0] msNoSynth_0_r_buffer_ff$D_IN, msNoSynth_0_r_buffer_ff$D_OUT; - wire msNoSynth_0_r_buffer_ff$CLR, - msNoSynth_0_r_buffer_ff$DEQ, - msNoSynth_0_r_buffer_ff$EMPTY_N, - msNoSynth_0_r_buffer_ff$ENQ, - msNoSynth_0_r_buffer_ff$FULL_N; + // ports of submodule merged_1_awff + wire [96 : 0] merged_1_awff$D_IN, merged_1_awff$D_OUT; + wire merged_1_awff$CLR, + merged_1_awff$DEQ, + merged_1_awff$EMPTY_N, + merged_1_awff$ENQ, + merged_1_awff$FULL_N; - // ports of submodule msNoSynth_0_r_buffer_firstValid - wire msNoSynth_0_r_buffer_firstValid$D_IN, - msNoSynth_0_r_buffer_firstValid$EN, - msNoSynth_0_r_buffer_firstValid$Q_OUT; + // ports of submodule merged_1_wff + wire [73 : 0] merged_1_wff$D_IN, merged_1_wff$D_OUT; + wire merged_1_wff$CLR, + merged_1_wff$DEQ, + merged_1_wff$EMPTY_N, + merged_1_wff$ENQ, + merged_1_wff$FULL_N; - // ports of submodule msNoSynth_1_b_buffer_ff - wire [5 : 0] msNoSynth_1_b_buffer_ff$D_IN, msNoSynth_1_b_buffer_ff$D_OUT; - wire msNoSynth_1_b_buffer_ff$CLR, - msNoSynth_1_b_buffer_ff$DEQ, - msNoSynth_1_b_buffer_ff$EMPTY_N, - msNoSynth_1_b_buffer_ff$ENQ, - msNoSynth_1_b_buffer_ff$FULL_N; + // ports of submodule msNoSynth_0_arNoSynth_buffer_ff + wire [96 : 0] msNoSynth_0_arNoSynth_buffer_ff$D_IN, + msNoSynth_0_arNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_arNoSynth_buffer_ff$CLR, + msNoSynth_0_arNoSynth_buffer_ff$DEQ, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_arNoSynth_buffer_ff$ENQ, + msNoSynth_0_arNoSynth_buffer_ff$FULL_N; - // ports of submodule msNoSynth_1_b_buffer_firstValid - wire msNoSynth_1_b_buffer_firstValid$D_IN, - msNoSynth_1_b_buffer_firstValid$EN, - msNoSynth_1_b_buffer_firstValid$Q_OUT; + // ports of submodule msNoSynth_0_arNoSynth_buffer_firstValid + wire msNoSynth_0_arNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_arNoSynth_buffer_firstValid$EN, + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule msNoSynth_1_r_buffer_ff - wire [71 : 0] msNoSynth_1_r_buffer_ff$D_IN, msNoSynth_1_r_buffer_ff$D_OUT; - wire msNoSynth_1_r_buffer_ff$CLR, - msNoSynth_1_r_buffer_ff$DEQ, - msNoSynth_1_r_buffer_ff$EMPTY_N, - msNoSynth_1_r_buffer_ff$ENQ, - msNoSynth_1_r_buffer_ff$FULL_N; + // ports of submodule msNoSynth_0_awNoSynth_buffer_ff + wire [96 : 0] msNoSynth_0_awNoSynth_buffer_ff$D_IN, + msNoSynth_0_awNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_awNoSynth_buffer_ff$CLR, + msNoSynth_0_awNoSynth_buffer_ff$DEQ, + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_awNoSynth_buffer_ff$ENQ, + msNoSynth_0_awNoSynth_buffer_ff$FULL_N; - // ports of submodule msNoSynth_1_r_buffer_firstValid - wire msNoSynth_1_r_buffer_firstValid$D_IN, - msNoSynth_1_r_buffer_firstValid$EN, - msNoSynth_1_r_buffer_firstValid$Q_OUT; + // ports of submodule msNoSynth_0_awNoSynth_buffer_firstValid + wire msNoSynth_0_awNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_awNoSynth_buffer_firstValid$EN, + msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_bNoSynth_buffer_ff + wire [5 : 0] msNoSynth_0_bNoSynth_buffer_ff$D_IN, + msNoSynth_0_bNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_bNoSynth_buffer_ff$CLR, + msNoSynth_0_bNoSynth_buffer_ff$DEQ, + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_bNoSynth_buffer_ff$ENQ, + msNoSynth_0_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_bNoSynth_buffer_firstValid + wire msNoSynth_0_bNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_bNoSynth_buffer_firstValid$EN, + msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_rNoSynth_buffer_ff + wire [71 : 0] msNoSynth_0_rNoSynth_buffer_ff$D_IN, + msNoSynth_0_rNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_rNoSynth_buffer_ff$CLR, + msNoSynth_0_rNoSynth_buffer_ff$DEQ, + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_rNoSynth_buffer_ff$ENQ, + msNoSynth_0_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_rNoSynth_buffer_firstValid + wire msNoSynth_0_rNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_rNoSynth_buffer_firstValid$EN, + msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_wNoSynth_buffer_ff + wire [73 : 0] msNoSynth_0_wNoSynth_buffer_ff$D_IN, + msNoSynth_0_wNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_wNoSynth_buffer_ff$CLR, + msNoSynth_0_wNoSynth_buffer_ff$DEQ, + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_wNoSynth_buffer_ff$ENQ, + msNoSynth_0_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_wNoSynth_buffer_firstValid + wire msNoSynth_0_wNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_wNoSynth_buffer_firstValid$EN, + msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_arNoSynth_buffer_ff + wire [96 : 0] msNoSynth_1_arNoSynth_buffer_ff$D_IN, + msNoSynth_1_arNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_arNoSynth_buffer_ff$CLR, + msNoSynth_1_arNoSynth_buffer_ff$DEQ, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_arNoSynth_buffer_ff$ENQ, + msNoSynth_1_arNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_arNoSynth_buffer_firstValid + wire msNoSynth_1_arNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_arNoSynth_buffer_firstValid$EN, + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_awNoSynth_buffer_ff + wire [96 : 0] msNoSynth_1_awNoSynth_buffer_ff$D_IN, + msNoSynth_1_awNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_awNoSynth_buffer_ff$CLR, + msNoSynth_1_awNoSynth_buffer_ff$DEQ, + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_awNoSynth_buffer_ff$ENQ, + msNoSynth_1_awNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_awNoSynth_buffer_firstValid + wire msNoSynth_1_awNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_awNoSynth_buffer_firstValid$EN, + msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_bNoSynth_buffer_ff + wire [5 : 0] msNoSynth_1_bNoSynth_buffer_ff$D_IN, + msNoSynth_1_bNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_bNoSynth_buffer_ff$CLR, + msNoSynth_1_bNoSynth_buffer_ff$DEQ, + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_bNoSynth_buffer_ff$ENQ, + msNoSynth_1_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_bNoSynth_buffer_firstValid + wire msNoSynth_1_bNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_bNoSynth_buffer_firstValid$EN, + msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_rNoSynth_buffer_ff + wire [71 : 0] msNoSynth_1_rNoSynth_buffer_ff$D_IN, + msNoSynth_1_rNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_rNoSynth_buffer_ff$CLR, + msNoSynth_1_rNoSynth_buffer_ff$DEQ, + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_rNoSynth_buffer_ff$ENQ, + msNoSynth_1_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_rNoSynth_buffer_firstValid + wire msNoSynth_1_rNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_rNoSynth_buffer_firstValid$EN, + msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_wNoSynth_buffer_ff + wire [73 : 0] msNoSynth_1_wNoSynth_buffer_ff$D_IN, + msNoSynth_1_wNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_wNoSynth_buffer_ff$CLR, + msNoSynth_1_wNoSynth_buffer_ff$DEQ, + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_wNoSynth_buffer_ff$ENQ, + msNoSynth_1_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_wNoSynth_buffer_firstValid + wire msNoSynth_1_wNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_wNoSynth_buffer_firstValid$EN, + msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, @@ -1591,7 +1717,10 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip; // ports of submodule proc + wire [96 : 0] proc$master1_ar_peek, proc$master1_aw_peek; wire [76 : 0] proc$hart0_csr_mem_server_request_put; + wire [73 : 0] proc$master1_w_peek; + wire [71 : 0] proc$master1_r_put_val; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; wire [64 : 0] proc$hart0_csr_mem_server_response_get, @@ -1604,10 +1733,6 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awaddr, proc$master0_rdata, proc$master0_wdata, - proc$master1_araddr, - proc$master1_awaddr, - proc$master1_rdata, - proc$master1_wdata, proc$start_fromhostAddr, proc$start_startpc, proc$start_tohostAddr; @@ -1616,10 +1741,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$debug_module_mem_server_wstrb, proc$master0_arlen, proc$master0_awlen, - proc$master0_wstrb, - proc$master1_arlen, - proc$master1_awlen, - proc$master1_wstrb; + proc$master0_wstrb; + wire [5 : 0] proc$master1_b_put_val; wire [4 : 0] proc$debug_module_mem_server_arid, proc$debug_module_mem_server_awid, proc$debug_module_mem_server_bid, @@ -1641,16 +1764,6 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awcache, proc$master0_awqos, proc$master0_awregion, - proc$master1_arcache, - proc$master1_arid, - proc$master1_arqos, - proc$master1_arregion, - proc$master1_awcache, - proc$master1_awid, - proc$master1_awqos, - proc$master1_awregion, - proc$master1_bid, - proc$master1_rid, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, @@ -1659,11 +1772,7 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arprot, proc$master0_arsize, proc$master0_awprot, - proc$master0_awsize, - proc$master1_arprot, - proc$master1_arsize, - proc$master1_awprot, - proc$master1_awsize; + proc$master0_awsize; wire [1 : 0] proc$debug_module_mem_server_arburst, proc$debug_module_mem_server_awburst, proc$debug_module_mem_server_bresp, @@ -1671,11 +1780,7 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arburst, proc$master0_awburst, proc$master0_bresp, - proc$master0_rresp, - proc$master1_arburst, - proc$master1_awburst, - proc$master1_bresp, - proc$master1_rresp; + proc$master0_rresp; wire proc$EN_hart0_csr_mem_server_request_put, proc$EN_hart0_csr_mem_server_response_get, proc$EN_hart0_fpr_mem_server_request_put, @@ -1685,6 +1790,11 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$EN_hart0_put_other_req_put, proc$EN_hart0_run_halt_server_request_put, proc$EN_hart0_run_halt_server_response_get, + proc$EN_master1_ar_drop, + proc$EN_master1_aw_drop, + proc$EN_master1_b_put, + proc$EN_master1_r_put, + proc$EN_master1_w_drop, proc$EN_set_verbosity, proc$EN_start, proc$RDY_hart0_csr_mem_server_request_put, @@ -1693,6 +1803,14 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$RDY_hart0_gpr_mem_server_response_get, proc$RDY_hart0_run_halt_server_request_put, proc$RDY_hart0_run_halt_server_response_get, + proc$RDY_master1_ar_drop, + proc$RDY_master1_ar_peek, + proc$RDY_master1_aw_drop, + proc$RDY_master1_aw_peek, + proc$RDY_master1_b_put, + proc$RDY_master1_r_put, + proc$RDY_master1_w_drop, + proc$RDY_master1_w_peek, proc$RDY_start, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, @@ -1729,21 +1847,11 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_wready, proc$master0_wuser, proc$master0_wvalid, - proc$master1_arlock, - proc$master1_arready, - proc$master1_arvalid, - proc$master1_awlock, - proc$master1_awready, - proc$master1_awvalid, - proc$master1_bready, - proc$master1_bvalid, - proc$master1_rlast, - proc$master1_rready, - proc$master1_ruser, - proc$master1_rvalid, - proc$master1_wlast, - proc$master1_wready, - proc$master1_wvalid, + proc$master1_ar_canPeek, + proc$master1_aw_canPeek, + proc$master1_b_canPut, + proc$master1_r_canPut, + proc$master1_w_canPeek, proc$non_maskable_interrupt_req_set_not_clear, proc$s_external_interrupt_req_set_not_clear, proc$start_running; @@ -1755,122 +1863,215 @@ module mkCoreW(RST_N_dm_power_on_reset, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr; - // ports of submodule ssNoSynth_0_ar_buffer_ff - wire [97 : 0] ssNoSynth_0_ar_buffer_ff$D_IN, ssNoSynth_0_ar_buffer_ff$D_OUT; - wire ssNoSynth_0_ar_buffer_ff$CLR, - ssNoSynth_0_ar_buffer_ff$DEQ, - ssNoSynth_0_ar_buffer_ff$EMPTY_N, - ssNoSynth_0_ar_buffer_ff$ENQ, - ssNoSynth_0_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_0_arNoSynth_buffer_ff$D_IN, + ssNoSynth_0_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_arNoSynth_buffer_ff$CLR, + ssNoSynth_0_arNoSynth_buffer_ff$DEQ, + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_arNoSynth_buffer_ff$ENQ, + ssNoSynth_0_arNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_ar_buffer_firstValid - wire ssNoSynth_0_ar_buffer_firstValid$D_IN, - ssNoSynth_0_ar_buffer_firstValid$EN, - ssNoSynth_0_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_arNoSynth_buffer_firstValid + wire ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_arNoSynth_buffer_firstValid$EN, + ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_0_aw_buffer_ff - wire [97 : 0] ssNoSynth_0_aw_buffer_ff$D_IN, ssNoSynth_0_aw_buffer_ff$D_OUT; - wire ssNoSynth_0_aw_buffer_ff$CLR, - ssNoSynth_0_aw_buffer_ff$DEQ, - ssNoSynth_0_aw_buffer_ff$EMPTY_N, - ssNoSynth_0_aw_buffer_ff$ENQ, - ssNoSynth_0_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_0_awNoSynth_buffer_ff$D_IN, + ssNoSynth_0_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_awNoSynth_buffer_ff$CLR, + ssNoSynth_0_awNoSynth_buffer_ff$DEQ, + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_awNoSynth_buffer_ff$ENQ, + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_aw_buffer_firstValid - wire ssNoSynth_0_aw_buffer_firstValid$D_IN, - ssNoSynth_0_aw_buffer_firstValid$EN, - ssNoSynth_0_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_awNoSynth_buffer_firstValid + wire ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_awNoSynth_buffer_firstValid$EN, + ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_0_w_buffer_ff - wire [73 : 0] ssNoSynth_0_w_buffer_ff$D_IN, ssNoSynth_0_w_buffer_ff$D_OUT; - wire ssNoSynth_0_w_buffer_ff$CLR, - ssNoSynth_0_w_buffer_ff$DEQ, - ssNoSynth_0_w_buffer_ff$EMPTY_N, - ssNoSynth_0_w_buffer_ff$ENQ, - ssNoSynth_0_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_0_bNoSynth_buffer_ff$D_IN, + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_bNoSynth_buffer_ff$CLR, + ssNoSynth_0_bNoSynth_buffer_ff$DEQ, + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_bNoSynth_buffer_ff$ENQ, + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_w_buffer_firstValid - wire ssNoSynth_0_w_buffer_firstValid$D_IN, - ssNoSynth_0_w_buffer_firstValid$EN, - ssNoSynth_0_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_bNoSynth_buffer_firstValid + wire ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_bNoSynth_buffer_firstValid$EN, + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_ar_buffer_ff - wire [97 : 0] ssNoSynth_1_ar_buffer_ff$D_IN, ssNoSynth_1_ar_buffer_ff$D_OUT; - wire ssNoSynth_1_ar_buffer_ff$CLR, - ssNoSynth_1_ar_buffer_ff$DEQ, - ssNoSynth_1_ar_buffer_ff$EMPTY_N, - ssNoSynth_1_ar_buffer_ff$ENQ, - ssNoSynth_1_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_0_rNoSynth_buffer_ff$D_IN, + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_rNoSynth_buffer_ff$CLR, + ssNoSynth_0_rNoSynth_buffer_ff$DEQ, + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_rNoSynth_buffer_ff$ENQ, + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_ar_buffer_firstValid - wire ssNoSynth_1_ar_buffer_firstValid$D_IN, - ssNoSynth_1_ar_buffer_firstValid$EN, - ssNoSynth_1_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_rNoSynth_buffer_firstValid + wire ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_rNoSynth_buffer_firstValid$EN, + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_aw_buffer_ff - wire [97 : 0] ssNoSynth_1_aw_buffer_ff$D_IN, ssNoSynth_1_aw_buffer_ff$D_OUT; - wire ssNoSynth_1_aw_buffer_ff$CLR, - ssNoSynth_1_aw_buffer_ff$DEQ, - ssNoSynth_1_aw_buffer_ff$EMPTY_N, - ssNoSynth_1_aw_buffer_ff$ENQ, - ssNoSynth_1_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_0_wNoSynth_buffer_ff$D_IN, + ssNoSynth_0_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_wNoSynth_buffer_ff$CLR, + ssNoSynth_0_wNoSynth_buffer_ff$DEQ, + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_wNoSynth_buffer_ff$ENQ, + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_aw_buffer_firstValid - wire ssNoSynth_1_aw_buffer_firstValid$D_IN, - ssNoSynth_1_aw_buffer_firstValid$EN, - ssNoSynth_1_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_wNoSynth_buffer_firstValid + wire ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_wNoSynth_buffer_firstValid$EN, + ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_w_buffer_ff - wire [73 : 0] ssNoSynth_1_w_buffer_ff$D_IN, ssNoSynth_1_w_buffer_ff$D_OUT; - wire ssNoSynth_1_w_buffer_ff$CLR, - ssNoSynth_1_w_buffer_ff$DEQ, - ssNoSynth_1_w_buffer_ff$EMPTY_N, - ssNoSynth_1_w_buffer_ff$ENQ, - ssNoSynth_1_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_1_arNoSynth_buffer_ff$D_IN, + ssNoSynth_1_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_arNoSynth_buffer_ff$CLR, + ssNoSynth_1_arNoSynth_buffer_ff$DEQ, + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_arNoSynth_buffer_ff$ENQ, + ssNoSynth_1_arNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_w_buffer_firstValid - wire ssNoSynth_1_w_buffer_firstValid$D_IN, - ssNoSynth_1_w_buffer_firstValid$EN, - ssNoSynth_1_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_arNoSynth_buffer_firstValid + wire ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_arNoSynth_buffer_firstValid$EN, + ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_ar_buffer_ff - wire [97 : 0] ssNoSynth_2_ar_buffer_ff$D_IN, ssNoSynth_2_ar_buffer_ff$D_OUT; - wire ssNoSynth_2_ar_buffer_ff$CLR, - ssNoSynth_2_ar_buffer_ff$DEQ, - ssNoSynth_2_ar_buffer_ff$EMPTY_N, - ssNoSynth_2_ar_buffer_ff$ENQ, - ssNoSynth_2_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_1_awNoSynth_buffer_ff$D_IN, + ssNoSynth_1_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_awNoSynth_buffer_ff$CLR, + ssNoSynth_1_awNoSynth_buffer_ff$DEQ, + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_awNoSynth_buffer_ff$ENQ, + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_ar_buffer_firstValid - wire ssNoSynth_2_ar_buffer_firstValid$D_IN, - ssNoSynth_2_ar_buffer_firstValid$EN, - ssNoSynth_2_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_awNoSynth_buffer_firstValid + wire ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_awNoSynth_buffer_firstValid$EN, + ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_aw_buffer_ff - wire [97 : 0] ssNoSynth_2_aw_buffer_ff$D_IN, ssNoSynth_2_aw_buffer_ff$D_OUT; - wire ssNoSynth_2_aw_buffer_ff$CLR, - ssNoSynth_2_aw_buffer_ff$DEQ, - ssNoSynth_2_aw_buffer_ff$EMPTY_N, - ssNoSynth_2_aw_buffer_ff$ENQ, - ssNoSynth_2_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_ff$D_IN, + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_bNoSynth_buffer_ff$CLR, + ssNoSynth_1_bNoSynth_buffer_ff$DEQ, + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_bNoSynth_buffer_ff$ENQ, + ssNoSynth_1_bNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_aw_buffer_firstValid - wire ssNoSynth_2_aw_buffer_firstValid$D_IN, - ssNoSynth_2_aw_buffer_firstValid$EN, - ssNoSynth_2_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_bNoSynth_buffer_firstValid + wire ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_bNoSynth_buffer_firstValid$EN, + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_w_buffer_ff - wire [73 : 0] ssNoSynth_2_w_buffer_ff$D_IN, ssNoSynth_2_w_buffer_ff$D_OUT; - wire ssNoSynth_2_w_buffer_ff$CLR, - ssNoSynth_2_w_buffer_ff$DEQ, - ssNoSynth_2_w_buffer_ff$EMPTY_N, - ssNoSynth_2_w_buffer_ff$ENQ, - ssNoSynth_2_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_ff$D_IN, + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_rNoSynth_buffer_ff$CLR, + ssNoSynth_1_rNoSynth_buffer_ff$DEQ, + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_rNoSynth_buffer_ff$ENQ, + ssNoSynth_1_rNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_w_buffer_firstValid - wire ssNoSynth_2_w_buffer_firstValid$D_IN, - ssNoSynth_2_w_buffer_firstValid$EN, - ssNoSynth_2_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_rNoSynth_buffer_firstValid + wire ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_rNoSynth_buffer_firstValid$EN, + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_1_wNoSynth_buffer_ff$D_IN, + ssNoSynth_1_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_wNoSynth_buffer_ff$CLR, + ssNoSynth_1_wNoSynth_buffer_ff$DEQ, + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_wNoSynth_buffer_ff$ENQ, + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_wNoSynth_buffer_firstValid + wire ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_wNoSynth_buffer_firstValid$EN, + ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_2_arNoSynth_buffer_ff$D_IN, + ssNoSynth_2_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_arNoSynth_buffer_ff$CLR, + ssNoSynth_2_arNoSynth_buffer_ff$DEQ, + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_arNoSynth_buffer_ff$ENQ, + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_arNoSynth_buffer_firstValid + wire ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_arNoSynth_buffer_firstValid$EN, + ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_2_awNoSynth_buffer_ff$D_IN, + ssNoSynth_2_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_awNoSynth_buffer_ff$CLR, + ssNoSynth_2_awNoSynth_buffer_ff$DEQ, + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_awNoSynth_buffer_ff$ENQ, + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_awNoSynth_buffer_firstValid + wire ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_awNoSynth_buffer_firstValid$EN, + ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_2_bNoSynth_buffer_ff$D_IN, + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_bNoSynth_buffer_ff$CLR, + ssNoSynth_2_bNoSynth_buffer_ff$DEQ, + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_bNoSynth_buffer_ff$ENQ, + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_bNoSynth_buffer_firstValid + wire ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_bNoSynth_buffer_firstValid$EN, + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_2_rNoSynth_buffer_ff$D_IN, + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_rNoSynth_buffer_ff$CLR, + ssNoSynth_2_rNoSynth_buffer_ff$DEQ, + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_rNoSynth_buffer_ff$ENQ, + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_rNoSynth_buffer_firstValid + wire ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_rNoSynth_buffer_firstValid$EN, + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_2_wNoSynth_buffer_ff$D_IN, + ssNoSynth_2_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_wNoSynth_buffer_ff$CLR, + ssNoSynth_2_wNoSynth_buffer_ff$DEQ, + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_wNoSynth_buffer_ff$ENQ, + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_wNoSynth_buffer_firstValid + wire ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_wNoSynth_buffer_firstValid$EN, + ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tagController_tmp_awreqff wire [97 : 0] tagController_tmp_awreqff$D_IN, @@ -1898,57 +2099,70 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_tagCon$RDY_memory_request_get, tagController_tmp_tagCon$RDY_memory_response_put; - // ports of submodule tmp0_b_buffer_ff - wire [5 : 0] tmp0_b_buffer_ff$D_IN, tmp0_b_buffer_ff$D_OUT; - wire tmp0_b_buffer_ff$CLR, - tmp0_b_buffer_ff$DEQ, - tmp0_b_buffer_ff$EMPTY_N, - tmp0_b_buffer_ff$ENQ, - tmp0_b_buffer_ff$FULL_N; + // ports of submodule tmp2_arNoSynth_buffer_ff + wire [97 : 0] tmp2_arNoSynth_buffer_ff$D_IN, tmp2_arNoSynth_buffer_ff$D_OUT; + wire tmp2_arNoSynth_buffer_ff$CLR, + tmp2_arNoSynth_buffer_ff$DEQ, + tmp2_arNoSynth_buffer_ff$EMPTY_N, + tmp2_arNoSynth_buffer_ff$ENQ, + tmp2_arNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp0_b_buffer_firstValid - wire tmp0_b_buffer_firstValid$D_IN, - tmp0_b_buffer_firstValid$EN, - tmp0_b_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_arNoSynth_buffer_firstValid + wire tmp2_arNoSynth_buffer_firstValid$D_IN, + tmp2_arNoSynth_buffer_firstValid$EN, + tmp2_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp0_r_buffer_ff - wire [71 : 0] tmp0_r_buffer_ff$D_IN, tmp0_r_buffer_ff$D_OUT; - wire tmp0_r_buffer_ff$CLR, - tmp0_r_buffer_ff$DEQ, - tmp0_r_buffer_ff$EMPTY_N, - tmp0_r_buffer_ff$ENQ, - tmp0_r_buffer_ff$FULL_N; + // ports of submodule tmp2_awNoSynth_buffer_ff + wire [97 : 0] tmp2_awNoSynth_buffer_ff$D_IN, tmp2_awNoSynth_buffer_ff$D_OUT; + wire tmp2_awNoSynth_buffer_ff$CLR, + tmp2_awNoSynth_buffer_ff$DEQ, + tmp2_awNoSynth_buffer_ff$EMPTY_N, + tmp2_awNoSynth_buffer_ff$ENQ, + tmp2_awNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp0_r_buffer_firstValid - wire tmp0_r_buffer_firstValid$D_IN, - tmp0_r_buffer_firstValid$EN, - tmp0_r_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_awNoSynth_buffer_firstValid + wire tmp2_awNoSynth_buffer_firstValid$D_IN, + tmp2_awNoSynth_buffer_firstValid$EN, + tmp2_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp2_b_buffer_ff - wire [6 : 0] tmp2_b_buffer_ff$D_IN, tmp2_b_buffer_ff$D_OUT; - wire tmp2_b_buffer_ff$CLR, - tmp2_b_buffer_ff$DEQ, - tmp2_b_buffer_ff$EMPTY_N, - tmp2_b_buffer_ff$ENQ, - tmp2_b_buffer_ff$FULL_N; + // ports of submodule tmp2_bNoSynth_buffer_ff + wire [6 : 0] tmp2_bNoSynth_buffer_ff$D_IN, tmp2_bNoSynth_buffer_ff$D_OUT; + wire tmp2_bNoSynth_buffer_ff$CLR, + tmp2_bNoSynth_buffer_ff$DEQ, + tmp2_bNoSynth_buffer_ff$EMPTY_N, + tmp2_bNoSynth_buffer_ff$ENQ, + tmp2_bNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp2_b_buffer_firstValid - wire tmp2_b_buffer_firstValid$D_IN, - tmp2_b_buffer_firstValid$EN, - tmp2_b_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_bNoSynth_buffer_firstValid + wire tmp2_bNoSynth_buffer_firstValid$D_IN, + tmp2_bNoSynth_buffer_firstValid$EN, + tmp2_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp2_r_buffer_ff - wire [72 : 0] tmp2_r_buffer_ff$D_IN, tmp2_r_buffer_ff$D_OUT; - wire tmp2_r_buffer_ff$CLR, - tmp2_r_buffer_ff$DEQ, - tmp2_r_buffer_ff$EMPTY_N, - tmp2_r_buffer_ff$ENQ, - tmp2_r_buffer_ff$FULL_N; + // ports of submodule tmp2_rNoSynth_buffer_ff + wire [72 : 0] tmp2_rNoSynth_buffer_ff$D_IN, tmp2_rNoSynth_buffer_ff$D_OUT; + wire tmp2_rNoSynth_buffer_ff$CLR, + tmp2_rNoSynth_buffer_ff$DEQ, + tmp2_rNoSynth_buffer_ff$EMPTY_N, + tmp2_rNoSynth_buffer_ff$ENQ, + tmp2_rNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp2_r_buffer_firstValid - wire tmp2_r_buffer_firstValid$D_IN, - tmp2_r_buffer_firstValid$EN, - tmp2_r_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_rNoSynth_buffer_firstValid + wire tmp2_rNoSynth_buffer_firstValid$D_IN, + tmp2_rNoSynth_buffer_firstValid$EN, + tmp2_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule tmp2_wNoSynth_buffer_ff + wire [73 : 0] tmp2_wNoSynth_buffer_ff$D_IN, tmp2_wNoSynth_buffer_ff$D_OUT; + wire tmp2_wNoSynth_buffer_ff$CLR, + tmp2_wNoSynth_buffer_ff$DEQ, + tmp2_wNoSynth_buffer_ff$EMPTY_N, + tmp2_wNoSynth_buffer_ff$ENQ, + tmp2_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule tmp2_wNoSynth_buffer_firstValid + wire tmp2_wNoSynth_buffer_firstValid$D_IN, + tmp2_wNoSynth_buffer_firstValid$EN, + tmp2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule uncached_mem_shim_arff wire [97 : 0] uncached_mem_shim_arff$D_IN, uncached_mem_shim_arff$D_OUT; @@ -1997,11 +2211,36 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_ClientServerResponse, CAN_FIRE_RL_ClientServerResponse_1, CAN_FIRE_RL_ClientServerResponse_2, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, CAN_FIRE_RL_arbitrate, CAN_FIRE_RL_arbitrate_1, CAN_FIRE_RL_arbitrate_2, @@ -2016,6 +2255,19 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_burst_7, CAN_FIRE_RL_burst_8, CAN_FIRE_RL_burst_9, + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut, + CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut, + CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_checkSinkReady, CAN_FIRE_RL_checkSinkReady_1, CAN_FIRE_RL_checkSinkReady_2, @@ -2042,67 +2294,132 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_ifcs_0_1_firstFlit_1, CAN_FIRE_RL_ifcs_0_1_followFlits, CAN_FIRE_RL_ifcs_0_1_followFlits_1, - CAN_FIRE_RL_ifcs_0_1_forwardRsp, CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_1_snk_doPut, + CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_0_drainFlits, CAN_FIRE_RL_ifcs_0_drainNoRouteResponse, CAN_FIRE_RL_ifcs_0_firstFlit, CAN_FIRE_RL_ifcs_0_firstFlit_1, CAN_FIRE_RL_ifcs_0_followFlits, CAN_FIRE_RL_ifcs_0_followFlits_1, - CAN_FIRE_RL_ifcs_0_forwardRsp, CAN_FIRE_RL_ifcs_0_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_snk_doPut, + CAN_FIRE_RL_ifcs_0_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_1_drainFlits, CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_1_firstFlit, CAN_FIRE_RL_ifcs_1_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_1_followFlits, CAN_FIRE_RL_ifcs_1_1_followFlits_1, - CAN_FIRE_RL_ifcs_1_1_forwardRsp, CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_1_snk_doPut, + CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_drainFlits, CAN_FIRE_RL_ifcs_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_firstFlit, CAN_FIRE_RL_ifcs_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_followFlits, CAN_FIRE_RL_ifcs_1_followFlits_1, - CAN_FIRE_RL_ifcs_1_forwardRsp, CAN_FIRE_RL_ifcs_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_snk_doPut, + CAN_FIRE_RL_ifcs_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_2_1_firstFlit, CAN_FIRE_RL_ifcs_2_1_followFlits, CAN_FIRE_RL_ifcs_2_firstFlit, CAN_FIRE_RL_ifcs_2_followFlits, + CAN_FIRE_RL_merged_0_awFlit, CAN_FIRE_RL_merged_0_genFirst, CAN_FIRE_RL_merged_0_genOther, + CAN_FIRE_RL_merged_0_passFlit, + CAN_FIRE_RL_merged_0_wFlit, + CAN_FIRE_RL_merged_1_awFlit, CAN_FIRE_RL_merged_1_genFirst, CAN_FIRE_RL_merged_1_genOther, + CAN_FIRE_RL_merged_1_passFlit, + CAN_FIRE_RL_merged_1_wFlit, CAN_FIRE_RL_mkConnectionGetPut, - CAN_FIRE_RL_msNoSynth_0_ar_forwardReady, - CAN_FIRE_RL_msNoSynth_0_aw_forwardReady, - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_0_b_dropFlit, - CAN_FIRE_RL_msNoSynth_0_b_forwardFlit, - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_0_r_dropFlit, - CAN_FIRE_RL_msNoSynth_0_r_forwardFlit, - CAN_FIRE_RL_msNoSynth_0_w_forwardReady, - CAN_FIRE_RL_msNoSynth_1_ar_forwardReady, - CAN_FIRE_RL_msNoSynth_1_aw_forwardReady, - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_1_b_dropFlit, - CAN_FIRE_RL_msNoSynth_1_b_forwardFlit, - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_1_r_dropFlit, - CAN_FIRE_RL_msNoSynth_1_r_forwardFlit, - CAN_FIRE_RL_msNoSynth_1_w_forwardReady, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, + CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut, + CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut, + CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, CAN_FIRE_RL_rl_dm_hart0_reset, CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_relay_external_interrupts, @@ -2116,6 +2433,38 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_sink_selected_7, CAN_FIRE_RL_sink_selected_8, CAN_FIRE_RL_sink_selected_9, + CAN_FIRE_RL_sinks_0_doPut, + CAN_FIRE_RL_sinks_0_warnDoPut, + CAN_FIRE_RL_sinks_1_0_doPut, + CAN_FIRE_RL_sinks_1_0_doPut_1, + CAN_FIRE_RL_sinks_1_0_warnDoPut, + CAN_FIRE_RL_sinks_1_0_warnDoPut_1, + CAN_FIRE_RL_sinks_1_1_0_doPut, + CAN_FIRE_RL_sinks_1_1_0_warnDoPut, + CAN_FIRE_RL_sinks_1_1_1_doPut, + CAN_FIRE_RL_sinks_1_1_1_warnDoPut, + CAN_FIRE_RL_sinks_1_1_doPut, + CAN_FIRE_RL_sinks_1_1_doPut_1, + CAN_FIRE_RL_sinks_1_1_warnDoPut, + CAN_FIRE_RL_sinks_1_1_warnDoPut_1, + CAN_FIRE_RL_sinks_1_2_doPut, + CAN_FIRE_RL_sinks_1_2_warnDoPut, + CAN_FIRE_RL_sinks_1_doPut, + CAN_FIRE_RL_sinks_1_warnDoPut, + CAN_FIRE_RL_sinks_2_doPut, + CAN_FIRE_RL_sinks_2_warnDoPut, + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop, + CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek, + CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop, + CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek, + CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, CAN_FIRE_RL_source_selected, CAN_FIRE_RL_source_selected_1, CAN_FIRE_RL_source_selected_2, @@ -2132,48 +2481,105 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_split_1_putOther, CAN_FIRE_RL_split_2_putFirst, CAN_FIRE_RL_split_2_putOther, - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_0_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_0_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_1_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_2_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, CAN_FIRE_RL_tagController_tmp_getCacheAW, CAN_FIRE_RL_tagController_tmp_passCacheRead, CAN_FIRE_RL_tagController_tmp_passCacheResponse, @@ -2207,77 +2613,87 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, - CAN_FIRE_RL_tmp0_ar_forwardReady, - CAN_FIRE_RL_tmp0_aw_forwardReady, - CAN_FIRE_RL_tmp0_b_buffer_dequeue, - CAN_FIRE_RL_tmp0_b_buffer_enqueue, - CAN_FIRE_RL_tmp0_b_dropFlit, - CAN_FIRE_RL_tmp0_b_forwardFlit, - CAN_FIRE_RL_tmp0_r_buffer_dequeue, - CAN_FIRE_RL_tmp0_r_buffer_enqueue, - CAN_FIRE_RL_tmp0_r_dropFlit, - CAN_FIRE_RL_tmp0_r_forwardFlit, - CAN_FIRE_RL_tmp0_w_forwardReady, - CAN_FIRE_RL_tmp2_ar_forwardReady, - CAN_FIRE_RL_tmp2_aw_forwardReady, - CAN_FIRE_RL_tmp2_b_buffer_dequeue, - CAN_FIRE_RL_tmp2_b_buffer_enqueue, - CAN_FIRE_RL_tmp2_b_dropFlit, - CAN_FIRE_RL_tmp2_b_forwardFlit, - CAN_FIRE_RL_tmp2_r_buffer_dequeue, - CAN_FIRE_RL_tmp2_r_buffer_enqueue, - CAN_FIRE_RL_tmp2_r_dropFlit, - CAN_FIRE_RL_tmp2_r_forwardFlit, - CAN_FIRE_RL_tmp2_w_forwardReady, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, - CAN_FIRE___me_check_156, - CAN_FIRE___me_check_157, - CAN_FIRE___me_check_158, - CAN_FIRE___me_check_160, - CAN_FIRE___me_check_163, - CAN_FIRE___me_check_164, - CAN_FIRE___me_check_165, - CAN_FIRE___me_check_167, - CAN_FIRE___me_check_170, - CAN_FIRE___me_check_172, - CAN_FIRE___me_check_174, - CAN_FIRE___me_check_182, - CAN_FIRE___me_check_184, - CAN_FIRE___me_check_186, - CAN_FIRE___me_check_195, - CAN_FIRE___me_check_197, - CAN_FIRE___me_check_199, - CAN_FIRE___me_check_201, - CAN_FIRE___me_check_203, - CAN_FIRE___me_check_204, - CAN_FIRE___me_check_205, - CAN_FIRE___me_check_207, - CAN_FIRE___me_check_210, - CAN_FIRE___me_check_211, - CAN_FIRE___me_check_212, - CAN_FIRE___me_check_214, - CAN_FIRE___me_check_217, - CAN_FIRE___me_check_219, - CAN_FIRE___me_check_221, - CAN_FIRE___me_check_229, - CAN_FIRE___me_check_231, - CAN_FIRE___me_check_233, - CAN_FIRE___me_check_242, - CAN_FIRE___me_check_244, - CAN_FIRE___me_check_246, - CAN_FIRE___me_check_248, + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_arNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_awNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit, + CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop, + CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek, + CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit, + CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop, + CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek, + CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_wNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, + CAN_FIRE___me_check_323, + CAN_FIRE___me_check_324, + CAN_FIRE___me_check_325, + CAN_FIRE___me_check_327, + CAN_FIRE___me_check_331, + CAN_FIRE___me_check_332, + CAN_FIRE___me_check_333, + CAN_FIRE___me_check_335, + CAN_FIRE___me_check_337, + CAN_FIRE___me_check_339, + CAN_FIRE___me_check_341, + CAN_FIRE___me_check_355, + CAN_FIRE___me_check_357, + CAN_FIRE___me_check_359, + CAN_FIRE___me_check_372, + CAN_FIRE___me_check_374, + CAN_FIRE___me_check_376, + CAN_FIRE___me_check_378, + CAN_FIRE___me_check_382, + CAN_FIRE___me_check_383, + CAN_FIRE___me_check_384, + CAN_FIRE___me_check_386, + CAN_FIRE___me_check_390, + CAN_FIRE___me_check_391, + CAN_FIRE___me_check_392, + CAN_FIRE___me_check_394, + CAN_FIRE___me_check_396, + CAN_FIRE___me_check_398, + CAN_FIRE___me_check_400, + CAN_FIRE___me_check_414, + CAN_FIRE___me_check_416, + CAN_FIRE___me_check_418, + CAN_FIRE___me_check_431, + CAN_FIRE___me_check_433, + CAN_FIRE___me_check_435, + CAN_FIRE___me_check_437, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -2318,11 +2734,36 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ClientServerResponse, WILL_FIRE_RL_ClientServerResponse_1, WILL_FIRE_RL_ClientServerResponse_2, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, WILL_FIRE_RL_arbitrate, WILL_FIRE_RL_arbitrate_1, WILL_FIRE_RL_arbitrate_2, @@ -2337,6 +2778,19 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_burst_7, WILL_FIRE_RL_burst_8, WILL_FIRE_RL_burst_9, + WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut, + WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut, + WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_checkSinkReady, WILL_FIRE_RL_checkSinkReady_1, WILL_FIRE_RL_checkSinkReady_2, @@ -2363,67 +2817,132 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ifcs_0_1_firstFlit_1, WILL_FIRE_RL_ifcs_0_1_followFlits, WILL_FIRE_RL_ifcs_0_1_followFlits_1, - WILL_FIRE_RL_ifcs_0_1_forwardRsp, WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_1_snk_doPut, + WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_0_drainFlits, WILL_FIRE_RL_ifcs_0_drainNoRouteResponse, WILL_FIRE_RL_ifcs_0_firstFlit, WILL_FIRE_RL_ifcs_0_firstFlit_1, WILL_FIRE_RL_ifcs_0_followFlits, WILL_FIRE_RL_ifcs_0_followFlits_1, - WILL_FIRE_RL_ifcs_0_forwardRsp, WILL_FIRE_RL_ifcs_0_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_snk_doPut, + WILL_FIRE_RL_ifcs_0_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_1_drainFlits, WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_1_firstFlit, WILL_FIRE_RL_ifcs_1_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_1_followFlits, WILL_FIRE_RL_ifcs_1_1_followFlits_1, - WILL_FIRE_RL_ifcs_1_1_forwardRsp, WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_1_snk_doPut, + WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_drainFlits, WILL_FIRE_RL_ifcs_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_firstFlit, WILL_FIRE_RL_ifcs_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_followFlits, WILL_FIRE_RL_ifcs_1_followFlits_1, - WILL_FIRE_RL_ifcs_1_forwardRsp, WILL_FIRE_RL_ifcs_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_snk_doPut, + WILL_FIRE_RL_ifcs_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_2_1_firstFlit, WILL_FIRE_RL_ifcs_2_1_followFlits, WILL_FIRE_RL_ifcs_2_firstFlit, WILL_FIRE_RL_ifcs_2_followFlits, + WILL_FIRE_RL_merged_0_awFlit, WILL_FIRE_RL_merged_0_genFirst, WILL_FIRE_RL_merged_0_genOther, + WILL_FIRE_RL_merged_0_passFlit, + WILL_FIRE_RL_merged_0_wFlit, + WILL_FIRE_RL_merged_1_awFlit, WILL_FIRE_RL_merged_1_genFirst, WILL_FIRE_RL_merged_1_genOther, + WILL_FIRE_RL_merged_1_passFlit, + WILL_FIRE_RL_merged_1_wFlit, WILL_FIRE_RL_mkConnectionGetPut, - WILL_FIRE_RL_msNoSynth_0_ar_forwardReady, - WILL_FIRE_RL_msNoSynth_0_aw_forwardReady, - WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_0_b_dropFlit, - WILL_FIRE_RL_msNoSynth_0_b_forwardFlit, - WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_0_r_dropFlit, - WILL_FIRE_RL_msNoSynth_0_r_forwardFlit, - WILL_FIRE_RL_msNoSynth_0_w_forwardReady, - WILL_FIRE_RL_msNoSynth_1_ar_forwardReady, - WILL_FIRE_RL_msNoSynth_1_aw_forwardReady, - WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_1_b_dropFlit, - WILL_FIRE_RL_msNoSynth_1_b_forwardFlit, - WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_1_r_dropFlit, - WILL_FIRE_RL_msNoSynth_1_r_forwardFlit, - WILL_FIRE_RL_msNoSynth_1_w_forwardReady, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, + WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, + WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut, + WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut, + WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, WILL_FIRE_RL_rl_dm_hart0_reset, WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_relay_external_interrupts, @@ -2437,6 +2956,38 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_sink_selected_7, WILL_FIRE_RL_sink_selected_8, WILL_FIRE_RL_sink_selected_9, + WILL_FIRE_RL_sinks_0_doPut, + WILL_FIRE_RL_sinks_0_warnDoPut, + WILL_FIRE_RL_sinks_1_0_doPut, + WILL_FIRE_RL_sinks_1_0_doPut_1, + WILL_FIRE_RL_sinks_1_0_warnDoPut, + WILL_FIRE_RL_sinks_1_0_warnDoPut_1, + WILL_FIRE_RL_sinks_1_1_0_doPut, + WILL_FIRE_RL_sinks_1_1_0_warnDoPut, + WILL_FIRE_RL_sinks_1_1_1_doPut, + WILL_FIRE_RL_sinks_1_1_1_warnDoPut, + WILL_FIRE_RL_sinks_1_1_doPut, + WILL_FIRE_RL_sinks_1_1_doPut_1, + WILL_FIRE_RL_sinks_1_1_warnDoPut, + WILL_FIRE_RL_sinks_1_1_warnDoPut_1, + WILL_FIRE_RL_sinks_1_2_doPut, + WILL_FIRE_RL_sinks_1_2_warnDoPut, + WILL_FIRE_RL_sinks_1_doPut, + WILL_FIRE_RL_sinks_1_warnDoPut, + WILL_FIRE_RL_sinks_2_doPut, + WILL_FIRE_RL_sinks_2_warnDoPut, + WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, + WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, + WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop, + WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek, + WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, + WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop, + WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek, + WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, + WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, WILL_FIRE_RL_source_selected, WILL_FIRE_RL_source_selected_1, WILL_FIRE_RL_source_selected_2, @@ -2453,48 +3004,105 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_split_1_putOther, WILL_FIRE_RL_split_2_putFirst, WILL_FIRE_RL_split_2_putOther, - WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_0_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_0_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_1_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_2_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, WILL_FIRE_RL_tagController_tmp_getCacheAW, WILL_FIRE_RL_tagController_tmp_passCacheRead, WILL_FIRE_RL_tagController_tmp_passCacheResponse, @@ -2528,77 +3136,87 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, - WILL_FIRE_RL_tmp0_ar_forwardReady, - WILL_FIRE_RL_tmp0_aw_forwardReady, - WILL_FIRE_RL_tmp0_b_buffer_dequeue, - WILL_FIRE_RL_tmp0_b_buffer_enqueue, - WILL_FIRE_RL_tmp0_b_dropFlit, - WILL_FIRE_RL_tmp0_b_forwardFlit, - WILL_FIRE_RL_tmp0_r_buffer_dequeue, - WILL_FIRE_RL_tmp0_r_buffer_enqueue, - WILL_FIRE_RL_tmp0_r_dropFlit, - WILL_FIRE_RL_tmp0_r_forwardFlit, - WILL_FIRE_RL_tmp0_w_forwardReady, - WILL_FIRE_RL_tmp2_ar_forwardReady, - WILL_FIRE_RL_tmp2_aw_forwardReady, - WILL_FIRE_RL_tmp2_b_buffer_dequeue, - WILL_FIRE_RL_tmp2_b_buffer_enqueue, - WILL_FIRE_RL_tmp2_b_dropFlit, - WILL_FIRE_RL_tmp2_b_forwardFlit, - WILL_FIRE_RL_tmp2_r_buffer_dequeue, - WILL_FIRE_RL_tmp2_r_buffer_enqueue, - WILL_FIRE_RL_tmp2_r_dropFlit, - WILL_FIRE_RL_tmp2_r_forwardFlit, - WILL_FIRE_RL_tmp2_w_forwardReady, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, - WILL_FIRE___me_check_156, - WILL_FIRE___me_check_157, - WILL_FIRE___me_check_158, - WILL_FIRE___me_check_160, - WILL_FIRE___me_check_163, - WILL_FIRE___me_check_164, - WILL_FIRE___me_check_165, - WILL_FIRE___me_check_167, - WILL_FIRE___me_check_170, - WILL_FIRE___me_check_172, - WILL_FIRE___me_check_174, - WILL_FIRE___me_check_182, - WILL_FIRE___me_check_184, - WILL_FIRE___me_check_186, - WILL_FIRE___me_check_195, - WILL_FIRE___me_check_197, - WILL_FIRE___me_check_199, - WILL_FIRE___me_check_201, - WILL_FIRE___me_check_203, - WILL_FIRE___me_check_204, - WILL_FIRE___me_check_205, - WILL_FIRE___me_check_207, - WILL_FIRE___me_check_210, - WILL_FIRE___me_check_211, - WILL_FIRE___me_check_212, - WILL_FIRE___me_check_214, - WILL_FIRE___me_check_217, - WILL_FIRE___me_check_219, - WILL_FIRE___me_check_221, - WILL_FIRE___me_check_229, - WILL_FIRE___me_check_231, - WILL_FIRE___me_check_233, - WILL_FIRE___me_check_242, - WILL_FIRE___me_check_244, - WILL_FIRE___me_check_246, - WILL_FIRE___me_check_248, + WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_arNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_awNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_bNoSynth_dropFlit, + WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop, + WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek, + WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_rNoSynth_dropFlit, + WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop, + WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek, + WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_wNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, + WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, + WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, + WILL_FIRE___me_check_323, + WILL_FIRE___me_check_324, + WILL_FIRE___me_check_325, + WILL_FIRE___me_check_327, + WILL_FIRE___me_check_331, + WILL_FIRE___me_check_332, + WILL_FIRE___me_check_333, + WILL_FIRE___me_check_335, + WILL_FIRE___me_check_337, + WILL_FIRE___me_check_339, + WILL_FIRE___me_check_341, + WILL_FIRE___me_check_355, + WILL_FIRE___me_check_357, + WILL_FIRE___me_check_359, + WILL_FIRE___me_check_372, + WILL_FIRE___me_check_374, + WILL_FIRE___me_check_376, + WILL_FIRE___me_check_378, + WILL_FIRE___me_check_382, + WILL_FIRE___me_check_383, + WILL_FIRE___me_check_384, + WILL_FIRE___me_check_386, + WILL_FIRE___me_check_390, + WILL_FIRE___me_check_391, + WILL_FIRE___me_check_392, + WILL_FIRE___me_check_394, + WILL_FIRE___me_check_396, + WILL_FIRE___me_check_398, + WILL_FIRE___me_check_400, + WILL_FIRE___me_check_414, + WILL_FIRE___me_check_416, + WILL_FIRE___me_check_418, + WILL_FIRE___me_check_431, + WILL_FIRE___me_check_433, + WILL_FIRE___me_check_435, + WILL_FIRE___me_check_437, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -2635,16 +3253,16 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_start; // inputs to muxes for submodule ports - reg [71 : 0] MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2, - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2; - reg [5 : 0] MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2, - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2; + reg [71 : 0] MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1, + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1; + reg [5 : 0] MUX_ifcs_0_snk_putWire$wset_1__VAL_1, + MUX_ifcs_1_snk_putWire$wset_1__VAL_1; wire [140 : 0] MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1, MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2; wire [76 : 0] MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1, MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2; - wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_1, - MUX_merged_1_flitLeft$write_1__VAL_1, + wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_2, + MUX_merged_1_flitLeft$write_1__VAL_2, MUX_rg_hart0_reset_delay$write_1__VAL_1, MUX_split_0_flitLeft$write_1__VAL_1, MUX_split_1_flitLeft$write_1__VAL_1, @@ -2720,99 +3338,105 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h22825; - reg [31 : 0] v__h22968; - reg [63 : 0] v__h50461; - reg [63 : 0] v__h49850; - reg [63 : 0] v__h54470; - reg [63 : 0] v__h53859; - reg [63 : 0] v__h84222; - reg [63 : 0] v__h83611; - reg [63 : 0] v__h87115; - reg [63 : 0] v__h86504; - reg [63 : 0] v__h65165; - reg [63 : 0] v__h64784; - reg [63 : 0] v__h67235; - reg [63 : 0] v__h66854; - reg [63 : 0] v__h69134; - reg [63 : 0] v__h68753; - reg [63 : 0] v__h96395; - reg [63 : 0] v__h96014; - reg [63 : 0] v__h98886; - reg [63 : 0] v__h98505; - reg [63 : 0] v__h101196; - reg [63 : 0] v__h100815; - reg [31 : 0] v__h103640; - reg [31 : 0] v__h22819; - reg [31 : 0] v__h22962; - reg [31 : 0] v__h103634; + reg [31 : 0] v__h27371; + reg [31 : 0] v__h27514; + reg [63 : 0] v__h71925; + reg [63 : 0] v__h71314; + reg [63 : 0] v__h75934; + reg [63 : 0] v__h75323; + reg [63 : 0] v__h87100; + reg [63 : 0] v__h86719; + reg [63 : 0] v__h89170; + reg [63 : 0] v__h88789; + reg [63 : 0] v__h91069; + reg [63 : 0] v__h90688; + reg [63 : 0] v__h107698; + reg [63 : 0] v__h107087; + reg [63 : 0] v__h110591; + reg [63 : 0] v__h109980; + reg [63 : 0] v__h120378; + reg [63 : 0] v__h119997; + reg [63 : 0] v__h122869; + reg [63 : 0] v__h122488; + reg [63 : 0] v__h125179; + reg [63 : 0] v__h124798; + reg [31 : 0] v__h128907; + reg [31 : 0] v__h27365; + reg [31 : 0] v__h27508; + reg [31 : 0] v__h128901; // synopsys translate_on // remaining internal signals + wire [171 : 0] IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645; wire [98 : 0] tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4, tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2; wire [72 : 0] tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3, uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1; - wire [63 : 0] araddr__h15540, - aw_awaddr__h10808, - tmp__h10591, - tmp__h8366, - v_araddr__h15557, - x__h37445, - x__h37480, - x__h40162, - x__h40187, - x__h71737, - x__h71762, - x__h74126, - x__h74151, - x__h8207, - x_rdata__h25045; - wire [39 : 0] x__h10840; - wire [8 : 0] x_port1__read__h72781, x_port1__read__h75154; - wire [7 : 0] arlen__h15541, v_arlen__h15558; - wire [5 : 0] v_arid__h15556; - wire [4 : 0] a_awid__h38523, - a_awid__h41194, - fatReq_arid__h72223, - fatReq_arid__h74597; - wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245, - arcache__h15545, - x__h10883, - x__h12617, - x__h12629, - x__h12641, - x__h12653, - x__h12665, - x__h12677, - x__h12689, - x__h14213, - x__h15621, - x_rid__h25044, - y__h12618, - y__h12630, - y__h12642, - y__h12654, - y__h12666, - y__h12678, - y__h12690; - wire [2 : 0] aw_awsize_val__h12547, v_arsize_val__h15603; - wire [1 : 0] IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207, - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211, - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863, - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22, - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17, - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12, - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7, + wire [63 : 0] addr__h93758, + addr__h96375, + araddr__h15343, + aw_awaddr__h10611, + tmp__h10394, + tmp__h8169, + v_araddr__h15360, + x__h56232, + x__h56267, + x__h59744, + x__h59769, + x__h8010, + x__h93834, + x__h93859, + x__h96451, + x__h96476; + wire [39 : 0] x__h10643; + wire [8 : 0] x__h95023, x__h97622; + wire [7 : 0] arlen__h15344, v_arlen__h15361, x__h94920, x__h97519; + wire [5 : 0] v_arid__h15359; + wire [4 : 0] fatReq_arid__h94342, + fatReq_arid__h96944, + x__h100325, + x__h62625, + x__h63516, + x__h64407, + x__h98415, + x__h99370; + wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224, + arcache__h15348, + x__h10686, + x__h12420, + x__h12432, + x__h12444, + x__h12456, + x__h12468, + x__h12480, + x__h12492, + x__h14016, + x__h15424, + y__h12421, + y__h12433, + y__h12445, + y__h12457, + y__h12469, + y__h12481, + y__h12493; + wire [2 : 0] aw_awsize_val__h12350, v_arsize_val__h15406; + wire [1 : 0] IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531, + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535, + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331, + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22, + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12, + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17, + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7, SEXT_arbiter_1_1_firstHot__q19, SEXT_arbiter_1_1_lastSelect_1__q21, SEXT_arbiter_1_1_lastSelect__q20, @@ -2823,146 +3447,146 @@ module mkCoreW(RST_N_dm_power_on_reset, SEXT_arbiter_1_lastSelect__q10, SEXT_arbiter_firstHot__q5, SEXT_arbiter_lastSelect__q6, - SEXT_x2747__q18, - SEXT_x3466__q13, - SEXT_x3500__q14, - SEXT_x4692__q23, - SEXT_x4726__q24, - SEXT_x8980__q8; - wire IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098, - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455, - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114, - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362, - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150, - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729, - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507, - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302, - IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425, - IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426, - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427, - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331, - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325, - SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319, - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138, - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698, - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692, - SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134, - SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686, - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495, - SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491, - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932, - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937, - debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930, - debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935, - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845, - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850, - proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843, - proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848, - reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669, - reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302, - split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093, - split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122, - split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151, - state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193, - state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233, - state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400, - state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436, - state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472, - state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761, - state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794, - state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828, - state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556, - state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600, - x__h48453, - x__h48556, - x__h48921, - x__h48980, - x__h49062, - x__h62645, - x__h62647, - x__h62796, - x__h62798, - x__h62932, - x__h62934, - x__h63404, - x__h63406, - x__h63466, - x__h63500, - x__h63592, - x__h63594, - x__h63773, - x__h63775, - x__h82220, - x__h82323, - x__h82688, - x__h82747, - x__h82829, - x__h93871, - x__h93873, - x__h94022, - x__h94024, - x__h94158, - x__h94160, - x__h94630, - x__h94632, - x__h94692, - x__h94726, - x__h94818, - x__h94820, - x__h94999, - x__h95001, - y__h48454, - y__h48557, - y__h48922, - y__h49063, - y__h62646, - y__h62648, - y__h62797, - y__h62799, - y__h62933, - y__h62935, - y__h63405, - y__h63407, - y__h63593, - y__h63595, - y__h63774, - y__h63776, - y__h82221, - y__h82324, - y__h82689, - y__h82830, - y__h93872, - y__h93874, - y__h94023, - y__h94025, - y__h94159, - y__h94161, - y__h94631, - y__h94633, - y__h94819, - y__h94821, - y__h95000, - y__h95002; + SEXT_x0450__q8, + SEXT_x06223__q18, + SEXT_x18675__q23, + SEXT_x18709__q24, + SEXT_x5401__q13, + SEXT_x5435__q14; + wire IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513, + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812, + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529, + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090, + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565, + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569, + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864, + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868, + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556, + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561, + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650, + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764, + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773, + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782, + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750, + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744, + SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738, + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059, + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553, + SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047, + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053, + SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549, + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852, + SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848, + reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030, + reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721, + split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409, + split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438, + split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467, + state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122, + state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155, + state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189, + state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819, + state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855, + state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891, + state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608, + state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648, + state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913, + state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957, + x__h105696, + x__h105799, + x__h106164, + x__h106223, + x__h106305, + x__h117854, + x__h117856, + x__h118005, + x__h118007, + x__h118141, + x__h118143, + x__h118613, + x__h118615, + x__h118675, + x__h118709, + x__h118801, + x__h118803, + x__h118982, + x__h118984, + x__h69923, + x__h70026, + x__h70391, + x__h70450, + x__h70532, + x__h84580, + x__h84582, + x__h84731, + x__h84733, + x__h84867, + x__h84869, + x__h85339, + x__h85341, + x__h85401, + x__h85435, + x__h85527, + x__h85529, + x__h85708, + x__h85710, + y__h105697, + y__h105800, + y__h106165, + y__h106306, + y__h117855, + y__h117857, + y__h118006, + y__h118008, + y__h118142, + y__h118144, + y__h118614, + y__h118616, + y__h118802, + y__h118804, + y__h118983, + y__h118985, + y__h69924, + y__h70027, + y__h70392, + y__h70533, + y__h84581, + y__h84583, + y__h84732, + y__h84734, + y__h84868, + y__h84870, + y__h85340, + y__h85342, + y__h85528, + y__h85530, + y__h85709, + y__h85711; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; @@ -3044,7 +3668,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_imem_master_b_bflit assign CAN_FIRE_cpu_imem_master_b_bflit = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_b_bflit = cpu_imem_master_bvalid ; + assign WILL_FIRE_cpu_imem_master_b_bflit = 1'd1 ; // value method cpu_imem_master_b_bready assign cpu_imem_master_bready = !tagController_tmp_shimMaster_bff_rv[8] ; @@ -3099,50 +3723,50 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_imem_master_r_rflit assign CAN_FIRE_cpu_imem_master_r_rflit = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_r_rflit = cpu_imem_master_rvalid ; + assign WILL_FIRE_cpu_imem_master_r_rflit = 1'd1 ; // value method cpu_imem_master_r_rready assign cpu_imem_master_rready = !tagController_tmp_shimMaster_rff_rv[73] ; // value method cpu_dmem_master_aw_awid assign cpu_dmem_master_awid = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[98:93] ; + uncached_mem_master_awSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_aw_awaddr assign cpu_dmem_master_awaddr = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[92:29] ; + uncached_mem_master_awSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_aw_awlen assign cpu_dmem_master_awlen = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[28:21] ; + uncached_mem_master_awSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_aw_awsize assign cpu_dmem_master_awsize = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[20:18] ; + uncached_mem_master_awSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_aw_awburst assign cpu_dmem_master_awburst = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[17:16] ; + uncached_mem_master_awSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_aw_awlock assign cpu_dmem_master_awlock = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[15] ; + uncached_mem_master_awSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_aw_awcache assign cpu_dmem_master_awcache = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[14:11] ; + uncached_mem_master_awSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_aw_awprot assign cpu_dmem_master_awprot = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[10:8] ; + uncached_mem_master_awSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_aw_awqos assign cpu_dmem_master_awqos = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[7:4] ; + uncached_mem_master_awSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_aw_awregion assign cpu_dmem_master_awregion = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[3:0] ; + uncached_mem_master_awSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_aw_awvalid assign cpu_dmem_master_awvalid = uncached_mem_shim_awff$EMPTY_N ; @@ -3172,50 +3796,50 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_dmem_master_b_bflit assign CAN_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_b_bflit = cpu_dmem_master_bvalid ; + assign WILL_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; // value method cpu_dmem_master_b_bready assign cpu_dmem_master_bready = uncached_mem_shim_bff$FULL_N ; // value method cpu_dmem_master_ar_arid assign cpu_dmem_master_arid = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[98:93] ; + uncached_mem_master_arSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_ar_araddr assign cpu_dmem_master_araddr = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[92:29] ; + uncached_mem_master_arSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_ar_arlen assign cpu_dmem_master_arlen = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[28:21] ; + uncached_mem_master_arSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_ar_arsize assign cpu_dmem_master_arsize = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[20:18] ; + uncached_mem_master_arSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_ar_arburst assign cpu_dmem_master_arburst = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[17:16] ; + uncached_mem_master_arSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_ar_arlock assign cpu_dmem_master_arlock = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[15] ; + uncached_mem_master_arSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_ar_arcache assign cpu_dmem_master_arcache = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[14:11] ; + uncached_mem_master_arSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_ar_arprot assign cpu_dmem_master_arprot = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[10:8] ; + uncached_mem_master_arSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_ar_arqos assign cpu_dmem_master_arqos = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[7:4] ; + uncached_mem_master_arSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_ar_arregion assign cpu_dmem_master_arregion = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[3:0] ; + uncached_mem_master_arSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_ar_arvalid assign cpu_dmem_master_arvalid = uncached_mem_shim_arff$EMPTY_N ; @@ -3226,7 +3850,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_dmem_master_r_rflit assign CAN_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_r_rflit = cpu_dmem_master_rvalid ; + assign WILL_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; // value method cpu_dmem_master_r_rready assign cpu_dmem_master_rready = uncached_mem_shim_rff$FULL_N ; @@ -3348,11 +3972,13 @@ module mkCoreW(RST_N_dm_power_on_reset, .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), .master_bresp(debug_module$master_bresp), + .master_bvalid(debug_module$master_bvalid), .master_rdata(debug_module$master_rdata), .master_rid(debug_module$master_rid), .master_rlast(debug_module$master_rlast), .master_rresp(debug_module$master_rresp), .master_ruser(debug_module$master_ruser), + .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), @@ -3371,8 +3997,6 @@ module mkCoreW(RST_N_dm_power_on_reset, .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), - .master_bvalid(debug_module$master_bvalid), - .master_rvalid(debug_module$master_rvalid), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), @@ -3705,79 +4329,239 @@ module mkCoreW(RST_N_dm_power_on_reset, .FULL_N(ifcs_2_rspBack$FULL_N), .EMPTY_N(ifcs_2_rspBack$EMPTY_N)); - // submodule msNoSynth_0_b_buffer_ff - FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_0_b_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_0_b_buffer_ff$D_IN), - .ENQ(msNoSynth_0_b_buffer_ff$ENQ), - .DEQ(msNoSynth_0_b_buffer_ff$DEQ), - .CLR(msNoSynth_0_b_buffer_ff$CLR), - .D_OUT(msNoSynth_0_b_buffer_ff$D_OUT), - .FULL_N(msNoSynth_0_b_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_0_b_buffer_ff$EMPTY_N)); + // submodule merged_0_awff + FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_0_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_0_awff$D_IN), + .ENQ(merged_0_awff$ENQ), + .DEQ(merged_0_awff$DEQ), + .CLR(merged_0_awff$CLR), + .D_OUT(merged_0_awff$D_OUT), + .FULL_N(merged_0_awff$FULL_N), + .EMPTY_N(merged_0_awff$EMPTY_N)); - // submodule msNoSynth_0_b_buffer_firstValid + // submodule merged_0_wff + FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_0_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_0_wff$D_IN), + .ENQ(merged_0_wff$ENQ), + .DEQ(merged_0_wff$DEQ), + .CLR(merged_0_wff$CLR), + .D_OUT(merged_0_wff$D_OUT), + .FULL_N(merged_0_wff$FULL_N), + .EMPTY_N(merged_0_wff$EMPTY_N)); + + // submodule merged_1_awff + FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_1_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_1_awff$D_IN), + .ENQ(merged_1_awff$ENQ), + .DEQ(merged_1_awff$DEQ), + .CLR(merged_1_awff$CLR), + .D_OUT(merged_1_awff$D_OUT), + .FULL_N(merged_1_awff$FULL_N), + .EMPTY_N(merged_1_awff$EMPTY_N)); + + // submodule merged_1_wff + FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_1_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_1_wff$D_IN), + .ENQ(merged_1_wff$ENQ), + .DEQ(merged_1_wff$DEQ), + .CLR(merged_1_wff$CLR), + .D_OUT(merged_1_wff$D_OUT), + .FULL_N(merged_1_wff$FULL_N), + .EMPTY_N(merged_1_wff$EMPTY_N)); + + // submodule msNoSynth_0_arNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_arNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_arNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_arNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_arNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_arNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_0_b_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_0_b_buffer_firstValid$D_IN), - .EN(msNoSynth_0_b_buffer_firstValid$EN), - .Q_OUT(msNoSynth_0_b_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_arNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_arNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_0_r_buffer_ff + // submodule msNoSynth_0_awNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_awNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_awNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_awNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_awNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_awNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_awNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_awNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_bNoSynth_buffer_ff + FIFO1 #(.width(32'd6), + .guarded(32'd0)) msNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_bNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_bNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_bNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_bNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_bNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_bNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_bNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), - .guarded(32'd0)) msNoSynth_0_r_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_0_r_buffer_ff$D_IN), - .ENQ(msNoSynth_0_r_buffer_ff$ENQ), - .DEQ(msNoSynth_0_r_buffer_ff$DEQ), - .CLR(msNoSynth_0_r_buffer_ff$CLR), - .D_OUT(msNoSynth_0_r_buffer_ff$D_OUT), - .FULL_N(msNoSynth_0_r_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_0_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) msNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_rNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_rNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_rNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_rNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_rNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_0_r_buffer_firstValid + // submodule msNoSynth_0_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_0_r_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_0_r_buffer_firstValid$D_IN), - .EN(msNoSynth_0_r_buffer_firstValid$EN), - .Q_OUT(msNoSynth_0_r_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_rNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_rNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_1_b_buffer_ff - FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_1_b_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_1_b_buffer_ff$D_IN), - .ENQ(msNoSynth_1_b_buffer_ff$ENQ), - .DEQ(msNoSynth_1_b_buffer_ff$DEQ), - .CLR(msNoSynth_1_b_buffer_ff$CLR), - .D_OUT(msNoSynth_1_b_buffer_ff$D_OUT), - .FULL_N(msNoSynth_1_b_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_1_b_buffer_ff$EMPTY_N)); + // submodule msNoSynth_0_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) msNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_wNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_wNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_wNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_wNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_wNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_1_b_buffer_firstValid + // submodule msNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_1_b_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_1_b_buffer_firstValid$D_IN), - .EN(msNoSynth_1_b_buffer_firstValid$EN), - .Q_OUT(msNoSynth_1_b_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_wNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_wNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_1_r_buffer_ff + // submodule msNoSynth_1_arNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_arNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_arNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_arNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_arNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_arNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_arNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_arNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_arNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_awNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_awNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_awNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_awNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_awNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_awNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_awNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_awNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_bNoSynth_buffer_ff + FIFO1 #(.width(32'd6), + .guarded(32'd0)) msNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_bNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_bNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_bNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_bNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_bNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_bNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_bNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), - .guarded(32'd0)) msNoSynth_1_r_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_1_r_buffer_ff$D_IN), - .ENQ(msNoSynth_1_r_buffer_ff$ENQ), - .DEQ(msNoSynth_1_r_buffer_ff$DEQ), - .CLR(msNoSynth_1_r_buffer_ff$CLR), - .D_OUT(msNoSynth_1_r_buffer_ff$D_OUT), - .FULL_N(msNoSynth_1_r_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_1_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) msNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_rNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_rNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_rNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_rNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_rNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_1_r_buffer_firstValid + // submodule msNoSynth_1_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_1_r_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_1_r_buffer_firstValid$D_IN), - .EN(msNoSynth_1_r_buffer_firstValid$EN), - .Q_OUT(msNoSynth_1_r_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_rNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_rNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) msNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_wNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_wNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_wNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_wNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_wNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_wNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_wNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_wNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), @@ -3792,6 +4576,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), + .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), @@ -3802,12 +4587,14 @@ module mkCoreW(RST_N_dm_power_on_reset, .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), + .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wuser(plic$axi4_slave_wuser), + .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), @@ -3832,9 +4619,6 @@ module mkCoreW(RST_N_dm_power_on_reset, .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(), @@ -3868,6 +4652,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .debug_module_mem_server_arqos(proc$debug_module_mem_server_arqos), .debug_module_mem_server_arregion(proc$debug_module_mem_server_arregion), .debug_module_mem_server_arsize(proc$debug_module_mem_server_arsize), + .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), .debug_module_mem_server_awaddr(proc$debug_module_mem_server_awaddr), .debug_module_mem_server_awburst(proc$debug_module_mem_server_awburst), .debug_module_mem_server_awcache(proc$debug_module_mem_server_awcache), @@ -3878,12 +4663,14 @@ module mkCoreW(RST_N_dm_power_on_reset, .debug_module_mem_server_awqos(proc$debug_module_mem_server_awqos), .debug_module_mem_server_awregion(proc$debug_module_mem_server_awregion), .debug_module_mem_server_awsize(proc$debug_module_mem_server_awsize), + .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wuser(proc$debug_module_mem_server_wuser), + .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), .hart0_csr_mem_server_request_put(proc$hart0_csr_mem_server_request_put), .hart0_fpr_mem_server_request_put(proc$hart0_fpr_mem_server_request_put), .hart0_gpr_mem_server_request_put(proc$hart0_gpr_mem_server_request_put), @@ -3894,22 +4681,16 @@ module mkCoreW(RST_N_dm_power_on_reset, .master0_awready(proc$master0_awready), .master0_bid(proc$master0_bid), .master0_bresp(proc$master0_bresp), + .master0_bvalid(proc$master0_bvalid), .master0_rdata(proc$master0_rdata), .master0_rid(proc$master0_rid), .master0_rlast(proc$master0_rlast), .master0_rresp(proc$master0_rresp), .master0_ruser(proc$master0_ruser), + .master0_rvalid(proc$master0_rvalid), .master0_wready(proc$master0_wready), - .master1_arready(proc$master1_arready), - .master1_awready(proc$master1_awready), - .master1_bid(proc$master1_bid), - .master1_bresp(proc$master1_bresp), - .master1_rdata(proc$master1_rdata), - .master1_rid(proc$master1_rid), - .master1_rlast(proc$master1_rlast), - .master1_rresp(proc$master1_rresp), - .master1_ruser(proc$master1_ruser), - .master1_wready(proc$master1_wready), + .master1_b_put_val(proc$master1_b_put_val), + .master1_r_put_val(proc$master1_r_put_val), .non_maskable_interrupt_req_set_not_clear(proc$non_maskable_interrupt_req_set_not_clear), .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), @@ -3918,14 +4699,12 @@ module mkCoreW(RST_N_dm_power_on_reset, .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), - .master0_bvalid(proc$master0_bvalid), - .master0_rvalid(proc$master0_rvalid), - .master1_bvalid(proc$master1_bvalid), - .master1_rvalid(proc$master1_rvalid), + .EN_master1_aw_drop(proc$EN_master1_aw_drop), + .EN_master1_w_drop(proc$EN_master1_w_drop), + .EN_master1_b_put(proc$EN_master1_b_put), + .EN_master1_ar_drop(proc$EN_master1_ar_drop), + .EN_master1_r_put(proc$EN_master1_r_put), .EN_set_verbosity(proc$EN_set_verbosity), - .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), - .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), - .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), .EN_hart0_run_halt_server_response_get(proc$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(proc$EN_hart0_gpr_mem_server_request_put), @@ -3965,35 +4744,22 @@ module mkCoreW(RST_N_dm_power_on_reset, .master0_arregion(proc$master0_arregion), .master0_arvalid(proc$master0_arvalid), .master0_rready(proc$master0_rready), - .master1_awid(proc$master1_awid), - .master1_awaddr(proc$master1_awaddr), - .master1_awlen(proc$master1_awlen), - .master1_awsize(proc$master1_awsize), - .master1_awburst(proc$master1_awburst), - .master1_awlock(proc$master1_awlock), - .master1_awcache(proc$master1_awcache), - .master1_awprot(proc$master1_awprot), - .master1_awqos(proc$master1_awqos), - .master1_awregion(proc$master1_awregion), - .master1_awvalid(proc$master1_awvalid), - .master1_wdata(proc$master1_wdata), - .master1_wstrb(proc$master1_wstrb), - .master1_wlast(proc$master1_wlast), - .master1_wuser(), - .master1_wvalid(proc$master1_wvalid), - .master1_bready(proc$master1_bready), - .master1_arid(proc$master1_arid), - .master1_araddr(proc$master1_araddr), - .master1_arlen(proc$master1_arlen), - .master1_arsize(proc$master1_arsize), - .master1_arburst(proc$master1_arburst), - .master1_arlock(proc$master1_arlock), - .master1_arcache(proc$master1_arcache), - .master1_arprot(proc$master1_arprot), - .master1_arqos(proc$master1_arqos), - .master1_arregion(proc$master1_arregion), - .master1_arvalid(proc$master1_arvalid), - .master1_rready(proc$master1_rready), + .master1_aw_canPeek(proc$master1_aw_canPeek), + .master1_aw_peek(proc$master1_aw_peek), + .RDY_master1_aw_peek(proc$RDY_master1_aw_peek), + .RDY_master1_aw_drop(proc$RDY_master1_aw_drop), + .master1_w_canPeek(proc$master1_w_canPeek), + .master1_w_peek(proc$master1_w_peek), + .RDY_master1_w_peek(proc$RDY_master1_w_peek), + .RDY_master1_w_drop(proc$RDY_master1_w_drop), + .master1_b_canPut(proc$master1_b_canPut), + .RDY_master1_b_put(proc$RDY_master1_b_put), + .master1_ar_canPeek(proc$master1_ar_canPeek), + .master1_ar_peek(proc$master1_ar_peek), + .RDY_master1_ar_peek(proc$RDY_master1_ar_peek), + .RDY_master1_ar_drop(proc$RDY_master1_ar_drop), + .master1_r_canPut(proc$master1_r_canPut), + .RDY_master1_r_put(proc$RDY_master1_r_put), .RDY_set_verbosity(), .debug_module_mem_server_awready(proc$debug_module_mem_server_awready), .debug_module_mem_server_wready(proc$debug_module_mem_server_wready), @@ -4045,176 +4811,290 @@ module mkCoreW(RST_N_dm_power_on_reset, .m_mtvec_reset_value(), .m_nmivec_reset_value()); - // submodule ssNoSynth_0_ar_buffer_ff + // submodule ssNoSynth_0_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_0_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_0_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_ar_buffer_firstValid + // submodule ssNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_0_aw_buffer_ff + // submodule ssNoSynth_0_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_0_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_0_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_aw_buffer_firstValid + // submodule ssNoSynth_0_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_0_w_buffer_ff + // submodule ssNoSynth_0_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_0_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_w_buffer_ff$DEQ), - .CLR(ssNoSynth_0_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_w_buffer_firstValid + // submodule ssNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_ar_buffer_ff + // submodule ssNoSynth_1_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_1_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_1_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_ar_buffer_firstValid + // submodule ssNoSynth_1_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_aw_buffer_ff + // submodule ssNoSynth_1_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_1_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_1_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_aw_buffer_firstValid + // submodule ssNoSynth_1_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_w_buffer_ff + // submodule ssNoSynth_1_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_1_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_w_buffer_ff$DEQ), - .CLR(ssNoSynth_1_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_w_buffer_firstValid + // submodule ssNoSynth_1_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_ar_buffer_ff + // submodule ssNoSynth_2_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_2_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_2_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_ar_buffer_firstValid + // submodule ssNoSynth_2_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_aw_buffer_ff + // submodule ssNoSynth_2_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_2_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_2_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_aw_buffer_firstValid + // submodule ssNoSynth_2_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_w_buffer_ff + // submodule ssNoSynth_2_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_2_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_2_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_2_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_w_buffer_ff$DEQ), - .CLR(ssNoSynth_2_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_w_buffer_firstValid + // submodule ssNoSynth_2_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule tagController_tmp_awreqff FIFO2 #(.width(32'd98), @@ -4259,77 +5139,100 @@ module mkCoreW(RST_N_dm_power_on_reset, .memory_response_canPut(), .RDY_memory_response_put(tagController_tmp_tagCon$RDY_memory_response_put)); - // submodule tmp0_b_buffer_ff - FIFO1 #(.width(32'd6), - .guarded(32'd0)) tmp0_b_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp0_b_buffer_ff$D_IN), - .ENQ(tmp0_b_buffer_ff$ENQ), - .DEQ(tmp0_b_buffer_ff$DEQ), - .CLR(tmp0_b_buffer_ff$CLR), - .D_OUT(tmp0_b_buffer_ff$D_OUT), - .FULL_N(tmp0_b_buffer_ff$FULL_N), - .EMPTY_N(tmp0_b_buffer_ff$EMPTY_N)); + // submodule tmp2_arNoSynth_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) tmp2_arNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_arNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_arNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_arNoSynth_buffer_ff$DEQ), + .CLR(tmp2_arNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_arNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_arNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp0_b_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp0_b_buffer_firstValid(.CLK(CLK), - .D_IN(tmp0_b_buffer_firstValid$D_IN), - .EN(tmp0_b_buffer_firstValid$EN), - .Q_OUT(tmp0_b_buffer_firstValid$Q_OUT)); + // submodule tmp2_arNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_arNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_arNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp0_r_buffer_ff - FIFO1 #(.width(32'd72), - .guarded(32'd0)) tmp0_r_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp0_r_buffer_ff$D_IN), - .ENQ(tmp0_r_buffer_ff$ENQ), - .DEQ(tmp0_r_buffer_ff$DEQ), - .CLR(tmp0_r_buffer_ff$CLR), - .D_OUT(tmp0_r_buffer_ff$D_OUT), - .FULL_N(tmp0_r_buffer_ff$FULL_N), - .EMPTY_N(tmp0_r_buffer_ff$EMPTY_N)); + // submodule tmp2_awNoSynth_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) tmp2_awNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_awNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_awNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_awNoSynth_buffer_ff$DEQ), + .CLR(tmp2_awNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_awNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_awNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp0_r_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp0_r_buffer_firstValid(.CLK(CLK), - .D_IN(tmp0_r_buffer_firstValid$D_IN), - .EN(tmp0_r_buffer_firstValid$EN), - .Q_OUT(tmp0_r_buffer_firstValid$Q_OUT)); + // submodule tmp2_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_awNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_awNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp2_b_buffer_ff + // submodule tmp2_bNoSynth_buffer_ff FIFO1 #(.width(32'd7), - .guarded(32'd0)) tmp2_b_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp2_b_buffer_ff$D_IN), - .ENQ(tmp2_b_buffer_ff$ENQ), - .DEQ(tmp2_b_buffer_ff$DEQ), - .CLR(tmp2_b_buffer_ff$CLR), - .D_OUT(tmp2_b_buffer_ff$D_OUT), - .FULL_N(tmp2_b_buffer_ff$FULL_N), - .EMPTY_N(tmp2_b_buffer_ff$EMPTY_N)); + .guarded(32'd0)) tmp2_bNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_bNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_bNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_bNoSynth_buffer_ff$DEQ), + .CLR(tmp2_bNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_bNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_bNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp2_b_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp2_b_buffer_firstValid(.CLK(CLK), - .D_IN(tmp2_b_buffer_firstValid$D_IN), - .EN(tmp2_b_buffer_firstValid$EN), - .Q_OUT(tmp2_b_buffer_firstValid$Q_OUT)); + // submodule tmp2_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_bNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_bNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_bNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp2_r_buffer_ff + // submodule tmp2_rNoSynth_buffer_ff FIFO1 #(.width(32'd73), - .guarded(32'd0)) tmp2_r_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp2_r_buffer_ff$D_IN), - .ENQ(tmp2_r_buffer_ff$ENQ), - .DEQ(tmp2_r_buffer_ff$DEQ), - .CLR(tmp2_r_buffer_ff$CLR), - .D_OUT(tmp2_r_buffer_ff$D_OUT), - .FULL_N(tmp2_r_buffer_ff$FULL_N), - .EMPTY_N(tmp2_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) tmp2_rNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_rNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_rNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_rNoSynth_buffer_ff$DEQ), + .CLR(tmp2_rNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_rNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_rNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp2_r_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp2_r_buffer_firstValid(.CLK(CLK), - .D_IN(tmp2_r_buffer_firstValid$D_IN), - .EN(tmp2_r_buffer_firstValid$EN), - .Q_OUT(tmp2_r_buffer_firstValid$Q_OUT)); + // submodule tmp2_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_rNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_rNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule tmp2_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) tmp2_wNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_wNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_wNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_wNoSynth_buffer_ff$DEQ), + .CLR(tmp2_wNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_wNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_wNoSynth_buffer_ff$EMPTY_N)); + + // submodule tmp2_wNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_wNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_wNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule uncached_mem_shim_arff FIFO2 #(.width(32'd98), @@ -4478,7 +5381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst assign CAN_FIRE_RL_burst = ifcs_0_innerReq$EMPTY_N && ifcs_0_innerRoute$EMPTY_N && - state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556 ; + state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 ; assign WILL_FIRE_RL_burst = CAN_FIRE_RL_burst ; // rule RL_source_selected_1 @@ -4491,38 +5394,132 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_1 assign CAN_FIRE_RL_burst_1 = ifcs_1_innerReq$EMPTY_N && ifcs_1_innerRoute$EMPTY_N && - state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600 ; + state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 ; assign WILL_FIRE_RL_burst_1 = CAN_FIRE_RL_burst_1 ; - // rule __me_check_182 - assign CAN_FIRE___me_check_182 = 1'b1 ; - assign WILL_FIRE___me_check_182 = 1'b1 ; + // rule __me_check_355 + assign CAN_FIRE___me_check_355 = 1'b1 ; + assign WILL_FIRE___me_check_355 = 1'b1 ; - // rule __me_check_184 - assign CAN_FIRE___me_check_184 = 1'b1 ; - assign WILL_FIRE___me_check_184 = 1'b1 ; + // rule __me_check_357 + assign CAN_FIRE___me_check_357 = 1'b1 ; + assign WILL_FIRE___me_check_357 = 1'b1 ; // rule RL_sink_selected assign CAN_FIRE_RL_sink_selected = - IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425 && - flitToSink_0$whas ; + flitToSink_0$whas && + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 ; assign WILL_FIRE_RL_sink_selected = CAN_FIRE_RL_sink_selected ; // rule RL_sink_selected_1 assign CAN_FIRE_RL_sink_selected_1 = - IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426 && - flitToSink_1$whas ; + flitToSink_1$whas && + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 ; assign WILL_FIRE_RL_sink_selected_1 = CAN_FIRE_RL_sink_selected_1 ; // rule RL_sink_selected_2 assign CAN_FIRE_RL_sink_selected_2 = - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 && - flitToSink_2$whas ; + flitToSink_2$whas && + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 ; assign WILL_FIRE_RL_sink_selected_2 = CAN_FIRE_RL_sink_selected_2 ; - // rule __me_check_186 - assign CAN_FIRE___me_check_186 = 1'b1 ; - assign WILL_FIRE___me_check_186 = 1'b1 ; + // rule __me_check_359 + assign CAN_FIRE___me_check_359 = 1'b1 ; + assign WILL_FIRE___me_check_359 = 1'b1 ; + + // rule RL_checkSinkReady_3 + assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + + // rule RL_checkSinkReady_4 + assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + + // rule RL_craftReq_2 + assign CAN_FIRE_RL_craftReq_2 = + ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; + + // rule RL_craftReq_3 + assign CAN_FIRE_RL_craftReq_3 = + ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; + + // rule RL_craftReq_4 + assign CAN_FIRE_RL_craftReq_4 = + ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; + + // rule RL_arbitrate_1 + assign CAN_FIRE_RL_arbitrate_1 = + reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 && + !state_1 ; + assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; + + // rule RL_source_selected_2 + assign CAN_FIRE_RL_source_selected_2 = + (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_0$whas ; + assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; + + // rule RL_burst_2 + assign CAN_FIRE_RL_burst_2 = + ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 ; + assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; + + // rule RL_source_selected_3 + assign CAN_FIRE_RL_source_selected_3 = + (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_1$whas ; + assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; + + // rule RL_burst_3 + assign CAN_FIRE_RL_burst_3 = + ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 ; + assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; + + // rule __me_check_374 + assign CAN_FIRE___me_check_374 = 1'b1 ; + assign WILL_FIRE___me_check_374 = 1'b1 ; + + // rule RL_source_selected_4 + assign CAN_FIRE_RL_source_selected_4 = + (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_2$whas ; + assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; + + // rule RL_burst_4 + assign CAN_FIRE_RL_burst_4 = + ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 ; + assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; + + // rule __me_check_372 + assign CAN_FIRE___me_check_372 = 1'b1 ; + assign WILL_FIRE___me_check_372 = 1'b1 ; + + // rule __me_check_376 + assign CAN_FIRE___me_check_376 = 1'b1 ; + assign WILL_FIRE___me_check_376 = 1'b1 ; + + // rule RL_sink_selected_3 + assign CAN_FIRE_RL_sink_selected_3 = + flitToSink_1_0$whas && msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; + + // rule RL_sink_selected_4 + assign CAN_FIRE_RL_sink_selected_4 = + flitToSink_1_1$whas && msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; + + // rule __me_check_378 + assign CAN_FIRE___me_check_378 = 1'b1 ; + assign WILL_FIRE___me_check_378 = 1'b1 ; // rule RL_checkSinkReady_5 assign CAN_FIRE_RL_checkSinkReady_5 = 1'd1 ; @@ -4563,7 +5560,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_5 assign CAN_FIRE_RL_burst_5 = ifcs_0_1_innerReq$EMPTY_N && ifcs_0_1_innerRoute$EMPTY_N && - state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193 ; + state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 ; assign WILL_FIRE_RL_burst_5 = CAN_FIRE_RL_burst_5 ; // rule RL_source_selected_6 @@ -4576,92 +5573,205 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_6 assign CAN_FIRE_RL_burst_6 = ifcs_1_1_innerReq$EMPTY_N && ifcs_1_1_innerRoute$EMPTY_N && - state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233 ; + state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 ; assign WILL_FIRE_RL_burst_6 = CAN_FIRE_RL_burst_6 ; - // rule __me_check_229 - assign CAN_FIRE___me_check_229 = 1'b1 ; - assign WILL_FIRE___me_check_229 = 1'b1 ; + // rule __me_check_414 + assign CAN_FIRE___me_check_414 = 1'b1 ; + assign WILL_FIRE___me_check_414 = 1'b1 ; - // rule __me_check_231 - assign CAN_FIRE___me_check_231 = 1'b1 ; - assign WILL_FIRE___me_check_231 = 1'b1 ; + // rule __me_check_416 + assign CAN_FIRE___me_check_416 = 1'b1 ; + assign WILL_FIRE___me_check_416 = 1'b1 ; // rule RL_sink_selected_5 assign CAN_FIRE_RL_sink_selected_5 = - ssNoSynth_0_ar_buffer_ff$FULL_N && flitToSink_1_0_1$whas ; + flitToSink_1_0_1$whas && ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_5 = CAN_FIRE_RL_sink_selected_5 ; // rule RL_sink_selected_6 assign CAN_FIRE_RL_sink_selected_6 = - ssNoSynth_1_ar_buffer_ff$FULL_N && flitToSink_1_1_1$whas ; + flitToSink_1_1_1$whas && ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_6 = CAN_FIRE_RL_sink_selected_6 ; // rule RL_sink_selected_7 assign CAN_FIRE_RL_sink_selected_7 = - ssNoSynth_2_ar_buffer_ff$FULL_N && flitToSink_1_2$whas ; + flitToSink_1_2$whas && ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_7 = CAN_FIRE_RL_sink_selected_7 ; - // rule __me_check_233 - assign CAN_FIRE___me_check_233 = 1'b1 ; - assign WILL_FIRE___me_check_233 = 1'b1 ; + // rule __me_check_418 + assign CAN_FIRE___me_check_418 = 1'b1 ; + assign WILL_FIRE___me_check_418 = 1'b1 ; + + // rule RL_checkSinkReady_8 + assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; + + // rule RL_checkSinkReady_9 + assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; + + // rule RL_craftReq_7 + assign CAN_FIRE_RL_craftReq_7 = + ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; + + // rule RL_craftReq_8 + assign CAN_FIRE_RL_craftReq_8 = + ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; + + // rule RL_craftReq_9 + assign CAN_FIRE_RL_craftReq_9 = + ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; + + // rule RL_arbitrate_3 + assign CAN_FIRE_RL_arbitrate_3 = + reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 && + !state_1_1_1 ; + assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; + + // rule RL_source_selected_7 + assign CAN_FIRE_RL_source_selected_7 = + (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; + + // rule RL_burst_7 + assign CAN_FIRE_RL_burst_7 = + ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 ; + assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; + + // rule RL_source_selected_8 + assign CAN_FIRE_RL_source_selected_8 = + (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_1_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; + + // rule RL_burst_8 + assign CAN_FIRE_RL_burst_8 = + ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 ; + assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; + + // rule __me_check_433 + assign CAN_FIRE___me_check_433 = 1'b1 ; + assign WILL_FIRE___me_check_433 = 1'b1 ; + + // rule RL_source_selected_9 + assign CAN_FIRE_RL_source_selected_9 = + (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_2$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; + + // rule RL_burst_9 + assign CAN_FIRE_RL_burst_9 = + ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 ; + assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; + + // rule __me_check_431 + assign CAN_FIRE___me_check_431 = 1'b1 ; + assign WILL_FIRE___me_check_431 = 1'b1 ; + + // rule __me_check_435 + assign CAN_FIRE___me_check_435 = 1'b1 ; + assign WILL_FIRE___me_check_435 = 1'b1 ; + + // rule RL_sink_selected_8 + assign CAN_FIRE_RL_sink_selected_8 = + flitToSink_1_1_0$whas && msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; + + // rule RL_sink_selected_9 + assign CAN_FIRE_RL_sink_selected_9 = + flitToSink_1_1_1_1$whas && + msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; + + // rule __me_check_437 + assign CAN_FIRE___me_check_437 = 1'b1 ; + assign WILL_FIRE___me_check_437 = 1'b1 ; // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_ug_uncached_mem_shim_master_u_aw_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + // rule RL_proc_uncached_awSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek = + proc$RDY_master1_aw_peek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek = + proc$RDY_master1_aw_peek ; + + // rule RL_proc_uncached_wSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek = + proc$RDY_master1_w_peek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek = + proc$RDY_master1_w_peek ; + + // rule RL_proc_uncached_arSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek = + proc$RDY_master1_ar_peek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek = + proc$RDY_master1_ar_peek ; + + // rule RL_uncached_mem_master_awSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = - ug_uncached_mem_shim_master_u_aw_dropWire$whas && + // rule RL_uncached_mem_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = + uncached_mem_master_awSynth_src_dropWire$whas && !uncached_mem_shim_awff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_w_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + // rule RL_uncached_mem_master_wSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_w_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = - ug_uncached_mem_shim_master_u_w_dropWire$whas && + // rule RL_uncached_mem_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = + uncached_mem_master_wSynth_src_dropWire$whas && !uncached_mem_shim_wff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_b_warnDoPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = - ug_uncached_mem_shim_master_u_b_putWire$whas && + // rule RL_uncached_mem_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = + uncached_mem_master_bSynth_snk_putWire$whas && !uncached_mem_shim_bff$FULL_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut ; - // rule RL_ug_uncached_mem_shim_master_u_ar_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + // rule RL_uncached_mem_master_arSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = - ug_uncached_mem_shim_master_u_ar_dropWire$whas && + // rule RL_uncached_mem_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = + uncached_mem_master_arSynth_src_dropWire$whas && !uncached_mem_shim_arff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_r_warnDoPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = - ug_uncached_mem_shim_master_u_r_putWire$whas && + // rule RL_uncached_mem_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = + uncached_mem_master_rSynth_snk_putWire$whas && !uncached_mem_shim_rff$FULL_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut ; // rule RL_tagController_tmp_passCacheResponse assign CAN_FIRE_RL_tagController_tmp_passCacheResponse = @@ -4699,113 +5809,176 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek ; - // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = - tagController_tmp_ug_master_u_aw_dropWire$whas && - !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; - - // rule RL_tagController_tmp_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = - tagController_tmp_shimMaster_awff_rv$port1__read[99] && - tagController_tmp_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; - // rule RL_tagController_tmp_ug_master_u_w_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = tagController_tmp_shimMaster_wff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek ; - // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = - tagController_tmp_ug_master_u_w_dropWire$whas && - !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; - - // rule RL_tagController_tmp_ug_master_u_w_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = - tagController_tmp_shimMaster_wff_rv$port1__read[73] && - tagController_tmp_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; - - // rule RL_tagController_tmp_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = - tagController_tmp_ug_master_u_b_putWire$whas && - tagController_tmp_shimMaster_bff_rv[8] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; - - // rule RL_tagController_tmp_ug_master_u_b_doPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = - !tagController_tmp_shimMaster_bff_rv[8] && - tagController_tmp_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; - // rule RL_tagController_tmp_ug_master_u_ar_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = tagController_tmp_shimMaster_arff_rv$port1__read[99] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek ; - // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = - tagController_tmp_ug_master_u_ar_dropWire$whas && - !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; + // rule RL_tmp2_awNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit = + proc$master0_awvalid && tmp2_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; - // rule RL_tagController_tmp_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = - tagController_tmp_shimMaster_arff_rv$port1__read[99] && - tagController_tmp_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; + // rule RL_tmp2_awNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; - // rule RL_tagController_tmp_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = - tagController_tmp_ug_master_u_r_putWire$whas && - tagController_tmp_shimMaster_rff_rv[73] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; + // rule RL_tmp2_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit && + !tmp2_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut ; - // rule RL_tagController_tmp_ug_master_u_r_doPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = - !tagController_tmp_shimMaster_rff_rv[73] && - tagController_tmp_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; + // rule RL_tmp2_awNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut = + tmp2_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut ; - // rule RL_tagController_tmp_passMemoryResponseWrite - assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = - tagController_tmp_shimMaster_bff_rv$port1__read[8] && - tagController_tmp_tagCon$RDY_memory_response_put ; - assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = - CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && - !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + // rule RL_tmp2_wNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit = + proc$master0_wvalid && tmp2_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; - // rule RL_tagController_tmp_passMemoryResponseRead - assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = - tagController_tmp_shimMaster_rff_rv$port1__read[73] && - tagController_tmp_tagCon$RDY_memory_response_put ; - assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = - CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + // rule RL_tmp2_wNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = - !tagController_tmp_shimSlave_awff_rv[98] && - proc$master0_awvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + // rule RL_tmp2_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit && + !tmp2_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut ; + + // rule RL_tmp2_wNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut = + tmp2_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut ; + + // rule RL_tmp2_bNoSynth_dropFlit + assign CAN_FIRE_RL_tmp2_bNoSynth_dropFlit = + tmp2_bNoSynth_buffer_ff$EMPTY_N && proc$master0_bready ; + assign WILL_FIRE_RL_tmp2_bNoSynth_dropFlit = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit ; + + // rule RL_tmp2_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && + !tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop ; + + // rule RL_tmp2_arNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit = + proc$master0_arvalid && tmp2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; + + // rule RL_tmp2_arNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_tmp2_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit && + !tmp2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut ; + + // rule RL_tmp2_arNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut = + tmp2_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut ; + + // rule RL_tmp2_rNoSynth_dropFlit + assign CAN_FIRE_RL_tmp2_rNoSynth_dropFlit = + tmp2_rNoSynth_buffer_ff$EMPTY_N && proc$master0_rready ; + assign WILL_FIRE_RL_tmp2_rNoSynth_dropFlit = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit ; + + // rule RL_tmp2_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && + !tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = + tmp2_awNoSynth_buffer_firstValid$Q_OUT && + (tmp2_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek ; + + // rule RL_Prelude_inst_changeSpecialWires_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + !tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; + + // rule RL_tmp2_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop || + tmp2_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; + + // rule RL_tmp2_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop && + tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + tagController_tmp_shimSlave_awff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = + tmp2_awNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_awff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_aw_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && tagController_tmp_shimSlave_awff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut ; @@ -4813,7 +5986,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_aw_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = !tagController_tmp_shimSlave_awff_rv[98] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut ; @@ -4824,19 +5997,66 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_getCacheAW = CAN_FIRE_RL_tagController_tmp_getCacheAW ; - // rule RL_tmp2_aw_forwardReady - assign CAN_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = + tmp2_wNoSynth_buffer_firstValid$Q_OUT && + (tmp2_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek ; - // rule RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = - !tagController_tmp_shimSlave_wff_rv[74] && proc$master0_wvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + // rule RL_Prelude_inst_changeSpecialWires_1_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + !tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; + + // rule RL_tmp2_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop || + tmp2_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; + + // rule RL_tmp2_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop && + tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + tagController_tmp_shimSlave_wff_rv[74] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = + tmp2_wNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_wff_rv[74] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_w_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && tagController_tmp_shimSlave_wff_rv[74] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut ; @@ -4844,24 +6064,39 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_w_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = !tagController_tmp_shimSlave_wff_rv[74] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut ; - // rule RL_tmp2_w_forwardReady - assign CAN_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = + 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = + // rule RL_Prelude_inst_changeSpecialWires_2_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = tagController_tmp_shimSlave_bff_rv$port1__read[7] && - tmp2_b_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + tmp2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; + + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_b_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop && !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop ; @@ -4869,47 +6104,118 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_b_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = tagController_tmp_shimSlave_bff_rv$port1__read[7] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop ; - // rule RL_tmp2_b_forwardFlit - assign CAN_FIRE_RL_tmp2_b_forwardFlit = - tmp2_b_buffer_firstValid$Q_OUT && - (tmp2_b_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) ; - assign WILL_FIRE_RL_tmp2_b_forwardFlit = CAN_FIRE_RL_tmp2_b_forwardFlit ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + !tmp2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut ; - // rule RL_tmp2_b_dropFlit - assign CAN_FIRE_RL_tmp2_b_dropFlit = - (tmp2_b_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) && - proc$master0_bready ; - assign WILL_FIRE_RL_tmp2_b_dropFlit = CAN_FIRE_RL_tmp2_b_dropFlit ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = + tmp2_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut ; - // rule RL_tmp2_b_buffer_enqueue - assign CAN_FIRE_RL_tmp2_b_buffer_enqueue = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && - (!CAN_FIRE_RL_tmp2_b_dropFlit || tmp2_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp2_b_buffer_enqueue = - CAN_FIRE_RL_tmp2_b_buffer_enqueue ; + // rule RL_tmp2_bNoSynth_src_setPeek + assign CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek = + tmp2_bNoSynth_buffer_firstValid$Q_OUT && + (tmp2_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut) ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek = + CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek ; - // rule RL_tmp2_b_buffer_dequeue - assign CAN_FIRE_RL_tmp2_b_buffer_dequeue = - CAN_FIRE_RL_tmp2_b_dropFlit && tmp2_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp2_b_buffer_dequeue = - CAN_FIRE_RL_tmp2_b_buffer_dequeue ; + // rule RL_tmp2_bNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = - !tagController_tmp_shimSlave_arff_rv[98] && - proc$master0_arvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + // rule RL_tmp2_bNoSynth_src_doDrop + assign CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && + tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; + + // rule RL_tmp2_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut && + (!CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop || + tmp2_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; + + // rule RL_tmp2_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop && + tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = + tmp2_arNoSynth_buffer_firstValid$Q_OUT && + (tmp2_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek ; + + // rule RL_Prelude_inst_changeSpecialWires_3_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + !tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; + + // rule RL_tmp2_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop || + tmp2_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; + + // rule RL_tmp2_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop && + tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + tagController_tmp_shimSlave_arff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = + tmp2_arNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_arff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_ar_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && tagController_tmp_shimSlave_arff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut ; @@ -4917,7 +6223,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_ar_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = !tagController_tmp_shimSlave_arff_rv[98] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut ; @@ -4937,20 +6243,35 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_passCacheRead = CAN_FIRE_RL_tagController_tmp_passCacheRead ; - // rule RL_tmp2_ar_forwardReady - assign CAN_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = + 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = + // rule RL_Prelude_inst_changeSpecialWires_4_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = tagController_tmp_shimSlave_rff_rv$port1__read[73] && - tmp2_r_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + tmp2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; + + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_r_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop && !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop ; @@ -4958,1182 +6279,1319 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_r_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = tagController_tmp_shimSlave_rff_rv$port1__read[73] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop ; - // rule RL_tagController_tmp_propagateReset - assign CAN_FIRE_RL_tagController_tmp_propagateReset = - !tagController_tmp_reset_done ; - assign WILL_FIRE_RL_tagController_tmp_propagateReset = - CAN_FIRE_RL_tagController_tmp_propagateReset ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + !tmp2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut ; - // rule RL_tmp2_r_forwardFlit - assign CAN_FIRE_RL_tmp2_r_forwardFlit = - tmp2_r_buffer_firstValid$Q_OUT && - (tmp2_r_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) ; - assign WILL_FIRE_RL_tmp2_r_forwardFlit = CAN_FIRE_RL_tmp2_r_forwardFlit ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = + tmp2_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut ; - // rule RL_tmp2_r_dropFlit - assign CAN_FIRE_RL_tmp2_r_dropFlit = - (tmp2_r_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) && - proc$master0_rready ; - assign WILL_FIRE_RL_tmp2_r_dropFlit = CAN_FIRE_RL_tmp2_r_dropFlit ; + // rule RL_tmp2_rNoSynth_src_setPeek + assign CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek = + tmp2_rNoSynth_buffer_firstValid$Q_OUT && + (tmp2_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut) ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek = + CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek ; - // rule RL_tmp2_r_buffer_enqueue - assign CAN_FIRE_RL_tmp2_r_buffer_enqueue = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && - (!CAN_FIRE_RL_tmp2_r_dropFlit || tmp2_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp2_r_buffer_enqueue = - CAN_FIRE_RL_tmp2_r_buffer_enqueue ; + // rule RL_tmp2_rNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; - // rule RL_tmp2_r_buffer_dequeue - assign CAN_FIRE_RL_tmp2_r_buffer_dequeue = - CAN_FIRE_RL_tmp2_r_dropFlit && tmp2_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp2_r_buffer_dequeue = - CAN_FIRE_RL_tmp2_r_buffer_dequeue ; + // rule RL_tmp2_rNoSynth_src_doDrop + assign CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && + tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; - // rule RL_ssNoSynth_0_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit = - !uncached_mem_shim_arff$FULL_N || - ssNoSynth_0_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_0_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_5) && - uncached_mem_shim_arff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + // rule RL_tmp2_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut && + (!CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop || + tmp2_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; - // rule RL_ssNoSynth_0_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit = - (ssNoSynth_0_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_5) && - uncached_mem_shim_arff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit ; + // rule RL_tmp2_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop && + tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; - // rule RL_ug_uncached_mem_shim_master_u_ar_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = - uncached_mem_shim_arff$EMPTY_N && - ug_uncached_mem_shim_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + // rule RL_slave_vector_0_bSynth_src_setPeek + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek = + uncached_mem_shim_bff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek = + uncached_mem_shim_bff$EMPTY_N ; - // rule RL_ssNoSynth_0_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_5 && - (!WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit || - ssNoSynth_0_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + // rule RL_slave_vector_0_rSynth_src_setPeek + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek = + uncached_mem_shim_rff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek = + uncached_mem_shim_rff$EMPTY_N ; - // rule RL_ssNoSynth_0_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit && - ssNoSynth_0_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + // rule RL_msNoSynth_0_awNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = + proc$master1_aw_canPeek && + msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; - // rule RL_ssNoSynth_1_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit = - ssNoSynth_1_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_1_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_6) ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; + // rule RL_msNoSynth_0_awNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_1_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit = - (ssNoSynth_1_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_6) && - plic$axi4_slave_arready ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + // rule RL_proc_uncached_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + !proc$master1_aw_canPeek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_6 && - (!CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit || - ssNoSynth_1_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + // rule RL_proc_uncached_awSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop = + proc$RDY_master1_aw_drop && + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + proc$master1_aw_canPeek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; - // rule RL_ssNoSynth_1_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit && - ssNoSynth_1_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + // rule RL_msNoSynth_0_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + !msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut ; - // rule RL_ssNoSynth_2_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit = - ssNoSynth_2_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_2_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_7) ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + // rule RL_msNoSynth_0_awNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = + msNoSynth_0_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut ; - // rule RL_ssNoSynth_2_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit = - (ssNoSynth_2_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_7) && - proc$debug_module_mem_server_arready ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + // rule RL_msNoSynth_0_wNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = + proc$master1_w_canPeek && msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; - // rule RL_ssNoSynth_2_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_7 && - (!CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit || - ssNoSynth_2_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + // rule RL_msNoSynth_0_wNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_2_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit && - ssNoSynth_2_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + // rule RL_proc_uncached_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + !proc$master1_w_canPeek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop ; - // rule RL_split_0_putFirst - assign CAN_FIRE_RL_split_0_putFirst = - split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 && - split_0_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + // rule RL_proc_uncached_wSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop = + proc$RDY_master1_w_drop && + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + proc$master1_w_canPeek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; - // rule RL_ssNoSynth_0_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit = - !uncached_mem_shim_awff$FULL_N || - ssNoSynth_0_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_0_aw_buffer_ff$EMPTY_N || - MUX_split_0_flitLeft$write_1__SEL_2) && + // rule RL_msNoSynth_0_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + !msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_0_wNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = + msNoSynth_0_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && proc$master1_b_canPut ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; + + // rule RL_msNoSynth_0_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + !msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_0_arNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = + proc$master1_ar_canPeek && + msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; + + // rule RL_msNoSynth_0_arNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_proc_uncached_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + !proc$master1_ar_canPeek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop ; + + // rule RL_proc_uncached_arSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop = + proc$RDY_master1_ar_drop && + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + proc$master1_ar_canPeek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; + + // rule RL_msNoSynth_0_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + !msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_0_arNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = + msNoSynth_0_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && proc$master1_r_canPut ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; + + // rule RL_msNoSynth_0_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + !msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_1_bNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + debug_module$master_bready ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit ; + + // rule RL_msNoSynth_1_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && + !msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_1_rNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + debug_module$master_rready ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit ; + + // rule RL_msNoSynth_1_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && + !msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_0_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_awff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_0_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit = - (ssNoSynth_0_aw_buffer_ff$EMPTY_N || - MUX_split_0_flitLeft$write_1__SEL_2) && - uncached_mem_shim_awff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit ; + // rule RL_ssNoSynth_0_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + !ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_aw_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = - uncached_mem_shim_awff$EMPTY_N && - ug_uncached_mem_shim_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; - - // rule RL_ssNoSynth_0_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = - MUX_split_0_flitLeft$write_1__SEL_2 && - (!WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit || - ssNoSynth_0_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; - - // rule RL_ssNoSynth_0_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit && - ssNoSynth_0_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; - - // rule RL_split_0_putOther - assign CAN_FIRE_RL_split_0_putOther = - CAN_FIRE_RL_sink_selected && - (!split_0_doPut$wget[172] || ssNoSynth_0_w_buffer_ff$FULL_N) && - split_0_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; - - // rule RL_ssNoSynth_0_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit = - !uncached_mem_shim_wff$FULL_N || - ssNoSynth_0_w_buffer_firstValid$Q_OUT && - (ssNoSynth_0_w_buffer_ff$EMPTY_N || - ssNoSynth_0_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_0_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_wff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_0_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_w_dropFlit = - (ssNoSynth_0_w_buffer_ff$EMPTY_N || - ssNoSynth_0_w_buffer_enqw$whas) && - uncached_mem_shim_wff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_w_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit ; + // rule RL_ssNoSynth_0_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + !ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_w_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = - uncached_mem_shim_wff$EMPTY_N && - ug_uncached_mem_shim_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + // rule RL_ssNoSynth_0_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = + uncached_mem_shim_bff$EMPTY_N && + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; - // rule RL_ssNoSynth_0_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = - ssNoSynth_0_w_buffer_enqw$whas && - (!WILL_FIRE_RL_ssNoSynth_0_w_dropFlit || - ssNoSynth_0_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + // rule RL_ssNoSynth_0_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_0_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit && - ssNoSynth_0_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + // rule RL_slave_vector_0_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && + !uncached_mem_shim_bff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = + CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop ; - // rule RL_split_1_putFirst - assign CAN_FIRE_RL_split_1_putFirst = - split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 && - split_1_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + // rule RL_slave_vector_0_bSynth_src_doDrop + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop = + uncached_mem_shim_bff$EMPTY_N && + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop = + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; - // rule RL_ssNoSynth_1_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit = - ssNoSynth_1_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_1_aw_buffer_ff$EMPTY_N || - MUX_split_1_flitLeft$write_1__SEL_2) ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + // rule RL_uncached_mem_master_bSynth_snk_doPut + assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = + uncached_mem_shim_bff$FULL_N && + uncached_mem_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; - // rule RL_ssNoSynth_1_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit = - (ssNoSynth_1_aw_buffer_ff$EMPTY_N || - MUX_split_1_flitLeft$write_1__SEL_2) && + // rule RL_ssNoSynth_0_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && + !ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_0_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_0_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + !ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_0_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = + uncached_mem_shim_rff$EMPTY_N && + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_0_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_slave_vector_0_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && + !uncached_mem_shim_rff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = + CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop ; + + // rule RL_slave_vector_0_rSynth_src_doDrop + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop = + uncached_mem_shim_rff$EMPTY_N && + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop = + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; + + // rule RL_uncached_mem_master_rSynth_snk_doPut + assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = + uncached_mem_shim_rff$FULL_N && + uncached_mem_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && + !ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_0_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_1_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_awready ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_1_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = - MUX_split_1_flitLeft$write_1__SEL_2 && - (!CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit || - ssNoSynth_1_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + // rule RL_ssNoSynth_1_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && + !ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit && - ssNoSynth_1_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; - - // rule RL_split_1_putOther - assign CAN_FIRE_RL_split_1_putOther = - CAN_FIRE_RL_sink_selected_1 && - (!split_1_doPut$wget[172] || ssNoSynth_1_w_buffer_ff$FULL_N) && - split_1_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; - - // rule RL_ssNoSynth_1_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit = - ssNoSynth_1_w_buffer_firstValid$Q_OUT && - (ssNoSynth_1_w_buffer_ff$EMPTY_N || - ssNoSynth_1_w_buffer_enqw$whas) ; - assign WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; - - // rule RL_ssNoSynth_1_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_w_dropFlit = - (ssNoSynth_1_w_buffer_ff$EMPTY_N || - ssNoSynth_1_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_1_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_wready ; - assign WILL_FIRE_RL_ssNoSynth_1_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_1_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = - ssNoSynth_1_w_buffer_enqw$whas && - (!CAN_FIRE_RL_ssNoSynth_1_w_dropFlit || - ssNoSynth_1_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + // rule RL_ssNoSynth_1_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && + !ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit && - ssNoSynth_1_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + // rule RL_ssNoSynth_1_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = + plic$axi4_slave_bvalid && ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; - // rule RL_split_2_putFirst - assign CAN_FIRE_RL_split_2_putFirst = - split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 && - split_2_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + // rule RL_ssNoSynth_1_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_2_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit = - ssNoSynth_2_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_2_aw_buffer_ff$EMPTY_N || - MUX_split_2_flitLeft$write_1__SEL_2) ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + // rule RL_ssNoSynth_1_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit && + !ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut ; - // rule RL_ssNoSynth_2_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit = - (ssNoSynth_2_aw_buffer_ff$EMPTY_N || - MUX_split_2_flitLeft$write_1__SEL_2) && + // rule RL_ssNoSynth_1_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = + ssNoSynth_1_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_1_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + plic$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_1_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && + !ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_1_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = + plic$axi4_slave_rvalid && ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_1_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_1_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit && + !ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_1_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = + ssNoSynth_1_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_2_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_awready ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_2_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = - MUX_split_2_flitLeft$write_1__SEL_2 && - (!CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit || - ssNoSynth_2_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + // rule RL_ssNoSynth_2_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && + !ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_2_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit && - ssNoSynth_2_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; - - // rule RL_split_2_putOther - assign CAN_FIRE_RL_split_2_putOther = - CAN_FIRE_RL_sink_selected_2 && - (!split_2_doPut$wget[172] || ssNoSynth_2_w_buffer_ff$FULL_N) && - split_2_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; - - // rule RL_ssNoSynth_2_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit = - ssNoSynth_2_w_buffer_firstValid$Q_OUT && - (ssNoSynth_2_w_buffer_ff$EMPTY_N || - ssNoSynth_2_w_buffer_enqw$whas) ; - assign WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; - - // rule RL_ssNoSynth_2_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_w_dropFlit = - (ssNoSynth_2_w_buffer_ff$EMPTY_N || - ssNoSynth_2_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_2_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_wready ; - assign WILL_FIRE_RL_ssNoSynth_2_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_2_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = - ssNoSynth_2_w_buffer_enqw$whas && - (!CAN_FIRE_RL_ssNoSynth_2_w_dropFlit || - ssNoSynth_2_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + // rule RL_ssNoSynth_2_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && + !ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_2_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit && - ssNoSynth_2_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + // rule RL_ssNoSynth_2_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N && + proc$debug_module_mem_server_arready ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_2_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && + !ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop ; + + // rule RL_merged_0_passFlit + assign CAN_FIRE_RL_merged_0_passFlit = + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_passFlit = CAN_FIRE_RL_merged_0_passFlit ; + + // rule RL_merged_1_passFlit + assign CAN_FIRE_RL_merged_1_passFlit = + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_passFlit = CAN_FIRE_RL_merged_1_passFlit ; // rule RL_ifcs_0_firstFlit assign CAN_FIRE_RL_ifcs_0_firstFlit = - proc$master1_wvalid && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && ifcs_0_innerRoute$FULL_N && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd0 && - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 == + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit = CAN_FIRE_RL_ifcs_0_firstFlit ; // rule RL_ifcs_0_followFlits assign CAN_FIRE_RL_ifcs_0_followFlits = - proc$master1_wvalid && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_followFlits = CAN_FIRE_RL_ifcs_0_followFlits ; // rule RL_ifcs_0_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_nonRoutableFlit = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + (!CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171] || + !ifcs_0_noRoute_inner_pendingReq) && ifcs_0_state == 2'd0 && - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 != + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_nonRoutableFlit ; // rule RL_ifcs_0_drainFlits assign CAN_FIRE_RL_ifcs_0_drainFlits = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - proc$master1_wvalid && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_drainFlits = CAN_FIRE_RL_ifcs_0_drainFlits ; - // rule __me_check_158 - assign CAN_FIRE___me_check_158 = 1'b1 ; - assign WILL_FIRE___me_check_158 = 1'b1 ; + // rule __me_check_325 + assign CAN_FIRE___me_check_325 = 1'b1 ; + assign WILL_FIRE___me_check_325 = 1'b1 ; - // rule RL_ifcs_0_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = - msNoSynth_0_b_buffer_ff$FULL_N && ifcs_0_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + // rule RL_ifcs_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_firstFlit = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_innerReq$FULL_N && + ifcs_1_innerRoute$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; - // rule RL_checkSinkReady_3 - assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + // rule RL_ifcs_1_followFlits + assign CAN_FIRE_RL_ifcs_1_followFlits = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_innerReq$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; - // rule RL_ifcs_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = - msNoSynth_1_b_buffer_ff$FULL_N && ifcs_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + // rule RL_ifcs_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + (!CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171] || + !ifcs_1_noRoute_inner_pendingReq) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; - // rule RL_checkSinkReady_4 - assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + // rule RL_ifcs_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_drainFlits = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; - // rule RL_craftReq_2 - assign CAN_FIRE_RL_craftReq_2 = - ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; - - // rule RL_craftReq_3 - assign CAN_FIRE_RL_craftReq_3 = - ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; - - // rule RL_craftReq_4 - assign CAN_FIRE_RL_craftReq_4 = - ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; - - // rule RL_arbitrate_1 - assign CAN_FIRE_RL_arbitrate_1 = - reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669 && - !state_1 ; - assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; - - // rule RL_source_selected_2 - assign CAN_FIRE_RL_source_selected_2 = - (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_0$whas ; - assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; - - // rule RL_burst_2 - assign CAN_FIRE_RL_burst_2 = - ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761 ; - assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; - - // rule RL_source_selected_3 - assign CAN_FIRE_RL_source_selected_3 = - (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_1$whas ; - assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; - - // rule RL_burst_3 - assign CAN_FIRE_RL_burst_3 = - ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794 ; - assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; - - // rule __me_check_197 - assign CAN_FIRE___me_check_197 = 1'b1 ; - assign WILL_FIRE___me_check_197 = 1'b1 ; - - // rule RL_source_selected_4 - assign CAN_FIRE_RL_source_selected_4 = - (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_2$whas ; - assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; - - // rule RL_burst_4 - assign CAN_FIRE_RL_burst_4 = - ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828 ; - assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; - - // rule __me_check_195 - assign CAN_FIRE___me_check_195 = 1'b1 ; - assign WILL_FIRE___me_check_195 = 1'b1 ; - - // rule __me_check_199 - assign CAN_FIRE___me_check_199 = 1'b1 ; - assign WILL_FIRE___me_check_199 = 1'b1 ; - - // rule RL_sink_selected_3 - assign CAN_FIRE_RL_sink_selected_3 = - !CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && flitToSink_1_0$whas ; - assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; - - // rule RL_sink_selected_4 - assign CAN_FIRE_RL_sink_selected_4 = - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && flitToSink_1_1$whas ; - assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; - - // rule __me_check_201 - assign CAN_FIRE___me_check_201 = 1'b1 ; - assign WILL_FIRE___me_check_201 = 1'b1 ; - - // rule RL_ifcs_0_forwardRsp - assign CAN_FIRE_RL_ifcs_0_forwardRsp = - msNoSynth_0_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_3 && - !ifcs_0_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_forwardRsp = CAN_FIRE_RL_ifcs_0_forwardRsp ; - - // rule RL_msNoSynth_0_b_forwardFlit - assign CAN_FIRE_RL_msNoSynth_0_b_forwardFlit = - !tmp0_b_buffer_ff$FULL_N || - msNoSynth_0_b_buffer_firstValid$Q_OUT && - (msNoSynth_0_b_buffer_ff$EMPTY_N || - msNoSynth_0_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_0_b_forwardFlit = - CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; - - // rule RL_tmp0_b_forwardFlit - assign CAN_FIRE_RL_tmp0_b_forwardFlit = - tmp0_b_buffer_firstValid$Q_OUT && - (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_tmp0_b_forwardFlit = CAN_FIRE_RL_tmp0_b_forwardFlit ; - - // rule RL_tmp0_b_dropFlit - assign CAN_FIRE_RL_tmp0_b_dropFlit = - (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) && - proc$master1_bready ; - assign WILL_FIRE_RL_tmp0_b_dropFlit = CAN_FIRE_RL_tmp0_b_dropFlit ; - - // rule RL_tmp0_b_buffer_enqueue - assign CAN_FIRE_RL_tmp0_b_buffer_enqueue = - tmp0_b_buffer_enqw$whas && - (!CAN_FIRE_RL_tmp0_b_dropFlit || tmp0_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp0_b_buffer_enqueue = - CAN_FIRE_RL_tmp0_b_buffer_enqueue ; - - // rule RL_tmp0_b_buffer_dequeue - assign CAN_FIRE_RL_tmp0_b_buffer_dequeue = - CAN_FIRE_RL_tmp0_b_dropFlit && tmp0_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp0_b_buffer_dequeue = - CAN_FIRE_RL_tmp0_b_buffer_dequeue ; - - // rule RL_msNoSynth_0_b_dropFlit - assign CAN_FIRE_RL_msNoSynth_0_b_dropFlit = - (msNoSynth_0_b_buffer_ff$EMPTY_N || - msNoSynth_0_b_buffer_enqw$whas) && - tmp0_b_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_msNoSynth_0_b_dropFlit = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; - - // rule RL_msNoSynth_0_b_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue = - msNoSynth_0_b_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_0_b_dropFlit || - msNoSynth_0_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; - - // rule RL_msNoSynth_0_b_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit && - msNoSynth_0_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; - - // rule RL_ifcs_0_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - ifcs_0_noRoute_inner_pendingReq$port1__read && - ifcs_0_noRouteRsp$FULL_N && - proc$master1_wvalid ; - assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; - - // rule __me_check_156 - assign CAN_FIRE___me_check_156 = 1'b1 ; - assign WILL_FIRE___me_check_156 = 1'b1 ; - - // rule __me_check_157 - assign CAN_FIRE___me_check_157 = 1'b1 ; - assign WILL_FIRE___me_check_157 = 1'b1 ; - - // rule __me_check_160 - assign CAN_FIRE___me_check_160 = 1'b1 ; - assign WILL_FIRE___me_check_160 = 1'b1 ; - - // rule RL_merged_0_genFirst - assign CAN_FIRE_RL_merged_0_genFirst = - proc$master1_awvalid && proc$master1_wvalid && - merged_0_doDrop$whas && - merged_0_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; - - // rule RL_msNoSynth_0_aw_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; - - // rule RL_tmp0_aw_forwardReady - assign CAN_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; - - // rule RL_merged_0_genOther - assign CAN_FIRE_RL_merged_0_genOther = - proc$master1_wvalid && merged_0_doDrop$whas && - merged_0_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; - - // rule RL_msNoSynth_0_w_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; - - // rule RL_tmp0_w_forwardReady - assign CAN_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_forwardRsp - assign CAN_FIRE_RL_ifcs_1_forwardRsp = - msNoSynth_1_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_4 && - !ifcs_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_forwardRsp = CAN_FIRE_RL_ifcs_1_forwardRsp ; - - // rule RL_msNoSynth_1_b_forwardFlit - assign CAN_FIRE_RL_msNoSynth_1_b_forwardFlit = - msNoSynth_1_b_buffer_firstValid$Q_OUT && - (msNoSynth_1_b_buffer_ff$EMPTY_N || - msNoSynth_1_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_1_b_forwardFlit = - CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; - - // rule RL_msNoSynth_1_b_dropFlit - assign CAN_FIRE_RL_msNoSynth_1_b_dropFlit = - (msNoSynth_1_b_buffer_ff$EMPTY_N || - msNoSynth_1_b_buffer_enqw$whas) && - debug_module$master_bready ; - assign WILL_FIRE_RL_msNoSynth_1_b_dropFlit = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; - - // rule RL_msNoSynth_1_b_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue = - msNoSynth_1_b_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_1_b_dropFlit || - msNoSynth_1_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; - - // rule RL_msNoSynth_1_b_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit && - msNoSynth_1_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + // rule __me_check_333 + assign CAN_FIRE___me_check_333 = 1'b1 ; + assign WILL_FIRE___me_check_333 = 1'b1 ; // rule RL_ifcs_0_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_firstFlit_1 = - uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && + ifcs_0_rspBack$FULL_N && ifcs_0_routeBack$FULL_N && !ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit_1 = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; // rule RL_ifcs_0_followFlits_1 assign CAN_FIRE_RL_ifcs_0_followFlits_1 = - uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && + ifcs_0_rspBack$FULL_N && ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_followFlits_1 = CAN_FIRE_RL_ifcs_0_followFlits_1 ; - // rule __me_check_170 - assign CAN_FIRE___me_check_170 = 1'b1 ; - assign WILL_FIRE___me_check_170 = 1'b1 ; + // rule __me_check_337 + assign CAN_FIRE___me_check_337 = 1'b1 ; + assign WILL_FIRE___me_check_337 = 1'b1 ; - // rule RL_ssNoSynth_0_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; - assign WILL_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; + // rule RL_ssNoSynth_0_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut && + (!ssNoSynth_0_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; - // rule RL_ug_uncached_mem_shim_master_u_b_doPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = - uncached_mem_shim_bff$FULL_N && - ug_uncached_mem_shim_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + // rule RL_ssNoSynth_0_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; // rule RL_ifcs_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_firstFlit_1 = - plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + ifcs_1_rspBack$FULL_N && ifcs_1_routeBack$FULL_N && !ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; // rule RL_ifcs_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_followFlits_1 = - plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + ifcs_1_rspBack$FULL_N && ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_followFlits_1 ; - // rule __me_check_172 - assign CAN_FIRE___me_check_172 = 1'b1 ; - assign WILL_FIRE___me_check_172 = 1'b1 ; + // rule __me_check_339 + assign CAN_FIRE___me_check_339 = 1'b1 ; + assign WILL_FIRE___me_check_339 = 1'b1 ; - // rule RL_ssNoSynth_1_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_1_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut && + (!ssNoSynth_1_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; - // rule RL_ifcs_2_firstFlit - assign CAN_FIRE_RL_ifcs_2_firstFlit = - proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && - ifcs_2_routeBack$FULL_N && - !ifcs_2_state ; - assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + // rule RL_ssNoSynth_1_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; - // rule RL_ifcs_2_followFlits - assign CAN_FIRE_RL_ifcs_2_followFlits = - proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && - ifcs_2_state ; - assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + // rule RL_sinks_0_warnDoPut + assign CAN_FIRE_RL_sinks_0_warnDoPut = + CAN_FIRE_RL_sink_selected && + ((split_0_flitLeft == 8'd0) ? + !ssNoSynth_0_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_0_warnDoPut = CAN_FIRE_RL_sinks_0_warnDoPut ; - // rule __me_check_174 - assign CAN_FIRE___me_check_174 = 1'b1 ; - assign WILL_FIRE___me_check_174 = 1'b1 ; + // rule RL_sinks_0_doPut + assign CAN_FIRE_RL_sinks_0_doPut = + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 && + CAN_FIRE_RL_sink_selected ; + assign WILL_FIRE_RL_sinks_0_doPut = CAN_FIRE_RL_sinks_0_doPut ; - // rule RL_ssNoSynth_2_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + // rule RL_split_0_putFirst + assign CAN_FIRE_RL_split_0_putFirst = + split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 && + split_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + + // rule RL_ssNoSynth_0_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = + ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + !uncached_mem_shim_awff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_awSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = + uncached_mem_shim_awff$EMPTY_N && + uncached_mem_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; + + // rule RL_slave_vector_0_awSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut = + uncached_mem_shim_awff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = + MUX_split_0_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop || + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop && + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; + + // rule RL_split_0_putOther + assign CAN_FIRE_RL_split_0_putOther = + CAN_FIRE_RL_sinks_0_doPut && + (!split_0_doPut$wget[172] || + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) && + split_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; + + // rule RL_ssNoSynth_0_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = + ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_0_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + !uncached_mem_shim_wff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_wSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = + uncached_mem_shim_wff$EMPTY_N && + uncached_mem_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; + + // rule RL_slave_vector_0_wSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut = + uncached_mem_shim_wff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = + ssNoSynth_0_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop || + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop && + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_warnDoPut = + CAN_FIRE_RL_sink_selected_1 && + ((split_1_flitLeft == 8'd0) ? + !ssNoSynth_1_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_1_warnDoPut = CAN_FIRE_RL_sinks_1_warnDoPut ; + + // rule RL_sinks_1_doPut + assign CAN_FIRE_RL_sinks_1_doPut = + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 && + CAN_FIRE_RL_sink_selected_1 ; + assign WILL_FIRE_RL_sinks_1_doPut = CAN_FIRE_RL_sinks_1_doPut ; + + // rule RL_split_1_putFirst + assign CAN_FIRE_RL_split_1_putFirst = + split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 && + split_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + + // rule RL_ssNoSynth_1_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = + ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_1_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = + MUX_split_1_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop || + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop && + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; + + // rule RL_split_1_putOther + assign CAN_FIRE_RL_split_1_putOther = + CAN_FIRE_RL_sinks_1_doPut && + (!split_1_doPut$wget[172] || + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) && + split_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; + + // rule RL_ssNoSynth_1_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = + ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_1_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_1_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = + ssNoSynth_1_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop || + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop && + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_2_warnDoPut + assign CAN_FIRE_RL_sinks_2_warnDoPut = + CAN_FIRE_RL_sink_selected_2 && + ((split_2_flitLeft == 8'd0) ? + !ssNoSynth_2_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_2_warnDoPut = CAN_FIRE_RL_sinks_2_warnDoPut ; + + // rule RL_sinks_2_doPut + assign CAN_FIRE_RL_sinks_2_doPut = + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 && + CAN_FIRE_RL_sink_selected_2 ; + assign WILL_FIRE_RL_sinks_2_doPut = CAN_FIRE_RL_sinks_2_doPut ; + + // rule RL_split_2_putFirst + assign CAN_FIRE_RL_split_2_putFirst = + split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 && + split_2_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + + // rule RL_ssNoSynth_2_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = + ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = + MUX_split_2_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop || + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop && + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; + + // rule RL_split_2_putOther + assign CAN_FIRE_RL_split_2_putOther = + CAN_FIRE_RL_sinks_2_doPut && + (!split_2_doPut$wget[172] || + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) && + split_2_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; + + // rule RL_ssNoSynth_2_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = + ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_2_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = + ssNoSynth_2_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop || + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop && + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_0_warnDoPut + assign CAN_FIRE_RL_sinks_1_0_warnDoPut = + CAN_FIRE_RL_sink_selected_3 && + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_0_warnDoPut = CAN_FIRE_RL_sinks_1_0_warnDoPut ; + + // rule RL_sinks_1_0_doPut + assign CAN_FIRE_RL_sinks_1_0_doPut = + msNoSynth_0_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_3 ; + assign WILL_FIRE_RL_sinks_1_0_doPut = CAN_FIRE_RL_sinks_1_0_doPut ; + + // rule RL_ifcs_0_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = + ifcs_0_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_0_doPut && + msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_0_doPut ; + + // rule RL_ifcs_0_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + ifcs_0_noRoute_inner_pendingReq$port1__read && + ifcs_0_noRouteRsp$FULL_N && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + + // rule __me_check_323 + assign CAN_FIRE___me_check_323 = 1'b1 ; + assign WILL_FIRE___me_check_323 = 1'b1 ; + + // rule __me_check_324 + assign CAN_FIRE___me_check_324 = 1'b1 ; + assign WILL_FIRE___me_check_324 = 1'b1 ; + + // rule __me_check_327 + assign CAN_FIRE___me_check_327 = 1'b1 ; + assign WILL_FIRE___me_check_327 = 1'b1 ; + + // rule RL_merged_0_awFlit + assign CAN_FIRE_RL_merged_0_awFlit = + msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut) && + merged_0_awff$FULL_N ; + assign WILL_FIRE_RL_merged_0_awFlit = CAN_FIRE_RL_merged_0_awFlit ; + + // rule RL_msNoSynth_0_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_0_awFlit || + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_0_awFlit && + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; + + // rule RL_merged_0_wFlit + assign CAN_FIRE_RL_merged_0_wFlit = + msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut) && + merged_0_wff$FULL_N ; + assign WILL_FIRE_RL_merged_0_wFlit = CAN_FIRE_RL_merged_0_wFlit ; + + // rule RL_msNoSynth_0_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_0_wFlit || + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_0_wFlit && + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; + + // rule RL_merged_0_genFirst + assign CAN_FIRE_RL_merged_0_genFirst = + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && + merged_0_doDrop$whas && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; + + // rule RL_merged_0_genOther + assign CAN_FIRE_RL_merged_0_genOther = + merged_0_wff$EMPTY_N && merged_0_doDrop$whas && + merged_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; + + // rule RL_ifcs_0_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_0_snk_warnDoPut = + ifcs_0_snk_putWire$whas && + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_snk_warnDoPut = + CAN_FIRE_RL_ifcs_0_snk_warnDoPut ; + + // rule RL_ifcs_0_snk_doPut + assign CAN_FIRE_RL_ifcs_0_snk_doPut = + msNoSynth_0_bNoSynth_buffer_ff$FULL_N && + ifcs_0_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_0_snk_doPut = CAN_FIRE_RL_ifcs_0_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = + msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_0_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek ; + + // rule RL_msNoSynth_0_bNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; + + // rule RL_proc_uncached_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + !proc$master1_b_canPut ; + assign WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = + CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut ; + + // rule RL_proc_uncached_bSynth_snk_doPut + assign CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut = + proc$RDY_master1_b_put && + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; + assign WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut = + CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; + + // rule RL_msNoSynth_0_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_0_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop || + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop && + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_warnDoPut = + CAN_FIRE_RL_sink_selected_4 && + !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_warnDoPut = CAN_FIRE_RL_sinks_1_1_warnDoPut ; + + // rule RL_sinks_1_1_doPut + assign CAN_FIRE_RL_sinks_1_1_doPut = + msNoSynth_1_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_4 ; + assign WILL_FIRE_RL_sinks_1_1_doPut = CAN_FIRE_RL_sinks_1_1_doPut ; + + // rule RL_ifcs_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = + ifcs_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_doPut && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_doPut ; + + // rule RL_ifcs_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_noRoute_inner_pendingReq$port1__read && + ifcs_1_noRouteRsp$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + + // rule __me_check_331 + assign CAN_FIRE___me_check_331 = 1'b1 ; + assign WILL_FIRE___me_check_331 = 1'b1 ; + + // rule __me_check_332 + assign CAN_FIRE___me_check_332 = 1'b1 ; + assign WILL_FIRE___me_check_332 = 1'b1 ; + + // rule __me_check_335 + assign CAN_FIRE___me_check_335 = 1'b1 ; + assign WILL_FIRE___me_check_335 = 1'b1 ; + + // rule RL_merged_1_genFirst + assign CAN_FIRE_RL_merged_1_genFirst = + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && + merged_1_doDrop$whas && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; + + // rule RL_merged_1_genOther + assign CAN_FIRE_RL_merged_1_genOther = + merged_1_wff$EMPTY_N && merged_1_doDrop$whas && + merged_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; + + // rule RL_ifcs_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_1_snk_warnDoPut = + ifcs_1_snk_putWire$whas && + !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_1_snk_warnDoPut ; + + // rule RL_ifcs_1_snk_doPut + assign CAN_FIRE_RL_ifcs_1_snk_doPut = + msNoSynth_1_bNoSynth_buffer_ff$FULL_N && + ifcs_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_1_snk_doPut = CAN_FIRE_RL_ifcs_1_snk_doPut ; + + // rule RL_msNoSynth_1_bNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = + msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek ; + + // rule RL_msNoSynth_1_bNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; + + // rule RL_msNoSynth_1_bNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; + + // rule RL_msNoSynth_1_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop || + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop && + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; // rule RL_ifcs_0_1_firstFlit assign CAN_FIRE_RL_ifcs_0_1_firstFlit = - proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_innerReq$FULL_N && ifcs_0_1_innerRoute$FULL_N && ifcs_0_1_state == 2'd0 && - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 == + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit = CAN_FIRE_RL_ifcs_0_1_firstFlit ; // rule RL_ifcs_0_1_followFlits assign CAN_FIRE_RL_ifcs_0_1_followFlits = - proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && - ifcs_0_1_state == 2'd1 ; + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_state == 2'd1 && + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ifcs_0_1_followFlits = CAN_FIRE_RL_ifcs_0_1_followFlits ; // rule RL_ifcs_0_1_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit = - ifcs_0_1_noRoute_flitCount == 9'd0 && proc$master1_arvalid && + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_noRoute_flitCount == 9'd0 && ifcs_0_1_state == 2'd0 && - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 != + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ; // rule RL_ifcs_0_1_drainFlits assign CAN_FIRE_RL_ifcs_0_1_drainFlits = - proc$master1_arvalid && ifcs_0_1_state == 2'd2 ; + (msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) && + ifcs_0_1_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_1_drainFlits = CAN_FIRE_RL_ifcs_0_1_drainFlits ; - // rule __me_check_205 - assign CAN_FIRE___me_check_205 = 1'b1 ; - assign WILL_FIRE___me_check_205 = 1'b1 ; - - // rule RL_ifcs_0_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = - msNoSynth_0_r_buffer_ff$FULL_N && ifcs_0_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; - - // rule RL_checkSinkReady_8 - assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; - - // rule RL_ifcs_1_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = - msNoSynth_1_r_buffer_ff$FULL_N && ifcs_1_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; - - // rule RL_checkSinkReady_9 - assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; - - // rule RL_craftReq_7 - assign CAN_FIRE_RL_craftReq_7 = - ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; - - // rule RL_craftReq_8 - assign CAN_FIRE_RL_craftReq_8 = - ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; - - // rule RL_craftReq_9 - assign CAN_FIRE_RL_craftReq_9 = - ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; - - // rule RL_arbitrate_3 - assign CAN_FIRE_RL_arbitrate_3 = - reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302 && - !state_1_1_1 ; - assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; - - // rule RL_source_selected_7 - assign CAN_FIRE_RL_source_selected_7 = - (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_0$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; - - // rule RL_burst_7 - assign CAN_FIRE_RL_burst_7 = - ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400 ; - assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; - - // rule RL_source_selected_8 - assign CAN_FIRE_RL_source_selected_8 = - (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_1_1$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; - - // rule RL_burst_8 - assign CAN_FIRE_RL_burst_8 = - ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436 ; - assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; - - // rule __me_check_244 - assign CAN_FIRE___me_check_244 = 1'b1 ; - assign WILL_FIRE___me_check_244 = 1'b1 ; - - // rule RL_source_selected_9 - assign CAN_FIRE_RL_source_selected_9 = - (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_2$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; - - // rule RL_burst_9 - assign CAN_FIRE_RL_burst_9 = - ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472 ; - assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; - - // rule __me_check_242 - assign CAN_FIRE___me_check_242 = 1'b1 ; - assign WILL_FIRE___me_check_242 = 1'b1 ; - - // rule __me_check_246 - assign CAN_FIRE___me_check_246 = 1'b1 ; - assign WILL_FIRE___me_check_246 = 1'b1 ; - - // rule RL_sink_selected_8 - assign CAN_FIRE_RL_sink_selected_8 = - !CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && - flitToSink_1_1_0$whas ; - assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; - - // rule RL_sink_selected_9 - assign CAN_FIRE_RL_sink_selected_9 = - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && - flitToSink_1_1_1_1$whas ; - assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; - - // rule __me_check_248 - assign CAN_FIRE___me_check_248 = 1'b1 ; - assign WILL_FIRE___me_check_248 = 1'b1 ; - - // rule RL_ifcs_0_1_forwardRsp - assign CAN_FIRE_RL_ifcs_0_1_forwardRsp = - msNoSynth_0_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_8 && - !ifcs_0_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_1_forwardRsp = CAN_FIRE_RL_ifcs_0_1_forwardRsp ; - - // rule RL_msNoSynth_0_r_forwardFlit - assign CAN_FIRE_RL_msNoSynth_0_r_forwardFlit = - !tmp0_r_buffer_ff$FULL_N || - msNoSynth_0_r_buffer_firstValid$Q_OUT && - (msNoSynth_0_r_buffer_ff$EMPTY_N || - msNoSynth_0_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_0_r_forwardFlit = - CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; - - // rule RL_tmp0_r_forwardFlit - assign CAN_FIRE_RL_tmp0_r_forwardFlit = - tmp0_r_buffer_firstValid$Q_OUT && - (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_tmp0_r_forwardFlit = CAN_FIRE_RL_tmp0_r_forwardFlit ; - - // rule RL_tmp0_r_dropFlit - assign CAN_FIRE_RL_tmp0_r_dropFlit = - (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) && - proc$master1_rready ; - assign WILL_FIRE_RL_tmp0_r_dropFlit = CAN_FIRE_RL_tmp0_r_dropFlit ; - - // rule RL_tmp0_r_buffer_enqueue - assign CAN_FIRE_RL_tmp0_r_buffer_enqueue = - tmp0_r_buffer_enqw$whas && - (!CAN_FIRE_RL_tmp0_r_dropFlit || tmp0_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp0_r_buffer_enqueue = - CAN_FIRE_RL_tmp0_r_buffer_enqueue ; - - // rule RL_tmp0_r_buffer_dequeue - assign CAN_FIRE_RL_tmp0_r_buffer_dequeue = - CAN_FIRE_RL_tmp0_r_dropFlit && tmp0_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp0_r_buffer_dequeue = - CAN_FIRE_RL_tmp0_r_buffer_dequeue ; - - // rule RL_msNoSynth_0_r_dropFlit - assign CAN_FIRE_RL_msNoSynth_0_r_dropFlit = - (msNoSynth_0_r_buffer_ff$EMPTY_N || - msNoSynth_0_r_buffer_enqw$whas) && - tmp0_r_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_msNoSynth_0_r_dropFlit = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; - - // rule RL_msNoSynth_0_r_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue = - msNoSynth_0_r_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_0_r_dropFlit || - msNoSynth_0_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; - - // rule RL_msNoSynth_0_r_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit && - msNoSynth_0_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; - - // rule RL_ifcs_0_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = - x_port1__read__h72781 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && - (x_port1__read__h72781 != 9'd1 || proc$master1_arvalid) ; - assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; - - // rule __me_check_203 - assign CAN_FIRE___me_check_203 = 1'b1 ; - assign WILL_FIRE___me_check_203 = 1'b1 ; - - // rule __me_check_204 - assign CAN_FIRE___me_check_204 = 1'b1 ; - assign WILL_FIRE___me_check_204 = 1'b1 ; - - // rule __me_check_207 - assign CAN_FIRE___me_check_207 = 1'b1 ; - assign WILL_FIRE___me_check_207 = 1'b1 ; - - // rule RL_msNoSynth_0_ar_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; - - // rule RL_tmp0_ar_forwardReady - assign CAN_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_1_forwardRsp - assign CAN_FIRE_RL_ifcs_1_1_forwardRsp = - msNoSynth_1_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_9 && - !ifcs_1_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_1_forwardRsp = CAN_FIRE_RL_ifcs_1_1_forwardRsp ; - - // rule RL_msNoSynth_1_r_forwardFlit - assign CAN_FIRE_RL_msNoSynth_1_r_forwardFlit = - msNoSynth_1_r_buffer_firstValid$Q_OUT && - (msNoSynth_1_r_buffer_ff$EMPTY_N || - msNoSynth_1_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_1_r_forwardFlit = - CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; - - // rule RL_msNoSynth_1_r_dropFlit - assign CAN_FIRE_RL_msNoSynth_1_r_dropFlit = - (msNoSynth_1_r_buffer_ff$EMPTY_N || - msNoSynth_1_r_buffer_enqw$whas) && - debug_module$master_rready ; - assign WILL_FIRE_RL_msNoSynth_1_r_dropFlit = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; - - // rule RL_msNoSynth_1_r_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue = - msNoSynth_1_r_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_1_r_dropFlit || - msNoSynth_1_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; - - // rule RL_msNoSynth_1_r_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit && - msNoSynth_1_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; - - // rule RL_ifcs_1_firstFlit - assign CAN_FIRE_RL_ifcs_1_firstFlit = - debug_module$master_wvalid && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_innerReq$FULL_N && - ifcs_1_innerRoute$FULL_N && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - ifcs_1_state == 2'd0 && - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 == - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; - - // rule RL_ifcs_1_followFlits - assign CAN_FIRE_RL_ifcs_1_followFlits = - debug_module$master_wvalid && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_innerReq$FULL_N && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - ifcs_1_state == 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; - - // rule RL_ifcs_1_nonRoutableFlit - assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350 && - ifcs_1_state == 2'd0 && - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 != - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = - CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; - - // rule RL_ifcs_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_noRoute_inner_pendingReq$port1__read && - ifcs_1_noRouteRsp$FULL_N && - debug_module$master_wvalid ; - assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; - - // rule RL_ifcs_1_drainFlits - assign CAN_FIRE_RL_ifcs_1_drainFlits = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - debug_module$master_wvalid && - ifcs_1_state == 2'd2 ; - assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; - - // rule __me_check_163 - assign CAN_FIRE___me_check_163 = 1'b1 ; - assign WILL_FIRE___me_check_163 = 1'b1 ; - - // rule __me_check_164 - assign CAN_FIRE___me_check_164 = 1'b1 ; - assign WILL_FIRE___me_check_164 = 1'b1 ; - - // rule __me_check_165 - assign CAN_FIRE___me_check_165 = 1'b1 ; - assign WILL_FIRE___me_check_165 = 1'b1 ; - - // rule __me_check_167 - assign CAN_FIRE___me_check_167 = 1'b1 ; - assign WILL_FIRE___me_check_167 = 1'b1 ; - - // rule RL_merged_1_genFirst - assign CAN_FIRE_RL_merged_1_genFirst = - debug_module$master_awvalid && debug_module$master_wvalid && - merged_1_doDrop$whas && - merged_1_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; - - // rule RL_msNoSynth_1_aw_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; - - // rule RL_merged_1_genOther - assign CAN_FIRE_RL_merged_1_genOther = - debug_module$master_wvalid && merged_1_doDrop$whas && - merged_1_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; - - // rule RL_msNoSynth_1_w_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_1_firstFlit - assign CAN_FIRE_RL_ifcs_1_1_firstFlit = - debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && - ifcs_1_1_innerRoute$FULL_N && - ifcs_1_1_state == 2'd0 && - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 == - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; - - // rule RL_ifcs_1_1_followFlits - assign CAN_FIRE_RL_ifcs_1_1_followFlits = - debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && - ifcs_1_1_state == 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_followFlits = - CAN_FIRE_RL_ifcs_1_1_followFlits ; - - // rule RL_ifcs_1_1_nonRoutableFlit - assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = - ifcs_1_1_noRoute_flitCount == 9'd0 && - debug_module$master_arvalid && - ifcs_1_1_state == 2'd0 && - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 != - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = - CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; - - // rule RL_ifcs_1_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = - x_port1__read__h75154 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && - (x_port1__read__h75154 != 9'd1 || debug_module$master_arvalid) ; - assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; - - // rule RL_ifcs_1_1_drainFlits - assign CAN_FIRE_RL_ifcs_1_1_drainFlits = - debug_module$master_arvalid && ifcs_1_1_state == 2'd2 ; - assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; - - // rule __me_check_210 - assign CAN_FIRE___me_check_210 = 1'b1 ; - assign WILL_FIRE___me_check_210 = 1'b1 ; - - // rule __me_check_211 - assign CAN_FIRE___me_check_211 = 1'b1 ; - assign WILL_FIRE___me_check_211 = 1'b1 ; - - // rule __me_check_212 - assign CAN_FIRE___me_check_212 = 1'b1 ; - assign WILL_FIRE___me_check_212 = 1'b1 ; - - // rule __me_check_214 - assign CAN_FIRE___me_check_214 = 1'b1 ; - assign WILL_FIRE___me_check_214 = 1'b1 ; - - // rule RL_msNoSynth_1_ar_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + // rule __me_check_384 + assign CAN_FIRE___me_check_384 = 1'b1 ; + assign WILL_FIRE___me_check_384 = 1'b1 ; // rule RL_ifcs_0_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_1_firstFlit_1 = - uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && + ifcs_0_1_rspBack$FULL_N && ifcs_0_1_routeBack$FULL_N && !ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit_1 = @@ -6141,29 +7599,37 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ifcs_0_1_followFlits_1 assign CAN_FIRE_RL_ifcs_0_1_followFlits_1 = - uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && + ifcs_0_1_rspBack$FULL_N && ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_followFlits_1 = CAN_FIRE_RL_ifcs_0_1_followFlits_1 ; - // rule __me_check_217 - assign CAN_FIRE___me_check_217 = 1'b1 ; - assign WILL_FIRE___me_check_217 = 1'b1 ; + // rule __me_check_396 + assign CAN_FIRE___me_check_396 = 1'b1 ; + assign WILL_FIRE___me_check_396 = 1'b1 ; - // rule RL_ssNoSynth_0_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; - assign WILL_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; + // rule RL_ssNoSynth_0_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut && + (!ssNoSynth_0_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; - // rule RL_ug_uncached_mem_shim_master_u_r_doPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = - uncached_mem_shim_rff$FULL_N && - ug_uncached_mem_shim_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + // rule RL_ssNoSynth_0_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; // rule RL_ifcs_1_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_1_firstFlit_1 = - plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + ifcs_1_1_rspBack$FULL_N && ifcs_1_1_routeBack$FULL_N && !ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_firstFlit_1 = @@ -6171,18 +7637,124 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ifcs_1_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_1_followFlits_1 = - plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + ifcs_1_1_rspBack$FULL_N && ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_1_followFlits_1 ; - // rule __me_check_219 - assign CAN_FIRE___me_check_219 = 1'b1 ; - assign WILL_FIRE___me_check_219 = 1'b1 ; + // rule __me_check_398 + assign CAN_FIRE___me_check_398 = 1'b1 ; + assign WILL_FIRE___me_check_398 = 1'b1 ; - // rule RL_ssNoSynth_1_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_1_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut && + (!ssNoSynth_1_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_0_warnDoPut_1 + assign CAN_FIRE_RL_sinks_1_0_warnDoPut_1 = + CAN_FIRE_RL_sink_selected_5 && + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_0_warnDoPut_1 = + CAN_FIRE_RL_sinks_1_0_warnDoPut_1 ; + + // rule RL_sinks_1_0_doPut_1 + assign CAN_FIRE_RL_sinks_1_0_doPut_1 = + ssNoSynth_0_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_5 ; + assign WILL_FIRE_RL_sinks_1_0_doPut_1 = CAN_FIRE_RL_sinks_1_0_doPut_1 ; + + // rule RL_ssNoSynth_0_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = + ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_0_doPut_1) ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + !uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_arSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = + uncached_mem_shim_arff$EMPTY_N && + uncached_mem_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; + + // rule RL_slave_vector_0_arSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut = + uncached_mem_shim_arff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_0_doPut_1 && + (!CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop || + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop && + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_warnDoPut_1 + assign CAN_FIRE_RL_sinks_1_1_warnDoPut_1 = + CAN_FIRE_RL_sink_selected_6 && + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_warnDoPut_1 = + CAN_FIRE_RL_sinks_1_1_warnDoPut_1 ; + + // rule RL_sinks_1_1_doPut_1 + assign CAN_FIRE_RL_sinks_1_1_doPut_1 = + ssNoSynth_1_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_6 ; + assign WILL_FIRE_RL_sinks_1_1_doPut_1 = CAN_FIRE_RL_sinks_1_1_doPut_1 ; + + // rule RL_ssNoSynth_1_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = + ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_1_doPut_1) ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = @@ -6198,27 +7770,752 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; + // rule RL_ssNoSynth_1_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_1_doPut_1 && + (!CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop || + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop && + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_2_warnDoPut + assign CAN_FIRE_RL_sinks_1_2_warnDoPut = + CAN_FIRE_RL_sink_selected_7 && + !ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_2_warnDoPut = CAN_FIRE_RL_sinks_1_2_warnDoPut ; + + // rule RL_sinks_1_2_doPut + assign CAN_FIRE_RL_sinks_1_2_doPut = + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_7 ; + assign WILL_FIRE_RL_sinks_1_2_doPut = CAN_FIRE_RL_sinks_1_2_doPut ; + + // rule RL_ssNoSynth_2_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = + ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_2_doPut) ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = + proc$debug_module_mem_server_bvalid && + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_2_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_2_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit && + !ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_2_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_2_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_2_doPut && + (!CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop || + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop && + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; + + // rule RL_ssNoSynth_2_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = + proc$debug_module_mem_server_rvalid && + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_2_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_2_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit && + !ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_2_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut ; + + // rule RL_ifcs_2_firstFlit + assign CAN_FIRE_RL_ifcs_2_firstFlit = + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && + ifcs_2_rspBack$FULL_N && + ifcs_2_routeBack$FULL_N && + !ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + + // rule RL_ifcs_2_followFlits + assign CAN_FIRE_RL_ifcs_2_followFlits = + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && + ifcs_2_rspBack$FULL_N && + ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + + // rule __me_check_341 + assign CAN_FIRE___me_check_341 = 1'b1 ; + assign WILL_FIRE___me_check_341 = 1'b1 ; + + // rule RL_ssNoSynth_2_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut && + (!ssNoSynth_2_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; + // rule RL_ifcs_2_1_firstFlit assign CAN_FIRE_RL_ifcs_2_1_firstFlit = - proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && + ifcs_2_1_rspBack$FULL_N && ifcs_2_1_routeBack$FULL_N && !ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_firstFlit = CAN_FIRE_RL_ifcs_2_1_firstFlit ; // rule RL_ifcs_2_1_followFlits assign CAN_FIRE_RL_ifcs_2_1_followFlits = - proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && + ifcs_2_1_rspBack$FULL_N && ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_followFlits = CAN_FIRE_RL_ifcs_2_1_followFlits ; - // rule __me_check_221 - assign CAN_FIRE___me_check_221 = 1'b1 ; - assign WILL_FIRE___me_check_221 = 1'b1 ; + // rule __me_check_400 + assign CAN_FIRE___me_check_400 = 1'b1 ; + assign WILL_FIRE___me_check_400 = 1'b1 ; - // rule RL_ssNoSynth_2_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_2_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut && + (!ssNoSynth_2_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_0_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_0_warnDoPut = + CAN_FIRE_RL_sink_selected_8 && + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_0_warnDoPut = + CAN_FIRE_RL_sinks_1_1_0_warnDoPut ; + + // rule RL_sinks_1_1_0_doPut + assign CAN_FIRE_RL_sinks_1_1_0_doPut = + msNoSynth_0_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_8 ; + assign WILL_FIRE_RL_sinks_1_1_0_doPut = CAN_FIRE_RL_sinks_1_1_0_doPut ; + + // rule RL_ifcs_0_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + ifcs_0_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_0_doPut && + msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_0_doPut ; + + // rule RL_ifcs_0_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + x__h95023 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && + (x__h95023 != 9'd1 || msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + + // rule __me_check_382 + assign CAN_FIRE___me_check_382 = 1'b1 ; + assign WILL_FIRE___me_check_382 = 1'b1 ; + + // rule __me_check_383 + assign CAN_FIRE___me_check_383 = 1'b1 ; + assign WILL_FIRE___me_check_383 = 1'b1 ; + + // rule __me_check_386 + assign CAN_FIRE___me_check_386 = 1'b1 ; + assign WILL_FIRE___me_check_386 = 1'b1 ; + + // rule RL_msNoSynth_0_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut && + (!msNoSynth_0_arNoSynth_buffer_dequeueing$whas || + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = + msNoSynth_0_arNoSynth_buffer_dequeueing$whas && + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; + + // rule RL_ifcs_0_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut = + ifcs_0_1_snk_putWire$whas && + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut ; + + // rule RL_ifcs_0_1_snk_doPut + assign CAN_FIRE_RL_ifcs_0_1_snk_doPut = + msNoSynth_0_rNoSynth_buffer_ff$FULL_N && + ifcs_0_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_0_1_snk_doPut = CAN_FIRE_RL_ifcs_0_1_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = + msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_0_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek ; + + // rule RL_msNoSynth_0_rNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; + + // rule RL_proc_uncached_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + !proc$master1_r_canPut ; + assign WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = + CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut ; + + // rule RL_proc_uncached_rSynth_snk_doPut + assign CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut = + proc$RDY_master1_r_put && + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; + assign WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut = + CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; + + // rule RL_msNoSynth_0_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_0_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop || + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop && + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_1_warnDoPut = + CAN_FIRE_RL_sink_selected_9 && + !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_1_warnDoPut = + CAN_FIRE_RL_sinks_1_1_1_warnDoPut ; + + // rule RL_sinks_1_1_1_doPut + assign CAN_FIRE_RL_sinks_1_1_1_doPut = + msNoSynth_1_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_9 ; + assign WILL_FIRE_RL_sinks_1_1_1_doPut = CAN_FIRE_RL_sinks_1_1_1_doPut ; + + // rule RL_ifcs_1_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + ifcs_1_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_1_doPut && + msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_1_doPut ; + + // rule RL_ifcs_1_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut = + ifcs_1_1_snk_putWire$whas && + !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut ; + + // rule RL_ifcs_1_1_snk_doPut + assign CAN_FIRE_RL_ifcs_1_1_snk_doPut = + msNoSynth_1_rNoSynth_buffer_ff$FULL_N && + ifcs_1_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_1_1_snk_doPut = CAN_FIRE_RL_ifcs_1_1_snk_doPut ; + + // rule RL_msNoSynth_1_rNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = + msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_1_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek ; + + // rule RL_msNoSynth_1_rNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; + + // rule RL_msNoSynth_1_awNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = + debug_module$master_awvalid && + msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_awNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit && + !msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_awNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = + msNoSynth_1_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_wNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = + debug_module$master_wvalid && + msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_wNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit && + !msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_wNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = + msNoSynth_1_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_arNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = + debug_module$master_arvalid && + msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_arNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit && + !msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_arNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = + msNoSynth_1_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_rNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; + + // rule RL_msNoSynth_1_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_1_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop || + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop && + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; + + // rule RL_merged_1_awFlit + assign CAN_FIRE_RL_merged_1_awFlit = + msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut) && + merged_1_awff$FULL_N ; + assign WILL_FIRE_RL_merged_1_awFlit = CAN_FIRE_RL_merged_1_awFlit ; + + // rule RL_msNoSynth_1_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_1_awFlit || + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_1_awFlit && + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; + + // rule RL_merged_1_wFlit + assign CAN_FIRE_RL_merged_1_wFlit = + msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut) && + merged_1_wff$FULL_N ; + assign WILL_FIRE_RL_merged_1_wFlit = CAN_FIRE_RL_merged_1_wFlit ; + + // rule RL_msNoSynth_1_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_1_wFlit || + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_1_wFlit && + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; + + // rule RL_ifcs_1_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_1_firstFlit = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_innerRoute$FULL_N && + ifcs_1_1_state == 2'd0 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + + // rule RL_ifcs_1_1_followFlits + assign CAN_FIRE_RL_ifcs_1_1_followFlits = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_state == 2'd1 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits = + CAN_FIRE_RL_ifcs_1_1_followFlits ; + + // rule RL_ifcs_1_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_noRoute_flitCount == 9'd0 && + ifcs_1_1_state == 2'd0 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; + + // rule RL_ifcs_1_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + x__h97622 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && + (x__h97622 != 9'd1 || msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_1_drainFlits = + (msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) && + ifcs_1_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; + + // rule __me_check_390 + assign CAN_FIRE___me_check_390 = 1'b1 ; + assign WILL_FIRE___me_check_390 = 1'b1 ; + + // rule __me_check_391 + assign CAN_FIRE___me_check_391 = 1'b1 ; + assign WILL_FIRE___me_check_391 = 1'b1 ; + + // rule __me_check_392 + assign CAN_FIRE___me_check_392 = 1'b1 ; + assign WILL_FIRE___me_check_392 = 1'b1 ; + + // rule __me_check_394 + assign CAN_FIRE___me_check_394 = 1'b1 ; + assign WILL_FIRE___me_check_394 = 1'b1 ; + + // rule RL_msNoSynth_1_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut && + (!msNoSynth_1_arNoSynth_buffer_dequeueing$whas || + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = + msNoSynth_1_arNoSynth_buffer_dequeueing$whas && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; + + // rule RL_cached_mem_master_awSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = + cached_mem_master_awSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_awSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop = + cached_mem_master_awSynth_src_dropWire$whas && + tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop && + !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; + + // rule RL_cached_mem_master_wSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = + cached_mem_master_wSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_wSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop = + cached_mem_master_wSynth_src_dropWire$whas && + tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop && + !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; + + // rule RL_cached_mem_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && + tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut ; + + // rule RL_cached_mem_master_bSynth_snk_doPut + assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut = + cpu_imem_master_bvalid && + !tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; + + // rule RL_tagController_tmp_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && + tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_b_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + !tagController_tmp_shimMaster_bff_rv[8] && + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; + + // rule RL_cached_mem_master_arSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = + cached_mem_master_arSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_arSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop = + cached_mem_master_arSynth_src_dropWire$whas && + tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop && + !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; + + // rule RL_cached_mem_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && + tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut ; + + // rule RL_cached_mem_master_rSynth_snk_doPut + assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut = + cpu_imem_master_rvalid && + !tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; + + // rule RL_tagController_tmp_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && + tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_r_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + !tagController_tmp_shimMaster_rff_rv[73] && + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; + + // rule RL_tagController_tmp_passMemoryResponseWrite + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + tagController_tmp_shimMaster_bff_rv$port1__read[8] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && + !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_tagController_tmp_passMemoryResponseRead + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = + tagController_tmp_shimMaster_rff_rv$port1__read[73] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_tagController_tmp_propagateReset + assign CAN_FIRE_RL_tagController_tmp_propagateReset = + !tagController_tmp_reset_done ; + assign WILL_FIRE_RL_tagController_tmp_propagateReset = + CAN_FIRE_RL_tagController_tmp_propagateReset ; // inputs to muxes for submodule ports assign MUX_activeSource_0$write_1__SEL_1 = @@ -6325,31 +8622,37 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_0_innerRoute$D_OUT[2] ; assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && - uncached_mem_shim_rff$D_OUT[1] ; + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_0_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits ; assign MUX_ifcs_0_state$write_1__SEL_1 = - MUX_ifcs_0_state$write_1__PSEL_1 && proc$master1_wlast ; + MUX_ifcs_0_state$write_1__PSEL_1 && + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; assign MUX_ifcs_0_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast ; + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_0_state$write_1__SEL_3 = - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast ; + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_1_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits ; assign MUX_ifcs_1_state$write_1__SEL_1 = - MUX_ifcs_1_state$write_1__PSEL_1 && debug_module$master_wlast ; + MUX_ifcs_1_state$write_1__PSEL_1 && + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; assign MUX_ifcs_1_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast ; + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_1_state$write_1__SEL_3 = WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - !debug_module$master_wlast ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_2_1_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_2_1_followFlits && - proc$debug_module_mem_server_rlast ; + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_proc$start_1__SEL_1 = WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 ; @@ -6377,41 +8680,19 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] ; assign MUX_activeSource_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign MUX_activeSource_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign MUX_activeSource_1_1_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign MUX_activeSource_1_1_1_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign MUX_activeSource_1_1_2$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 ; - assign MUX_merged_0_flitLeft$write_1__VAL_1 = merged_0_flitLeft - 8'd1 ; - assign MUX_merged_1_flitLeft$write_1__VAL_1 = merged_1_flitLeft - 8'd1 ; - always@(MUX_flitToSink_1_0$wset_1__SEL_1 or - MUX_flitToSink_1_0$wset_1__SEL_4 or - ifcs_0_rspBack$D_OUT or - MUX_flitToSink_1_0$wset_1__SEL_2 or - MUX_flitToSink_1_0$wset_1__SEL_5 or - ifcs_1_rspBack$D_OUT or - MUX_flitToSink_1_0$wset_1__SEL_3 or - MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) - begin - case (1'b1) // synopsys parallel_case - MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; - MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; - MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; - default: MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = - 6'b101010 /* unspecified value */ ; - endcase - end + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; always@(MUX_flitToSink_1_1_0$wset_1__SEL_1 or MUX_flitToSink_1_1_0$wset_1__SEL_4 or ifcs_0_1_rspBack$D_OUT or @@ -6424,37 +8705,34 @@ module mkCoreW(RST_N_dm_power_on_reset, case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_0$wset_1__SEL_1 || MUX_flitToSink_1_1_0$wset_1__SEL_4: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_0_1_rspBack$D_OUT; + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_2 || MUX_flitToSink_1_1_0$wset_1__SEL_5: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_1_1_rspBack$D_OUT; + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_3 || MUX_flitToSink_1_1_0$wset_1__SEL_6: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_2_1_rspBack$D_OUT; - default: MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; + default: MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(MUX_flitToSink_1_1$wset_1__SEL_1 or - MUX_flitToSink_1_1$wset_1__SEL_4 or + always@(MUX_flitToSink_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_0$wset_1__SEL_4 or ifcs_0_rspBack$D_OUT or - MUX_flitToSink_1_1$wset_1__SEL_2 or - MUX_flitToSink_1_1$wset_1__SEL_5 or + MUX_flitToSink_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_0$wset_1__SEL_5 or ifcs_1_rspBack$D_OUT or - MUX_flitToSink_1_1$wset_1__SEL_3 or - MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + MUX_flitToSink_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) begin case (1'b1) // synopsys parallel_case - MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; - MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; - MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; - default: MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = + MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = 6'b101010 /* unspecified value */ ; endcase end @@ -6470,27 +8748,46 @@ module mkCoreW(RST_N_dm_power_on_reset, case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1_1$wset_1__SEL_4: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_0_1_rspBack$D_OUT; + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1_1_1$wset_1__SEL_5: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_1_1_rspBack$D_OUT; + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1_1_1$wset_1__SEL_6: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_2_1_rspBack$D_OUT; - default: MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; + default: MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + always@(MUX_flitToSink_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = + 6'b101010 /* unspecified value */ ; + endcase + end + assign MUX_merged_0_flitLeft$write_1__VAL_2 = merged_0_flitLeft - 8'd1 ; + assign MUX_merged_1_flitLeft$write_1__VAL_2 = merged_1_flitLeft - 8'd1 ; assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = rg_hart0_reset_delay - 8'd1 ; assign MUX_split_0_flitLeft$write_1__VAL_1 = split_0_flitLeft - 8'd1 ; assign MUX_split_1_flitLeft$write_1__VAL_1 = split_1_flitLeft - 8'd1 ; assign MUX_split_2_flitLeft$write_1__VAL_1 = split_2_flitLeft - 8'd1 ; assign MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1 = - { tmp__h8366[39:3], + { tmp__h8169[39:3], 4'd0, tagController_tmp_awreqff$D_OUT[97:93], 3'd1, @@ -6521,48 +8818,51 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_rff_rv$port1__read[67:3] } ; // inlined wires - assign tmp0_aw_dwReady$whas = - proc$master1_awvalid && CAN_FIRE_RL_merged_0_genFirst ; - assign tmp0_w_dwReady$whas = - proc$master1_wvalid && msNoSynth_0_w_dwReady$whas ; - assign tmp0_b_buffer_enqw$wget = - msNoSynth_0_b_buffer_ff$EMPTY_N ? - msNoSynth_0_b_buffer_ff$D_OUT : - msNoSynth_0_b_buffer_enqw$wget ; - assign tmp0_b_buffer_enqw$whas = - WILL_FIRE_RL_msNoSynth_0_b_forwardFlit && - tmp0_b_buffer_ff$FULL_N ; - assign tmp0_ar_dwReady$whas = - proc$master1_arvalid && msNoSynth_0_ar_dwReady$whas ; - assign tmp0_r_buffer_enqw$wget = - { x_rid__h25044, - x_rdata__h25045, - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[3:2] : - msNoSynth_0_r_buffer_enqw$wget[3:2], - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[1] : - msNoSynth_0_r_buffer_enqw$wget[1], - 1'd0 } ; - assign tmp0_r_buffer_enqw$whas = - WILL_FIRE_RL_msNoSynth_0_r_forwardFlit && - tmp0_r_buffer_ff$FULL_N ; - assign ug_uncached_mem_shim_master_u_aw_peekWire$wget = + assign proc_uncached_wSynth_src_peekWire$wget = + { proc$master1_w_peek[73:1], 1'd0 } ; + assign proc_uncached_bSynth_snk_putWire$wget = + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_bNoSynth_buffer_ff$D_OUT : + msNoSynth_0_bNoSynth_buffer_enqw$wget ; + assign proc_uncached_rSynth_snk_putWire$wget = + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_rNoSynth_buffer_ff$D_OUT : + msNoSynth_0_rNoSynth_buffer_enqw$wget ; + assign uncached_mem_master_awSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_awff$D_OUT } ; - assign ug_uncached_mem_shim_master_u_b_putWire$wget = + assign uncached_mem_master_bSynth_snk_putWire$wget = { cpu_dmem_master_bid, cpu_dmem_master_bresp } ; - assign ug_uncached_mem_shim_master_u_b_putWire$whas = + assign uncached_mem_master_bSynth_snk_putWire$whas = cpu_dmem_master_bvalid && uncached_mem_shim_bff$FULL_N ; - assign ug_uncached_mem_shim_master_u_ar_peekWire$wget = + assign uncached_mem_master_arSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_arff$D_OUT } ; - assign ug_uncached_mem_shim_master_u_r_putWire$wget = + assign uncached_mem_master_rSynth_snk_putWire$wget = { cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast } ; - assign ug_uncached_mem_shim_master_u_r_putWire$whas = + assign uncached_mem_master_rSynth_snk_putWire$whas = cpu_dmem_master_rvalid && uncached_mem_shim_rff$FULL_N ; assign tagController_tmp_ug_slave_u_aw_putWire$wget = + tmp2_awNoSynth_buffer_ff$EMPTY_N ? + tmp2_awNoSynth_buffer_ff$D_OUT : + tmp2_awNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_slave_u_w_putWire$wget = + tmp2_wNoSynth_buffer_ff$EMPTY_N ? + tmp2_wNoSynth_buffer_ff$D_OUT : + tmp2_wNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_slave_u_ar_putWire$wget = + tmp2_arNoSynth_buffer_ff$EMPTY_N ? + tmp2_arNoSynth_buffer_ff$D_OUT : + tmp2_arNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_master_u_b_putWire$wget = + { cpu_imem_master_bid, cpu_imem_master_bresp } ; + assign tagController_tmp_ug_master_u_r_putWire$wget = + { cpu_imem_master_rid, + cpu_imem_master_rdata, + cpu_imem_master_rresp, + cpu_imem_master_rlast } ; + assign tmp2_awNoSynth_buffer_enqw$wget = { proc$master0_awid, proc$master0_awaddr, proc$master0_awlen, @@ -6573,12 +8873,16 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awprot, proc$master0_awqos, proc$master0_awregion } ; - assign tagController_tmp_ug_slave_u_w_putWire$wget = + assign tmp2_wNoSynth_buffer_enqw$wget = { proc$master0_wdata, proc$master0_wstrb, proc$master0_wlast, proc$master0_wuser } ; - assign tagController_tmp_ug_slave_u_ar_putWire$wget = + assign tmp2_bNoSynth_src_peekWire$wget = + tmp2_bNoSynth_buffer_ff$EMPTY_N ? + tmp2_bNoSynth_buffer_ff$D_OUT : + tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; + assign tmp2_arNoSynth_buffer_enqw$wget = { proc$master0_arid, proc$master0_araddr, proc$master0_arlen, @@ -6589,115 +8893,142 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arprot, proc$master0_arqos, proc$master0_arregion } ; - assign tagController_tmp_ug_master_u_b_putWire$wget = - { cpu_imem_master_bid, cpu_imem_master_bresp } ; - assign tagController_tmp_ug_master_u_b_putWire$whas = - cpu_imem_master_bvalid && - !tagController_tmp_shimMaster_bff_rv[8] ; - assign tagController_tmp_ug_master_u_r_putWire$wget = - { cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast } ; - assign tagController_tmp_ug_master_u_r_putWire$whas = - cpu_imem_master_rvalid && - !tagController_tmp_shimMaster_rff_rv[73] ; - assign tmp2_b_buffer_enqw$wget = - tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; - assign tmp2_r_buffer_enqw$wget = - tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; - assign msNoSynth_0_w_dwReady$whas = - WILL_FIRE_RL_merged_0_genOther || - WILL_FIRE_RL_merged_0_genFirst ; - assign msNoSynth_0_b_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ? - ifcs_0_noRouteRsp$D_OUT : - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_0_b_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_0_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_0_forwardRsp ; - assign msNoSynth_0_ar_dwReady$whas = - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && - x_port1__read__h72781 == 9'd1 || - WILL_FIRE_RL_ifcs_0_1_drainFlits || - WILL_FIRE_RL_ifcs_0_1_followFlits || - WILL_FIRE_RL_ifcs_0_1_firstFlit ; - assign msNoSynth_0_r_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ? - ifcs_0_1_noRouteRsp$D_OUT : - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_0_r_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_0_1_forwardRsp ; - assign msNoSynth_1_w_dwReady$whas = - WILL_FIRE_RL_merged_1_genOther || - WILL_FIRE_RL_merged_1_genFirst ; - assign msNoSynth_1_b_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ? - ifcs_1_noRouteRsp$D_OUT : - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_1_b_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_1_forwardRsp ; - assign msNoSynth_1_ar_dwReady$whas = - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && - x_port1__read__h75154 == 9'd1 || - WILL_FIRE_RL_ifcs_1_1_drainFlits || - WILL_FIRE_RL_ifcs_1_1_followFlits || - WILL_FIRE_RL_ifcs_1_1_firstFlit ; - assign msNoSynth_1_r_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ? - ifcs_1_1_noRouteRsp$D_OUT : - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_1_r_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_1_1_forwardRsp ; - assign ssNoSynth_0_w_buffer_enqw$whas = + assign tmp2_rNoSynth_src_peekWire$wget = + tmp2_rNoSynth_buffer_ff$EMPTY_N ? + tmp2_rNoSynth_buffer_ff$D_OUT : + tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; + assign slave_vector_0_awSynth_snk_putWire$wget = + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_awNoSynth_buffer_ff$D_OUT : + split_0_doPut$wget[171:74] ; + assign slave_vector_0_wSynth_snk_putWire$wget = + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_wNoSynth_buffer_ff$D_OUT : + split_0_doPut$wget[73:0] ; + assign slave_vector_0_arSynth_snk_putWire$wget = + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_0_arNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_bNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_0_doPut ? + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 : + ifcs_0_noRouteRsp$D_OUT ; + assign msNoSynth_0_rNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_0_doPut ? + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 : + ifcs_0_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_awNoSynth_buffer_enqw$wget = + { debug_module$master_awid, + debug_module$master_awaddr, + debug_module$master_awlen, + debug_module$master_awsize, + debug_module$master_awburst, + debug_module$master_awlock, + debug_module$master_awcache, + debug_module$master_awprot, + debug_module$master_awqos, + debug_module$master_awregion } ; + assign msNoSynth_1_wNoSynth_buffer_enqw$wget = + { debug_module$master_wdata, + debug_module$master_wstrb, + debug_module$master_wlast, + debug_module$master_wuser } ; + assign msNoSynth_1_bNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_doPut ? + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 : + ifcs_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_bNoSynth_src_peekWire$wget = + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_bNoSynth_buffer_ff$D_OUT : + msNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_arNoSynth_buffer_enqw$wget = + { debug_module$master_arid, + debug_module$master_araddr, + debug_module$master_arlen, + debug_module$master_arsize, + debug_module$master_arburst, + debug_module$master_arlock, + debug_module$master_arcache, + debug_module$master_arprot, + debug_module$master_arqos, + debug_module$master_arregion } ; + assign msNoSynth_1_rNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_1_doPut ? + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 : + ifcs_1_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_rNoSynth_src_peekWire$wget = + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_rNoSynth_buffer_ff$D_OUT : + msNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_0_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] || WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[172] ; - assign ssNoSynth_0_b_dwReady$whas = - WILL_FIRE_RL_ifcs_0_followFlits_1 || - WILL_FIRE_RL_ifcs_0_firstFlit_1 ; - assign ssNoSynth_0_ar_buffer_enqw$wget = + assign ssNoSynth_0_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_0_1$wset_1__SEL_1 || MUX_flitToSink_1_0_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_0_r_dwReady$whas = - WILL_FIRE_RL_ifcs_0_1_followFlits_1 || - WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; - assign ssNoSynth_1_aw_buffer_enqw$wget = split_1_doPut$wget[171:74] ; - assign ssNoSynth_1_w_buffer_enqw$wget = split_1_doPut$wget[73:0] ; - assign ssNoSynth_1_w_buffer_enqw$whas = + assign ssNoSynth_1_awNoSynth_src_peekWire$wget = + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_awNoSynth_buffer_ff$D_OUT : + split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] || WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[172] ; - assign ssNoSynth_1_b_dwReady$whas = - WILL_FIRE_RL_ifcs_1_followFlits_1 || - WILL_FIRE_RL_ifcs_1_firstFlit_1 ; - assign ssNoSynth_1_ar_buffer_enqw$wget = + assign ssNoSynth_1_wNoSynth_src_peekWire$wget = + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_wNoSynth_buffer_ff$D_OUT : + split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_bNoSynth_buffer_enqw$wget = + { plic$axi4_slave_bid, plic$axi4_slave_bresp } ; + assign ssNoSynth_1_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_1_r_dwReady$whas = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 || - WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; - assign ssNoSynth_2_aw_buffer_enqw$wget = split_2_doPut$wget[171:74] ; - assign ssNoSynth_2_w_buffer_enqw$wget = split_2_doPut$wget[73:0] ; - assign ssNoSynth_2_w_buffer_enqw$whas = + assign ssNoSynth_1_arNoSynth_src_peekWire$wget = + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_rNoSynth_buffer_enqw$wget = + { plic$axi4_slave_rid, + plic$axi4_slave_rdata, + plic$axi4_slave_rresp, + plic$axi4_slave_rlast, + plic$axi4_slave_ruser } ; + assign ssNoSynth_2_awNoSynth_src_peekWire$wget = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_awNoSynth_buffer_ff$D_OUT : + split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] || WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[172] ; - assign ssNoSynth_2_b_dwReady$whas = - WILL_FIRE_RL_ifcs_2_followFlits || - WILL_FIRE_RL_ifcs_2_firstFlit ; - assign ssNoSynth_2_ar_buffer_enqw$wget = + assign ssNoSynth_2_wNoSynth_src_peekWire$wget = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_wNoSynth_buffer_ff$D_OUT : + split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_bNoSynth_buffer_enqw$wget = + { proc$debug_module_mem_server_bid, + proc$debug_module_mem_server_bresp } ; + assign ssNoSynth_2_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_2$wset_1__SEL_1 || MUX_flitToSink_1_2$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_2_r_dwReady$whas = - WILL_FIRE_RL_ifcs_2_1_followFlits || - WILL_FIRE_RL_ifcs_2_1_firstFlit ; + assign ssNoSynth_2_arNoSynth_src_peekWire$wget = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_2_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_rNoSynth_buffer_enqw$wget = + { proc$debug_module_mem_server_rid, + proc$debug_module_mem_server_rdata, + proc$debug_module_mem_server_rresp, + proc$debug_module_mem_server_rlast, + proc$debug_module_mem_server_ruser } ; + assign merged_0_outflit$wget = + { 1'd0, merged_0_awff$D_OUT, merged_0_wff$D_OUT } ; + assign merged_1_outflit$wget = + { 1'd0, merged_1_awff$D_OUT, merged_1_wff$D_OUT } ; assign split_0_doPut$wget = (MUX_flitToSink_0$wset_1__SEL_1 || MUX_flitToSink_0$wset_1__SEL_3) ? @@ -6713,15 +9044,21 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_flitToSink_2$wset_1__SEL_3) ? ifcs_0_innerReq$D_OUT : ifcs_1_innerReq$D_OUT ; + assign ifcs_0_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_0_doPut || + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_doPut || + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign reqWires_0$wget = (!ifcs_0_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0] ; assign reqWires_1$wget = (!ifcs_1_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0] ; assign flitToSink_0$whas = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] || @@ -6746,21 +9083,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_innerRoute$D_OUT[2] ; assign reqWires_1_0$wget = (!ifcs_0_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_0_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_0_routeBack$D_OUT[0] ; assign reqWires_1_1$wget = (!ifcs_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_1_routeBack$D_OUT[0] ; assign reqWires_1_2$wget = (!ifcs_2_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_2_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_2_routeBack$D_OUT[0] ; assign flitToSink_1_0$whas = WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] || @@ -6782,15 +9119,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && ifcs_2_routeBack$D_OUT[1] ; + assign ifcs_0_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_0_doPut || + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_1_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_1_doPut || + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign reqWires_1_0_1$wget = (!ifcs_0_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 : + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : ifcs_0_1_innerRoute$D_OUT[0] ; assign reqWires_1_1_1$wget = (!ifcs_1_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 : + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : ifcs_1_1_innerRoute$D_OUT[0] ; assign flitToSink_1_0_1$whas = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] || @@ -6815,21 +9158,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_innerRoute$D_OUT[2] ; assign reqWires_1_1_0$wget = (!ifcs_0_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0] ; assign reqWires_1_1_1_1$wget = (!ifcs_1_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0] ; assign reqWires_1_1_2$wget = (!ifcs_2_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0] ; assign flitToSink_1_1_0$whas = WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] || @@ -6851,21 +9194,40 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_routeBack$D_OUT[1] ; - assign ug_uncached_mem_shim_master_u_aw_dropWire$whas = + assign uncached_mem_master_awSynth_src_dropWire$whas = uncached_mem_shim_awff$EMPTY_N && cpu_dmem_master_awready ; - assign ug_uncached_mem_shim_master_u_w_dropWire$whas = + assign uncached_mem_master_wSynth_src_dropWire$whas = uncached_mem_shim_wff$EMPTY_N && cpu_dmem_master_wready ; - assign ug_uncached_mem_shim_master_u_ar_dropWire$whas = + assign uncached_mem_master_arSynth_src_dropWire$whas = uncached_mem_shim_arff$EMPTY_N && cpu_dmem_master_arready ; - assign tagController_tmp_ug_master_u_aw_dropWire$whas = - tagController_tmp_shimMaster_awff_rv$port1__read[99] && - cpu_imem_master_awready ; - assign tagController_tmp_ug_master_u_w_dropWire$whas = - tagController_tmp_shimMaster_wff_rv$port1__read[73] && - cpu_imem_master_wready ; - assign tagController_tmp_ug_master_u_ar_dropWire$whas = - tagController_tmp_shimMaster_arff_rv$port1__read[99] && - cpu_imem_master_arready ; + assign msNoSynth_0_arNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && x__h95023 == 9'd1 || + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign msNoSynth_1_arNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && x__h97622 == 9'd1 || + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign ssNoSynth_0_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_followFlits_1 || + WILL_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ssNoSynth_0_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ssNoSynth_1_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ssNoSynth_1_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ssNoSynth_2_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_2_followFlits || + WILL_FIRE_RL_ifcs_2_firstFlit ; + assign ssNoSynth_2_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_2_1_followFlits || + WILL_FIRE_RL_ifcs_2_1_firstFlit ; assign merged_0_doDrop$whas = WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp || WILL_FIRE_RL_ifcs_0_drainFlits || @@ -6878,19 +9240,28 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ifcs_1_firstFlit ; assign sourceSelect_1_0$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign sourceSelect_1_1$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign sourceSelect_1_2$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign sourceSelect_1_0_1$whas = WILL_FIRE_RL_arbitrate_2 && - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign sourceSelect_1_1_1$whas = WILL_FIRE_RL_arbitrate_2 && - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; + assign cached_mem_master_awSynth_src_dropWire$whas = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + cpu_imem_master_awready ; + assign cached_mem_master_wSynth_src_dropWire$whas = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + cpu_imem_master_wready ; + assign cached_mem_master_arSynth_src_dropWire$whas = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + cpu_imem_master_arready ; assign tagController_tmp_shimSlave_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_slave_u_aw_putWire$wget } ; assign tagController_tmp_shimSlave_awff_rv$port1__read = @@ -6983,11 +9354,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign tagController_tmp_shimMaster_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_tagCon$memory_request_get[100:95], - aw_awaddr__h10808, + aw_awaddr__h10611, tagController_tmp_tagCon$memory_request_get[7:0], - aw_awsize_val__h12547, + aw_awsize_val__h12350, 3'd2, - x__h14213, + x__h14016, 11'd0 } ; assign tagController_tmp_shimMaster_awff_rv$port1__read = tagController_tmp_shimMaster_awff_rv$EN_port0__write ? @@ -7040,12 +9411,12 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_tagCon$memory_request_get[93:92] != 2'd1 ; assign tagController_tmp_shimMaster_arff_rv$port0__write_1 = { 1'd1, - v_arid__h15556, - v_araddr__h15557, - v_arlen__h15558, - v_arsize_val__h15603, + v_arid__h15359, + v_araddr__h15360, + v_arlen__h15361, + v_arsize_val__h15406, 3'd2, - x__h15621, + x__h15424, 11'd0 } ; assign tagController_tmp_shimMaster_arff_rv$port1__read = tagController_tmp_shimMaster_arff_rv$EN_port0__write ? @@ -7075,25 +9446,16 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_rff_rv$port2__read ; assign ifcs_0_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - merged_0_flitLeft == 8'd0 ; - assign ifcs_0_noRoute_inner_currentReq$port0__write_1 = - { proc$master1_awid, - proc$master1_awaddr, - proc$master1_awlen, - proc$master1_awsize, - proc$master1_awburst, - proc$master1_awlock, - proc$master1_awcache, - proc$master1_awprot, - proc$master1_awqos, - proc$master1_awregion } ; + CAN_FIRE_RL_merged_0_passFlit && + !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_currentReq$port1__read = ifcs_0_noRoute_inner_currentReq$EN_port0__write ? - ifcs_0_noRoute_inner_currentReq$port0__write_1 : + merged_0_outflit$wget[170:74] : ifcs_0_noRoute_inner_currentReq ; assign ifcs_0_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - merged_0_flitLeft == 8'd0 ; + CAN_FIRE_RL_merged_0_passFlit && + !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_pendingReq$port1__read = ifcs_0_noRoute_inner_pendingReq$EN_port0__write || ifcs_0_noRoute_inner_pendingReq ; @@ -7102,77 +9464,44 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_0_noRoute_inner_pendingReq$port1__read ; assign ifcs_1_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - merged_1_flitLeft == 8'd0 ; - assign ifcs_1_noRoute_inner_currentReq$port0__write_1 = - { debug_module$master_awid, - debug_module$master_awaddr, - debug_module$master_awlen, - debug_module$master_awsize, - debug_module$master_awburst, - debug_module$master_awlock, - debug_module$master_awcache, - debug_module$master_awprot, - debug_module$master_awqos, - debug_module$master_awregion } ; + CAN_FIRE_RL_merged_1_passFlit && + !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_currentReq$port1__read = ifcs_1_noRoute_inner_currentReq$EN_port0__write ? - ifcs_1_noRoute_inner_currentReq$port0__write_1 : + merged_1_outflit$wget[170:74] : ifcs_1_noRoute_inner_currentReq ; assign ifcs_1_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - merged_1_flitLeft == 8'd0 ; + CAN_FIRE_RL_merged_1_passFlit && + !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_pendingReq$port1__read = ifcs_1_noRoute_inner_pendingReq$EN_port0__write || ifcs_1_noRoute_inner_pendingReq ; assign ifcs_1_noRoute_inner_pendingReq$port2__read = !CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp && ifcs_1_noRoute_inner_pendingReq$port1__read ; - assign ifcs_0_1_noRoute_currentReq$port0__write_1 = - { proc$master1_arid, - proc$master1_araddr, - proc$master1_arlen, - proc$master1_arsize, - proc$master1_arburst, - proc$master1_arlock, - proc$master1_arcache, - proc$master1_arprot, - proc$master1_arqos, - proc$master1_arregion } ; assign ifcs_0_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? - ifcs_0_1_noRoute_currentReq$port0__write_1 : + msNoSynth_0_arNoSynth_buffer_ff$D_OUT : ifcs_0_1_noRoute_currentReq ; assign ifcs_0_1_noRoute_flitCount$port0__write_1 = - { 1'd0, proc$master1_arlen } + 9'd1 ; - assign ifcs_0_1_noRoute_flitCount$port1__write_1 = - x_port1__read__h72781 - 9'd1 ; + { 1'd0, x__h94920 } + 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port1__write_1 = x__h95023 - 9'd1 ; assign ifcs_0_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ? ifcs_0_1_noRoute_flitCount$port1__write_1 : - x_port1__read__h72781 ; - assign ifcs_1_1_noRoute_currentReq$port0__write_1 = - { debug_module$master_arid, - debug_module$master_araddr, - debug_module$master_arlen, - debug_module$master_arsize, - debug_module$master_arburst, - debug_module$master_arlock, - debug_module$master_arcache, - debug_module$master_arprot, - debug_module$master_arqos, - debug_module$master_arregion } ; + x__h95023 ; assign ifcs_1_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? - ifcs_1_1_noRoute_currentReq$port0__write_1 : + msNoSynth_1_arNoSynth_buffer_ff$D_OUT : ifcs_1_1_noRoute_currentReq ; assign ifcs_1_1_noRoute_flitCount$port0__write_1 = - { 1'd0, debug_module$master_arlen } + 9'd1 ; - assign ifcs_1_1_noRoute_flitCount$port1__write_1 = - x_port1__read__h75154 - 9'd1 ; + { 1'd0, x__h97519 } + 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port1__write_1 = x__h97622 - 9'd1 ; assign ifcs_1_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ? ifcs_1_1_noRoute_flitCount$port1__write_1 : - x_port1__read__h75154 ; + x__h97622 ; // register activeSource_0 assign activeSource_0$D_IN = @@ -7290,52 +9619,52 @@ module mkCoreW(RST_N_dm_power_on_reset, // register arbiter_1_1_firstHot assign arbiter_1_1_firstHot$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; assign arbiter_1_1_firstHot$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect assign arbiter_1_1_lastSelect$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign arbiter_1_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect_1 assign arbiter_1_1_lastSelect_1$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign arbiter_1_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_firstHot assign arbiter_1_firstHot$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign arbiter_1_firstHot$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_firstHot_1 assign arbiter_1_firstHot_1$D_IN = - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; assign arbiter_1_firstHot_1$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_1_lastSelect assign arbiter_1_lastSelect$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign arbiter_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_1 assign arbiter_1_lastSelect_1$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign arbiter_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_2 assign arbiter_1_lastSelect_2$D_IN = - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign arbiter_1_lastSelect_2$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_firstHot assign arbiter_firstHot$D_IN = - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign arbiter_firstHot$EN = CAN_FIRE_RL_arbitrate ; // register arbiter_lastSelect assign arbiter_lastSelect$D_IN = - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign arbiter_lastSelect$EN = CAN_FIRE_RL_arbitrate ; // register ifcs_0_1_noRoute_currentReq @@ -7358,9 +9687,9 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_state_1$D_IN = !MUX_ifcs_0_1_state_1$write_1__SEL_1 ; assign ifcs_0_1_state_1$EN = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && - uncached_mem_shim_rff$D_OUT[1] || + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && - !uncached_mem_shim_rff$D_OUT[1] ; + !ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_0_noRoute_inner_currentReq assign ifcs_0_noRoute_inner_currentReq$D_IN = @@ -7386,9 +9715,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_state$EN = (WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits) && - proc$master1_wlast || - WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast || - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 || + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; // register ifcs_0_state_1 assign ifcs_0_state_1$D_IN = 1'd0 ; @@ -7413,8 +9744,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // register ifcs_1_1_state_1 assign ifcs_1_1_state_1$D_IN = !MUX_ifcs_1_1_state_1$write_1__SEL_1 ; assign ifcs_1_1_state_1$EN = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast || - WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && !plic$axi4_slave_rlast ; + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + !ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_1_noRoute_inner_currentReq assign ifcs_1_noRoute_inner_currentReq$D_IN = @@ -7440,10 +9773,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_state$EN = (WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits) && - debug_module$master_wlast || - WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast || + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 || + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - !debug_module$master_wlast ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; // register ifcs_1_state_1 assign ifcs_1_state_1$D_IN = 1'd0 ; @@ -7453,9 +9787,9 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_2_1_state$D_IN = !MUX_ifcs_2_1_state$write_1__SEL_1 ; assign ifcs_2_1_state$EN = WILL_FIRE_RL_ifcs_2_1_followFlits && - proc$debug_module_mem_server_rlast || + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_2_1_firstFlit && - !proc$debug_module_mem_server_rlast ; + !ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_2_state assign ifcs_2_state$D_IN = 1'd0 ; @@ -7463,17 +9797,21 @@ module mkCoreW(RST_N_dm_power_on_reset, // register merged_0_flitLeft assign merged_0_flitLeft$D_IN = - WILL_FIRE_RL_merged_0_genOther ? - MUX_merged_0_flitLeft$write_1__VAL_1 : - proc$master1_awlen ; - assign merged_0_flitLeft$EN = msNoSynth_0_w_dwReady$whas ; + WILL_FIRE_RL_merged_0_genFirst ? + merged_0_awff$D_OUT[28:21] : + MUX_merged_0_flitLeft$write_1__VAL_2 ; + assign merged_0_flitLeft$EN = + WILL_FIRE_RL_merged_0_genFirst || + WILL_FIRE_RL_merged_0_genOther ; // register merged_1_flitLeft assign merged_1_flitLeft$D_IN = - WILL_FIRE_RL_merged_1_genOther ? - MUX_merged_1_flitLeft$write_1__VAL_1 : - debug_module$master_awlen ; - assign merged_1_flitLeft$EN = msNoSynth_1_w_dwReady$whas ; + WILL_FIRE_RL_merged_1_genFirst ? + merged_1_awff$D_OUT[28:21] : + MUX_merged_1_flitLeft$write_1__VAL_2 ; + assign merged_1_flitLeft$EN = + WILL_FIRE_RL_merged_1_genFirst || + WILL_FIRE_RL_merged_1_genOther ; // register rg_fromhost_addr assign rg_fromhost_addr$D_IN = start_fromhost_addr ; @@ -7497,21 +9835,21 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_split_0_flitLeft$write_1__SEL_1 ? MUX_split_0_flitLeft$write_1__VAL_1 : split_0_doPut$wget[102:95] ; - assign split_0_flitLeft$EN = ssNoSynth_0_w_buffer_enqw$whas ; + assign split_0_flitLeft$EN = ssNoSynth_0_wNoSynth_buffer_enqw$whas ; // register split_1_flitLeft assign split_1_flitLeft$D_IN = MUX_split_1_flitLeft$write_1__SEL_1 ? MUX_split_1_flitLeft$write_1__VAL_1 : split_1_doPut$wget[102:95] ; - assign split_1_flitLeft$EN = ssNoSynth_1_w_buffer_enqw$whas ; + assign split_1_flitLeft$EN = ssNoSynth_1_wNoSynth_buffer_enqw$whas ; // register split_2_flitLeft assign split_2_flitLeft$D_IN = MUX_split_2_flitLeft$write_1__SEL_1 ? MUX_split_2_flitLeft$write_1__VAL_1 : split_2_doPut$wget[102:95] ; - assign split_2_flitLeft$EN = ssNoSynth_2_w_buffer_enqw$whas ; + assign split_2_flitLeft$EN = ssNoSynth_2_wNoSynth_buffer_enqw$whas ; // register state assign state$D_IN = !MUX_state$write_1__SEL_1 && !MUX_state$write_1__SEL_2 ; @@ -7553,7 +9891,7 @@ module mkCoreW(RST_N_dm_power_on_reset, assign tagController_tmp_addrOffset$D_IN = tagController_tmp_shimSlave_wff_rv$port1__read[1] ? 64'd0 : - x__h8207 ; + x__h8010 ; assign tagController_tmp_addrOffset$EN = WILL_FIRE_RL_tagController_tmp_passCacheWrite ; @@ -7631,37 +9969,27 @@ module mkCoreW(RST_N_dm_power_on_reset, assign debug_module$hart0_gpr_mem_client_response_put = proc$hart0_gpr_mem_server_response_get ; assign debug_module$hart0_reset_client_response_put = 1'd1 ; - assign debug_module$master_arready = msNoSynth_1_ar_dwReady$whas ; - assign debug_module$master_awready = CAN_FIRE_RL_merged_1_genFirst ; + assign debug_module$master_arready = + msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign debug_module$master_awready = + msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; assign debug_module$master_bid = - msNoSynth_1_b_buffer_ff$EMPTY_N ? - msNoSynth_1_b_buffer_ff$D_OUT[5:2] : - msNoSynth_1_b_buffer_enqw$wget[5:2] ; + msNoSynth_1_bNoSynth_src_peekWire$wget[5:2] ; assign debug_module$master_bresp = - msNoSynth_1_b_buffer_ff$EMPTY_N ? - msNoSynth_1_b_buffer_ff$D_OUT[1:0] : - msNoSynth_1_b_buffer_enqw$wget[1:0] ; + msNoSynth_1_bNoSynth_src_peekWire$wget[1:0] ; + assign debug_module$master_bvalid = msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign debug_module$master_rdata = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[67:4] : - msNoSynth_1_r_buffer_enqw$wget[67:4] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[67:4] ; assign debug_module$master_rid = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[71:68] : - msNoSynth_1_r_buffer_enqw$wget[71:68] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[71:68] ; assign debug_module$master_rlast = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[1] : - msNoSynth_1_r_buffer_enqw$wget[1] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[1] ; assign debug_module$master_rresp = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[3:2] : - msNoSynth_1_r_buffer_enqw$wget[3:2] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[3:2] ; assign debug_module$master_ruser = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[0] : - msNoSynth_1_r_buffer_enqw$wget[0] ; - assign debug_module$master_wready = msNoSynth_1_w_dwReady$whas ; + msNoSynth_1_rNoSynth_src_peekWire$wget[0] ; + assign debug_module$master_rvalid = msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign debug_module$master_wready = msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; assign debug_module$ndm_reset_client_response_put = ndm_reset_client_response_put ; assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; @@ -7691,24 +10019,16 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_ndm_reset_client_request_get ; assign debug_module$EN_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; - assign debug_module$master_bvalid = CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; - assign debug_module$master_rvalid = CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; // submodule dm_hart0_reset_controller assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; // submodule ifcs_0_1_innerReq assign ifcs_0_1_innerReq$D_IN = - { fatReq_arid__h72223, - proc$master1_araddr, - proc$master1_arlen, - proc$master1_arsize, - proc$master1_arburst, - proc$master1_arlock, - proc$master1_arcache, - proc$master1_arprot, - proc$master1_arqos, - proc$master1_arregion } ; + { fatReq_arid__h94342, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:0] : + proc$master1_ar_peek[92:0] } ; assign ifcs_0_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_1_followFlits || WILL_FIRE_RL_ifcs_0_1_firstFlit ; @@ -7719,16 +10039,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_1_innerRoute assign ifcs_0_1_innerRoute$D_IN = - { !proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845, - (proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - !proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850, - (proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - (proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850) } ; + { !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) } ; assign ifcs_0_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit ; assign ifcs_0_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || @@ -7739,14 +10059,15 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_noRouteRsp$D_IN = { ifcs_0_1_noRoute_currentReq$port1__read[96:93], 66'h2AAAAAAAAAAAAAAAB, - x_port1__read__h72781 == 9'd1, + x__h95023 == 9'd1, 1'h0 } ; assign ifcs_0_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; - assign ifcs_0_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_0_1_noRouteRsp$DEQ = + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; assign ifcs_0_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_1_routeBack - assign ifcs_0_1_routeBack$D_IN = 2'd1 << uncached_mem_shim_rff$D_OUT[72] ; + assign ifcs_0_1_routeBack$D_IN = 2'd1 << x__h98415[4] ; assign ifcs_0_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; assign ifcs_0_1_routeBack$DEQ = WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] || @@ -7755,8 +10076,12 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_routeBack$CLR = 1'b0 ; // submodule ifcs_0_1_rspBack - assign ifcs_0_1_rspBack$D_IN = uncached_mem_shim_rff$D_OUT[71:0] ; - assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_r_dwReady$whas ; + assign ifcs_0_1_rspBack$D_IN = + { x__h98415[3:0], + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[67:0] : + uncached_mem_shim_rff$D_OUT[67:0] } ; + assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; assign ifcs_0_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_7 ; @@ -7764,21 +10089,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_innerReq assign ifcs_0_innerReq$D_IN = - { merged_0_flitLeft != 8'd0, - a_awid__h38523, - proc$master1_awaddr, - proc$master1_awlen, - proc$master1_awsize, - proc$master1_awburst, - proc$master1_awlock, - proc$master1_awcache, - proc$master1_awprot, - proc$master1_awqos, - proc$master1_awregion, - proc$master1_wdata, - proc$master1_wstrb, - proc$master1_wlast, - 1'd0 } ; + { !CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171], + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 } ; assign ifcs_0_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_followFlits || WILL_FIRE_RL_ifcs_0_firstFlit ; @@ -7789,16 +10101,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_innerRoute assign ifcs_0_innerRoute$D_IN = - { !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195, - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203, - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203) } ; + { !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) } ; assign ifcs_0_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit ; assign ifcs_0_innerRoute$DEQ = WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] || @@ -7810,11 +10122,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_noRouteRsp$D_IN = { ifcs_0_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_0_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; - assign ifcs_0_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_0_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; assign ifcs_0_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_routeBack - assign ifcs_0_routeBack$D_IN = 2'd1 << uncached_mem_shim_bff$D_OUT[6] ; + assign ifcs_0_routeBack$D_IN = 2'd1 << x__h62625[4] ; assign ifcs_0_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; assign ifcs_0_routeBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || @@ -7822,8 +10134,12 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_routeBack$CLR = 1'b0 ; // submodule ifcs_0_rspBack - assign ifcs_0_rspBack$D_IN = uncached_mem_shim_bff$D_OUT[5:0] ; - assign ifcs_0_rspBack$ENQ = ssNoSynth_0_b_dwReady$whas ; + assign ifcs_0_rspBack$D_IN = + { x__h62625[3:0], + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[1:0] : + uncached_mem_shim_bff$D_OUT[1:0] } ; + assign ifcs_0_rspBack$ENQ = ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; assign ifcs_0_rspBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || WILL_FIRE_RL_burst_2 ; @@ -7831,16 +10147,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_innerReq assign ifcs_1_1_innerReq$D_IN = - { fatReq_arid__h74597, - debug_module$master_araddr, - debug_module$master_arlen, - debug_module$master_arsize, - debug_module$master_arburst, - debug_module$master_arlock, - debug_module$master_arcache, - debug_module$master_arprot, - debug_module$master_arqos, - debug_module$master_arregion } ; + { fatReq_arid__h96944, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:0] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[92:0] } ; assign ifcs_1_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_1_followFlits || WILL_FIRE_RL_ifcs_1_1_firstFlit ; @@ -7851,16 +10161,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_innerRoute assign ifcs_1_1_innerRoute$D_IN = - { !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932, - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937, - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937) } ; + { !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) } ; assign ifcs_1_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit ; assign ifcs_1_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || @@ -7871,14 +10181,15 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_1_noRouteRsp$D_IN = { ifcs_1_1_noRoute_currentReq$port1__read[96:93], 66'h2AAAAAAAAAAAAAAAB, - x_port1__read__h75154 == 9'd1, + x__h97622 == 9'd1, 1'h0 } ; assign ifcs_1_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; - assign ifcs_1_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ifcs_1_1_noRouteRsp$DEQ = + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign ifcs_1_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_1_routeBack - assign ifcs_1_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_rid[4] ; + assign ifcs_1_1_routeBack$D_IN = 2'd1 << x__h99370[4] ; assign ifcs_1_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; assign ifcs_1_1_routeBack$DEQ = WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] || @@ -7888,12 +10199,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_rspBack assign ifcs_1_1_rspBack$D_IN = - { plic$axi4_slave_rid[3:0], - plic$axi4_slave_rdata, - plic$axi4_slave_rresp, - plic$axi4_slave_rlast, - plic$axi4_slave_ruser } ; - assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_r_dwReady$whas ; + { x__h99370[3:0], + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[67:0] : + ssNoSynth_1_rNoSynth_buffer_enqw$wget[67:0] } ; + assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; assign ifcs_1_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_8 ; @@ -7901,21 +10211,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_innerReq assign ifcs_1_innerReq$D_IN = - { merged_1_flitLeft != 8'd0, - a_awid__h41194, - debug_module$master_awaddr, - debug_module$master_awlen, - debug_module$master_awsize, - debug_module$master_awburst, - debug_module$master_awlock, - debug_module$master_awcache, - debug_module$master_awprot, - debug_module$master_awqos, - debug_module$master_awregion, - debug_module$master_wdata, - debug_module$master_wstrb, - debug_module$master_wlast, - debug_module$master_wuser } ; + { !CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171], + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 } ; assign ifcs_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_followFlits || WILL_FIRE_RL_ifcs_1_firstFlit ; @@ -7926,16 +10223,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_innerRoute assign ifcs_1_innerRoute$D_IN = - { !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297, - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302, - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302) } ; + { !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) } ; assign ifcs_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit ; assign ifcs_1_innerRoute$DEQ = WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] || @@ -7947,11 +10244,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_noRouteRsp$D_IN = { ifcs_1_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; - assign ifcs_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign ifcs_1_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign ifcs_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_routeBack - assign ifcs_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_bid[4] ; + assign ifcs_1_routeBack$D_IN = 2'd1 << x__h63516[4] ; assign ifcs_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; assign ifcs_1_routeBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || @@ -7960,16 +10257,18 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_rspBack assign ifcs_1_rspBack$D_IN = - { plic$axi4_slave_bid[3:0], plic$axi4_slave_bresp } ; - assign ifcs_1_rspBack$ENQ = ssNoSynth_1_b_dwReady$whas ; + { x__h63516[3:0], + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[1:0] : + ssNoSynth_1_bNoSynth_buffer_enqw$wget[1:0] } ; + assign ifcs_1_rspBack$ENQ = ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; assign ifcs_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_3 ; assign ifcs_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_1_routeBack - assign ifcs_2_1_routeBack$D_IN = - 2'd1 << proc$debug_module_mem_server_rid[4] ; + assign ifcs_2_1_routeBack$D_IN = 2'd1 << x__h100325[4] ; assign ifcs_2_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_1_firstFlit ; assign ifcs_2_1_routeBack$DEQ = WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] || @@ -7979,19 +10278,18 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_2_1_rspBack assign ifcs_2_1_rspBack$D_IN = - { proc$debug_module_mem_server_rid[3:0], - proc$debug_module_mem_server_rdata, - proc$debug_module_mem_server_rresp, - proc$debug_module_mem_server_rlast, - proc$debug_module_mem_server_ruser } ; - assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_r_dwReady$whas ; + { x__h100325[3:0], + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[67:0] : + ssNoSynth_2_rNoSynth_buffer_enqw$wget[67:0] } ; + assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; assign ifcs_2_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_9 ; assign ifcs_2_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_routeBack - assign ifcs_2_routeBack$D_IN = 2'd1 << proc$debug_module_mem_server_bid[4] ; + assign ifcs_2_routeBack$D_IN = 2'd1 << x__h64407[4] ; assign ifcs_2_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_firstFlit ; assign ifcs_2_routeBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || @@ -8000,165 +10298,245 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_2_rspBack assign ifcs_2_rspBack$D_IN = - { proc$debug_module_mem_server_bid[3:0], - proc$debug_module_mem_server_bresp } ; - assign ifcs_2_rspBack$ENQ = ssNoSynth_2_b_dwReady$whas ; + { x__h64407[3:0], + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[1:0] : + ssNoSynth_2_bNoSynth_buffer_enqw$wget[1:0] } ; + assign ifcs_2_rspBack$ENQ = ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; assign ifcs_2_rspBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || WILL_FIRE_RL_burst_4 ; assign ifcs_2_rspBack$CLR = 1'b0 ; - // submodule msNoSynth_0_b_buffer_ff - assign msNoSynth_0_b_buffer_ff$D_IN = msNoSynth_0_b_buffer_enqw$wget ; - assign msNoSynth_0_b_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; - assign msNoSynth_0_b_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; - assign msNoSynth_0_b_buffer_ff$CLR = 1'b0 ; + // submodule merged_0_awff + assign merged_0_awff$D_IN = + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_awNoSynth_buffer_ff$D_OUT : + proc$master1_aw_peek ; + assign merged_0_awff$ENQ = CAN_FIRE_RL_merged_0_awFlit ; + assign merged_0_awff$DEQ = CAN_FIRE_RL_merged_0_genFirst ; + assign merged_0_awff$CLR = 1'b0 ; - // submodule msNoSynth_0_b_buffer_firstValid - assign msNoSynth_0_b_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_0_b_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + // submodule merged_0_wff + assign merged_0_wff$D_IN = + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_wNoSynth_buffer_ff$D_OUT : + proc_uncached_wSynth_src_peekWire$wget ; + assign merged_0_wff$ENQ = CAN_FIRE_RL_merged_0_wFlit ; + assign merged_0_wff$DEQ = + WILL_FIRE_RL_merged_0_genOther || + WILL_FIRE_RL_merged_0_genFirst ; + assign merged_0_wff$CLR = 1'b0 ; - // submodule msNoSynth_0_r_buffer_ff - assign msNoSynth_0_r_buffer_ff$D_IN = msNoSynth_0_r_buffer_enqw$wget ; - assign msNoSynth_0_r_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; - assign msNoSynth_0_r_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; - assign msNoSynth_0_r_buffer_ff$CLR = 1'b0 ; + // submodule merged_1_awff + assign merged_1_awff$D_IN = + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_awNoSynth_buffer_ff$D_OUT : + msNoSynth_1_awNoSynth_buffer_enqw$wget ; + assign merged_1_awff$ENQ = CAN_FIRE_RL_merged_1_awFlit ; + assign merged_1_awff$DEQ = CAN_FIRE_RL_merged_1_genFirst ; + assign merged_1_awff$CLR = 1'b0 ; - // submodule msNoSynth_0_r_buffer_firstValid - assign msNoSynth_0_r_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_0_r_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; + // submodule merged_1_wff + assign merged_1_wff$D_IN = + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_wNoSynth_buffer_ff$D_OUT : + msNoSynth_1_wNoSynth_buffer_enqw$wget ; + assign merged_1_wff$ENQ = CAN_FIRE_RL_merged_1_wFlit ; + assign merged_1_wff$DEQ = + WILL_FIRE_RL_merged_1_genOther || + WILL_FIRE_RL_merged_1_genFirst ; + assign merged_1_wff$CLR = 1'b0 ; - // submodule msNoSynth_1_b_buffer_ff - assign msNoSynth_1_b_buffer_ff$D_IN = msNoSynth_1_b_buffer_enqw$wget ; - assign msNoSynth_1_b_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; - assign msNoSynth_1_b_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; - assign msNoSynth_1_b_buffer_ff$CLR = 1'b0 ; + // submodule msNoSynth_0_arNoSynth_buffer_ff + assign msNoSynth_0_arNoSynth_buffer_ff$D_IN = proc$master1_ar_peek ; + assign msNoSynth_0_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; + assign msNoSynth_0_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; + assign msNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule msNoSynth_1_b_buffer_firstValid - assign msNoSynth_1_b_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_1_b_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + // submodule msNoSynth_0_arNoSynth_buffer_firstValid + assign msNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_arNoSynth_buffer_firstValid$EN = + msNoSynth_0_arNoSynth_buffer_dequeueing$whas ; - // submodule msNoSynth_1_r_buffer_ff - assign msNoSynth_1_r_buffer_ff$D_IN = msNoSynth_1_r_buffer_enqw$wget ; - assign msNoSynth_1_r_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; - assign msNoSynth_1_r_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; - assign msNoSynth_1_r_buffer_ff$CLR = 1'b0 ; + // submodule msNoSynth_0_awNoSynth_buffer_ff + assign msNoSynth_0_awNoSynth_buffer_ff$D_IN = proc$master1_aw_peek ; + assign msNoSynth_0_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; + assign msNoSynth_0_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; + assign msNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule msNoSynth_1_r_buffer_firstValid - assign msNoSynth_1_r_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_1_r_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; + // submodule msNoSynth_0_awNoSynth_buffer_firstValid + assign msNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_0_awFlit ; + + // submodule msNoSynth_0_bNoSynth_buffer_ff + assign msNoSynth_0_bNoSynth_buffer_ff$D_IN = + msNoSynth_0_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; + assign msNoSynth_0_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; + assign msNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_bNoSynth_buffer_firstValid + assign msNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; + + // submodule msNoSynth_0_rNoSynth_buffer_ff + assign msNoSynth_0_rNoSynth_buffer_ff$D_IN = + msNoSynth_0_rNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; + assign msNoSynth_0_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; + assign msNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_rNoSynth_buffer_firstValid + assign msNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; + + // submodule msNoSynth_0_wNoSynth_buffer_ff + assign msNoSynth_0_wNoSynth_buffer_ff$D_IN = + proc_uncached_wSynth_src_peekWire$wget ; + assign msNoSynth_0_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; + assign msNoSynth_0_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; + assign msNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_wNoSynth_buffer_firstValid + assign msNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_0_wFlit ; + + // submodule msNoSynth_1_arNoSynth_buffer_ff + assign msNoSynth_1_arNoSynth_buffer_ff$D_IN = + msNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; + assign msNoSynth_1_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; + assign msNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_arNoSynth_buffer_firstValid + assign msNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_arNoSynth_buffer_firstValid$EN = + msNoSynth_1_arNoSynth_buffer_dequeueing$whas ; + + // submodule msNoSynth_1_awNoSynth_buffer_ff + assign msNoSynth_1_awNoSynth_buffer_ff$D_IN = + msNoSynth_1_awNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; + assign msNoSynth_1_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; + assign msNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_awNoSynth_buffer_firstValid + assign msNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_1_awFlit ; + + // submodule msNoSynth_1_bNoSynth_buffer_ff + assign msNoSynth_1_bNoSynth_buffer_ff$D_IN = + msNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; + assign msNoSynth_1_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; + assign msNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_bNoSynth_buffer_firstValid + assign msNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; + + // submodule msNoSynth_1_rNoSynth_buffer_ff + assign msNoSynth_1_rNoSynth_buffer_ff$D_IN = + msNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; + assign msNoSynth_1_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; + assign msNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_rNoSynth_buffer_firstValid + assign msNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; + + // submodule msNoSynth_1_wNoSynth_buffer_ff + assign msNoSynth_1_wNoSynth_buffer_ff$D_IN = + msNoSynth_1_wNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; + assign msNoSynth_1_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; + assign msNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_wNoSynth_buffer_firstValid + assign msNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_1_wFlit ; // submodule plic assign plic$axi4_slave_araddr = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[92:29] : - ssNoSynth_1_ar_buffer_enqw$wget[92:29] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_arburst = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[17:16] : - ssNoSynth_1_ar_buffer_enqw$wget[17:16] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_arcache = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[14:11] : - ssNoSynth_1_ar_buffer_enqw$wget[14:11] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_arid = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[97:93] : - ssNoSynth_1_ar_buffer_enqw$wget[97:93] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_arlen = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[28:21] : - ssNoSynth_1_ar_buffer_enqw$wget[28:21] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_arlock = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[15] : - ssNoSynth_1_ar_buffer_enqw$wget[15] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_arprot = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[10:8] : - ssNoSynth_1_ar_buffer_enqw$wget[10:8] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_arqos = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[7:4] : - ssNoSynth_1_ar_buffer_enqw$wget[7:4] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_arregion = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[3:0] : - ssNoSynth_1_ar_buffer_enqw$wget[3:0] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_arsize = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[20:18] : - ssNoSynth_1_ar_buffer_enqw$wget[20:18] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[20:18] ; + assign plic$axi4_slave_arvalid = ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign plic$axi4_slave_awaddr = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[92:29] : - ssNoSynth_1_aw_buffer_enqw$wget[92:29] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_awburst = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[17:16] : - ssNoSynth_1_aw_buffer_enqw$wget[17:16] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_awcache = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[14:11] : - ssNoSynth_1_aw_buffer_enqw$wget[14:11] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_awid = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[97:93] : - ssNoSynth_1_aw_buffer_enqw$wget[97:93] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_awlen = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[28:21] : - ssNoSynth_1_aw_buffer_enqw$wget[28:21] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_awlock = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[15] : - ssNoSynth_1_aw_buffer_enqw$wget[15] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_awprot = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[10:8] : - ssNoSynth_1_aw_buffer_enqw$wget[10:8] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_awqos = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[7:4] : - ssNoSynth_1_aw_buffer_enqw$wget[7:4] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_awregion = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[3:0] : - ssNoSynth_1_aw_buffer_enqw$wget[3:0] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_awsize = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[20:18] : - ssNoSynth_1_aw_buffer_enqw$wget[20:18] ; - assign plic$axi4_slave_bready = ssNoSynth_1_b_dwReady$whas ; - assign plic$axi4_slave_rready = ssNoSynth_1_r_dwReady$whas ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[20:18] ; + assign plic$axi4_slave_awvalid = ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign plic$axi4_slave_bready = ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign plic$axi4_slave_rready = ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign plic$axi4_slave_wdata = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[73:10] : - ssNoSynth_1_w_buffer_enqw$wget[73:10] ; - assign plic$axi4_slave_wlast = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[1] : - ssNoSynth_1_w_buffer_enqw$wget[1] ; - assign plic$axi4_slave_wstrb = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[9:2] : - ssNoSynth_1_w_buffer_enqw$wget[9:2] ; - assign plic$axi4_slave_wuser = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[0] : - ssNoSynth_1_w_buffer_enqw$wget[0] ; + ssNoSynth_1_wNoSynth_src_peekWire$wget[73:10] ; + assign plic$axi4_slave_wlast = ssNoSynth_1_wNoSynth_src_peekWire$wget[1] ; + assign plic$axi4_slave_wstrb = ssNoSynth_1_wNoSynth_src_peekWire$wget[9:2] ; + assign plic$axi4_slave_wuser = ssNoSynth_1_wNoSynth_src_peekWire$wget[0] ; + assign plic$axi4_slave_wvalid = ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_range[127:64] ; assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_range[127:64] + @@ -8201,109 +10579,66 @@ module mkCoreW(RST_N_dm_power_on_reset, assign plic$EN_server_reset_request_put = 1'b0 ; assign plic$EN_server_reset_response_get = 1'b0 ; assign plic$EN_set_addr_map = EN_start ; - assign plic$axi4_slave_awvalid = CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; - assign plic$axi4_slave_wvalid = CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; - assign plic$axi4_slave_arvalid = CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; // submodule proc assign proc$debug_module_mem_server_araddr = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[92:29] : - ssNoSynth_2_ar_buffer_enqw$wget[92:29] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_arburst = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[17:16] : - ssNoSynth_2_ar_buffer_enqw$wget[17:16] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_arcache = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[14:11] : - ssNoSynth_2_ar_buffer_enqw$wget[14:11] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_arid = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[97:93] : - ssNoSynth_2_ar_buffer_enqw$wget[97:93] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_arlen = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[28:21] : - ssNoSynth_2_ar_buffer_enqw$wget[28:21] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_arlock = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[15] : - ssNoSynth_2_ar_buffer_enqw$wget[15] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_arprot = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[10:8] : - ssNoSynth_2_ar_buffer_enqw$wget[10:8] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_arqos = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[7:4] : - ssNoSynth_2_ar_buffer_enqw$wget[7:4] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_arregion = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[3:0] : - ssNoSynth_2_ar_buffer_enqw$wget[3:0] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_arsize = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[20:18] : - ssNoSynth_2_ar_buffer_enqw$wget[20:18] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[20:18] ; + assign proc$debug_module_mem_server_arvalid = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; assign proc$debug_module_mem_server_awaddr = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[92:29] : - ssNoSynth_2_aw_buffer_enqw$wget[92:29] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_awburst = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[17:16] : - ssNoSynth_2_aw_buffer_enqw$wget[17:16] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_awcache = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[14:11] : - ssNoSynth_2_aw_buffer_enqw$wget[14:11] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_awid = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[97:93] : - ssNoSynth_2_aw_buffer_enqw$wget[97:93] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_awlen = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[28:21] : - ssNoSynth_2_aw_buffer_enqw$wget[28:21] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_awlock = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[15] : - ssNoSynth_2_aw_buffer_enqw$wget[15] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_awprot = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[10:8] : - ssNoSynth_2_aw_buffer_enqw$wget[10:8] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_awqos = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[7:4] : - ssNoSynth_2_aw_buffer_enqw$wget[7:4] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_awregion = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[3:0] : - ssNoSynth_2_aw_buffer_enqw$wget[3:0] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_awsize = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[20:18] : - ssNoSynth_2_aw_buffer_enqw$wget[20:18] ; - assign proc$debug_module_mem_server_bready = ssNoSynth_2_b_dwReady$whas ; - assign proc$debug_module_mem_server_rready = ssNoSynth_2_r_dwReady$whas ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[20:18] ; + assign proc$debug_module_mem_server_awvalid = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign proc$debug_module_mem_server_bready = + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign proc$debug_module_mem_server_rready = + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; assign proc$debug_module_mem_server_wdata = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[73:10] : - ssNoSynth_2_w_buffer_enqw$wget[73:10] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[73:10] ; assign proc$debug_module_mem_server_wlast = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[1] : - ssNoSynth_2_w_buffer_enqw$wget[1] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[1] ; assign proc$debug_module_mem_server_wstrb = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[9:2] : - ssNoSynth_2_w_buffer_enqw$wget[9:2] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[9:2] ; assign proc$debug_module_mem_server_wuser = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[0] : - ssNoSynth_2_w_buffer_enqw$wget[0] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[0] ; + assign proc$debug_module_mem_server_wvalid = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; assign proc$hart0_csr_mem_server_request_put = debug_module$hart0_csr_mem_client_request_get ; assign proc$hart0_fpr_mem_server_request_put = 70'h0 ; @@ -8314,71 +10649,21 @@ module mkCoreW(RST_N_dm_power_on_reset, debug_module$hart0_client_run_halt_request_get ; assign proc$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign proc$master0_arready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; - assign proc$master0_awready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; - assign proc$master0_bid = - tmp2_b_buffer_ff$EMPTY_N ? - tmp2_b_buffer_ff$D_OUT[6:2] : - tmp2_b_buffer_enqw$wget[6:2] ; - assign proc$master0_bresp = - tmp2_b_buffer_ff$EMPTY_N ? - tmp2_b_buffer_ff$D_OUT[1:0] : - tmp2_b_buffer_enqw$wget[1:0] ; - assign proc$master0_rdata = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[67:4] : - tmp2_r_buffer_enqw$wget[67:4] ; - assign proc$master0_rid = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[72:68] : - tmp2_r_buffer_enqw$wget[72:68] ; - assign proc$master0_rlast = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[1] : - tmp2_r_buffer_enqw$wget[1] ; - assign proc$master0_rresp = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[3:2] : - tmp2_r_buffer_enqw$wget[3:2] ; - assign proc$master0_ruser = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[0] : - tmp2_r_buffer_enqw$wget[0] ; - assign proc$master0_wready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; - assign proc$master1_arready = tmp0_ar_dwReady$whas ; - assign proc$master1_awready = tmp0_aw_dwReady$whas ; - assign proc$master1_bid = - tmp0_b_buffer_ff$EMPTY_N ? - tmp0_b_buffer_ff$D_OUT[5:2] : - tmp0_b_buffer_enqw$wget[5:2] ; - assign proc$master1_bresp = - tmp0_b_buffer_ff$EMPTY_N ? - tmp0_b_buffer_ff$D_OUT[1:0] : - tmp0_b_buffer_enqw$wget[1:0] ; - assign proc$master1_rdata = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[67:4] : - tmp0_r_buffer_enqw$wget[67:4] ; - assign proc$master1_rid = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[71:68] : - tmp0_r_buffer_enqw$wget[71:68] ; - assign proc$master1_rlast = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[1] : - tmp0_r_buffer_enqw$wget[1] ; - assign proc$master1_rresp = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[3:2] : - tmp0_r_buffer_enqw$wget[3:2] ; - assign proc$master1_ruser = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[0] : - tmp0_r_buffer_enqw$wget[0] ; - assign proc$master1_wready = tmp0_w_dwReady$whas ; + assign proc$master0_arready = tmp2_arNoSynth_buffer_ff$FULL_N ; + assign proc$master0_awready = tmp2_awNoSynth_buffer_ff$FULL_N ; + assign proc$master0_bid = tmp2_bNoSynth_src_peekWire$wget[6:2] ; + assign proc$master0_bresp = tmp2_bNoSynth_src_peekWire$wget[1:0] ; + assign proc$master0_bvalid = tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign proc$master0_rdata = tmp2_rNoSynth_src_peekWire$wget[67:4] ; + assign proc$master0_rid = tmp2_rNoSynth_src_peekWire$wget[72:68] ; + assign proc$master0_rlast = tmp2_rNoSynth_src_peekWire$wget[1] ; + assign proc$master0_rresp = tmp2_rNoSynth_src_peekWire$wget[3:2] ; + assign proc$master0_ruser = tmp2_rNoSynth_src_peekWire$wget[0] ; + assign proc$master0_rvalid = tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign proc$master0_wready = tmp2_wNoSynth_buffer_ff$FULL_N ; + assign proc$master1_b_put_val = proc_uncached_bSynth_snk_putWire$wget ; + assign proc$master1_r_put_val = + { proc_uncached_rSynth_snk_putWire$wget[71:1], 1'd0 } ; assign proc$non_maskable_interrupt_req_set_not_clear = 1'd0 ; assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; @@ -8395,17 +10680,15 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 || EN_start ; - assign proc$master0_bvalid = CAN_FIRE_RL_tmp2_b_forwardFlit ; - assign proc$master0_rvalid = CAN_FIRE_RL_tmp2_r_forwardFlit ; - assign proc$master1_bvalid = CAN_FIRE_RL_tmp0_b_forwardFlit ; - assign proc$master1_rvalid = CAN_FIRE_RL_tmp0_r_forwardFlit ; + assign proc$EN_master1_aw_drop = + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; + assign proc$EN_master1_w_drop = + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; + assign proc$EN_master1_b_put = CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; + assign proc$EN_master1_ar_drop = + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; + assign proc$EN_master1_r_put = CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; assign proc$EN_set_verbosity = EN_set_verbosity ; - assign proc$debug_module_mem_server_awvalid = - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; - assign proc$debug_module_mem_server_wvalid = - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; - assign proc$debug_module_mem_server_arvalid = - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; assign proc$EN_hart0_run_halt_server_request_put = CAN_FIRE_RL_ClientServerRequest ; assign proc$EN_hart0_run_halt_server_response_get = @@ -8428,122 +10711,207 @@ module mkCoreW(RST_N_dm_power_on_reset, assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - // submodule ssNoSynth_0_ar_buffer_ff - assign ssNoSynth_0_ar_buffer_ff$D_IN = ssNoSynth_0_ar_buffer_enqw$wget ; - assign ssNoSynth_0_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; - assign ssNoSynth_0_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; - assign ssNoSynth_0_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_arNoSynth_buffer_ff + assign ssNoSynth_0_arNoSynth_buffer_ff$D_IN = + ssNoSynth_0_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_0_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; + assign ssNoSynth_0_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; + assign ssNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_ar_buffer_firstValid - assign ssNoSynth_0_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_ar_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + // submodule ssNoSynth_0_arNoSynth_buffer_firstValid + assign ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; - // submodule ssNoSynth_0_aw_buffer_ff - assign ssNoSynth_0_aw_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; - assign ssNoSynth_0_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; - assign ssNoSynth_0_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; - assign ssNoSynth_0_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_awNoSynth_buffer_ff + assign ssNoSynth_0_awNoSynth_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; + assign ssNoSynth_0_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; + assign ssNoSynth_0_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; + assign ssNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_aw_buffer_firstValid - assign ssNoSynth_0_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_aw_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + // submodule ssNoSynth_0_awNoSynth_buffer_firstValid + assign ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; - // submodule ssNoSynth_0_w_buffer_ff - assign ssNoSynth_0_w_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; - assign ssNoSynth_0_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; - assign ssNoSynth_0_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; - assign ssNoSynth_0_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_bNoSynth_buffer_ff + assign ssNoSynth_0_bNoSynth_buffer_ff$D_IN = uncached_mem_shim_bff$D_OUT ; + assign ssNoSynth_0_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; + assign ssNoSynth_0_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; + assign ssNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_w_buffer_firstValid - assign ssNoSynth_0_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_w_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit ; + // submodule ssNoSynth_0_bNoSynth_buffer_firstValid + assign ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_bNoSynth_buffer_firstValid$EN = + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_1_ar_buffer_ff - assign ssNoSynth_1_ar_buffer_ff$D_IN = ssNoSynth_1_ar_buffer_enqw$wget ; - assign ssNoSynth_1_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; - assign ssNoSynth_1_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; - assign ssNoSynth_1_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_rNoSynth_buffer_ff + assign ssNoSynth_0_rNoSynth_buffer_ff$D_IN = uncached_mem_shim_rff$D_OUT ; + assign ssNoSynth_0_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; + assign ssNoSynth_0_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; + assign ssNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_ar_buffer_firstValid - assign ssNoSynth_1_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_ar_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + // submodule ssNoSynth_0_rNoSynth_buffer_firstValid + assign ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_rNoSynth_buffer_firstValid$EN = + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_1_aw_buffer_ff - assign ssNoSynth_1_aw_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; - assign ssNoSynth_1_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; - assign ssNoSynth_1_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; - assign ssNoSynth_1_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_wNoSynth_buffer_ff + assign ssNoSynth_0_wNoSynth_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; + assign ssNoSynth_0_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; + assign ssNoSynth_0_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; + assign ssNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_aw_buffer_firstValid - assign ssNoSynth_1_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_aw_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + // submodule ssNoSynth_0_wNoSynth_buffer_firstValid + assign ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; - // submodule ssNoSynth_1_w_buffer_ff - assign ssNoSynth_1_w_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; - assign ssNoSynth_1_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; - assign ssNoSynth_1_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; - assign ssNoSynth_1_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_arNoSynth_buffer_ff + assign ssNoSynth_1_arNoSynth_buffer_ff$D_IN = + ssNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; + assign ssNoSynth_1_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; + assign ssNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_w_buffer_firstValid - assign ssNoSynth_1_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_w_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + // submodule ssNoSynth_1_arNoSynth_buffer_firstValid + assign ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; - // submodule ssNoSynth_2_ar_buffer_ff - assign ssNoSynth_2_ar_buffer_ff$D_IN = ssNoSynth_2_ar_buffer_enqw$wget ; - assign ssNoSynth_2_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; - assign ssNoSynth_2_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; - assign ssNoSynth_2_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_awNoSynth_buffer_ff + assign ssNoSynth_1_awNoSynth_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; + assign ssNoSynth_1_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; + assign ssNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_ar_buffer_firstValid - assign ssNoSynth_2_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_ar_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + // submodule ssNoSynth_1_awNoSynth_buffer_firstValid + assign ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; - // submodule ssNoSynth_2_aw_buffer_ff - assign ssNoSynth_2_aw_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; - assign ssNoSynth_2_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; - assign ssNoSynth_2_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; - assign ssNoSynth_2_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_bNoSynth_buffer_ff + assign ssNoSynth_1_bNoSynth_buffer_ff$D_IN = + ssNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; + assign ssNoSynth_1_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; + assign ssNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_aw_buffer_firstValid - assign ssNoSynth_2_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_aw_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + // submodule ssNoSynth_1_bNoSynth_buffer_firstValid + assign ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_bNoSynth_buffer_firstValid$EN = + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_2_w_buffer_ff - assign ssNoSynth_2_w_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; - assign ssNoSynth_2_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; - assign ssNoSynth_2_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; - assign ssNoSynth_2_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_rNoSynth_buffer_ff + assign ssNoSynth_1_rNoSynth_buffer_ff$D_IN = + ssNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; + assign ssNoSynth_1_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; + assign ssNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_w_buffer_firstValid - assign ssNoSynth_2_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_w_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + // submodule ssNoSynth_1_rNoSynth_buffer_firstValid + assign ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_rNoSynth_buffer_firstValid$EN = + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_1_wNoSynth_buffer_ff + assign ssNoSynth_1_wNoSynth_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; + assign ssNoSynth_1_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; + assign ssNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_wNoSynth_buffer_firstValid + assign ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_arNoSynth_buffer_ff + assign ssNoSynth_2_arNoSynth_buffer_ff$D_IN = + ssNoSynth_2_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; + assign ssNoSynth_2_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; + assign ssNoSynth_2_arNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_arNoSynth_buffer_firstValid + assign ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_awNoSynth_buffer_ff + assign ssNoSynth_2_awNoSynth_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; + assign ssNoSynth_2_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; + assign ssNoSynth_2_awNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_awNoSynth_buffer_firstValid + assign ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_bNoSynth_buffer_ff + assign ssNoSynth_2_bNoSynth_buffer_ff$D_IN = + ssNoSynth_2_bNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; + assign ssNoSynth_2_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; + assign ssNoSynth_2_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_bNoSynth_buffer_firstValid + assign ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_bNoSynth_buffer_firstValid$EN = + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_2_rNoSynth_buffer_ff + assign ssNoSynth_2_rNoSynth_buffer_ff$D_IN = + ssNoSynth_2_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; + assign ssNoSynth_2_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; + assign ssNoSynth_2_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_rNoSynth_buffer_firstValid + assign ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_rNoSynth_buffer_firstValid$EN = + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_2_wNoSynth_buffer_ff + assign ssNoSynth_2_wNoSynth_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; + assign ssNoSynth_2_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; + assign ssNoSynth_2_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_wNoSynth_buffer_firstValid + assign ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; // submodule tagController_tmp_awreqff assign tagController_tmp_awreqff$D_IN = @@ -8579,505 +10947,543 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite || WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; - // submodule tmp0_b_buffer_ff - assign tmp0_b_buffer_ff$D_IN = tmp0_b_buffer_enqw$wget ; - assign tmp0_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_b_buffer_enqueue ; - assign tmp0_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_b_buffer_dequeue ; - assign tmp0_b_buffer_ff$CLR = 1'b0 ; + // submodule tmp2_arNoSynth_buffer_ff + assign tmp2_arNoSynth_buffer_ff$D_IN = tmp2_arNoSynth_buffer_enqw$wget ; + assign tmp2_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; + assign tmp2_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; + assign tmp2_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp0_b_buffer_firstValid - assign tmp0_b_buffer_firstValid$D_IN = 1'd1 ; - assign tmp0_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_b_dropFlit ; + // submodule tmp2_arNoSynth_buffer_firstValid + assign tmp2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; - // submodule tmp0_r_buffer_ff - assign tmp0_r_buffer_ff$D_IN = tmp0_r_buffer_enqw$wget ; - assign tmp0_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_r_buffer_enqueue ; - assign tmp0_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_r_buffer_dequeue ; - assign tmp0_r_buffer_ff$CLR = 1'b0 ; + // submodule tmp2_awNoSynth_buffer_ff + assign tmp2_awNoSynth_buffer_ff$D_IN = tmp2_awNoSynth_buffer_enqw$wget ; + assign tmp2_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; + assign tmp2_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; + assign tmp2_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp0_r_buffer_firstValid - assign tmp0_r_buffer_firstValid$D_IN = 1'd1 ; - assign tmp0_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_r_dropFlit ; + // submodule tmp2_awNoSynth_buffer_firstValid + assign tmp2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; - // submodule tmp2_b_buffer_ff - assign tmp2_b_buffer_ff$D_IN = + // submodule tmp2_bNoSynth_buffer_ff + assign tmp2_bNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; - assign tmp2_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_b_buffer_enqueue ; - assign tmp2_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_b_buffer_dequeue ; - assign tmp2_b_buffer_ff$CLR = 1'b0 ; + assign tmp2_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; + assign tmp2_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; + assign tmp2_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp2_b_buffer_firstValid - assign tmp2_b_buffer_firstValid$D_IN = 1'd1 ; - assign tmp2_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_b_dropFlit ; + // submodule tmp2_bNoSynth_buffer_firstValid + assign tmp2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; - // submodule tmp2_r_buffer_ff - assign tmp2_r_buffer_ff$D_IN = + // submodule tmp2_rNoSynth_buffer_ff + assign tmp2_rNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; - assign tmp2_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_r_buffer_enqueue ; - assign tmp2_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_r_buffer_dequeue ; - assign tmp2_r_buffer_ff$CLR = 1'b0 ; + assign tmp2_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; + assign tmp2_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; + assign tmp2_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp2_r_buffer_firstValid - assign tmp2_r_buffer_firstValid$D_IN = 1'd1 ; - assign tmp2_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_r_dropFlit ; + // submodule tmp2_rNoSynth_buffer_firstValid + assign tmp2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; + + // submodule tmp2_wNoSynth_buffer_ff + assign tmp2_wNoSynth_buffer_ff$D_IN = tmp2_wNoSynth_buffer_enqw$wget ; + assign tmp2_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; + assign tmp2_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; + assign tmp2_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule tmp2_wNoSynth_buffer_firstValid + assign tmp2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; // submodule uncached_mem_shim_arff assign uncached_mem_shim_arff$D_IN = - ssNoSynth_0_ar_buffer_ff$EMPTY_N ? - ssNoSynth_0_ar_buffer_ff$D_OUT : - ssNoSynth_0_ar_buffer_enqw$wget ; + slave_vector_0_arSynth_snk_putWire$wget ; assign uncached_mem_shim_arff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit && - uncached_mem_shim_arff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; assign uncached_mem_shim_arff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; assign uncached_mem_shim_arff$CLR = 1'b0 ; // submodule uncached_mem_shim_awff assign uncached_mem_shim_awff$D_IN = - ssNoSynth_0_aw_buffer_ff$EMPTY_N ? - ssNoSynth_0_aw_buffer_ff$D_OUT : - split_0_doPut$wget[171:74] ; + slave_vector_0_awSynth_snk_putWire$wget ; assign uncached_mem_shim_awff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit && - uncached_mem_shim_awff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; assign uncached_mem_shim_awff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; assign uncached_mem_shim_awff$CLR = 1'b0 ; // submodule uncached_mem_shim_bff assign uncached_mem_shim_bff$D_IN = - ug_uncached_mem_shim_master_u_b_putWire$wget[6:0] ; + uncached_mem_master_bSynth_snk_putWire$wget[6:0] ; assign uncached_mem_shim_bff$ENQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; assign uncached_mem_shim_bff$DEQ = - uncached_mem_shim_bff$EMPTY_N && ssNoSynth_0_b_dwReady$whas ; + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; assign uncached_mem_shim_bff$CLR = 1'b0 ; // submodule uncached_mem_shim_rff assign uncached_mem_shim_rff$D_IN = - { ug_uncached_mem_shim_master_u_r_putWire$wget[71:0], 1'd0 } ; + { uncached_mem_master_rSynth_snk_putWire$wget[71:0], 1'd0 } ; assign uncached_mem_shim_rff$ENQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; assign uncached_mem_shim_rff$DEQ = - uncached_mem_shim_rff$EMPTY_N && ssNoSynth_0_r_dwReady$whas ; + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; assign uncached_mem_shim_rff$CLR = 1'b0 ; // submodule uncached_mem_shim_wff - assign uncached_mem_shim_wff$D_IN = - ssNoSynth_0_w_buffer_ff$EMPTY_N ? - ssNoSynth_0_w_buffer_ff$D_OUT : - split_0_doPut$wget[73:0] ; + assign uncached_mem_shim_wff$D_IN = slave_vector_0_wSynth_snk_putWire$wget ; assign uncached_mem_shim_wff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit && - uncached_mem_shim_wff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; assign uncached_mem_shim_wff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; assign uncached_mem_shim_wff$CLR = 1'b0 ; // remaining internal signals - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207 = - ((IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203)) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 = + ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527)) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211 = - ((IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 = + ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 = - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207 + - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211 + - ((!IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 = + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 + + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 + + ((!IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) ? 2'd1 : 2'd0) ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306 = - ((IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302)) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 = + ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621)) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310 = - ((IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 = + ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 = - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306 + - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310 + - ((!IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 = + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 + + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 + + ((!IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) ? 2'd1 : 2'd0) ; - assign IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 = + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 = + ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 = + ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 = + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 + + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 + + ((!IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) ? + 2'd1 : + 2'd0) ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 = + ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 = + ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 = + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 + + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 + + ((!IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) ? + 2'd1 : + 2'd0) ; + assign IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 = (!ifcs_0_1_innerRoute$D_OUT[1] || - !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_innerRoute$D_OUT[2] && - ssNoSynth_2_ar_buffer_ff$FULL_N : + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_0_1_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 = + assign IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 = (!ifcs_0_innerRoute$D_OUT[1] || - !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426) ? + !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_0_innerRoute$D_OUT[2] && - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 : + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_0_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 = + assign IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 = (!ifcs_1_1_innerRoute$D_OUT[1] || - !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_innerRoute$D_OUT[2] && - ssNoSynth_2_ar_buffer_ff$FULL_N : + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_1_1_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 = + assign IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 = (!ifcs_1_innerRoute$D_OUT[1] || - !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426) ? + !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_1_innerRoute$D_OUT[2] && - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 : + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_1_innerRoute$D_OUT[1] ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94630 | y__h94631 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118613 | y__h118614 : arbiter_1_1_lastSelect ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94818 | y__h94819 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118801 | y__h118802 : arbiter_1_1_lastSelect_1 ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94999 | y__h95000 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118982 | y__h118983 : arbiter_1_1_firstHot ; - assign IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 = - (SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 || - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) ? - x__h82688 | y__h82689 : - arbiter_1_lastSelect_2 ; - assign IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 = - (SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 || - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) ? - x__h82829 | y__h82830 : - arbiter_1_firstHot_1 ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63404 | y__h63405 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85339 | y__h85340 : arbiter_1_lastSelect ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63592 | y__h63593 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85527 | y__h85528 : arbiter_1_lastSelect_1 ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63773 | y__h63774 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85708 | y__h85709 : arbiter_1_firstHot ; - assign IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 = - (SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 || - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) ? - x__h48921 | y__h48922 : + assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 = + (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? + x__h106164 | y__h106165 : + arbiter_1_lastSelect_2 ; + assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 = + (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? + x__h106305 | y__h106306 : + arbiter_1_firstHot_1 ; + assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 = + (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? + x__h70391 | y__h70392 : arbiter_lastSelect ; - assign IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 = - (SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 || - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) ? - x__h49062 | y__h49063 : + assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 = + (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? + x__h70532 | y__h70533 : arbiter_firstHot ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941 = - ((debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937)) ? - 2'd1 : - 2'd0 ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945 = - ((debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937) ? - 2'd1 : - 2'd0 ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 = - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941 + - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945 + - ((!debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) ? - 2'd1 : - 2'd0) ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 = - ((merged_0_flitLeft == 8'd0) ? - !proc$master1_awvalid || !proc$master1_wvalid : - !proc$master1_wvalid) || - merged_0_flitLeft != 8'd0 ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250 = - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && - (merged_0_flitLeft != 8'd0 || - !ifcs_0_noRoute_inner_pendingReq && proc$master1_awvalid) ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 = + assign IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 = (merged_0_flitLeft == 8'd0) ? - proc$master1_awvalid && proc$master1_wvalid : - proc$master1_wvalid ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 = - proc$master1_awaddr < + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N : + merged_0_wff$EMPTY_N ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 = + merged_0_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195 = - x__h37445 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 = - proc$master1_awaddr < soc_map$m_plic_addr_range[127:64] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203 = - x__h37480 < soc_map$m_plic_addr_range[63:0] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 = - ((merged_1_flitLeft == 8'd0) ? - !debug_module$master_awvalid || !debug_module$master_wvalid : - !debug_module$master_wvalid) || - merged_1_flitLeft != 8'd0 ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350 = - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - (merged_1_flitLeft != 8'd0 || - !ifcs_1_noRoute_inner_pendingReq && - debug_module$master_awvalid) ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 = + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519 = + x__h56232 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 = + merged_0_outflit$wget[166:103] < + soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527 = + x__h56267 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 = + (CAN_FIRE_RL_merged_0_passFlit && !merged_0_outflit$wget[171]) ? + { 1'd0, merged_0_outflit$wget[170:0] } : + { 98'h2AAAAAAAAAAAAAAAAAAAAAAAA, + CAN_FIRE_RL_merged_0_passFlit ? + merged_0_outflit$wget[73:0] : + merged_0_wff$D_OUT } ; + assign IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 = + CAN_FIRE_RL_merged_0_passFlit ? + !merged_0_outflit$wget[1] : + !merged_0_wff$D_OUT[1] ; + assign IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 = + CAN_FIRE_RL_merged_0_passFlit ? + merged_0_outflit$wget[1] : + merged_0_wff$D_OUT[1] ; + assign IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 = (merged_1_flitLeft == 8'd0) ? - debug_module$master_awvalid && debug_module$master_wvalid : - debug_module$master_wvalid ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 = - debug_module$master_awaddr < + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N : + merged_1_wff$EMPTY_N ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 = + merged_1_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297 = - x__h40162 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 = - debug_module$master_awaddr < soc_map$m_plic_addr_range[127:64] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 = - x__h40187 < soc_map$m_plic_addr_range[63:0] ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854 = - ((proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - (proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850)) ? - 2'd1 : - 2'd0 ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858 = - ((proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - !proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850) ? - 2'd1 : - 2'd0 ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 = - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854 + - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858 + - ((!proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) ? - 2'd1 : - 2'd0) ; - assign IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425 = + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616 = + x__h59744 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 = + merged_1_outflit$wget[166:103] < + soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621 = + x__h59769 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 = + (CAN_FIRE_RL_merged_1_passFlit && !merged_1_outflit$wget[171]) ? + { 1'd1, merged_1_outflit$wget[170:0] } : + { 98'h2AAAAAAAAAAAAAAAAAAAAAAAA, + CAN_FIRE_RL_merged_1_passFlit ? + merged_1_outflit$wget[73:0] : + merged_1_wff$D_OUT } ; + assign IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 = + CAN_FIRE_RL_merged_1_passFlit ? + !merged_1_outflit$wget[1] : + !merged_1_wff$D_OUT[1] ; + assign IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 = + CAN_FIRE_RL_merged_1_passFlit ? + merged_1_outflit$wget[1] : + merged_1_wff$D_OUT[1] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 = + addr__h93758 < soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218 = + x__h93834 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 = + addr__h93758 < soc_map$m_plic_addr_range[127:64] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223 = + x__h93859 < soc_map$m_plic_addr_range[63:0] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 = + addr__h96375 < soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313 = + x__h96451 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 = + addr__h96375 < soc_map$m_plic_addr_range[127:64] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318 = + x__h96476 < soc_map$m_plic_addr_range[63:0] ; + assign IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 = (split_0_flitLeft == 8'd0) ? - ssNoSynth_0_aw_buffer_ff$FULL_N && - ssNoSynth_0_w_buffer_ff$FULL_N : - ssNoSynth_0_w_buffer_ff$FULL_N ; - assign IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426 = + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 = (split_1_flitLeft == 8'd0) ? - ssNoSynth_1_aw_buffer_ff$FULL_N && - ssNoSynth_1_w_buffer_ff$FULL_N : - ssNoSynth_1_w_buffer_ff$FULL_N ; - assign IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 = + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 = (split_2_flitLeft == 8'd0) ? - ssNoSynth_2_aw_buffer_ff$FULL_N && - ssNoSynth_2_w_buffer_ff$FULL_N : - ssNoSynth_2_w_buffer_ff$FULL_N ; - assign SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22 = - {2{SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331}} ; - assign SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17 = - {2{SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138}} ; - assign SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12 = - {2{SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698}} ; - assign SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7 = - {2{SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495}} ; - assign SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 = - x__h94158 | y__h94159 ; + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N ; + assign SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22 = + {2{SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750}} ; + assign SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12 = + {2{SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059}} ; + assign SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17 = + {2{SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553}} ; + assign SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7 = + {2{SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852}} ; + assign SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 = + x__h118141 | y__h118142 ; assign SEXT_arbiter_1_1_firstHot__q19 = {2{arbiter_1_1_firstHot}} ; - assign SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 = - x__h94022 | y__h94023 ; + assign SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 = + x__h118005 | y__h118006 ; assign SEXT_arbiter_1_1_lastSelect_1__q21 = {2{arbiter_1_1_lastSelect_1}} ; - assign SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 = - x__h93871 | y__h93872 ; + assign SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 = + x__h117854 | y__h117855 ; assign SEXT_arbiter_1_1_lastSelect__q20 = {2{arbiter_1_1_lastSelect}} ; - assign SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138 = - x__h82323 | y__h82324 ; + assign SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 = + x__h84867 | y__h84868 ; + assign SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 = + x__h105799 | y__h105800 ; assign SEXT_arbiter_1_firstHot_1__q15 = {2{arbiter_1_firstHot_1}} ; - assign SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 = - x__h62932 | y__h62933 ; assign SEXT_arbiter_1_firstHot__q9 = {2{arbiter_1_firstHot}} ; - assign SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 = - x__h62796 | y__h62797 ; + assign SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 = + x__h84580 | y__h84581 ; + assign SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 = + x__h84731 | y__h84732 ; assign SEXT_arbiter_1_lastSelect_1__q11 = {2{arbiter_1_lastSelect_1}} ; - assign SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 = - x__h82220 | y__h82221 ; + assign SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 = + x__h105696 | y__h105697 ; assign SEXT_arbiter_1_lastSelect_2__q16 = {2{arbiter_1_lastSelect_2}} ; - assign SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 = - x__h62645 | y__h62646 ; assign SEXT_arbiter_1_lastSelect__q10 = {2{arbiter_1_lastSelect}} ; - assign SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495 = - x__h48556 | y__h48557 ; + assign SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 = + x__h70026 | y__h70027 ; assign SEXT_arbiter_firstHot__q5 = {2{arbiter_firstHot}} ; - assign SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 = - x__h48453 | y__h48454 ; + assign SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 = + x__h69923 | y__h69924 ; assign SEXT_arbiter_lastSelect__q6 = {2{arbiter_lastSelect}} ; - assign SEXT_x2747__q18 = {2{x__h82747}} ; - assign SEXT_x3466__q13 = {2{x__h63466}} ; - assign SEXT_x3500__q14 = {2{x__h63500}} ; - assign SEXT_x4692__q23 = {2{x__h94692}} ; - assign SEXT_x4726__q24 = {2{x__h94726}} ; - assign SEXT_x8980__q8 = {2{x__h48980}} ; - assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245 = - x__h12617 + y__h12618 ; - assign a_awid__h38523 = { 1'd0, proc$master1_awid } ; - assign a_awid__h41194 = { 1'd1, debug_module$master_awid } ; - assign araddr__h15540 = + assign SEXT_x0450__q8 = {2{x__h70450}} ; + assign SEXT_x06223__q18 = {2{x__h106223}} ; + assign SEXT_x18675__q23 = {2{x__h118675}} ; + assign SEXT_x18709__q24 = {2{x__h118709}} ; + assign SEXT_x5401__q13 = {2{x__h85401}} ; + assign SEXT_x5435__q14 = {2{x__h85435}} ; + assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224 = + x__h12420 + y__h12421 ; + assign addr__h93758 = + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:29] : + proc$master1_ar_peek[92:29] ; + assign addr__h96375 = + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:29] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[92:29] ; + assign araddr__h15343 = { 24'd0, tagController_tmp_tagCon$memory_request_get[140:101] } ; - assign arcache__h15545 = + assign arcache__h15348 = tagController_tmp_tagCon$memory_request_get[8] ? 4'd0 : 4'd15 ; - assign arlen__h15541 = + assign arlen__h15344 = { 5'd0, tagController_tmp_tagCon$memory_request_get[5:3] } ; - assign aw_awaddr__h10808 = tmp__h10591 + { 60'd0, x__h10883 } ; - assign aw_awsize_val__h12547 = - _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[0] ? + assign aw_awaddr__h10611 = tmp__h10394 + { 60'd0, x__h10686 } ; + assign aw_awsize_val__h12350 = + _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[0] ? 3'd0 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[1] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[1] ? 3'd1 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[2] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[2] ? 3'd2 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[3] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[3] ? 3'd3 : 3'd4))) ; - assign debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932 = - x__h74126 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937 = - x__h74151 < soc_map$m_plic_addr_range[63:0] ; - assign debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 = - debug_module$master_araddr < - soc_map$m_mem0_controller_addr_range[127:64] ; - assign debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 = - debug_module$master_araddr < soc_map$m_plic_addr_range[127:64] ; - assign fatReq_arid__h72223 = { 1'd0, proc$master1_arid } ; - assign fatReq_arid__h74597 = { 1'd1, debug_module$master_arid } ; - assign proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845 = - x__h71737 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850 = - x__h71762 < soc_map$m_plic_addr_range[63:0] ; - assign proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 = - proc$master1_araddr < - soc_map$m_mem0_controller_addr_range[127:64] ; - assign proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 = - proc$master1_araddr < soc_map$m_plic_addr_range[127:64] ; - assign reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669 = + assign fatReq_arid__h94342 = + { 1'd0, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[96:93] : + proc$master1_ar_peek[96:93] } ; + assign fatReq_arid__h96944 = + { 1'd1, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[96:93] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[96:93] } ; + assign reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 = CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget || CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget || CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget ; - assign reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302 = + assign reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 = CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget || CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget || CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget ; - assign split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 = - CAN_FIRE_RL_sink_selected && + assign split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 = + CAN_FIRE_RL_sinks_0_doPut && (split_0_doPut$wget[172] || - ssNoSynth_0_aw_buffer_ff$FULL_N && - ssNoSynth_0_w_buffer_ff$FULL_N) ; - assign split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 = - CAN_FIRE_RL_sink_selected_1 && + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; + assign split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 = + CAN_FIRE_RL_sinks_1_doPut && (split_1_doPut$wget[172] || - ssNoSynth_1_aw_buffer_ff$FULL_N && - ssNoSynth_1_w_buffer_ff$FULL_N) ; - assign split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 = - CAN_FIRE_RL_sink_selected_2 && + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; + assign split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 = + CAN_FIRE_RL_sinks_2_doPut && (split_2_doPut$wget[172] || - ssNoSynth_2_aw_buffer_ff$FULL_N && - ssNoSynth_2_w_buffer_ff$FULL_N) ; - assign state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193 = - state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && - ((!ifcs_0_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 : - ifcs_0_1_innerRoute$D_OUT[0]) ; - assign state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233 = - state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && - ((!ifcs_1_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 : - ifcs_1_1_innerRoute$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400 = + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; + assign state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 = + state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && + ((!ifcs_0_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_0_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_0_routeBack$D_OUT[0]) ; + assign state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 = + state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && + ((!ifcs_1_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_1_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_1_routeBack$D_OUT[0]) ; + assign state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 = + state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && + ((!ifcs_2_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_2_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_2_routeBack$D_OUT[0]) ; + assign state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 = state_1_1_1 && activeSource_1_1_0 && ifcs_0_1_routeBack$EMPTY_N && ((!ifcs_0_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436 = + assign state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 = state_1_1_1 && activeSource_1_1_1_1 && ifcs_1_1_routeBack$EMPTY_N && ((!ifcs_1_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472 = + assign state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 = state_1_1_1 && activeSource_1_1_2 && ifcs_2_1_routeBack$EMPTY_N && ((!ifcs_2_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761 = - state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && - ((!ifcs_0_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_0_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_0_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794 = - state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && - ((!ifcs_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_1_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828 = - state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && - ((!ifcs_2_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_2_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_2_routeBack$D_OUT[0]) ; - assign state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556 = + assign state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 = + state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && + ((!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : + ifcs_0_1_innerRoute$D_OUT[0]) ; + assign state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 = + state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && + ((!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : + ifcs_1_1_innerRoute$D_OUT[0]) ; + assign state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 = state && activeSource_0 && ifcs_0_innerRoute$EMPTY_N && ((!ifcs_0_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0]) ; - assign state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600 = + assign state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 = state && activeSource_1 && ifcs_1_innerRoute$EMPTY_N && ((!ifcs_1_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0]) ; assign tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4 = tagController_tmp_shimMaster_arff_rv$port1__read[98:0] ; @@ -9085,31 +11491,48 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_awff_rv$port1__read[98:0] ; assign tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3 = tagController_tmp_shimMaster_wff_rv$port1__read[72:0] ; - assign tmp__h10591 = { 24'd0, x__h10840 } ; - assign tmp__h8366 = + assign tmp__h10394 = { 24'd0, x__h10643 } ; + assign tmp__h8169 = tagController_tmp_awreqff$D_OUT[92:29] + tagController_tmp_addrOffset ; assign uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1 = uncached_mem_shim_wff$D_OUT[73:1] ; - assign v_araddr__h15557 = + assign v_araddr__h15360 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - araddr__h15540 : + araddr__h15343 : 64'hAAAAAAAAAAAAAAAA ; - assign v_arid__h15556 = + assign v_arid__h15359 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[100:95] : 6'd0 ; - assign v_arlen__h15558 = + assign v_arlen__h15361 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - arlen__h15541 : + arlen__h15344 : 8'd0 ; - assign v_arsize_val__h15603 = + assign v_arsize_val__h15406 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[2:0] : 3'b0 ; - assign x__h10840 = + assign x__h100325 = + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[72:68] : + ssNoSynth_2_rNoSynth_buffer_enqw$wget[72:68] ; + assign x__h105696 = + SEXT_arbiter_1_lastSelect_2__q16[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h105799 = + SEXT_arbiter_1_firstHot_1__q15[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h106164 = + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & + arbiter_1_firstHot_1 ; + assign x__h106223 = + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 && + SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 ; + assign x__h106305 = SEXT_x06223__q18[0] & arbiter_1_firstHot_1 ; + assign x__h10643 = { tagController_tmp_tagCon$memory_request_get[140:104], 3'd0 } ; - assign x__h10883 = + assign x__h10686 = tagController_tmp_tagCon$memory_request_get[81] ? 4'd0 : (tagController_tmp_tagCon$memory_request_get[82] ? @@ -9127,227 +11550,234 @@ module mkCoreW(RST_N_dm_power_on_reset, (tagController_tmp_tagCon$memory_request_get[88] ? 4'd7 : 4'd8))))))) ; - assign x__h12617 = x__h12629 + y__h12630 ; - assign x__h12629 = x__h12641 + y__h12642 ; - assign x__h12641 = x__h12653 + y__h12654 ; - assign x__h12653 = x__h12665 + y__h12666 ; - assign x__h12665 = x__h12677 + y__h12678 ; - assign x__h12677 = x__h12689 + y__h12690 ; - assign x__h12689 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; - assign x__h14213 = - tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; - assign x__h15621 = - (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - arcache__h15545 : - 4'd0 ; - assign x__h37445 = - proc$master1_awaddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h37480 = proc$master1_awaddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h40162 = - debug_module$master_awaddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h40187 = - debug_module$master_awaddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h48453 = - SEXT_arbiter_lastSelect__q6[0] & - (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; - assign x__h48556 = - SEXT_arbiter_firstHot__q5[0] & - (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; - assign x__h48921 = - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7[0] & - arbiter_firstHot ; - assign x__h48980 = - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495 && - SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 ; - assign x__h49062 = SEXT_x8980__q8[0] & arbiter_firstHot ; - assign x__h62645 = x__h62647 | y__h62648 ; - assign x__h62647 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h62796 = x__h62798 | y__h62799 ; - assign x__h62798 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h62932 = x__h62934 | y__h62935 ; - assign x__h62934 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h63404 = x__h63406 | y__h63407 ; - assign x__h63406 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_firstHot ; - assign x__h63466 = - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 && - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 ; - assign x__h63500 = - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 && - SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 ; - assign x__h63592 = x__h63594 | y__h63595 ; - assign x__h63594 = SEXT_x3466__q13[0] & arbiter_1_firstHot ; - assign x__h63773 = x__h63775 | y__h63776 ; - assign x__h63775 = SEXT_x3500__q14[0] & arbiter_1_firstHot ; - assign x__h71737 = - proc$master1_araddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h71762 = proc$master1_araddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h74126 = - debug_module$master_araddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h74151 = - debug_module$master_araddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h8207 = - tagController_tmp_addrOffset + - (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; - assign x__h82220 = - SEXT_arbiter_1_lastSelect_2__q16[0] & - (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; - assign x__h82323 = - SEXT_arbiter_1_firstHot_1__q15[0] & - (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; - assign x__h82688 = - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17[0] & - arbiter_1_firstHot_1 ; - assign x__h82747 = - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138 && - SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 ; - assign x__h82829 = SEXT_x2747__q18[0] & arbiter_1_firstHot_1 ; - assign x__h93871 = x__h93873 | y__h93874 ; - assign x__h93873 = + assign x__h117854 = x__h117856 | y__h117857 ; + assign x__h117856 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94022 = x__h94024 | y__h94025 ; - assign x__h94024 = + assign x__h118005 = x__h118007 | y__h118008 ; + assign x__h118007 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94158 = x__h94160 | y__h94161 ; - assign x__h94160 = + assign x__h118141 = x__h118143 | y__h118144 ; + assign x__h118143 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94630 = x__h94632 | y__h94633 ; - assign x__h94632 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign x__h118613 = x__h118615 | y__h118616 ; + assign x__h118615 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_firstHot ; - assign x__h94692 = - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 && - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 ; - assign x__h94726 = - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 && - SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 ; - assign x__h94818 = x__h94820 | y__h94821 ; - assign x__h94820 = SEXT_x4692__q23[0] & arbiter_1_1_firstHot ; - assign x__h94999 = x__h95001 | y__h95002 ; - assign x__h95001 = SEXT_x4726__q24[0] & arbiter_1_1_firstHot ; - assign x_port1__read__h72781 = + assign x__h118675 = + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 ; + assign x__h118709 = + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && + SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 ; + assign x__h118801 = x__h118803 | y__h118804 ; + assign x__h118803 = SEXT_x18675__q23[0] & arbiter_1_1_firstHot ; + assign x__h118982 = x__h118984 | y__h118985 ; + assign x__h118984 = SEXT_x18709__q24[0] & arbiter_1_1_firstHot ; + assign x__h12420 = x__h12432 + y__h12433 ; + assign x__h12432 = x__h12444 + y__h12445 ; + assign x__h12444 = x__h12456 + y__h12457 ; + assign x__h12456 = x__h12468 + y__h12469 ; + assign x__h12468 = x__h12480 + y__h12481 ; + assign x__h12480 = x__h12492 + y__h12493 ; + assign x__h12492 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; + assign x__h14016 = + tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; + assign x__h15424 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + arcache__h15348 : + 4'd0 ; + assign x__h56232 = + merged_0_outflit$wget[166:103] - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h56267 = + merged_0_outflit$wget[166:103] - + soc_map$m_plic_addr_range[127:64] ; + assign x__h59744 = + merged_1_outflit$wget[166:103] - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h59769 = + merged_1_outflit$wget[166:103] - + soc_map$m_plic_addr_range[127:64] ; + assign x__h62625 = + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[6:2] : + uncached_mem_shim_bff$D_OUT[6:2] ; + assign x__h63516 = + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[6:2] : + ssNoSynth_1_bNoSynth_buffer_enqw$wget[6:2] ; + assign x__h64407 = + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[6:2] : + ssNoSynth_2_bNoSynth_buffer_enqw$wget[6:2] ; + assign x__h69923 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h70026 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h70391 = + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & + arbiter_firstHot ; + assign x__h70450 = + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 && + SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 ; + assign x__h70532 = SEXT_x0450__q8[0] & arbiter_firstHot ; + assign x__h8010 = + tagController_tmp_addrOffset + + (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; + assign x__h84580 = x__h84582 | y__h84583 ; + assign x__h84582 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h84731 = x__h84733 | y__h84734 ; + assign x__h84733 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h84867 = x__h84869 | y__h84870 ; + assign x__h84869 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h85339 = x__h85341 | y__h85342 ; + assign x__h85341 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_firstHot ; + assign x__h85401 = + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 ; + assign x__h85435 = + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && + SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 ; + assign x__h85527 = x__h85529 | y__h85530 ; + assign x__h85529 = SEXT_x5401__q13[0] & arbiter_1_firstHot ; + assign x__h85708 = x__h85710 | y__h85711 ; + assign x__h85710 = SEXT_x5435__q14[0] & arbiter_1_firstHot ; + assign x__h93834 = + addr__h93758 - soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h93859 = addr__h93758 - soc_map$m_plic_addr_range[127:64] ; + assign x__h94920 = + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[28:21] : + proc$master1_ar_peek[28:21] ; + assign x__h95023 = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? ifcs_0_1_noRoute_flitCount$port0__write_1 : ifcs_0_1_noRoute_flitCount ; - assign x_port1__read__h75154 = + assign x__h96451 = + addr__h96375 - soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h96476 = addr__h96375 - soc_map$m_plic_addr_range[127:64] ; + assign x__h97519 = + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[28:21] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[28:21] ; + assign x__h97622 = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? ifcs_1_1_noRoute_flitCount$port0__write_1 : ifcs_1_1_noRoute_flitCount ; - assign x_rdata__h25045 = - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[67:4] : - msNoSynth_0_r_buffer_enqw$wget[67:4] ; - assign x_rid__h25044 = - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[71:68] : - msNoSynth_0_r_buffer_enqw$wget[71:68] ; - assign y__h12618 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; - assign y__h12630 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; - assign y__h12642 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; - assign y__h12654 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; - assign y__h12666 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; - assign y__h12678 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; - assign y__h12690 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; - assign y__h48454 = - SEXT_arbiter_firstHot__q5[0] & - (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; - assign y__h48557 = - SEXT_arbiter_lastSelect__q6[0] & - (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; - assign y__h48922 = SEXT_x8980__q8[0] & arbiter_lastSelect ; - assign y__h49063 = - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7[0] & - arbiter_lastSelect ; - assign y__h62646 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62648 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h62797 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62799 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h62933 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62935 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h63405 = SEXT_x3500__q14[0] & arbiter_1_lastSelect ; - assign y__h63407 = SEXT_x3466__q13[0] & arbiter_1_lastSelect_1 ; - assign y__h63593 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_lastSelect ; - assign y__h63595 = SEXT_x3500__q14[0] & arbiter_1_lastSelect_1 ; - assign y__h63774 = SEXT_x3466__q13[0] & arbiter_1_lastSelect ; - assign y__h63776 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_lastSelect_1 ; - assign y__h82221 = + assign x__h98415 = + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[72:68] : + uncached_mem_shim_rff$D_OUT[72:68] ; + assign x__h99370 = + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[72:68] : + ssNoSynth_1_rNoSynth_buffer_enqw$wget[72:68] ; + assign y__h105697 = SEXT_arbiter_1_firstHot_1__q15[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; - assign y__h82324 = + assign y__h105800 = SEXT_arbiter_1_lastSelect_2__q16[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; - assign y__h82689 = SEXT_x2747__q18[0] & arbiter_1_lastSelect_2 ; - assign y__h82830 = - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17[0] & + assign y__h106165 = SEXT_x06223__q18[0] & arbiter_1_lastSelect_2 ; + assign y__h106306 = + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & arbiter_1_lastSelect_2 ; - assign y__h93872 = + assign y__h117855 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h93874 = + assign y__h117857 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94023 = + assign y__h118006 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h94025 = + assign y__h118008 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94159 = + assign y__h118142 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h94161 = + assign y__h118144 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94631 = SEXT_x4726__q24[0] & arbiter_1_1_lastSelect ; - assign y__h94633 = SEXT_x4692__q23[0] & arbiter_1_1_lastSelect_1 ; - assign y__h94819 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign y__h118614 = SEXT_x18709__q24[0] & arbiter_1_1_lastSelect ; + assign y__h118616 = SEXT_x18675__q23[0] & arbiter_1_1_lastSelect_1 ; + assign y__h118802 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect ; - assign y__h94821 = SEXT_x4726__q24[0] & arbiter_1_1_lastSelect_1 ; - assign y__h95000 = SEXT_x4692__q23[0] & arbiter_1_1_lastSelect ; - assign y__h95002 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign y__h118804 = SEXT_x18709__q24[0] & arbiter_1_1_lastSelect_1 ; + assign y__h118983 = SEXT_x18675__q23[0] & arbiter_1_1_lastSelect ; + assign y__h118985 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect_1 ; + assign y__h12421 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; + assign y__h12433 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; + assign y__h12445 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; + assign y__h12457 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; + assign y__h12469 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; + assign y__h12481 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; + assign y__h12493 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; + assign y__h69924 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h70027 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h70392 = SEXT_x0450__q8[0] & arbiter_lastSelect ; + assign y__h70533 = + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & + arbiter_lastSelect ; + assign y__h84581 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84583 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h84732 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84734 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h84868 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84870 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h85340 = SEXT_x5435__q14[0] & arbiter_1_lastSelect ; + assign y__h85342 = SEXT_x5401__q13[0] & arbiter_1_lastSelect_1 ; + assign y__h85528 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_lastSelect ; + assign y__h85530 = SEXT_x5435__q14[0] & arbiter_1_lastSelect_1 ; + assign y__h85709 = SEXT_x5401__q13[0] & arbiter_1_lastSelect ; + assign y__h85711 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_lastSelect_1 ; // handling of inlined registers @@ -9677,15 +12107,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h22825 = $stime; + v__h27371 = $stime; #0; end - v__h22819 = v__h22825 / 32'd10; + v__h27365 = v__h27371 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h22819, + v__h27365, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -9693,29 +12123,29 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h22968 = $stime; + v__h27514 = $stime; #0; end - v__h22962 = v__h22968 / 32'd10; + v__h27508 = v__h27514 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h22962, + v__h27508, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && - !SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 && - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) + !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && - !SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 && - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) + !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && @@ -9724,7 +12154,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h50461 = $time; + v__h71925 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -9734,7 +12164,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h50461, + v__h71925, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && @@ -9843,13 +12273,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) begin - v__h49850 = $time; + v__h71314 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h49850, + v__h71314, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) @@ -9861,7 +12291,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h54470 = $time; + v__h75934 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -9871,7 +12301,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h54470, + v__h75934, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && @@ -9980,13 +12410,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) begin - v__h53859 = $time; + v__h75323 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h53859, + v__h75323, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) @@ -10008,15 +12438,352 @@ module mkCoreW(RST_N_dm_power_on_reset, if ((WILL_FIRE_RL_sink_selected || WILL_FIRE_RL_sink_selected_1) && WILL_FIRE_RL_sink_selected_2) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected,\n RL_sink_selected_1] and [RL_sink_selected_2] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h87100 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h87100, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + begin + v__h86719 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h86719, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h89170 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h89170, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + begin + v__h88789 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h88789, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h91069 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h91069, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + begin + v__h90688 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h90688, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && + (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || + WILL_FIRE_RL_source_selected_3 || + WILL_FIRE_RL_burst_3) && + (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && - !SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 && - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) + !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && - !SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 && - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) + !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && @@ -10025,7 +12792,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h84222 = $time; + v__h107698 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10035,7 +12802,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h84222, + v__h107698, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && @@ -10144,13 +12911,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) begin - v__h83611 = $time; + v__h107087 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h83611, + v__h107087, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) @@ -10162,7 +12929,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h87115 = $time; + v__h110591 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10172,7 +12939,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h87115, + v__h110591, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && @@ -10281,13 +13048,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) begin - v__h86504 = $time; + v__h109980 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h86504, + v__h109980, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) @@ -10309,575 +13076,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if ((WILL_FIRE_RL_sink_selected_5 || WILL_FIRE_RL_sink_selected_6) && WILL_FIRE_RL_sink_selected_7) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5,\n RL_sink_selected_6] and [RL_sink_selected_7] ) fired in the same clock\n cycle.\n"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - split_0_doPut$wget[1] && - split_0_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - split_0_doPut$wget[1] && - split_0_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - !split_0_doPut$wget[1] && - split_0_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - !split_0_doPut$wget[1] && - split_0_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - split_1_doPut$wget[1] && - split_1_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - split_1_doPut$wget[1] && - split_1_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - !split_1_doPut$wget[1] && - split_1_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - !split_1_doPut$wget[1] && - split_1_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - split_2_doPut$wget[1] && - split_2_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - split_2_doPut$wget[1] && - split_2_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - !split_2_doPut$wget[1] && - split_2_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - !split_2_doPut$wget[1] && - split_2_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_arbitrate_1 && - !SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 && - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) - $display("mkOneHotArbiter: next method should not be run with no pending request"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_arbitrate_1 && - !SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 && - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h65165 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h65165, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - begin - v__h64784 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h64784, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h67235 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h67235, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - begin - v__h66854 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h66854, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h69134 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h69134, - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - begin - v__h68753 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h68753, - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && - (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || - WILL_FIRE_RL_source_selected_3 || - WILL_FIRE_RL_burst_3) && - (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && - WILL_FIRE_RL_ifcs_0_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_drainFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && - merged_0_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && - merged_0_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && - merged_0_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && - merged_0_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && - WILL_FIRE_RL_ifcs_0_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && - WILL_FIRE_RL_ifcs_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && - !SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 && - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) + !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && - !SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 && - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) + !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && @@ -10885,7 +13094,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h96395 = $time; + v__h120378 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10894,7 +13103,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h96395, + v__h120378, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && @@ -10969,13 +13178,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) begin - v__h96014 = $time; + v__h119997 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h96014, + v__h119997, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) @@ -10986,7 +13195,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h98886 = $time; + v__h122869 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10995,7 +13204,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h98886, + v__h122869, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && @@ -11070,13 +13279,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) begin - v__h98505 = $time; + v__h122488 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h98505, + v__h122488, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) @@ -11090,7 +13299,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h101196 = $time; + v__h125179 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -11099,7 +13308,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h101196, + v__h125179, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && @@ -11174,13 +13383,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) begin - v__h100815 = $time; + v__h124798 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h100815, + v__h124798, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) @@ -11204,183 +13413,576 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sink_selected_8 && WILL_FIRE_RL_sink_selected_9) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_8] and\n [RL_sink_selected_9] ) fired in the same clock cycle.\n"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_2_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_drainFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && + merged_0_flitLeft > 8'd1) + $display("%m - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && + merged_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && + merged_0_flitLeft == 8'd1) + $display("%m - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && + merged_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_drainFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_sinks_1_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && - WILL_FIRE_RL_ifcs_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_drainFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_drainFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && - merged_1_flitLeft > 8'd1) - $display("Expecting more write data flits"); + if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && + merged_1_flitLeft > 8'd1) + $display("%m - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && - merged_1_flitLeft > 8'd1) - $finish(32'd0); + if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && + merged_1_flitLeft > 8'd1) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && - merged_1_flitLeft == 8'd1) - $display("Expecting last write data flit"); + if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && + merged_1_flitLeft == 8'd1) + $display("%m - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && - merged_1_flitLeft == 8'd1) - $finish(32'd0); + if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && + merged_1_flitLeft == 8'd1) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_drainFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && - WILL_FIRE_RL_ifcs_0_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && WILL_FIRE_RL_ifcs_1_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_0_warnDoPut_1) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_warnDoPut_1) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h103640 = $stime; + v__h128907 = $stime; #0; end - v__h103634 = v__h103640 / 32'd10; + v__h128901 = v__h128907 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h103634, + v__h128901, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_2_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_1_firstFlit && + WILL_FIRE_RL_ifcs_2_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_drainFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_2_1_firstFlit && - WILL_FIRE_RL_ifcs_2_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_drainFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v index e65be88..9a7f2e1 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:10 BST 2020 +// On Wed Jun 24 20:31:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v index a004347..a5ea406 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:00 BST 2020 +// On Wed Jun 24 20:23:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v index 4176804..52cd854 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:59 BST 2020 +// On Wed Jun 24 20:23:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v index 8261ced..69cefb4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:15 BST 2020 +// On Wed Jun 24 20:24:14 BST 2020 // // // Ports: @@ -46,9 +46,11 @@ // write_dm_word I 32 // master_awready I 1 // master_wready I 1 +// master_bvalid I 1 // master_bid I 4 // master_bresp I 2 // master_arready I 1 +// master_rvalid I 1 // master_rid I 4 // master_rdata I 64 // master_rresp I 2 @@ -56,154 +58,153 @@ // master_ruser I 1 // EN_reset I 1 // EN_write I 1 -// master_bvalid I 1 -// master_rvalid I 1 // EN_av_read I 1 // // Combinational paths from inputs to outputs: // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awid +// EN_write) -> master_awid // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awaddr +// EN_write) -> master_awaddr // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awlen +// EN_write) -> master_awlen // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awsize +// EN_write) -> master_awsize // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awburst +// EN_write) -> master_awburst // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awlock +// EN_write) -> master_awlock // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awcache +// EN_write) -> master_awcache // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awprot +// EN_write) -> master_awprot // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awqos +// EN_write) -> master_awqos // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awregion +// EN_write) -> master_awregion // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awuser +// EN_write) -> master_awuser // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awvalid +// EN_write) -> master_awvalid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wdata +// EN_write) -> master_wdata // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wstrb +// EN_write) -> master_wstrb // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wlast +// EN_write) -> master_wlast // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wuser +// EN_write) -> master_wuser // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wvalid +// EN_write) -> master_wvalid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -211,10 +212,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -222,10 +223,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_araddr // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -233,10 +234,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arlen // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -244,10 +245,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arsize // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -255,10 +256,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arburst // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -266,10 +267,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arlock // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -277,10 +278,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arcache // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -288,10 +289,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arprot // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -299,10 +300,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arqos // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -310,10 +311,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arregion // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -321,10 +322,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_aruser // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -332,7 +333,6 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arvalid // av_read_dm_addr -> av_read // @@ -403,9 +403,9 @@ module mkDM_System_Bus(CLK, master_wready, + master_bvalid, master_bid, master_bresp, - master_bvalid, master_bready, @@ -433,12 +433,12 @@ module mkDM_System_Bus(CLK, master_arready, + master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, master_ruser, - master_rvalid, master_rready); input CLK; @@ -517,9 +517,9 @@ module mkDM_System_Bus(CLK, input master_wready; // action method master_b_bflit + input master_bvalid; input [3 : 0] master_bid; input [1 : 0] master_bresp; - input master_bvalid; // value method master_b_bready output master_bready; @@ -563,12 +563,12 @@ module mkDM_System_Bus(CLK, input master_arready; // action method master_r_rflit + input master_rvalid; input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; input master_ruser; - input master_rvalid; // value method master_r_rready output master_rready; @@ -617,18 +617,18 @@ module mkDM_System_Bus(CLK, master_xactor_shim_rff_rv$port1__read, master_xactor_shim_rff_rv$port2__read, master_xactor_shim_rff_rv$port3__read; - wire [71 : 0] master_xactor_ug_master_u_r_putWire$wget; + wire [71 : 0] master_xactor_master_rSynth_snk_putWire$wget; wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1, master_xactor_shim_bff_rv$port1__read, master_xactor_shim_bff_rv$port2__read, master_xactor_shim_bff_rv$port3__read; - wire [5 : 0] master_xactor_ug_master_u_b_putWire$wget; - wire master_xactor_shim_arff_rv$EN_port0__write, - master_xactor_ug_master_u_ar_dropWire$whas, - master_xactor_ug_master_u_aw_dropWire$whas, - master_xactor_ug_master_u_b_putWire$whas, - master_xactor_ug_master_u_r_putWire$whas, - master_xactor_ug_master_u_w_dropWire$whas; + wire [5 : 0] master_xactor_master_bSynth_snk_putWire$wget; + wire master_xactor_master_arSynth_src_dropWire$whas, + master_xactor_master_awSynth_src_dropWire$whas, + master_xactor_master_bSynth_snk_putWire$whas, + master_xactor_master_rSynth_snk_putWire$whas, + master_xactor_master_wSynth_src_dropWire$whas, + master_xactor_shim_arff_rv$EN_port0__write; // register master_xactor_clearing reg master_xactor_clearing; @@ -713,19 +713,19 @@ module mkDM_System_Bus(CLK, // rule scheduling signals wire CAN_FIRE_RL_master_xactor_do_clear, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut, + CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut, + CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, CAN_FIRE_av_read, @@ -737,19 +737,19 @@ module mkDM_System_Bus(CLK, CAN_FIRE_reset, CAN_FIRE_write, WILL_FIRE_RL_master_xactor_do_clear, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut, + WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut, + WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_rl_sb_read_finish, WILL_FIRE_RL_rl_sb_write_response, WILL_FIRE_av_read, @@ -784,38 +784,38 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117, IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155, IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130, - wrd_wdata__h7269; - reg [7 : 0] wrd_wstrb__h7270; - reg [2 : 0] _theResult___snd_snd_val__h7160, axi4_size_val__h5415; + wrd_wdata__h7347; + reg [7 : 0] wrd_wstrb__h7348; + reg [2 : 0] _theResult___snd_snd_val__h7238, axi4_size_val__h5493; wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3, master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1; wire [73 : 0] master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2; - wire [63 : 0] _theResult___fst__h7145, - addr64__h6432, - result__h3808, - result__h3838, - result__h3865, - result__h3892, - result__h3919, - result__h3946, - result__h3973, - result__h4000, - result__h4045, - result__h4072, - result__h4099, - result__h4126, - result__h4167, - result__h4194, + wire [63 : 0] _theResult___fst__h7223, + addr64__h6510, + result__h3886, + result__h3916, + result__h3943, + result__h3970, + result__h3997, + result__h4024, + result__h4051, + result__h4078, + result__h4123, + result__h4150, + result__h4177, + result__h4204, + result__h4245, + result__h4272, rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156, rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354, - sbaddress__h3099, - word64__h7090; + sbaddress__h3177, + word64__h7168; wire [31 : 0] IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365, IF_write_dm_addr_EQ_0x39_13_THEN_rg_sbaddress1_ETC___d356, - v__h4807, - v__h4941; - wire [7 : 0] strobe64__h7143, strobe64__h7147, strobe64__h7151; - wire [5 : 0] shift_bits__h7093; + v__h4885, + v__h5019; + wire [7 : 0] strobe64__h7221, strobe64__h7225, strobe64__h7229; + wire [5 : 0] shift_bits__h7171; wire rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147, rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162, rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371, @@ -834,13 +834,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h4807 or rg_sbaddress0 or rg_sbaddress1 or v__h4941) + v__h4885 or rg_sbaddress0 or rg_sbaddress1 or v__h5019) begin case (av_read_dm_addr) - 7'h38: av_read = v__h4807; + 7'h38: av_read = v__h4885; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h4941; + 7'h3C: av_read = v__h5019; default: av_read = 32'd0; endcase end @@ -906,7 +906,8 @@ module mkDM_System_Bus(CLK, master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[3:0] ; // value method master_aw_awvalid - assign master_awvalid = CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + assign master_awvalid = + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ; // action method master_aw_awready assign CAN_FIRE_master_aw_awready = 1'd1 ; @@ -929,7 +930,7 @@ module mkDM_System_Bus(CLK, master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2[0] ; // value method master_w_wvalid - assign master_wvalid = CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + assign master_wvalid = CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ; // action method master_w_wready assign CAN_FIRE_master_w_wready = 1'd1 ; @@ -937,7 +938,7 @@ module mkDM_System_Bus(CLK, // action method master_b_bflit assign CAN_FIRE_master_b_bflit = 1'd1 ; - assign WILL_FIRE_master_b_bflit = master_bvalid ; + assign WILL_FIRE_master_b_bflit = 1'd1 ; // value method master_b_bready assign master_bready = !master_xactor_shim_bff_rv[6] ; @@ -983,7 +984,8 @@ module mkDM_System_Bus(CLK, master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[3:0] ; // value method master_ar_arvalid - assign master_arvalid = CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + assign master_arvalid = + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ; // action method master_ar_arready assign CAN_FIRE_master_ar_arready = 1'd1 ; @@ -991,38 +993,38 @@ module mkDM_System_Bus(CLK, // action method master_r_rflit assign CAN_FIRE_master_r_rflit = 1'd1 ; - assign WILL_FIRE_master_r_rflit = master_rvalid ; + assign WILL_FIRE_master_r_rflit = 1'd1 ; // value method master_r_rready assign master_rready = !master_xactor_shim_rff_rv[72] ; - // rule RL_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = - master_xactor_ug_master_u_b_putWire$whas && + // rule RL_master_xactor_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut = + master_xactor_master_bSynth_snk_putWire$whas && master_xactor_shim_bff_rv[6] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut ; - // rule RL_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut = + // rule RL_master_xactor_master_bSynth_snk_doPut + assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut = !master_xactor_shim_bff_rv[6] && - master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ; + master_xactor_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut = + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ; - // rule RL_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = - master_xactor_ug_master_u_r_putWire$whas && + // rule RL_master_xactor_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut = + master_xactor_master_rSynth_snk_putWire$whas && master_xactor_shim_rff_rv[72] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut ; - // rule RL_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut = + // rule RL_master_xactor_master_rSynth_snk_doPut + assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut = !master_xactor_shim_rff_rv[72] && - master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ; + master_xactor_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut = + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ; // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = @@ -1039,65 +1041,65 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_RL_rl_sb_write_response = CAN_FIRE_RL_rl_sb_write_response ; - // rule RL_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + // rule RL_master_xactor_master_awSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek = master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = - master_xactor_ug_master_u_aw_dropWire$whas && + // rule RL_master_xactor_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop = + master_xactor_master_awSynth_src_dropWire$whas && !master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + // rule RL_master_xactor_master_awSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop = master_xactor_shim_awff_rv$port1__read[97] && - master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ; + master_xactor_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ; - // rule RL_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + // rule RL_master_xactor_master_wSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek = master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = - master_xactor_ug_master_u_w_dropWire$whas && + // rule RL_master_xactor_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop = + master_xactor_master_wSynth_src_dropWire$whas && !master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + // rule RL_master_xactor_master_wSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop = master_xactor_shim_wff_rv$port1__read[74] && - master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ; + master_xactor_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ; - // rule RL_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + // rule RL_master_xactor_master_arSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek = master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = - master_xactor_ug_master_u_ar_dropWire$whas && + // rule RL_master_xactor_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop = + master_xactor_master_arSynth_src_dropWire$whas && !master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + // rule RL_master_xactor_master_arSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop = master_xactor_shim_arff_rv$port1__read[97] && - master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ; + master_xactor_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ; // rule RL_master_xactor_do_clear assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; @@ -1144,12 +1146,12 @@ module mkDM_System_Bus(CLK, write_dm_addr_EQ_0x3C_16_AND_rg_sb_state_7_EQ__ETC___d381 ; assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = { 5'd16, - sbaddress__h3099, + sbaddress__h3177, 8'd0, - axi4_size_val__h5415, + axi4_size_val__h5493, 18'd65536 } ; assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = - { 5'd16, addr64__h6432, 8'd0, axi4_size_val__h5415, 18'd65536 } ; + { 5'd16, addr64__h6510, 8'd0, axi4_size_val__h5493, 18'd65536 } ; always@(write_dm_addr or rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 or IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365) @@ -1183,36 +1185,36 @@ module mkDM_System_Bus(CLK, end // inlined wires - assign master_xactor_ug_master_u_b_putWire$wget = + assign master_xactor_master_bSynth_snk_putWire$wget = { master_bid, master_bresp } ; - assign master_xactor_ug_master_u_b_putWire$whas = + assign master_xactor_master_bSynth_snk_putWire$whas = master_bvalid && !master_xactor_shim_bff_rv[6] ; - assign master_xactor_ug_master_u_r_putWire$wget = + assign master_xactor_master_rSynth_snk_putWire$wget = { master_rid, master_rdata, master_rresp, master_rlast, master_ruser } ; - assign master_xactor_ug_master_u_r_putWire$whas = + assign master_xactor_master_rSynth_snk_putWire$whas = master_rvalid && !master_xactor_shim_rff_rv[72] ; - assign master_xactor_ug_master_u_aw_dropWire$whas = + assign master_xactor_master_awSynth_src_dropWire$whas = master_xactor_shim_awff_rv$port1__read[97] && master_awready ; - assign master_xactor_ug_master_u_w_dropWire$whas = + assign master_xactor_master_wSynth_src_dropWire$whas = master_xactor_shim_wff_rv$port1__read[74] && master_wready ; - assign master_xactor_ug_master_u_ar_dropWire$whas = + assign master_xactor_master_arSynth_src_dropWire$whas = master_xactor_shim_arff_rv$port1__read[97] && master_arready ; assign master_xactor_shim_awff_rv$port0__write_1 = { 5'd16, - sbaddress__h3099, + sbaddress__h3177, 8'd0, - _theResult___snd_snd_val__h7160, + _theResult___snd_snd_val__h7238, 18'd65536 } ; assign master_xactor_shim_awff_rv$port1__read = MUX_rg_sbdata0$write_1__SEL_3 ? master_xactor_shim_awff_rv$port0__write_1 : master_xactor_shim_awff_rv ; assign master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ? + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ? 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_awff_rv$port1__read ; assign master_xactor_shim_awff_rv$port3__read = @@ -1220,13 +1222,13 @@ module mkDM_System_Bus(CLK, 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_awff_rv$port2__read ; assign master_xactor_shim_wff_rv$port0__write_1 = - { 1'd1, wrd_wdata__h7269, wrd_wstrb__h7270, 2'd2 } ; + { 1'd1, wrd_wdata__h7347, wrd_wstrb__h7348, 2'd2 } ; assign master_xactor_shim_wff_rv$port1__read = MUX_rg_sbdata0$write_1__SEL_3 ? master_xactor_shim_wff_rv$port0__write_1 : master_xactor_shim_wff_rv ; assign master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ? + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ? 75'h2AAAAAAAAAAAAAAAAAA : master_xactor_shim_wff_rv$port1__read ; assign master_xactor_shim_wff_rv$port3__read = @@ -1234,9 +1236,9 @@ module mkDM_System_Bus(CLK, 75'h2AAAAAAAAAAAAAAAAAA : master_xactor_shim_wff_rv$port2__read ; assign master_xactor_shim_bff_rv$port0__write_1 = - { 1'd1, master_xactor_ug_master_u_b_putWire$wget } ; + { 1'd1, master_xactor_master_bSynth_snk_putWire$wget } ; assign master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ? + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ? master_xactor_shim_bff_rv$port0__write_1 : master_xactor_shim_bff_rv ; assign master_xactor_shim_bff_rv$port2__read = @@ -1261,7 +1263,7 @@ module mkDM_System_Bus(CLK, master_xactor_shim_arff_rv$port0__write_1 : master_xactor_shim_arff_rv ; assign master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ? + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ? 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_arff_rv$port1__read ; assign master_xactor_shim_arff_rv$port3__read = @@ -1269,9 +1271,9 @@ module mkDM_System_Bus(CLK, 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_arff_rv$port2__read ; assign master_xactor_shim_rff_rv$port0__write_1 = - { 1'd1, master_xactor_ug_master_u_r_putWire$wget } ; + { 1'd1, master_xactor_master_rSynth_snk_putWire$wget } ; assign master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ? + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ? master_xactor_shim_rff_rv$port0__write_1 : master_xactor_shim_rff_rv ; assign master_xactor_shim_rff_rv$port2__read = @@ -1368,8 +1370,8 @@ module mkDM_System_Bus(CLK, // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? - sbaddress__h3099 : - addr64__h6432 ; + sbaddress__h3177 : + addr64__h6510 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 || @@ -1474,41 +1476,41 @@ module mkDM_System_Bus(CLK, (write_dm_addr == 7'h39) ? rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354[63:32] : write_dm_word ; - assign _theResult___fst__h7145 = word64__h7090 << shift_bits__h7093 ; - assign addr64__h6432 = { rg_sbaddress1, write_dm_word } ; + assign _theResult___fst__h7223 = word64__h7168 << shift_bits__h7171 ; + assign addr64__h6510 = { rg_sbaddress1, write_dm_word } ; assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3 = master_xactor_shim_arff_rv$port1__read[96:0] ; assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1 = master_xactor_shim_awff_rv$port1__read[96:0] ; assign master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2 = master_xactor_shim_wff_rv$port1__read[73:0] ; - assign result__h3808 = + assign result__h3886 = { 56'd0, master_xactor_shim_rff_rv$port1__read[11:4] } ; - assign result__h3838 = + assign result__h3916 = { 56'd0, master_xactor_shim_rff_rv$port1__read[19:12] } ; - assign result__h3865 = + assign result__h3943 = { 56'd0, master_xactor_shim_rff_rv$port1__read[27:20] } ; - assign result__h3892 = + assign result__h3970 = { 56'd0, master_xactor_shim_rff_rv$port1__read[35:28] } ; - assign result__h3919 = + assign result__h3997 = { 56'd0, master_xactor_shim_rff_rv$port1__read[43:36] } ; - assign result__h3946 = + assign result__h4024 = { 56'd0, master_xactor_shim_rff_rv$port1__read[51:44] } ; - assign result__h3973 = + assign result__h4051 = { 56'd0, master_xactor_shim_rff_rv$port1__read[59:52] } ; - assign result__h4000 = + assign result__h4078 = { 56'd0, master_xactor_shim_rff_rv$port1__read[67:60] } ; - assign result__h4045 = + assign result__h4123 = { 48'd0, master_xactor_shim_rff_rv$port1__read[19:4] } ; - assign result__h4072 = + assign result__h4150 = { 48'd0, master_xactor_shim_rff_rv$port1__read[35:20] } ; - assign result__h4099 = + assign result__h4177 = { 48'd0, master_xactor_shim_rff_rv$port1__read[51:36] } ; - assign result__h4126 = + assign result__h4204 = { 48'd0, master_xactor_shim_rff_rv$port1__read[67:52] } ; - assign result__h4167 = + assign result__h4245 = { 32'd0, master_xactor_shim_rff_rv$port1__read[35:4] } ; - assign result__h4194 = + assign result__h4272 = { 32'd0, master_xactor_shim_rff_rv$port1__read[67:36] } ; assign rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && @@ -1523,21 +1525,21 @@ module mkDM_System_Bus(CLK, rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadonaddr ; assign rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 = - sbaddress__h3099 + + sbaddress__h3177 + IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ; assign rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354 = - addr64__h6432 + + addr64__h6510 + IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ; assign rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d346 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress__h3099 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h7093 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h7143 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h7147 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h7151 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h4807 = + assign sbaddress__h3177 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h7171 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h7221 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h7225 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h7229 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h4885 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1547,12 +1549,12 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd2055 } ; - assign v__h4941 = + assign v__h5019 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h7090 = { 32'd0, write_dm_word } ; + assign word64__h7168 = { 32'd0, write_dm_word } ; assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && @@ -1585,34 +1587,34 @@ module mkDM_System_Bus(CLK, always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: axi4_size_val__h5415 = rg_sbcs_sbaccess; - default: axi4_size_val__h5415 = 3'b011; + 3'd0, 3'd1, 3'd2: axi4_size_val__h5493 = rg_sbcs_sbaccess; + default: axi4_size_val__h5493 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) 3'd0, 3'd1, 3'd2, 3'd3: - _theResult___snd_snd_val__h7160 = rg_sbcs_sbaccess; - default: _theResult___snd_snd_val__h7160 = 3'b111; + _theResult___snd_snd_val__h7238 = rg_sbcs_sbaccess; + default: _theResult___snd_snd_val__h7238 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h7143 or strobe64__h7147 or strobe64__h7151) + strobe64__h7221 or strobe64__h7225 or strobe64__h7229) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h7270 = strobe64__h7143; - 3'd1: wrd_wstrb__h7270 = strobe64__h7147; - 3'd2: wrd_wstrb__h7270 = strobe64__h7151; - 3'd3: wrd_wstrb__h7270 = 8'b11111111; - default: wrd_wstrb__h7270 = 8'd0; + 3'd0: wrd_wstrb__h7348 = strobe64__h7221; + 3'd1: wrd_wstrb__h7348 = strobe64__h7225; + 3'd2: wrd_wstrb__h7348 = strobe64__h7229; + 3'd3: wrd_wstrb__h7348 = 8'b11111111; + default: wrd_wstrb__h7348 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h7090 or _theResult___fst__h7145) + always@(rg_sbcs_sbaccess or word64__h7168 or _theResult___fst__h7223) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h7269 = _theResult___fst__h7145; - default: wrd_wdata__h7269 = word64__h7090; + 3'd0, 3'd1, 3'd2: wrd_wdata__h7347 = _theResult___fst__h7223; + default: wrd_wdata__h7347 = word64__h7168; endcase end always@(rg_sbcs_sbaccess) @@ -1627,68 +1629,68 @@ module mkDM_System_Bus(CLK, endcase end always@(rg_sbaddress_reading or - result__h3808 or - result__h3838 or - result__h3865 or - result__h3892 or - result__h3919 or result__h3946 or result__h3973 or result__h4000) + result__h3886 or + result__h3916 or + result__h3943 or + result__h3970 or + result__h3997 or result__h4024 or result__h4051 or result__h4078) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3808; + result__h3886; 3'h1: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3838; + result__h3916; 3'h2: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3865; + result__h3943; 3'h3: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3892; + result__h3970; 3'h4: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3919; + result__h3997; 3'h5: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3946; + result__h4024; 3'h6: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3973; + result__h4051; 3'h7: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h4000; + result__h4078; endcase end always@(rg_sbaddress_reading or - result__h4045 or result__h4072 or result__h4099 or result__h4126) + result__h4123 or result__h4150 or result__h4177 or result__h4204) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4045; + result__h4123; 3'h2: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4072; + result__h4150; 3'h4: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4099; + result__h4177; 3'h6: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4126; + result__h4204; default: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h4167 or result__h4194) + always@(rg_sbaddress_reading or result__h4245 or result__h4272) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = - result__h4167; + result__h4245; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = - result__h4194; + result__h4272; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = 64'd0; endcase end @@ -1943,11 +1945,11 @@ module mkDM_System_Bus(CLK, av_read_dm_addr != 7'h3C) $write("] not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 && write_dm_word[14:12] == 3'd0) @@ -2204,14 +2206,14 @@ module mkDM_System_Bus(CLK, master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkDM_System_Bus diff --git a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v index 467c728..4e8f32a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:10 BST 2020 +// On Wed Jun 24 20:31:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v index 16d4073..055e7a2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:13 BST 2020 +// On Wed Jun 24 20:31:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v index 1f96002..6dcc0cb 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:43 BST 2020 +// On Wed Jun 24 20:31:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v index e4dd9c6..e9cc1ac 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:16 BST 2020 +// On Wed Jun 24 20:24:16 BST 2020 // // // Ports: @@ -72,9 +72,11 @@ // ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 +// master_bvalid I 1 // master_bid I 4 // master_bresp I 2 // master_arready I 1 +// master_rvalid I 1 // master_rid I 4 // master_rdata I 64 // master_rresp I 2 @@ -88,8 +90,6 @@ // EN_hart0_fpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 // EN_ndm_reset_client_response_put I 1 -// master_bvalid I 1 -// master_rvalid I 1 // EN_dmi_read_data I 1 // EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 @@ -101,265 +101,265 @@ // // Combinational paths from inputs to outputs: // (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awid -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awaddr -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awlen -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awsize -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awburst -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awlock -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awcache -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awprot -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awqos -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awregion -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awuser -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awvalid -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wdata -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wstrb -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wlast -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wuser -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wvalid -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, // master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awid +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awaddr +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awlen +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awsize +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awburst +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awlock +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awcache +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awprot +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awqos +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awregion +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awuser +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wdata +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wstrb +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wlast +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wuser +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write, // EN_dmi_read_data) -> master_arid // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_araddr // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arlen // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arsize // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arburst // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arlock // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arcache // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arprot // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arqos // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arregion // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_aruser // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arvalid // EN_dmi_read_data -> dmi_read_data // @@ -482,9 +482,9 @@ module mkDebug_Module(CLK, master_wready, + master_bvalid, master_bid, master_bresp, - master_bvalid, master_bready, @@ -512,12 +512,12 @@ module mkDebug_Module(CLK, master_arready, + master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, master_ruser, - master_rvalid, master_rready); input CLK; @@ -661,9 +661,9 @@ module mkDebug_Module(CLK, input master_wready; // action method master_b_bflit + input master_bvalid; input [3 : 0] master_bid; input [1 : 0] master_bresp; - input master_bvalid; // value method master_b_bready output master_bready; @@ -707,12 +707,12 @@ module mkDebug_Module(CLK, input master_arready; // action method master_r_rflit + input master_rvalid; input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; input master_ruser; - input master_rvalid; // value method master_r_rready output master_rready; @@ -928,8 +928,8 @@ module mkDebug_Module(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h756; - reg [31 : 0] v__h750; + reg [31 : 0] v__h772; + reg [31 : 0] v__h766; // synopsys translate_on // action method dmi_read_addr @@ -1173,7 +1173,7 @@ module mkDebug_Module(CLK, // action method master_b_bflit assign CAN_FIRE_master_b_bflit = 1'd1 ; - assign WILL_FIRE_master_b_bflit = master_bvalid ; + assign WILL_FIRE_master_b_bflit = 1'd1 ; // value method master_b_bready assign master_bready = dm_system_bus$master_bready ; @@ -1217,7 +1217,7 @@ module mkDebug_Module(CLK, // action method master_r_rflit assign CAN_FIRE_master_r_rflit = 1'd1 ; - assign WILL_FIRE_master_r_rflit = master_rvalid ; + assign WILL_FIRE_master_r_rflit = 1'd1 ; // value method master_r_rready assign master_rready = dm_system_bus$master_rready ; @@ -1299,19 +1299,19 @@ module mkDebug_Module(CLK, .master_awready(dm_system_bus$master_awready), .master_bid(dm_system_bus$master_bid), .master_bresp(dm_system_bus$master_bresp), + .master_bvalid(dm_system_bus$master_bvalid), .master_rdata(dm_system_bus$master_rdata), .master_rid(dm_system_bus$master_rid), .master_rlast(dm_system_bus$master_rlast), .master_rresp(dm_system_bus$master_rresp), .master_ruser(dm_system_bus$master_ruser), + .master_rvalid(dm_system_bus$master_rvalid), .master_wready(dm_system_bus$master_wready), .write_dm_addr(dm_system_bus$write_dm_addr), .write_dm_word(dm_system_bus$write_dm_word), .EN_reset(dm_system_bus$EN_reset), .EN_av_read(dm_system_bus$EN_av_read), .EN_write(dm_system_bus$EN_write), - .master_bvalid(dm_system_bus$master_bvalid), - .master_rvalid(dm_system_bus$master_rvalid), .RDY_reset(dm_system_bus$RDY_reset), .av_read(dm_system_bus$av_read), .RDY_av_read(dm_system_bus$RDY_av_read), @@ -1474,11 +1474,13 @@ module mkDebug_Module(CLK, assign dm_system_bus$master_awready = master_awready ; assign dm_system_bus$master_bid = master_bid ; assign dm_system_bus$master_bresp = master_bresp ; + assign dm_system_bus$master_bvalid = master_bvalid ; assign dm_system_bus$master_rdata = master_rdata ; assign dm_system_bus$master_rid = master_rid ; assign dm_system_bus$master_rlast = master_rlast ; assign dm_system_bus$master_rresp = master_rresp ; assign dm_system_bus$master_ruser = master_ruser ; + assign dm_system_bus$master_rvalid = master_rvalid ; assign dm_system_bus$master_wready = master_wready ; assign dm_system_bus$write_dm_addr = dmi_write_dm_addr ; assign dm_system_bus$write_dm_word = dmi_write_dm_word ; @@ -1501,8 +1503,6 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h3D || dmi_write_dm_addr == 7'h3E || dmi_write_dm_addr == 7'h3F) ; - assign dm_system_bus$master_bvalid = master_bvalid ; - assign dm_system_bus$master_rvalid = master_rvalid ; // submodule f_read_addr assign f_read_addr$D_IN = dmi_read_addr_dm_addr ; @@ -1519,12 +1519,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h756 = $stime; + v__h772 = $stime; #0; end - v__h750 = v__h756 / 32'd10; + v__h766 = v__h772 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h750); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h766); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v index 7eeadfd..6a74a77 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:00 BST 2020 +// On Wed Jun 24 20:34:13 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v index eadd60c..911dc8a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:03 BST 2020 +// On Wed Jun 24 20:33:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v index 8dbe0fd..fe9629b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:43 BST 2020 +// On Wed Jun 24 20:32:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v index e75c361..bf9e380 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:49 BST 2020 +// On Wed Jun 24 20:32:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v index 6623d05..072da97 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:46 BST 2020 +// On Wed Jun 24 20:32:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v index eb75e18..8fd546d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:36:08 BST 2020 +// On Wed Jun 24 20:25:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v index 7621648..f45cb51 100644 --- a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:57 BST 2020 +// On Wed Jun 24 20:24:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v index 810ddac..0df28b8 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:14 BST 2020 +// On Wed Jun 24 20:34:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v index 394b4a6..4f7d456 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:51 BST 2020 +// On Wed Jun 24 20:33:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v index b40422c..81af6ae 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:04 BST 2020 +// On Wed Jun 24 20:33:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v index 56ad13d..b6b52a9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:05 BST 2020 +// On Wed Jun 24 20:33:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v index c73200c..0180a73 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:57 BST 2020 +// On Wed Jun 24 20:34:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v index 3c08a5c..d03e3b6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:57 BST 2020 +// On Wed Jun 24 20:34:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v index a6c8b6d..5111af7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v index 618d926..3fdb02d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v index 7fc1eae..16ccbdb 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:20 BST 2020 +// On Wed Jun 24 20:31:29 BST 2020 // // // Ports: @@ -585,7 +585,7 @@ module mkIBankWrapper(CLK, SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425, addr__h42425; reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31, x__h45568; reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38, @@ -616,7 +616,7 @@ module mkIBankWrapper(CLK, IF_m_pipeline_first__47_BITS_518_TO_516_52_EQ__ETC___d595; wire [5 : 0] IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d600, SEL_ARR_m_rqToPQ_data_0_84_BITS_5_TO_4_94_m_rq_ETC___d806; - wire [3 : 0] sel__h51069; + wire [3 : 0] sel__h51068; wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d615, SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461, SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d739, @@ -1055,7 +1055,7 @@ module mkIBankWrapper(CLK, WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[575] ; assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 = { 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, 1'd1, CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ; assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 = @@ -1714,7 +1714,7 @@ module mkIBankWrapper(CLK, assign resp_addr__h45726 = { m_cRqMshr$sendRsToP_cRq_getSlot[53:1], m_cRqMshr$sendRsToP_cRq_getRq[10:0] } ; - assign sel__h51069 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; + assign sel__h51068 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; assign v__h10212 = IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ? v__h10363 : @@ -2150,56 +2150,56 @@ module mkIBankWrapper(CLK, m_fromPQ_data_1[586]; endcase end - always@(sel__h51069 or m_pipeline$first) + always@(sel__h51068 or m_pipeline$first) begin - case (sel__h51069) + case (sel__h51068) 4'd0: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[31:0]; 4'd1: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[63:32]; 4'd2: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[95:64]; 4'd3: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[127:96]; 4'd4: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[159:128]; 4'd5: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[191:160]; 4'd6: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[223:192]; 4'd7: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[255:224]; 4'd8: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[287:256]; 4'd9: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[319:288]; 4'd10: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[351:320]; 4'd11: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[383:352]; 4'd12: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[415:384]; 4'd13: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[447:416]; 4'd14: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[479:448]; 4'd15: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[511:480]; endcase end diff --git a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v index 8f8a8f1..3415259 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:14 BST 2020 +// On Wed Jun 24 20:31:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkICoCache.v b/src_SSITH_P3/Verilog_RTL/mkICoCache.v index 1291863..ba24afa 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:20 BST 2020 +// On Wed Jun 24 20:31:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v index b90ae70..5f3183a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:15 BST 2020 +// On Wed Jun 24 20:31:24 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v index 3fd92c5..2ce4a9c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:17 BST 2020 +// On Wed Jun 24 20:31:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkITlb.v b/src_SSITH_P3/Verilog_RTL/mkITlb.v index a23f2b3..4fb2738 100644 --- a/src_SSITH_P3/Verilog_RTL/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:55 BST 2020 +// On Wed Jun 24 20:24:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v index 2edf342..45ffba2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:28 BST 2020 +// On Wed Jun 24 20:23:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v index 0eba9aa..9d8d163 100644 --- a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:41:46 BST 2020 +// On Wed Jun 24 20:30:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLLCache.v b/src_SSITH_P3/Verilog_RTL/mkLLCache.v index d1a386c..77af758 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:36 BST 2020 +// On Wed Jun 24 20:32:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v index 27be9d4..45331a0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:23 BST 2020 +// On Wed Jun 24 20:32:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v index aa267b2..5951f84 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:14 BST 2020 +// On Wed Jun 24 20:29:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v index 79241f5..defd5a8 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:15 BST 2020 +// On Wed Jun 24 20:32:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v index e494fc6..f8addaf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:45 BST 2020 +// On Wed Jun 24 20:24:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v index 8557c30..c5b2dc5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:34 BST 2020 +// On Wed Jun 24 20:31:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v index f1b13c4..47e788a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:51 BST 2020 +// On Wed Jun 24 20:32:01 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v index 3cc03bd..468f746 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:34 BST 2020 +// On Wed Jun 24 20:31:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v index 10cdea1..e713911 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:51 BST 2020 +// On Wed Jun 24 20:33:01 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v index e61cdd6..6b1d524 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:03 BST 2020 +// On Wed Jun 24 20:33:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v index 874419a..50c0aff 100644 --- a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:39 BST 2020 +// On Wed Jun 24 20:24:39 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index de0c878..ceae4bd 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:47:39 BST 2020 +// On Wed Jun 24 20:36:59 BST 2020 // // // Ports: @@ -69,18 +69,22 @@ // RST_N I 1 reset // master0_awready I 1 // master0_wready I 1 +// master0_bvalid I 1 // master0_bid I 6 // master0_bresp I 2 // master0_arready I 1 +// master0_rvalid I 1 // master0_rid I 6 // master0_rdata I 64 // master0_rresp I 2 // master0_rlast I 1 // master1_awready I 1 // master1_wready I 1 +// master1_bvalid I 1 // master1_bid I 6 reg // master1_bresp I 2 reg // master1_arready I 1 +// master1_rvalid I 1 // master1_rid I 6 reg // master1_rdata I 64 reg // master1_rresp I 2 reg @@ -90,10 +94,6 @@ // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 -// master0_bvalid I 1 -// master0_rvalid I 1 -// master1_bvalid I 1 -// master1_rvalid I 1 // // No combinational paths from inputs to outputs // @@ -149,9 +149,9 @@ module mkP3_Core(CLK, master0_wready, + master0_bvalid, master0_bid, master0_bresp, - master0_bvalid, master0_bready, @@ -179,11 +179,11 @@ module mkP3_Core(CLK, master0_arready, + master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, - master0_rvalid, master0_rready, @@ -221,9 +221,9 @@ module mkP3_Core(CLK, master1_wready, + master1_bvalid, master1_bid, master1_bresp, - master1_bvalid, master1_bready, @@ -251,11 +251,11 @@ module mkP3_Core(CLK, master1_arready, + master1_rvalid, master1_rid, master1_rdata, master1_rresp, master1_rlast, - master1_rvalid, master1_rready, @@ -332,9 +332,9 @@ module mkP3_Core(CLK, input master0_wready; // action method master0_b_bflit + input master0_bvalid; input [5 : 0] master0_bid; input [1 : 0] master0_bresp; - input master0_bvalid; // value method master0_b_bready output master0_bready; @@ -378,11 +378,11 @@ module mkP3_Core(CLK, input master0_arready; // action method master0_r_rflit + input master0_rvalid; input [5 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; - input master0_rvalid; // value method master0_r_rready output master0_rready; @@ -443,9 +443,9 @@ module mkP3_Core(CLK, input master1_wready; // action method master1_b_bflit + input master1_bvalid; input [5 : 0] master1_bid; input [1 : 0] master1_bresp; - input master1_bvalid; // value method master1_b_bready output master1_bready; @@ -489,11 +489,11 @@ module mkP3_Core(CLK, input master1_arready; // action method master1_r_rflit + input master1_rvalid; input [5 : 0] master1_rid; input [63 : 0] master1_rdata; input [1 : 0] master1_rresp; input master1_rlast; - input master1_rvalid; // value method master1_r_rready output master1_rready; @@ -854,10 +854,10 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1321; - reg [31 : 0] v__h1469; - reg [31 : 0] v__h1315; - reg [31 : 0] v__h1463; + reg [31 : 0] v__h1353; + reg [31 : 0] v__h1501; + reg [31 : 0] v__h1347; + reg [31 : 0] v__h1495; // synopsys translate_on // remaining internal signals @@ -925,7 +925,7 @@ module mkP3_Core(CLK, // action method master0_b_bflit assign CAN_FIRE_master0_b_bflit = 1'd1 ; - assign WILL_FIRE_master0_b_bflit = master0_bvalid ; + assign WILL_FIRE_master0_b_bflit = 1'd1 ; // value method master0_b_bready assign master0_bready = corew$cpu_imem_master_bready ; @@ -969,7 +969,7 @@ module mkP3_Core(CLK, // action method master0_r_rflit assign CAN_FIRE_master0_r_rflit = 1'd1 ; - assign WILL_FIRE_master0_r_rflit = master0_rvalid ; + assign WILL_FIRE_master0_r_rflit = 1'd1 ; // value method master0_r_rready assign master0_rready = corew$cpu_imem_master_rready ; @@ -1029,7 +1029,7 @@ module mkP3_Core(CLK, // action method master1_b_bflit assign CAN_FIRE_master1_b_bflit = 1'd1 ; - assign WILL_FIRE_master1_b_bflit = master1_bvalid ; + assign WILL_FIRE_master1_b_bflit = 1'd1 ; // value method master1_b_bready assign master1_bready = corew$cpu_dmem_master_bready ; @@ -1073,7 +1073,7 @@ module mkP3_Core(CLK, // action method master1_r_rflit assign CAN_FIRE_master1_r_rflit = 1'd1 ; - assign WILL_FIRE_master1_r_rflit = master1_rvalid ; + assign WILL_FIRE_master1_r_rflit = 1'd1 ; // value method master1_r_rready assign master1_rready = corew$cpu_dmem_master_rready ; @@ -1136,19 +1136,23 @@ module mkP3_Core(CLK, .cpu_dmem_master_awready(corew$cpu_dmem_master_awready), .cpu_dmem_master_bid(corew$cpu_dmem_master_bid), .cpu_dmem_master_bresp(corew$cpu_dmem_master_bresp), + .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), .cpu_dmem_master_rdata(corew$cpu_dmem_master_rdata), .cpu_dmem_master_rid(corew$cpu_dmem_master_rid), .cpu_dmem_master_rlast(corew$cpu_dmem_master_rlast), .cpu_dmem_master_rresp(corew$cpu_dmem_master_rresp), + .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), .cpu_dmem_master_wready(corew$cpu_dmem_master_wready), .cpu_imem_master_arready(corew$cpu_imem_master_arready), .cpu_imem_master_awready(corew$cpu_imem_master_awready), .cpu_imem_master_bid(corew$cpu_imem_master_bid), .cpu_imem_master_bresp(corew$cpu_imem_master_bresp), + .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), .cpu_imem_master_rdata(corew$cpu_imem_master_rdata), .cpu_imem_master_rid(corew$cpu_imem_master_rid), .cpu_imem_master_rlast(corew$cpu_imem_master_rlast), .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), + .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), .dmi_read_addr_dm_addr(corew$dmi_read_addr_dm_addr), .dmi_write_dm_addr(corew$dmi_write_dm_addr), @@ -1162,10 +1166,6 @@ module mkP3_Core(CLK, .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), - .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), - .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), - .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), - .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), .EN_dmi_read_addr(corew$EN_dmi_read_addr), .EN_dmi_read_data(corew$EN_dmi_read_data), .EN_dmi_write(corew$EN_dmi_write), @@ -1554,19 +1554,23 @@ module mkP3_Core(CLK, assign corew$cpu_dmem_master_awready = master1_awready ; assign corew$cpu_dmem_master_bid = master1_bid ; assign corew$cpu_dmem_master_bresp = master1_bresp ; + assign corew$cpu_dmem_master_bvalid = master1_bvalid ; assign corew$cpu_dmem_master_rdata = master1_rdata ; assign corew$cpu_dmem_master_rid = master1_rid ; assign corew$cpu_dmem_master_rlast = master1_rlast ; assign corew$cpu_dmem_master_rresp = master1_rresp ; + assign corew$cpu_dmem_master_rvalid = master1_rvalid ; assign corew$cpu_dmem_master_wready = master1_wready ; assign corew$cpu_imem_master_arready = master0_arready ; assign corew$cpu_imem_master_awready = master0_awready ; assign corew$cpu_imem_master_bid = master0_bid ; assign corew$cpu_imem_master_bresp = master0_bresp ; + assign corew$cpu_imem_master_bvalid = master0_bvalid ; assign corew$cpu_imem_master_rdata = master0_rdata ; assign corew$cpu_imem_master_rid = master0_rid ; assign corew$cpu_imem_master_rlast = master0_rlast ; assign corew$cpu_imem_master_rresp = master0_rresp ; + assign corew$cpu_imem_master_rvalid = master0_rvalid ; assign corew$cpu_imem_master_wready = master0_wready ; assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; @@ -1582,10 +1586,6 @@ module mkP3_Core(CLK, assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; - assign corew$cpu_imem_master_bvalid = master0_bvalid ; - assign corew$cpu_imem_master_rvalid = master0_rvalid ; - assign corew$cpu_dmem_master_bvalid = master1_bvalid ; - assign corew$cpu_dmem_master_rvalid = master1_rvalid ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1682,31 +1682,31 @@ module mkP3_Core(CLK, if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1321 = $stime; + v__h1353 = $stime; #0; end - v__h1315 = v__h1321 / 32'd10; + v__h1347 = v__h1353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset) $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1315, + v__h1347, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) begin - v__h1469 = $stime; + v__h1501 = $stime; #0; end - v__h1463 = v__h1469 / 32'd10; + v__h1495 = v__h1501 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1463); + v__h1495); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v index 9299a7a..c0fd0bf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:09 BST 2020 +// On Wed Jun 24 20:24:08 BST 2020 // // // Ports: @@ -30,6 +30,7 @@ // set_verbosity_verbosity I 4 reg // set_addr_map_addr_base I 64 reg // set_addr_map_addr_lim I 64 reg +// axi4_slave_awvalid I 1 // axi4_slave_awid I 5 reg // axi4_slave_awaddr I 64 reg // axi4_slave_awlen I 8 reg @@ -40,11 +41,13 @@ // axi4_slave_awprot I 3 reg // axi4_slave_awqos I 4 reg // axi4_slave_awregion I 4 reg +// axi4_slave_wvalid I 1 // axi4_slave_wdata I 64 reg // axi4_slave_wstrb I 8 reg // axi4_slave_wlast I 1 reg // axi4_slave_wuser I 1 reg // axi4_slave_bready I 1 +// axi4_slave_arvalid I 1 // axi4_slave_arid I 5 reg // axi4_slave_araddr I 64 reg // axi4_slave_arlen I 8 reg @@ -77,9 +80,6 @@ // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_set_addr_map I 1 -// axi4_slave_awvalid I 1 -// axi4_slave_wvalid I 1 -// axi4_slave_arvalid I 1 // // No combinational paths from inputs to outputs // @@ -119,6 +119,7 @@ module mkPLIC_16_2_7(CLK, EN_set_addr_map, RDY_set_addr_map, + axi4_slave_awvalid, axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -129,15 +130,14 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion, - axi4_slave_awvalid, axi4_slave_awready, + axi4_slave_wvalid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, axi4_slave_wuser, - axi4_slave_wvalid, axi4_slave_wready, @@ -149,6 +149,7 @@ module mkPLIC_16_2_7(CLK, axi4_slave_bready, + axi4_slave_arvalid, axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -159,7 +160,6 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion, - axi4_slave_arvalid, axi4_slave_arready, @@ -239,6 +239,7 @@ module mkPLIC_16_2_7(CLK, output RDY_set_addr_map; // action method axi4_slave_aw_awflit + input axi4_slave_awvalid; input [4 : 0] axi4_slave_awid; input [63 : 0] axi4_slave_awaddr; input [7 : 0] axi4_slave_awlen; @@ -249,17 +250,16 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_awprot; input [3 : 0] axi4_slave_awqos; input [3 : 0] axi4_slave_awregion; - input axi4_slave_awvalid; // value method axi4_slave_aw_awready output axi4_slave_awready; // action method axi4_slave_w_wflit + input axi4_slave_wvalid; input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; input axi4_slave_wuser; - input axi4_slave_wvalid; // value method axi4_slave_w_wready output axi4_slave_wready; @@ -279,6 +279,7 @@ module mkPLIC_16_2_7(CLK, input axi4_slave_bready; // action method axi4_slave_ar_arflit + input axi4_slave_arvalid; input [4 : 0] axi4_slave_arid; input [63 : 0] axi4_slave_araddr; input [7 : 0] axi4_slave_arlen; @@ -289,7 +290,6 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_arprot; input [3 : 0] axi4_slave_arqos; input [3 : 0] axi4_slave_arregion; - input axi4_slave_arvalid; // value method axi4_slave_ar_arready output axi4_slave_arready; @@ -389,15 +389,15 @@ module mkPLIC_16_2_7(CLK, v_targets_1_m_eip; // inlined wires - wire [97 : 0] m_slave_xactor_ug_slave_u_ar_putWire$wget, - m_slave_xactor_ug_slave_u_aw_putWire$wget; - wire [73 : 0] m_slave_xactor_ug_slave_u_w_putWire$wget; - wire [72 : 0] m_slave_xactor_ug_slave_u_r_peekWire$wget; - wire m_slave_xactor_ug_slave_u_ar_putWire$whas, - m_slave_xactor_ug_slave_u_aw_putWire$whas, - m_slave_xactor_ug_slave_u_b_dropWire$whas, - m_slave_xactor_ug_slave_u_r_dropWire$whas, - m_slave_xactor_ug_slave_u_w_putWire$whas; + wire [97 : 0] m_slave_xactor_slvSynth_arSynth_snk_putWire$wget, + m_slave_xactor_slvSynth_awSynth_snk_putWire$wget; + wire [73 : 0] m_slave_xactor_slvSynth_wSynth_snk_putWire$wget; + wire [72 : 0] m_slave_xactor_slvSynth_rSynth_src_peekWire$wget; + wire m_slave_xactor_slvSynth_arSynth_snk_putWire$whas, + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas, + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas, + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas, + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas; // register m_cfg_verbosity reg [3 : 0] m_cfg_verbosity; @@ -854,18 +854,18 @@ module mkPLIC_16_2_7(CLK, CAN_FIRE_RL_m_rl_process_wr_req, CAN_FIRE_RL_m_rl_reset, CAN_FIRE_RL_m_slave_xactor_do_clear, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut, CAN_FIRE_axi4_slave_ar_arflit, CAN_FIRE_axi4_slave_aw_awflit, CAN_FIRE_axi4_slave_b_bready, @@ -896,18 +896,18 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_wr_req, WILL_FIRE_RL_m_rl_reset, WILL_FIRE_RL_m_slave_xactor_do_clear, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut, WILL_FIRE_axi4_slave_ar_arflit, WILL_FIRE_axi4_slave_aw_awflit, WILL_FIRE_axi4_slave_b_bready, @@ -1061,142 +1061,142 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h77333; - reg [31 : 0] v__h77531; - reg [31 : 0] v__h77729; - reg [31 : 0] v__h77927; - reg [31 : 0] v__h78125; - reg [31 : 0] v__h78323; - reg [31 : 0] v__h78521; - reg [31 : 0] v__h78719; - reg [31 : 0] v__h78917; - reg [31 : 0] v__h79115; - reg [31 : 0] v__h79313; - reg [31 : 0] v__h79511; - reg [31 : 0] v__h79709; - reg [31 : 0] v__h79907; - reg [31 : 0] v__h80105; - reg [31 : 0] v__h80303; - reg [31 : 0] v__h7530; - reg [31 : 0] v__h28194; - reg [31 : 0] v__h28448; - reg [31 : 0] v__h29372; - reg [31 : 0] v__h29558; - reg [31 : 0] v__h68542; - reg [31 : 0] v__h68832; - reg [31 : 0] v__h69364; - reg [31 : 0] v__h69450; - reg [31 : 0] v__h69661; - reg [31 : 0] v__h69907; - reg [31 : 0] v__h14375; - reg [31 : 0] v__h14590; - reg [31 : 0] v__h14818; - reg [31 : 0] v__h15069; - reg [31 : 0] v__h19543; - reg [31 : 0] v__h25160; - reg [31 : 0] v__h27336; - reg [31 : 0] v__h25416; - reg [31 : 0] v__h27627; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h76288; - reg [31 : 0] v__h76398; - reg [31 : 0] v__h76511; - reg [31 : 0] v__h7524; - reg [31 : 0] v__h14369; - reg [31 : 0] v__h14584; - reg [31 : 0] v__h14812; - reg [31 : 0] v__h15063; - reg [31 : 0] v__h19537; - reg [31 : 0] v__h25154; - reg [31 : 0] v__h25410; - reg [31 : 0] v__h27330; - reg [31 : 0] v__h27621; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28188; - reg [31 : 0] v__h28442; - reg [31 : 0] v__h29366; - reg [31 : 0] v__h29552; - reg [31 : 0] v__h68536; - reg [31 : 0] v__h68826; - reg [31 : 0] v__h69358; - reg [31 : 0] v__h69444; - reg [31 : 0] v__h69655; - reg [31 : 0] v__h69901; - reg [31 : 0] v__h76282; - reg [31 : 0] v__h76392; - reg [31 : 0] v__h76505; - reg [31 : 0] v__h77327; - reg [31 : 0] v__h77525; - reg [31 : 0] v__h77723; - reg [31 : 0] v__h77921; - reg [31 : 0] v__h78119; - reg [31 : 0] v__h78317; - reg [31 : 0] v__h78515; - reg [31 : 0] v__h78713; - reg [31 : 0] v__h78911; - reg [31 : 0] v__h79109; - reg [31 : 0] v__h79307; - reg [31 : 0] v__h79505; - reg [31 : 0] v__h79703; - reg [31 : 0] v__h79901; - reg [31 : 0] v__h80099; - reg [31 : 0] v__h80297; + reg [31 : 0] v__h77354; + reg [31 : 0] v__h77552; + reg [31 : 0] v__h77750; + reg [31 : 0] v__h77948; + reg [31 : 0] v__h78146; + reg [31 : 0] v__h78344; + reg [31 : 0] v__h78542; + reg [31 : 0] v__h78740; + reg [31 : 0] v__h78938; + reg [31 : 0] v__h79136; + reg [31 : 0] v__h79334; + reg [31 : 0] v__h79532; + reg [31 : 0] v__h79730; + reg [31 : 0] v__h79928; + reg [31 : 0] v__h80126; + reg [31 : 0] v__h80324; + reg [31 : 0] v__h7589; + reg [31 : 0] v__h28253; + reg [31 : 0] v__h28507; + reg [31 : 0] v__h29431; + reg [31 : 0] v__h29617; + reg [31 : 0] v__h68601; + reg [31 : 0] v__h68891; + reg [31 : 0] v__h69423; + reg [31 : 0] v__h69509; + reg [31 : 0] v__h69720; + reg [31 : 0] v__h69966; + reg [31 : 0] v__h14434; + reg [31 : 0] v__h14649; + reg [31 : 0] v__h14877; + reg [31 : 0] v__h15128; + reg [31 : 0] v__h19602; + reg [31 : 0] v__h25219; + reg [31 : 0] v__h27395; + reg [31 : 0] v__h25475; + reg [31 : 0] v__h27686; + reg [31 : 0] v__h27924; + reg [31 : 0] v__h76347; + reg [31 : 0] v__h76457; + reg [31 : 0] v__h76570; + reg [31 : 0] v__h7583; + reg [31 : 0] v__h14428; + reg [31 : 0] v__h14643; + reg [31 : 0] v__h14871; + reg [31 : 0] v__h15122; + reg [31 : 0] v__h19596; + reg [31 : 0] v__h25213; + reg [31 : 0] v__h25469; + reg [31 : 0] v__h27389; + reg [31 : 0] v__h27680; + reg [31 : 0] v__h27918; + reg [31 : 0] v__h28247; + reg [31 : 0] v__h28501; + reg [31 : 0] v__h29425; + reg [31 : 0] v__h29611; + reg [31 : 0] v__h68595; + reg [31 : 0] v__h68885; + reg [31 : 0] v__h69417; + reg [31 : 0] v__h69503; + reg [31 : 0] v__h69714; + reg [31 : 0] v__h69960; + reg [31 : 0] v__h76341; + reg [31 : 0] v__h76451; + reg [31 : 0] v__h76564; + reg [31 : 0] v__h77348; + reg [31 : 0] v__h77546; + reg [31 : 0] v__h77744; + reg [31 : 0] v__h77942; + reg [31 : 0] v__h78140; + reg [31 : 0] v__h78338; + reg [31 : 0] v__h78536; + reg [31 : 0] v__h78734; + reg [31 : 0] v__h78932; + reg [31 : 0] v__h79130; + reg [31 : 0] v__h79328; + reg [31 : 0] v__h79526; + reg [31 : 0] v__h79724; + reg [31 : 0] v__h79922; + reg [31 : 0] v__h80120; + reg [31 : 0] v__h80318; // synopsys translate_on // remaining internal signals - reg [63 : 0] y_avValue_fst__h27509; - reg [4 : 0] x__h25371, x__h69004; - reg [2 : 0] x__h14848, x__h25190; - reg [1 : 0] CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49, - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50; - reg CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, + reg [63 : 0] y_avValue_fst__h27568; + reg [4 : 0] x__h25430, x__h69063; + reg [2 : 0] x__h14907, x__h25249; + reg [1 : 0] CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49, + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50; + reg CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029, SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164, SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168, @@ -1294,127 +1294,127 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586; - wire [63 : 0] addr_offset__h14540, - addr_offset__h28408, - rdata___1__h27806, - rdata__h27563, - v__h14777, - v__h15027, - v__h19501, - v__h25119, - v__h26816, - v__h26835, - x__h27766, - y_avValue_fst__h27455, - y_avValue_fst__h27476, - y_avValue_fst__h27488, - y_avValue_fst__h27504, - y_avValue_fst__h27520, - y_avValue_fst__h27525, - y_avValue_fst__h27536, - y_avValue_fst__h27541, - y_avValue_fst__h27555; - wire [31 : 0] v_ie__h19504, - v_ip__h15030, - wdata32__h28409, - x__h25030, - x__h68623; - wire [9 : 0] source_id__h17021, - source_id__h17128, - source_id__h17201, - source_id__h17274, - source_id__h17347, - source_id__h17420, - source_id__h17493, - source_id__h17566, - source_id__h17639, - source_id__h17712, - source_id__h17785, - source_id__h17858, - source_id__h17931, - source_id__h18004, - source_id__h18077, - source_id__h18150, - source_id__h18223, - source_id__h18296, - source_id__h18369, - source_id__h18442, - source_id__h18515, - source_id__h18588, - source_id__h18661, - source_id__h18734, - source_id__h18807, - source_id__h18880, - source_id__h18953, - source_id__h19026, - source_id__h19099, - source_id__h19172, - source_id__h19245, - source_id__h21494, - source_id__h21670, - source_id__h21778, - source_id__h21886, - source_id__h21994, - source_id__h22102, - source_id__h22210, - source_id__h22318, - source_id__h22426, - source_id__h22534, - source_id__h22642, - source_id__h22750, - source_id__h22858, - source_id__h22966, - source_id__h23074, - source_id__h23182, - source_id__h23290, - source_id__h23398, - source_id__h23506, - source_id__h23614, - source_id__h23722, - source_id__h23830, - source_id__h23938, - source_id__h24046, - source_id__h24154, - source_id__h24262, - source_id__h24370, - source_id__h24478, - source_id__h24586, - source_id__h24694, - source_id__h24802, - source_id__h30987, - source_id__h32197, - source_id__h33407, - source_id__h34617, - source_id__h35827, - source_id__h37037, - source_id__h38247, - source_id__h39457, - source_id__h40667, - source_id__h41877, - source_id__h43087, - source_id__h44297, - source_id__h45507, - source_id__h46717, - source_id__h47927, - source_id__h49137, - source_id__h50347, - source_id__h51557, - source_id__h52767, - source_id__h53977, - source_id__h55187, - source_id__h56397, - source_id__h57607, - source_id__h58817, - source_id__h60027, - source_id__h61237, - source_id__h62447, - source_id__h63657, - source_id__h64867, - source_id__h66077, - source_id__h67287, - source_id__h68952, - source_id_base__h14985, - source_id_base__h29659; + wire [63 : 0] addr_offset__h14599, + addr_offset__h28467, + rdata___1__h27865, + rdata__h27622, + v__h14836, + v__h15086, + v__h19560, + v__h25178, + v__h26875, + v__h26894, + x__h27825, + y_avValue_fst__h27514, + y_avValue_fst__h27535, + y_avValue_fst__h27547, + y_avValue_fst__h27563, + y_avValue_fst__h27579, + y_avValue_fst__h27584, + y_avValue_fst__h27595, + y_avValue_fst__h27600, + y_avValue_fst__h27614; + wire [31 : 0] v_ie__h19563, + v_ip__h15089, + wdata32__h28468, + x__h25089, + x__h68682; + wire [9 : 0] source_id__h17080, + source_id__h17187, + source_id__h17260, + source_id__h17333, + source_id__h17406, + source_id__h17479, + source_id__h17552, + source_id__h17625, + source_id__h17698, + source_id__h17771, + source_id__h17844, + source_id__h17917, + source_id__h17990, + source_id__h18063, + source_id__h18136, + source_id__h18209, + source_id__h18282, + source_id__h18355, + source_id__h18428, + source_id__h18501, + source_id__h18574, + source_id__h18647, + source_id__h18720, + source_id__h18793, + source_id__h18866, + source_id__h18939, + source_id__h19012, + source_id__h19085, + source_id__h19158, + source_id__h19231, + source_id__h19304, + source_id__h21553, + source_id__h21729, + source_id__h21837, + source_id__h21945, + source_id__h22053, + source_id__h22161, + source_id__h22269, + source_id__h22377, + source_id__h22485, + source_id__h22593, + source_id__h22701, + source_id__h22809, + source_id__h22917, + source_id__h23025, + source_id__h23133, + source_id__h23241, + source_id__h23349, + source_id__h23457, + source_id__h23565, + source_id__h23673, + source_id__h23781, + source_id__h23889, + source_id__h23997, + source_id__h24105, + source_id__h24213, + source_id__h24321, + source_id__h24429, + source_id__h24537, + source_id__h24645, + source_id__h24753, + source_id__h24861, + source_id__h31046, + source_id__h32256, + source_id__h33466, + source_id__h34676, + source_id__h35886, + source_id__h37096, + source_id__h38306, + source_id__h39516, + source_id__h40726, + source_id__h41936, + source_id__h43146, + source_id__h44356, + source_id__h45566, + source_id__h46776, + source_id__h47986, + source_id__h49196, + source_id__h50406, + source_id__h51616, + source_id__h52826, + source_id__h54036, + source_id__h55246, + source_id__h56456, + source_id__h57666, + source_id__h58876, + source_id__h60086, + source_id__h61296, + source_id__h62506, + source_id__h63716, + source_id__h64926, + source_id__h66136, + source_id__h67346, + source_id__h69011, + source_id_base__h15044, + source_id_base__h29718; wire [4 : 0] IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d3227, IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d3321, IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d733, @@ -1436,9 +1436,9 @@ module mkPLIC_16_2_7(CLK, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3225, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3319, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d731, - b__h72911, - b__h74916, - max_id__h25318; + b__h72970, + b__h74975, + max_id__h25377; wire [2 : 0] IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d3186, IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d3280, IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d681, @@ -1483,8 +1483,8 @@ module mkPLIC_16_2_7(CLK, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3181, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3275, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d674, - a__h72910, - a__h74915; + a__h72969, + a__h74974; wire [1 : 0] IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d875, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d876, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877, @@ -1546,22 +1546,22 @@ module mkPLIC_16_2_7(CLK, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962, - NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439, - NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447, - NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455, - NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463, - NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471, - NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479, - NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487, - NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368, - NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375, - NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383, - NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391, - NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399, - NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407, - NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415, - NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423, - NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431, + NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442, + NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450, + NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458, + NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466, + NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474, + NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482, + NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490, + NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371, + NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378, + NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386, + NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394, + NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402, + NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410, + NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418, + NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426, + NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434, _dfoo1, _dfoo10, _dfoo100, @@ -3242,14 +3242,14 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_aw_awflit assign CAN_FIRE_axi4_slave_aw_awflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_aw_awflit = axi4_slave_awvalid ; + assign WILL_FIRE_axi4_slave_aw_awflit = 1'd1 ; // value method axi4_slave_aw_awready assign axi4_slave_awready = m_slave_xactor_shim_awff$FULL_N ; // action method axi4_slave_w_wflit assign CAN_FIRE_axi4_slave_w_wflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_w_wflit = axi4_slave_wvalid ; + assign WILL_FIRE_axi4_slave_w_wflit = 1'd1 ; // value method axi4_slave_w_wready assign axi4_slave_wready = m_slave_xactor_shim_wff$FULL_N ; @@ -3269,25 +3269,30 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_ar_arflit assign CAN_FIRE_axi4_slave_ar_arflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_ar_arflit = axi4_slave_arvalid ; + assign WILL_FIRE_axi4_slave_ar_arflit = 1'd1 ; // value method axi4_slave_ar_arready assign axi4_slave_arready = m_slave_xactor_shim_arff$FULL_N ; // value method axi4_slave_r_rid - assign axi4_slave_rid = m_slave_xactor_ug_slave_u_r_peekWire$wget[72:68] ; + assign axi4_slave_rid = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[72:68] ; // value method axi4_slave_r_rdata - assign axi4_slave_rdata = m_slave_xactor_ug_slave_u_r_peekWire$wget[67:4] ; + assign axi4_slave_rdata = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[67:4] ; // value method axi4_slave_r_rresp - assign axi4_slave_rresp = m_slave_xactor_ug_slave_u_r_peekWire$wget[3:2] ; + assign axi4_slave_rresp = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[3:2] ; // value method axi4_slave_r_rlast - assign axi4_slave_rlast = m_slave_xactor_ug_slave_u_r_peekWire$wget[1] ; + assign axi4_slave_rlast = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[1] ; // value method axi4_slave_r_ruser - assign axi4_slave_ruser = m_slave_xactor_ug_slave_u_r_peekWire$wget[0] ; + assign axi4_slave_ruser = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[0] ; // value method axi4_slave_r_rvalid assign axi4_slave_rvalid = m_slave_xactor_shim_rff$EMPTY_N ; @@ -3361,10 +3366,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h72910 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h72969 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h74915 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h74974 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3460,39 +3465,39 @@ module mkPLIC_16_2_7(CLK, m_f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - // rule RL_m_slave_xactor_ug_slave_u_aw_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = - m_slave_xactor_ug_slave_u_aw_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas && !m_slave_xactor_shim_awff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_w_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = - m_slave_xactor_ug_slave_u_w_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas && !m_slave_xactor_shim_wff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_b_setPeek - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + // rule RL_m_slave_xactor_slvSynth_bSynth_src_setPeek + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek = m_slave_xactor_shim_bff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek = m_slave_xactor_shim_bff$EMPTY_N ; - // rule RL_m_slave_xactor_ug_slave_u_b_warnDoDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = - m_slave_xactor_ug_slave_u_b_dropWire$whas && + // rule RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas && !m_slave_xactor_shim_bff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop ; - // rule RL_m_slave_xactor_ug_slave_u_b_doDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = + // rule RL_m_slave_xactor_slvSynth_bSynth_src_doDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop = m_slave_xactor_shim_bff$EMPTY_N && - m_slave_xactor_ug_slave_u_b_dropWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop ; // rule RL_m_rl_process_wr_req assign CAN_FIRE_RL_m_rl_process_wr_req = @@ -3504,46 +3509,46 @@ module mkPLIC_16_2_7(CLK, CAN_FIRE_RL_m_rl_process_wr_req && !WILL_FIRE_RL_m_rl_process_rd_req ; - // rule RL_m_slave_xactor_ug_slave_u_aw_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = + // rule RL_m_slave_xactor_slvSynth_awSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut = m_slave_xactor_shim_awff$FULL_N && - m_slave_xactor_ug_slave_u_aw_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut ; - // rule RL_m_slave_xactor_ug_slave_u_w_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = + // rule RL_m_slave_xactor_slvSynth_wSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut = m_slave_xactor_shim_wff$FULL_N && - m_slave_xactor_ug_slave_u_w_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut ; - // rule RL_m_slave_xactor_ug_slave_u_ar_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = - m_slave_xactor_ug_slave_u_ar_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_arSynth_snk_putWire$whas && !m_slave_xactor_shim_arff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_r_setPeek - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + // rule RL_m_slave_xactor_slvSynth_rSynth_src_setPeek + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek = m_slave_xactor_shim_rff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek = m_slave_xactor_shim_rff$EMPTY_N ; - // rule RL_m_slave_xactor_ug_slave_u_r_warnDoDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = - m_slave_xactor_ug_slave_u_r_dropWire$whas && + // rule RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas && !m_slave_xactor_shim_rff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop ; - // rule RL_m_slave_xactor_ug_slave_u_r_doDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = + // rule RL_m_slave_xactor_slvSynth_rSynth_src_doDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop = m_slave_xactor_shim_rff$EMPTY_N && - m_slave_xactor_ug_slave_u_r_dropWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop ; // rule RL_m_rl_process_rd_req assign CAN_FIRE_RL_m_rl_process_rd_req = @@ -3552,12 +3557,12 @@ module mkPLIC_16_2_7(CLK, !m_f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - // rule RL_m_slave_xactor_ug_slave_u_ar_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = + // rule RL_m_slave_xactor_slvSynth_arSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut = m_slave_xactor_shim_arff$FULL_N && - m_slave_xactor_ug_slave_u_ar_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + m_slave_xactor_slvSynth_arSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut ; // rule RL_m_slave_xactor_do_clear assign CAN_FIRE_RL_m_slave_xactor_do_clear = m_slave_xactor_clearing ; @@ -3566,139 +3571,139 @@ module mkPLIC_16_2_7(CLK, // inputs to muxes for submodule ports assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd0 && + addr_offset__h14599[16:12] == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd1 && + addr_offset__h14599[16:12] == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd0 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd1 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd10 && + source_id__h69011 == 10'd10 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd11 && + source_id__h69011 == 10'd11 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd12 && + source_id__h69011 == 10'd12 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd13 && + source_id__h69011 == 10'd13 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd14 && + source_id__h69011 == 10'd14 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd15 && + source_id__h69011 == 10'd15 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd16 && + source_id__h69011 == 10'd16 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd2 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd2 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd3 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd3 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd4 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd4 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd5 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd5 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd6 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd6 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd7 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd7 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd8 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd8 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd9 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd9 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[11:2] == 10'd0 && + addr_offset__h28467[11:2] == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && @@ -3823,178 +3828,178 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h29659 == 10'd0 && + (source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h29659 == 10'd1 && + (source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h29659 == 10'd10 && + (source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h29659 == 10'd11 && + (source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h29659 == 10'd12 && + (source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h29659 == 10'd13 && + (source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h29659 == 10'd14 && + (source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h29659 == 10'd15 && + (source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h29659 == 10'd16 && + (source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h29659 == 10'd2 && + (source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h29659 == 10'd3 && + (source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h29659 == 10'd4 && + (source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h29659 == 10'd5 && + (source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h29659 == 10'd6 && + (source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h29659 == 10'd7 && + (source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h29659 == 10'd8 && + (source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h29659 == 10'd9 && + (source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h29659 == 10'd0 && + (source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h29659 == 10'd1 && + (source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h29659 == 10'd10 && + (source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h29659 == 10'd11 && + (source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h29659 == 10'd12 && + (source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h29659 == 10'd13 && + (source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h29659 == 10'd14 && + (source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h29659 == 10'd15 && + (source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h29659 == 10'd16 && + (source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h29659 == 10'd2 && + (source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h29659 == 10'd3 && + (source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h29659 == 10'd4 && + (source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h29659 == 10'd5 && + (source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h29659 == 10'd6 && + (source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h29659 == 10'd7 && + (source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h29659 == 10'd8 && + (source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h29659 == 10'd9 && + (source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1988 ; // inlined wires - assign m_slave_xactor_ug_slave_u_aw_putWire$wget = + assign m_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -4005,16 +4010,16 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion } ; - assign m_slave_xactor_ug_slave_u_aw_putWire$whas = + assign m_slave_xactor_slvSynth_awSynth_snk_putWire$whas = axi4_slave_awvalid && m_slave_xactor_shim_awff$FULL_N ; - assign m_slave_xactor_ug_slave_u_w_putWire$wget = + assign m_slave_xactor_slvSynth_wSynth_snk_putWire$wget = { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, axi4_slave_wuser } ; - assign m_slave_xactor_ug_slave_u_w_putWire$whas = + assign m_slave_xactor_slvSynth_wSynth_snk_putWire$whas = axi4_slave_wvalid && m_slave_xactor_shim_wff$FULL_N ; - assign m_slave_xactor_ug_slave_u_ar_putWire$wget = + assign m_slave_xactor_slvSynth_arSynth_snk_putWire$wget = { axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -4025,13 +4030,13 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion } ; - assign m_slave_xactor_ug_slave_u_ar_putWire$whas = + assign m_slave_xactor_slvSynth_arSynth_snk_putWire$whas = axi4_slave_arvalid && m_slave_xactor_shim_arff$FULL_N ; - assign m_slave_xactor_ug_slave_u_r_peekWire$wget = + assign m_slave_xactor_slvSynth_rSynth_src_peekWire$wget = { m_slave_xactor_shim_rff$D_OUT, 1'd0 } ; - assign m_slave_xactor_ug_slave_u_b_dropWire$whas = + assign m_slave_xactor_slvSynth_bSynth_src_dropWire$whas = m_slave_xactor_shim_bff$EMPTY_N && axi4_slave_bready ; - assign m_slave_xactor_ug_slave_u_r_dropWire$whas = + assign m_slave_xactor_slvSynth_rSynth_src_dropWire$whas = m_slave_xactor_shim_rff$EMPTY_N && axi4_slave_rready ; // register m_cfg_verbosity @@ -4054,30 +4059,30 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_servicing_source_0 assign m_vrg_servicing_source_0$D_IN = MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h25318 : + max_id__h25377 : 5'd0 ; assign m_vrg_servicing_source_0$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd0 && + addr_offset__h14599[16:12] == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[16:12] == 5'd0 && + addr_offset__h28467[16:12] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 assign m_vrg_servicing_source_1$D_IN = MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h25318 : + max_id__h25377 : 5'd0 ; assign m_vrg_servicing_source_1$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd1 && + addr_offset__h14599[16:12] == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[16:12] == 5'd1 && + addr_offset__h28467[16:12] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4086,10 +4091,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_0$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd0 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd0 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4098,10 +4103,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_1$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd1 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4110,11 +4115,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_10$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd10 && + source_id__h69011 == 10'd10 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4123,11 +4128,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_11$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd11 && + source_id__h69011 == 10'd11 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4136,11 +4141,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_12$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd12 && + source_id__h69011 == 10'd12 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4149,11 +4154,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_13$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd13 && + source_id__h69011 == 10'd13 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4162,11 +4167,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_14$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd14 && + source_id__h69011 == 10'd14 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4175,11 +4180,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_15$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd15 && + source_id__h69011 == 10'd15 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4188,11 +4193,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_16$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd16 && + source_id__h69011 == 10'd16 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4201,10 +4206,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_2$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd2 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd2 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4213,10 +4218,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_3$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd3 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd3 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4225,10 +4230,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_4$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd4 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd4 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4237,10 +4242,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_5$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd5 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd5 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4249,10 +4254,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_6$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd6 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd6 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4261,10 +4266,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_7$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd7 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd7 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4273,10 +4278,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_8$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd8 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd8 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4285,17 +4290,17 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_9$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd9 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd9 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 assign m_vrg_source_ip_0$D_IN = 1'd0 ; assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd0 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4307,7 +4312,7 @@ module mkPLIC_16_2_7(CLK, v_sources_0_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_1$EN = !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4319,7 +4324,7 @@ module mkPLIC_16_2_7(CLK, v_sources_9_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_10$EN = !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4331,7 +4336,7 @@ module mkPLIC_16_2_7(CLK, v_sources_10_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_11$EN = !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4343,7 +4348,7 @@ module mkPLIC_16_2_7(CLK, v_sources_11_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_12$EN = !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4355,7 +4360,7 @@ module mkPLIC_16_2_7(CLK, v_sources_12_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_13$EN = !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4367,7 +4372,7 @@ module mkPLIC_16_2_7(CLK, v_sources_13_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_14$EN = !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4379,7 +4384,7 @@ module mkPLIC_16_2_7(CLK, v_sources_14_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_15$EN = !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4391,7 +4396,7 @@ module mkPLIC_16_2_7(CLK, v_sources_15_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_16$EN = !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4403,7 +4408,7 @@ module mkPLIC_16_2_7(CLK, v_sources_1_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_2$EN = !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4415,7 +4420,7 @@ module mkPLIC_16_2_7(CLK, v_sources_2_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_3$EN = !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4427,7 +4432,7 @@ module mkPLIC_16_2_7(CLK, v_sources_3_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_4$EN = !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4439,7 +4444,7 @@ module mkPLIC_16_2_7(CLK, v_sources_4_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_5$EN = !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4451,7 +4456,7 @@ module mkPLIC_16_2_7(CLK, v_sources_5_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_6$EN = !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4463,7 +4468,7 @@ module mkPLIC_16_2_7(CLK, v_sources_6_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_7$EN = !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4475,7 +4480,7 @@ module mkPLIC_16_2_7(CLK, v_sources_7_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_8$EN = !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4487,7 +4492,7 @@ module mkPLIC_16_2_7(CLK, v_sources_8_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_9$EN = !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4495,18 +4500,18 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[11:2] == 10'd0 && + addr_offset__h28467[11:2] == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4516,7 +4521,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4526,7 +4531,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4536,7 +4541,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4546,7 +4551,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4556,7 +4561,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4566,7 +4571,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4576,7 +4581,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4586,7 +4591,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4596,7 +4601,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4606,7 +4611,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4616,7 +4621,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4626,7 +4631,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4636,7 +4641,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4646,7 +4651,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4656,7 +4661,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4666,7 +4671,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4676,7 +4681,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4967,17 +4972,17 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_shim_arff assign m_slave_xactor_shim_arff$D_IN = - m_slave_xactor_ug_slave_u_ar_putWire$wget ; + m_slave_xactor_slvSynth_arSynth_snk_putWire$wget ; assign m_slave_xactor_shim_arff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut ; assign m_slave_xactor_shim_arff$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; assign m_slave_xactor_shim_arff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_awff assign m_slave_xactor_shim_awff$D_IN = - m_slave_xactor_ug_slave_u_aw_putWire$wget ; + m_slave_xactor_slvSynth_awSynth_snk_putWire$wget ; assign m_slave_xactor_shim_awff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut ; assign m_slave_xactor_shim_awff$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_awff$CLR = m_slave_xactor_clearing ; @@ -4989,27 +4994,27 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3123 } ; assign m_slave_xactor_shim_bff$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_bff$DEQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop ; assign m_slave_xactor_shim_bff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_rff assign m_slave_xactor_shim_rff$D_IN = { m_slave_xactor_shim_arff$D_OUT[97:93], - x__h27766, + x__h27825, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 ? 2'd3 : IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877, 1'd1 } ; assign m_slave_xactor_shim_rff$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; assign m_slave_xactor_shim_rff$DEQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop ; assign m_slave_xactor_shim_rff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_wff assign m_slave_xactor_shim_wff$D_IN = - m_slave_xactor_ug_slave_u_w_putWire$wget[73:1] ; + m_slave_xactor_slvSynth_wSynth_snk_putWire$wget[73:1] ; assign m_slave_xactor_shim_wff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut ; assign m_slave_xactor_shim_wff$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_wff$CLR = m_slave_xactor_clearing ; @@ -5018,14 +5023,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 : - ((x__h25030 == 32'h00200000) ? + ((x__h25089 == 32'h00200000) ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 : - x__h25030 != 32'h00200004 || + x__h25089 != 32'h00200004 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 || - x__h25371 != 5'd0) ; + x__h25430 != 5'd0) ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - addr_offset__h14540[11:2] == 10'd0 || + addr_offset__h14599[11:2] == 10'd0 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 : (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 : @@ -5036,7 +5041,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308) ? 2'd0 : 2'd2) : - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 ; + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d876 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 ? @@ -5045,7 +5050,7 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d875 ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - ((addr_offset__h14540[11:2] != 10'd0 && + ((addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106) ? 2'd0 : 2'd2) : @@ -5054,14 +5059,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 : - ((x__h25030 == 32'h00200000) ? + ((x__h25089 == 32'h00200000) ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 : - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0) ; + x__h25430 == 5'd0) ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d888 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - addr_offset__h14540[11:2] != 10'd0 && + addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 : (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 : @@ -5070,14 +5075,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 : - ((x__h68623 == 32'h00200000) ? + ((x__h68682 == 32'h00200000) ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 : - x__h68623 != 32'h00200004 || + x__h68682 != 32'h00200004 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 || !SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - addr_offset__h28408[11:2] == 10'd0 || + addr_offset__h28467[11:2] == 10'd0 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 : (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 : @@ -5088,7 +5093,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025) ? 2'd0 : 2'd2) : - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 ; + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3122 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 ? @@ -5097,7 +5102,7 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3121 ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3123 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - ((addr_offset__h28408[11:2] != 10'd0 && + ((addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959) ? 2'd0 : 2'd2) : @@ -5106,14 +5111,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 : - ((x__h68623 == 32'h00200000) ? + ((x__h68682 == 32'h00200000) ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 : - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3131 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 : (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 : @@ -5449,23 +5454,23 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200000 && + x__h25089 == 32'h00200000 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 = !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0 && + x__h25430 == 5'd0 && m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810 = !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0 && + x__h25430 == 5'd0 && m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822 = @@ -5473,9 +5478,9 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 != 5'd0 ; + x__h25430 != 5'd0 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && @@ -5493,7 +5498,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h30987 <= 10'd16 ; + source_id__h31046 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5501,7 +5506,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h32197 <= 10'd16 ; + source_id__h32256 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5509,7 +5514,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h33407 <= 10'd16 ; + source_id__h33466 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5517,7 +5522,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h34617 <= 10'd16 ; + source_id__h34676 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5525,7 +5530,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h35827 <= 10'd16 ; + source_id__h35886 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5533,7 +5538,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h37037 <= 10'd16 ; + source_id__h37096 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5541,7 +5546,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h38247 <= 10'd16 ; + source_id__h38306 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5549,7 +5554,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h39457 <= 10'd16 ; + source_id__h39516 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5557,7 +5562,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h40667 <= 10'd16 ; + source_id__h40726 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5565,7 +5570,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h41877 <= 10'd16 ; + source_id__h41936 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5573,7 +5578,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h43087 <= 10'd16 ; + source_id__h43146 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5581,7 +5586,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h44297 <= 10'd16 ; + source_id__h44356 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5589,7 +5594,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h45507 <= 10'd16 ; + source_id__h45566 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5597,7 +5602,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h46717 <= 10'd16 ; + source_id__h46776 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5605,7 +5610,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h47927 <= 10'd16 ; + source_id__h47986 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5613,7 +5618,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h49137 <= 10'd16 ; + source_id__h49196 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5621,7 +5626,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h50347 <= 10'd16 ; + source_id__h50406 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5629,7 +5634,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h51557 <= 10'd16 ; + source_id__h51616 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5637,7 +5642,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h52767 <= 10'd16 ; + source_id__h52826 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5645,7 +5650,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h53977 <= 10'd16 ; + source_id__h54036 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5653,7 +5658,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h55187 <= 10'd16 ; + source_id__h55246 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5661,7 +5666,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h56397 <= 10'd16 ; + source_id__h56456 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5669,7 +5674,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h57607 <= 10'd16 ; + source_id__h57666 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5677,7 +5682,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h58817 <= 10'd16 ; + source_id__h58876 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5685,7 +5690,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h60027 <= 10'd16 ; + source_id__h60086 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5693,7 +5698,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h61237 <= 10'd16 ; + source_id__h61296 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5701,7 +5706,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h62447 <= 10'd16 ; + source_id__h62506 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5709,7 +5714,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h63657 <= 10'd16 ; + source_id__h63716 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5717,7 +5722,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h64867 <= 10'd16 ; + source_id__h64926 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5725,7 +5730,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h66077 <= 10'd16 ; + source_id__h66136 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5733,7 +5738,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h67287 <= 10'd16 ; + source_id__h67346 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5745,14 +5750,14 @@ module mkPLIC_16_2_7(CLK, assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200000 && + x__h68682 == 32'h00200000 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200000 && + x__h68682 == 32'h00200000 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 = @@ -5760,14 +5765,14 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 && m_cfg_verbosity != 4'd0 ; @@ -5776,10631 +5781,10631 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && !SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; - assign NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439 = + assign NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447 = + assign NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455 = + assign NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463 = + assign NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471 = + assign NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479 = + assign NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487 = + assign NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490 = !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_16 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368 = + assign NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375 = + assign NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383 = + assign NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391 = + assign NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399 = + assign NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407 = + assign NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415 = + assign NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423 = + assign NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431 = + assign NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo10 = - (source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo100 = - (source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo865 ; assign _dfoo1002 = - (source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo867 ; assign _dfoo1004 = - (source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo869 ; assign _dfoo1006 = - (source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo871 ; assign _dfoo1008 = - (source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo873 ; assign _dfoo1010 = - (source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo875 ; assign _dfoo1012 = - (source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo877 ; assign _dfoo1014 = - (source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo879 ; assign _dfoo1016 = - (source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo881 ; assign _dfoo1018 = - (source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo883 ; assign _dfoo102 = - (source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo953 ; assign _dfoo1090 = - (source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo955 ; assign _dfoo1092 = - (source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo957 ; assign _dfoo1094 = - (source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo959 ; assign _dfoo1096 = - (source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo961 ; assign _dfoo1098 = - (source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo963 ; assign _dfoo11 = - source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo110 = - (source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo965 ; assign _dfoo1102 = - (source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo967 ; assign _dfoo1104 = - (source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo969 ; assign _dfoo1106 = - (source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo971 ; assign _dfoo1108 = - (source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo973 ; assign _dfoo1110 = - (source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo975 ; assign _dfoo1112 = - (source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo977 ; assign _dfoo1114 = - (source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo979 ; assign _dfoo1116 = - (source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo981 ; assign _dfoo1118 = - (source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo983 ; assign _dfoo112 = - (source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo985 ; assign _dfoo1122 = - (source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo987 ; assign _dfoo1124 = - (source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo989 ; assign _dfoo1126 = - (source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo991 ; assign _dfoo1128 = - (source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo993 ; assign _dfoo1130 = - (source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo995 ; assign _dfoo1132 = - (source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo997 ; assign _dfoo1134 = - (source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo999 ; assign _dfoo1136 = - (source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1003 ; assign _dfoo114 = - (source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo120 = - (source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1103 ; assign _dfoo124 = - (source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1123 ; assign _dfoo126 = - (source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1143 ; assign _dfoo128 = - (source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo130 = - (source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1233 ; assign _dfoo137 = - source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo1 ; assign _dfoo1370 = - (source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1243 ; assign _dfoo138 = - (source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1253 ; assign _dfoo139 = - source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo3 ; assign _dfoo1390 = - (source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1263 ; assign _dfoo14 = - (source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo140 = - (source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1273 ; assign _dfoo141 = - source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo5 ; assign _dfoo1410 = - (source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1283 ; assign _dfoo142 = - (source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo7 ; assign _dfoo1430 = - (source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo9 ; assign _dfoo1450 = - (source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo11 ; assign _dfoo1470 = - (source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo13 ; assign _dfoo1490 = - (source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1363 ; assign _dfoo15 = - source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo150 = - (source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1373 ; assign _dfoo151 = - source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo15 ; assign _dfoo1510 = - (source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1383 ; assign _dfoo152 = - (source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1393 ; assign _dfoo153 = - source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo17 ; assign _dfoo1530 = - (source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1403 ; assign _dfoo154 = - (source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1413 ; assign _dfoo155 = - source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo19 ; assign _dfoo1550 = - (source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1423 ; assign _dfoo156 = - (source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo21 ; assign _dfoo1570 = - (source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo23 ; assign _dfoo1590 = - (source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo160 = - (source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo25 ; assign _dfoo1610 = - (source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo27 ; assign _dfoo1630 = - (source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1503 ; assign _dfoo164 = - (source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1513 ; assign _dfoo165 = - source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo29 ; assign _dfoo1650 = - (source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1523 ; assign _dfoo166 = - (source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1533 ; assign _dfoo167 = - source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo31 ; assign _dfoo1670 = - (source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1543 ; assign _dfoo168 = - (source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1553 ; assign _dfoo169 = - source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo33 ; assign _dfoo1690 = - (source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1563 ; assign _dfoo17 = - source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo170 = - (source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo35 ; assign _dfoo1710 = - (source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo37 ; assign _dfoo1730 = - (source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo39 ; assign _dfoo1750 = - (source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1633 ; assign _dfoo177 = - source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo41 ; assign _dfoo1770 = - (source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1643 ; assign _dfoo178 = - (source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1653 ; assign _dfoo179 = - source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo43 ; assign _dfoo1790 = - (source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1663 ; assign _dfoo18 = - (source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo180 = - (source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1673 ; assign _dfoo181 = - source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo45 ; assign _dfoo1810 = - (source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1683 ; assign _dfoo182 = - (source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1693 ; assign _dfoo183 = - source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo47 ; assign _dfoo1830 = - (source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo49 ; assign _dfoo1850 = - (source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo51 ; assign _dfoo1870 = - (source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo53 ; assign _dfoo1890 = - (source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo190 = - (source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1773 ; assign _dfoo191 = - source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo55 ; assign _dfoo1910 = - (source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1783 ; assign _dfoo192 = - (source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1793 ; assign _dfoo193 = - source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo57 ; assign _dfoo1930 = - (source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1803 ; assign _dfoo194 = - (source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1813 ; assign _dfoo195 = - source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo59 ; assign _dfoo1950 = - (source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1823 ; assign _dfoo196 = - (source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1833 ; assign _dfoo197 = - source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo61 ; assign _dfoo1970 = - (source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo63 ; assign _dfoo1990 = - (source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo20 = - (source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo200 = - (source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo65 ; assign _dfoo2010 = - (source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo67 ; assign _dfoo2030 = - (source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h29659 == 10'd16 && + source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h29659 == 10'd15 && + source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h29659 == 10'd14 && + source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h29659 == 10'd13 && + source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h29659 == 10'd12 && + source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h29659 == 10'd11 && + source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h29659 == 10'd10 && + source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h29659 == 10'd9 && + source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h29659 == 10'd8 && + source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h29659 == 10'd7 && + source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1923 ; assign _dfoo206 = - (source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h29659 == 10'd6 && + source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h29659 == 10'd5 && + source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h29659 == 10'd4 && + source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h29659 == 10'd3 && + source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h29659 == 10'd2 && + source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h29659 == 10'd1 && + source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h29659 == 10'd0 && + source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h29659 == 10'd16 && + source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h29659 == 10'd15 && + source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h29659 == 10'd14 && + source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1943 ; assign _dfoo208 = - (source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h29659 == 10'd13 && + source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h29659 == 10'd12 && + source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h29659 == 10'd11 && + source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h29659 == 10'd10 && + source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h29659 == 10'd9 && + source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h29659 == 10'd8 && + source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h29659 == 10'd7 && + source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h29659 == 10'd6 && + source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h29659 == 10'd5 && + source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h29659 == 10'd4 && + source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1963 ; assign _dfoo21 = - source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo210 = - (source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h29659 == 10'd3 && + source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h29659 == 10'd2 && + source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h29659 == 10'd1 && + source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h29659 == 10'd0 && + source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1971 ; assign _dfoo212 = - (source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo220 = - (source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo160 ; assign _dfoo23 = - source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo230 = - (source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo240 = - (source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo180 ; assign _dfoo25 = - source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo250 = - (source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo260 = - (source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo200 ; assign _dfoo27 = - source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo270 = - (source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo204 ; assign _dfoo273 = - source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo137 ; assign _dfoo274 = - (source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo206 ; assign _dfoo275 = - source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo139 ; assign _dfoo276 = - (source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo208 ; assign _dfoo277 = - source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo141 ; assign _dfoo278 = - (source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo210 ; assign _dfoo279 = - source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo143 ; assign _dfoo28 = - (source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo280 = - (source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo212 ; assign _dfoo281 = - source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo145 ; assign _dfoo282 = - (source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo214 ; assign _dfoo283 = - source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo147 ; assign _dfoo284 = - (source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo216 ; assign _dfoo285 = - source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo149 ; assign _dfoo286 = - (source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo218 ; assign _dfoo287 = - source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo151 ; assign _dfoo288 = - (source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo220 ; assign _dfoo289 = - source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo153 ; assign _dfoo29 = - source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo290 = - (source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo222 ; assign _dfoo291 = - source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo155 ; assign _dfoo292 = - (source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo224 ; assign _dfoo293 = - source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo157 ; assign _dfoo294 = - (source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo226 ; assign _dfoo295 = - source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo159 ; assign _dfoo296 = - (source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo228 ; assign _dfoo297 = - source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo161 ; assign _dfoo298 = - (source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo230 ; assign _dfoo299 = - source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo163 ; assign _dfoo3 = - source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo30 = - (source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo300 = - (source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo232 ; assign _dfoo301 = - source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo165 ; assign _dfoo302 = - (source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo234 ; assign _dfoo303 = - source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo167 ; assign _dfoo304 = - (source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo236 ; assign _dfoo305 = - source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo169 ; assign _dfoo306 = - (source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo238 ; assign _dfoo307 = - source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo171 ; assign _dfoo308 = - (source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo240 ; assign _dfoo309 = - source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo173 ; assign _dfoo31 = - source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo310 = - (source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo242 ; assign _dfoo311 = - source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo175 ; assign _dfoo312 = - (source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo244 ; assign _dfoo313 = - source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo177 ; assign _dfoo314 = - (source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo246 ; assign _dfoo315 = - source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo179 ; assign _dfoo316 = - (source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo248 ; assign _dfoo317 = - source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo181 ; assign _dfoo318 = - (source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo250 ; assign _dfoo319 = - source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo183 ; assign _dfoo32 = - (source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo320 = - (source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo252 ; assign _dfoo321 = - source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo185 ; assign _dfoo322 = - (source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo254 ; assign _dfoo323 = - source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo187 ; assign _dfoo324 = - (source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo256 ; assign _dfoo325 = - source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo189 ; assign _dfoo326 = - (source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo258 ; assign _dfoo327 = - source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo191 ; assign _dfoo328 = - (source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo260 ; assign _dfoo329 = - source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo193 ; assign _dfoo33 = - source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo330 = - (source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo262 ; assign _dfoo331 = - source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo195 ; assign _dfoo332 = - (source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo264 ; assign _dfoo333 = - source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo197 ; assign _dfoo334 = - (source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo266 ; assign _dfoo335 = - source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo199 ; assign _dfoo336 = - (source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo268 ; assign _dfoo337 = - source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo201 ; assign _dfoo338 = - (source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo270 ; assign _dfoo339 = - source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo203 ; assign _dfoo34 = - (source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo340 = - (source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo280 ; assign _dfoo35 = - source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo350 = - (source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo360 = - (source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo300 ; assign _dfoo37 = - source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo370 = - (source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo380 = - (source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo320 ; assign _dfoo39 = - source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo390 = - (source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo40 = - (source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo400 = - (source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo340 ; assign _dfoo409 = - source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo273 ; assign _dfoo41 = - source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo410 = - (source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo342 ; assign _dfoo411 = - source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo275 ; assign _dfoo412 = - (source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo344 ; assign _dfoo413 = - source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo277 ; assign _dfoo414 = - (source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo346 ; assign _dfoo415 = - source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo279 ; assign _dfoo416 = - (source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo348 ; assign _dfoo417 = - source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo281 ; assign _dfoo418 = - (source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo350 ; assign _dfoo419 = - source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo283 ; assign _dfoo42 = - (source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo420 = - (source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo352 ; assign _dfoo421 = - source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo285 ; assign _dfoo422 = - (source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo354 ; assign _dfoo423 = - source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo287 ; assign _dfoo424 = - (source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo356 ; assign _dfoo425 = - source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo289 ; assign _dfoo426 = - (source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo358 ; assign _dfoo427 = - source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo291 ; assign _dfoo428 = - (source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo360 ; assign _dfoo429 = - source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo293 ; assign _dfoo43 = - source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo430 = - (source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo362 ; assign _dfoo431 = - source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo295 ; assign _dfoo432 = - (source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo364 ; assign _dfoo433 = - source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo297 ; assign _dfoo434 = - (source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo366 ; assign _dfoo435 = - source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo299 ; assign _dfoo436 = - (source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo368 ; assign _dfoo437 = - source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo301 ; assign _dfoo438 = - (source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo370 ; assign _dfoo439 = - source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo303 ; assign _dfoo44 = - (source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo440 = - (source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo372 ; assign _dfoo441 = - source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo305 ; assign _dfoo442 = - (source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo374 ; assign _dfoo443 = - source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo307 ; assign _dfoo444 = - (source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo376 ; assign _dfoo445 = - source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo309 ; assign _dfoo446 = - (source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo378 ; assign _dfoo447 = - source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo311 ; assign _dfoo448 = - (source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo380 ; assign _dfoo449 = - source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo313 ; assign _dfoo45 = - source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo450 = - (source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo382 ; assign _dfoo451 = - source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo315 ; assign _dfoo452 = - (source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo384 ; assign _dfoo453 = - source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo317 ; assign _dfoo454 = - (source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo386 ; assign _dfoo455 = - source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo319 ; assign _dfoo456 = - (source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo388 ; assign _dfoo457 = - source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo321 ; assign _dfoo458 = - (source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo390 ; assign _dfoo459 = - source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo323 ; assign _dfoo46 = - (source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo460 = - (source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo392 ; assign _dfoo461 = - source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo325 ; assign _dfoo462 = - (source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo394 ; assign _dfoo463 = - source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo327 ; assign _dfoo464 = - (source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo396 ; assign _dfoo465 = - source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo329 ; assign _dfoo466 = - (source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo398 ; assign _dfoo467 = - source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo331 ; assign _dfoo468 = - (source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo400 ; assign _dfoo469 = - source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo333 ; assign _dfoo47 = - source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo470 = - (source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo402 ; assign _dfoo471 = - source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo335 ; assign _dfoo472 = - (source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo404 ; assign _dfoo473 = - source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo337 ; assign _dfoo474 = - (source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo406 ; assign _dfoo475 = - source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo339 ; assign _dfoo476 = - (source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo480 = - (source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo420 ; assign _dfoo49 = - source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo490 = - (source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo430 ; assign _dfoo5 = - source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo50 = - (source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo500 = - (source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo440 ; assign _dfoo51 = - source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo510 = - (source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo520 = - (source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo460 ; assign _dfoo53 = - source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo530 = - (source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo540 = - (source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo476 ; assign _dfoo545 = - source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo409 ; assign _dfoo546 = - (source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo478 ; assign _dfoo547 = - source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo411 ; assign _dfoo548 = - (source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo480 ; assign _dfoo549 = - source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo413 ; assign _dfoo55 = - source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo550 = - (source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo482 ; assign _dfoo551 = - source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo415 ; assign _dfoo552 = - (source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo484 ; assign _dfoo553 = - source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo417 ; assign _dfoo554 = - (source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo486 ; assign _dfoo555 = - source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo419 ; assign _dfoo556 = - (source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo488 ; assign _dfoo557 = - source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo421 ; assign _dfoo558 = - (source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo490 ; assign _dfoo559 = - source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo423 ; assign _dfoo56 = - (source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo560 = - (source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo492 ; assign _dfoo561 = - source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo425 ; assign _dfoo562 = - (source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo494 ; assign _dfoo563 = - source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo427 ; assign _dfoo564 = - (source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo496 ; assign _dfoo565 = - source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo429 ; assign _dfoo566 = - (source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo498 ; assign _dfoo567 = - source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo431 ; assign _dfoo568 = - (source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo500 ; assign _dfoo569 = - source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo433 ; assign _dfoo57 = - source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo570 = - (source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo502 ; assign _dfoo571 = - source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo435 ; assign _dfoo572 = - (source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo504 ; assign _dfoo573 = - source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo437 ; assign _dfoo574 = - (source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo506 ; assign _dfoo575 = - source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo439 ; assign _dfoo576 = - (source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo508 ; assign _dfoo577 = - source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo441 ; assign _dfoo578 = - (source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo510 ; assign _dfoo579 = - source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo443 ; assign _dfoo58 = - (source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo580 = - (source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo512 ; assign _dfoo581 = - source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo445 ; assign _dfoo582 = - (source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo514 ; assign _dfoo583 = - source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo447 ; assign _dfoo584 = - (source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo516 ; assign _dfoo585 = - source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo449 ; assign _dfoo586 = - (source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo518 ; assign _dfoo587 = - source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo451 ; assign _dfoo588 = - (source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo520 ; assign _dfoo589 = - source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo453 ; assign _dfoo59 = - source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo590 = - (source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo522 ; assign _dfoo591 = - source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo455 ; assign _dfoo592 = - (source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo524 ; assign _dfoo593 = - source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo457 ; assign _dfoo594 = - (source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo526 ; assign _dfoo595 = - source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo459 ; assign _dfoo596 = - (source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo528 ; assign _dfoo597 = - source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo461 ; assign _dfoo598 = - (source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo530 ; assign _dfoo599 = - source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo463 ; assign _dfoo6 = - (source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo60 = - (source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo600 = - (source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo532 ; assign _dfoo601 = - source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo465 ; assign _dfoo602 = - (source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo534 ; assign _dfoo603 = - source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo467 ; assign _dfoo604 = - (source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo536 ; assign _dfoo605 = - source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo469 ; assign _dfoo606 = - (source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo538 ; assign _dfoo607 = - source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo471 ; assign _dfoo608 = - (source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo540 ; assign _dfoo609 = - source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo473 ; assign _dfoo61 = - source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo610 = - (source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo542 ; assign _dfoo611 = - source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo475 ; assign _dfoo612 = - (source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo620 = - (source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo560 ; assign _dfoo63 = - source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo630 = - (source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo640 = - (source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo580 ; assign _dfoo65 = - source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo650 = - (source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo660 = - (source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo600 ; assign _dfoo67 = - source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo670 = - (source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo680 = - (source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo612 ; assign _dfoo681 = - source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo545 ; assign _dfoo682 = - (source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo614 ; assign _dfoo683 = - source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo547 ; assign _dfoo684 = - (source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo616 ; assign _dfoo685 = - source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo549 ; assign _dfoo686 = - (source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo618 ; assign _dfoo687 = - source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo551 ; assign _dfoo688 = - (source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo620 ; assign _dfoo689 = - source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo553 ; assign _dfoo690 = - (source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo622 ; assign _dfoo691 = - source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo555 ; assign _dfoo692 = - (source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo624 ; assign _dfoo693 = - source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo557 ; assign _dfoo694 = - (source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo626 ; assign _dfoo695 = - source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo559 ; assign _dfoo696 = - (source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo628 ; assign _dfoo697 = - source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo561 ; assign _dfoo698 = - (source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo630 ; assign _dfoo699 = - source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo563 ; assign _dfoo7 = - source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo70 = - (source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo632 ; assign _dfoo701 = - source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo565 ; assign _dfoo702 = - (source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo634 ; assign _dfoo703 = - source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo567 ; assign _dfoo704 = - (source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo636 ; assign _dfoo705 = - source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo569 ; assign _dfoo706 = - (source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo638 ; assign _dfoo707 = - source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo571 ; assign _dfoo708 = - (source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo640 ; assign _dfoo709 = - source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo573 ; assign _dfoo710 = - (source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo642 ; assign _dfoo711 = - source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo575 ; assign _dfoo712 = - (source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo644 ; assign _dfoo713 = - source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo577 ; assign _dfoo714 = - (source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo646 ; assign _dfoo715 = - source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo579 ; assign _dfoo716 = - (source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo648 ; assign _dfoo717 = - source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo581 ; assign _dfoo718 = - (source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo650 ; assign _dfoo719 = - source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo583 ; assign _dfoo72 = - (source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo652 ; assign _dfoo721 = - source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo585 ; assign _dfoo722 = - (source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo654 ; assign _dfoo723 = - source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo587 ; assign _dfoo724 = - (source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo656 ; assign _dfoo725 = - source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo589 ; assign _dfoo726 = - (source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo658 ; assign _dfoo727 = - source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo591 ; assign _dfoo728 = - (source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo660 ; assign _dfoo729 = - source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo593 ; assign _dfoo730 = - (source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo662 ; assign _dfoo731 = - source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo595 ; assign _dfoo732 = - (source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo664 ; assign _dfoo733 = - source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo597 ; assign _dfoo734 = - (source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo666 ; assign _dfoo735 = - source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo599 ; assign _dfoo736 = - (source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo668 ; assign _dfoo737 = - source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo601 ; assign _dfoo738 = - (source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo670 ; assign _dfoo739 = - source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo603 ; assign _dfoo74 = - (source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo672 ; assign _dfoo741 = - source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo605 ; assign _dfoo742 = - (source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo674 ; assign _dfoo743 = - source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo607 ; assign _dfoo744 = - (source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo676 ; assign _dfoo745 = - source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo609 ; assign _dfoo746 = - (source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo678 ; assign _dfoo747 = - source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo611 ; assign _dfoo748 = - (source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo80 = - (source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo748 ; assign _dfoo817 = - source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo681 ; assign _dfoo818 = - (source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo750 ; assign _dfoo819 = - source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo683 ; assign _dfoo82 = - (source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo752 ; assign _dfoo821 = - source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo685 ; assign _dfoo822 = - (source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo754 ; assign _dfoo823 = - source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo687 ; assign _dfoo824 = - (source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo756 ; assign _dfoo825 = - source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo689 ; assign _dfoo826 = - (source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo758 ; assign _dfoo827 = - source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo691 ; assign _dfoo828 = - (source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo760 ; assign _dfoo829 = - source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo693 ; assign _dfoo830 = - (source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo762 ; assign _dfoo831 = - source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo695 ; assign _dfoo832 = - (source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo764 ; assign _dfoo833 = - source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo697 ; assign _dfoo834 = - (source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo766 ; assign _dfoo835 = - source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo699 ; assign _dfoo836 = - (source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo768 ; assign _dfoo837 = - source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo701 ; assign _dfoo838 = - (source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo770 ; assign _dfoo839 = - source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo703 ; assign _dfoo84 = - (source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo772 ; assign _dfoo841 = - source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo705 ; assign _dfoo842 = - (source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo774 ; assign _dfoo843 = - source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo707 ; assign _dfoo844 = - (source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo776 ; assign _dfoo845 = - source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo709 ; assign _dfoo846 = - (source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo778 ; assign _dfoo847 = - source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo711 ; assign _dfoo848 = - (source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo780 ; assign _dfoo849 = - source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo713 ; assign _dfoo850 = - (source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo782 ; assign _dfoo851 = - source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo715 ; assign _dfoo852 = - (source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo784 ; assign _dfoo853 = - source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo717 ; assign _dfoo854 = - (source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo786 ; assign _dfoo855 = - source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo719 ; assign _dfoo856 = - (source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo788 ; assign _dfoo857 = - source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo721 ; assign _dfoo858 = - (source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo790 ; assign _dfoo859 = - source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo723 ; assign _dfoo86 = - (source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo792 ; assign _dfoo861 = - source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo725 ; assign _dfoo862 = - (source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo794 ; assign _dfoo863 = - source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo727 ; assign _dfoo864 = - (source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo796 ; assign _dfoo865 = - source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo729 ; assign _dfoo866 = - (source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo798 ; assign _dfoo867 = - source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo731 ; assign _dfoo868 = - (source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo800 ; assign _dfoo869 = - source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo733 ; assign _dfoo870 = - (source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo802 ; assign _dfoo871 = - source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo735 ; assign _dfoo872 = - (source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo804 ; assign _dfoo873 = - source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo737 ; assign _dfoo874 = - (source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo806 ; assign _dfoo875 = - source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo739 ; assign _dfoo876 = - (source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo808 ; assign _dfoo877 = - source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo741 ; assign _dfoo878 = - (source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo810 ; assign _dfoo879 = - source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo743 ; assign _dfoo88 = - (source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo812 ; assign _dfoo881 = - source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo745 ; assign _dfoo882 = - (source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo814 ; assign _dfoo883 = - source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo747 ; assign _dfoo884 = - (source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo830 ; assign _dfoo9 = - source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo90 = - (source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo884 ; assign _dfoo953 = - source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo817 ; assign _dfoo954 = - (source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo886 ; assign _dfoo955 = - source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo819 ; assign _dfoo956 = - (source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo888 ; assign _dfoo957 = - source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo821 ; assign _dfoo958 = - (source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo890 ; assign _dfoo959 = - source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo823 ; assign _dfoo96 = - (source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo892 ; assign _dfoo961 = - source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo825 ; assign _dfoo962 = - (source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo894 ; assign _dfoo963 = - source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo827 ; assign _dfoo964 = - (source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo896 ; assign _dfoo965 = - source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo829 ; assign _dfoo966 = - (source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo898 ; assign _dfoo967 = - source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo831 ; assign _dfoo968 = - (source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo900 ; assign _dfoo969 = - source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo833 ; assign _dfoo970 = - (source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo902 ; assign _dfoo971 = - source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo835 ; assign _dfoo972 = - (source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo904 ; assign _dfoo973 = - source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo837 ; assign _dfoo974 = - (source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo906 ; assign _dfoo975 = - source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo839 ; assign _dfoo976 = - (source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo908 ; assign _dfoo977 = - source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo841 ; assign _dfoo978 = - (source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo910 ; assign _dfoo979 = - source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo843 ; assign _dfoo98 = - (source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo912 ; assign _dfoo981 = - source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo845 ; assign _dfoo982 = - (source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo914 ; assign _dfoo983 = - source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo847 ; assign _dfoo984 = - (source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo916 ; assign _dfoo985 = - source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo849 ; assign _dfoo986 = - (source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo918 ; assign _dfoo987 = - source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo851 ; assign _dfoo988 = - (source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo920 ; assign _dfoo989 = - source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo853 ; assign _dfoo990 = - (source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo922 ; assign _dfoo991 = - source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo855 ; assign _dfoo992 = - (source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo924 ; assign _dfoo993 = - source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo857 ; assign _dfoo994 = - (source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo926 ; assign _dfoo995 = - source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo859 ; assign _dfoo996 = - (source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo928 ; assign _dfoo997 = - source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo861 ; assign _dfoo998 = - (source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo930 ; assign _dfoo999 = - source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo863 ; - assign a__h72910 = + assign a__h72969 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 ? m_vrg_source_prio_16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3211 ; - assign a__h74915 = + assign a__h74974 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3309 ? m_vrg_source_prio_16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3305 ; - assign addr_offset__h14540 = + assign addr_offset__h14599 = m_slave_xactor_shim_arff$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h28408 = + assign addr_offset__h28467 = m_slave_xactor_shim_awff$D_OUT[92:29] - m_rg_addr_base ; - assign b__h72911 = + assign b__h72970 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3231 ; - assign b__h74916 = + assign b__h74975 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3309 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3325 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 = - addr_offset__h14540 < 64'h0000000000001000 ; + addr_offset__h14599 < 64'h0000000000001000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 = - addr_offset__h14540[11:2] <= 10'd16 ; + addr_offset__h14599[11:2] <= 10'd16 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && - addr_offset__h14540[11:2] != 10'd0 && + addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 && m_cfg_verbosity != 4'd0 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 = - addr_offset__h14540 < 64'h0000000000002000 ; + addr_offset__h14599 < 64'h0000000000002000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 = - source_id_base__h14985 <= 10'd16 ; + source_id_base__h15044 <= 10'd16 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 = - addr_offset__h14540 < 64'h0000000000003000 ; + addr_offset__h14599 < 64'h0000000000003000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 = - addr_offset__h14540[11:7] <= 5'd1 ; + addr_offset__h14599[11:7] <= 5'd1 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 = - addr_offset__h14540[16:12] <= 5'd1 ; + addr_offset__h14599[16:12] <= 5'd1 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 = m_slave_xactor_shim_arff$D_OUT[92:29] < m_rg_addr_base ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1001 = - addr_offset__h28408[11:2] == 10'd15 && + addr_offset__h28467[11:2] == 10'd15 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1003 = - addr_offset__h28408[11:2] == 10'd16 && + addr_offset__h28467[11:2] == 10'd16 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 && m_cfg_verbosity != 4'd0 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 = - addr_offset__h28408 < 64'h0000000000002000 ; + addr_offset__h28467 < 64'h0000000000002000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 = - source_id_base__h29659 <= 10'd16 ; + source_id_base__h29718 <= 10'd16 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 = - addr_offset__h28408 < 64'h0000000000003000 ; + addr_offset__h28467 < 64'h0000000000003000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 = - addr_offset__h28408[11:7] <= 5'd1 ; + addr_offset__h28467[11:7] <= 5'd1 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 = - addr_offset__h28408[11:7] == 5'd0 && + addr_offset__h28467[11:7] == 5'd0 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1028 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 = - addr_offset__h28408[11:7] == 5'd1 && + addr_offset__h28467[11:7] == 5'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1028 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 = - addr_offset__h28408[16:12] <= 5'd1 ; + addr_offset__h28467[16:12] <= 5'd1 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2996 = - addr_offset__h28408[16:12] == 5'd0 && + addr_offset__h28467[16:12] == 5'd0 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2998 = - addr_offset__h28408[16:12] == 5'd1 && + addr_offset__h28467[16:12] == 5'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 = m_slave_xactor_shim_awff$D_OUT[92:29] < m_rg_addr_base ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 = - addr_offset__h28408 < 64'h0000000000001000 ; + addr_offset__h28467 < 64'h0000000000001000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 = - addr_offset__h28408[11:2] <= 10'd16 ; + addr_offset__h28467[11:2] <= 10'd16 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d973 = - addr_offset__h28408[11:2] == 10'd1 && + addr_offset__h28467[11:2] == 10'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d975 = - addr_offset__h28408[11:2] == 10'd2 && + addr_offset__h28467[11:2] == 10'd2 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d977 = - addr_offset__h28408[11:2] == 10'd3 && + addr_offset__h28467[11:2] == 10'd3 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d979 = - addr_offset__h28408[11:2] == 10'd4 && + addr_offset__h28467[11:2] == 10'd4 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d981 = - addr_offset__h28408[11:2] == 10'd5 && + addr_offset__h28467[11:2] == 10'd5 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d983 = - addr_offset__h28408[11:2] == 10'd6 && + addr_offset__h28467[11:2] == 10'd6 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d985 = - addr_offset__h28408[11:2] == 10'd7 && + addr_offset__h28467[11:2] == 10'd7 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d987 = - addr_offset__h28408[11:2] == 10'd8 && + addr_offset__h28467[11:2] == 10'd8 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d989 = - addr_offset__h28408[11:2] == 10'd9 && + addr_offset__h28467[11:2] == 10'd9 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d991 = - addr_offset__h28408[11:2] == 10'd10 && + addr_offset__h28467[11:2] == 10'd10 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d993 = - addr_offset__h28408[11:2] == 10'd11 && + addr_offset__h28467[11:2] == 10'd11 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d995 = - addr_offset__h28408[11:2] == 10'd12 && + addr_offset__h28467[11:2] == 10'd12 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d997 = - addr_offset__h28408[11:2] == 10'd13 && + addr_offset__h28467[11:2] == 10'd13 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d999 = - addr_offset__h28408[11:2] == 10'd14 && + addr_offset__h28467[11:2] == 10'd14 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; @@ -16418,7 +16423,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_10 && m_vrg_source_prio_10 > IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d674 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; assign m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_sour_ETC___d3190 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > @@ -16433,7 +16438,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_11 && m_vrg_source_prio_11 > IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d681 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; assign m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_sour_ETC___d3195 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > @@ -16448,7 +16453,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_12 && m_vrg_source_prio_12 > IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d688 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; assign m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d3200 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > @@ -16463,7 +16468,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 && m_vrg_source_prio_13 > IF_m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_s_ETC___d695 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; assign m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d757 = m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d701 || m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_sour_ETC___d694 || @@ -16486,7 +16491,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_14 && m_vrg_source_prio_14 > IF_m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_s_ETC___d702 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; assign m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d3210 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > @@ -16501,7 +16506,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_15 && m_vrg_source_prio_15 > IF_m_vrg_source_ip_14_read__60_AND_NOT_m_vrg_s_ETC___d709 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > @@ -16515,7 +16520,7 @@ module mkPLIC_16_2_7(CLK, assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 = m_vrg_source_ip_16 && !m_vrg_source_prio_16_29_ULE_IF_m_vrg_source_ip_ETC___d717 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 || m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d715 || @@ -16523,7 +16528,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d757 ; assign m_vrg_source_ip_1_read__47_AND_NOT_m_vrg_sourc_ETC___d617 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; assign m_vrg_source_ip_2_read__48_AND_NOT_m_vrg_sourc_ETC___d3145 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > @@ -16538,7 +16543,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_2 && m_vrg_source_prio_2 > IF_m_vrg_source_ip_1_read__47_AND_NOT_m_vrg_so_ETC___d618 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; assign m_vrg_source_ip_3_read__49_AND_NOT_m_vrg_sourc_ETC___d3150 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > @@ -16553,7 +16558,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_3 && m_vrg_source_prio_3 > IF_m_vrg_source_ip_2_read__48_AND_NOT_m_vrg_so_ETC___d625 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; assign m_vrg_source_ip_4_read__50_AND_NOT_m_vrg_sourc_ETC___d3155 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > @@ -16568,7 +16573,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_4 && m_vrg_source_prio_4 > IF_m_vrg_source_ip_3_read__49_AND_NOT_m_vrg_so_ETC___d632 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; assign m_vrg_source_ip_5_read__51_AND_NOT_m_vrg_sourc_ETC___d3160 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > @@ -16583,7 +16588,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_5 && m_vrg_source_prio_5 > IF_m_vrg_source_ip_4_read__50_AND_NOT_m_vrg_so_ETC___d639 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; assign m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_sourc_ETC___d3165 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > @@ -16598,7 +16603,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_6 && m_vrg_source_prio_6 > IF_m_vrg_source_ip_5_read__51_AND_NOT_m_vrg_so_ETC___d646 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; assign m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d3170 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > @@ -16613,7 +16618,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_7 && m_vrg_source_prio_7 > IF_m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_so_ETC___d653 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; assign m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d751 = m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d659 || m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_sourc_ETC___d652 || @@ -16636,7 +16641,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_8 && m_vrg_source_prio_8 > IF_m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_so_ETC___d660 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; assign m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_sourc_ETC___d3180 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > @@ -16651,306 +16656,306 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_9 && m_vrg_source_prio_9 > IF_m_vrg_source_ip_8_read__54_AND_NOT_m_vrg_so_ETC___d667 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; assign m_vrg_source_prio_16_29_ULE_IF_m_vrg_source_ip_ETC___d717 = m_vrg_source_prio_16 <= (m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d715 ? m_vrg_source_prio_15 : IF_m_vrg_source_ip_14_read__60_AND_NOT_m_vrg_s_ETC___d709) ; - assign max_id__h25318 = + assign max_id__h25377 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d737 ; - assign rdata___1__h27806 = { rdata__h27563[31:0], 32'h0 } ; - assign rdata__h27563 = + assign rdata___1__h27865 = { rdata__h27622[31:0], 32'h0 } ; + assign rdata__h27622 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 ? 64'd0 : - y_avValue_fst__h27555 ; - assign source_id__h17021 = { addr_offset__h14540[4:0], 5'd31 } ; - assign source_id__h17128 = { addr_offset__h14540[4:0], 5'd30 } ; - assign source_id__h17201 = { addr_offset__h14540[4:0], 5'd29 } ; - assign source_id__h17274 = { addr_offset__h14540[4:0], 5'd28 } ; - assign source_id__h17347 = { addr_offset__h14540[4:0], 5'd27 } ; - assign source_id__h17420 = { addr_offset__h14540[4:0], 5'd26 } ; - assign source_id__h17493 = { addr_offset__h14540[4:0], 5'd25 } ; - assign source_id__h17566 = { addr_offset__h14540[4:0], 5'd24 } ; - assign source_id__h17639 = { addr_offset__h14540[4:0], 5'd23 } ; - assign source_id__h17712 = { addr_offset__h14540[4:0], 5'd22 } ; - assign source_id__h17785 = { addr_offset__h14540[4:0], 5'd21 } ; - assign source_id__h17858 = { addr_offset__h14540[4:0], 5'd20 } ; - assign source_id__h17931 = { addr_offset__h14540[4:0], 5'd19 } ; - assign source_id__h18004 = { addr_offset__h14540[4:0], 5'd18 } ; - assign source_id__h18077 = { addr_offset__h14540[4:0], 5'd17 } ; - assign source_id__h18150 = { addr_offset__h14540[4:0], 5'd16 } ; - assign source_id__h18223 = { addr_offset__h14540[4:0], 5'd15 } ; - assign source_id__h18296 = { addr_offset__h14540[4:0], 5'd14 } ; - assign source_id__h18369 = { addr_offset__h14540[4:0], 5'd13 } ; - assign source_id__h18442 = { addr_offset__h14540[4:0], 5'd12 } ; - assign source_id__h18515 = { addr_offset__h14540[4:0], 5'd11 } ; - assign source_id__h18588 = { addr_offset__h14540[4:0], 5'd10 } ; - assign source_id__h18661 = { addr_offset__h14540[4:0], 5'd9 } ; - assign source_id__h18734 = { addr_offset__h14540[4:0], 5'd8 } ; - assign source_id__h18807 = { addr_offset__h14540[4:0], 5'd7 } ; - assign source_id__h18880 = { addr_offset__h14540[4:0], 5'd6 } ; - assign source_id__h18953 = { addr_offset__h14540[4:0], 5'd5 } ; - assign source_id__h19026 = { addr_offset__h14540[4:0], 5'd4 } ; - assign source_id__h19099 = { addr_offset__h14540[4:0], 5'd3 } ; - assign source_id__h19172 = { addr_offset__h14540[4:0], 5'd2 } ; - assign source_id__h19245 = { addr_offset__h14540[4:0], 5'd1 } ; - assign source_id__h21494 = 10'd31 + source_id_base__h14985 ; - assign source_id__h21670 = 10'd30 + source_id_base__h14985 ; - assign source_id__h21778 = 10'd29 + source_id_base__h14985 ; - assign source_id__h21886 = 10'd28 + source_id_base__h14985 ; - assign source_id__h21994 = 10'd27 + source_id_base__h14985 ; - assign source_id__h22102 = 10'd26 + source_id_base__h14985 ; - assign source_id__h22210 = 10'd25 + source_id_base__h14985 ; - assign source_id__h22318 = 10'd24 + source_id_base__h14985 ; - assign source_id__h22426 = 10'd23 + source_id_base__h14985 ; - assign source_id__h22534 = 10'd22 + source_id_base__h14985 ; - assign source_id__h22642 = 10'd21 + source_id_base__h14985 ; - assign source_id__h22750 = 10'd20 + source_id_base__h14985 ; - assign source_id__h22858 = 10'd19 + source_id_base__h14985 ; - assign source_id__h22966 = 10'd18 + source_id_base__h14985 ; - assign source_id__h23074 = 10'd17 + source_id_base__h14985 ; - assign source_id__h23182 = 10'd16 + source_id_base__h14985 ; - assign source_id__h23290 = 10'd15 + source_id_base__h14985 ; - assign source_id__h23398 = 10'd14 + source_id_base__h14985 ; - assign source_id__h23506 = 10'd13 + source_id_base__h14985 ; - assign source_id__h23614 = 10'd12 + source_id_base__h14985 ; - assign source_id__h23722 = 10'd11 + source_id_base__h14985 ; - assign source_id__h23830 = 10'd10 + source_id_base__h14985 ; - assign source_id__h23938 = 10'd9 + source_id_base__h14985 ; - assign source_id__h24046 = 10'd8 + source_id_base__h14985 ; - assign source_id__h24154 = 10'd7 + source_id_base__h14985 ; - assign source_id__h24262 = 10'd6 + source_id_base__h14985 ; - assign source_id__h24370 = 10'd5 + source_id_base__h14985 ; - assign source_id__h24478 = 10'd4 + source_id_base__h14985 ; - assign source_id__h24586 = 10'd3 + source_id_base__h14985 ; - assign source_id__h24694 = 10'd2 + source_id_base__h14985 ; - assign source_id__h24802 = 10'd1 + source_id_base__h14985 ; - assign source_id__h30987 = { addr_offset__h28408[4:0], 5'd1 } ; - assign source_id__h32197 = { addr_offset__h28408[4:0], 5'd2 } ; - assign source_id__h33407 = { addr_offset__h28408[4:0], 5'd3 } ; - assign source_id__h34617 = { addr_offset__h28408[4:0], 5'd4 } ; - assign source_id__h35827 = { addr_offset__h28408[4:0], 5'd5 } ; - assign source_id__h37037 = { addr_offset__h28408[4:0], 5'd6 } ; - assign source_id__h38247 = { addr_offset__h28408[4:0], 5'd7 } ; - assign source_id__h39457 = { addr_offset__h28408[4:0], 5'd8 } ; - assign source_id__h40667 = { addr_offset__h28408[4:0], 5'd9 } ; - assign source_id__h41877 = { addr_offset__h28408[4:0], 5'd10 } ; - assign source_id__h43087 = { addr_offset__h28408[4:0], 5'd11 } ; - assign source_id__h44297 = { addr_offset__h28408[4:0], 5'd12 } ; - assign source_id__h45507 = { addr_offset__h28408[4:0], 5'd13 } ; - assign source_id__h46717 = { addr_offset__h28408[4:0], 5'd14 } ; - assign source_id__h47927 = { addr_offset__h28408[4:0], 5'd15 } ; - assign source_id__h49137 = { addr_offset__h28408[4:0], 5'd16 } ; - assign source_id__h50347 = { addr_offset__h28408[4:0], 5'd17 } ; - assign source_id__h51557 = { addr_offset__h28408[4:0], 5'd18 } ; - assign source_id__h52767 = { addr_offset__h28408[4:0], 5'd19 } ; - assign source_id__h53977 = { addr_offset__h28408[4:0], 5'd20 } ; - assign source_id__h55187 = { addr_offset__h28408[4:0], 5'd21 } ; - assign source_id__h56397 = { addr_offset__h28408[4:0], 5'd22 } ; - assign source_id__h57607 = { addr_offset__h28408[4:0], 5'd23 } ; - assign source_id__h58817 = { addr_offset__h28408[4:0], 5'd24 } ; - assign source_id__h60027 = { addr_offset__h28408[4:0], 5'd25 } ; - assign source_id__h61237 = { addr_offset__h28408[4:0], 5'd26 } ; - assign source_id__h62447 = { addr_offset__h28408[4:0], 5'd27 } ; - assign source_id__h63657 = { addr_offset__h28408[4:0], 5'd28 } ; - assign source_id__h64867 = { addr_offset__h28408[4:0], 5'd29 } ; - assign source_id__h66077 = { addr_offset__h28408[4:0], 5'd30 } ; - assign source_id__h67287 = { addr_offset__h28408[4:0], 5'd31 } ; - assign source_id__h68952 = { 5'd0, x__h69004 } ; - assign source_id_base__h14985 = { addr_offset__h14540[4:0], 5'h0 } ; - assign source_id_base__h29659 = { addr_offset__h28408[4:0], 5'h0 } ; - assign v__h14777 = { 61'd0, x__h14848 } ; - assign v__h15027 = { 32'd0, v_ip__h15030 } ; - assign v__h19501 = { 32'd0, v_ie__h19504 } ; - assign v__h25119 = { 61'd0, x__h25190 } ; - assign v__h26816 = + y_avValue_fst__h27614 ; + assign source_id__h17080 = { addr_offset__h14599[4:0], 5'd31 } ; + assign source_id__h17187 = { addr_offset__h14599[4:0], 5'd30 } ; + assign source_id__h17260 = { addr_offset__h14599[4:0], 5'd29 } ; + assign source_id__h17333 = { addr_offset__h14599[4:0], 5'd28 } ; + assign source_id__h17406 = { addr_offset__h14599[4:0], 5'd27 } ; + assign source_id__h17479 = { addr_offset__h14599[4:0], 5'd26 } ; + assign source_id__h17552 = { addr_offset__h14599[4:0], 5'd25 } ; + assign source_id__h17625 = { addr_offset__h14599[4:0], 5'd24 } ; + assign source_id__h17698 = { addr_offset__h14599[4:0], 5'd23 } ; + assign source_id__h17771 = { addr_offset__h14599[4:0], 5'd22 } ; + assign source_id__h17844 = { addr_offset__h14599[4:0], 5'd21 } ; + assign source_id__h17917 = { addr_offset__h14599[4:0], 5'd20 } ; + assign source_id__h17990 = { addr_offset__h14599[4:0], 5'd19 } ; + assign source_id__h18063 = { addr_offset__h14599[4:0], 5'd18 } ; + assign source_id__h18136 = { addr_offset__h14599[4:0], 5'd17 } ; + assign source_id__h18209 = { addr_offset__h14599[4:0], 5'd16 } ; + assign source_id__h18282 = { addr_offset__h14599[4:0], 5'd15 } ; + assign source_id__h18355 = { addr_offset__h14599[4:0], 5'd14 } ; + assign source_id__h18428 = { addr_offset__h14599[4:0], 5'd13 } ; + assign source_id__h18501 = { addr_offset__h14599[4:0], 5'd12 } ; + assign source_id__h18574 = { addr_offset__h14599[4:0], 5'd11 } ; + assign source_id__h18647 = { addr_offset__h14599[4:0], 5'd10 } ; + assign source_id__h18720 = { addr_offset__h14599[4:0], 5'd9 } ; + assign source_id__h18793 = { addr_offset__h14599[4:0], 5'd8 } ; + assign source_id__h18866 = { addr_offset__h14599[4:0], 5'd7 } ; + assign source_id__h18939 = { addr_offset__h14599[4:0], 5'd6 } ; + assign source_id__h19012 = { addr_offset__h14599[4:0], 5'd5 } ; + assign source_id__h19085 = { addr_offset__h14599[4:0], 5'd4 } ; + assign source_id__h19158 = { addr_offset__h14599[4:0], 5'd3 } ; + assign source_id__h19231 = { addr_offset__h14599[4:0], 5'd2 } ; + assign source_id__h19304 = { addr_offset__h14599[4:0], 5'd1 } ; + assign source_id__h21553 = 10'd31 + source_id_base__h15044 ; + assign source_id__h21729 = 10'd30 + source_id_base__h15044 ; + assign source_id__h21837 = 10'd29 + source_id_base__h15044 ; + assign source_id__h21945 = 10'd28 + source_id_base__h15044 ; + assign source_id__h22053 = 10'd27 + source_id_base__h15044 ; + assign source_id__h22161 = 10'd26 + source_id_base__h15044 ; + assign source_id__h22269 = 10'd25 + source_id_base__h15044 ; + assign source_id__h22377 = 10'd24 + source_id_base__h15044 ; + assign source_id__h22485 = 10'd23 + source_id_base__h15044 ; + assign source_id__h22593 = 10'd22 + source_id_base__h15044 ; + assign source_id__h22701 = 10'd21 + source_id_base__h15044 ; + assign source_id__h22809 = 10'd20 + source_id_base__h15044 ; + assign source_id__h22917 = 10'd19 + source_id_base__h15044 ; + assign source_id__h23025 = 10'd18 + source_id_base__h15044 ; + assign source_id__h23133 = 10'd17 + source_id_base__h15044 ; + assign source_id__h23241 = 10'd16 + source_id_base__h15044 ; + assign source_id__h23349 = 10'd15 + source_id_base__h15044 ; + assign source_id__h23457 = 10'd14 + source_id_base__h15044 ; + assign source_id__h23565 = 10'd13 + source_id_base__h15044 ; + assign source_id__h23673 = 10'd12 + source_id_base__h15044 ; + assign source_id__h23781 = 10'd11 + source_id_base__h15044 ; + assign source_id__h23889 = 10'd10 + source_id_base__h15044 ; + assign source_id__h23997 = 10'd9 + source_id_base__h15044 ; + assign source_id__h24105 = 10'd8 + source_id_base__h15044 ; + assign source_id__h24213 = 10'd7 + source_id_base__h15044 ; + assign source_id__h24321 = 10'd6 + source_id_base__h15044 ; + assign source_id__h24429 = 10'd5 + source_id_base__h15044 ; + assign source_id__h24537 = 10'd4 + source_id_base__h15044 ; + assign source_id__h24645 = 10'd3 + source_id_base__h15044 ; + assign source_id__h24753 = 10'd2 + source_id_base__h15044 ; + assign source_id__h24861 = 10'd1 + source_id_base__h15044 ; + assign source_id__h31046 = { addr_offset__h28467[4:0], 5'd1 } ; + assign source_id__h32256 = { addr_offset__h28467[4:0], 5'd2 } ; + assign source_id__h33466 = { addr_offset__h28467[4:0], 5'd3 } ; + assign source_id__h34676 = { addr_offset__h28467[4:0], 5'd4 } ; + assign source_id__h35886 = { addr_offset__h28467[4:0], 5'd5 } ; + assign source_id__h37096 = { addr_offset__h28467[4:0], 5'd6 } ; + assign source_id__h38306 = { addr_offset__h28467[4:0], 5'd7 } ; + assign source_id__h39516 = { addr_offset__h28467[4:0], 5'd8 } ; + assign source_id__h40726 = { addr_offset__h28467[4:0], 5'd9 } ; + assign source_id__h41936 = { addr_offset__h28467[4:0], 5'd10 } ; + assign source_id__h43146 = { addr_offset__h28467[4:0], 5'd11 } ; + assign source_id__h44356 = { addr_offset__h28467[4:0], 5'd12 } ; + assign source_id__h45566 = { addr_offset__h28467[4:0], 5'd13 } ; + assign source_id__h46776 = { addr_offset__h28467[4:0], 5'd14 } ; + assign source_id__h47986 = { addr_offset__h28467[4:0], 5'd15 } ; + assign source_id__h49196 = { addr_offset__h28467[4:0], 5'd16 } ; + assign source_id__h50406 = { addr_offset__h28467[4:0], 5'd17 } ; + assign source_id__h51616 = { addr_offset__h28467[4:0], 5'd18 } ; + assign source_id__h52826 = { addr_offset__h28467[4:0], 5'd19 } ; + assign source_id__h54036 = { addr_offset__h28467[4:0], 5'd20 } ; + assign source_id__h55246 = { addr_offset__h28467[4:0], 5'd21 } ; + assign source_id__h56456 = { addr_offset__h28467[4:0], 5'd22 } ; + assign source_id__h57666 = { addr_offset__h28467[4:0], 5'd23 } ; + assign source_id__h58876 = { addr_offset__h28467[4:0], 5'd24 } ; + assign source_id__h60086 = { addr_offset__h28467[4:0], 5'd25 } ; + assign source_id__h61296 = { addr_offset__h28467[4:0], 5'd26 } ; + assign source_id__h62506 = { addr_offset__h28467[4:0], 5'd27 } ; + assign source_id__h63716 = { addr_offset__h28467[4:0], 5'd28 } ; + assign source_id__h64926 = { addr_offset__h28467[4:0], 5'd29 } ; + assign source_id__h66136 = { addr_offset__h28467[4:0], 5'd30 } ; + assign source_id__h67346 = { addr_offset__h28467[4:0], 5'd31 } ; + assign source_id__h69011 = { 5'd0, x__h69063 } ; + assign source_id_base__h15044 = { addr_offset__h14599[4:0], 5'h0 } ; + assign source_id_base__h29718 = { addr_offset__h28467[4:0], 5'h0 } ; + assign v__h14836 = { 61'd0, x__h14907 } ; + assign v__h15086 = { 32'd0, v_ip__h15089 } ; + assign v__h19560 = { 32'd0, v_ie__h19563 } ; + assign v__h25178 = { 61'd0, x__h25249 } ; + assign v__h26875 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 ? - v__h26835 : + v__h26894 : 64'd0 ; - assign v__h26835 = { 59'd0, max_id__h25318 } ; - assign v_ie__h19504 = - { source_id__h21494 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h21670 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h21778 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h21886 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h21994 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h22102 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h22210 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h22318 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h22426 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h22534 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h22642 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h22750 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h22858 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h22966 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h23074 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h23182 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h23290 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h23398 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h23506 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h23614 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h23722 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h23830 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h23938 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h24046 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h24154 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h24262 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h24370 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h24478 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h24586 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h24694 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h24802 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + assign v__h26894 = { 59'd0, max_id__h25377 } ; + assign v_ie__h19563 = + { source_id__h21553 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, + source_id__h21729 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + source_id__h21837 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + source_id__h21945 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + source_id__h22053 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + source_id__h22161 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + source_id__h22269 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + source_id__h22377 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + source_id__h22485 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + source_id__h22593 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + source_id__h22701 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + source_id__h22809 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + source_id__h22917 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + source_id__h23025 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + source_id__h23133 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + source_id__h23241 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + source_id__h23349 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + source_id__h23457 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + source_id__h23565 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + source_id__h23673 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + source_id__h23781 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + source_id__h23889 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + source_id__h23997 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + source_id__h24105 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + source_id__h24213 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + source_id__h24321 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + source_id__h24429 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + source_id__h24537 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + source_id__h24645 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + source_id__h24753 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + source_id__h24861 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h15030 = - { source_id__h17021 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; + assign v_ip__h15089 = + { source_id__h17080 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164, - source_id__h17128 <= 10'd16 && + source_id__h17187 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168, - source_id__h17201 <= 10'd16 && + source_id__h17260 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d173, - source_id__h17274 <= 10'd16 && + source_id__h17333 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d177, - source_id__h17347 <= 10'd16 && + source_id__h17406 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d182, - source_id__h17420 <= 10'd16 && + source_id__h17479 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d186, - source_id__h17493 <= 10'd16 && + source_id__h17552 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d191, - source_id__h17566 <= 10'd16 && + source_id__h17625 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d195, - source_id__h17639 <= 10'd16 && + source_id__h17698 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d200, - source_id__h17712 <= 10'd16 && + source_id__h17771 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d204, - source_id__h17785 <= 10'd16 && + source_id__h17844 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d209, - source_id__h17858 <= 10'd16 && + source_id__h17917 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d213, - source_id__h17931 <= 10'd16 && + source_id__h17990 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d218, - source_id__h18004 <= 10'd16 && + source_id__h18063 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d222, - source_id__h18077 <= 10'd16 && + source_id__h18136 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d227, - source_id__h18150 <= 10'd16 && + source_id__h18209 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d231, - source_id__h18223 <= 10'd16 && + source_id__h18282 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d236, - source_id__h18296 <= 10'd16 && + source_id__h18355 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d240, - source_id__h18369 <= 10'd16 && + source_id__h18428 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d245, - source_id__h18442 <= 10'd16 && + source_id__h18501 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d249, - source_id__h18515 <= 10'd16 && + source_id__h18574 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d254, - source_id__h18588 <= 10'd16 && + source_id__h18647 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d258, - source_id__h18661 <= 10'd16 && + source_id__h18720 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d263, - source_id__h18734 <= 10'd16 && + source_id__h18793 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d267, - source_id__h18807 <= 10'd16 && + source_id__h18866 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d272, - source_id__h18880 <= 10'd16 && + source_id__h18939 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d276, - source_id__h18953 <= 10'd16 && + source_id__h19012 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d281, - source_id__h19026 <= 10'd16 && + source_id__h19085 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d285, - source_id__h19099 <= 10'd16 && + source_id__h19158 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d290, - source_id__h19172 <= 10'd16 && + source_id__h19231 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d294, - source_id__h19245 <= 10'd16 && + source_id__h19304 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d299, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d301 } ; - assign wdata32__h28409 = - (addr_offset__h28408[2:0] == 3'd4) ? + assign wdata32__h28468 = + (addr_offset__h28467[2:0] == 3'd4) ? m_slave_xactor_shim_wff$D_OUT[72:41] : m_slave_xactor_shim_wff$D_OUT[40:9] ; - assign x__h25030 = - { addr_offset__h14540[31:16], 4'd0, addr_offset__h14540[11:0] } ; - assign x__h27766 = - (addr_offset__h14540[2:0] == 3'd4) ? - rdata___1__h27806 : - rdata__h27563 ; - assign x__h68623 = - { addr_offset__h28408[31:16], 4'd0, addr_offset__h28408[11:0] } ; - assign y_avValue_fst__h27455 = (x__h25371 == 5'd0) ? v__h26816 : 64'd0 ; - assign y_avValue_fst__h27476 = + assign x__h25089 = + { addr_offset__h14599[31:16], 4'd0, addr_offset__h14599[11:0] } ; + assign x__h27825 = + (addr_offset__h14599[2:0] == 3'd4) ? + rdata___1__h27865 : + rdata__h27622 ; + assign x__h68682 = + { addr_offset__h28467[31:16], 4'd0, addr_offset__h28467[11:0] } ; + assign y_avValue_fst__h27514 = (x__h25430 == 5'd0) ? v__h26875 : 64'd0 ; + assign y_avValue_fst__h27535 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - y_avValue_fst__h27455 : + y_avValue_fst__h27514 : 64'd0 ; - assign y_avValue_fst__h27488 = + assign y_avValue_fst__h27547 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - v__h25119 : + v__h25178 : 64'd0 ; - assign y_avValue_fst__h27504 = + assign y_avValue_fst__h27563 = (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308) ? - v__h19501 : + v__h19560 : 64'd0 ; - assign y_avValue_fst__h27520 = + assign y_avValue_fst__h27579 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 ? - v__h15027 : + v__h15086 : 64'd0 ; - assign y_avValue_fst__h27525 = + assign y_avValue_fst__h27584 = (!m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306) ? - y_avValue_fst__h27504 : - y_avValue_fst__h27509 ; - assign y_avValue_fst__h27536 = - (addr_offset__h14540[11:2] != 10'd0 && + y_avValue_fst__h27563 : + y_avValue_fst__h27568 ; + assign y_avValue_fst__h27595 = + (addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106) ? - v__h14777 : + v__h14836 : 64'd0 ; - assign y_avValue_fst__h27541 = + assign y_avValue_fst__h27600 = (!m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134) ? - y_avValue_fst__h27520 : - y_avValue_fst__h27525 ; - assign y_avValue_fst__h27555 = + y_avValue_fst__h27579 : + y_avValue_fst__h27584 ; + assign y_avValue_fst__h27614 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - y_avValue_fst__h27536 : - y_avValue_fst__h27541 ; - always@(addr_offset__h14540 or + y_avValue_fst__h27595 : + y_avValue_fst__h27600 ; + always@(addr_offset__h14599 or m_vrg_source_prio_0 or m_vrg_source_prio_1 or m_vrg_source_prio_2 or @@ -16968,55 +16973,55 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_prio_14 or m_vrg_source_prio_15 or m_vrg_source_prio_16) begin - case (addr_offset__h14540[11:2]) - 10'd0: x__h14848 = m_vrg_source_prio_0; - 10'd1: x__h14848 = m_vrg_source_prio_1; - 10'd2: x__h14848 = m_vrg_source_prio_2; - 10'd3: x__h14848 = m_vrg_source_prio_3; - 10'd4: x__h14848 = m_vrg_source_prio_4; - 10'd5: x__h14848 = m_vrg_source_prio_5; - 10'd6: x__h14848 = m_vrg_source_prio_6; - 10'd7: x__h14848 = m_vrg_source_prio_7; - 10'd8: x__h14848 = m_vrg_source_prio_8; - 10'd9: x__h14848 = m_vrg_source_prio_9; - 10'd10: x__h14848 = m_vrg_source_prio_10; - 10'd11: x__h14848 = m_vrg_source_prio_11; - 10'd12: x__h14848 = m_vrg_source_prio_12; - 10'd13: x__h14848 = m_vrg_source_prio_13; - 10'd14: x__h14848 = m_vrg_source_prio_14; - 10'd15: x__h14848 = m_vrg_source_prio_15; - 10'd16: x__h14848 = m_vrg_source_prio_16; - default: x__h14848 = 3'b010 /* unspecified value */ ; + case (addr_offset__h14599[11:2]) + 10'd0: x__h14907 = m_vrg_source_prio_0; + 10'd1: x__h14907 = m_vrg_source_prio_1; + 10'd2: x__h14907 = m_vrg_source_prio_2; + 10'd3: x__h14907 = m_vrg_source_prio_3; + 10'd4: x__h14907 = m_vrg_source_prio_4; + 10'd5: x__h14907 = m_vrg_source_prio_5; + 10'd6: x__h14907 = m_vrg_source_prio_6; + 10'd7: x__h14907 = m_vrg_source_prio_7; + 10'd8: x__h14907 = m_vrg_source_prio_8; + 10'd9: x__h14907 = m_vrg_source_prio_9; + 10'd10: x__h14907 = m_vrg_source_prio_10; + 10'd11: x__h14907 = m_vrg_source_prio_11; + 10'd12: x__h14907 = m_vrg_source_prio_12; + 10'd13: x__h14907 = m_vrg_source_prio_13; + 10'd14: x__h14907 = m_vrg_source_prio_14; + 10'd15: x__h14907 = m_vrg_source_prio_15; + 10'd16: x__h14907 = m_vrg_source_prio_16; + default: x__h14907 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or m_vrg_target_threshold_0 or m_vrg_target_threshold_1) begin - case (addr_offset__h14540[16:12]) - 5'd0: x__h25190 = m_vrg_target_threshold_0; - 5'd1: x__h25190 = m_vrg_target_threshold_1; - default: x__h25190 = 3'b010 /* unspecified value */ ; + case (addr_offset__h14599[16:12]) + 5'd0: x__h25249 = m_vrg_target_threshold_0; + 5'd1: x__h25249 = m_vrg_target_threshold_1; + default: x__h25249 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h14540[16:12]) - 5'd0: x__h25371 = m_vrg_servicing_source_0; - 5'd1: x__h25371 = m_vrg_servicing_source_1; - default: x__h25371 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h14599[16:12]) + 5'd0: x__h25430 = m_vrg_servicing_source_0; + 5'd1: x__h25430 = m_vrg_servicing_source_1; + default: x__h25430 = 5'b01010 /* unspecified value */ ; endcase end - always@(addr_offset__h28408 or + always@(addr_offset__h28467 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h28408[16:12]) - 5'd0: x__h69004 = m_vrg_servicing_source_0; - 5'd1: x__h69004 = m_vrg_servicing_source_1; - default: x__h69004 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h28467[16:12]) + 5'd0: x__h69063 = m_vrg_servicing_source_0; + 5'd1: x__h69063 = m_vrg_servicing_source_1; + default: x__h69063 = 5'b01010 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17033,7 +17038,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d301 = m_vrg_source_ip_0; @@ -17089,7 +17094,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21670 or + always@(source_id__h21729 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17106,7 +17111,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21670) + case (source_id__h21729) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362 = m_vvrg_ie_0_0; @@ -17162,7 +17167,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21670 or + always@(source_id__h21729 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17179,7 +17184,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21670) + case (source_id__h21729) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363 = m_vvrg_ie_1_0; @@ -17235,7 +17240,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21494 or + always@(source_id__h21553 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17252,7 +17257,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21494) + case (source_id__h21553) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337 = m_vvrg_ie_0_0; @@ -17308,7 +17313,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21494 or + always@(source_id__h21553 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17325,7 +17330,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21494) + case (source_id__h21553) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356 = m_vvrg_ie_1_0; @@ -17381,7 +17386,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21778 or + always@(source_id__h21837 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17398,7 +17403,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21778) + case (source_id__h21837) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370 = m_vvrg_ie_0_0; @@ -17454,7 +17459,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17021 or + always@(source_id__h17080 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17471,7 +17476,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17021) + case (source_id__h17080) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164 = m_vrg_source_ip_0; @@ -17527,7 +17532,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21778 or + always@(source_id__h21837 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17544,7 +17549,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21778) + case (source_id__h21837) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371 = m_vvrg_ie_1_0; @@ -17600,7 +17605,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21886 or + always@(source_id__h21945 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17617,7 +17622,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21886) + case (source_id__h21945) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378 = m_vvrg_ie_1_0; @@ -17673,7 +17678,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21886 or + always@(source_id__h21945 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17690,7 +17695,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21886) + case (source_id__h21945) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377 = m_vvrg_ie_0_0; @@ -17746,7 +17751,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17128 or + always@(source_id__h17187 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17763,7 +17768,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17128) + case (source_id__h17187) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168 = m_vrg_source_ip_0; @@ -17819,7 +17824,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21994 or + always@(source_id__h22053 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17836,7 +17841,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21994) + case (source_id__h22053) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385 = m_vvrg_ie_0_0; @@ -17892,7 +17897,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21994 or + always@(source_id__h22053 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17909,7 +17914,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21994) + case (source_id__h22053) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386 = m_vvrg_ie_1_0; @@ -17965,7 +17970,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17201 or + always@(source_id__h17260 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17982,7 +17987,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17201) + case (source_id__h17260) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d173 = m_vrg_source_ip_0; @@ -18038,7 +18043,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22102 or + always@(source_id__h22161 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18055,7 +18060,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22102) + case (source_id__h22161) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392 = m_vvrg_ie_0_0; @@ -18111,7 +18116,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22102 or + always@(source_id__h22161 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18128,7 +18133,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22102) + case (source_id__h22161) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393 = m_vvrg_ie_1_0; @@ -18184,7 +18189,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17274 or + always@(source_id__h17333 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18201,7 +18206,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17274) + case (source_id__h17333) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d177 = m_vrg_source_ip_0; @@ -18257,7 +18262,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22210 or + always@(source_id__h22269 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18274,7 +18279,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22210) + case (source_id__h22269) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400 = m_vvrg_ie_0_0; @@ -18330,7 +18335,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22210 or + always@(source_id__h22269 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18347,7 +18352,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22210) + case (source_id__h22269) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401 = m_vvrg_ie_1_0; @@ -18403,7 +18408,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22318 or + always@(source_id__h22377 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18420,7 +18425,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22318) + case (source_id__h22377) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407 = m_vvrg_ie_0_0; @@ -18476,7 +18481,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17347 or + always@(source_id__h17406 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18493,7 +18498,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17347) + case (source_id__h17406) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d182 = m_vrg_source_ip_0; @@ -18549,7 +18554,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22318 or + always@(source_id__h22377 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18566,7 +18571,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22318) + case (source_id__h22377) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408 = m_vvrg_ie_1_0; @@ -18622,7 +18627,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17420 or + always@(source_id__h17479 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18639,7 +18644,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17420) + case (source_id__h17479) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d186 = m_vrg_source_ip_0; @@ -18695,7 +18700,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22426 or + always@(source_id__h22485 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18712,7 +18717,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22426) + case (source_id__h22485) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415 = m_vvrg_ie_0_0; @@ -18768,7 +18773,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22426 or + always@(source_id__h22485 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18785,7 +18790,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22426) + case (source_id__h22485) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416 = m_vvrg_ie_1_0; @@ -18841,7 +18846,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22534 or + always@(source_id__h22593 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18858,7 +18863,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22534) + case (source_id__h22593) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422 = m_vvrg_ie_0_0; @@ -18914,7 +18919,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17493 or + always@(source_id__h17552 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18931,7 +18936,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17493) + case (source_id__h17552) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d191 = m_vrg_source_ip_0; @@ -18987,7 +18992,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22534 or + always@(source_id__h22593 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19004,7 +19009,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22534) + case (source_id__h22593) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423 = m_vvrg_ie_1_0; @@ -19060,7 +19065,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17566 or + always@(source_id__h17625 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19077,7 +19082,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17566) + case (source_id__h17625) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d195 = m_vrg_source_ip_0; @@ -19133,7 +19138,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22642 or + always@(source_id__h22701 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19150,7 +19155,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22642) + case (source_id__h22701) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431 = m_vvrg_ie_1_0; @@ -19206,7 +19211,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22642 or + always@(source_id__h22701 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19223,7 +19228,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22642) + case (source_id__h22701) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430 = m_vvrg_ie_0_0; @@ -19279,7 +19284,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22750 or + always@(source_id__h22809 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19296,7 +19301,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22750) + case (source_id__h22809) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437 = m_vvrg_ie_0_0; @@ -19352,7 +19357,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17639 or + always@(source_id__h17698 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19369,7 +19374,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17639) + case (source_id__h17698) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d200 = m_vrg_source_ip_0; @@ -19425,7 +19430,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22750 or + always@(source_id__h22809 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19442,7 +19447,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22750) + case (source_id__h22809) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438 = m_vvrg_ie_1_0; @@ -19498,7 +19503,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17712 or + always@(source_id__h17771 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19515,7 +19520,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17712) + case (source_id__h17771) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d204 = m_vrg_source_ip_0; @@ -19571,7 +19576,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22858 or + always@(source_id__h22917 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19588,7 +19593,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22858) + case (source_id__h22917) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445 = m_vvrg_ie_0_0; @@ -19644,7 +19649,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22858 or + always@(source_id__h22917 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19661,7 +19666,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22858) + case (source_id__h22917) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446 = m_vvrg_ie_1_0; @@ -19717,7 +19722,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17785 or + always@(source_id__h17844 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19734,7 +19739,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17785) + case (source_id__h17844) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d209 = m_vrg_source_ip_0; @@ -19790,7 +19795,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22966 or + always@(source_id__h23025 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19807,7 +19812,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22966) + case (source_id__h23025) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452 = m_vvrg_ie_0_0; @@ -19863,7 +19868,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22966 or + always@(source_id__h23025 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19880,7 +19885,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22966) + case (source_id__h23025) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453 = m_vvrg_ie_1_0; @@ -19936,7 +19941,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18442 or + always@(source_id__h18501 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19953,7 +19958,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18442) + case (source_id__h18501) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d249 = m_vrg_source_ip_0; @@ -20009,7 +20014,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17858 or + always@(source_id__h17917 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20026,7 +20031,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17858) + case (source_id__h17917) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d213 = m_vrg_source_ip_0; @@ -20082,7 +20087,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23074 or + always@(source_id__h23133 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20099,7 +20104,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23074) + case (source_id__h23133) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460 = m_vvrg_ie_0_0; @@ -20155,7 +20160,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23074 or + always@(source_id__h23133 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20172,7 +20177,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23074) + case (source_id__h23133) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461 = m_vvrg_ie_1_0; @@ -20228,7 +20233,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23182 or + always@(source_id__h23241 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20245,7 +20250,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23182) + case (source_id__h23241) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467 = m_vvrg_ie_0_0; @@ -20301,7 +20306,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17931 or + always@(source_id__h17990 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20318,7 +20323,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17931) + case (source_id__h17990) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d218 = m_vrg_source_ip_0; @@ -20374,7 +20379,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23182 or + always@(source_id__h23241 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20391,7 +20396,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23182) + case (source_id__h23241) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468 = m_vvrg_ie_1_0; @@ -20447,7 +20452,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18004 or + always@(source_id__h18063 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20464,7 +20469,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18004) + case (source_id__h18063) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d222 = m_vrg_source_ip_0; @@ -20520,7 +20525,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23290 or + always@(source_id__h23349 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20537,7 +20542,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23290) + case (source_id__h23349) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475 = m_vvrg_ie_0_0; @@ -20593,7 +20598,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23290 or + always@(source_id__h23349 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20610,7 +20615,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23290) + case (source_id__h23349) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476 = m_vvrg_ie_1_0; @@ -20666,7 +20671,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23398 or + always@(source_id__h23457 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20683,7 +20688,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23398) + case (source_id__h23457) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482 = m_vvrg_ie_0_0; @@ -20739,7 +20744,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18077 or + always@(source_id__h18136 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20756,7 +20761,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18077) + case (source_id__h18136) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d227 = m_vrg_source_ip_0; @@ -20812,7 +20817,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23398 or + always@(source_id__h23457 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20829,7 +20834,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23398) + case (source_id__h23457) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483 = m_vvrg_ie_1_0; @@ -20885,7 +20890,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18150 or + always@(source_id__h18209 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20902,7 +20907,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18150) + case (source_id__h18209) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d231 = m_vrg_source_ip_0; @@ -20958,7 +20963,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23506 or + always@(source_id__h23565 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20975,7 +20980,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23506) + case (source_id__h23565) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491 = m_vvrg_ie_1_0; @@ -21031,7 +21036,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23506 or + always@(source_id__h23565 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21048,7 +21053,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23506) + case (source_id__h23565) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490 = m_vvrg_ie_0_0; @@ -21104,7 +21109,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23614 or + always@(source_id__h23673 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21121,7 +21126,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23614) + case (source_id__h23673) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497 = m_vvrg_ie_0_0; @@ -21177,7 +21182,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18223 or + always@(source_id__h18282 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21194,7 +21199,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18223) + case (source_id__h18282) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d236 = m_vrg_source_ip_0; @@ -21250,7 +21255,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23614 or + always@(source_id__h23673 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21267,7 +21272,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23614) + case (source_id__h23673) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498 = m_vvrg_ie_1_0; @@ -21323,7 +21328,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18296 or + always@(source_id__h18355 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21340,7 +21345,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18296) + case (source_id__h18355) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d240 = m_vrg_source_ip_0; @@ -21396,7 +21401,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23722 or + always@(source_id__h23781 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21413,7 +21418,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23722) + case (source_id__h23781) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505 = m_vvrg_ie_0_0; @@ -21469,7 +21474,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23722 or + always@(source_id__h23781 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21486,7 +21491,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23722) + case (source_id__h23781) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506 = m_vvrg_ie_1_0; @@ -21542,7 +21547,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23830 or + always@(source_id__h23889 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21559,7 +21564,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23830) + case (source_id__h23889) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512 = m_vvrg_ie_0_0; @@ -21615,7 +21620,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18369 or + always@(source_id__h18428 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21632,7 +21637,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18369) + case (source_id__h18428) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d245 = m_vrg_source_ip_0; @@ -21688,7 +21693,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23830 or + always@(source_id__h23889 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21705,7 +21710,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23830) + case (source_id__h23889) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513 = m_vvrg_ie_1_0; @@ -21761,7 +21766,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23938 or + always@(source_id__h23997 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21778,7 +21783,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23938) + case (source_id__h23997) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520 = m_vvrg_ie_0_0; @@ -21834,7 +21839,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23938 or + always@(source_id__h23997 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21851,7 +21856,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23938) + case (source_id__h23997) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521 = m_vvrg_ie_1_0; @@ -21907,7 +21912,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24046 or + always@(source_id__h24105 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21924,7 +21929,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24046) + case (source_id__h24105) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527 = m_vvrg_ie_0_0; @@ -21980,7 +21985,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24046 or + always@(source_id__h24105 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21997,7 +22002,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24046) + case (source_id__h24105) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528 = m_vvrg_ie_1_0; @@ -22053,7 +22058,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18588 or + always@(source_id__h18647 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22070,7 +22075,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18588) + case (source_id__h18647) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d258 = m_vrg_source_ip_0; @@ -22126,7 +22131,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18515 or + always@(source_id__h18574 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22143,7 +22148,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18515) + case (source_id__h18574) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d254 = m_vrg_source_ip_0; @@ -22199,7 +22204,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24154 or + always@(source_id__h24213 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22216,7 +22221,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24154) + case (source_id__h24213) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535 = m_vvrg_ie_0_0; @@ -22272,7 +22277,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24154 or + always@(source_id__h24213 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22289,7 +22294,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24154) + case (source_id__h24213) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536 = m_vvrg_ie_1_0; @@ -22345,7 +22350,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24262 or + always@(source_id__h24321 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22362,7 +22367,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24262) + case (source_id__h24321) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542 = m_vvrg_ie_0_0; @@ -22418,7 +22423,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24262 or + always@(source_id__h24321 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22435,7 +22440,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24262) + case (source_id__h24321) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543 = m_vvrg_ie_1_0; @@ -22491,7 +22496,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18734 or + always@(source_id__h18793 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22508,7 +22513,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18734) + case (source_id__h18793) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d267 = m_vrg_source_ip_0; @@ -22564,7 +22569,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18661 or + always@(source_id__h18720 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22581,7 +22586,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18661) + case (source_id__h18720) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d263 = m_vrg_source_ip_0; @@ -22637,7 +22642,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24370 or + always@(source_id__h24429 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22654,7 +22659,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24370) + case (source_id__h24429) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550 = m_vvrg_ie_0_0; @@ -22710,7 +22715,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24478 or + always@(source_id__h24537 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22727,7 +22732,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24478) + case (source_id__h24537) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557 = m_vvrg_ie_0_0; @@ -22783,7 +22788,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24370 or + always@(source_id__h24429 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22800,7 +22805,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24370) + case (source_id__h24429) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551 = m_vvrg_ie_1_0; @@ -22856,7 +22861,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24478 or + always@(source_id__h24537 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22873,7 +22878,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24478) + case (source_id__h24537) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558 = m_vvrg_ie_1_0; @@ -22929,7 +22934,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18880 or + always@(source_id__h18939 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22946,7 +22951,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18880) + case (source_id__h18939) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d276 = m_vrg_source_ip_0; @@ -23002,7 +23007,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18807 or + always@(source_id__h18866 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23019,7 +23024,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18807) + case (source_id__h18866) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d272 = m_vrg_source_ip_0; @@ -23075,7 +23080,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24586 or + always@(source_id__h24645 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23092,7 +23097,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24586) + case (source_id__h24645) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565 = m_vvrg_ie_0_0; @@ -23148,7 +23153,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24586 or + always@(source_id__h24645 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23165,7 +23170,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24586) + case (source_id__h24645) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566 = m_vvrg_ie_1_0; @@ -23221,7 +23226,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24694 or + always@(source_id__h24753 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23238,7 +23243,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24694) + case (source_id__h24753) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572 = m_vvrg_ie_0_0; @@ -23294,7 +23299,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24694 or + always@(source_id__h24753 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23311,7 +23316,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24694) + case (source_id__h24753) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573 = m_vvrg_ie_1_0; @@ -23367,7 +23372,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18953 or + always@(source_id__h19012 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23384,7 +23389,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18953) + case (source_id__h19012) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d281 = m_vrg_source_ip_0; @@ -23440,7 +23445,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19026 or + always@(source_id__h19085 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23457,7 +23462,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19026) + case (source_id__h19085) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d285 = m_vrg_source_ip_0; @@ -23513,7 +23518,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24802 or + always@(source_id__h24861 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23530,7 +23535,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24802) + case (source_id__h24861) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580 = m_vvrg_ie_0_0; @@ -23586,7 +23591,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24802 or + always@(source_id__h24861 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23603,7 +23608,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24802) + case (source_id__h24861) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581 = m_vvrg_ie_1_0; @@ -23659,7 +23664,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23676,7 +23681,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585 = m_vvrg_ie_0_0; @@ -23732,7 +23737,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23749,7 +23754,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586 = m_vvrg_ie_1_0; @@ -23805,487 +23810,487 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19172 or + always@(source_id__h19231 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24302,7 +24307,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19172) + case (source_id__h19231) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d294 = m_vrg_source_ip_0; @@ -24358,7 +24363,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19099 or + always@(source_id__h19158 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24375,7 +24380,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19099) + case (source_id__h19158) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d290 = m_vrg_source_ip_0; @@ -24431,7 +24436,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19245 or + always@(source_id__h19304 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24448,7 +24453,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19245) + case (source_id__h19304) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d299 = m_vrg_source_ip_0; @@ -24504,223 +24509,223 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) + always@(addr_offset__h14599 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = m_vvrg_ie_0_1; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = m_vvrg_ie_1_1; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) + always@(addr_offset__h14599 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_0_2; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_1_2; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) + always@(addr_offset__h14599 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_0_3; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_1_3; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) + always@(addr_offset__h14599 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_0_4; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_1_4; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) + always@(addr_offset__h14599 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_0_5; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_1_5; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) + always@(addr_offset__h14599 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_0_6; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_1_6; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) + always@(addr_offset__h14599 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_0_7; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_1_7; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) + always@(addr_offset__h14599 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_0_8; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_1_8; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) + always@(addr_offset__h14599 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_0_9; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_1_9; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) + always@(addr_offset__h14599 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_0_10; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_1_10; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) + always@(addr_offset__h14599 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_0_11; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_1_11; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) + always@(addr_offset__h14599 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_0_12; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_1_12; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) + always@(addr_offset__h14599 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_0_13; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_1_13; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) + always@(addr_offset__h14599 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_0_14; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_1_14; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) + always@(addr_offset__h14599 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_0_15; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_1_15; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) + always@(addr_offset__h14599 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_0_16; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_1_16; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h25030 or y_avValue_fst__h27488 or y_avValue_fst__h27476) + always@(x__h25089 or y_avValue_fst__h27547 or y_avValue_fst__h27535) begin - case (x__h25030) - 32'h00200000: y_avValue_fst__h27509 = y_avValue_fst__h27488; - 32'h00200004: y_avValue_fst__h27509 = y_avValue_fst__h27476; - default: y_avValue_fst__h27509 = 64'd0; + case (x__h25089) + 32'h00200000: y_avValue_fst__h27568 = y_avValue_fst__h27547; + 32'h00200004: y_avValue_fst__h27568 = y_avValue_fst__h27535; + default: y_avValue_fst__h27568 = 64'd0; endcase end - always@(source_id__h68952 or + always@(source_id__h69011 or m_vrg_source_busy_0 or m_vrg_source_busy_1 or m_vrg_source_busy_2 or @@ -24738,7 +24743,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_busy_14 or m_vrg_source_busy_15 or m_vrg_source_busy_16) begin - case (source_id__h68952) + case (source_id__h69011) 10'd0: SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 = m_vrg_source_busy_0; @@ -24794,42 +24799,42 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h25030 or + always@(x__h25089 or m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 or - x__h25371) + x__h25430) begin - case (x__h25030) + case (x__h25089) 32'h00200000: - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? 2'd0 : 2'd2; 32'h00200004: - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - ((x__h25371 == 5'd0) ? 2'd0 : 2'd2) : + ((x__h25430 == 5'd0) ? 2'd0 : 2'd2) : 2'd2; - default: CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = 2'd2; + default: CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = 2'd2; endcase end - always@(x__h68623 or + always@(x__h68682 or m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 or SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) begin - case (x__h68623) + case (x__h68682) 32'h00200000: - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ? 2'd0 : 2'd2; 32'h00200004: - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ? (SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ? 2'd0 : 2'd2) : 2'd2; - default: CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = 2'd2; + default: CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = 2'd2; endcase end @@ -25421,9 +25426,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h72910, + a__h72969, m_vrg_target_threshold_0, - b__h72911, + b__h72970, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25464,249 +25469,249 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h74915, + a__h74974, m_vrg_target_threshold_1, - b__h74916, + b__h74975, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368) + if (NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371) begin - v__h77333 = $stime; + v__h77354 = $stime; #0; end - v__h77327 = v__h77333 / 32'd10; + v__h77348 = v__h77354 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368) + if (NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77327, + v__h77348, $signed(32'd1), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375) + if (NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378) begin - v__h77531 = $stime; + v__h77552 = $stime; #0; end - v__h77525 = v__h77531 / 32'd10; + v__h77546 = v__h77552 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375) + if (NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77525, + v__h77546, $signed(32'd2), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383) + if (NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386) begin - v__h77729 = $stime; + v__h77750 = $stime; #0; end - v__h77723 = v__h77729 / 32'd10; + v__h77744 = v__h77750 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383) + if (NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77723, + v__h77744, $signed(32'd3), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391) + if (NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394) begin - v__h77927 = $stime; + v__h77948 = $stime; #0; end - v__h77921 = v__h77927 / 32'd10; + v__h77942 = v__h77948 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391) + if (NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77921, + v__h77942, $signed(32'd4), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399) + if (NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402) begin - v__h78125 = $stime; + v__h78146 = $stime; #0; end - v__h78119 = v__h78125 / 32'd10; + v__h78140 = v__h78146 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399) + if (NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78119, + v__h78140, $signed(32'd5), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407) + if (NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410) begin - v__h78323 = $stime; + v__h78344 = $stime; #0; end - v__h78317 = v__h78323 / 32'd10; + v__h78338 = v__h78344 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407) + if (NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78317, + v__h78338, $signed(32'd6), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415) + if (NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418) begin - v__h78521 = $stime; + v__h78542 = $stime; #0; end - v__h78515 = v__h78521 / 32'd10; + v__h78536 = v__h78542 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415) + if (NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78515, + v__h78536, $signed(32'd7), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423) + if (NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426) begin - v__h78719 = $stime; + v__h78740 = $stime; #0; end - v__h78713 = v__h78719 / 32'd10; + v__h78734 = v__h78740 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423) + if (NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78713, + v__h78734, $signed(32'd8), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431) + if (NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434) begin - v__h78917 = $stime; + v__h78938 = $stime; #0; end - v__h78911 = v__h78917 / 32'd10; + v__h78932 = v__h78938 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431) + if (NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78911, + v__h78932, $signed(32'd9), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439) + if (NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442) begin - v__h79115 = $stime; + v__h79136 = $stime; #0; end - v__h79109 = v__h79115 / 32'd10; + v__h79130 = v__h79136 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439) + if (NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79109, + v__h79130, $signed(32'd10), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447) + if (NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450) begin - v__h79313 = $stime; + v__h79334 = $stime; #0; end - v__h79307 = v__h79313 / 32'd10; + v__h79328 = v__h79334 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447) + if (NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79307, + v__h79328, $signed(32'd11), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455) + if (NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458) begin - v__h79511 = $stime; + v__h79532 = $stime; #0; end - v__h79505 = v__h79511 / 32'd10; + v__h79526 = v__h79532 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455) + if (NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79505, + v__h79526, $signed(32'd12), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463) + if (NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466) begin - v__h79709 = $stime; + v__h79730 = $stime; #0; end - v__h79703 = v__h79709 / 32'd10; + v__h79724 = v__h79730 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463) + if (NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79703, + v__h79724, $signed(32'd13), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471) + if (NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474) begin - v__h79907 = $stime; + v__h79928 = $stime; #0; end - v__h79901 = v__h79907 / 32'd10; + v__h79922 = v__h79928 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471) + if (NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79901, + v__h79922, $signed(32'd14), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479) + if (NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482) begin - v__h80105 = $stime; + v__h80126 = $stime; #0; end - v__h80099 = v__h80105 / 32'd10; + v__h80120 = v__h80126 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479) + if (NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h80099, + v__h80120, $signed(32'd15), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487) + if (NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490) begin - v__h80303 = $stime; + v__h80324 = $stime; #0; end - v__h80297 = v__h80303 / 32'd10; + v__h80318 = v__h80324 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487) + if (NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h80297, + v__h80318, $signed(32'd16), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) begin - v__h7530 = $stime; + v__h7589 = $stime; #0; end - v__h7524 = v__h7530 / 32'd10; + v__h7583 = v__h7589 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h7524); + $display("%0d: PLIC.rl_reset", v__h7583); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h28194 = $stime; + v__h28253 = $stime; #0; end - v__h28188 = v__h28194 / 32'd10; + v__h28247 = v__h28253 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_wr_req", v__h28188); + $display("%0d: PLIC.rl_process_wr_req", v__h28247); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -25881,15 +25886,15 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) begin - v__h28448 = $stime; + v__h28507 = $stime; #0; end - v__h28442 = v__h28448 / 32'd10; + v__h28501 = v__h28507 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h28442); + v__h28501); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) @@ -26065,101 +26070,101 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005) begin - v__h29372 = $stime; + v__h29431 = $stime; #0; end - v__h29366 = v__h29372 / 32'd10; + v__h29425 = v__h29431 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h29366, - addr_offset__h28408[11:2], - wdata32__h28409); + v__h29425, + addr_offset__h28467[11:2], + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016) begin - v__h29558 = $stime; + v__h29617 = $stime; #0; end - v__h29552 = v__h29558 / 32'd10; + v__h29611 = v__h29617 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h29552, - source_id_base__h29659); + v__h29611, + source_id_base__h29718); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980) begin - v__h68542 = $stime; + v__h68601 = $stime; #0; end - v__h68536 = v__h68542 / 32'd10; + v__h68595 = v__h68601 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h68536, - addr_offset__h28408[11:7], - source_id_base__h29659, - wdata32__h28409); + v__h68595, + addr_offset__h28467[11:7], + source_id_base__h29718, + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004) begin - v__h68832 = $stime; + v__h68891 = $stime; #0; end - v__h68826 = v__h68832 / 32'd10; + v__h68885 = v__h68891 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h68826, - addr_offset__h28408[16:12], - wdata32__h28409); + v__h68885, + addr_offset__h28467[16:12], + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076) begin - v__h69364 = $stime; + v__h69423 = $stime; #0; end - v__h69358 = v__h69364 / 32'd10; + v__h69417 = v__h69423 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h69358, - addr_offset__h28408[16:12], - source_id__h68952); + v__h69417, + addr_offset__h28467[16:12], + source_id__h69011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) begin - v__h69450 = $stime; + v__h69509 = $stime; #0; end - v__h69444 = v__h69450 / 32'd10; + v__h69503 = v__h69509 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h69444); + v__h69503); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) $display(" Completion message from target %0d to source %0d", - addr_offset__h28408[16:12], - source_id__h68952); + addr_offset__h28467[16:12], + source_id__h69011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) @@ -26169,16 +26174,16 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101)) begin - v__h69661 = $stime; + v__h69720 = $stime; #0; end - v__h69655 = v__h69661 / 32'd10; + v__h69714 = v__h69720 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h69655); + v__h69714); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || @@ -26393,14 +26398,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h69907 = $stime; + v__h69966 = $stime; #0; end - v__h69901 = v__h69907 / 32'd10; + v__h69960 = v__h69966 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h69901); + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h69960); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -26620,23 +26625,23 @@ module mkPLIC_16_2_7(CLK, NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h14375 = $stime; + v__h14434 = $stime; #0; end - v__h14369 = v__h14375 / 32'd10; + v__h14428 = v__h14434 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_rd_req:", v__h14369); + $display("%0d: PLIC.rl_process_rd_req:", v__h14428); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -26765,15 +26770,15 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) begin - v__h14590 = $stime; + v__h14649 = $stime; #0; end - v__h14584 = v__h14590 / 32'd10; + v__h14643 = v__h14649 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h14584); + v__h14643); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) @@ -26903,107 +26908,107 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109) begin - v__h14818 = $stime; + v__h14877 = $stime; #0; end - v__h14812 = v__h14818 / 32'd10; + v__h14871 = v__h14877 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109) $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h14812, - addr_offset__h14540[11:2], - v__h14777); + v__h14871, + addr_offset__h14599[11:2], + v__h14836); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d140) begin - v__h15069 = $stime; + v__h15128 = $stime; #0; end - v__h15063 = v__h15069 / 32'd10; + v__h15122 = v__h15128 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d140) $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h15063, - source_id_base__h14985, - v__h15027); + v__h15122, + source_id_base__h15044, + v__h15086); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d314) begin - v__h19543 = $stime; + v__h19602 = $stime; #0; end - v__h19537 = v__h19543 / 32'd10; + v__h19596 = v__h19602 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d314) $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h19537, - source_id_base__h14985, - v__h19501); + v__h19596, + source_id_base__h15044, + v__h19560); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d604) begin - v__h25160 = $stime; + v__h25219 = $stime; #0; end - v__h25154 = v__h25160 / 32'd10; + v__h25213 = v__h25219 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d604) $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h25154, - addr_offset__h14540[16:12], - v__h25119); + v__h25213, + addr_offset__h14599[16:12], + v__h25178); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810) begin - v__h27336 = $stime; + v__h27395 = $stime; #0; end - v__h27330 = v__h27336 / 32'd10; + v__h27389 = v__h27395 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810) $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h27330, - addr_offset__h14540[16:12], - v__h26835); + v__h27389, + addr_offset__h14599[16:12], + v__h26894); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) begin - v__h25416 = $stime; + v__h25475 = $stime; #0; end - v__h25410 = v__h25416 / 32'd10; + v__h25469 = v__h25475 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h25410, - addr_offset__h14540[16:12]); + v__h25469, + addr_offset__h14599[16:12]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) - $display(" Still servicing interrupt from source %0d", x__h25371); + $display(" Still servicing interrupt from source %0d", x__h25430); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) $display(" Trying to claim service for source %0d", - max_id__h25318); + max_id__h25377); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) @@ -27013,16 +27018,16 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837)) begin - v__h27627 = $stime; + v__h27686 = $stime; #0; end - v__h27621 = v__h27627 / 32'd10; + v__h27680 = v__h27686 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837)) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h27621); + v__h27680); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || @@ -27180,14 +27185,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h27865 = $stime; + v__h27924 = $stime; #0; end - v__h27859 = v__h27865 / 32'd10; + v__h27918 = v__h27924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_rd_req", v__h27859); + $display("%0d: PLIC.rl_process_rd_req", v__h27918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -27331,7 +27336,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $write("'h%h", x__h27766); + $write("'h%h", x__h27825); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -27379,38 +27384,38 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h76288 = $stime; + v__h76347 = $stime; #0; end - v__h76282 = v__h76288 / 32'd10; + v__h76341 = v__h76347 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h76282, + v__h76341, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h76398 = $stime; + v__h76457 = $stime; #0; end - v__h76392 = v__h76398 / 32'd10; + v__h76451 = v__h76457 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h76392, + v__h76451, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h76511 = $stime; + v__h76570 = $stime; #0; end - v__h76505 = v__h76511 / 32'd10; + v__h76564 = v__h76570 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h76505, + v__h76564, set_addr_map_addr_base, set_addr_map_addr_lim); end diff --git a/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v index 3022e50..1b21cdd 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v +++ b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:25 BST 2020 +// On Wed Jun 24 20:23:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 78c9db6..3ed86ce 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:47:18 BST 2020 +// On Wed Jun 24 20:36:37 BST 2020 // // // Ports: @@ -36,35 +36,22 @@ // master0_arregion O 4 // master0_arvalid O 1 // master0_rready O 1 -// master1_awid O 4 -// master1_awaddr O 64 -// master1_awlen O 8 -// master1_awsize O 3 -// master1_awburst O 2 -// master1_awlock O 1 -// master1_awcache O 4 -// master1_awprot O 3 -// master1_awqos O 4 -// master1_awregion O 4 -// master1_awvalid O 1 -// master1_wdata O 64 -// master1_wstrb O 8 -// master1_wlast O 1 -// master1_wuser O 1 -// master1_wvalid O 1 -// master1_bready O 1 -// master1_arid O 4 -// master1_araddr O 64 -// master1_arlen O 8 -// master1_arsize O 3 -// master1_arburst O 2 -// master1_arlock O 1 -// master1_arcache O 4 -// master1_arprot O 3 -// master1_arqos O 4 -// master1_arregion O 4 -// master1_arvalid O 1 -// master1_rready O 1 +// master1_aw_canPeek O 1 reg +// master1_aw_peek O 97 reg +// RDY_master1_aw_peek O 1 reg +// RDY_master1_aw_drop O 1 reg +// master1_w_canPeek O 1 reg +// master1_w_peek O 74 reg +// RDY_master1_w_peek O 1 reg +// RDY_master1_w_drop O 1 reg +// master1_b_canPut O 1 reg +// RDY_master1_b_put O 1 reg +// master1_ar_canPeek O 1 reg +// master1_ar_peek O 97 reg +// RDY_master1_ar_peek O 1 reg +// RDY_master1_ar_drop O 1 reg +// master1_r_canPut O 1 reg +// RDY_master1_r_put O 1 reg // RDY_set_verbosity O 1 const // debug_module_mem_server_awready O 1 // debug_module_mem_server_wready O 1 @@ -99,28 +86,23 @@ // start_fromhostAddr I 64 reg // master0_awready I 1 // master0_wready I 1 +// master0_bvalid I 1 // master0_bid I 5 // master0_bresp I 2 // master0_arready I 1 +// master0_rvalid I 1 // master0_rid I 5 // master0_rdata I 64 // master0_rresp I 2 // master0_rlast I 1 // master0_ruser I 1 -// master1_awready I 1 -// master1_wready I 1 -// master1_bid I 4 -// master1_bresp I 2 -// master1_arready I 1 -// master1_rid I 4 -// master1_rdata I 64 -// master1_rresp I 2 -// master1_rlast I 1 -// master1_ruser I 1 +// master1_b_put_val I 6 reg +// master1_r_put_val I 72 reg // m_external_interrupt_req_set_not_clear I 1 reg // s_external_interrupt_req_set_not_clear I 1 // non_maskable_interrupt_req_set_not_clear I 1 unused // set_verbosity_verbosity I 4 +// debug_module_mem_server_awvalid I 1 // debug_module_mem_server_awid I 5 // debug_module_mem_server_awaddr I 64 // debug_module_mem_server_awlen I 8 @@ -131,11 +113,13 @@ // debug_module_mem_server_awprot I 3 // debug_module_mem_server_awqos I 4 // debug_module_mem_server_awregion I 4 +// debug_module_mem_server_wvalid I 1 // debug_module_mem_server_wdata I 64 // debug_module_mem_server_wstrb I 8 // debug_module_mem_server_wlast I 1 // debug_module_mem_server_wuser I 1 // debug_module_mem_server_bready I 1 +// debug_module_mem_server_arvalid I 1 // debug_module_mem_server_arid I 5 // debug_module_mem_server_araddr I 64 // debug_module_mem_server_arlen I 8 @@ -153,14 +137,12 @@ // hart0_csr_mem_server_request_put I 77 reg // hart0_put_other_req_put I 4 // EN_start I 1 -// master0_bvalid I 1 -// master0_rvalid I 1 -// master1_bvalid I 1 -// master1_rvalid I 1 +// EN_master1_aw_drop I 1 +// EN_master1_w_drop I 1 +// EN_master1_b_put I 1 +// EN_master1_ar_drop I 1 +// EN_master1_r_put I 1 // EN_set_verbosity I 1 -// debug_module_mem_server_awvalid I 1 -// debug_module_mem_server_wvalid I 1 -// debug_module_mem_server_arvalid I 1 // EN_hart0_run_halt_server_request_put I 1 // EN_hart0_gpr_mem_server_request_put I 1 // EN_hart0_fpr_mem_server_request_put I 1 @@ -172,7 +154,8 @@ // EN_hart0_csr_mem_server_response_get I 1 // // Combinational paths from inputs to outputs: -// (debug_module_mem_server_awid, +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -182,13 +165,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bid -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bid +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -198,13 +181,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bresp -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bresp +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -214,13 +197,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_buser -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_buser +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -230,13 +213,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bvalid -// (debug_module_mem_server_arid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bvalid +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -245,9 +228,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rid -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rid +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -256,9 +239,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rdata -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rdata +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -267,9 +250,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rresp -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rresp +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -278,9 +261,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rlast -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rlast +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -289,9 +272,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_ruser -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_ruser +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -300,8 +283,7 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rvalid +// debug_module_mem_server_arregion) -> debug_module_mem_server_rvalid // // @@ -364,9 +346,9 @@ module mkProc(CLK, master0_wready, + master0_bvalid, master0_bid, master0_bresp, - master0_bvalid, master0_bready, @@ -394,89 +376,50 @@ module mkProc(CLK, master0_arready, + master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, master0_ruser, - master0_rvalid, master0_rready, - master1_awid, + master1_aw_canPeek, - master1_awaddr, + master1_aw_peek, + RDY_master1_aw_peek, - master1_awlen, + EN_master1_aw_drop, + RDY_master1_aw_drop, - master1_awsize, + master1_w_canPeek, - master1_awburst, + master1_w_peek, + RDY_master1_w_peek, - master1_awlock, + EN_master1_w_drop, + RDY_master1_w_drop, - master1_awcache, + master1_b_canPut, - master1_awprot, + master1_b_put_val, + EN_master1_b_put, + RDY_master1_b_put, - master1_awqos, + master1_ar_canPeek, - master1_awregion, + master1_ar_peek, + RDY_master1_ar_peek, - master1_awvalid, + EN_master1_ar_drop, + RDY_master1_ar_drop, - master1_awready, + master1_r_canPut, - master1_wdata, - - master1_wstrb, - - master1_wlast, - - master1_wuser, - - master1_wvalid, - - master1_wready, - - master1_bid, - master1_bresp, - master1_bvalid, - - master1_bready, - - master1_arid, - - master1_araddr, - - master1_arlen, - - master1_arsize, - - master1_arburst, - - master1_arlock, - - master1_arcache, - - master1_arprot, - - master1_arqos, - - master1_arregion, - - master1_arvalid, - - master1_arready, - - master1_rid, - master1_rdata, - master1_rresp, - master1_rlast, - master1_ruser, - master1_rvalid, - - master1_rready, + master1_r_put_val, + EN_master1_r_put, + RDY_master1_r_put, m_external_interrupt_req_set_not_clear, @@ -488,6 +431,7 @@ module mkProc(CLK, EN_set_verbosity, RDY_set_verbosity, + debug_module_mem_server_awvalid, debug_module_mem_server_awid, debug_module_mem_server_awaddr, debug_module_mem_server_awlen, @@ -498,15 +442,14 @@ module mkProc(CLK, debug_module_mem_server_awprot, debug_module_mem_server_awqos, debug_module_mem_server_awregion, - debug_module_mem_server_awvalid, debug_module_mem_server_awready, + debug_module_mem_server_wvalid, debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, debug_module_mem_server_wuser, - debug_module_mem_server_wvalid, debug_module_mem_server_wready, @@ -518,6 +461,7 @@ module mkProc(CLK, debug_module_mem_server_bready, + debug_module_mem_server_arvalid, debug_module_mem_server_arid, debug_module_mem_server_araddr, debug_module_mem_server_arlen, @@ -528,7 +472,6 @@ module mkProc(CLK, debug_module_mem_server_arprot, debug_module_mem_server_arqos, debug_module_mem_server_arregion, - debug_module_mem_server_arvalid, debug_module_mem_server_arready, @@ -649,9 +592,9 @@ module mkProc(CLK, input master0_wready; // action method master0_b_bflit + input master0_bvalid; input [4 : 0] master0_bid; input [1 : 0] master0_bresp; - input master0_bvalid; // value method master0_b_bready output master0_bready; @@ -695,128 +638,64 @@ module mkProc(CLK, input master0_arready; // action method master0_r_rflit + input master0_rvalid; input [4 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; input master0_ruser; - input master0_rvalid; // value method master0_r_rready output master0_rready; - // value method master1_aw_awid - output [3 : 0] master1_awid; + // value method master1_aw_canPeek + output master1_aw_canPeek; - // value method master1_aw_awaddr - output [63 : 0] master1_awaddr; + // value method master1_aw_peek + output [96 : 0] master1_aw_peek; + output RDY_master1_aw_peek; - // value method master1_aw_awlen - output [7 : 0] master1_awlen; + // action method master1_aw_drop + input EN_master1_aw_drop; + output RDY_master1_aw_drop; - // value method master1_aw_awsize - output [2 : 0] master1_awsize; + // value method master1_w_canPeek + output master1_w_canPeek; - // value method master1_aw_awburst - output [1 : 0] master1_awburst; + // value method master1_w_peek + output [73 : 0] master1_w_peek; + output RDY_master1_w_peek; - // value method master1_aw_awlock - output master1_awlock; + // action method master1_w_drop + input EN_master1_w_drop; + output RDY_master1_w_drop; - // value method master1_aw_awcache - output [3 : 0] master1_awcache; + // value method master1_b_canPut + output master1_b_canPut; - // value method master1_aw_awprot - output [2 : 0] master1_awprot; + // action method master1_b_put + input [5 : 0] master1_b_put_val; + input EN_master1_b_put; + output RDY_master1_b_put; - // value method master1_aw_awqos - output [3 : 0] master1_awqos; + // value method master1_ar_canPeek + output master1_ar_canPeek; - // value method master1_aw_awregion - output [3 : 0] master1_awregion; + // value method master1_ar_peek + output [96 : 0] master1_ar_peek; + output RDY_master1_ar_peek; - // value method master1_aw_awuser + // action method master1_ar_drop + input EN_master1_ar_drop; + output RDY_master1_ar_drop; - // value method master1_aw_awvalid - output master1_awvalid; + // value method master1_r_canPut + output master1_r_canPut; - // action method master1_aw_awready - input master1_awready; - - // value method master1_w_wdata - output [63 : 0] master1_wdata; - - // value method master1_w_wstrb - output [7 : 0] master1_wstrb; - - // value method master1_w_wlast - output master1_wlast; - - // value method master1_w_wuser - output master1_wuser; - - // value method master1_w_wvalid - output master1_wvalid; - - // action method master1_w_wready - input master1_wready; - - // action method master1_b_bflit - input [3 : 0] master1_bid; - input [1 : 0] master1_bresp; - input master1_bvalid; - - // value method master1_b_bready - output master1_bready; - - // value method master1_ar_arid - output [3 : 0] master1_arid; - - // value method master1_ar_araddr - output [63 : 0] master1_araddr; - - // value method master1_ar_arlen - output [7 : 0] master1_arlen; - - // value method master1_ar_arsize - output [2 : 0] master1_arsize; - - // value method master1_ar_arburst - output [1 : 0] master1_arburst; - - // value method master1_ar_arlock - output master1_arlock; - - // value method master1_ar_arcache - output [3 : 0] master1_arcache; - - // value method master1_ar_arprot - output [2 : 0] master1_arprot; - - // value method master1_ar_arqos - output [3 : 0] master1_arqos; - - // value method master1_ar_arregion - output [3 : 0] master1_arregion; - - // value method master1_ar_aruser - - // value method master1_ar_arvalid - output master1_arvalid; - - // action method master1_ar_arready - input master1_arready; - - // action method master1_r_rflit - input [3 : 0] master1_rid; - input [63 : 0] master1_rdata; - input [1 : 0] master1_rresp; - input master1_rlast; - input master1_ruser; - input master1_rvalid; - - // value method master1_r_rready - output master1_rready; + // action method master1_r_put + input [71 : 0] master1_r_put_val; + input EN_master1_r_put; + output RDY_master1_r_put; // action method m_external_interrupt_req input m_external_interrupt_req_set_not_clear; @@ -833,6 +712,7 @@ module mkProc(CLK, output RDY_set_verbosity; // action method debug_module_mem_server_aw_awflit + input debug_module_mem_server_awvalid; input [4 : 0] debug_module_mem_server_awid; input [63 : 0] debug_module_mem_server_awaddr; input [7 : 0] debug_module_mem_server_awlen; @@ -843,17 +723,16 @@ module mkProc(CLK, input [2 : 0] debug_module_mem_server_awprot; input [3 : 0] debug_module_mem_server_awqos; input [3 : 0] debug_module_mem_server_awregion; - input debug_module_mem_server_awvalid; // value method debug_module_mem_server_aw_awready output debug_module_mem_server_awready; // action method debug_module_mem_server_w_wflit + input debug_module_mem_server_wvalid; input [63 : 0] debug_module_mem_server_wdata; input [7 : 0] debug_module_mem_server_wstrb; input debug_module_mem_server_wlast; input debug_module_mem_server_wuser; - input debug_module_mem_server_wvalid; // value method debug_module_mem_server_w_wready output debug_module_mem_server_wready; @@ -873,6 +752,7 @@ module mkProc(CLK, input debug_module_mem_server_bready; // action method debug_module_mem_server_ar_arflit + input debug_module_mem_server_arvalid; input [4 : 0] debug_module_mem_server_arid; input [63 : 0] debug_module_mem_server_araddr; input [7 : 0] debug_module_mem_server_arlen; @@ -883,7 +763,6 @@ module mkProc(CLK, input [2 : 0] debug_module_mem_server_arprot; input [3 : 0] debug_module_mem_server_arqos; input [3 : 0] debug_module_mem_server_arregion; - input debug_module_mem_server_arvalid; // value method debug_module_mem_server_ar_arready output debug_module_mem_server_arready; @@ -955,22 +834,16 @@ module mkProc(CLK, output RDY_hart0_put_other_req_put; // signals for module outputs + wire [96 : 0] master1_ar_peek, master1_aw_peek; + wire [73 : 0] master1_w_peek; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; wire [63 : 0] debug_module_mem_server_rdata, master0_araddr, master0_awaddr, - master0_wdata, - master1_araddr, - master1_awaddr, - master1_wdata; - wire [7 : 0] master0_arlen, - master0_awlen, - master0_wstrb, - master1_arlen, - master1_awlen, - master1_wstrb; + master0_wdata; + wire [7 : 0] master0_arlen, master0_awlen, master0_wstrb; wire [4 : 0] debug_module_mem_server_bid, debug_module_mem_server_rid, master0_arid, @@ -980,29 +853,12 @@ module mkProc(CLK, master0_arregion, master0_awcache, master0_awqos, - master0_awregion, - master1_arcache, - master1_arid, - master1_arqos, - master1_arregion, - master1_awcache, - master1_awid, - master1_awqos, - master1_awregion; - wire [2 : 0] master0_arprot, - master0_arsize, - master0_awprot, - master0_awsize, - master1_arprot, - master1_arsize, - master1_awprot, - master1_awsize; + master0_awregion; + wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, master0_awsize; wire [1 : 0] debug_module_mem_server_bresp, debug_module_mem_server_rresp, master0_arburst, - master0_awburst, - master1_arburst, - master1_awburst; + master0_awburst; wire RDY_hart0_csr_mem_server_request_put, RDY_hart0_csr_mem_server_response_get, RDY_hart0_fpr_mem_server_request_put, @@ -1012,6 +868,14 @@ module mkProc(CLK, RDY_hart0_put_other_req_put, RDY_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_response_get, + RDY_master1_ar_drop, + RDY_master1_ar_peek, + RDY_master1_aw_drop, + RDY_master1_aw_peek, + RDY_master1_b_put, + RDY_master1_r_put, + RDY_master1_w_drop, + RDY_master1_w_peek, RDY_set_verbosity, RDY_start, debug_module_mem_server_arready, @@ -1031,15 +895,11 @@ module mkProc(CLK, master0_wlast, master0_wuser, master0_wvalid, - master1_arlock, - master1_arvalid, - master1_awlock, - master1_awvalid, - master1_bready, - master1_rready, - master1_wlast, - master1_wuser, - master1_wvalid; + master1_ar_canPeek, + master1_aw_canPeek, + master1_b_canPut, + master1_r_canPut, + master1_w_canPeek; // inlined wires wire [584 : 0] enqDst_1_0_lat_0$wget; @@ -1060,16 +920,8 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read; - wire [97 : 0] llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read; + wire [97 : 0] llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget, + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget; wire [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read, llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read, @@ -1077,11 +929,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read, - llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read; + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read; wire [73 : 0] enqDst_0_lat_0$wget, llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read, @@ -1091,30 +939,21 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget; - wire [72 : 0] llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget; + wire [72 : 0] llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget, propDstData_0_lat_0$wget, propDstData_1_lat_0$wget; - wire [71 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget; wire [65 : 0] llc_mem_server_enqDst_0_lat_0$wget; wire [64 : 0] mmioPlatform_toHostQ_enqReq_lat_0$wget; wire [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read, llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read, llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read; - wire [6 : 0] llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read; - wire [5 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget; + wire [6 : 0] llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget; wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, @@ -1124,29 +963,21 @@ module mkProc(CLK, wire enqDst_0_lat_0$whas, enqDst_1_0_lat_0$whas, llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas, + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas, + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas, + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas, + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas, llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas, llc_mem_server_propDstIdx_0_lat_1$whas, mmioPlatform_fromHostQ_deqReq_lat_0$whas, mmioPlatform_toHostQ_enqReq_lat_0$whas, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, propDstIdx_1_1_lat_1$whas, propDstIdx_1_lat_1$whas; @@ -1210,11 +1041,6 @@ module mkProc(CLK, wire [515 : 0] llc_axi4_adapter_rg_cline$D_IN; wire llc_axi4_adapter_rg_cline$EN; - // register llc_axi4_adapter_rg_rd_req_beat - reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat; - wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN; - wire llc_axi4_adapter_rg_rd_req_beat$EN; - // register llc_axi4_adapter_rg_rd_rsp_beat reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat; wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN; @@ -1453,41 +1279,26 @@ module mkProc(CLK, wire [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; wire mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN; - // register mmio_axi4_adapter_master_xactor_clearing - reg mmio_axi4_adapter_master_xactor_clearing; - wire mmio_axi4_adapter_master_xactor_clearing$D_IN, - mmio_axi4_adapter_master_xactor_clearing$EN; - - // register mmio_axi4_adapter_master_xactor_shim_arff_rv - reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv; - wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_arff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_awff_rv - reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv; - wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_awff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_bff_rv - reg [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv; - wire [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_bff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_rff_rv - reg [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv; - wire [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_rff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_wff_rv - reg [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv; - wire [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_wff_rv$EN; - // register mmio_axi4_adapter_read_req_addr reg [63 : 0] mmio_axi4_adapter_read_req_addr; wire [63 : 0] mmio_axi4_adapter_read_req_addr$D_IN; wire mmio_axi4_adapter_read_req_addr$EN; + // register mmio_axi4_adapter_rg_rd_rsp_beat + reg mmio_axi4_adapter_rg_rd_rsp_beat; + wire mmio_axi4_adapter_rg_rd_rsp_beat$D_IN, + mmio_axi4_adapter_rg_rd_rsp_beat$EN; + + // register mmio_axi4_adapter_rg_wr_req_beat + reg mmio_axi4_adapter_rg_wr_req_beat; + wire mmio_axi4_adapter_rg_wr_req_beat$D_IN, + mmio_axi4_adapter_rg_wr_req_beat$EN; + + // register mmio_axi4_adapter_rspData + reg [128 : 0] mmio_axi4_adapter_rspData; + wire [128 : 0] mmio_axi4_adapter_rspData$D_IN; + wire mmio_axi4_adapter_rspData$EN; + // register propDstData_0_rl reg [72 : 0] propDstData_0_rl; wire [72 : 0] propDstData_0_rl$D_IN; @@ -1721,6 +1532,51 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$ENQ, mmio_axi4_adapter_f_rsps_to_core$FULL_N; + // ports of submodule mmio_axi4_adapter_master_shim_arff + wire [96 : 0] mmio_axi4_adapter_master_shim_arff$D_IN, + mmio_axi4_adapter_master_shim_arff$D_OUT; + wire mmio_axi4_adapter_master_shim_arff$CLR, + mmio_axi4_adapter_master_shim_arff$DEQ, + mmio_axi4_adapter_master_shim_arff$EMPTY_N, + mmio_axi4_adapter_master_shim_arff$ENQ, + mmio_axi4_adapter_master_shim_arff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_awff + wire [96 : 0] mmio_axi4_adapter_master_shim_awff$D_IN, + mmio_axi4_adapter_master_shim_awff$D_OUT; + wire mmio_axi4_adapter_master_shim_awff$CLR, + mmio_axi4_adapter_master_shim_awff$DEQ, + mmio_axi4_adapter_master_shim_awff$EMPTY_N, + mmio_axi4_adapter_master_shim_awff$ENQ, + mmio_axi4_adapter_master_shim_awff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_bff + wire [5 : 0] mmio_axi4_adapter_master_shim_bff$D_IN, + mmio_axi4_adapter_master_shim_bff$D_OUT; + wire mmio_axi4_adapter_master_shim_bff$CLR, + mmio_axi4_adapter_master_shim_bff$DEQ, + mmio_axi4_adapter_master_shim_bff$EMPTY_N, + mmio_axi4_adapter_master_shim_bff$ENQ, + mmio_axi4_adapter_master_shim_bff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_rff + wire [71 : 0] mmio_axi4_adapter_master_shim_rff$D_IN, + mmio_axi4_adapter_master_shim_rff$D_OUT; + wire mmio_axi4_adapter_master_shim_rff$CLR, + mmio_axi4_adapter_master_shim_rff$DEQ, + mmio_axi4_adapter_master_shim_rff$EMPTY_N, + mmio_axi4_adapter_master_shim_rff$ENQ, + mmio_axi4_adapter_master_shim_rff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_wff + wire [73 : 0] mmio_axi4_adapter_master_shim_wff$D_IN, + mmio_axi4_adapter_master_shim_wff$D_OUT; + wire mmio_axi4_adapter_master_shim_wff$CLR, + mmio_axi4_adapter_master_shim_wff$DEQ, + mmio_axi4_adapter_master_shim_wff$EMPTY_N, + mmio_axi4_adapter_master_shim_wff$ENQ, + mmio_axi4_adapter_master_shim_wff$FULL_N; + // ports of submodule mmio_axi4_adapter_soc_map wire [63 : 0] mmio_axi4_adapter_soc_map$m_is_IO_addr_addr, mmio_axi4_adapter_soc_map$m_is_mem_addr_addr, @@ -1736,36 +1592,36 @@ module mkProc(CLK, CAN_FIRE_RL_enqDst_0_canon, CAN_FIRE_RL_enqDst_1_0_canon, CAN_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut, CAN_FIRE_RL_llc_mem_server_doEnq, CAN_FIRE_RL_llc_mem_server_dstSelectSrc, CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, @@ -1812,20 +1668,6 @@ module mkProc(CLK, CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone, CAN_FIRE_RL_mmioPlatform_waitMTimeDone, CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, @@ -1879,11 +1721,11 @@ module mkProc(CLK, CAN_FIRE_master0_b_bflit, CAN_FIRE_master0_r_rflit, CAN_FIRE_master0_w_wready, - CAN_FIRE_master1_ar_arready, - CAN_FIRE_master1_aw_awready, - CAN_FIRE_master1_b_bflit, - CAN_FIRE_master1_r_rflit, - CAN_FIRE_master1_w_wready, + CAN_FIRE_master1_ar_drop, + CAN_FIRE_master1_aw_drop, + CAN_FIRE_master1_b_put, + CAN_FIRE_master1_r_put, + CAN_FIRE_master1_w_drop, CAN_FIRE_non_maskable_interrupt_req, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_set_verbosity, @@ -1896,36 +1738,36 @@ module mkProc(CLK, WILL_FIRE_RL_enqDst_0_canon, WILL_FIRE_RL_enqDst_1_0_canon, WILL_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut, WILL_FIRE_RL_llc_mem_server_doEnq, WILL_FIRE_RL_llc_mem_server_dstSelectSrc, WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, @@ -1972,20 +1814,6 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone, WILL_FIRE_RL_mmioPlatform_waitMTimeDone, WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, @@ -2039,11 +1867,11 @@ module mkProc(CLK, WILL_FIRE_master0_b_bflit, WILL_FIRE_master0_r_rflit, WILL_FIRE_master0_w_wready, - WILL_FIRE_master1_ar_arready, - WILL_FIRE_master1_aw_awready, - WILL_FIRE_master1_b_bflit, - WILL_FIRE_master1_r_rflit, - WILL_FIRE_master1_w_wready, + WILL_FIRE_master1_ar_drop, + WILL_FIRE_master1_aw_drop, + WILL_FIRE_master1_b_put, + WILL_FIRE_master1_r_put, + WILL_FIRE_master1_w_drop, WILL_FIRE_non_maskable_interrupt_req, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_set_verbosity, @@ -2057,7 +1885,7 @@ module mkProc(CLK, MUX_llc$dma_memReq_enq_1__VAL_3, MUX_llc$dma_memReq_enq_1__VAL_4; wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, - MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; + MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2; wire [515 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [214 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, @@ -2074,7 +1902,7 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9; wire [129 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1, - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2; wire [128 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1, MUX_mmioPlatform_amoResp$write_1__VAL_2; wire [66 : 0] MUX_mmioPlatform_curReq$write_1__VAL_1, @@ -2115,46 +1943,51 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1, - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2, + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h221935; - reg [31 : 0] v__h221472; - reg [31 : 0] v__h11342; - reg [31 : 0] v__h15880; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h4363; - reg [31 : 0] v__h7984; - reg [31 : 0] v__h19409; - reg [31 : 0] v__h18412; - reg [31 : 0] v__h18942; - reg [31 : 0] v__h10403; - reg [31 : 0] v__h10598; - reg [31 : 0] v__h199123; - reg [31 : 0] v__h212832; - reg [31 : 0] v__h191102; - reg [31 : 0] v__h220458; - reg [31 : 0] v__h191691; - reg [31 : 0] v__h191877; - reg [31 : 0] v__h4357; - reg [31 : 0] v__h7978; - reg [31 : 0] v__h10397; - reg [31 : 0] v__h10592; - reg [31 : 0] v__h11336; - reg [31 : 0] v__h15874; - reg [31 : 0] v__h16017; - reg [31 : 0] v__h18406; - reg [31 : 0] v__h18936; - reg [31 : 0] v__h19403; - reg [31 : 0] v__h191096; - reg [31 : 0] v__h191685; - reg [31 : 0] v__h191871; - reg [31 : 0] v__h199117; - reg [31 : 0] v__h212826; - reg [31 : 0] v__h220452; - reg [31 : 0] v__h221466; - reg [31 : 0] v__h221929; + reg [31 : 0] v__h224105; + reg [31 : 0] v__h223657; + reg [31 : 0] v__h9702; + reg [31 : 0] v__h9897; + reg [31 : 0] v__h11307; + reg [31 : 0] v__h17239; + reg [31 : 0] v__h17410; + reg [31 : 0] v__h18103; + reg [31 : 0] v__h18189; + reg [31 : 0] v__h2280; + reg [31 : 0] v__h7388; + reg [31 : 0] v__h20501; + reg [31 : 0] v__h21031; + reg [31 : 0] v__h21496; + reg [31 : 0] v__h201308; + reg [31 : 0] v__h215017; + reg [31 : 0] v__h193285; + reg [31 : 0] v__h222643; + reg [31 : 0] v__h193874; + reg [31 : 0] v__h194060; + reg [31 : 0] v__h2274; + reg [31 : 0] v__h7382; + reg [31 : 0] v__h9696; + reg [31 : 0] v__h9891; + reg [31 : 0] v__h11301; + reg [31 : 0] v__h17233; + reg [31 : 0] v__h17404; + reg [31 : 0] v__h18097; + reg [31 : 0] v__h18183; + reg [31 : 0] v__h20495; + reg [31 : 0] v__h21025; + reg [31 : 0] v__h21490; + reg [31 : 0] v__h193279; + reg [31 : 0] v__h193868; + reg [31 : 0] v__h194054; + reg [31 : 0] v__h201302; + reg [31 : 0] v__h215011; + reg [31 : 0] v__h222637; + reg [31 : 0] v__h223651; + reg [31 : 0] v__h224099; // synopsys translate_on // remaining internal signals @@ -2162,210 +1995,248 @@ module mkProc(CLK, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937, - dword__h148173, - ld_data__h185995, - v_wdata__h213140; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351; - reg [7 : 0] v_wstrb__h213141; - reg [5 : 0] IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811; - reg [2 : 0] x__h98832; - reg [1 : 0] CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16; + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966, + dword__h150325, + ld_data__h188147, + v_wdata__h215325, + wflit_wdata__h18041; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379; + reg [7 : 0] v_wstrb__h215326, wflit_wstrb__h18042; + reg [5 : 0] IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839; + reg [2 : 0] x__h100922; + reg [1 : 0] CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677, - v_wuser__h213143, - x__h125469, - x__h98833; - wire [583 : 0] IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1648; - wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1797; - wire [517 : 0] IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1647; - wire [515 : 0] IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639, - IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1792; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1985, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1774; - wire [129 : 0] IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1131; - wire [128 : 0] amoExec___d1043, - amoExec___d1096, - amoExec___d1321, - amoExec___d887, - amoExec___d973; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1740, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1757, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1791, - _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213; - wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37, - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35; - wire [96 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13, - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11; - wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36, - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12; - wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34; - wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513, - IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511; - wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__258_BI_ETC___d1359; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619, - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126, - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885, - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021, - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949, - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073, - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571, - addr1__h88409, - data__h138449, - failed_testnum__h221515, - line_addr__h137882, - line_addr__h147990, - line_addr__h191238, - mmioPlatform_mtime__h57710, - newData__h43098, - newData__h51199, - v_awaddr__h212729, - value__h59417, - x__h46411, - x__h54489, - x__h62366, - x__h66321, - x__h68995, - x__h71490, - x__h77037; - wire [47 : 0] IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1112, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989; - wire [31 : 0] IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1107, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984, - IF_mmioPlatform_fetchingWay_330_THEN_mmioPlatf_ETC___d1356, - amo_req_data__h36993, - lower_data__h42399, + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705, + v_wuser__h215328, + x__h100923, + x__h127559; + wire [583 : 0] IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1676; + wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1825; + wire [517 : 0] IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1675; + wire [515 : 0] IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667, + IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1820; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2014, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1802; + wire [129 : 0] IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1159; + wire [128 : 0] amoExec___d1001, + amoExec___d1071, + amoExec___d1124, + amoExec___d1349, + amoExec___d915, + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1768, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1785, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1819; + wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34, + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32; + wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33; + wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31; + wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541, + IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539; + wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__286_BI_ETC___d1387; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154, + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101, + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599, + addr1__h90499, + data__h140598, + failed_testnum__h223700, + line_addr__h140031, + line_addr__h150142, + line_addr__h193421, + mmioPlatform_mtime__h59797, + newData__h45185, + newData__h53286, + v_awaddr__h214914, + value__h61504, + x__h48498, + x__h56576, + x__h64456, + x__h68411, + x__h71085, + x__h73580, + x__h79127; + wire [47 : 0] IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1140, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942; + wire [31 : 0] IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1135, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933, + IF_mmioPlatform_fetchingWay_358_THEN_mmioPlatf_ETC___d1384, + amo_req_data__h39080, + lower_data__h44486, mmioPlatform_mtime_BITS_31_TO_0__q8, mmioPlatform_mtime_BITS_63_TO_32__q7, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, - upper_data__h42400, - v__h42255, - v__h42292, - x_data__h39934; - wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1500; - wire [7 : 0] IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872, - mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877; - wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33; - wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1499; - wire [3 : 0] b__h191029, b__h4263, mmioPlatform_reqAmofunc__h86179; - wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1715, - v_awsize_val__h15192; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576; - wire IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929, - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785, - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924, - IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645, - IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064, - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1138, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334, - IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850, - IF_mmio_axi4_adapter_f_rsps_to_core_first__258_ETC___d1334, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597, - IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446, - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383, - IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679, - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516, - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523, - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390, - NOT_enqDst_0_rl_412_BIT_73_413_418_AND_SEL_ARR_ETC___d1506, - NOT_enqDst_1_0_rl_607_BIT_584_608_613_AND_SEL__ETC___d1803, - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207, - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2286, - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2289, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1161, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1256, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1267, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1277, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1325, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1337, - NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755, - core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2218, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902, - mmioPlatform_amoWaitWriteResp_271_OR_core_0_RD_ETC___d1274, - mmioPlatform_cycle_57_ULT_99___d458, - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339, - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996, - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941, - x__h114170, - x__h120734, - x__h98632; + upper_data__h44487, + v__h44342, + v__h44379, + x_data__h42021; + wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1528; + wire [7 : 0] IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900, + mem_req_rd_addr_arlen__h5411, + mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905; + wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30; + wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1527, + x__h15205, + x__h15217, + x__h15229, + x__h15241, + x__h15253, + x__h15265, + x__h15277, + x__h15289, + x__h15301, + x__h15313, + x__h15325, + x__h15337, + x__h15349, + x__h15361, + x__h15373, + y__h15206, + y__h15218, + y__h15230, + y__h15242, + y__h15254, + y__h15266, + y__h15278, + y__h15290, + y__h15302, + y__h15314, + y__h15326, + y__h15338, + y__h15350, + y__h15362, + y__h15374; + wire [3 : 0] b__h193221, b__h2174, mmioPlatform_reqAmofunc__h88269; + wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1743, + _theResult_____1_awsize_val__h17178; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604; + wire IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957, + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813, + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952, + IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673, + IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096, + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1166, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362, + IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878, + IF_mmio_axi4_adapter_f_rsps_to_core_first__286_ETC___d1362, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625, + IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474, + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411, + IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707, + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544, + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551, + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418, + NOT_enqDst_0_rl_440_BIT_73_441_446_AND_SEL_ARR_ETC___d1534, + NOT_enqDst_1_0_rl_635_BIT_584_636_641_AND_SEL__ETC___d1831, + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236, + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2315, + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2318, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1189, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1284, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1295, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1305, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1353, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1365, + NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709, + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, + _theResult____h13554, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783, + core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2247, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931, + mmioPlatform_amoWaitWriteResp_299_OR_core_0_RD_ETC___d1302, + mmioPlatform_cycle_85_ULT_99___d486, + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367, + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024, + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252, + mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, + mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210, + whichHalf___1__h15117, + x__h100722, + x__h10759, + x__h116260, + x__h122824, + x__h17973; // action method start assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; @@ -2375,47 +2246,47 @@ module mkProc(CLK, // value method master0_aw_awid assign master0_awid = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[97:93] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[97:93] ; // value method master0_aw_awaddr assign master0_awaddr = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[92:29] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[92:29] ; // value method master0_aw_awlen assign master0_awlen = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[28:21] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[28:21] ; // value method master0_aw_awsize assign master0_awsize = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[20:18] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[20:18] ; // value method master0_aw_awburst assign master0_awburst = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[17:16] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[17:16] ; // value method master0_aw_awlock assign master0_awlock = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[15] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[15] ; // value method master0_aw_awcache assign master0_awcache = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[14:11] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[14:11] ; // value method master0_aw_awprot assign master0_awprot = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[10:8] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[10:8] ; // value method master0_aw_awqos assign master0_awqos = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[7:4] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[7:4] ; // value method master0_aw_awregion assign master0_awregion = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[3:0] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[3:0] ; // value method master0_aw_awvalid assign master0_awvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek ; // action method master0_aw_awready assign CAN_FIRE_master0_aw_awready = 1'd1 ; @@ -2423,23 +2294,23 @@ module mkProc(CLK, // value method master0_w_wdata assign master0_wdata = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[73:10] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[73:10] ; // value method master0_w_wstrb assign master0_wstrb = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[9:2] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[9:2] ; // value method master0_w_wlast assign master0_wlast = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[1] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[1] ; // value method master0_w_wuser assign master0_wuser = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[0] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[0] ; // value method master0_w_wvalid assign master0_wvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek ; // action method master0_w_wready assign CAN_FIRE_master0_w_wready = 1'd1 ; @@ -2447,54 +2318,54 @@ module mkProc(CLK, // action method master0_b_bflit assign CAN_FIRE_master0_b_bflit = 1'd1 ; - assign WILL_FIRE_master0_b_bflit = master0_bvalid ; + assign WILL_FIRE_master0_b_bflit = 1'd1 ; // value method master0_b_bready assign master0_bready = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; // value method master0_ar_arid assign master0_arid = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[97:93] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[97:93] ; // value method master0_ar_araddr assign master0_araddr = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[92:29] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[92:29] ; // value method master0_ar_arlen assign master0_arlen = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[28:21] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[28:21] ; // value method master0_ar_arsize assign master0_arsize = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[20:18] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[20:18] ; // value method master0_ar_arburst assign master0_arburst = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[17:16] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[17:16] ; // value method master0_ar_arlock assign master0_arlock = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[15] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[15] ; // value method master0_ar_arcache assign master0_arcache = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[14:11] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[14:11] ; // value method master0_ar_arprot assign master0_arprot = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[10:8] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[10:8] ; // value method master0_ar_arqos assign master0_arqos = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[7:4] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[7:4] ; // value method master0_ar_arregion assign master0_arregion = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[3:0] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[3:0] ; // value method master0_ar_arvalid assign master0_arvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek ; // action method master0_ar_arready assign CAN_FIRE_master0_ar_arready = 1'd1 ; @@ -2502,144 +2373,64 @@ module mkProc(CLK, // action method master0_r_rflit assign CAN_FIRE_master0_r_rflit = 1'd1 ; - assign WILL_FIRE_master0_r_rflit = master0_rvalid ; + assign WILL_FIRE_master0_r_rflit = 1'd1 ; // value method master0_r_rready assign master0_rready = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - // value method master1_aw_awid - assign master1_awid = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[96:93] ; + // value method master1_aw_canPeek + assign master1_aw_canPeek = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; - // value method master1_aw_awaddr - assign master1_awaddr = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[92:29] ; + // value method master1_aw_peek + assign master1_aw_peek = mmio_axi4_adapter_master_shim_awff$D_OUT ; + assign RDY_master1_aw_peek = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; - // value method master1_aw_awlen - assign master1_awlen = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[28:21] ; + // action method master1_aw_drop + assign RDY_master1_aw_drop = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; + assign CAN_FIRE_master1_aw_drop = + mmio_axi4_adapter_master_shim_awff$EMPTY_N ; + assign WILL_FIRE_master1_aw_drop = EN_master1_aw_drop ; - // value method master1_aw_awsize - assign master1_awsize = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[20:18] ; + // value method master1_w_canPeek + assign master1_w_canPeek = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; - // value method master1_aw_awburst - assign master1_awburst = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[17:16] ; + // value method master1_w_peek + assign master1_w_peek = mmio_axi4_adapter_master_shim_wff$D_OUT ; + assign RDY_master1_w_peek = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; - // value method master1_aw_awlock - assign master1_awlock = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[15] ; + // action method master1_w_drop + assign RDY_master1_w_drop = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; + assign CAN_FIRE_master1_w_drop = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; + assign WILL_FIRE_master1_w_drop = EN_master1_w_drop ; - // value method master1_aw_awcache - assign master1_awcache = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[14:11] ; + // value method master1_b_canPut + assign master1_b_canPut = mmio_axi4_adapter_master_shim_bff$FULL_N ; - // value method master1_aw_awprot - assign master1_awprot = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[10:8] ; + // action method master1_b_put + assign RDY_master1_b_put = mmio_axi4_adapter_master_shim_bff$FULL_N ; + assign CAN_FIRE_master1_b_put = mmio_axi4_adapter_master_shim_bff$FULL_N ; + assign WILL_FIRE_master1_b_put = EN_master1_b_put ; - // value method master1_aw_awqos - assign master1_awqos = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[7:4] ; + // value method master1_ar_canPeek + assign master1_ar_canPeek = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; - // value method master1_aw_awregion - assign master1_awregion = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[3:0] ; + // value method master1_ar_peek + assign master1_ar_peek = mmio_axi4_adapter_master_shim_arff$D_OUT ; + assign RDY_master1_ar_peek = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; - // value method master1_aw_awvalid - assign master1_awvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + // action method master1_ar_drop + assign RDY_master1_ar_drop = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; + assign CAN_FIRE_master1_ar_drop = + mmio_axi4_adapter_master_shim_arff$EMPTY_N ; + assign WILL_FIRE_master1_ar_drop = EN_master1_ar_drop ; - // action method master1_aw_awready - assign CAN_FIRE_master1_aw_awready = 1'd1 ; - assign WILL_FIRE_master1_aw_awready = 1'd1 ; + // value method master1_r_canPut + assign master1_r_canPut = mmio_axi4_adapter_master_shim_rff$FULL_N ; - // value method master1_w_wdata - assign master1_wdata = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[73:10] ; - - // value method master1_w_wstrb - assign master1_wstrb = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[9:2] ; - - // value method master1_w_wlast - assign master1_wlast = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[1] ; - - // value method master1_w_wuser - assign master1_wuser = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[0] ; - - // value method master1_w_wvalid - assign master1_wvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - - // action method master1_w_wready - assign CAN_FIRE_master1_w_wready = 1'd1 ; - assign WILL_FIRE_master1_w_wready = 1'd1 ; - - // action method master1_b_bflit - assign CAN_FIRE_master1_b_bflit = 1'd1 ; - assign WILL_FIRE_master1_b_bflit = master1_bvalid ; - - // value method master1_b_bready - assign master1_bready = !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - - // value method master1_ar_arid - assign master1_arid = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[96:93] ; - - // value method master1_ar_araddr - assign master1_araddr = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[92:29] ; - - // value method master1_ar_arlen - assign master1_arlen = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[28:21] ; - - // value method master1_ar_arsize - assign master1_arsize = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[20:18] ; - - // value method master1_ar_arburst - assign master1_arburst = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[17:16] ; - - // value method master1_ar_arlock - assign master1_arlock = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[15] ; - - // value method master1_ar_arcache - assign master1_arcache = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[14:11] ; - - // value method master1_ar_arprot - assign master1_arprot = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[10:8] ; - - // value method master1_ar_arqos - assign master1_arqos = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[7:4] ; - - // value method master1_ar_arregion - assign master1_arregion = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[3:0] ; - - // value method master1_ar_arvalid - assign master1_arvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - - // action method master1_ar_arready - assign CAN_FIRE_master1_ar_arready = 1'd1 ; - assign WILL_FIRE_master1_ar_arready = 1'd1 ; - - // action method master1_r_rflit - assign CAN_FIRE_master1_r_rflit = 1'd1 ; - assign WILL_FIRE_master1_r_rflit = master1_rvalid ; - - // value method master1_r_rready - assign master1_rready = !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; + // action method master1_r_put + assign RDY_master1_r_put = mmio_axi4_adapter_master_shim_rff$FULL_N ; + assign CAN_FIRE_master1_r_put = mmio_axi4_adapter_master_shim_rff$FULL_N ; + assign WILL_FIRE_master1_r_put = EN_master1_r_put ; // action method m_external_interrupt_req assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; @@ -2660,8 +2451,7 @@ module mkProc(CLK, // action method debug_module_mem_server_aw_awflit assign CAN_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_aw_awflit = - debug_module_mem_server_awvalid ; + assign WILL_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ; // value method debug_module_mem_server_aw_awready assign debug_module_mem_server_awready = @@ -2669,8 +2459,7 @@ module mkProc(CLK, // action method debug_module_mem_server_w_wflit assign CAN_FIRE_debug_module_mem_server_w_wflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_w_wflit = - debug_module_mem_server_wvalid ; + assign WILL_FIRE_debug_module_mem_server_w_wflit = 1'd1 ; // value method debug_module_mem_server_w_wready assign debug_module_mem_server_wready = @@ -2678,15 +2467,15 @@ module mkProc(CLK, // value method debug_module_mem_server_b_bid assign debug_module_mem_server_bid = - llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33[6:2] ; + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30[6:2] ; // value method debug_module_mem_server_b_bresp assign debug_module_mem_server_bresp = - llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33[1:0] ; + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30[1:0] ; // value method debug_module_mem_server_b_bvalid assign debug_module_mem_server_bvalid = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek ; // action method debug_module_mem_server_b_bready assign CAN_FIRE_debug_module_mem_server_b_bready = 1'd1 ; @@ -2694,8 +2483,7 @@ module mkProc(CLK, // action method debug_module_mem_server_ar_arflit assign CAN_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_ar_arflit = - debug_module_mem_server_arvalid ; + assign WILL_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ; // value method debug_module_mem_server_ar_arready assign debug_module_mem_server_arready = @@ -2703,27 +2491,27 @@ module mkProc(CLK, // value method debug_module_mem_server_r_rid assign debug_module_mem_server_rid = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[72:68] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[72:68] ; // value method debug_module_mem_server_r_rdata assign debug_module_mem_server_rdata = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[67:4] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[67:4] ; // value method debug_module_mem_server_r_rresp assign debug_module_mem_server_rresp = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[3:2] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[3:2] ; // value method debug_module_mem_server_r_rlast assign debug_module_mem_server_rlast = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[1] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[1] ; // value method debug_module_mem_server_r_ruser assign debug_module_mem_server_ruser = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[0] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[0] ; // value method debug_module_mem_server_r_rvalid assign debug_module_mem_server_rvalid = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek ; // action method debug_module_mem_server_r_rready assign CAN_FIRE_debug_module_mem_server_r_rready = 1'd1 ; @@ -3081,6 +2869,66 @@ module mkProc(CLK, .FULL_N(mmio_axi4_adapter_f_rsps_to_core$FULL_N), .EMPTY_N(mmio_axi4_adapter_f_rsps_to_core$EMPTY_N)); + // submodule mmio_axi4_adapter_master_shim_arff + FIFO2 #(.width(32'd97), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_arff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_arff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_arff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_arff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_arff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_arff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_arff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_arff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_awff + FIFO2 #(.width(32'd97), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_awff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_awff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_awff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_awff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_awff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_awff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_awff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_bff + FIFO2 #(.width(32'd6), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_bff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_bff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_bff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_bff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_bff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_bff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_bff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_bff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_rff + FIFO2 #(.width(32'd72), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_rff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_rff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_rff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_rff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_rff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_rff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_rff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_rff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_wff + FIFO2 #(.width(32'd74), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_wff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_wff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_wff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_wff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_wff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_wff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_wff$EMPTY_N)); + // submodule mmio_axi4_adapter_soc_map mkSoC_Map mmio_axi4_adapter_soc_map(.CLK(CLK), .RST_N(RST_N), @@ -3126,7 +2974,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && - IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414 ; + IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3150,7 +2998,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609 ; + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3240,22 +3088,41 @@ module mkProc(CLK, assign CAN_FIRE_RL_rl_tohost = !mmioPlatform_toHostQ_empty ; assign WILL_FIRE_RL_rl_tohost = CAN_FIRE_RL_rl_tohost ; + // rule RL_mmio_axi4_adapter_rl_handle_read_rsps + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + mmio_axi4_adapter_master_shim_rff$EMPTY_N && + (!mmio_axi4_adapter_master_shim_rff$D_OUT[1] || + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + // rule RL_mmio_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 && + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = - mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 && + mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd1 && - b__h4263 == 4'd0 ; + b__h2174 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + + // rule RL_mmio_axi4_adapter_rl_discard_write_rsp + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + b__h2174 != 4'd0 && mmio_axi4_adapter_master_shim_bff$EMPTY_N && + (mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 || + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_handle_non_Ld_St assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = @@ -3265,123 +3132,6 @@ module mkProc(CLK, assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ; - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && - mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = - !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] && - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ; - - // rule RL_mmio_axi4_adapter_rl_discard_write_rsp - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - !mmio_axi4_adapter_master_xactor_clearing && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[6] && - b__h4263 != 4'd0 && - (mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 || - mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && - mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = - !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] && - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ; - - // rule RL_mmio_axi4_adapter_rl_handle_read_rsps - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - !mmio_axi4_adapter_master_xactor_clearing && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72] && - mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // rule RL_mmio_axi4_adapter_master_xactor_do_clear - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = - mmio_axi4_adapter_master_xactor_clearing ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = - mmio_axi4_adapter_master_xactor_clearing ; - // rule RL_mmioPlatform_propagateTime assign CAN_FIRE_RL_mmioPlatform_propagateTime = mmioPlatform_state != 2'd0 ; assign WILL_FIRE_RL_mmioPlatform_propagateTime = @@ -3390,23 +3140,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_57_ULT_99___d458 ; + mmioPlatform_cycle_85_ULT_99___d486 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_57_ULT_99___d458 ; + !mmioPlatform_cycle_85_ULT_99___d486 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 && + NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3423,7 +3173,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786 && + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3432,7 +3182,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850 && + IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3478,7 +3228,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h71490 == 64'd0 || + x__h73580 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3496,7 +3246,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1161 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1189 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3504,37 +3254,37 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1256 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1284 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1267 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1295 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - mmioPlatform_amoWaitWriteResp_271_OR_core_0_RD_ETC___d1274 && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1277 ; + mmioPlatform_amoWaitWriteResp_299_OR_core_0_RD_ETC___d1302 && + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1305 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1325 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1353 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__258_ETC___d1334 && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1337 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__286_ETC___d1362 && + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1365 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3648,7 +3398,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3667,47 +3417,47 @@ module mkProc(CLK, assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut ; // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = @@ -3716,7 +3466,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3728,7 +3478,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3747,7 +3497,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3758,7 +3508,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3771,7 +3521,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3781,7 +3531,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3798,45 +3548,45 @@ module mkProc(CLK, !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas && !llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ; + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas && !llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ; + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop ; // rule RL_llc_mem_server_axi4_slave_xactor_do_clear assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear = @@ -3877,110 +3627,110 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && - b__h191029 == 4'd0 ; + b__h193221 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut = + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas && llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = + // rule RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] && - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ; + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = !llc_axi4_adapter_master_xactor_clearing && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] && - b__h191029 != 4'd0 ; + b__h193221 != 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut = + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas && llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = + // rule RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] && - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ; + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut ; // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2218 ; + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2247 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3993,7 +3743,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ; + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4001,25 +3751,25 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 || + (!mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4049,12 +3799,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && @@ -4080,31 +3830,33 @@ module mkProc(CLK, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 && !mmio_axi4_adapter_soc_map$m_is_IO_addr ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_master_shim_rff$D_OUT[1] ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3 = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0 ; + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0 ; assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = - { 1'd0, llc$to_child_toC_first[586:1] } ; - assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd1, llc$to_child_toC_first[586:521], llc$to_child_toC_first[519:0] } ; + assign MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2 = + { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amo_req_data__h36993 : - x_data__h39934 } ; + amo_req_data__h39080 : + x_data__h42021 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4120,16 +3872,16 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 67'h60000000000000000, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 3'd6, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 65'h0AAAAAAAAAAAAAAAA, - mmio_axi4_adapter_f_rsps_to_core_first__258_BI_ETC___d1359 } ; + mmio_axi4_adapter_f_rsps_to_core_first__286_BI_ETC___d1387 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = @@ -4138,24 +3890,24 @@ module mkProc(CLK, { 3'd6, mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h42255, 32'd0 }, + { v__h44342, 32'd0 }, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1131 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1159 } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = { llc_mem_server_rg_cacheline_cache_addr, 64'hFFFFFFFFFFFFFFFF, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h137882, + { line_addr__h140031, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h147990, + { line_addr__h150142, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4175,14 +3927,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1985, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2014, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd0) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4190,21 +3942,21 @@ module mkProc(CLK, { 65'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 } ; + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 } ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = { 1'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049, 64'd0 } ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) ? 67'h1AAAAAAAAAAAAAAAA : - ((!core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) ? + ((!core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) ? 67'h2AAAAAAAAAAAAAAAA : - IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513) ; + IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, (mmioPlatform_instSel == 2'd3) ? @@ -4217,11 +3969,11 @@ module mkProc(CLK, mmioPlatform_instSel + 2'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_3 = @@ -4232,32 +3984,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 or + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 or + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_5 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_5 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_5 = - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4265,95 +4017,79 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_6 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - (mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ? + (mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - amoExec___d1321 } ; + amoExec___d1349 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { addr1__h88409, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + { addr1__h90499, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ; - assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = - { mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0, - 1'd0, - _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 } ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = + { mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0, + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 } ; // inlined wires - assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = - { master1_bid, master1_bresp } ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = - master1_bvalid && - !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = - { master1_rid, - master1_rdata, - master1_rresp, - master1_rlast, - master1_ruser } ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = - master1_rvalid && - !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h71490 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73580 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h71490 != 64'd0 ; + x__h73580 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h66321 == 64'd0 ; + x__h68411 == 64'd0 ; assign propDstIdx_1_lat_1$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 && - x__h98632 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 && + x__h100722 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17, - SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1500 } ; + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1528 } ; assign enqDst_0_lat_0$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 ; assign propDstIdx_1_1_lat_1$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 && - x__h120734 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 && + x__h122824 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1797 } ; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1825 } ; assign enqDst_1_0_lat_0$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 ; + assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { debug_module_mem_server_awid, debug_module_mem_server_awaddr, debug_module_mem_server_awlen, @@ -4364,18 +4100,18 @@ module mkProc(CLK, debug_module_mem_server_awprot, debug_module_mem_server_awqos, debug_module_mem_server_awregion } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas = debug_module_mem_server_awvalid && !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget = + assign llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget = { debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, debug_module_mem_server_wuser } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas = debug_module_mem_server_wvalid && !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget = + assign llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget = { debug_module_mem_server_arid, debug_module_mem_server_araddr, debug_module_mem_server_arlen, @@ -4386,159 +4122,60 @@ module mkProc(CLK, debug_module_mem_server_arprot, debug_module_mem_server_arqos, debug_module_mem_server_arregion } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas = debug_module_mem_server_arvalid && !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071 } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103 } ; + assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = + assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = master0_bvalid && !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; - assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = + assign llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget = { master0_rid, master0_rdata, master0_rresp, master0_rlast, master0_ruser } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = + assign llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas = master0_rvalid && !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && - master1_awready ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - master1_wready ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && - master1_arready ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && debug_module_mem_server_bready ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && debug_module_mem_server_rready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && master0_awready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && master0_wready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && master0_arready ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 5'd16, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], - 8'd0, - v_awsize_val__h15192, - 18'd65536 } ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_awff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129], - 2'd2 } ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_wff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? - 75'h2AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 75'h2AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ? - mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_bff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read = - WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? - 7'd42 : - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 7'd42 : - mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 5'd16, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], - 29'd851968 } ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_arff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ? - mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_rff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ? - 73'h0AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 73'h0AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h4263 - 4'd1 ; + b__h2174 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h4263 ; + b__h2174 ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_awff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read = @@ -4551,9 +4188,9 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_wff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read = @@ -4564,12 +4201,16 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_clearing ? 75'h2AAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[97:93], + 2'd0 } ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read = WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? - 8'd128 : + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_bff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop ? 8'd42 : llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read = @@ -4578,9 +4219,9 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_arff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read = @@ -4592,13 +4233,16 @@ module mkProc(CLK, 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 = - { 6'd32, dword__h148173, 4'd2 } ; + { 1'd1, + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[97:93], + dword__h150325, + 4'd2 } ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_rff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop ? 74'h0AAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read = @@ -4609,13 +4253,13 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 6'd32, v_awaddr__h212729, 29'd15532032 } ; + { 6'd32, v_awaddr__h214914, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read = llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_awff_rv ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop ? 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read = @@ -4624,16 +4268,16 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - v_wdata__h213140, - v_wstrb__h213141, + v_wdata__h215325, + v_wstrb__h215326, llc_axi4_adapter_rg_wr_req_beat == 3'd7, - v_wuser__h213143 } ; + v_wuser__h215328 } ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_wff_rv ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop ? 75'h2AAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read = @@ -4642,9 +4286,9 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = { 1'd1, - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget } ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut ? llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_bff_rv ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read = @@ -4656,13 +4300,13 @@ module mkProc(CLK, 8'd42 : llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 6'd32, line_addr__h191238, 29'd15532032 } ; + { 6'd32, line_addr__h193421, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ? llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_arff_rv ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop ? 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read = @@ -4671,9 +4315,9 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = { 1'd1, - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget } ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut ? llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_rff_rv ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read = @@ -4690,11 +4334,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h191029 - 4'd1 ; + b__h193221 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h191029 ; + b__h193221 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4706,7 +4350,7 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414, + IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : (enqDst_0_lat_0$whas ? @@ -4717,8 +4361,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609, - IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1648 } ; + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637, + IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1676 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4762,14 +4406,10 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253 ; + IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; - // register llc_axi4_adapter_rg_rd_req_beat - assign llc_axi4_adapter_rg_rd_req_beat$D_IN = 3'h0 ; - assign llc_axi4_adapter_rg_rd_req_beat$EN = 1'b0 ; - // register llc_axi4_adapter_rg_rd_rsp_beat assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN = llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; @@ -4815,7 +4455,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081, + IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4825,20 +4465,20 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h137882 : - line_addr__h147990 ; + line_addr__h140031 : + line_addr__h150142 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4921,7 +4561,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ; + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4934,11 +4574,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 && + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4948,11 +4588,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ; + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -5003,16 +4643,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ; + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h51199 : + newData__h53286 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -5021,7 +4661,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h43098 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h45185 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5031,9 +4671,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -5142,7 +4782,7 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = !mmioPlatform_toHostQ_clearReq_rl && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -5163,7 +4803,7 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = !mmioPlatform_toHostQ_clearReq_rl && - (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 || + (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl && mmioPlatform_toHostQ_full) ; @@ -5176,7 +4816,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5184,15 +4824,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5203,36 +4843,6 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_clearing - assign mmio_axi4_adapter_master_xactor_clearing$D_IN = 1'd0 ; - assign mmio_axi4_adapter_master_xactor_clearing$EN = - mmio_axi4_adapter_master_xactor_clearing ; - - // register mmio_axi4_adapter_master_xactor_shim_arff_rv - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_awff_rv - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_bff_rv - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_rff_rv - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_wff_rv - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_read_req_addr assign mmio_axi4_adapter_read_req_addr$D_IN = mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; @@ -5240,6 +4850,30 @@ module mkProc(CLK, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr ; + // register mmio_axi4_adapter_rg_rd_rsp_beat + assign mmio_axi4_adapter_rg_rd_rsp_beat$D_IN = + !mmio_axi4_adapter_master_shim_rff$D_OUT[1] && x__h10759 ; + assign mmio_axi4_adapter_rg_rd_rsp_beat$EN = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + + // register mmio_axi4_adapter_rg_wr_req_beat + assign mmio_axi4_adapter_rg_wr_req_beat$D_IN = + !whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + !mmio_axi4_adapter_rg_wr_req_beat && + x__h17973 ; + assign mmio_axi4_adapter_rg_wr_req_beat$EN = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + + // register mmio_axi4_adapter_rspData + assign mmio_axi4_adapter_rspData$D_IN = + mmio_axi4_adapter_master_shim_rff$D_OUT[1] ? + 129'd0 : + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 ; + assign mmio_axi4_adapter_rspData$EN = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + // register propDstData_0_rl assign propDstData_0_rl$D_IN = CAN_FIRE_RL_srcPropose ? @@ -5249,28 +4883,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538, + { IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[517] : propDstData_1_0_rl[517], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516:1] : propDstData_1_0_rl[516:1], - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559 } ; + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576, + { IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[517] : propDstData_1_1_rl[517], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516:1] : propDstData_1_1_rl[516:1], - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597 } ; + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5282,26 +4916,26 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = - !NOT_enqDst_0_rl_412_BIT_73_413_418_AND_SEL_ARR_ETC___d1506 && - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383 ; + !NOT_enqDst_0_rl_440_BIT_73_441_446_AND_SEL_ARR_ETC___d1534 && + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = - !NOT_enqDst_1_0_rl_607_BIT_584_608_613_AND_SEL__ETC___d1803 && - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516 ; + !NOT_enqDst_1_0_rl_635_BIT_584_636_641_AND_SEL__ETC___d1831 && + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523 ; + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390 ; + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 @@ -5320,9 +4954,9 @@ module mkProc(CLK, assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq ? + WILL_FIRE_RL_sendPRs ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : - MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; + MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2 ; assign core_0$hart0_csr_mem_server_request_put = hart0_csr_mem_server_request_put ; assign core_0$hart0_fpr_mem_server_request_put = @@ -5332,9 +4966,9 @@ module mkProc(CLK, assign core_0$hart0_run_halt_server_request_put = hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq_1 ? + WILL_FIRE_RL_sendPRs_1 ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : - MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; + MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2 ; always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 or MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 or @@ -5420,7 +5054,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h185995, llc$dma_respLd_first[3] } ; + { ld_data__h188147, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5428,11 +5062,11 @@ module mkProc(CLK, assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ; assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ; assign core_0$EN_dCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ; + WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ; assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; + WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ; assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_llc_mem_server_srcPropose ; assign core_0$EN_tlbToMem_respLd_enq = @@ -5443,13 +5077,13 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp || WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 || + (!mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -5459,15 +5093,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_processFromHost ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 || + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5549,13 +5183,13 @@ module mkProc(CLK, enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645 } ; + { IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5648,8 +5282,8 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; assign mmio_axi4_adapter_f_reqs_from_core$DEQ = + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St || - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ; @@ -5657,8 +5291,8 @@ module mkProc(CLK, always@(MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 or MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 or MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 or - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps or - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3) + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 or + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1: @@ -5666,10 +5300,10 @@ module mkProc(CLK, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1; MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2: mmio_axi4_adapter_f_rsps_to_core$D_IN = - 130'h200000000000000000000000000000000; - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps: + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3: mmio_axi4_adapter_f_rsps_to_core$D_IN = - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + 130'h200000000000000000000000000000000; default: mmio_axi4_adapter_f_rsps_to_core$D_IN = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -5678,16 +5312,69 @@ module mkProc(CLK, (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req) && !mmio_axi4_adapter_soc_map$m_is_IO_addr || + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_master_shim_rff$D_OUT[1] || WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0 || - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0 ; assign mmio_axi4_adapter_f_rsps_to_core$DEQ = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; assign mmio_axi4_adapter_f_rsps_to_core$CLR = 1'b0 ; + // submodule mmio_axi4_adapter_master_shim_arff + assign mmio_axi4_adapter_master_shim_arff$D_IN = + { 4'd0, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + mem_req_rd_addr_arlen__h5411, + 21'd851968 } ; + assign mmio_axi4_adapter_master_shim_arff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_shim_arff$DEQ = EN_master1_ar_drop ; + assign mmio_axi4_adapter_master_shim_arff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_awff + assign mmio_axi4_adapter_master_shim_awff$D_IN = + { 4'd0, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + mem_req_rd_addr_arlen__h5411, + _theResult_____1_awsize_val__h17178, + 18'd65536 } ; + assign mmio_axi4_adapter_master_shim_awff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 ; + assign mmio_axi4_adapter_master_shim_awff$DEQ = EN_master1_aw_drop ; + assign mmio_axi4_adapter_master_shim_awff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_bff + assign mmio_axi4_adapter_master_shim_bff$D_IN = master1_b_put_val ; + assign mmio_axi4_adapter_master_shim_bff$ENQ = EN_master1_b_put ; + assign mmio_axi4_adapter_master_shim_bff$DEQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ; + assign mmio_axi4_adapter_master_shim_bff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_rff + assign mmio_axi4_adapter_master_shim_rff$D_IN = master1_r_put_val ; + assign mmio_axi4_adapter_master_shim_rff$ENQ = EN_master1_r_put ; + assign mmio_axi4_adapter_master_shim_rff$DEQ = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + assign mmio_axi4_adapter_master_shim_rff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_wff + assign mmio_axi4_adapter_master_shim_wff$D_IN = + { wflit_wdata__h18041, + wflit_wstrb__h18042, + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat, + 1'd0 } ; + assign mmio_axi4_adapter_master_shim_wff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_shim_wff$DEQ = EN_master1_w_drop ; + assign mmio_axi4_adapter_master_shim_wff$CLR = 1'b0 ; + // submodule mmio_axi4_adapter_soc_map assign mmio_axi4_adapter_soc_map$m_is_IO_addr_addr = mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; @@ -5695,41 +5382,41 @@ module mkProc(CLK, assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current({ 65'd0, - value__h59417 }), + value__h61504 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d887)); - module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d915)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current({ 65'd0, - mmioPlatform_mtime__h57710 }), + mmioPlatform_mtime__h59797 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d973)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1001)); + module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current(129'd0), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d1043)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1071)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), - .amoExec_current({ 65'd0, x__h77037 }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), + .amoExec_current({ 65'd0, x__h79127 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d1096)); - module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h86179, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1124)); + module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88269, ((mmioPlatform_reqBE[0] ? 5'd1 : 5'd0) + @@ -5785,294 +5472,294 @@ module mkProc(CLK, .amoExec_wordIdx(mmioPlatform_curReq[3:2]), .amoExec_current(mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0]), .amoExec_inpt(mmioPlatform_reqData), - .amoExec(amoExec___d1321)); - assign IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929 = - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + .amoExec(amoExec___d1349)); + assign IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957 = + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1107 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - mmioPlatform_fromHostQ_data_0[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - mmioPlatform_fromHostQ_data_0[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - mmioPlatform_fromHostQ_data_0[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1112 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1107, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - mmioPlatform_fromHostQ_data_0[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - mmioPlatform_mtimecmp_0[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - mmioPlatform_mtimecmp_0[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - mmioPlatform_mtimecmp_0[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - mmioPlatform_mtimecmp_0[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : mmioPlatform_mtime[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : mmioPlatform_mtime[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : mmioPlatform_mtime[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : mmioPlatform_mtime[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513 = - (!core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) ? + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1135 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + mmioPlatform_fromHostQ_data_0[63:56], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + mmioPlatform_fromHostQ_data_0[55:48], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + mmioPlatform_fromHostQ_data_0[47:40], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + mmioPlatform_fromHostQ_data_0[39:32] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1140 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1135, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + mmioPlatform_fromHostQ_data_0[31:24], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + mmioPlatform_fromHostQ_data_0[23:16] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + mmioPlatform_mtimecmp_0[63:56], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + mmioPlatform_mtimecmp_0[55:48], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + mmioPlatform_mtimecmp_0[47:40], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + mmioPlatform_mtimecmp_0[39:32] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + mmioPlatform_mtimecmp_0[31:24], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + mmioPlatform_mtimecmp_0[23:16] } ; + assign IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541 = + (!core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) ? 67'h3AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511) ; - assign IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785 = + IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539) ; + assign IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 = - newData__h43098 <= mmioPlatform_mtime ; - assign IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511 = - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 ? + assign IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 = + newData__h45185 <= mmioPlatform_mtime ; + assign IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539 = + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 ? 67'h5AAAAAAAAAAAAAAAA : - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ? + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ; - assign IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414 = + assign IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442 = enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[584] : enqDst_1_0_rl[584] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[583:520] : enqDst_1_0_rl[583:520] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[519:518] : enqDst_1_0_rl[519:518] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[517] : enqDst_1_0_rl[517] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[516:1] : enqDst_1_0_rl[516:1] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1647 = + assign IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1675 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657, CAN_FIRE_RL_doEnq_1 ? 516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639, - x__h114170 } ; - assign IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1648 = + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667, + x__h116260 } ; + assign IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1676 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624, - IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1647 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253 = + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652, + IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1675 } ; + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1985 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2014 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd6) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd5) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd4) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[319:256], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd3) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd2) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_fetchingWay_330_THEN_mmioPlatf_ETC___d1356 = + assign IF_mmioPlatform_fetchingWay_358_THEN_mmioPlatf_ETC___d1384 = mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 ; - assign IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 ; + assign IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154 = (mmioPlatform_fromHostQ_empty || mmioPlatform_fromHostAddr[0]) ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124 = + assign IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152 = mmioPlatform_fromHostQ_empty ? 64'd0 : (mmioPlatform_fromHostAddr[0] ? mmioPlatform_fromHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005 = - ((mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + assign IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033 = + ((mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872 = + assign IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 8'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqBE[15:8] : mmioPlatform_reqBE[7:0]) ; - assign IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 = + assign IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 64'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqData[127:64] : mmioPlatform_reqData[63:0]) ; - assign IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021 = + assign IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q7 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q8 } ; - assign IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 = + assign IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067, + { IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095, 1'd0, - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1131 = + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101 } ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1159 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121, + { IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149, 1'd0, - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124, - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786 = + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154 } ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022 = + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949 = + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067 = + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? mmioPlatform_toHostQ_empty : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h71490 == 64'd0 : - x__h66321 == 64'd0) : + x__h73580 == 64'd0 : + x__h68411 == 64'd0) : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1138 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1166 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h71490 != 64'd0 : - x__h66321 != 64'd0) : + x__h73580 != 64'd0 : + x__h68411 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; - assign IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073 = + assign IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101 = (mmioPlatform_toHostQ_empty || mmioPlatform_toHostAddr[0]) ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071 = + assign IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099 = mmioPlatform_toHostQ_empty ? 64'd0 : (mmioPlatform_toHostAddr[0] ? mmioPlatform_toHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 = + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850 = + assign IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6080,85 +5767,82 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__258_ETC___d1334 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__286_ETC___d1362 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 = + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? - !mmio_axi4_adapter_master_xactor_clearing && - !mmio_axi4_adapter_master_xactor_shim_awff_rv[97] && - !mmio_axi4_adapter_master_xactor_shim_wff_rv[74] : + mmio_axi4_adapter_master_shim_wff$FULL_N && + (!whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + mmio_axi4_adapter_rg_wr_req_beat || + mmio_axi4_adapter_master_shim_awff$FULL_N) : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 = - mmio_axi4_adapter_soc_map$m_is_IO_addr ? - !mmio_axi4_adapter_master_xactor_clearing && - !mmio_axi4_adapter_master_xactor_shim_arff_rv[97] : - mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533 = + assign IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[583:520] : propDstData_1_0_rl[583:520] ; - assign IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538 = + assign IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[519:518] : propDstData_1_0_rl[519:518] ; - assign IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559 = + assign IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571 = + assign IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[583:520] : propDstData_1_1_rl[583:520] ; - assign IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576 = + assign IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[519:518] : propDstData_1_1_rl[519:518] ; - assign IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597 = + assign IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446 = + assign IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474 = !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383 = + assign IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679 = + assign IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707 = !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516 = + assign IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523 = + assign IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390 = + assign IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_rl_412_BIT_73_413_418_AND_SEL_ARR_ETC___d1506 = + assign NOT_enqDst_0_rl_440_BIT_73_441_446_AND_SEL_ARR_ETC___d1534 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 && - (SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 ? + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 && + (SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 ? !srcRR_0 : - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383) ; - assign NOT_enqDst_1_0_rl_607_BIT_584_608_613_AND_SEL__ETC___d1803 = + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411) ; + assign NOT_enqDst_1_0_rl_635_BIT_584_636_641_AND_SEL__ETC___d1831 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 && - (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 ? + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 && + (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 ? !srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 = + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2286 = - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2315 = + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2289 = - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2318 = + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1161 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1189 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6169,7 +5853,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1256 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1284 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6180,7 +5864,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1267 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1295 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6192,7 +5876,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1277 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1305 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6204,7 +5888,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1325 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1353 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6214,7 +5898,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1337 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1365 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6224,96 +5908,105 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 = + assign NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (!mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (!IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || !mmioPlatform_mtip_0) ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1499 = - { CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14, - x__h98832, - x__h98833 } ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1500 = - { CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16, - SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1499 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1715 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1740 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1757 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1774 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1740, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1757, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1791 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1792 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1715, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1774, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1791 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1797 = - { CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30, - !CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1792, - x__h125469 } ; - assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 || - (IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446 ? - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390 : - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383) ; - assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 || - (IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679 ? - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523 : - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516) ; - assign _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 = - { 64'd0, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4] } << - (mmio_axi4_adapter_read_req_addr[3] ? 32'd64 : 32'd0) ; - assign addr1__h88409 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign amo_req_data__h36993 = + assign SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1527 = + { CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + x__h100922, + x__h100923 } ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1528 = + { CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1527 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1743 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1768 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1785 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1802 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1768, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1785, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1819 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1820 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1743, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1802, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1819 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1825 = + { CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, + !CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1820, + x__h127559 } ; + assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 || + (IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474 ? + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418 : + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411) ; + assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 || + (IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707 ? + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551 : + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544) ; + assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat) ; + assign _theResult_____1_awsize_val__h17178 = + (x__h15205 + y__h15206 <= 5'd4) ? 3'b010 : 3'b011 ; + assign _theResult____h13554 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? + whichHalf___1__h15117 : + mmio_axi4_adapter_rg_wr_req_beat ; + assign addr1__h90499 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign amo_req_data__h39080 = (mmioPlatform_reqBE[3:0] == 4'd0 && mmioPlatform_reqBE[7:4] == 4'd0 && mmioPlatform_reqBE[11:8] == 4'd0 && @@ -6329,208 +6022,213 @@ module mkProc(CLK, ((mmioPlatform_reqBE[3:0] == 4'd0) ? mmioPlatform_reqData[63:32] : mmioPlatform_reqData[31:0]))) ; - assign b__h191029 = + assign b__h193221 = llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h4263 = + assign b__h2174 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554432 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556480 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_toHostAddr ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_fromHostAddr ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 ; + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ; + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ; - assign core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731 = + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ; + assign core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759 = core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497 ; - assign data__h138449 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525 ; + assign data__h140598 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[7:0] } ; - assign failed_testnum__h221515 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[7:0] } ; + assign failed_testnum__h223700 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h137882 = + assign line_addr__h140031 = { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h147990 = + assign line_addr__h150142 = { llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h191238 = { llc$to_mem_toM_first[68:11], 6'h0 } ; - assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37 = + assign line_addr__h193421 = { llc$to_mem_toM_first[68:11], 6'h0 } ; + assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34 = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35 = + assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2218 = + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2247 = llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || llc$RDY_to_mem_rsFromM_enq && llc_axi4_adapter_f_pending_reads$EMPTY_N) ; - assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36 = + assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 = - line_addr__h147990 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 = - line_addr__h137882 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33 = + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 = + line_addr__h150142 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 = + line_addr__h140031 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34 = + assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31 = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ; - assign lower_data__h42399 = - mmioPlatform_waitLowerMSIPCRs ? v__h42292 : 32'd0 ; - assign mmioPlatform_amoWaitWriteResp_271_OR_core_0_RD_ETC___d1274 = + assign lower_data__h44486 = + mmioPlatform_waitLowerMSIPCRs ? v__h44379 : 32'd0 ; + assign mem_req_rd_addr_arlen__h5411 = + (!whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? + 8'd1 : + 8'd0 ; + assign mmioPlatform_amoWaitWriteResp_299_OR_core_0_RD_ETC___d1302 = mmioPlatform_amoWaitWriteResp || core_0$RDY_mmioToPlatform_pRs_enq && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) ; - assign mmioPlatform_cycle_57_ULT_99___d458 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 = + assign mmioPlatform_cycle_85_ULT_99___d486 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h57710 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 = - mmioPlatform_mtimecmp_0 <= newData__h51199 ; - assign mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 = + assign mmioPlatform_mtime__h59797 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 = + mmioPlatform_mtimecmp_0 <= newData__h53286 ; + assign mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd0 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd1 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd2 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd3 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd4 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd5 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd6 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd7 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd8 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -6544,162 +6242,215 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_first[148:145] != 4'd6 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd7 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd8 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492 ; - assign mmioPlatform_reqAmofunc__h86179 = mmioPlatform_reqAmofunc ; - assign mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877 = + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520 ; + assign mmioPlatform_reqAmofunc__h88269 = mmioPlatform_reqAmofunc ; + assign mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905 = { mmioPlatform_reqFunc[3:0], - (IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0]) ? + (IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0]) ? 2'd1 : 2'd2, 2'd0 } ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (!mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (!IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || !mmioPlatform_mtip_0) ; - assign mmio_axi4_adapter_f_rsps_to_core_first__258_BI_ETC___d1359 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) && + mmio_axi4_adapter_cfg_verbosity != 4'd0 ; + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) && + mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15 ; + assign mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8 = + mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && + (mmio_axi4_adapter_soc_map$m_is_IO_addr ? + mmio_axi4_adapter_master_shim_arff$FULL_N : + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign mmio_axi4_adapter_f_rsps_to_core_first__286_BI_ETC___d1387 = { mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmioPlatform_fetchingWay, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - IF_mmioPlatform_fetchingWay_330_THEN_mmioPlatf_ETC___d1356 : + IF_mmioPlatform_fetchingWay_358_THEN_mmioPlatf_ETC___d1384 : mmioPlatform_fetchedInsts_0 } ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13 = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[96:0] ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11 = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[96:0] ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12 = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign newData__h43098 = + assign mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 = + mmio_axi4_adapter_read_req_addr[3] + + mmio_axi4_adapter_rg_rd_rsp_beat ; + assign mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 = + { mmio_axi4_adapter_rspData[128], + mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 ? + { mmio_axi4_adapter_master_shim_rff$D_OUT[67:4], + mmio_axi4_adapter_rspData[63:0] } : + { mmio_axi4_adapter_rspData[127:64], + mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; + assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 = + mmio_axi4_adapter_soc_map$m_is_IO_addr && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) ; + assign newData__h45185 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d887[63:0] : - x__h46411 ; - assign newData__h51199 = + amoExec___d915[63:0] : + x__h48498 ; + assign newData__h53286 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d973[63:0] : - x__h54489 ; - assign upper_data__h42400 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h42255 ; - assign v__h42255 = mmioPlatform_waitUpperMSIPCRs ? v__h42292 : 32'd0 ; - assign v__h42292 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign v_awaddr__h212729 = { llc$to_mem_toM_first[643:586], 6'h0 } ; - assign v_awsize_val__h15192 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:133] == 4'd0 || - mmio_axi4_adapter_f_reqs_from_core$D_OUT[132:129] == 4'd0) ? - 3'b010 : - 3'b011 ; - assign value__h59417 = mmioPlatform_mtimecmp_0 ; - assign x__h114170 = - !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645 ; - assign x__h120734 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 ? - srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679 ; - assign x__h46411 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_mtimecmp_0[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_mtimecmp_0[7:0] } ; - assign x__h54489 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_mtime[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_mtime[7:0] } ; - assign x__h62366 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - 8'd0 } ; - assign x__h66321 = - (mmioPlatform_reqFunc[5:4] != 2'd0 && - mmioPlatform_reqFunc[5:4] != 2'd1 && - mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1096[63:0] : - x__h68995 ; - assign x__h68995 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1112, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_fromHostQ_data_0[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_fromHostQ_data_0[7:0] } ; - assign x__h71490 = - (mmioPlatform_reqFunc[5:4] != 2'd0 && - mmioPlatform_reqFunc[5:4] != 2'd1 && - mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1043[63:0] : - x__h62366 ; - assign x__h77037 = mmioPlatform_fromHostQ_data_0 ; - assign x__h98632 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 ? + amoExec___d1001[63:0] : + x__h56576 ; + assign upper_data__h44487 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44342 ; + assign v__h44342 = mmioPlatform_waitUpperMSIPCRs ? v__h44379 : 32'd0 ; + assign v__h44379 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign v_awaddr__h214914 = { llc$to_mem_toM_first[643:586], 6'h0 } ; + assign value__h61504 = mmioPlatform_mtimecmp_0 ; + assign whichHalf___1__h15117 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; + assign x__h100722 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 ? srcRR_0 : - IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446 ; - assign x_data__h39934 = { 31'd0, mmioPlatform_reqData[0] } ; + IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474 ; + assign x__h10759 = mmio_axi4_adapter_rg_rd_rsp_beat + 1'd1 ; + assign x__h116260 = + !CAN_FIRE_RL_doEnq_1 && + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673 ; + assign x__h122824 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 ? + srcRR_1_0 : + IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707 ; + assign x__h15205 = x__h15217 + y__h15218 ; + assign x__h15217 = x__h15229 + y__h15230 ; + assign x__h15229 = x__h15241 + y__h15242 ; + assign x__h15241 = x__h15253 + y__h15254 ; + assign x__h15253 = x__h15265 + y__h15266 ; + assign x__h15265 = x__h15277 + y__h15278 ; + assign x__h15277 = x__h15289 + y__h15290 ; + assign x__h15289 = x__h15301 + y__h15302 ; + assign x__h15301 = x__h15313 + y__h15314 ; + assign x__h15313 = x__h15325 + y__h15326 ; + assign x__h15325 = x__h15337 + y__h15338 ; + assign x__h15337 = x__h15349 + y__h15350 ; + assign x__h15349 = x__h15361 + y__h15362 ; + assign x__h15361 = x__h15373 + y__h15374 ; + assign x__h15373 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144] } ; + assign x__h17973 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; + assign x__h48498 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_mtimecmp_0[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_mtimecmp_0[7:0] } ; + assign x__h56576 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_mtime[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_mtime[7:0] } ; + assign x__h64456 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + 8'd0 } ; + assign x__h68411 = + (mmioPlatform_reqFunc[5:4] != 2'd0 && + mmioPlatform_reqFunc[5:4] != 2'd1 && + mmioPlatform_reqFunc[5:4] != 2'd2) ? + amoExec___d1124[63:0] : + x__h71085 ; + assign x__h71085 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1140, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_fromHostQ_data_0[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_fromHostQ_data_0[7:0] } ; + assign x__h73580 = + (mmioPlatform_reqFunc[5:4] != 2'd0 && + mmioPlatform_reqFunc[5:4] != 2'd1 && + mmioPlatform_reqFunc[5:4] != 2'd2) ? + amoExec___d1071[63:0] : + x__h64456 ; + assign x__h79127 = mmioPlatform_fromHostQ_data_0 ; + assign x_data__h42021 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h15206 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[129] } ; + assign y__h15218 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[130] } ; + assign y__h15230 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[131] } ; + assign y__h15242 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[132] } ; + assign y__h15254 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[133] } ; + assign y__h15266 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[134] } ; + assign y__h15278 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[135] } ; + assign y__h15290 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[136] } ; + assign y__h15302 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[137] } ; + assign y__h15314 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[138] } ; + assign y__h15326 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[139] } ; + assign y__h15338 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[140] } ; + assign y__h15350 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141] } ; + assign y__h15362 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[142] } ; + assign y__h15374 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[143] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h185995 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h185995 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h185995 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h185995 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h185995 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h185995 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h185995 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h185995 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h188147 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h188147 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h188147 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h188147 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h188147 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h188147 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h188147 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h188147 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) @@ -6754,49 +6505,71 @@ module mkProc(CLK, begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) 2'd0: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1; 2'd1: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2; 2'd2: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3; 2'd3: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: v_wstrb__h213141 = llc$to_mem_toM_first[523:516]; - 3'd1: v_wstrb__h213141 = llc$to_mem_toM_first[531:524]; - 3'd2: v_wstrb__h213141 = llc$to_mem_toM_first[539:532]; - 3'd3: v_wstrb__h213141 = llc$to_mem_toM_first[547:540]; - 3'd4: v_wstrb__h213141 = llc$to_mem_toM_first[555:548]; - 3'd5: v_wstrb__h213141 = llc$to_mem_toM_first[563:556]; - 3'd6: v_wstrb__h213141 = llc$to_mem_toM_first[571:564]; - 3'd7: v_wstrb__h213141 = llc$to_mem_toM_first[579:572]; + 3'd0: v_wstrb__h215326 = llc$to_mem_toM_first[523:516]; + 3'd1: v_wstrb__h215326 = llc$to_mem_toM_first[531:524]; + 3'd2: v_wstrb__h215326 = llc$to_mem_toM_first[539:532]; + 3'd3: v_wstrb__h215326 = llc$to_mem_toM_first[547:540]; + 3'd4: v_wstrb__h215326 = llc$to_mem_toM_first[555:548]; + 3'd5: v_wstrb__h215326 = llc$to_mem_toM_first[563:556]; + 3'd6: v_wstrb__h215326 = llc$to_mem_toM_first[571:564]; + 3'd7: v_wstrb__h215326 = llc$to_mem_toM_first[579:572]; + endcase + end + always@(_theResult____h13554 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) + begin + case (_theResult____h13554) + 1'd0: + wflit_wdata__h18041 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]; + 1'd1: + wflit_wdata__h18041 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64]; + endcase + end + always@(_theResult____h13554 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) + begin + case (_theResult____h13554) + 1'd0: + wflit_wstrb__h18042 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129]; + 1'd1: + wflit_wstrb__h18042 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) - 2'd0: v_wuser__h213143 = llc$to_mem_toM_first[512]; - 2'd1: v_wuser__h213143 = llc$to_mem_toM_first[513]; - 2'd2: v_wuser__h213143 = llc$to_mem_toM_first[514]; - 2'd3: v_wuser__h213143 = llc$to_mem_toM_first[515]; + 2'd0: v_wuser__h215328 = llc$to_mem_toM_first[512]; + 2'd1: v_wuser__h215328 = llc$to_mem_toM_first[513]; + 2'd2: v_wuser__h215328 = llc$to_mem_toM_first[514]; + 2'd3: v_wuser__h215328 = llc$to_mem_toM_first[515]; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811 = + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811 = + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6804,21 +6577,21 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 2'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 2'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; 2'd2: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64]; 2'd3: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929 or + IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6826,11 +6599,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = - IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929; + IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005 or + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6838,452 +6611,452 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005; + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033; endcase end always@(srcRR_0 or - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383 or - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390) + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411 or + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418) begin case (srcRR_0) 1'd0: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 = - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 = + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411; 1'd1: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 = - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 = + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418; endcase end always@(srcRR_1_0 or - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516 or - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523) + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544 or + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551) begin case (srcRR_1_0) 1'd0: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 = - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 = + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544; 1'd1: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 = - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 = + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - x__h98832 = + x__h100922 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]; 1'd1: - x__h98832 = + x__h100922 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - x__h98833 = + x__h100923 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]; 1'd1: - x__h98833 = + x__h100923 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]; endcase end - always@(x__h120734 or - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559 or - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597) + always@(x__h122824 or + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587 or + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625) begin - case (x__h120734) + case (x__h122824) 1'd0: - x__h125469 = - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559; + x__h127559 = + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587; 1'd1: - x__h125469 = - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597; + x__h127559 = + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516] : propDstData_1_0_rl[516]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516] : propDstData_1_1_rl[516]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515] : propDstData_1_0_rl[515]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515] : propDstData_1_1_rl[515]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[514] : propDstData_1_0_rl[514]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[514] : propDstData_1_1_rl[514]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513]; endcase end - always@(x__h120734 or - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538 or - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576) + always@(x__h122824 or + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566 or + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30 = - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566; 1'd1: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30 = - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[517] : !propDstData_1_0_rl[517]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[517] : !propDstData_1_1_rl[517]; endcase end - always@(x__h120734 or - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533 or - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571) + always@(x__h122824 or + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561 or + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32 = - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561; 1'd1: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32 = - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599; endcase end always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or @@ -7291,28 +7064,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7320,14 +7093,14 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32]) - 3'd0: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7355,7 +7128,6 @@ module mkProc(CLK, 74'h0AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY 75'h2AAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_mem_server_axi4_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY @@ -7400,21 +7172,12 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY - 1'd0; - mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY - 7'd42; - mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY - 73'h0AAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY - 75'h2AAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmio_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmio_axi4_adapter_rspData <= `BSV_ASSIGNMENT_DELAY 129'd0; propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7460,9 +7223,6 @@ module mkProc(CLK, if (llc_axi4_adapter_master_xactor_shim_wff_rv$EN) llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN; - if (llc_axi4_adapter_rg_rd_req_beat$EN) - llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_rg_rd_req_beat$D_IN; if (llc_axi4_adapter_rg_rd_rsp_beat$EN) llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_rd_rsp_beat$D_IN; @@ -7565,24 +7325,15 @@ module mkProc(CLK, if (mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN) mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; - if (mmio_axi4_adapter_master_xactor_clearing$EN) - mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_clearing$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_arff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_awff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_bff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_rff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_wff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; + if (mmio_axi4_adapter_rg_rd_rsp_beat$EN) + mmio_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rg_rd_rsp_beat$D_IN; + if (mmio_axi4_adapter_rg_wr_req_beat$EN) + mmio_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rg_wr_req_beat$D_IN; + if (mmio_axi4_adapter_rspData$EN) + mmio_axi4_adapter_rspData <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rspData$D_IN; if (propDstData_0_rl$EN) propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN; if (propDstData_1_0_rl$EN) @@ -7669,7 +7420,6 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_rg_cline = 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_rg_rd_req_beat = 3'h2; llc_axi4_adapter_rg_rd_rsp_beat = 3'h2; llc_axi4_adapter_rg_wr_req_beat = 3'h2; llc_mem_server_axi4_slave_xactor_clearing = 1'h0; @@ -7723,15 +7473,10 @@ module mkProc(CLK, mmioPlatform_waitUpperMSIPCRs = 1'h0; mmio_axi4_adapter_cfg_verbosity = 4'hA; mmio_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA; - mmio_axi4_adapter_master_xactor_clearing = 1'h0; - mmio_axi4_adapter_master_xactor_shim_arff_rv = - 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_awff_rv = - 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_bff_rv = 7'h2A; - mmio_axi4_adapter_master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; mmio_axi4_adapter_read_req_addr = 64'hAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_rg_rd_rsp_beat = 1'h0; + mmio_axi4_adapter_rg_wr_req_beat = 1'h0; + mmio_axi4_adapter_rspData = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl = 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7757,14 +7502,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h221935 = $stime; + v__h224105 = $stime; #0; end - v__h221929 = v__h221935 / 32'd10; + v__h224099 = v__h224105 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h221929, + v__h224099, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -7774,14 +7519,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h221472 = $stime; + v__h223657 = $stime; #0; end - v__h221466 = v__h221472 / 32'd10; + v__h223651 = v__h223657 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h221466, + v__h223651, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7791,22 +7536,280 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h221515); + $display("FAIL %0d", failed_testnum__h223700); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h11342 = $stime; + v__h9702 = $stime; #0; end - v__h11336 = v__h11342 / 32'd10; + v__h9696 = v__h9702 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_handle_read_rsps ", v__h9696); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[71:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd1 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + begin + v__h9897 = $stime; + #0; + end + v__h9891 = v__h9897 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $display("%0d: %m.rl_handle_read_rsp: fabric response error", + v__h9891); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[71:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd1 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + !mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" Response MMIO to core: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("MMIODataPRs { ", "valid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_rspData[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_rspData[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h11336); + begin + v__h11307 = $stime; + #0; + end + v__h11301 = v__h11307 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%d: %m.rl_handle_write_req: St request:", v__h11301); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8128,37 +8131,259 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) begin - v__h15880 = $stime; + v__h17239 = $stime; #0; end - v__h15874 = v__h15880 / 32'd10; + v__h17233 = v__h17239 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h15874); + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $display("%d: %m.rl_handle_write_req: sent aw flit:", v__h17233); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", mem_req_rd_addr_arlen__h5411); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", _theResult_____1_awsize_val__h17178, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) + begin + v__h17410 = $stime; + #0; + end + v__h17404 = v__h17410 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) + $display("%0d: ERROR: CreditCounter: overflow", v__h17404); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + begin + v__h18103 = $stime; + #0; + end + v__h18097 = v__h18103 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%d: %m.rl_handle_write_req: sent w flit:", v__h18097); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", wflit_wdata__h18041); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", wflit_wstrb__h18042); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + !mmio_axi4_adapter_rg_wr_req_beat) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat)) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("first: %d, last: %d, whichHalf: %d", + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat, + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat, + _theResult____h13554, + "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h16023 = $stime; + v__h18189 = $stime; #0; end - v__h16017 = v__h16023 / 32'd10; + v__h18183 = v__h18189 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h16017); + v__h18183); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8552,14 +8777,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4363 = $stime; + v__h2280 = $stime; #0; end - v__h4357 = v__h4363 / 32'd10; + v__h2274 = v__h2280 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h4357); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2274); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8912,7 +9137,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 8'd0); + $write("'h%h", mem_req_rd_addr_arlen__h5411); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9008,16 +9233,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h7984 = $stime; + v__h7388 = $stime; #0; end - v__h7978 = v__h7984 / 32'd10; + v__h7382 = v__h7388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h7978); + v__h7382); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9408,16 +9633,137 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h19409 = $stime; + v__h20501 = $stime; #0; end - v__h19403 = v__h19409 / 32'd10; + v__h20495 = v__h20501 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_discard_write_rsp", v__h20495); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_bff$D_OUT[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd1 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + begin + v__h21031 = $stime; + #0; + end + v__h21025 = v__h21031 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", + v__h21025); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_bff$D_OUT[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd1 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) + begin + v__h21496 = $stime; + #0; + end + v__h21490 = v__h21496 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h19403); + v__h21490); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9707,572 +10053,130 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - begin - v__h18412 = $stime; - #0; - end - v__h18406 = v__h18412 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h18406); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_BFlit { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0) - $write("OKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - begin - v__h18942 = $stime; - #0; - end - v__h18936 = v__h18942 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h18936); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("AXI4_BFlit { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - begin - v__h10403 = $stime; - #0; - end - v__h10397 = v__h10403 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h10397); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_RFlit { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0) - $write("OKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - begin - v__h10598 = $stime; - #0; - end - v__h10592 = v__h10598 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h10592); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("AXI4_RFlit { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" Response MMIO to core: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("MMIODataPRs { ", "valid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("TaggedData { ", "tag: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write("[Platform - SelectReq] timer interrupt", ", mtime %x", mmioPlatform_mtime, ", mtimcmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(", old mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(", new interrupts "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("[Platform - SelectReq] core %d, req ", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write("tagged Inst ", "'h%h", core_0$mmioToPlatform_cRq_first[145]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write("tagged Ld ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write("tagged St ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -10281,542 +10185,542 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579) $write("Swap"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585) $write("Add"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591) $write("Xor"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597) $write("And"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603) $write("Or"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609) $write("Min"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615) $write("Max"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621) $write("Minu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627) $write("Maxu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649) $write("None"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("TaggedData { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[128]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && !core_0$mmioToPlatform_cRq_first[128]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" req type "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755) $write("tagged MSIP ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && - core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731) + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && + core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759) $write("tagged MTimeCmp ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736) + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764) $write("tagged MTime ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742) + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770) $write("tagged ToHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748) + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776) $write("tagged FromHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755) + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783) $write("tagged MMIO_Fabric_Adapter ", "'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) @@ -10879,8 +10783,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h42399, - upper_data__h42400); + lower_data__h44486, + upper_data__h44487); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -10892,62 +10796,62 @@ module mkProc(CLK, mmioPlatform_mtimecmp_0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write("[Platform - process mtimecmp] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(", mtime %x", mmioPlatform_mtime, ", old mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h43098, "\n"); + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) + $write(", new mtimecmp[%d] %x", 1'd0, newData__h45185, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -10992,61 +10896,61 @@ module mkProc(CLK, mmioPlatform_mtime); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write("[Platform - process mtime] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) - $write(", new mtime %x", newData__h51199, ", mtimecmp "); + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) + $write(", new mtime %x", newData__h53286, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeDone) @@ -11103,7 +11007,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11129,13 +11033,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11172,12 +11076,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1138) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1166) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11203,13 +11107,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124, + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11704,7 +11608,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", addr1__h88409); + $write("'h%h", addr1__h90499); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -11789,76 +11693,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $display(" fetchingWay %0d instSel %0d inst 0x%0h", mmioPlatform_fetchingWay, mmioPlatform_instSel, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351); + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp: final resp to core:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && @@ -11907,35 +11811,35 @@ module mkProc(CLK, !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h199123 = $stime; + v__h201308 = $stime; #0; end - v__h199117 = v__h199123 / 32'd10; + v__h201302 = v__h201308 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h199117); + v__h201302); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -13392,15 +13296,15 @@ module mkProc(CLK, llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h212832 = $stime; + v__h215017 = $stime; #0; end - v__h212826 = v__h212832 / 32'd10; + v__h215011 = v__h215017 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h212826); + $display("%0d: ERROR: CreditCounter: overflow", v__h215011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && @@ -13408,209 +13312,193 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h191102 = $stime; + v__h193285 = $stime; #0; end - v__h191096 = v__h191102 / 32'd10; + v__h193279 = v__h193285 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) - $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h191096, - llc_axi4_adapter_rg_rd_req_beat); + llc_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory", + v__h193279); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("LdMemRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", llc$to_mem_toM_first[68:5]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0 && llc$to_mem_toM_first[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0 && !llc$to_mem_toM_first[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", llc$to_mem_toM_first[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) - $write("'h%h", line_addr__h191238); + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) + $write("'h%h", line_addr__h193421); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) begin - v__h220458 = $stime; + v__h222643 = $stime; #0; end - v__h220452 = v__h220458 / 32'd10; + v__h222637 = v__h222643 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h220452); + v__h222637); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) @@ -13661,69 +13549,69 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) begin - v__h191691 = $stime; + v__h193874 = $stime; #0; end - v__h191685 = v__h191691 / 32'd10; + v__h193868 = v__h193874 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h191685, + v__h193868, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13732,45 +13620,45 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) begin - v__h191877 = $stime; + v__h194060 = $stime; #0; end - v__h191871 = v__h191877 / 32'd10; + v__h194054 = v__h194060 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h191871); + v__h194054); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) @@ -13850,27 +13738,27 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v index 176b18d..93125a7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:03 BST 2020 +// On Wed Jun 24 20:28:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRas.v b/src_SSITH_P3/Verilog_RTL/mkRas.v index fd5a0ae..76c10b4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:08 BST 2020 +// On Wed Jun 24 20:29:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v index 07ad852..7aa37d4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:36:35 BST 2020 +// On Wed Jun 24 20:25:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v index e75ac21..7fa8e2d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:44 BST 2020 +// On Wed Jun 24 20:28:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v index e07452b..b46fbd0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:26 BST 2020 +// On Wed Jun 24 20:34:41 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v index bd6d4ae..2b2e2fc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:58 BST 2020 +// On Wed Jun 24 20:29:02 BST 2020 // // // Ports: @@ -8963,71 +8963,6 @@ module mkReservationStationFpuMulDiv(CLK, m_data_15[1]; endcase end - always@(idx__h87141 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h87141) - 4'd0: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_0[0]; - 4'd1: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_1[0]; - 4'd2: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_2[0]; - 4'd3: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_3[0]; - 4'd4: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_4[0]; - 4'd5: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_5[0]; - 4'd6: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_6[0]; - 4'd7: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_7[0]; - 4'd8: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_8[0]; - 4'd9: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_9[0]; - 4'd10: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_10[0]; - 4'd11: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_11[0]; - 4'd12: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_12[0]; - 4'd13: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_13[0]; - 4'd14: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_14[0]; - 4'd15: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_15[0]; - endcase - end always@(idx__h87141 or m_data_0 or m_data_1 or @@ -9093,6 +9028,71 @@ module mkReservationStationFpuMulDiv(CLK, m_data_15[2]; endcase end + always@(idx__h87141 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h87141) + 4'd0: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_0[0]; + 4'd1: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_1[0]; + 4'd2: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_2[0]; + 4'd3: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_3[0]; + 4'd4: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_4[0]; + 4'd5: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_5[0]; + 4'd6: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_6[0]; + 4'd7: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_7[0]; + 4'd8: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_8[0]; + 4'd9: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_9[0]; + 4'd10: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_10[0]; + 4'd11: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_11[0]; + 4'd12: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_12[0]; + 4'd13: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_13[0]; + 4'd14: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_14[0]; + 4'd15: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_15[0]; + endcase + end always@(idx__h87141 or m_data_0 or m_data_1 or diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v index b5be7f3..29350a6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:53 BST 2020 +// On Wed Jun 24 20:28:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v index 3b81235..cee4a98 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:13 BST 2020 +// On Wed Jun 24 20:28:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v index 131067b..0a7f7de 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:41:26 BST 2020 +// On Wed Jun 24 20:30:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v index bcc2e21..6d17c92 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:41:19 BST 2020 +// On Wed Jun 24 20:30:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v index 2095ab1..95ecaa4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:51 BST 2020 +// On Wed Jun 24 20:33:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v index 1d9b270..b60a26c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v +++ b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:04 BST 2020 +// On Wed Jun 24 20:24:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v index 7eb938c..c66410d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:38:54 BST 2020 +// On Wed Jun 24 20:27:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v index 84b7b29..f3adfdb 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:51 BST 2020 +// On Wed Jun 24 20:29:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v index 9a91803..7159584 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:38 BST 2020 +// On Wed Jun 24 20:24:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v index 4706f80..449811b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:36:07 BST 2020 +// On Wed Jun 24 20:25:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v index 707f069..3570f20 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:46 BST 2020 +// On Wed Jun 24 20:31:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v b/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v index 60af2a2..1a41439 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:46 BST 2020 +// On Wed Jun 24 20:31:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTagController.v b/src_SSITH_P3/Verilog_RTL/mkTagController.v index 7e42390..8ec3206 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTagController.v +++ b/src_SSITH_P3/Verilog_RTL/mkTagController.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:52 BST 2020 +// On Wed Jun 24 20:34:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v index 7b93571..1bf9ae5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPred.v b/src_SSITH_P3/Verilog_RTL/mkTourPred.v index 29fc3bc..4b153c6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v index 3d77cfe..d8f1d08 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:59 BST 2020 +// On Wed Jun 24 20:34:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v index 012d58a..6ccee51 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v index df685fc..cae3995 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v index 2699fb2..bdc6945 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v index 11c4ad2..c118fe7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v index 53f40d4..b2c85cf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v index a9de33f..3b0d41f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v index 3dea0ff..c8f3301 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v index b61d7ea..2c53437 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v index 50dce32..89c5e28 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_alu.v b/src_SSITH_P3/Verilog_RTL/module_alu.v index 0830d8e..030a399 100644 --- a/src_SSITH_P3/Verilog_RTL/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:23 BST 2020 +// On Wed Jun 24 20:24:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_aluBr.v b/src_SSITH_P3/Verilog_RTL/module_aluBr.v index f47d598..d911b0a 100644 --- a/src_SSITH_P3/Verilog_RTL/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_amoExec.v b/src_SSITH_P3/Verilog_RTL/module_amoExec.v index f3d83fd..5d8e2b6 100644 --- a/src_SSITH_P3/Verilog_RTL/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:01 BST 2020 +// On Wed Jun 24 20:24:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_basicExec.v b/src_SSITH_P3/Verilog_RTL/module_basicExec.v index 95627f3..192297d 100644 --- a/src_SSITH_P3/Verilog_RTL/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v index c31d7fe..fda6208 100644 --- a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capChecks.v b/src_SSITH_P3/Verilog_RTL/module_capChecks.v index 3e899d6..46aa618 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capChecks.v +++ b/src_SSITH_P3/Verilog_RTL/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:23 BST 2020 +// On Wed Jun 24 20:24:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capInspect.v b/src_SSITH_P3/Verilog_RTL/module_capInspect.v index 93414fd..0500e55 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capInspect.v +++ b/src_SSITH_P3/Verilog_RTL/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capModify.v b/src_SSITH_P3/Verilog_RTL/module_capModify.v index c120409..3413ac0 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capModify.v +++ b/src_SSITH_P3/Verilog_RTL/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:25 BST 2020 +// On Wed Jun 24 20:24:24 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_checkForException.v b/src_SSITH_P3/Verilog_RTL/module_checkForException.v index b1ccbbb..1213985 100644 --- a/src_SSITH_P3/Verilog_RTL/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:27 BST 2020 +// On Wed Jun 24 20:24:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_decode.v b/src_SSITH_P3/Verilog_RTL/module_decode.v index 81b141c..486ee3c 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:04 BST 2020 +// On Wed Jun 24 20:29:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v index d42b9f5..fca467c 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:01 BST 2020 +// On Wed Jun 24 20:29:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v index e851af6..a66d32f 100644 --- a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:58 BST 2020 +// On Wed Jun 24 20:33:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v b/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v index 501bab3..4c58c0d 100644 --- a/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:23 BST 2020 +// On Wed Jun 24 20:24:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v b/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v index beaae24..e6585e1 100644 --- a/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v +++ b/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:24 BST 2020 +// On Wed Jun 24 20:24:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v b/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v index a44941d..4f2e316 100644 --- a/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v +++ b/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:25 BST 2020 +// On Wed Jun 24 20:24:24 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v index c573753..e55baef 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:32:01 BST 2020 +// On Wed Jun 24 20:21:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v index 862456d..ea612b2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:32:02 BST 2020 +// On Wed Jun 24 20:21:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v index efa8cf9..8431256 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:32:02 BST 2020 +// On Wed Jun 24 20:21:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkBht.v b/src_SSITH_P3/Verilog_RTL_sim/mkBht.v index 05766f7..c48e2be 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:54 BST 2020 +// On Wed Jun 24 20:19:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index 049c09c..9f32205 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:33:05 BST 2020 +// On Wed Jun 24 20:22:07 BST 2020 // // // Ports: @@ -3747,17 +3747,17 @@ module mkCore(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h215806; - reg [63 : 0] v__h218142; - reg [63 : 0] v__h275333; - reg [63 : 0] v__h351091; - reg [63 : 0] v__h427707; + reg [63 : 0] v__h215805; + reg [63 : 0] v__h218141; + reg [63 : 0] v__h275330; + reg [63 : 0] v__h351088; + reg [63 : 0] v__h427704; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5493; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4893; - reg [65 : 0] thin_address__h863688, thin_address__h904584; + reg [65 : 0] thin_address__h863685, thin_address__h904580; reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q364, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q290, @@ -3796,33 +3796,33 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2242, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2154, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2158, - addr__h509900, - addr__h850180, - addr__h893851, - data_out__h1026352, - trap_val__h1005091, - x__h267596; + addr__h509897, + addr__h850177, + addr__h893847, + data_out__h1026346, + trap_val__h1005086, + x__h267593; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32, - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q232, - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q233, - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q234, - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q235, - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q236, - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q237, - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q226, - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q227, - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q228, - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q229, - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q230, - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q231, - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q216, - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q217, - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q218, - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q219, - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q220, - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q221, + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q232, + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q233, + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q234, + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q235, + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q236, + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q237, + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q226, + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q227, + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q228, + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q229, + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q230, + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q231, + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q216, + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q217, + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q218, + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q219, + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q220, + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q221, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13358, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13385, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13404, @@ -3836,7 +3836,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17273; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_31_TO_0_ETC___d2046, - x__h267751; + x__h267748; reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q347, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341, @@ -3847,54 +3847,54 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363, IF_fetchStage_pipelines_0_first__0337_BITS_267_ETC___d20463, IF_fetchStage_pipelines_1_first__0346_BITS_267_ETC___d21424; - reg [22 : 0] CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q65, - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q66, - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q96, - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q97, - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q94, - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q95, - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q98, - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q99, - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q100, - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q101, - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q131, - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q132, - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q61, - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q62, - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q129, - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q130, - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q59, - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q60, - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q133, - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q134, - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q63, - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q64, - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q135, - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q136, - _theResult___fst_sfd__h580788, - _theResult___fst_sfd__h589511, - _theResult___fst_sfd__h598093, - _theResult___fst_sfd__h607277, - _theResult___fst_sfd__h615913, - _theResult___fst_sfd__h626539, - _theResult___fst_sfd__h635260, - _theResult___fst_sfd__h643842, - _theResult___fst_sfd__h653026, - _theResult___fst_sfd__h661662, - _theResult___fst_sfd__h672286, - _theResult___fst_sfd__h681007, - _theResult___fst_sfd__h689589, - _theResult___fst_sfd__h698773, - _theResult___fst_sfd__h707409; - reg [17 : 0] thin_otype__h863693, thin_otype__h904589; + reg [22 : 0] CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q65, + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q66, + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q96, + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q97, + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q94, + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q95, + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q98, + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q99, + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q100, + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q101, + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q131, + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q132, + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q61, + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q62, + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q129, + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q130, + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q59, + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q60, + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q133, + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q134, + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q63, + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q64, + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q135, + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q136, + _theResult___fst_sfd__h580785, + _theResult___fst_sfd__h589508, + _theResult___fst_sfd__h598090, + _theResult___fst_sfd__h607274, + _theResult___fst_sfd__h615910, + _theResult___fst_sfd__h626536, + _theResult___fst_sfd__h635257, + _theResult___fst_sfd__h643839, + _theResult___fst_sfd__h653023, + _theResult___fst_sfd__h661659, + _theResult___fst_sfd__h672283, + _theResult___fst_sfd__h681004, + _theResult___fst_sfd__h689586, + _theResult___fst_sfd__h698770, + _theResult___fst_sfd__h707406; + reg [17 : 0] thin_otype__h863690, thin_otype__h904585; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1889, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_15_TO_0_ETC___d2058; - reg [13 : 0] thin_addrBits__h863689, - thin_addrBits__h904585, - thin_bounds_baseBits__h865687, - thin_bounds_baseBits__h905991, - thin_bounds_topBits__h865686, - thin_bounds_topBits__h905990; + reg [13 : 0] thin_addrBits__h863686, + thin_addrBits__h904581, + thin_bounds_baseBits__h865684, + thin_bounds_baseBits__h905987, + thin_bounds_topBits__h865683, + thin_bounds_topBits__h905986; reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q338, CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q334, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q324; @@ -3917,24 +3917,24 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255, CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263, - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q171, - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q172, - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q200, - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q201, - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q202, - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q203, - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q154, - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q155, - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q222, - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q223, - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q224, - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q225, - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q194, - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q195, - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q196, - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q197, - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q198, - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q199, + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q171, + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q172, + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q200, + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q201, + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q202, + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q203, + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q154, + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q155, + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q222, + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q223, + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q224, + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q225, + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q194, + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q195, + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q196, + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q197, + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q198, + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q199, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13258, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13301, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13332, @@ -3944,47 +3944,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14743, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14781, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14812; - reg [7 : 0] CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q57, - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q58, - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q81, - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q82, - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q79, - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q80, - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q87, - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q88, - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q92, - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q93, - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q116, - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q117, - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q46, - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q47, - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q114, - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q115, - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q44, - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q45, - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q122, - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q123, - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q52, - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q53, - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q127, - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q128, + reg [7 : 0] CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q57, + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q58, + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q81, + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q82, + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q79, + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q80, + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q87, + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q88, + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q92, + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q93, + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q116, + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q117, + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q46, + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q47, + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q114, + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q115, + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q44, + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q45, + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q122, + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q123, + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q52, + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q53, + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q127, + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q128, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1911, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_7_TO_0__ETC___d2079, - _theResult___fst_exp__h580787, - _theResult___fst_exp__h589510, - _theResult___fst_exp__h598092, - _theResult___fst_exp__h607276, - _theResult___fst_exp__h615912, - _theResult___fst_exp__h626538, - _theResult___fst_exp__h635259, - _theResult___fst_exp__h643841, - _theResult___fst_exp__h653025, - _theResult___fst_exp__h661661, - _theResult___fst_exp__h672285, - _theResult___fst_exp__h681006, - _theResult___fst_exp__h689588, - _theResult___fst_exp__h698772, - _theResult___fst_exp__h707408; + _theResult___fst_exp__h580784, + _theResult___fst_exp__h589507, + _theResult___fst_exp__h598089, + _theResult___fst_exp__h607273, + _theResult___fst_exp__h615909, + _theResult___fst_exp__h626535, + _theResult___fst_exp__h635256, + _theResult___fst_exp__h643838, + _theResult___fst_exp__h653022, + _theResult___fst_exp__h661658, + _theResult___fst_exp__h672282, + _theResult___fst_exp__h681003, + _theResult___fst_exp__h689585, + _theResult___fst_exp__h698769, + _theResult___fst_exp__h707405; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q339, CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q330, @@ -4013,10 +4013,10 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_95_TO_3227_BIT_ETC__q329, IF_fetchStage_pipelines_0_first__0337_BITS_264_ETC___d22134, IF_fetchStage_pipelines_1_first__0346_BITS_264_ETC___d22315, - cause_code__h1003524, - i__h1003540, - t__h215234, - t__h217587; + cause_code__h1003519, + i__h1003535, + t__h215233, + t__h217586; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__843_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9503_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q245, @@ -4042,9 +4042,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0346_BITS_235_ETC___d21450, IF_fetchStage_pipelines_1_first__0346_BITS_264_ETC___d22316, IF_rob_deqPort_0_deq_data__2403_BIT_294_3418_T_ETC___d23440, - i__h1003714, - thin_perms_soft__h863940, - thin_perms_soft__h904764; + i__h1003709, + thin_perms_soft__h863937, + thin_perms_soft__h904760; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__843_ETC__q246, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9503_ETC__q248, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q244, @@ -4074,15 +4074,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14956, IF_fetchStage_pipelines_0_first__0337_BITS_231_ETC___d20518, IF_fetchStage_pipelines_1_first__0346_BITS_231_ETC___d21479, - x__h505382, - x__h513050; + x__h505379, + x__h513047; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q368, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - thin_reserved__h863692, - thin_reserved__h904588; + thin_reserved__h863689, + thin_reserved__h904584; reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161, @@ -4124,46 +4124,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266, CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q270, CASE_fetchStagepipelines_1_first_BITS_267_TO__ETC__q272, - CASE_guard07290_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74, - CASE_guard07290_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73, - CASE_guard09341_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183, - CASE_guard09341_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173, - CASE_guard18653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179, - CASE_guard18653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175, - CASE_guard26566_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103, - CASE_guard26566_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102, - CASE_guard27722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181, - CASE_guard27722_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177, - CASE_guard31184_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard35273_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105, - CASE_guard35273_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104, - CASE_guard40496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard44203_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107, - CASE_guard44203_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106, - CASE_guard49565_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160, - CASE_guard53039_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109, - CASE_guard53039_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108, - CASE_guard70037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214, - CASE_guard70037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204, - CASE_guard72313_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138, - CASE_guard72313_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, - CASE_guard79349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210, - CASE_guard79349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208, - CASE_guard80815_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68, - CASE_guard80815_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67, - CASE_guard81020_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140, - CASE_guard81020_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139, - CASE_guard88418_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212, - CASE_guard88418_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206, - CASE_guard89524_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70, - CASE_guard89524_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69, - CASE_guard89950_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, - CASE_guard89950_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, - CASE_guard98454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72, - CASE_guard98454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, - CASE_guard98786_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, - CASE_guard98786_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, - CASE_k51774_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267, + CASE_guard07287_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74, + CASE_guard07287_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73, + CASE_guard09338_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183, + CASE_guard09338_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173, + CASE_guard18650_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179, + CASE_guard18650_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175, + CASE_guard26563_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103, + CASE_guard26563_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102, + CASE_guard27719_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181, + CASE_guard27719_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177, + CASE_guard31181_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard35270_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105, + CASE_guard35270_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104, + CASE_guard40493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard44200_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107, + CASE_guard44200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106, + CASE_guard49562_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160, + CASE_guard53036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109, + CASE_guard53036_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108, + CASE_guard70034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214, + CASE_guard70034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204, + CASE_guard72310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138, + CASE_guard72310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, + CASE_guard79346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210, + CASE_guard79346_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208, + CASE_guard80812_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68, + CASE_guard80812_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67, + CASE_guard81017_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140, + CASE_guard81017_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139, + CASE_guard88415_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212, + CASE_guard88415_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206, + CASE_guard89521_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70, + CASE_guard89521_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69, + CASE_guard89947_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, + CASE_guard89947_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, + CASE_guard98451_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72, + CASE_guard98451_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, + CASE_guard98783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, + CASE_guard98783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, + CASE_k51769_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19250, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19286, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19295, @@ -4296,31 +4296,31 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5565; wire [128 : 0] amoExec___d4924, amoExec___d775, - fallthrough_pc__h946297, - fallthrough_pc__h970681, - new_pc__h879225, - new_pc__h918535, - next_pc__h1018619, - pc__h970672, - v__h1018941, - v__h1019394, - x__h872605, - x__h886260, - x__h912582, - x__h921139, - y__h872859, - y__h912836; + fallthrough_pc__h946292, + fallthrough_pc__h970676, + new_pc__h879221, + new_pc__h918530, + next_pc__h1018614, + pc__h970667, + v__h1018936, + v__h1019389, + x__h872602, + x__h886256, + x__h912578, + x__h921134, + y__h872856, + y__h912832; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5170, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4883, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4891, - b__h840751, - b__h840827, - b__h840928, - b__h840940, + b__h840748, + b__h840824, + b__h840925, + b__h840937, coreFix_memExe_regToExeQ_first__652_BITS_139_T_ETC___d4071, - x__h185142, - x__h201306, - x__h841752; + x__h185141, + x__h201305, + x__h841749; wire [108 : 0] IF_fetchStage_pipelines_0_first__0337_BITS_237_ETC___d20692, IF_fetchStage_pipelines_1_first__0346_BITS_237_ETC___d21653; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__689_BIT_10_ETC___d3587; @@ -4344,70 +4344,70 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16429, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3063, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3425, - addTop__h242807, - addTop__h243964, - addTop__h257570, - address__h1007698, - address__h1008042, - address__h1008355, - address__h1008699, + addTop__h242806, + addTop__h243963, + addTop__h257568, + address__h1007693, + address__h1008037, + address__h1008350, + address__h1008694, coreFix_memExe_dTlb_procResp__258_BITS_452_TO__ETC___d4408, coreFix_memExe_regToExeQ_first__652_BITS_219_T_ETC___d3773, coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d3711, - cr_address__h871442, - cr_address__h871990, - cr_address__h911419, - cr_address__h911967, - data_address__h1025079, - data_address__h1025933, - in__h1005860, - in__h242638, - in__h243795, - in__h257401, - pc_address__h1002943, - pointer__h1016884, - pointer__h1036714, - pointer__h245459, - res_address__h127818, - res_address__h140958, - res_address__h180641, - res_address__h199718, - res_address__h218882, - res_address__h238158, - res_address__h571697, - res_address__h572549, - res_address__h618306, - res_address__h664053, - res_address__h709939, - res_address__h710885, - res_address__h854911, - res_address__h898574, - result__h243434, - result__h244591, - result__h258197, - result_d_address__h245670, - ret__h242811, - ret__h243968, - ret__h257574, - x__h1005878, - x__h1007892, - x__h1008196, - x__h1008549, - x__h1008853, - x__h1016908, - x__h1036737, - x__h238581, - x__h242656, - x__h242804, - x__h243813, - x__h243961, - x__h250942, - x__h257419, - x__h257567, - y__h1005877, - y__h242655, - y__h243812, - y__h257418; + cr_address__h871439, + cr_address__h871987, + cr_address__h911415, + cr_address__h911963, + data_address__h1025073, + data_address__h1025927, + in__h1005855, + in__h242637, + in__h243794, + in__h257399, + pc_address__h1002938, + pointer__h1016879, + pointer__h1036708, + pointer__h245458, + res_address__h127817, + res_address__h140957, + res_address__h180640, + res_address__h199717, + res_address__h218881, + res_address__h238157, + res_address__h571693, + res_address__h572546, + res_address__h618303, + res_address__h664050, + res_address__h709936, + res_address__h710882, + res_address__h854908, + res_address__h898570, + result__h243433, + result__h244590, + result__h258195, + result_d_address__h245669, + ret__h242810, + ret__h243967, + ret__h257572, + x__h1005873, + x__h1007887, + x__h1008191, + x__h1008544, + x__h1008848, + x__h1016903, + x__h1036731, + x__h238580, + x__h242655, + x__h242803, + x__h243812, + x__h243960, + x__h250940, + x__h257417, + x__h257565, + y__h1005872, + y__h242654, + y__h243811, + y__h257416; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13412, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12579, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12580, @@ -4433,181 +4433,181 @@ module mkCore(CLK, SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22824, _18446744073709551615_SL_csrf_mtcc_reg_read__68_ETC___d22978, _18446744073709551615_SL_csrf_stcc_reg_read__68_ETC___d22903, - _theResult___fst__h841151, - _theResult___snd__h841152, - a___1__h840765, - a___1__h841156, - a__h840603, - addBase__h242698, - addBase__h243855, - addBase__h257461, - addr__h149965, - addr__h153541, - addr__h238152, - addr__h997804, - address__h1007632, - address__h1007682, - address__h1018672, - address__h872898, - address__h912839, - address__h963272, - address__h988140, - b___1__h840766, - b___1__h841217, - b__h840604, - base__h1007593, - base__h1007647, + _theResult___fst__h841148, + _theResult___snd__h841149, + a___1__h840762, + a___1__h841153, + a__h840600, + addBase__h242697, + addBase__h243854, + addBase__h257459, + addr__h149964, + addr__h153540, + addr__h238151, + addr__h997799, + address__h1007627, + address__h1007677, + address__h1018667, + address__h872895, + address__h912835, + address__h963267, + address__h988135, + b___1__h840763, + b___1__h841214, + b__h840601, + base__h1007588, + base__h1007642, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15384, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15385, csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d22968, csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22891, - data___1__h709961, - data___1__h710907, - data__h572031, - data__h617791, - data__h663538, - data__h709423, - data__h709454, - data__h710369, - data__h710400, - fcsr_csr__read__h855486, - fflags_csr__read__h855461, - frm_csr__read__h855472, - mask__h1007704, - mask__h1008361, - mcause_csr__read__h856902, - mcounteren_csr__read__h856723, - medeleg_csr__read__h856403, - mideleg_csr__read__h856501, - mie_csr__read__h856628, - mip_csr__read__h857141, - mstatus_csr__read__h856249, - n__read__h1020084, + data___1__h709958, + data___1__h710904, + data__h572028, + data__h617788, + data__h663535, + data__h709420, + data__h709451, + data__h710366, + data__h710397, + fcsr_csr__read__h855483, + fflags_csr__read__h855458, + frm_csr__read__h855469, + mask__h1007699, + mask__h1008356, + mcause_csr__read__h856899, + mcounteren_csr__read__h856720, + medeleg_csr__read__h856400, + mideleg_csr__read__h856498, + mie_csr__read__h856625, + mip_csr__read__h857138, + mstatus_csr__read__h856246, + n__read__h1020079, n__read__h7877, - newAddrDiff__h1007705, - newAddrDiff__h1008049, - newAddrDiff__h1008362, - newAddrDiff__h1008706, - offset__h245449, - q___1__h710982, - rVal1__h719373, - rVal2__h719374, - r___1__h711009, - res_data__h572589, - res_data__h572594, - res_data__h618343, - res_data__h618348, - res_data__h664090, - res_data__h664095, - resp_addr__h513469, - rg_tdata1__read__h858242, + newAddrDiff__h1007700, + newAddrDiff__h1008044, + newAddrDiff__h1008357, + newAddrDiff__h1008701, + offset__h245448, + q___1__h710979, + rVal1__h719370, + rVal2__h719371, + r___1__h711006, + res_data__h572586, + res_data__h572591, + res_data__h618340, + res_data__h618345, + res_data__h664087, + res_data__h664092, + resp_addr__h513466, + rg_tdata1__read__h858239, robdeqPort_0_deq_data_BITS_95_TO_32__q327, - satp_csr__read__h856103, - scause_csr__read__h855900, - scounteren_csr__read__h855805, - sie_csr__read__h855752, - sip_csr__read__h856040, - sstatus_csr__read__h855682, - thin_address__h1007586, - tmpAddr__h245658, - trap_val__h1005244, - upd__h1020160, + satp_csr__read__h856100, + scause_csr__read__h855897, + scounteren_csr__read__h855802, + sie_csr__read__h855749, + sip_csr__read__h856037, + sstatus_csr__read__h855679, + thin_address__h1007581, + tmpAddr__h245657, + trap_val__h1005239, + upd__h1020155, upd__h3035, upd__h3645, upd__h7946, - value__h242528, - value__h242692, - value__h243685, - value__h243849, - value__h257291, - value__h257455, - x__h1003115, - x__h1005791, - x__h1005793, - x__h128299, - x__h141443, - x__h185224, - x__h204287, - x__h219258, - x__h242546, - x__h242548, - x__h243703, - x__h243705, - x__h245598, + value__h242527, + value__h242691, + value__h243684, + value__h243848, + value__h257289, + value__h257453, + x__h1003110, + x__h1005786, + x__h1005788, + x__h128298, + x__h141442, + x__h185223, + x__h204286, + x__h219257, + x__h242545, + x__h242547, + x__h243702, + x__h243704, + x__h245597, + x__h257307, x__h257309, - x__h257311, - x__h719279, - x__h719280, - x__h719281, - x__h841140, - x__h871619, - x__h872167, - x__h911596, - x__h912144, + x__h719276, + x__h719277, + x__h719278, + x__h841137, + x__h871616, + x__h872164, + x__h911592, + x__h912140, x_addr__h19852, x_addr__h44221, - x_addr__h539726, - x_quotient__h710171, - x_reg_ifc__read__h855591, - x_remainder__h710172, - y__h1007821, - y__h1008478, - y__h1022701, - y_avValue__h715328, - y_avValue__h716036, - y_avValue__h716738, - y_avValue_snd_snd_snd_snd_snd__h1022111, - y_avValue_snd_snd_snd_snd_snd__h1022754, - y_avValue_snd_snd_snd_snd_snd__h1022783; + x_addr__h539722, + x_quotient__h710168, + x_reg_ifc__read__h855588, + x_remainder__h710169, + y__h1007816, + y__h1008473, + y__h1022696, + y_avValue__h715325, + y_avValue__h716033, + y_avValue__h716735, + y_avValue_snd_snd_snd_snd_snd__h1022106, + y_avValue_snd_snd_snd_snd_snd__h1022749, + y_avValue_snd_snd_snd_snd_snd__h1022778; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14121, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14891, - r1__read__h859119, - r1__read__h859523, - r1__read__h860033, - r1__read__h860052, - r1__read__h860285, - r1__read__h860451, - r1__read__h860544, - r1__read__h860563; - wire [61 : 0] r1__read__h859121, - r1__read__h859525, - r1__read__h860035, - r1__read__h860054, - r1__read__h860287, - r1__read__h860427, - r1__read__h860453, - r1__read__h860546, - r1__read__h860565; - wire [60 : 0] r1__read__h860289, - r1__read__h860429, - r1__read__h860455, - r1__read__h860567; - wire [59 : 0] r1__read__h859123, - r1__read__h859527, - r1__read__h860056, - r1__read__h860291, - r1__read__h860457, - r1__read__h860569; + r1__read__h859116, + r1__read__h859520, + r1__read__h860030, + r1__read__h860049, + r1__read__h860282, + r1__read__h860448, + r1__read__h860541, + r1__read__h860560; + wire [61 : 0] r1__read__h859118, + r1__read__h859522, + r1__read__h860032, + r1__read__h860051, + r1__read__h860284, + r1__read__h860424, + r1__read__h860450, + r1__read__h860543, + r1__read__h860562; + wire [60 : 0] r1__read__h860286, + r1__read__h860426, + r1__read__h860452, + r1__read__h860564; + wire [59 : 0] r1__read__h859120, + r1__read__h859524, + r1__read__h860053, + r1__read__h860288, + r1__read__h860454, + r1__read__h860566; wire [58 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5501, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5543, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d7025, - r1__read__h859125, - r1__read__h859529, - r1__read__h860045, - r1__read__h860058, - r1__read__h860293, - r1__read__h860459, - r1__read__h860556, - r1__read__h860571; + r1__read__h859122, + r1__read__h859526, + r1__read__h860042, + r1__read__h860055, + r1__read__h860290, + r1__read__h860456, + r1__read__h860553, + r1__read__h860568; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7284, - r1__read__h859127, - r1__read__h859531, - r1__read__h860060, - r1__read__h860295, - r1__read__h860431, - r1__read__h860461, - r1__read__h860573, - y__h426243; + r1__read__h859124, + r1__read__h859528, + r1__read__h860057, + r1__read__h860292, + r1__read__h860428, + r1__read__h860458, + r1__read__h860570, + y__h426240; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75, @@ -4635,195 +4635,195 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10151, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11548, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8754, - _theResult____h580805, - _theResult____h598444, - _theResult____h626556, - _theResult____h644193, - _theResult____h672303, - _theResult____h689940, - _theResult____h740486, - _theResult____h779339, - _theResult____h818643, - _theResult___snd__h588927, - _theResult___snd__h588938, - _theResult___snd__h588940, - _theResult___snd__h588950, - _theResult___snd__h588956, - _theResult___snd__h588979, - _theResult___snd__h597523, - _theResult___snd__h597525, - _theResult___snd__h597532, - _theResult___snd__h597538, - _theResult___snd__h597561, - _theResult___snd__h606693, - _theResult___snd__h606704, - _theResult___snd__h606706, - _theResult___snd__h606716, - _theResult___snd__h606722, - _theResult___snd__h606745, - _theResult___snd__h615313, - _theResult___snd__h615327, - _theResult___snd__h615333, - _theResult___snd__h615351, - _theResult___snd__h634676, - _theResult___snd__h634687, - _theResult___snd__h634689, - _theResult___snd__h634699, - _theResult___snd__h634705, - _theResult___snd__h634728, - _theResult___snd__h643272, - _theResult___snd__h643274, - _theResult___snd__h643281, - _theResult___snd__h643287, - _theResult___snd__h643310, - _theResult___snd__h652442, - _theResult___snd__h652453, - _theResult___snd__h652455, - _theResult___snd__h652465, - _theResult___snd__h652471, - _theResult___snd__h652494, - _theResult___snd__h661062, - _theResult___snd__h661076, - _theResult___snd__h661082, - _theResult___snd__h661100, - _theResult___snd__h680423, - _theResult___snd__h680434, - _theResult___snd__h680436, - _theResult___snd__h680446, - _theResult___snd__h680452, - _theResult___snd__h680475, - _theResult___snd__h689019, - _theResult___snd__h689021, - _theResult___snd__h689028, - _theResult___snd__h689034, - _theResult___snd__h689057, - _theResult___snd__h698189, - _theResult___snd__h698200, - _theResult___snd__h698202, - _theResult___snd__h698212, - _theResult___snd__h698218, - _theResult___snd__h698241, - _theResult___snd__h706809, - _theResult___snd__h706823, - _theResult___snd__h706829, - _theResult___snd__h706847, - _theResult___snd__h739096, - _theResult___snd__h739098, - _theResult___snd__h739105, - _theResult___snd__h739111, - _theResult___snd__h739134, - _theResult___snd__h748733, - _theResult___snd__h748744, - _theResult___snd__h748746, - _theResult___snd__h748756, - _theResult___snd__h748762, - _theResult___snd__h748785, - _theResult___snd__h757501, - _theResult___snd__h757515, - _theResult___snd__h757521, - _theResult___snd__h757539, - _theResult___snd__h777949, - _theResult___snd__h777951, - _theResult___snd__h777958, - _theResult___snd__h777964, - _theResult___snd__h777987, - _theResult___snd__h787586, - _theResult___snd__h787597, - _theResult___snd__h787599, - _theResult___snd__h787609, - _theResult___snd__h787615, - _theResult___snd__h787638, - _theResult___snd__h796354, - _theResult___snd__h796368, - _theResult___snd__h796374, - _theResult___snd__h796392, - _theResult___snd__h817253, - _theResult___snd__h817255, - _theResult___snd__h817262, - _theResult___snd__h817268, - _theResult___snd__h817291, - _theResult___snd__h826890, - _theResult___snd__h826901, - _theResult___snd__h826903, - _theResult___snd__h826913, - _theResult___snd__h826919, - _theResult___snd__h826942, - _theResult___snd__h835658, - _theResult___snd__h835672, - _theResult___snd__h835678, - _theResult___snd__h835696, - r1__read__h860297, - r1__read__h860433, - r1__read__h860463, - r1__read__h860575, - result__h599057, - result__h644806, - result__h690553, - result__h741099, - result__h779952, - result__h819256, - sfd__h573200, - sfd__h618954, - sfd__h664701, - sfd__h720119, - sfd__h759113, - sfd__h798417, - sfdin__h588910, - sfdin__h606676, - sfdin__h634659, - sfdin__h652425, - sfdin__h680406, - sfdin__h698172, - sfdin__h748716, - sfdin__h787569, - sfdin__h826873, - x__h599154, - x__h644903, - x__h690650, - x__h741194, - x__h780047, - x__h819351; + _theResult____h580802, + _theResult____h598441, + _theResult____h626553, + _theResult____h644190, + _theResult____h672300, + _theResult____h689937, + _theResult____h740483, + _theResult____h779336, + _theResult____h818640, + _theResult___snd__h588924, + _theResult___snd__h588935, + _theResult___snd__h588937, + _theResult___snd__h588947, + _theResult___snd__h588953, + _theResult___snd__h588976, + _theResult___snd__h597520, + _theResult___snd__h597522, + _theResult___snd__h597529, + _theResult___snd__h597535, + _theResult___snd__h597558, + _theResult___snd__h606690, + _theResult___snd__h606701, + _theResult___snd__h606703, + _theResult___snd__h606713, + _theResult___snd__h606719, + _theResult___snd__h606742, + _theResult___snd__h615310, + _theResult___snd__h615324, + _theResult___snd__h615330, + _theResult___snd__h615348, + _theResult___snd__h634673, + _theResult___snd__h634684, + _theResult___snd__h634686, + _theResult___snd__h634696, + _theResult___snd__h634702, + _theResult___snd__h634725, + _theResult___snd__h643269, + _theResult___snd__h643271, + _theResult___snd__h643278, + _theResult___snd__h643284, + _theResult___snd__h643307, + _theResult___snd__h652439, + _theResult___snd__h652450, + _theResult___snd__h652452, + _theResult___snd__h652462, + _theResult___snd__h652468, + _theResult___snd__h652491, + _theResult___snd__h661059, + _theResult___snd__h661073, + _theResult___snd__h661079, + _theResult___snd__h661097, + _theResult___snd__h680420, + _theResult___snd__h680431, + _theResult___snd__h680433, + _theResult___snd__h680443, + _theResult___snd__h680449, + _theResult___snd__h680472, + _theResult___snd__h689016, + _theResult___snd__h689018, + _theResult___snd__h689025, + _theResult___snd__h689031, + _theResult___snd__h689054, + _theResult___snd__h698186, + _theResult___snd__h698197, + _theResult___snd__h698199, + _theResult___snd__h698209, + _theResult___snd__h698215, + _theResult___snd__h698238, + _theResult___snd__h706806, + _theResult___snd__h706820, + _theResult___snd__h706826, + _theResult___snd__h706844, + _theResult___snd__h739093, + _theResult___snd__h739095, + _theResult___snd__h739102, + _theResult___snd__h739108, + _theResult___snd__h739131, + _theResult___snd__h748730, + _theResult___snd__h748741, + _theResult___snd__h748743, + _theResult___snd__h748753, + _theResult___snd__h748759, + _theResult___snd__h748782, + _theResult___snd__h757498, + _theResult___snd__h757512, + _theResult___snd__h757518, + _theResult___snd__h757536, + _theResult___snd__h777946, + _theResult___snd__h777948, + _theResult___snd__h777955, + _theResult___snd__h777961, + _theResult___snd__h777984, + _theResult___snd__h787583, + _theResult___snd__h787594, + _theResult___snd__h787596, + _theResult___snd__h787606, + _theResult___snd__h787612, + _theResult___snd__h787635, + _theResult___snd__h796351, + _theResult___snd__h796365, + _theResult___snd__h796371, + _theResult___snd__h796389, + _theResult___snd__h817250, + _theResult___snd__h817252, + _theResult___snd__h817259, + _theResult___snd__h817265, + _theResult___snd__h817288, + _theResult___snd__h826887, + _theResult___snd__h826898, + _theResult___snd__h826900, + _theResult___snd__h826910, + _theResult___snd__h826916, + _theResult___snd__h826939, + _theResult___snd__h835655, + _theResult___snd__h835669, + _theResult___snd__h835675, + _theResult___snd__h835693, + r1__read__h860294, + r1__read__h860430, + r1__read__h860460, + r1__read__h860572, + result__h599054, + result__h644803, + result__h690550, + result__h741096, + result__h779949, + result__h819253, + sfd__h573197, + sfd__h618951, + sfd__h664698, + sfd__h720116, + sfd__h759110, + sfd__h798414, + sfdin__h588907, + sfdin__h606673, + sfdin__h634656, + sfdin__h652422, + sfdin__h680403, + sfdin__h698169, + sfdin__h748713, + sfdin__h787566, + sfdin__h826870, + x__h599151, + x__h644900, + x__h690647, + x__h741191, + x__h780044, + x__h819348; wire [55 : 0] coreFix_memExe_dispToRegQ_first__689_BIT_101_6_ETC___d3586, - r1__read__h859129, - r1__read__h859533, - r1__read__h860062, - r1__read__h860299, - r1__read__h860465, - r1__read__h860577; + r1__read__h859126, + r1__read__h859530, + r1__read__h860059, + r1__read__h860296, + r1__read__h860462, + r1__read__h860574; wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19440, IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17276, - r1__read__h859131, - r1__read__h859535, - r1__read__h860064, - r1__read__h860301, - r1__read__h860467, - r1__read__h860579; - wire [53 : 0] r1__read__h860410, - r1__read__h860435, - r1__read__h860469, - r1__read__h860581, - sfd__h739163, - sfd__h748814, - sfd__h757574, - sfd__h778016, - sfd__h787667, - sfd__h796427, - sfd__h817320, - sfd__h826971, - sfd__h835731, - value__h581427, - value__h627176, - value__h672923; + r1__read__h859128, + r1__read__h859532, + r1__read__h860061, + r1__read__h860298, + r1__read__h860464, + r1__read__h860576; + wire [53 : 0] r1__read__h860407, + r1__read__h860432, + r1__read__h860466, + r1__read__h860578, + sfd__h739160, + sfd__h748811, + sfd__h757571, + sfd__h778013, + sfd__h787664, + sfd__h796424, + sfd__h817317, + sfd__h826968, + sfd__h835728, + value__h581424, + value__h627173, + value__h672920; wire [52 : 0] IF_coreFix_memExe_dispToRegQ_first__689_BIT_10_ETC___d3585, INV_coreFix_aluExe_0_regToExeQ_first__9503_BIT_ETC___d19807, INV_coreFix_aluExe_0_regToExeQ_first__9503_BIT_ETC___d19871, INV_coreFix_aluExe_1_regToExeQ_first__7365_BIT_ETC___d17669, INV_coreFix_aluExe_1_regToExeQ_first__7365_BIT_ETC___d17733, - r1__read__h860303, - r1__read__h860412, - r1__read__h860437, - r1__read__h860471, - r1__read__h860583; + r1__read__h860300, + r1__read__h860409, + r1__read__h860434, + r1__read__h860468, + r1__read__h860580; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13379, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13381, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14088, @@ -4845,85 +4845,85 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13411, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14120, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14890, - _theResult___fst_sfd__h724073, + _theResult___fst_sfd__h724070, + _theResult___fst_sfd__h739898, _theResult___fst_sfd__h739901, - _theResult___fst_sfd__h739904, + _theResult___fst_sfd__h749549, _theResult___fst_sfd__h749552, - _theResult___fst_sfd__h749555, + _theResult___fst_sfd__h758333, _theResult___fst_sfd__h758336, - _theResult___fst_sfd__h758339, - _theResult___fst_sfd__h758348, - _theResult___fst_sfd__h758354, - _theResult___fst_sfd__h762926, + _theResult___fst_sfd__h758345, + _theResult___fst_sfd__h758351, + _theResult___fst_sfd__h762923, + _theResult___fst_sfd__h778751, _theResult___fst_sfd__h778754, - _theResult___fst_sfd__h778757, + _theResult___fst_sfd__h788402, _theResult___fst_sfd__h788405, - _theResult___fst_sfd__h788408, + _theResult___fst_sfd__h797186, _theResult___fst_sfd__h797189, - _theResult___fst_sfd__h797192, - _theResult___fst_sfd__h797201, - _theResult___fst_sfd__h797207, - _theResult___fst_sfd__h802230, + _theResult___fst_sfd__h797198, + _theResult___fst_sfd__h797204, + _theResult___fst_sfd__h802227, + _theResult___fst_sfd__h818055, _theResult___fst_sfd__h818058, - _theResult___fst_sfd__h818061, + _theResult___fst_sfd__h827706, _theResult___fst_sfd__h827709, - _theResult___fst_sfd__h827712, + _theResult___fst_sfd__h836490, _theResult___fst_sfd__h836493, - _theResult___fst_sfd__h836496, - _theResult___fst_sfd__h836505, - _theResult___fst_sfd__h836511, - _theResult___sfd__h739801, - _theResult___sfd__h749452, - _theResult___sfd__h758236, - _theResult___sfd__h778654, - _theResult___sfd__h788305, - _theResult___sfd__h797089, - _theResult___sfd__h817958, - _theResult___sfd__h827609, - _theResult___sfd__h836393, - _theResult___snd_fst_sfd__h720073, - _theResult___snd_fst_sfd__h739907, - _theResult___snd_fst_sfd__h758342, - _theResult___snd_fst_sfd__h759067, - _theResult___snd_fst_sfd__h778760, - _theResult___snd_fst_sfd__h797195, - _theResult___snd_fst_sfd__h798371, - _theResult___snd_fst_sfd__h818064, - _theResult___snd_fst_sfd__h836499, - mask__h242808, - mask__h243965, - mask__h257571, - out___1_sfd__h719821, - out___1_sfd__h758815, - out___1_sfd__h798119, - out_sfd__h739804, - out_sfd__h749455, - out_sfd__h758239, - out_sfd__h778657, - out_sfd__h788308, - out_sfd__h797092, - out_sfd__h817961, - out_sfd__h827612, - out_sfd__h836396; - wire [50 : 0] r1__read__h859133, r1__read__h860305; + _theResult___fst_sfd__h836502, + _theResult___fst_sfd__h836508, + _theResult___sfd__h739798, + _theResult___sfd__h749449, + _theResult___sfd__h758233, + _theResult___sfd__h778651, + _theResult___sfd__h788302, + _theResult___sfd__h797086, + _theResult___sfd__h817955, + _theResult___sfd__h827606, + _theResult___sfd__h836390, + _theResult___snd_fst_sfd__h720070, + _theResult___snd_fst_sfd__h739904, + _theResult___snd_fst_sfd__h758339, + _theResult___snd_fst_sfd__h759064, + _theResult___snd_fst_sfd__h778757, + _theResult___snd_fst_sfd__h797192, + _theResult___snd_fst_sfd__h798368, + _theResult___snd_fst_sfd__h818061, + _theResult___snd_fst_sfd__h836496, + mask__h242807, + mask__h243964, + mask__h257569, + out___1_sfd__h719818, + out___1_sfd__h758812, + out___1_sfd__h798116, + out_sfd__h739801, + out_sfd__h749452, + out_sfd__h758236, + out_sfd__h778654, + out_sfd__h788305, + out_sfd__h797089, + out_sfd__h817958, + out_sfd__h827609, + out_sfd__h836393; + wire [50 : 0] r1__read__h859130, r1__read__h860302; wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q5, coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3, - highOffsetBits__h245468, - mask__h242699, - mask__h243856, - mask__h257462, - r1__read__h860414, - signBits__h245465, - x__h245495; - wire [48 : 0] r1__read__h859135, r1__read__h860307, r1__read__h860416; - wire [46 : 0] r1__read__h859137, r1__read__h860309; - wire [45 : 0] r1__read__h859139, r1__read__h860311; - wire [44 : 0] r1__read__h859141, r1__read__h860313; - wire [43 : 0] r1__read__h859143, r1__read__h860315; - wire [42 : 0] r1__read__h860317; - wire [41 : 0] r1__read__h860319; - wire [40 : 0] r1__read__h860321; + highOffsetBits__h245467, + mask__h242698, + mask__h243855, + mask__h257460, + r1__read__h860411, + signBits__h245464, + x__h245494; + wire [48 : 0] r1__read__h859132, r1__read__h860304, r1__read__h860413; + wire [46 : 0] r1__read__h859134, r1__read__h860306; + wire [45 : 0] r1__read__h859136, r1__read__h860308; + wire [44 : 0] r1__read__h859138, r1__read__h860310; + wire [43 : 0] r1__read__h859140, r1__read__h860312; + wire [42 : 0] r1__read__h860314; + wire [41 : 0] r1__read__h860316; + wire [40 : 0] r1__read__h860318; wire [38 : 0] IF_csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_c_ETC___d23035; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958, IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126, @@ -4947,17 +4947,17 @@ module mkCore(CLK, wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22, coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16, - data09423_BITS_31_TO_0__q21, - data10369_BITS_31_TO_0__q26, - r1__read__h859145, - r1__read__h860323, - x__h572604, - x__h618358, + data09420_BITS_31_TO_0__q21, + data10366_BITS_31_TO_0__q26, + r1__read__h859142, + r1__read__h860320, + x__h572601, + x__h618355, x__h65608, - x__h664105, + x__h664102, x_data__h60109; - wire [29 : 0] r1__read__h859147, r1__read__h860325; - wire [27 : 0] r1__read__h860327; + wire [29 : 0] r1__read__h859144, r1__read__h860322; + wire [27 : 0] r1__read__h860324; wire [25 : 0] IF_IF_csrf_prv_reg_read__0367_ULE_1_2761_AND_I_ETC___d23053, IF_basicExec_7757_BIT_325_7768_THEN_basicExec__ETC___d17776, IF_basicExec_9895_BIT_325_9906_THEN_basicExec__ETC___d19914, @@ -4969,21 +4969,21 @@ module mkCore(CLK, IF_csrf_mepcc_reg_read_wget__3506_BIT_34_3515__ETC___d23523, IF_csrf_rg_dpc_read__6376_BIT_34_4200_THEN_csr_ETC___d24208, IF_csrf_sepcc_reg_read_wget__3477_BIT_34_3486__ETC___d23494; - wire [24 : 0] sfd__h589008, - sfd__h597590, - sfd__h606774, - sfd__h615386, - sfd__h634757, - sfd__h643339, - sfd__h652523, - sfd__h661135, - sfd__h680504, - sfd__h689086, - sfd__h698270, - sfd__h706882, - value__h724702, - value__h763555, - value__h802859; + wire [24 : 0] sfd__h589005, + sfd__h597587, + sfd__h606771, + sfd__h615383, + sfd__h634754, + sfd__h643336, + sfd__h652520, + sfd__h661132, + sfd__h680501, + sfd__h689083, + sfd__h698267, + sfd__h706879, + value__h724699, + value__h763552, + value__h802856; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10550, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10552, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11947, @@ -5008,67 +5008,67 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9174, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9218, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9220, - _theResult___fst_sfd__h589514, - _theResult___fst_sfd__h598096, - _theResult___fst_sfd__h607280, - _theResult___fst_sfd__h615916, - _theResult___fst_sfd__h615925, - _theResult___fst_sfd__h615931, - _theResult___fst_sfd__h635263, - _theResult___fst_sfd__h643845, - _theResult___fst_sfd__h653029, - _theResult___fst_sfd__h661665, - _theResult___fst_sfd__h661674, - _theResult___fst_sfd__h661680, - _theResult___fst_sfd__h681010, - _theResult___fst_sfd__h689592, - _theResult___fst_sfd__h698776, - _theResult___fst_sfd__h707412, - _theResult___fst_sfd__h707421, - _theResult___fst_sfd__h707427, - _theResult___sfd__h589433, - _theResult___sfd__h598015, - _theResult___sfd__h607199, - _theResult___sfd__h615835, - _theResult___sfd__h615937, - _theResult___sfd__h635182, - _theResult___sfd__h643764, - _theResult___sfd__h652948, - _theResult___sfd__h661584, - _theResult___sfd__h661686, - _theResult___sfd__h680929, - _theResult___sfd__h689511, - _theResult___sfd__h698695, - _theResult___sfd__h707331, - _theResult___sfd__h707433, - _theResult___snd_fst_sfd__h573150, - _theResult___snd_fst_sfd__h598099, - _theResult___snd_fst_sfd__h615919, - _theResult___snd_fst_sfd__h618904, - _theResult___snd_fst_sfd__h643848, - _theResult___snd_fst_sfd__h661668, - _theResult___snd_fst_sfd__h664651, - _theResult___snd_fst_sfd__h689595, - _theResult___snd_fst_sfd__h707415, - f1_sfd__h719758, - f2_sfd__h758752, - f3_sfd__h798056, - out_f_sfd__h616214, - out_f_sfd__h661963, - out_f_sfd__h707710, - out_sfd__h589436, - out_sfd__h598018, - out_sfd__h607202, - out_sfd__h615838, - out_sfd__h635185, - out_sfd__h643767, - out_sfd__h652951, - out_sfd__h661587, - out_sfd__h680932, - out_sfd__h689514, - out_sfd__h698698, - out_sfd__h707334; - wire [19 : 0] r1__read__h860262; + _theResult___fst_sfd__h589511, + _theResult___fst_sfd__h598093, + _theResult___fst_sfd__h607277, + _theResult___fst_sfd__h615913, + _theResult___fst_sfd__h615922, + _theResult___fst_sfd__h615928, + _theResult___fst_sfd__h635260, + _theResult___fst_sfd__h643842, + _theResult___fst_sfd__h653026, + _theResult___fst_sfd__h661662, + _theResult___fst_sfd__h661671, + _theResult___fst_sfd__h661677, + _theResult___fst_sfd__h681007, + _theResult___fst_sfd__h689589, + _theResult___fst_sfd__h698773, + _theResult___fst_sfd__h707409, + _theResult___fst_sfd__h707418, + _theResult___fst_sfd__h707424, + _theResult___sfd__h589430, + _theResult___sfd__h598012, + _theResult___sfd__h607196, + _theResult___sfd__h615832, + _theResult___sfd__h615934, + _theResult___sfd__h635179, + _theResult___sfd__h643761, + _theResult___sfd__h652945, + _theResult___sfd__h661581, + _theResult___sfd__h661683, + _theResult___sfd__h680926, + _theResult___sfd__h689508, + _theResult___sfd__h698692, + _theResult___sfd__h707328, + _theResult___sfd__h707430, + _theResult___snd_fst_sfd__h573147, + _theResult___snd_fst_sfd__h598096, + _theResult___snd_fst_sfd__h615916, + _theResult___snd_fst_sfd__h618901, + _theResult___snd_fst_sfd__h643845, + _theResult___snd_fst_sfd__h661665, + _theResult___snd_fst_sfd__h664648, + _theResult___snd_fst_sfd__h689592, + _theResult___snd_fst_sfd__h707412, + f1_sfd__h719755, + f2_sfd__h758749, + f3_sfd__h798053, + out_f_sfd__h616211, + out_f_sfd__h661960, + out_f_sfd__h707707, + out_sfd__h589433, + out_sfd__h598015, + out_sfd__h607199, + out_sfd__h615835, + out_sfd__h635182, + out_sfd__h643764, + out_sfd__h652948, + out_sfd__h661584, + out_sfd__h680929, + out_sfd__h689511, + out_sfd__h698695, + out_sfd__h707331; + wire [19 : 0] r1__read__h860259; wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, @@ -5077,8 +5077,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, - INV_x01306_BITS_108_TO_90__q36, - INV_x85142_BITS_108_TO_90__q34; + INV_x01305_BITS_108_TO_90__q36, + INV_x85141_BITS_108_TO_90__q34; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19096, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19097, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__578_ETC___d16653, @@ -5095,23 +5095,23 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3567; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404, IF_coreFix_memExe_dispToRegQ_first__689_BIT_10_ETC___d3544, - _theResult____h926748, - base__h1005778, - base__h242533, - base__h243690, - base__h257296, - enabled_ints___1__h927273, - enabled_ints__h927319, - offset__h1005779, - offset__h242534, - offset__h243691, - offset__h257297, - pend_ints__h926746, - x__h242906, - x__h244063, - x__h257669, - x__h902154, - y__h927285; + _theResult____h926743, + base__h1005773, + base__h242532, + base__h243689, + base__h257294, + enabled_ints___1__h927268, + enabled_ints__h927314, + offset__h1005774, + offset__h242533, + offset__h243690, + offset__h257295, + pend_ints__h926741, + x__h242905, + x__h244062, + x__h257667, + x__h902150, + y__h927280; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d18882, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d18883, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__578_ETC___d16439, @@ -5133,65 +5133,65 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16444, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3083, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3433, - b_base__h1003340, - b_base__h128524, - b_base__h141668, - b_base__h185449, - b_base__h204512, - b_base__h219483, - b_base__h871857, - b_base__h872405, - b_base__h911834, - b_base__h912382, + b_base__h1003335, + b_base__h128523, + b_base__h141667, + b_base__h185448, + b_base__h204511, + b_base__h219482, + b_base__h871854, + b_base__h872402, + b_base__h911830, + b_base__h912378, checkForException___d20724, checkForException___d21674, - cr_addrBits__h871443, - cr_addrBits__h871991, - cr_addrBits__h911420, - cr_addrBits__h911968, - data_addrBits__h1025080, - data_addrBits__h1025934, - pc_addrBits__h1002944, - r1__read_BITS_13_TO_0___h927295, - repBoundBits__h245474, - res_addrBits__h127819, - res_addrBits__h140959, - res_addrBits__h180642, - res_addrBits__h199719, - res_addrBits__h218883, - res_addrBits__h238159, - res_addrBits__h571698, - res_addrBits__h572550, - res_addrBits__h618307, - res_addrBits__h664054, - res_addrBits__h709940, - res_addrBits__h710886, - res_addrBits__h854912, - res_addrBits__h898575, - toBoundsM1__h245478, - toBounds__h245477, - x1_avValue_new_pcc_capFat_bounds_baseBits__h1009091, - x__h1003313, - x__h1003333, - x__h1009088, - x__h128497, - x__h128517, - x__h141641, - x__h141661, - x__h185422, - x__h185442, - x__h204485, - x__h204505, - x__h219456, - x__h219476, - x__h871830, - x__h871850, - x__h872378, - x__h872398, - x__h911807, - x__h911827, - x__h912355, - x__h912375; + cr_addrBits__h871440, + cr_addrBits__h871988, + cr_addrBits__h911416, + cr_addrBits__h911964, + data_addrBits__h1025074, + data_addrBits__h1025928, + pc_addrBits__h1002939, + r1__read_BITS_13_TO_0___h927290, + repBoundBits__h245473, + res_addrBits__h127818, + res_addrBits__h140958, + res_addrBits__h180641, + res_addrBits__h199718, + res_addrBits__h218882, + res_addrBits__h238158, + res_addrBits__h571694, + res_addrBits__h572547, + res_addrBits__h618304, + res_addrBits__h664051, + res_addrBits__h709937, + res_addrBits__h710883, + res_addrBits__h854909, + res_addrBits__h898571, + toBoundsM1__h245477, + toBounds__h245476, + x1_avValue_new_pcc_capFat_bounds_baseBits__h1009086, + x__h1003308, + x__h1003328, + x__h1009083, + x__h128496, + x__h128516, + x__h141640, + x__h141660, + x__h185421, + x__h185441, + x__h204484, + x__h204504, + x__h219455, + x__h219475, + x__h871827, + x__h871847, + x__h872375, + x__h872395, + x__h911803, + x__h911823, + x__h912351, + x__h912371; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__258_BIT_27_ETC___d4758, IF_NOT_renameStage_rg_m_halt_req_0364_BIT_4_03_ETC___d21057, IF_NOT_renameStage_rg_m_halt_req_0364_BIT_4_03_ETC___d21058, @@ -5227,47 +5227,47 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10147, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11544, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8750, - b_top__h1003339, - b_top__h128523, - b_top__h141667, - b_top__h185448, - b_top__h204511, - b_top__h219482, - b_top__h871856, - b_top__h872404, - b_top__h911833, - b_top__h912381, + b_top__h1003334, + b_top__h128522, + b_top__h141666, + b_top__h185447, + b_top__h204510, + b_top__h219481, + b_top__h871853, + b_top__h872401, + b_top__h911829, + b_top__h912377, capChecks___d4161, - inc__h963271, - inc__h988139, - renaming_spec_bits__h976130, - result__h922326, - result__h922377, - spec_bits__h981149, - topBits__h1003242, - topBits__h128426, - topBits__h141570, - topBits__h185351, - topBits__h204414, - topBits__h219385, - topBits__h871758, - topBits__h872306, - topBits__h911735, - topBits__h912283, - w__h922321, - x__h599187, - x__h644936, - x__h690683, - x__h741227, - x__h780080, - x__h819384, - x__h922325, - x__h922376, - y__h922355, - y__h981162, - y_avValue_snd_fst__h970815, - y_avValue_snd_fst__h970857, - y_avValue_snd_fst__h970899; + inc__h963266, + inc__h988134, + renaming_spec_bits__h976125, + result__h922321, + result__h922372, + spec_bits__h981144, + topBits__h1003237, + topBits__h128425, + topBits__h141569, + topBits__h185350, + topBits__h204413, + topBits__h219384, + topBits__h871755, + topBits__h872303, + topBits__h911731, + topBits__h912279, + w__h922316, + x__h599184, + x__h644933, + x__h690680, + x__h741224, + x__h780077, + x__h819381, + x__h922320, + x__h922371, + y__h922350, + y__h981157, + y_avValue_snd_fst__h970810, + y_avValue_snd_fst__h970852, + y_avValue_snd_fst__h970894; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13295, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13297, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14005, @@ -5291,103 +5291,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q151, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q168, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q191, - _theResult___exp__h739800, - _theResult___exp__h749451, - _theResult___exp__h758235, - _theResult___exp__h778653, - _theResult___exp__h788304, - _theResult___exp__h797088, - _theResult___exp__h817957, - _theResult___exp__h827608, - _theResult___exp__h836392, - _theResult___fst_exp__h724072, - _theResult___fst_exp__h739136, + _theResult___exp__h739797, + _theResult___exp__h749448, + _theResult___exp__h758232, + _theResult___exp__h778650, + _theResult___exp__h788301, + _theResult___exp__h797085, + _theResult___exp__h817954, + _theResult___exp__h827605, + _theResult___exp__h836389, + _theResult___fst_exp__h724069, + _theResult___fst_exp__h739133, + _theResult___fst_exp__h739139, _theResult___fst_exp__h739142, - _theResult___fst_exp__h739145, + _theResult___fst_exp__h739897, _theResult___fst_exp__h739900, - _theResult___fst_exp__h739903, - _theResult___fst_exp__h748722, - _theResult___fst_exp__h748787, + _theResult___fst_exp__h748719, + _theResult___fst_exp__h748784, + _theResult___fst_exp__h748790, _theResult___fst_exp__h748793, - _theResult___fst_exp__h748796, + _theResult___fst_exp__h749548, _theResult___fst_exp__h749551, - _theResult___fst_exp__h749554, - _theResult___fst_exp__h757507, - _theResult___fst_exp__h757546, + _theResult___fst_exp__h757504, + _theResult___fst_exp__h757543, + _theResult___fst_exp__h757549, _theResult___fst_exp__h757552, - _theResult___fst_exp__h757555, + _theResult___fst_exp__h758332, _theResult___fst_exp__h758335, - _theResult___fst_exp__h758338, + _theResult___fst_exp__h758344, _theResult___fst_exp__h758347, - _theResult___fst_exp__h758350, - _theResult___fst_exp__h762925, - _theResult___fst_exp__h777989, + _theResult___fst_exp__h762922, + _theResult___fst_exp__h777986, + _theResult___fst_exp__h777992, _theResult___fst_exp__h777995, - _theResult___fst_exp__h777998, + _theResult___fst_exp__h778750, _theResult___fst_exp__h778753, - _theResult___fst_exp__h778756, - _theResult___fst_exp__h787575, - _theResult___fst_exp__h787640, + _theResult___fst_exp__h787572, + _theResult___fst_exp__h787637, + _theResult___fst_exp__h787643, _theResult___fst_exp__h787646, - _theResult___fst_exp__h787649, + _theResult___fst_exp__h788401, _theResult___fst_exp__h788404, - _theResult___fst_exp__h788407, - _theResult___fst_exp__h796360, - _theResult___fst_exp__h796399, + _theResult___fst_exp__h796357, + _theResult___fst_exp__h796396, + _theResult___fst_exp__h796402, _theResult___fst_exp__h796405, - _theResult___fst_exp__h796408, + _theResult___fst_exp__h797185, _theResult___fst_exp__h797188, - _theResult___fst_exp__h797191, + _theResult___fst_exp__h797197, _theResult___fst_exp__h797200, - _theResult___fst_exp__h797203, - _theResult___fst_exp__h802229, - _theResult___fst_exp__h817293, + _theResult___fst_exp__h802226, + _theResult___fst_exp__h817290, + _theResult___fst_exp__h817296, _theResult___fst_exp__h817299, - _theResult___fst_exp__h817302, + _theResult___fst_exp__h818054, _theResult___fst_exp__h818057, - _theResult___fst_exp__h818060, - _theResult___fst_exp__h826879, - _theResult___fst_exp__h826944, + _theResult___fst_exp__h826876, + _theResult___fst_exp__h826941, + _theResult___fst_exp__h826947, _theResult___fst_exp__h826950, - _theResult___fst_exp__h826953, + _theResult___fst_exp__h827705, _theResult___fst_exp__h827708, - _theResult___fst_exp__h827711, - _theResult___fst_exp__h835664, - _theResult___fst_exp__h835703, + _theResult___fst_exp__h835661, + _theResult___fst_exp__h835700, + _theResult___fst_exp__h835706, _theResult___fst_exp__h835709, - _theResult___fst_exp__h835712, + _theResult___fst_exp__h836489, _theResult___fst_exp__h836492, - _theResult___fst_exp__h836495, + _theResult___fst_exp__h836501, _theResult___fst_exp__h836504, - _theResult___fst_exp__h836507, - _theResult___snd_fst_exp__h739906, - _theResult___snd_fst_exp__h758341, - _theResult___snd_fst_exp__h778759, - _theResult___snd_fst_exp__h797194, - _theResult___snd_fst_exp__h818063, - _theResult___snd_fst_exp__h836498, + _theResult___snd_fst_exp__h739903, + _theResult___snd_fst_exp__h758338, + _theResult___snd_fst_exp__h778756, + _theResult___snd_fst_exp__h797191, + _theResult___snd_fst_exp__h818060, + _theResult___snd_fst_exp__h836495, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q48, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q118, - din_inc___2_exp__h758395, - din_inc___2_exp__h758430, - din_inc___2_exp__h758456, - din_inc___2_exp__h797248, - din_inc___2_exp__h797283, - din_inc___2_exp__h797309, - din_inc___2_exp__h836552, - din_inc___2_exp__h836587, - din_inc___2_exp__h836613, - out_exp__h739803, - out_exp__h749454, - out_exp__h758238, - out_exp__h778656, - out_exp__h788307, - out_exp__h797091, - out_exp__h817960, - out_exp__h827611, - out_exp__h836395, - x__h1007065; + din_inc___2_exp__h758392, + din_inc___2_exp__h758427, + din_inc___2_exp__h758453, + din_inc___2_exp__h797245, + din_inc___2_exp__h797280, + din_inc___2_exp__h797306, + din_inc___2_exp__h836549, + din_inc___2_exp__h836584, + din_inc___2_exp__h836610, + out_exp__h739800, + out_exp__h749451, + out_exp__h758235, + out_exp__h778653, + out_exp__h788304, + out_exp__h797088, + out_exp__h817957, + out_exp__h827608, + out_exp__h836392, + x__h1007060; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__689_BIT_10_ETC___d3642; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10465, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11862, @@ -5443,128 +5443,128 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q89, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q54, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q124, - _theResult___exp__h589432, - _theResult___exp__h598014, - _theResult___exp__h607198, - _theResult___exp__h615834, - _theResult___exp__h615936, - _theResult___exp__h635181, - _theResult___exp__h643763, - _theResult___exp__h652947, - _theResult___exp__h661583, - _theResult___exp__h661685, - _theResult___exp__h680928, - _theResult___exp__h689510, - _theResult___exp__h698694, - _theResult___exp__h707330, - _theResult___exp__h707432, - _theResult___fst_exp__h588916, - _theResult___fst_exp__h588981, + _theResult___exp__h589429, + _theResult___exp__h598011, + _theResult___exp__h607195, + _theResult___exp__h615831, + _theResult___exp__h615933, + _theResult___exp__h635178, + _theResult___exp__h643760, + _theResult___exp__h652944, + _theResult___exp__h661580, + _theResult___exp__h661682, + _theResult___exp__h680925, + _theResult___exp__h689507, + _theResult___exp__h698691, + _theResult___exp__h707327, + _theResult___exp__h707429, + _theResult___fst_exp__h588913, + _theResult___fst_exp__h588978, + _theResult___fst_exp__h588984, _theResult___fst_exp__h588987, - _theResult___fst_exp__h588990, - _theResult___fst_exp__h589513, - _theResult___fst_exp__h597563, + _theResult___fst_exp__h589510, + _theResult___fst_exp__h597560, + _theResult___fst_exp__h597566, _theResult___fst_exp__h597569, - _theResult___fst_exp__h597572, - _theResult___fst_exp__h598095, - _theResult___fst_exp__h606682, - _theResult___fst_exp__h606747, + _theResult___fst_exp__h598092, + _theResult___fst_exp__h606679, + _theResult___fst_exp__h606744, + _theResult___fst_exp__h606750, _theResult___fst_exp__h606753, - _theResult___fst_exp__h606756, - _theResult___fst_exp__h607279, - _theResult___fst_exp__h615319, - _theResult___fst_exp__h615358, + _theResult___fst_exp__h607276, + _theResult___fst_exp__h615316, + _theResult___fst_exp__h615355, + _theResult___fst_exp__h615361, _theResult___fst_exp__h615364, - _theResult___fst_exp__h615367, - _theResult___fst_exp__h615915, + _theResult___fst_exp__h615912, + _theResult___fst_exp__h615921, _theResult___fst_exp__h615924, - _theResult___fst_exp__h615927, - _theResult___fst_exp__h634665, - _theResult___fst_exp__h634730, + _theResult___fst_exp__h634662, + _theResult___fst_exp__h634727, + _theResult___fst_exp__h634733, _theResult___fst_exp__h634736, - _theResult___fst_exp__h634739, - _theResult___fst_exp__h635262, - _theResult___fst_exp__h643312, + _theResult___fst_exp__h635259, + _theResult___fst_exp__h643309, + _theResult___fst_exp__h643315, _theResult___fst_exp__h643318, - _theResult___fst_exp__h643321, - _theResult___fst_exp__h643844, - _theResult___fst_exp__h652431, - _theResult___fst_exp__h652496, + _theResult___fst_exp__h643841, + _theResult___fst_exp__h652428, + _theResult___fst_exp__h652493, + _theResult___fst_exp__h652499, _theResult___fst_exp__h652502, - _theResult___fst_exp__h652505, - _theResult___fst_exp__h653028, - _theResult___fst_exp__h661068, - _theResult___fst_exp__h661107, + _theResult___fst_exp__h653025, + _theResult___fst_exp__h661065, + _theResult___fst_exp__h661104, + _theResult___fst_exp__h661110, _theResult___fst_exp__h661113, - _theResult___fst_exp__h661116, - _theResult___fst_exp__h661664, + _theResult___fst_exp__h661661, + _theResult___fst_exp__h661670, _theResult___fst_exp__h661673, - _theResult___fst_exp__h661676, - _theResult___fst_exp__h680412, - _theResult___fst_exp__h680477, + _theResult___fst_exp__h680409, + _theResult___fst_exp__h680474, + _theResult___fst_exp__h680480, _theResult___fst_exp__h680483, - _theResult___fst_exp__h680486, - _theResult___fst_exp__h681009, - _theResult___fst_exp__h689059, + _theResult___fst_exp__h681006, + _theResult___fst_exp__h689056, + _theResult___fst_exp__h689062, _theResult___fst_exp__h689065, - _theResult___fst_exp__h689068, - _theResult___fst_exp__h689591, - _theResult___fst_exp__h698178, - _theResult___fst_exp__h698243, + _theResult___fst_exp__h689588, + _theResult___fst_exp__h698175, + _theResult___fst_exp__h698240, + _theResult___fst_exp__h698246, _theResult___fst_exp__h698249, - _theResult___fst_exp__h698252, - _theResult___fst_exp__h698775, - _theResult___fst_exp__h706815, - _theResult___fst_exp__h706854, + _theResult___fst_exp__h698772, + _theResult___fst_exp__h706812, + _theResult___fst_exp__h706851, + _theResult___fst_exp__h706857, _theResult___fst_exp__h706860, - _theResult___fst_exp__h706863, - _theResult___fst_exp__h707411, + _theResult___fst_exp__h707408, + _theResult___fst_exp__h707417, _theResult___fst_exp__h707420, - _theResult___fst_exp__h707423, - _theResult___snd_fst_exp__h598098, - _theResult___snd_fst_exp__h615918, - _theResult___snd_fst_exp__h643847, - _theResult___snd_fst_exp__h661667, - _theResult___snd_fst_exp__h689594, - _theResult___snd_fst_exp__h707414, - din_inc___2_exp__h615949, - din_inc___2_exp__h615973, - din_inc___2_exp__h616003, - din_inc___2_exp__h616027, - din_inc___2_exp__h661698, - din_inc___2_exp__h661722, - din_inc___2_exp__h661752, - din_inc___2_exp__h661776, - din_inc___2_exp__h707445, - din_inc___2_exp__h707469, - din_inc___2_exp__h707499, - din_inc___2_exp__h707523, - f1_exp19757_MINUS_127__q147, - f1_exp__h719757, - f2_exp58751_MINUS_127__q187, - f2_exp__h758751, - f3_exp98055_MINUS_127__q164, - f3_exp__h798055, - out_exp__h589435, - out_exp__h598017, - out_exp__h607201, - out_exp__h615837, - out_exp__h635184, - out_exp__h643766, - out_exp__h652950, - out_exp__h661586, - out_exp__h680931, - out_exp__h689513, - out_exp__h698697, - out_exp__h707333, - out_f_exp__h616213, - out_f_exp__h661962, - out_f_exp__h707709, - x__h859104; + _theResult___snd_fst_exp__h598095, + _theResult___snd_fst_exp__h615915, + _theResult___snd_fst_exp__h643844, + _theResult___snd_fst_exp__h661664, + _theResult___snd_fst_exp__h689591, + _theResult___snd_fst_exp__h707411, + din_inc___2_exp__h615946, + din_inc___2_exp__h615970, + din_inc___2_exp__h616000, + din_inc___2_exp__h616024, + din_inc___2_exp__h661695, + din_inc___2_exp__h661719, + din_inc___2_exp__h661749, + din_inc___2_exp__h661773, + din_inc___2_exp__h707442, + din_inc___2_exp__h707466, + din_inc___2_exp__h707496, + din_inc___2_exp__h707520, + f1_exp19754_MINUS_127__q147, + f1_exp__h719754, + f2_exp58748_MINUS_127__q187, + f2_exp__h758748, + f3_exp98052_MINUS_127__q164, + f3_exp__h798052, + out_exp__h589432, + out_exp__h598014, + out_exp__h607198, + out_exp__h615834, + out_exp__h635181, + out_exp__h643763, + out_exp__h652947, + out_exp__h661583, + out_exp__h680928, + out_exp__h689510, + out_exp__h698694, + out_exp__h707330, + out_f_exp__h616210, + out_f_exp__h661959, + out_f_exp__h707706, + x__h859101; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8431_BI_ETC___d19482, NOT_coreFix_aluExe_1_dispToRegQ_first__5760_BI_ETC___d17344, - x__h1007791, - x__h247500; + x__h1007786, + x__h247498; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11237, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8443, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9840, @@ -5591,19 +5591,19 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24324, fetchStage_pipelines_0_first__0337_BIT_167_066_ETC___d20686, fetchStage_pipelines_1_first__0346_BIT_167_162_ETC___d21647, - x__h1003153, - x__h1007765, - x__h1008422, - x__h1009109, - x__h128337, - x__h141481, - x__h185262, - x__h204325, - x__h219296, - x__h871657, - x__h872205, - x__h911634, - x__h912182; + x__h1003148, + x__h1007760, + x__h1008417, + x__h1009104, + x__h128336, + x__h141480, + x__h185261, + x__h204324, + x__h219295, + x__h871654, + x__h872202, + x__h911630, + x__h912178; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__0026_B_ETC___d20170, IF_IF_coreFix_aluExe_0_exeToFinQ_first__0026_B_ETC___d20171, IF_IF_coreFix_aluExe_1_exeToFinQ_first__7888_B_ETC___d18033, @@ -5646,51 +5646,51 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10779, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12176, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9382, - cause_code__h1005062, + cause_code__h1005057, coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d4124, csrf_ddc_reg_read__066_BITS_85_TO_83_146_ULT_c_ETC___d4157, - fflags__h1022678, - r1__read__h860892, - res_fflags__h572590, - res_fflags__h618344, - res_fflags__h664091, + fflags__h1022673, + r1__read__h860889, + res_fflags__h572587, + res_fflags__h618341, + res_fflags__h664088, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19230, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16787, - x__h150517, - x__h153651, - x__h252297, - x__h252309, - x__h252321, - x__h252333, - x__h252345, - x__h252357, - x__h252369, - x__h252381, - x__h252393, - x__h252405, - x__h252417, - x__h252429, - x__h252441, - x__h252453, - x__h252465, - y__h252298, - y__h252310, - y__h252322, - y__h252334, - y__h252346, - y__h252358, - y__h252370, - y__h252382, - y__h252394, - y__h252406, - y__h252418, - y__h252430, - y__h252442, - y__h252454, - y__h252466, - y_avValue_snd_fst__h1022095, - y_avValue_snd_fst__h1022738, - y_avValue_snd_fst__h1022767; + x__h150516, + x__h153650, + x__h252295, + x__h252307, + x__h252319, + x__h252331, + x__h252343, + x__h252355, + x__h252367, + x__h252379, + x__h252391, + x__h252403, + x__h252415, + x__h252427, + x__h252439, + x__h252451, + x__h252463, + y__h252296, + y__h252308, + y__h252320, + y__h252332, + y__h252344, + y__h252356, + y__h252368, + y__h252380, + y__h252392, + y__h252404, + y__h252416, + y__h252428, + y__h252440, + y__h252452, + y__h252464, + y_avValue_snd_fst__h1022090, + y_avValue_snd_fst__h1022733, + y_avValue_snd_fst__h1022762; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8431__ETC___d19479, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5760__ETC___d17341, IF_IF_renameStage_rg_m_halt_req_0364_BIT_4_036_ETC___d21047, @@ -5735,7 +5735,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3404, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3441, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3639, - vm_mode_reg__read__h860268; + vm_mode_reg__read__h860265; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19140, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19141, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__578_ETC___d16697, @@ -5752,54 +5752,54 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3596, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7166, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24257, - _theResult_____2__h519720, - dcsr_cause__h1002568, - next_deqP___1__h519965, - repBound__h1005803, - repBound__h1007856, - repBound__h1008513, - repBound__h240153, - repBound__h241838, - repBound__h251040, - repBound__h251565, - repBound__h862472, - repBound__h865816, - repBound__h865834, - repBound__h871911, - repBound__h872459, - repBound__h903761, - repBound__h906088, - repBound__h906106, - repBound__h911888, - repBound__h912436, - tb__h871908, - tb__h872456, - tb__h911885, - tb__h912433, - tmp_expBotHalf__h1003108, - tmp_expBotHalf__h128292, - tmp_expBotHalf__h141436, - tmp_expBotHalf__h185217, - tmp_expBotHalf__h204280, - tmp_expBotHalf__h219251, - tmp_expBotHalf__h871611, - tmp_expBotHalf__h872159, - tmp_expBotHalf__h911588, - tmp_expBotHalf__h912136, - tmp_expTopHalf__h1003106, - tmp_expTopHalf__h128290, - tmp_expTopHalf__h141434, - tmp_expTopHalf__h185215, - tmp_expTopHalf__h204278, - tmp_expTopHalf__h219249, - tmp_expTopHalf__h871609, - tmp_expTopHalf__h872157, - tmp_expTopHalf__h911586, - tmp_expTopHalf__h912134, - v__h519176, - v__h519371, - x__h526027, - x_decodeInfo_frm__h932727; + _theResult_____2__h519716, + dcsr_cause__h1002563, + next_deqP___1__h519961, + repBound__h1005798, + repBound__h1007851, + repBound__h1008508, + repBound__h240152, + repBound__h241837, + repBound__h251038, + repBound__h251563, + repBound__h862469, + repBound__h865813, + repBound__h865831, + repBound__h871908, + repBound__h872456, + repBound__h903757, + repBound__h906084, + repBound__h906102, + repBound__h911884, + repBound__h912432, + tb__h871905, + tb__h872453, + tb__h911881, + tb__h912429, + tmp_expBotHalf__h1003103, + tmp_expBotHalf__h128291, + tmp_expBotHalf__h141435, + tmp_expBotHalf__h185216, + tmp_expBotHalf__h204279, + tmp_expBotHalf__h219250, + tmp_expBotHalf__h871608, + tmp_expBotHalf__h872156, + tmp_expBotHalf__h911584, + tmp_expBotHalf__h912132, + tmp_expTopHalf__h1003101, + tmp_expTopHalf__h128289, + tmp_expTopHalf__h141433, + tmp_expTopHalf__h185214, + tmp_expTopHalf__h204277, + tmp_expTopHalf__h219248, + tmp_expTopHalf__h871606, + tmp_expTopHalf__h872154, + tmp_expTopHalf__h911582, + tmp_expTopHalf__h912130, + v__h519172, + v__h519367, + x__h526023, + x_decodeInfo_frm__h932722; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19083, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19084, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__578_ETC___d16640, @@ -5815,106 +5815,106 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16645, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3284, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3559, - IF_sfdin06676_BIT_33_THEN_2_ELSE_0__q51, - IF_sfdin26873_BIT_4_THEN_2_ELSE_0__q167, - IF_sfdin34659_BIT_33_THEN_2_ELSE_0__q76, - IF_sfdin48716_BIT_4_THEN_2_ELSE_0__q150, - IF_sfdin52425_BIT_33_THEN_2_ELSE_0__q86, - IF_sfdin80406_BIT_33_THEN_2_ELSE_0__q111, - IF_sfdin87569_BIT_4_THEN_2_ELSE_0__q190, - IF_sfdin88910_BIT_33_THEN_2_ELSE_0__q41, - IF_sfdin98172_BIT_33_THEN_2_ELSE_0__q121, - IF_theResult___snd06809_BIT_33_THEN_2_ELSE_0__q126, - IF_theResult___snd15313_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd17253_BIT_4_THEN_2_ELSE_0__q163, - IF_theResult___snd35658_BIT_4_THEN_2_ELSE_0__q170, - IF_theResult___snd39096_BIT_4_THEN_2_ELSE_0__q146, - IF_theResult___snd43272_BIT_33_THEN_2_ELSE_0__q78, - IF_theResult___snd57501_BIT_4_THEN_2_ELSE_0__q153, - IF_theResult___snd61062_BIT_33_THEN_2_ELSE_0__q91, - IF_theResult___snd77949_BIT_4_THEN_2_ELSE_0__q186, - IF_theResult___snd89019_BIT_33_THEN_2_ELSE_0__q113, - IF_theResult___snd96354_BIT_4_THEN_2_ELSE_0__q193, - IF_theResult___snd97523_BIT_33_THEN_2_ELSE_0__q43, - carry_out__h1003244, - carry_out__h128428, - carry_out__h141572, - carry_out__h185353, - carry_out__h204416, - carry_out__h219387, - carry_out__h871760, - carry_out__h872308, - carry_out__h911737, - carry_out__h912285, + IF_sfdin06673_BIT_33_THEN_2_ELSE_0__q51, + IF_sfdin26870_BIT_4_THEN_2_ELSE_0__q167, + IF_sfdin34656_BIT_33_THEN_2_ELSE_0__q76, + IF_sfdin48713_BIT_4_THEN_2_ELSE_0__q150, + IF_sfdin52422_BIT_33_THEN_2_ELSE_0__q86, + IF_sfdin80403_BIT_33_THEN_2_ELSE_0__q111, + IF_sfdin87566_BIT_4_THEN_2_ELSE_0__q190, + IF_sfdin88907_BIT_33_THEN_2_ELSE_0__q41, + IF_sfdin98169_BIT_33_THEN_2_ELSE_0__q121, + IF_theResult___snd06806_BIT_33_THEN_2_ELSE_0__q126, + IF_theResult___snd15310_BIT_33_THEN_2_ELSE_0__q56, + IF_theResult___snd17250_BIT_4_THEN_2_ELSE_0__q163, + IF_theResult___snd35655_BIT_4_THEN_2_ELSE_0__q170, + IF_theResult___snd39093_BIT_4_THEN_2_ELSE_0__q146, + IF_theResult___snd43269_BIT_33_THEN_2_ELSE_0__q78, + IF_theResult___snd57498_BIT_4_THEN_2_ELSE_0__q153, + IF_theResult___snd61059_BIT_33_THEN_2_ELSE_0__q91, + IF_theResult___snd77946_BIT_4_THEN_2_ELSE_0__q186, + IF_theResult___snd89016_BIT_33_THEN_2_ELSE_0__q113, + IF_theResult___snd96351_BIT_4_THEN_2_ELSE_0__q193, + IF_theResult___snd97520_BIT_33_THEN_2_ELSE_0__q43, + carry_out__h1003239, + carry_out__h128427, + carry_out__h141571, + carry_out__h185352, + carry_out__h204415, + carry_out__h219386, + carry_out__h871757, + carry_out__h872305, + carry_out__h911733, + carry_out__h912281, coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, coreFix_memExe_regToExeQfirst_BITS_222_TO_221__q2, coreFix_memExe_regToExeQfirst_BITS_59_TO_58__q4, - cr_reserved__h871994, - cr_reserved__h911971, - guard__h580815, - guard__h589524, - guard__h598454, - guard__h607290, - guard__h626566, - guard__h635273, - guard__h644203, - guard__h653039, - guard__h672313, - guard__h681020, - guard__h689950, - guard__h698786, - guard__h731184, - guard__h740496, - guard__h749565, - guard__h770037, - guard__h779349, - guard__h788418, - guard__h809341, - guard__h818653, - guard__h827722, - impliedTopBits__h1003246, - impliedTopBits__h128430, - impliedTopBits__h141574, - impliedTopBits__h185355, - impliedTopBits__h204418, - impliedTopBits__h219389, - impliedTopBits__h871762, - impliedTopBits__h872310, - impliedTopBits__h911739, - impliedTopBits__h912287, - len_correction__h1003245, - len_correction__h128429, - len_correction__h141573, - len_correction__h185354, - len_correction__h204417, - len_correction__h219388, - len_correction__h871761, - len_correction__h872309, - len_correction__h911738, - len_correction__h912286, - prv__h1023771, - prv__h1023815, - r1__read_BITS_13_TO_12___h932929, - sbIdx__h153542, - v__h841822, - v__h841832, - v__h842863, - wordIdx__h266096, - x__h1003330, - x__h1018962, - x__h1022926, - x__h128514, - x__h141658, - x__h185439, - x__h204502, - x__h219473, - x__h871847, - x__h872395, - x__h911824, - x__h912372, - y_avValue_snd_snd_snd_fst__h1022105, - y_avValue_snd_snd_snd_fst__h1022748, - y_avValue_snd_snd_snd_fst__h1022777; + cr_reserved__h871991, + cr_reserved__h911967, + guard__h580812, + guard__h589521, + guard__h598451, + guard__h607287, + guard__h626563, + guard__h635270, + guard__h644200, + guard__h653036, + guard__h672310, + guard__h681017, + guard__h689947, + guard__h698783, + guard__h731181, + guard__h740493, + guard__h749562, + guard__h770034, + guard__h779346, + guard__h788415, + guard__h809338, + guard__h818650, + guard__h827719, + impliedTopBits__h1003241, + impliedTopBits__h128429, + impliedTopBits__h141573, + impliedTopBits__h185354, + impliedTopBits__h204417, + impliedTopBits__h219388, + impliedTopBits__h871759, + impliedTopBits__h872307, + impliedTopBits__h911735, + impliedTopBits__h912283, + len_correction__h1003240, + len_correction__h128428, + len_correction__h141572, + len_correction__h185353, + len_correction__h204416, + len_correction__h219387, + len_correction__h871758, + len_correction__h872306, + len_correction__h911734, + len_correction__h912282, + prv__h1023766, + prv__h1023810, + r1__read_BITS_13_TO_12___h932924, + sbIdx__h153541, + v__h841819, + v__h841829, + v__h842860, + wordIdx__h266094, + x__h1003325, + x__h1018957, + x__h1022921, + x__h128513, + x__h141657, + x__h185438, + x__h204501, + x__h219472, + x__h871844, + x__h872392, + x__h911820, + x__h912368, + y_avValue_snd_snd_snd_fst__h1022100, + y_avValue_snd_snd_snd_fst__h1022743, + y_avValue_snd_snd_snd_fst__h1022772; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10662, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10712, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12059, @@ -6641,12 +6641,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h530497, - _theResult_____2__h537590, - _theResult_____2__h548225, - _theResult_____2__h562058, - _theResult_____2__h565837, - cause_interrupt__h1003522, + _theResult_____2__h530493, + _theResult_____2__h537586, + _theResult_____2__h548221, + _theResult_____2__h562054, + _theResult_____2__h565833, + cause_interrupt__h1003517, commitStage_commitTrap_2410_BITS_44_TO_43_2608_ETC___d22648, commitStage_commitTrap_2410_BITS_44_TO_43_2608_ETC___d22655, commitStage_commitTrap_2410_BITS_44_TO_43_2608_ETC___d22760, @@ -7045,8 +7045,8 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__652_BITS_264_T_ETC___d3724, coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d4114, coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23186, - cr_flags__h871993, - cr_flags__h911970, + cr_flags__h871990, + cr_flags__h911966, csrf_ddc_reg_read__066_BITS_13_TO_11_141_ULT_c_ETC___d4145, csrf_ddc_reg_read__066_BITS_27_TO_25_143_ULT_c_ETC___d4144, csrf_ddc_reg_read__066_BITS_85_TO_83_146_ULT_c_ETC___d4147, @@ -7088,27 +7088,27 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0337_BIT_69_0366_ETC___d21815, fetchStage_pipelines_1_first__0346_BITS_267_TO_ETC___d21958, fetchStage_pipelines_1_first__0346_BITS_272_TO_ETC___d21969, - guard__h599052, - guard__h644801, - guard__h690548, - guard__h741094, - guard__h779947, - guard__h819251, - idx__h976269, - k__h951774, + guard__h599049, + guard__h644798, + guard__h690545, + guard__h741091, + guard__h779944, + guard__h819248, + idx__h976264, + k__h951769, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20749, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21141, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21161, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22078, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22080, - next_deqP___1__h530742, - next_deqP___1__h538020, - next_deqP___1__h548655, - next_deqP___1__h562303, - next_deqP___1__h566082, - r1__read_BIT_20___h933435, - r__h859151, - r__h860638, + next_deqP___1__h530738, + next_deqP___1__h538016, + next_deqP___1__h548651, + next_deqP___1__h562299, + next_deqP___1__h566078, + r1__read_BIT_20___h933430, + r__h859148, + r__h860635, regRenamingTable_RDY_rename_0_getRename__1098__ETC___d21109, regRenamingTable_RDY_rename_0_getRename__1098__ETC___d21924, regRenamingTable_rename_0_canRename__1238_AND__ETC___d21262, @@ -7157,20 +7157,20 @@ module mkCore(CLK, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3616, rg_core_run_state_read__0752_EQ_2_0753_AND_NOT_ETC___d23856, rob_enqPort_1_canEnq__1704_AND_epochManager_ch_ETC___d21709, - v__h521196, - v__h521576, - v__h536915, - v__h537110, - v__h539364, - v__h539559, - v__h560384, - v__h560579, - v__h564163, - v__h564358, - x__h242975, - x__h244132, - x__h257738, - x__h841166; + v__h521192, + v__h521572, + v__h536911, + v__h537106, + v__h539360, + v__h539555, + v__h560380, + v__h560575, + v__h564159, + v__h564354, + x__h242974, + x__h244131, + x__h257736, + x__h841163; // action method coreReq_start assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; @@ -11262,15 +11262,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h997804, + addr__h997799, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q324, rob$deqPort_0_deq_data[501:470] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1022701 ; + commitStage_rg_serial_num + y__h1022696 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h951774 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h951769 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0337_BITS_26_ETC___d22085) ? { fetchStage$pipelines_0_first[272:268], IF_fetchStage_pipelines_0_first__0337_BITS_267_ETC___d20463, @@ -11288,7 +11288,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h976130, + renaming_spec_bits__h976125, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11396,7 +11396,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h505382 } ; + x__h505379 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7106 } ; @@ -11406,7 +11406,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h509900, + addr__h509897, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7214 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11423,12 +11423,12 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : coreFix_memExe_reqLrScAmoQ_data_0_rl ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h150517, - addr__h149965, + { x__h150516, + addr__h149964, 158'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h153651, - addr__h153541, + { x__h153650, + addr__h153540, 158'h32AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 = { 1'd1, @@ -11438,7 +11438,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h513469, + resp_addr__h513466, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11446,8 +11446,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1023815, - prv__h1023815 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1023810, + prv__h1023810 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11516,39 +11516,39 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4856, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4893 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h921139, - new_pc__h918535, + { x__h921134, + new_pc__h918530, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h921139, - new_pc__h918535, + { x__h921134, + new_pc__h918530, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h886260, - new_pc__h879225, + { x__h886256, + new_pc__h879221, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h886260, - new_pc__h879225, + { x__h886256, + new_pc__h879221, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1022678 ; + csrf_fflags_reg | fflags__h1022673 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__2403_BIT_288_3077_T_ETC___d23171 == 6'd1) ? @@ -11597,9 +11597,9 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1020084 + 64'd1 ; + n__read__h1020079 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1020084 + { 62'd0, x__h1022926 } ; + n__read__h1020079 + { 62'd0, x__h1022921 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2403_BIT_288_3077_T_ETC___d23171 == @@ -11607,11 +11607,11 @@ module mkCore(CLK, MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h1005244 or trap_val__h1005091) + always@(commitStage_commitTrap or trap_val__h1005239 or trap_val__h1005086) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h1005244; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h1005091; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h1005239; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h1005086; default: MUX_csrf_mtval_csr$write_1__VAL_2 = 64'd0; endcase end @@ -11633,7 +11633,7 @@ module mkCore(CLK, 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1018962 : + x__h1018957 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 ? @@ -11642,29 +11642,29 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h1002568, + dcsr_cause__h1002563, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = { csrf_rg_dpc[152], - pointer__h1016884, - x__h1016908[13:0], + pointer__h1016879, + x__h1016903[13:0], csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = { commitStage_commitTrap[237], - pc_address__h1002943, - pc_addrBits__h1002944, + pc_address__h1002938, + pc_addrBits__h1002939, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22727, - x__h1003313, - x__h1003333 } ; + x__h1003308, + x__h1003328 } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { csrf_rg_dpc[152], - pointer__h1036714, - x__h1036737[13:0], + pointer__h1036708, + x__h1036731[13:0], csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = @@ -11675,7 +11675,7 @@ module mkCore(CLK, 6'd19) && MUX_csrf_rg_tselect$write_1__VAL_2[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1026352 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1026346 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11691,14 +11691,14 @@ module mkCore(CLK, IF_IF_csrf_prv_reg_read__0367_ULE_1_2761_AND_I_ETC___d23053[14:3], ~IF_IF_csrf_prv_reg_read__0367_ULE_1_2761_AND_I_ETC___d23053[2], IF_IF_csrf_prv_reg_read__0367_ULE_1_2761_AND_I_ETC___d23053[1:0], - thin_address__h1007586 } ; + thin_address__h1007581 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1018619 or v__h1018941 or v__h1019394) + next_pc__h1018614 or v__h1018936 or v__h1019389) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1018941; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1019394; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1018619; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1018936; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1019389; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1018614; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11745,38 +11745,38 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h571697, - res_addrBits__h571698, + res_address__h571693, + res_addrBits__h571694, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, - res_address__h572549, - res_addrBits__h572550, + res_address__h572546, + res_addrBits__h572547, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_3 = { 1'd0, - res_address__h618306, - res_addrBits__h618307, + res_address__h618303, + res_addrBits__h618304, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_4 = { 1'd0, - res_address__h664053, - res_addrBits__h664054, + res_address__h664050, + res_addrBits__h664051, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_5 = { 1'd0, - res_address__h709939, - res_addrBits__h709940, + res_address__h709936, + res_addrBits__h709937, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_6 = { 1'd0, - res_address__h710885, - res_addrBits__h710886, + res_address__h710882, + res_addrBits__h710883, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_3_wr_2__VAL_1 = { coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h127818, - res_addrBits__h127819, + res_address__h127817, + res_addrBits__h127818, coreFix_memExe_respLrScAmoQ_data_0[127:112], coreFix_memExe_respLrScAmoQ_data_0[109], coreFix_memExe_respLrScAmoQ_data_0[111:110], @@ -11784,8 +11784,8 @@ module mkCore(CLK, IF_INV_coreFix_memExe_respLrScAmoQ_data_0_235__ETC___d1275 } ; assign MUX_rf$write_3_wr_2__VAL_2 = { mmio_dataRespQ_data_0[128], - res_address__h140958, - res_addrBits__h140959, + res_address__h140957, + res_addrBits__h140958, mmio_dataRespQ_data_0[127:112], mmio_dataRespQ_data_0[109], mmio_dataRespQ_data_0[111:110], @@ -11794,27 +11794,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h180641, - res_addrBits__h180642, - x__h185142[127:112], - x__h185142[109], - x__h185142[111:110], - ~x__h185142[108:90], + res_address__h180640, + res_addrBits__h180641, + x__h185141[127:112], + x__h185141[109], + x__h185141[111:110], + ~x__h185141[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h199718, - res_addrBits__h199719, - x__h201306[127:112], - x__h201306[109], - x__h201306[111:110], - ~x__h201306[108:90], + res_address__h199717, + res_addrBits__h199718, + x__h201305[127:112], + x__h201305[109], + x__h201305[111:110], + ~x__h201305[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h218882, - res_addrBits__h218883, + res_address__h218881, + res_addrBits__h218882, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -11822,13 +11822,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1025079, - data_addrBits__h1025080, + data_address__h1025073, + data_addrBits__h1025074, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1025933, - data_addrBits__h1025934, + data_address__h1025927, + data_addrBits__h1025928, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[590:462], @@ -11890,15 +11890,15 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h572590 ; + res_fflags__h572587 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h618344 ; + res_fflags__h618341 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h664091 ; + res_fflags__h664088 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12326,8 +12326,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h842863 : - v__h841822 ; + v__h842860 : + v__h841819 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -12464,7 +12464,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h519720 ; + _theResult_____2__h519716 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12483,7 +12483,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h519176 ; + v__h519172 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12525,7 +12525,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h530497 ; + _theResult_____2__h530493 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12544,7 +12544,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h521196 ; + v__h521192 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12641,7 +12641,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h537590 ; + _theResult_____2__h537586 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12657,7 +12657,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h536915 ; + v__h536911 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12677,7 +12677,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h539726, + { x_addr__h539722, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12704,7 +12704,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h548225 ; + _theResult_____2__h548221 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12723,7 +12723,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h539364 ; + v__h539360 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12799,7 +12799,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h565837 ; + _theResult_____2__h565833 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12814,7 +12814,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h564163 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h564159 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12855,7 +12855,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h562058 ; + _theResult_____2__h562054 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12870,7 +12870,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h560384 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h560380 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13230,13 +13230,13 @@ module mkCore(CLK, always@(MUX_csrf_mcause_interrupt_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h1003524 or + cause_code__h1003519 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_interrupt_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h1003524; + csrf_mcause_code_reg$D_IN = cause_code__h1003519; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; @@ -13256,14 +13256,14 @@ module mkCore(CLK, always@(MUX_csrf_mcause_interrupt_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_interrupt__h1003522 or + cause_interrupt__h1003517 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_interrupt_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[63]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h1003522; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h1003517; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; @@ -13439,7 +13439,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3035 : - n__read__h1020084 ; + n__read__h1020079 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13790,13 +13790,13 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h1003524 or + cause_code__h1003519 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h1003524; + csrf_scause_code_reg$D_IN = cause_code__h1003519; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; @@ -13816,14 +13816,14 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_interrupt__h1003522 or + cause_interrupt__h1003517 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[63]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h1003522; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h1003517; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; @@ -14990,7 +14990,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h951774 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h951769 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0337_BITS_26_ETC___d22085) ? { fetchStage$pipelines_0_first[272:268], IF_fetchStage_pipelines_0_first__0337_BITS_267_ETC___d20463, @@ -15008,7 +15008,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h976130, + renaming_spec_bits__h976125, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15486,12 +15486,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h841140, - b__h840604 == 64'd0, - a__h840603, + { x__h841137, + b__h840601 == 64'd0, + a__h840600, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h841166, - a__h840603[63], + x__h841163, + a__h840600[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -15506,8 +15506,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h841152 : - b__h840604 ; + _theResult___snd__h841149 : + b__h840601 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && @@ -15520,7 +15520,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h841752, + { x__h841749, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -15601,9 +15601,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h719279, - x__h719280, - x__h719281, + x__h719276, + x__h719277, + x__h719278, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20278 ; @@ -15655,7 +15655,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0346_BITS_267_ETC___d21424, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h976130, + renaming_spec_bits__h976125, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15813,7 +15813,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h505382 ; + x__h505379 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0) ? @@ -16245,7 +16245,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1238_AND__ETC___d22165) ? specTagManager$currentSpecBits : - renaming_spec_bits__h976130 ; + renaming_spec_bits__h976125 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1238_AND__ETC___d22174) ? @@ -16265,7 +16265,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1238_AND__ETC___d22174) ? specTagManager$currentSpecBits : - renaming_spec_bits__h976130 ; + renaming_spec_bits__h976125 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16294,8 +16294,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h215234 : - t__h217587 ; + t__h215233 : + t__h217586 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16348,7 +16348,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__652_BIT_102_ETC___d4018[2], IF_coreFix_memExe_regToExeQ_first__652_BIT_102_ETC___d4018[1:0], coreFix_memExe_regToExeQ$first[217:154] } : - { pointer__h245459[3:0] == 4'd0 && + { pointer__h245458[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16518,7 +16518,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[238], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h976130, + renaming_spec_bits__h976125, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16931,9 +16931,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h879225 or + new_pc__h879221 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h918535 or + new_pc__h918530 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -16944,9 +16944,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h879225; + fetchStage$redirect_pc = new_pc__h879221; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h918535; + fetchStage$redirect_pc = new_pc__h918530; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -17136,7 +17136,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h976130 ; + renaming_spec_bits__h976125 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17413,7 +17413,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0346_BITS_264_ETC___d22313, IF_NOT_fetchStage_pipelines_1_first__0346_BITS_ETC___d22384, 7'd32, - renaming_spec_bits__h976130 } ; + renaming_spec_bits__h976125 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17497,29 +17497,29 @@ module mkCore(CLK, always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or - data__h572031 or + data__h572028 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or - data__h617791 or + data__h617788 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or - data__h663538 or + data__h663535 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or - data__h709454 or - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h710400) + data__h709451 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h710397) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h572031; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h572028; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h617791; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h617788; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h663538; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h663535; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h709454; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h709451; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h710400; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h710397; default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -17976,11 +17976,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h860638 }), + .amoExec_current({ 128'd0, r__h860635 }), .amoExec_inpt({ 97'd0, x__h65608 }), .amoExec(amoExec___d775)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h266096), + .amoExec_wordIdx(wordIdx__h266094), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4856, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4863, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4869 } }), @@ -17997,12 +17997,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h932727, - r1__read_BITS_13_TO_12___h932929 != + .checkForException_csrState({ x_decodeInfo_frm__h932722, + r1__read_BITS_13_TO_12___h932924 != 2'd0, - { prv__h1023771, + { prv__h1023766, csrf_tvm_reg, - { r1__read_BIT_20___h933435, + { r1__read_BIT_20___h933430, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18028,12 +18028,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h932727, - r1__read_BITS_13_TO_12___h932929 != + .checkForException_csrState({ x_decodeInfo_frm__h932722, + r1__read_BITS_13_TO_12___h932924 != 2'd0, - { prv__h1023771, + { prv__h1023766, csrf_tvm_reg, - { r1__read_BIT_20___h933435, + { r1__read_BIT_20___h933430, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18044,14 +18044,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h970672), + .checkForException_pcc(pc__h970667), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21674)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[383:221]), .capChecks_b(coreFix_memExe_regToExeQ$first[220:58]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h251565, + repBound__h251563, { csrf_ddc_reg_read__066_BITS_27_TO_25_143_ULT_c_ETC___d4144, csrf_ddc_reg_read__066_BITS_13_TO_11_141_ULT_c_ETC___d4145, csrf_ddc_reg_read__066_BITS_85_TO_83_146_ULT_c_ETC___d4157 } }), @@ -18062,20 +18062,20 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[220:58]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h251565, + repBound__h251563, { csrf_ddc_reg_read__066_BITS_27_TO_25_143_ULT_c_ETC___d4144, csrf_ddc_reg_read__066_BITS_13_TO_11_141_ULT_c_ETC___d4145, csrf_ddc_reg_read__066_BITS_85_TO_83_146_ULT_c_ETC___d4157 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h245658), - .prepareBoundsCheck_size(x__h252297 + - y__h252298), + .prepareBoundsCheck_vaddr(tmpAddr__h245657), + .prepareBoundsCheck_size(x__h252295 + + y__h252296), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[57:12]), .prepareBoundsCheck(prepareBoundsCheck___d4245)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q278, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h719373), - .execFpuSimple_rVal2(rVal2__h719374), + .execFpuSimple_rVal1(rVal1__h719370), + .execFpuSimple_rVal2(rVal2__h719371), .execFpuSimple(execFpuSimple___d15295)); module_basicExec instance_basicExec_8(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[821:817], CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280, @@ -18088,24 +18088,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h871442, - cr_addrBits__h871443, + { cr_address__h871439, + cr_addrBits__h871440, { coreFix_aluExe_1_regToExeQ$first[305:290], { coreFix_aluExe_1_regToExeQ$first[287], coreFix_aluExe_1_regToExeQ$first[289:288] }, INV_coreFix_aluExe_1_regToExeQ_first__7365_BIT_ETC___d17669 } }, - repBound__h871911, + repBound__h871908, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17676, IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17677, IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17689 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h871990, - cr_addrBits__h871991, + { cr_address__h871987, + cr_addrBits__h871988, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h871993, - cr_reserved__h871994 }, + { cr_flags__h871990, + cr_reserved__h871991 }, INV_coreFix_aluExe_1_regToExeQ_first__7365_BIT_ETC___d17733 } }, - repBound__h872459, + repBound__h872456, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17740, IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17741, IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17753 } }), @@ -18122,24 +18122,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h911419, - cr_addrBits__h911420, + { cr_address__h911415, + cr_addrBits__h911416, { coreFix_aluExe_0_regToExeQ$first[305:290], { coreFix_aluExe_0_regToExeQ$first[287], coreFix_aluExe_0_regToExeQ$first[289:288] }, INV_coreFix_aluExe_0_regToExeQ_first__9503_BIT_ETC___d19807 } }, - repBound__h911888, + repBound__h911884, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19814, IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19815, IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19827 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h911967, - cr_addrBits__h911968, + { cr_address__h911963, + cr_addrBits__h911964, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h911970, - cr_reserved__h911971 }, + { cr_flags__h911966, + cr_reserved__h911967 }, INV_coreFix_aluExe_0_regToExeQ_first__9503_BIT_ETC___d19871 } }, - repBound__h912436, + repBound__h912432, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19878, IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19879, IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19891 } }), @@ -18147,1191 +18147,1191 @@ module mkCore(CLK, .basicExec(basicExec___d19895)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11239 ? - _theResult___snd__h680475 : - _theResult____h672303 ; + _theResult___snd__h680472 : + _theResult____h672300 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8445 ? - _theResult___snd__h588979 : - _theResult____h580805 ; + _theResult___snd__h588976 : + _theResult____h580802 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9842 ? - _theResult___snd__h634728 : - _theResult____h626556 ; + _theResult___snd__h634725 : + _theResult____h626553 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13136 ? - _theResult___snd__h748785 : - _theResult____h740486 ; + _theResult___snd__h748782 : + _theResult____h740483 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13851 ? - _theResult___snd__h826942 : - _theResult____h818643 ; + _theResult___snd__h826939 : + _theResult____h818640 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14621 ? - _theResult___snd__h787638 : - _theResult____h779339 ; + _theResult___snd__h787635 : + _theResult____h779336 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q120 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11790 ? - _theResult___snd__h698241 : - _theResult____h689940 ; + _theResult___snd__h698238 : + _theResult____h689937 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q50 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8996 ? - _theResult___snd__h606745 : - _theResult____h598444 ; + _theResult___snd__h606742 : + _theResult____h598441 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q85 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10393 ? - _theResult___snd__h652494 : - _theResult____h644193 ; + _theResult___snd__h652491 : + _theResult____h644190 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12824 ? - _theResult___snd__h739134 : + _theResult___snd__h739131 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13186 ? - _theResult___snd__h739134 : - _theResult___snd__h757539 ; + _theResult___snd__h739131 : + _theResult___snd__h757536 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13554 ? - _theResult___snd__h817291 : + _theResult___snd__h817288 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13901 ? - _theResult___snd__h817291 : - _theResult___snd__h835696 ; + _theResult___snd__h817288 : + _theResult___snd__h835693 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14324 ? - _theResult___snd__h777987 : + _theResult___snd__h777984 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14671 ? - _theResult___snd__h777987 : - _theResult___snd__h796392 ; + _theResult___snd__h777984 : + _theResult___snd__h796389 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q112 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11470 ? - _theResult___snd__h689057 : + _theResult___snd__h689054 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q125 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11863 ? - _theResult___snd__h689057 : - _theResult___snd__h706847 ; + _theResult___snd__h689054 : + _theResult___snd__h706844 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q42 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8676 ? - _theResult___snd__h597561 : + _theResult___snd__h597558 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q55 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9069 ? - _theResult___snd__h597561 : - _theResult___snd__h615351 ; + _theResult___snd__h597558 : + _theResult___snd__h615348 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q77 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10073 ? - _theResult___snd__h643310 : + _theResult___snd__h643307 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q90 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10466 ? - _theResult___snd__h643310 : - _theResult___snd__h661100 ; + _theResult___snd__h643307 : + _theResult___snd__h661097 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10662 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9606 ? - ((_theResult___fst_exp__h634665 == 8'd255) ? + ((_theResult___fst_exp__h634662 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647) : - ((_theResult___fst_exp__h643321 == 8'd255) ? + ((_theResult___fst_exp__h643318 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10660) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10712 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9606 ? - ((_theResult___fst_exp__h634665 == 8'd255) ? + ((_theResult___fst_exp__h634662 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10703) : - ((_theResult___fst_exp__h643321 == 8'd255) ? + ((_theResult___fst_exp__h643318 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10710) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12059 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11003 ? - ((_theResult___fst_exp__h680412 == 8'd255) ? + ((_theResult___fst_exp__h680409 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044) : - ((_theResult___fst_exp__h689068 == 8'd255) ? + ((_theResult___fst_exp__h689065 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12057) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12109 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11003 ? - ((_theResult___fst_exp__h680412 == 8'd255) ? + ((_theResult___fst_exp__h680409 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12100) : - ((_theResult___fst_exp__h689068 == 8'd255) ? + ((_theResult___fst_exp__h689065 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12107) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9265 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8209 ? - ((_theResult___fst_exp__h588916 == 8'd255) ? + ((_theResult___fst_exp__h588913 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250) : - ((_theResult___fst_exp__h597572 == 8'd255) ? + ((_theResult___fst_exp__h597569 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9263) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9315 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8209 ? - ((_theResult___fst_exp__h588916 == 8'd255) ? + ((_theResult___fst_exp__h588913 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9306) : - ((_theResult___fst_exp__h597572 == 8'd255) ? + ((_theResult___fst_exp__h597569 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9313) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11237 = - (_theResult____h672303[56] ? + (_theResult____h672300[56] ? 6'd0 : - (_theResult____h672303[55] ? + (_theResult____h672300[55] ? 6'd1 : - (_theResult____h672303[54] ? + (_theResult____h672300[54] ? 6'd2 : - (_theResult____h672303[53] ? + (_theResult____h672300[53] ? 6'd3 : - (_theResult____h672303[52] ? + (_theResult____h672300[52] ? 6'd4 : - (_theResult____h672303[51] ? + (_theResult____h672300[51] ? 6'd5 : - (_theResult____h672303[50] ? + (_theResult____h672300[50] ? 6'd6 : - (_theResult____h672303[49] ? + (_theResult____h672300[49] ? 6'd7 : - (_theResult____h672303[48] ? + (_theResult____h672300[48] ? 6'd8 : - (_theResult____h672303[47] ? + (_theResult____h672300[47] ? 6'd9 : - (_theResult____h672303[46] ? + (_theResult____h672300[46] ? 6'd10 : - (_theResult____h672303[45] ? + (_theResult____h672300[45] ? 6'd11 : - (_theResult____h672303[44] ? + (_theResult____h672300[44] ? 6'd12 : - (_theResult____h672303[43] ? + (_theResult____h672300[43] ? 6'd13 : - (_theResult____h672303[42] ? + (_theResult____h672300[42] ? 6'd14 : - (_theResult____h672303[41] ? + (_theResult____h672300[41] ? 6'd15 : - (_theResult____h672303[40] ? + (_theResult____h672300[40] ? 6'd16 : - (_theResult____h672303[39] ? + (_theResult____h672300[39] ? 6'd17 : - (_theResult____h672303[38] ? + (_theResult____h672300[38] ? 6'd18 : - (_theResult____h672303[37] ? + (_theResult____h672300[37] ? 6'd19 : - (_theResult____h672303[36] ? + (_theResult____h672300[36] ? 6'd20 : - (_theResult____h672303[35] ? + (_theResult____h672300[35] ? 6'd21 : - (_theResult____h672303[34] ? + (_theResult____h672300[34] ? 6'd22 : - (_theResult____h672303[33] ? + (_theResult____h672300[33] ? 6'd23 : - (_theResult____h672303[32] ? + (_theResult____h672300[32] ? 6'd24 : - (_theResult____h672303[31] ? + (_theResult____h672300[31] ? 6'd25 : - (_theResult____h672303[30] ? + (_theResult____h672300[30] ? 6'd26 : - (_theResult____h672303[29] ? + (_theResult____h672300[29] ? 6'd27 : - (_theResult____h672303[28] ? + (_theResult____h672300[28] ? 6'd28 : - (_theResult____h672303[27] ? + (_theResult____h672300[27] ? 6'd29 : - (_theResult____h672303[26] ? + (_theResult____h672300[26] ? 6'd30 : - (_theResult____h672303[25] ? + (_theResult____h672300[25] ? 6'd31 : - (_theResult____h672303[24] ? + (_theResult____h672300[24] ? 6'd32 : - (_theResult____h672303[23] ? + (_theResult____h672300[23] ? 6'd33 : - (_theResult____h672303[22] ? + (_theResult____h672300[22] ? 6'd34 : - (_theResult____h672303[21] ? + (_theResult____h672300[21] ? 6'd35 : - (_theResult____h672303[20] ? + (_theResult____h672300[20] ? 6'd36 : - (_theResult____h672303[19] ? + (_theResult____h672300[19] ? 6'd37 : - (_theResult____h672303[18] ? + (_theResult____h672300[18] ? 6'd38 : - (_theResult____h672303[17] ? + (_theResult____h672300[17] ? 6'd39 : - (_theResult____h672303[16] ? + (_theResult____h672300[16] ? 6'd40 : - (_theResult____h672303[15] ? + (_theResult____h672300[15] ? 6'd41 : - (_theResult____h672303[14] ? + (_theResult____h672300[14] ? 6'd42 : - (_theResult____h672303[13] ? + (_theResult____h672300[13] ? 6'd43 : - (_theResult____h672303[12] ? + (_theResult____h672300[12] ? 6'd44 : - (_theResult____h672303[11] ? + (_theResult____h672300[11] ? 6'd45 : - (_theResult____h672303[10] ? + (_theResult____h672300[10] ? 6'd46 : - (_theResult____h672303[9] ? + (_theResult____h672300[9] ? 6'd47 : - (_theResult____h672303[8] ? + (_theResult____h672300[8] ? 6'd48 : - (_theResult____h672303[7] ? + (_theResult____h672300[7] ? 6'd49 : - (_theResult____h672303[6] ? + (_theResult____h672300[6] ? 6'd50 : - (_theResult____h672303[5] ? + (_theResult____h672300[5] ? 6'd51 : - (_theResult____h672303[4] ? + (_theResult____h672300[4] ? 6'd52 : - (_theResult____h672303[3] ? + (_theResult____h672300[3] ? 6'd53 : - (_theResult____h672303[2] ? + (_theResult____h672300[2] ? 6'd54 : - (_theResult____h672303[1] ? + (_theResult____h672300[1] ? 6'd55 : - (_theResult____h672303[0] ? + (_theResult____h672300[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8443 = - (_theResult____h580805[56] ? + (_theResult____h580802[56] ? 6'd0 : - (_theResult____h580805[55] ? + (_theResult____h580802[55] ? 6'd1 : - (_theResult____h580805[54] ? + (_theResult____h580802[54] ? 6'd2 : - (_theResult____h580805[53] ? + (_theResult____h580802[53] ? 6'd3 : - (_theResult____h580805[52] ? + (_theResult____h580802[52] ? 6'd4 : - (_theResult____h580805[51] ? + (_theResult____h580802[51] ? 6'd5 : - (_theResult____h580805[50] ? + (_theResult____h580802[50] ? 6'd6 : - (_theResult____h580805[49] ? + (_theResult____h580802[49] ? 6'd7 : - (_theResult____h580805[48] ? + (_theResult____h580802[48] ? 6'd8 : - (_theResult____h580805[47] ? + (_theResult____h580802[47] ? 6'd9 : - (_theResult____h580805[46] ? + (_theResult____h580802[46] ? 6'd10 : - (_theResult____h580805[45] ? + (_theResult____h580802[45] ? 6'd11 : - (_theResult____h580805[44] ? + (_theResult____h580802[44] ? 6'd12 : - (_theResult____h580805[43] ? + (_theResult____h580802[43] ? 6'd13 : - (_theResult____h580805[42] ? + (_theResult____h580802[42] ? 6'd14 : - (_theResult____h580805[41] ? + (_theResult____h580802[41] ? 6'd15 : - (_theResult____h580805[40] ? + (_theResult____h580802[40] ? 6'd16 : - (_theResult____h580805[39] ? + (_theResult____h580802[39] ? 6'd17 : - (_theResult____h580805[38] ? + (_theResult____h580802[38] ? 6'd18 : - (_theResult____h580805[37] ? + (_theResult____h580802[37] ? 6'd19 : - (_theResult____h580805[36] ? + (_theResult____h580802[36] ? 6'd20 : - (_theResult____h580805[35] ? + (_theResult____h580802[35] ? 6'd21 : - (_theResult____h580805[34] ? + (_theResult____h580802[34] ? 6'd22 : - (_theResult____h580805[33] ? + (_theResult____h580802[33] ? 6'd23 : - (_theResult____h580805[32] ? + (_theResult____h580802[32] ? 6'd24 : - (_theResult____h580805[31] ? + (_theResult____h580802[31] ? 6'd25 : - (_theResult____h580805[30] ? + (_theResult____h580802[30] ? 6'd26 : - (_theResult____h580805[29] ? + (_theResult____h580802[29] ? 6'd27 : - (_theResult____h580805[28] ? + (_theResult____h580802[28] ? 6'd28 : - (_theResult____h580805[27] ? + (_theResult____h580802[27] ? 6'd29 : - (_theResult____h580805[26] ? + (_theResult____h580802[26] ? 6'd30 : - (_theResult____h580805[25] ? + (_theResult____h580802[25] ? 6'd31 : - (_theResult____h580805[24] ? + (_theResult____h580802[24] ? 6'd32 : - (_theResult____h580805[23] ? + (_theResult____h580802[23] ? 6'd33 : - (_theResult____h580805[22] ? + (_theResult____h580802[22] ? 6'd34 : - (_theResult____h580805[21] ? + (_theResult____h580802[21] ? 6'd35 : - (_theResult____h580805[20] ? + (_theResult____h580802[20] ? 6'd36 : - (_theResult____h580805[19] ? + (_theResult____h580802[19] ? 6'd37 : - (_theResult____h580805[18] ? + (_theResult____h580802[18] ? 6'd38 : - (_theResult____h580805[17] ? + (_theResult____h580802[17] ? 6'd39 : - (_theResult____h580805[16] ? + (_theResult____h580802[16] ? 6'd40 : - (_theResult____h580805[15] ? + (_theResult____h580802[15] ? 6'd41 : - (_theResult____h580805[14] ? + (_theResult____h580802[14] ? 6'd42 : - (_theResult____h580805[13] ? + (_theResult____h580802[13] ? 6'd43 : - (_theResult____h580805[12] ? + (_theResult____h580802[12] ? 6'd44 : - (_theResult____h580805[11] ? + (_theResult____h580802[11] ? 6'd45 : - (_theResult____h580805[10] ? + (_theResult____h580802[10] ? 6'd46 : - (_theResult____h580805[9] ? + (_theResult____h580802[9] ? 6'd47 : - (_theResult____h580805[8] ? + (_theResult____h580802[8] ? 6'd48 : - (_theResult____h580805[7] ? + (_theResult____h580802[7] ? 6'd49 : - (_theResult____h580805[6] ? + (_theResult____h580802[6] ? 6'd50 : - (_theResult____h580805[5] ? + (_theResult____h580802[5] ? 6'd51 : - (_theResult____h580805[4] ? + (_theResult____h580802[4] ? 6'd52 : - (_theResult____h580805[3] ? + (_theResult____h580802[3] ? 6'd53 : - (_theResult____h580805[2] ? + (_theResult____h580802[2] ? 6'd54 : - (_theResult____h580805[1] ? + (_theResult____h580802[1] ? 6'd55 : - (_theResult____h580805[0] ? + (_theResult____h580802[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9840 = - (_theResult____h626556[56] ? + (_theResult____h626553[56] ? 6'd0 : - (_theResult____h626556[55] ? + (_theResult____h626553[55] ? 6'd1 : - (_theResult____h626556[54] ? + (_theResult____h626553[54] ? 6'd2 : - (_theResult____h626556[53] ? + (_theResult____h626553[53] ? 6'd3 : - (_theResult____h626556[52] ? + (_theResult____h626553[52] ? 6'd4 : - (_theResult____h626556[51] ? + (_theResult____h626553[51] ? 6'd5 : - (_theResult____h626556[50] ? + (_theResult____h626553[50] ? 6'd6 : - (_theResult____h626556[49] ? + (_theResult____h626553[49] ? 6'd7 : - (_theResult____h626556[48] ? + (_theResult____h626553[48] ? 6'd8 : - (_theResult____h626556[47] ? + (_theResult____h626553[47] ? 6'd9 : - (_theResult____h626556[46] ? + (_theResult____h626553[46] ? 6'd10 : - (_theResult____h626556[45] ? + (_theResult____h626553[45] ? 6'd11 : - (_theResult____h626556[44] ? + (_theResult____h626553[44] ? 6'd12 : - (_theResult____h626556[43] ? + (_theResult____h626553[43] ? 6'd13 : - (_theResult____h626556[42] ? + (_theResult____h626553[42] ? 6'd14 : - (_theResult____h626556[41] ? + (_theResult____h626553[41] ? 6'd15 : - (_theResult____h626556[40] ? + (_theResult____h626553[40] ? 6'd16 : - (_theResult____h626556[39] ? + (_theResult____h626553[39] ? 6'd17 : - (_theResult____h626556[38] ? + (_theResult____h626553[38] ? 6'd18 : - (_theResult____h626556[37] ? + (_theResult____h626553[37] ? 6'd19 : - (_theResult____h626556[36] ? + (_theResult____h626553[36] ? 6'd20 : - (_theResult____h626556[35] ? + (_theResult____h626553[35] ? 6'd21 : - (_theResult____h626556[34] ? + (_theResult____h626553[34] ? 6'd22 : - (_theResult____h626556[33] ? + (_theResult____h626553[33] ? 6'd23 : - (_theResult____h626556[32] ? + (_theResult____h626553[32] ? 6'd24 : - (_theResult____h626556[31] ? + (_theResult____h626553[31] ? 6'd25 : - (_theResult____h626556[30] ? + (_theResult____h626553[30] ? 6'd26 : - (_theResult____h626556[29] ? + (_theResult____h626553[29] ? 6'd27 : - (_theResult____h626556[28] ? + (_theResult____h626553[28] ? 6'd28 : - (_theResult____h626556[27] ? + (_theResult____h626553[27] ? 6'd29 : - (_theResult____h626556[26] ? + (_theResult____h626553[26] ? 6'd30 : - (_theResult____h626556[25] ? + (_theResult____h626553[25] ? 6'd31 : - (_theResult____h626556[24] ? + (_theResult____h626553[24] ? 6'd32 : - (_theResult____h626556[23] ? + (_theResult____h626553[23] ? 6'd33 : - (_theResult____h626556[22] ? + (_theResult____h626553[22] ? 6'd34 : - (_theResult____h626556[21] ? + (_theResult____h626553[21] ? 6'd35 : - (_theResult____h626556[20] ? + (_theResult____h626553[20] ? 6'd36 : - (_theResult____h626556[19] ? + (_theResult____h626553[19] ? 6'd37 : - (_theResult____h626556[18] ? + (_theResult____h626553[18] ? 6'd38 : - (_theResult____h626556[17] ? + (_theResult____h626553[17] ? 6'd39 : - (_theResult____h626556[16] ? + (_theResult____h626553[16] ? 6'd40 : - (_theResult____h626556[15] ? + (_theResult____h626553[15] ? 6'd41 : - (_theResult____h626556[14] ? + (_theResult____h626553[14] ? 6'd42 : - (_theResult____h626556[13] ? + (_theResult____h626553[13] ? 6'd43 : - (_theResult____h626556[12] ? + (_theResult____h626553[12] ? 6'd44 : - (_theResult____h626556[11] ? + (_theResult____h626553[11] ? 6'd45 : - (_theResult____h626556[10] ? + (_theResult____h626553[10] ? 6'd46 : - (_theResult____h626556[9] ? + (_theResult____h626553[9] ? 6'd47 : - (_theResult____h626556[8] ? + (_theResult____h626553[8] ? 6'd48 : - (_theResult____h626556[7] ? + (_theResult____h626553[7] ? 6'd49 : - (_theResult____h626556[6] ? + (_theResult____h626553[6] ? 6'd50 : - (_theResult____h626556[5] ? + (_theResult____h626553[5] ? 6'd51 : - (_theResult____h626556[4] ? + (_theResult____h626553[4] ? 6'd52 : - (_theResult____h626556[3] ? + (_theResult____h626553[3] ? 6'd53 : - (_theResult____h626556[2] ? + (_theResult____h626553[2] ? 6'd54 : - (_theResult____h626556[1] ? + (_theResult____h626553[1] ? 6'd55 : - (_theResult____h626556[0] ? + (_theResult____h626553[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13134 = - (_theResult____h740486[56] ? + (_theResult____h740483[56] ? 6'd0 : - (_theResult____h740486[55] ? + (_theResult____h740483[55] ? 6'd1 : - (_theResult____h740486[54] ? + (_theResult____h740483[54] ? 6'd2 : - (_theResult____h740486[53] ? + (_theResult____h740483[53] ? 6'd3 : - (_theResult____h740486[52] ? + (_theResult____h740483[52] ? 6'd4 : - (_theResult____h740486[51] ? + (_theResult____h740483[51] ? 6'd5 : - (_theResult____h740486[50] ? + (_theResult____h740483[50] ? 6'd6 : - (_theResult____h740486[49] ? + (_theResult____h740483[49] ? 6'd7 : - (_theResult____h740486[48] ? + (_theResult____h740483[48] ? 6'd8 : - (_theResult____h740486[47] ? + (_theResult____h740483[47] ? 6'd9 : - (_theResult____h740486[46] ? + (_theResult____h740483[46] ? 6'd10 : - (_theResult____h740486[45] ? + (_theResult____h740483[45] ? 6'd11 : - (_theResult____h740486[44] ? + (_theResult____h740483[44] ? 6'd12 : - (_theResult____h740486[43] ? + (_theResult____h740483[43] ? 6'd13 : - (_theResult____h740486[42] ? + (_theResult____h740483[42] ? 6'd14 : - (_theResult____h740486[41] ? + (_theResult____h740483[41] ? 6'd15 : - (_theResult____h740486[40] ? + (_theResult____h740483[40] ? 6'd16 : - (_theResult____h740486[39] ? + (_theResult____h740483[39] ? 6'd17 : - (_theResult____h740486[38] ? + (_theResult____h740483[38] ? 6'd18 : - (_theResult____h740486[37] ? + (_theResult____h740483[37] ? 6'd19 : - (_theResult____h740486[36] ? + (_theResult____h740483[36] ? 6'd20 : - (_theResult____h740486[35] ? + (_theResult____h740483[35] ? 6'd21 : - (_theResult____h740486[34] ? + (_theResult____h740483[34] ? 6'd22 : - (_theResult____h740486[33] ? + (_theResult____h740483[33] ? 6'd23 : - (_theResult____h740486[32] ? + (_theResult____h740483[32] ? 6'd24 : - (_theResult____h740486[31] ? + (_theResult____h740483[31] ? 6'd25 : - (_theResult____h740486[30] ? + (_theResult____h740483[30] ? 6'd26 : - (_theResult____h740486[29] ? + (_theResult____h740483[29] ? 6'd27 : - (_theResult____h740486[28] ? + (_theResult____h740483[28] ? 6'd28 : - (_theResult____h740486[27] ? + (_theResult____h740483[27] ? 6'd29 : - (_theResult____h740486[26] ? + (_theResult____h740483[26] ? 6'd30 : - (_theResult____h740486[25] ? + (_theResult____h740483[25] ? 6'd31 : - (_theResult____h740486[24] ? + (_theResult____h740483[24] ? 6'd32 : - (_theResult____h740486[23] ? + (_theResult____h740483[23] ? 6'd33 : - (_theResult____h740486[22] ? + (_theResult____h740483[22] ? 6'd34 : - (_theResult____h740486[21] ? + (_theResult____h740483[21] ? 6'd35 : - (_theResult____h740486[20] ? + (_theResult____h740483[20] ? 6'd36 : - (_theResult____h740486[19] ? + (_theResult____h740483[19] ? 6'd37 : - (_theResult____h740486[18] ? + (_theResult____h740483[18] ? 6'd38 : - (_theResult____h740486[17] ? + (_theResult____h740483[17] ? 6'd39 : - (_theResult____h740486[16] ? + (_theResult____h740483[16] ? 6'd40 : - (_theResult____h740486[15] ? + (_theResult____h740483[15] ? 6'd41 : - (_theResult____h740486[14] ? + (_theResult____h740483[14] ? 6'd42 : - (_theResult____h740486[13] ? + (_theResult____h740483[13] ? 6'd43 : - (_theResult____h740486[12] ? + (_theResult____h740483[12] ? 6'd44 : - (_theResult____h740486[11] ? + (_theResult____h740483[11] ? 6'd45 : - (_theResult____h740486[10] ? + (_theResult____h740483[10] ? 6'd46 : - (_theResult____h740486[9] ? + (_theResult____h740483[9] ? 6'd47 : - (_theResult____h740486[8] ? + (_theResult____h740483[8] ? 6'd48 : - (_theResult____h740486[7] ? + (_theResult____h740483[7] ? 6'd49 : - (_theResult____h740486[6] ? + (_theResult____h740483[6] ? 6'd50 : - (_theResult____h740486[5] ? + (_theResult____h740483[5] ? 6'd51 : - (_theResult____h740486[4] ? + (_theResult____h740483[4] ? 6'd52 : - (_theResult____h740486[3] ? + (_theResult____h740483[3] ? 6'd53 : - (_theResult____h740486[2] ? + (_theResult____h740483[2] ? 6'd54 : - (_theResult____h740486[1] ? + (_theResult____h740483[1] ? 6'd55 : - (_theResult____h740486[0] ? + (_theResult____h740483[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13849 = - (_theResult____h818643[56] ? + (_theResult____h818640[56] ? 6'd0 : - (_theResult____h818643[55] ? + (_theResult____h818640[55] ? 6'd1 : - (_theResult____h818643[54] ? + (_theResult____h818640[54] ? 6'd2 : - (_theResult____h818643[53] ? + (_theResult____h818640[53] ? 6'd3 : - (_theResult____h818643[52] ? + (_theResult____h818640[52] ? 6'd4 : - (_theResult____h818643[51] ? + (_theResult____h818640[51] ? 6'd5 : - (_theResult____h818643[50] ? + (_theResult____h818640[50] ? 6'd6 : - (_theResult____h818643[49] ? + (_theResult____h818640[49] ? 6'd7 : - (_theResult____h818643[48] ? + (_theResult____h818640[48] ? 6'd8 : - (_theResult____h818643[47] ? + (_theResult____h818640[47] ? 6'd9 : - (_theResult____h818643[46] ? + (_theResult____h818640[46] ? 6'd10 : - (_theResult____h818643[45] ? + (_theResult____h818640[45] ? 6'd11 : - (_theResult____h818643[44] ? + (_theResult____h818640[44] ? 6'd12 : - (_theResult____h818643[43] ? + (_theResult____h818640[43] ? 6'd13 : - (_theResult____h818643[42] ? + (_theResult____h818640[42] ? 6'd14 : - (_theResult____h818643[41] ? + (_theResult____h818640[41] ? 6'd15 : - (_theResult____h818643[40] ? + (_theResult____h818640[40] ? 6'd16 : - (_theResult____h818643[39] ? + (_theResult____h818640[39] ? 6'd17 : - (_theResult____h818643[38] ? + (_theResult____h818640[38] ? 6'd18 : - (_theResult____h818643[37] ? + (_theResult____h818640[37] ? 6'd19 : - (_theResult____h818643[36] ? + (_theResult____h818640[36] ? 6'd20 : - (_theResult____h818643[35] ? + (_theResult____h818640[35] ? 6'd21 : - (_theResult____h818643[34] ? + (_theResult____h818640[34] ? 6'd22 : - (_theResult____h818643[33] ? + (_theResult____h818640[33] ? 6'd23 : - (_theResult____h818643[32] ? + (_theResult____h818640[32] ? 6'd24 : - (_theResult____h818643[31] ? + (_theResult____h818640[31] ? 6'd25 : - (_theResult____h818643[30] ? + (_theResult____h818640[30] ? 6'd26 : - (_theResult____h818643[29] ? + (_theResult____h818640[29] ? 6'd27 : - (_theResult____h818643[28] ? + (_theResult____h818640[28] ? 6'd28 : - (_theResult____h818643[27] ? + (_theResult____h818640[27] ? 6'd29 : - (_theResult____h818643[26] ? + (_theResult____h818640[26] ? 6'd30 : - (_theResult____h818643[25] ? + (_theResult____h818640[25] ? 6'd31 : - (_theResult____h818643[24] ? + (_theResult____h818640[24] ? 6'd32 : - (_theResult____h818643[23] ? + (_theResult____h818640[23] ? 6'd33 : - (_theResult____h818643[22] ? + (_theResult____h818640[22] ? 6'd34 : - (_theResult____h818643[21] ? + (_theResult____h818640[21] ? 6'd35 : - (_theResult____h818643[20] ? + (_theResult____h818640[20] ? 6'd36 : - (_theResult____h818643[19] ? + (_theResult____h818640[19] ? 6'd37 : - (_theResult____h818643[18] ? + (_theResult____h818640[18] ? 6'd38 : - (_theResult____h818643[17] ? + (_theResult____h818640[17] ? 6'd39 : - (_theResult____h818643[16] ? + (_theResult____h818640[16] ? 6'd40 : - (_theResult____h818643[15] ? + (_theResult____h818640[15] ? 6'd41 : - (_theResult____h818643[14] ? + (_theResult____h818640[14] ? 6'd42 : - (_theResult____h818643[13] ? + (_theResult____h818640[13] ? 6'd43 : - (_theResult____h818643[12] ? + (_theResult____h818640[12] ? 6'd44 : - (_theResult____h818643[11] ? + (_theResult____h818640[11] ? 6'd45 : - (_theResult____h818643[10] ? + (_theResult____h818640[10] ? 6'd46 : - (_theResult____h818643[9] ? + (_theResult____h818640[9] ? 6'd47 : - (_theResult____h818643[8] ? + (_theResult____h818640[8] ? 6'd48 : - (_theResult____h818643[7] ? + (_theResult____h818640[7] ? 6'd49 : - (_theResult____h818643[6] ? + (_theResult____h818640[6] ? 6'd50 : - (_theResult____h818643[5] ? + (_theResult____h818640[5] ? 6'd51 : - (_theResult____h818643[4] ? + (_theResult____h818640[4] ? 6'd52 : - (_theResult____h818643[3] ? + (_theResult____h818640[3] ? 6'd53 : - (_theResult____h818643[2] ? + (_theResult____h818640[2] ? 6'd54 : - (_theResult____h818643[1] ? + (_theResult____h818640[1] ? 6'd55 : - (_theResult____h818643[0] ? + (_theResult____h818640[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14619 = - (_theResult____h779339[56] ? + (_theResult____h779336[56] ? 6'd0 : - (_theResult____h779339[55] ? + (_theResult____h779336[55] ? 6'd1 : - (_theResult____h779339[54] ? + (_theResult____h779336[54] ? 6'd2 : - (_theResult____h779339[53] ? + (_theResult____h779336[53] ? 6'd3 : - (_theResult____h779339[52] ? + (_theResult____h779336[52] ? 6'd4 : - (_theResult____h779339[51] ? + (_theResult____h779336[51] ? 6'd5 : - (_theResult____h779339[50] ? + (_theResult____h779336[50] ? 6'd6 : - (_theResult____h779339[49] ? + (_theResult____h779336[49] ? 6'd7 : - (_theResult____h779339[48] ? + (_theResult____h779336[48] ? 6'd8 : - (_theResult____h779339[47] ? + (_theResult____h779336[47] ? 6'd9 : - (_theResult____h779339[46] ? + (_theResult____h779336[46] ? 6'd10 : - (_theResult____h779339[45] ? + (_theResult____h779336[45] ? 6'd11 : - (_theResult____h779339[44] ? + (_theResult____h779336[44] ? 6'd12 : - (_theResult____h779339[43] ? + (_theResult____h779336[43] ? 6'd13 : - (_theResult____h779339[42] ? + (_theResult____h779336[42] ? 6'd14 : - (_theResult____h779339[41] ? + (_theResult____h779336[41] ? 6'd15 : - (_theResult____h779339[40] ? + (_theResult____h779336[40] ? 6'd16 : - (_theResult____h779339[39] ? + (_theResult____h779336[39] ? 6'd17 : - (_theResult____h779339[38] ? + (_theResult____h779336[38] ? 6'd18 : - (_theResult____h779339[37] ? + (_theResult____h779336[37] ? 6'd19 : - (_theResult____h779339[36] ? + (_theResult____h779336[36] ? 6'd20 : - (_theResult____h779339[35] ? + (_theResult____h779336[35] ? 6'd21 : - (_theResult____h779339[34] ? + (_theResult____h779336[34] ? 6'd22 : - (_theResult____h779339[33] ? + (_theResult____h779336[33] ? 6'd23 : - (_theResult____h779339[32] ? + (_theResult____h779336[32] ? 6'd24 : - (_theResult____h779339[31] ? + (_theResult____h779336[31] ? 6'd25 : - (_theResult____h779339[30] ? + (_theResult____h779336[30] ? 6'd26 : - (_theResult____h779339[29] ? + (_theResult____h779336[29] ? 6'd27 : - (_theResult____h779339[28] ? + (_theResult____h779336[28] ? 6'd28 : - (_theResult____h779339[27] ? + (_theResult____h779336[27] ? 6'd29 : - (_theResult____h779339[26] ? + (_theResult____h779336[26] ? 6'd30 : - (_theResult____h779339[25] ? + (_theResult____h779336[25] ? 6'd31 : - (_theResult____h779339[24] ? + (_theResult____h779336[24] ? 6'd32 : - (_theResult____h779339[23] ? + (_theResult____h779336[23] ? 6'd33 : - (_theResult____h779339[22] ? + (_theResult____h779336[22] ? 6'd34 : - (_theResult____h779339[21] ? + (_theResult____h779336[21] ? 6'd35 : - (_theResult____h779339[20] ? + (_theResult____h779336[20] ? 6'd36 : - (_theResult____h779339[19] ? + (_theResult____h779336[19] ? 6'd37 : - (_theResult____h779339[18] ? + (_theResult____h779336[18] ? 6'd38 : - (_theResult____h779339[17] ? + (_theResult____h779336[17] ? 6'd39 : - (_theResult____h779339[16] ? + (_theResult____h779336[16] ? 6'd40 : - (_theResult____h779339[15] ? + (_theResult____h779336[15] ? 6'd41 : - (_theResult____h779339[14] ? + (_theResult____h779336[14] ? 6'd42 : - (_theResult____h779339[13] ? + (_theResult____h779336[13] ? 6'd43 : - (_theResult____h779339[12] ? + (_theResult____h779336[12] ? 6'd44 : - (_theResult____h779339[11] ? + (_theResult____h779336[11] ? 6'd45 : - (_theResult____h779339[10] ? + (_theResult____h779336[10] ? 6'd46 : - (_theResult____h779339[9] ? + (_theResult____h779336[9] ? 6'd47 : - (_theResult____h779339[8] ? + (_theResult____h779336[8] ? 6'd48 : - (_theResult____h779339[7] ? + (_theResult____h779336[7] ? 6'd49 : - (_theResult____h779339[6] ? + (_theResult____h779336[6] ? 6'd50 : - (_theResult____h779339[5] ? + (_theResult____h779336[5] ? 6'd51 : - (_theResult____h779339[4] ? + (_theResult____h779336[4] ? 6'd52 : - (_theResult____h779339[3] ? + (_theResult____h779336[3] ? 6'd53 : - (_theResult____h779339[2] ? + (_theResult____h779336[2] ? 6'd54 : - (_theResult____h779339[1] ? + (_theResult____h779336[1] ? 6'd55 : - (_theResult____h779339[0] ? + (_theResult____h779336[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10391 = - (_theResult____h644193[56] ? + (_theResult____h644190[56] ? 6'd0 : - (_theResult____h644193[55] ? + (_theResult____h644190[55] ? 6'd1 : - (_theResult____h644193[54] ? + (_theResult____h644190[54] ? 6'd2 : - (_theResult____h644193[53] ? + (_theResult____h644190[53] ? 6'd3 : - (_theResult____h644193[52] ? + (_theResult____h644190[52] ? 6'd4 : - (_theResult____h644193[51] ? + (_theResult____h644190[51] ? 6'd5 : - (_theResult____h644193[50] ? + (_theResult____h644190[50] ? 6'd6 : - (_theResult____h644193[49] ? + (_theResult____h644190[49] ? 6'd7 : - (_theResult____h644193[48] ? + (_theResult____h644190[48] ? 6'd8 : - (_theResult____h644193[47] ? + (_theResult____h644190[47] ? 6'd9 : - (_theResult____h644193[46] ? + (_theResult____h644190[46] ? 6'd10 : - (_theResult____h644193[45] ? + (_theResult____h644190[45] ? 6'd11 : - (_theResult____h644193[44] ? + (_theResult____h644190[44] ? 6'd12 : - (_theResult____h644193[43] ? + (_theResult____h644190[43] ? 6'd13 : - (_theResult____h644193[42] ? + (_theResult____h644190[42] ? 6'd14 : - (_theResult____h644193[41] ? + (_theResult____h644190[41] ? 6'd15 : - (_theResult____h644193[40] ? + (_theResult____h644190[40] ? 6'd16 : - (_theResult____h644193[39] ? + (_theResult____h644190[39] ? 6'd17 : - (_theResult____h644193[38] ? + (_theResult____h644190[38] ? 6'd18 : - (_theResult____h644193[37] ? + (_theResult____h644190[37] ? 6'd19 : - (_theResult____h644193[36] ? + (_theResult____h644190[36] ? 6'd20 : - (_theResult____h644193[35] ? + (_theResult____h644190[35] ? 6'd21 : - (_theResult____h644193[34] ? + (_theResult____h644190[34] ? 6'd22 : - (_theResult____h644193[33] ? + (_theResult____h644190[33] ? 6'd23 : - (_theResult____h644193[32] ? + (_theResult____h644190[32] ? 6'd24 : - (_theResult____h644193[31] ? + (_theResult____h644190[31] ? 6'd25 : - (_theResult____h644193[30] ? + (_theResult____h644190[30] ? 6'd26 : - (_theResult____h644193[29] ? + (_theResult____h644190[29] ? 6'd27 : - (_theResult____h644193[28] ? + (_theResult____h644190[28] ? 6'd28 : - (_theResult____h644193[27] ? + (_theResult____h644190[27] ? 6'd29 : - (_theResult____h644193[26] ? + (_theResult____h644190[26] ? 6'd30 : - (_theResult____h644193[25] ? + (_theResult____h644190[25] ? 6'd31 : - (_theResult____h644193[24] ? + (_theResult____h644190[24] ? 6'd32 : - (_theResult____h644193[23] ? + (_theResult____h644190[23] ? 6'd33 : - (_theResult____h644193[22] ? + (_theResult____h644190[22] ? 6'd34 : - (_theResult____h644193[21] ? + (_theResult____h644190[21] ? 6'd35 : - (_theResult____h644193[20] ? + (_theResult____h644190[20] ? 6'd36 : - (_theResult____h644193[19] ? + (_theResult____h644190[19] ? 6'd37 : - (_theResult____h644193[18] ? + (_theResult____h644190[18] ? 6'd38 : - (_theResult____h644193[17] ? + (_theResult____h644190[17] ? 6'd39 : - (_theResult____h644193[16] ? + (_theResult____h644190[16] ? 6'd40 : - (_theResult____h644193[15] ? + (_theResult____h644190[15] ? 6'd41 : - (_theResult____h644193[14] ? + (_theResult____h644190[14] ? 6'd42 : - (_theResult____h644193[13] ? + (_theResult____h644190[13] ? 6'd43 : - (_theResult____h644193[12] ? + (_theResult____h644190[12] ? 6'd44 : - (_theResult____h644193[11] ? + (_theResult____h644190[11] ? 6'd45 : - (_theResult____h644193[10] ? + (_theResult____h644190[10] ? 6'd46 : - (_theResult____h644193[9] ? + (_theResult____h644190[9] ? 6'd47 : - (_theResult____h644193[8] ? + (_theResult____h644190[8] ? 6'd48 : - (_theResult____h644193[7] ? + (_theResult____h644190[7] ? 6'd49 : - (_theResult____h644193[6] ? + (_theResult____h644190[6] ? 6'd50 : - (_theResult____h644193[5] ? + (_theResult____h644190[5] ? 6'd51 : - (_theResult____h644193[4] ? + (_theResult____h644190[4] ? 6'd52 : - (_theResult____h644193[3] ? + (_theResult____h644190[3] ? 6'd53 : - (_theResult____h644193[2] ? + (_theResult____h644190[2] ? 6'd54 : - (_theResult____h644193[1] ? + (_theResult____h644190[1] ? 6'd55 : - (_theResult____h644193[0] ? + (_theResult____h644190[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11788 = - (_theResult____h689940[56] ? + (_theResult____h689937[56] ? 6'd0 : - (_theResult____h689940[55] ? + (_theResult____h689937[55] ? 6'd1 : - (_theResult____h689940[54] ? + (_theResult____h689937[54] ? 6'd2 : - (_theResult____h689940[53] ? + (_theResult____h689937[53] ? 6'd3 : - (_theResult____h689940[52] ? + (_theResult____h689937[52] ? 6'd4 : - (_theResult____h689940[51] ? + (_theResult____h689937[51] ? 6'd5 : - (_theResult____h689940[50] ? + (_theResult____h689937[50] ? 6'd6 : - (_theResult____h689940[49] ? + (_theResult____h689937[49] ? 6'd7 : - (_theResult____h689940[48] ? + (_theResult____h689937[48] ? 6'd8 : - (_theResult____h689940[47] ? + (_theResult____h689937[47] ? 6'd9 : - (_theResult____h689940[46] ? + (_theResult____h689937[46] ? 6'd10 : - (_theResult____h689940[45] ? + (_theResult____h689937[45] ? 6'd11 : - (_theResult____h689940[44] ? + (_theResult____h689937[44] ? 6'd12 : - (_theResult____h689940[43] ? + (_theResult____h689937[43] ? 6'd13 : - (_theResult____h689940[42] ? + (_theResult____h689937[42] ? 6'd14 : - (_theResult____h689940[41] ? + (_theResult____h689937[41] ? 6'd15 : - (_theResult____h689940[40] ? + (_theResult____h689937[40] ? 6'd16 : - (_theResult____h689940[39] ? + (_theResult____h689937[39] ? 6'd17 : - (_theResult____h689940[38] ? + (_theResult____h689937[38] ? 6'd18 : - (_theResult____h689940[37] ? + (_theResult____h689937[37] ? 6'd19 : - (_theResult____h689940[36] ? + (_theResult____h689937[36] ? 6'd20 : - (_theResult____h689940[35] ? + (_theResult____h689937[35] ? 6'd21 : - (_theResult____h689940[34] ? + (_theResult____h689937[34] ? 6'd22 : - (_theResult____h689940[33] ? + (_theResult____h689937[33] ? 6'd23 : - (_theResult____h689940[32] ? + (_theResult____h689937[32] ? 6'd24 : - (_theResult____h689940[31] ? + (_theResult____h689937[31] ? 6'd25 : - (_theResult____h689940[30] ? + (_theResult____h689937[30] ? 6'd26 : - (_theResult____h689940[29] ? + (_theResult____h689937[29] ? 6'd27 : - (_theResult____h689940[28] ? + (_theResult____h689937[28] ? 6'd28 : - (_theResult____h689940[27] ? + (_theResult____h689937[27] ? 6'd29 : - (_theResult____h689940[26] ? + (_theResult____h689937[26] ? 6'd30 : - (_theResult____h689940[25] ? + (_theResult____h689937[25] ? 6'd31 : - (_theResult____h689940[24] ? + (_theResult____h689937[24] ? 6'd32 : - (_theResult____h689940[23] ? + (_theResult____h689937[23] ? 6'd33 : - (_theResult____h689940[22] ? + (_theResult____h689937[22] ? 6'd34 : - (_theResult____h689940[21] ? + (_theResult____h689937[21] ? 6'd35 : - (_theResult____h689940[20] ? + (_theResult____h689937[20] ? 6'd36 : - (_theResult____h689940[19] ? + (_theResult____h689937[19] ? 6'd37 : - (_theResult____h689940[18] ? + (_theResult____h689937[18] ? 6'd38 : - (_theResult____h689940[17] ? + (_theResult____h689937[17] ? 6'd39 : - (_theResult____h689940[16] ? + (_theResult____h689937[16] ? 6'd40 : - (_theResult____h689940[15] ? + (_theResult____h689937[15] ? 6'd41 : - (_theResult____h689940[14] ? + (_theResult____h689937[14] ? 6'd42 : - (_theResult____h689940[13] ? + (_theResult____h689937[13] ? 6'd43 : - (_theResult____h689940[12] ? + (_theResult____h689937[12] ? 6'd44 : - (_theResult____h689940[11] ? + (_theResult____h689937[11] ? 6'd45 : - (_theResult____h689940[10] ? + (_theResult____h689937[10] ? 6'd46 : - (_theResult____h689940[9] ? + (_theResult____h689937[9] ? 6'd47 : - (_theResult____h689940[8] ? + (_theResult____h689937[8] ? 6'd48 : - (_theResult____h689940[7] ? + (_theResult____h689937[7] ? 6'd49 : - (_theResult____h689940[6] ? + (_theResult____h689937[6] ? 6'd50 : - (_theResult____h689940[5] ? + (_theResult____h689937[5] ? 6'd51 : - (_theResult____h689940[4] ? + (_theResult____h689937[4] ? 6'd52 : - (_theResult____h689940[3] ? + (_theResult____h689937[3] ? 6'd53 : - (_theResult____h689940[2] ? + (_theResult____h689937[2] ? 6'd54 : - (_theResult____h689940[1] ? + (_theResult____h689937[1] ? 6'd55 : - (_theResult____h689940[0] ? + (_theResult____h689937[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8994 = - (_theResult____h598444[56] ? + (_theResult____h598441[56] ? 6'd0 : - (_theResult____h598444[55] ? + (_theResult____h598441[55] ? 6'd1 : - (_theResult____h598444[54] ? + (_theResult____h598441[54] ? 6'd2 : - (_theResult____h598444[53] ? + (_theResult____h598441[53] ? 6'd3 : - (_theResult____h598444[52] ? + (_theResult____h598441[52] ? 6'd4 : - (_theResult____h598444[51] ? + (_theResult____h598441[51] ? 6'd5 : - (_theResult____h598444[50] ? + (_theResult____h598441[50] ? 6'd6 : - (_theResult____h598444[49] ? + (_theResult____h598441[49] ? 6'd7 : - (_theResult____h598444[48] ? + (_theResult____h598441[48] ? 6'd8 : - (_theResult____h598444[47] ? + (_theResult____h598441[47] ? 6'd9 : - (_theResult____h598444[46] ? + (_theResult____h598441[46] ? 6'd10 : - (_theResult____h598444[45] ? + (_theResult____h598441[45] ? 6'd11 : - (_theResult____h598444[44] ? + (_theResult____h598441[44] ? 6'd12 : - (_theResult____h598444[43] ? + (_theResult____h598441[43] ? 6'd13 : - (_theResult____h598444[42] ? + (_theResult____h598441[42] ? 6'd14 : - (_theResult____h598444[41] ? + (_theResult____h598441[41] ? 6'd15 : - (_theResult____h598444[40] ? + (_theResult____h598441[40] ? 6'd16 : - (_theResult____h598444[39] ? + (_theResult____h598441[39] ? 6'd17 : - (_theResult____h598444[38] ? + (_theResult____h598441[38] ? 6'd18 : - (_theResult____h598444[37] ? + (_theResult____h598441[37] ? 6'd19 : - (_theResult____h598444[36] ? + (_theResult____h598441[36] ? 6'd20 : - (_theResult____h598444[35] ? + (_theResult____h598441[35] ? 6'd21 : - (_theResult____h598444[34] ? + (_theResult____h598441[34] ? 6'd22 : - (_theResult____h598444[33] ? + (_theResult____h598441[33] ? 6'd23 : - (_theResult____h598444[32] ? + (_theResult____h598441[32] ? 6'd24 : - (_theResult____h598444[31] ? + (_theResult____h598441[31] ? 6'd25 : - (_theResult____h598444[30] ? + (_theResult____h598441[30] ? 6'd26 : - (_theResult____h598444[29] ? + (_theResult____h598441[29] ? 6'd27 : - (_theResult____h598444[28] ? + (_theResult____h598441[28] ? 6'd28 : - (_theResult____h598444[27] ? + (_theResult____h598441[27] ? 6'd29 : - (_theResult____h598444[26] ? + (_theResult____h598441[26] ? 6'd30 : - (_theResult____h598444[25] ? + (_theResult____h598441[25] ? 6'd31 : - (_theResult____h598444[24] ? + (_theResult____h598441[24] ? 6'd32 : - (_theResult____h598444[23] ? + (_theResult____h598441[23] ? 6'd33 : - (_theResult____h598444[22] ? + (_theResult____h598441[22] ? 6'd34 : - (_theResult____h598444[21] ? + (_theResult____h598441[21] ? 6'd35 : - (_theResult____h598444[20] ? + (_theResult____h598441[20] ? 6'd36 : - (_theResult____h598444[19] ? + (_theResult____h598441[19] ? 6'd37 : - (_theResult____h598444[18] ? + (_theResult____h598441[18] ? 6'd38 : - (_theResult____h598444[17] ? + (_theResult____h598441[17] ? 6'd39 : - (_theResult____h598444[16] ? + (_theResult____h598441[16] ? 6'd40 : - (_theResult____h598444[15] ? + (_theResult____h598441[15] ? 6'd41 : - (_theResult____h598444[14] ? + (_theResult____h598441[14] ? 6'd42 : - (_theResult____h598444[13] ? + (_theResult____h598441[13] ? 6'd43 : - (_theResult____h598444[12] ? + (_theResult____h598441[12] ? 6'd44 : - (_theResult____h598444[11] ? + (_theResult____h598441[11] ? 6'd45 : - (_theResult____h598444[10] ? + (_theResult____h598441[10] ? 6'd46 : - (_theResult____h598444[9] ? + (_theResult____h598441[9] ? 6'd47 : - (_theResult____h598444[8] ? + (_theResult____h598441[8] ? 6'd48 : - (_theResult____h598444[7] ? + (_theResult____h598441[7] ? 6'd49 : - (_theResult____h598444[6] ? + (_theResult____h598441[6] ? 6'd50 : - (_theResult____h598444[5] ? + (_theResult____h598441[5] ? 6'd51 : - (_theResult____h598444[4] ? + (_theResult____h598441[4] ? 6'd52 : - (_theResult____h598444[3] ? + (_theResult____h598441[3] ? 6'd53 : - (_theResult____h598444[2] ? + (_theResult____h598441[2] ? 6'd54 : - (_theResult____h598444[1] ? + (_theResult____h598441[1] ? 6'd55 : - (_theResult____h598444[0] ? + (_theResult____h598441[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13178 = - (_theResult___fst_exp__h748722 == 11'd2047) ? + (_theResult___fst_exp__h748719 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19339,10 +19339,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard40496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard40493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13893 = - (_theResult___fst_exp__h826879 == 11'd2047) ? + (_theResult___fst_exp__h826876 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19350,10 +19350,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 : + CASE_guard18650_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14161 = - (_theResult___fst_exp__h826879 == 11'd2047) ? + (_theResult___fst_exp__h826876 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19361,10 +19361,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 : + CASE_guard18650_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14663 = - (_theResult___fst_exp__h787575 == 11'd2047) ? + (_theResult___fst_exp__h787572 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19372,10 +19372,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 : + CASE_guard79346_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14930 = - (_theResult___fst_exp__h787575 == 11'd2047) ? + (_theResult___fst_exp__h787572 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19383,404 +19383,404 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 : + CASE_guard79346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10550 = - (guard__h626566 == 2'b0 || + (guard__h626563 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h634659[56:34] : - _theResult___sfd__h635182 ; + sfdin__h634656[56:34] : + _theResult___sfd__h635179 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10552 = - (guard__h626566 == 2'b0) ? - sfdin__h634659[56:34] : + (guard__h626563 == 2'b0) ? + sfdin__h634656[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h635182 : - sfdin__h634659[56:34]) ; + _theResult___sfd__h635179 : + sfdin__h634656[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11300 = - (guard__h672313 == 2'b0 || + (guard__h672310 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h680412 : - _theResult___exp__h680928 ; + _theResult___fst_exp__h680409 : + _theResult___exp__h680925 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11303 = - (guard__h672313 == 2'b0) ? - _theResult___fst_exp__h680412 : + (guard__h672310 == 2'b0) ? + _theResult___fst_exp__h680409 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h680928 : - _theResult___fst_exp__h680412) ; + _theResult___exp__h680925 : + _theResult___fst_exp__h680409) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11947 = - (guard__h672313 == 2'b0 || + (guard__h672310 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h680406[56:34] : - _theResult___sfd__h680929 ; + sfdin__h680403[56:34] : + _theResult___sfd__h680926 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11949 = - (guard__h672313 == 2'b0) ? - sfdin__h680406[56:34] : + (guard__h672310 == 2'b0) ? + sfdin__h680403[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h680929 : - sfdin__h680406[56:34]) ; + _theResult___sfd__h680926 : + sfdin__h680403[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8506 = - (guard__h580815 == 2'b0 || + (guard__h580812 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h588916 : - _theResult___exp__h589432 ; + _theResult___fst_exp__h588913 : + _theResult___exp__h589429 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8509 = - (guard__h580815 == 2'b0) ? - _theResult___fst_exp__h588916 : + (guard__h580812 == 2'b0) ? + _theResult___fst_exp__h588913 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h589432 : - _theResult___fst_exp__h588916) ; + _theResult___exp__h589429 : + _theResult___fst_exp__h588913) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9153 = - (guard__h580815 == 2'b0 || + (guard__h580812 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h588910[56:34] : - _theResult___sfd__h589433 ; + sfdin__h588907[56:34] : + _theResult___sfd__h589430 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9155 = - (guard__h580815 == 2'b0) ? - sfdin__h588910[56:34] : + (guard__h580812 == 2'b0) ? + sfdin__h588907[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h589433 : - sfdin__h588910[56:34]) ; + _theResult___sfd__h589430 : + sfdin__h588907[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9903 = - (guard__h626566 == 2'b0 || + (guard__h626563 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h634665 : - _theResult___exp__h635181 ; + _theResult___fst_exp__h634662 : + _theResult___exp__h635178 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9906 = - (guard__h626566 == 2'b0) ? - _theResult___fst_exp__h634665 : + (guard__h626563 == 2'b0) ? + _theResult___fst_exp__h634662 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h635181 : - _theResult___fst_exp__h634665) ; + _theResult___exp__h635178 : + _theResult___fst_exp__h634662) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13295 = - (guard__h740496 == 2'b0 || + (guard__h740493 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h748722 : - _theResult___exp__h749451 ; + _theResult___fst_exp__h748719 : + _theResult___exp__h749448 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13297 = - (guard__h740496 == 2'b0) ? - _theResult___fst_exp__h748722 : + (guard__h740493 == 2'b0) ? + _theResult___fst_exp__h748719 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h749451 : - _theResult___fst_exp__h748722) ; + _theResult___exp__h749448 : + _theResult___fst_exp__h748719) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13379 = - (guard__h740496 == 2'b0 || + (guard__h740493 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h748716[56:5] : - _theResult___sfd__h749452 ; + sfdin__h748713[56:5] : + _theResult___sfd__h749449 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13381 = - (guard__h740496 == 2'b0) ? - sfdin__h748716[56:5] : + (guard__h740493 == 2'b0) ? + sfdin__h748713[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h749452 : - sfdin__h748716[56:5]) ; + _theResult___sfd__h749449 : + sfdin__h748713[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14005 = - (guard__h818653 == 2'b0 || + (guard__h818650 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h826879 : - _theResult___exp__h827608 ; + _theResult___fst_exp__h826876 : + _theResult___exp__h827605 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14007 = - (guard__h818653 == 2'b0) ? - _theResult___fst_exp__h826879 : + (guard__h818650 == 2'b0) ? + _theResult___fst_exp__h826876 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h827608 : - _theResult___fst_exp__h826879) ; + _theResult___exp__h827605 : + _theResult___fst_exp__h826876) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14088 = - (guard__h818653 == 2'b0 || + (guard__h818650 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h826873[56:5] : - _theResult___sfd__h827609 ; + sfdin__h826870[56:5] : + _theResult___sfd__h827606 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14090 = - (guard__h818653 == 2'b0) ? - sfdin__h826873[56:5] : + (guard__h818650 == 2'b0) ? + sfdin__h826870[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h827609 : - sfdin__h826873[56:5]) ; + _theResult___sfd__h827606 : + sfdin__h826870[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14775 = - (guard__h779349 == 2'b0 || + (guard__h779346 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h787575 : - _theResult___exp__h788304 ; + _theResult___fst_exp__h787572 : + _theResult___exp__h788301 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14777 = - (guard__h779349 == 2'b0) ? - _theResult___fst_exp__h787575 : + (guard__h779346 == 2'b0) ? + _theResult___fst_exp__h787572 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h788304 : - _theResult___fst_exp__h787575) ; + _theResult___exp__h788301 : + _theResult___fst_exp__h787572) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14858 = - (guard__h779349 == 2'b0 || + (guard__h779346 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h787569[56:5] : - _theResult___sfd__h788305 ; + sfdin__h787566[56:5] : + _theResult___sfd__h788302 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14860 = - (guard__h779349 == 2'b0) ? - sfdin__h787569[56:5] : + (guard__h779346 == 2'b0) ? + sfdin__h787566[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h788305 : - sfdin__h787569[56:5]) ; + _theResult___sfd__h788302 : + sfdin__h787566[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10450 = - (guard__h644203 == 2'b0 || + (guard__h644200 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h652431 : - _theResult___exp__h652947 ; + _theResult___fst_exp__h652428 : + _theResult___exp__h652944 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10452 = - (guard__h644203 == 2'b0) ? - _theResult___fst_exp__h652431 : + (guard__h644200 == 2'b0) ? + _theResult___fst_exp__h652428 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h652947 : - _theResult___fst_exp__h652431) ; + _theResult___exp__h652944 : + _theResult___fst_exp__h652428) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10596 = - (guard__h644203 == 2'b0 || + (guard__h644200 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h652425[56:34] : - _theResult___sfd__h652948 ; + sfdin__h652422[56:34] : + _theResult___sfd__h652945 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10598 = - (guard__h644203 == 2'b0) ? - sfdin__h652425[56:34] : + (guard__h644200 == 2'b0) ? + sfdin__h652422[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h652948 : - sfdin__h652425[56:34]) ; + _theResult___sfd__h652945 : + sfdin__h652422[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11847 = - (guard__h689950 == 2'b0 || + (guard__h689947 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h698178 : - _theResult___exp__h698694 ; + _theResult___fst_exp__h698175 : + _theResult___exp__h698691 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11849 = - (guard__h689950 == 2'b0) ? - _theResult___fst_exp__h698178 : + (guard__h689947 == 2'b0) ? + _theResult___fst_exp__h698175 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h698694 : - _theResult___fst_exp__h698178) ; + _theResult___exp__h698691 : + _theResult___fst_exp__h698175) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11993 = - (guard__h689950 == 2'b0 || + (guard__h689947 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h698172[56:34] : - _theResult___sfd__h698695 ; + sfdin__h698169[56:34] : + _theResult___sfd__h698692 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11995 = - (guard__h689950 == 2'b0) ? - sfdin__h698172[56:34] : + (guard__h689947 == 2'b0) ? + sfdin__h698169[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h698695 : - sfdin__h698172[56:34]) ; + _theResult___sfd__h698692 : + sfdin__h698169[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9053 = - (guard__h598454 == 2'b0 || + (guard__h598451 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h606682 : - _theResult___exp__h607198 ; + _theResult___fst_exp__h606679 : + _theResult___exp__h607195 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9055 = - (guard__h598454 == 2'b0) ? - _theResult___fst_exp__h606682 : + (guard__h598451 == 2'b0) ? + _theResult___fst_exp__h606679 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h607198 : - _theResult___fst_exp__h606682) ; + _theResult___exp__h607195 : + _theResult___fst_exp__h606679) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9199 = - (guard__h598454 == 2'b0 || + (guard__h598451 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h606676[56:34] : - _theResult___sfd__h607199 ; + sfdin__h606673[56:34] : + _theResult___sfd__h607196 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9201 = - (guard__h598454 == 2'b0) ? - sfdin__h606676[56:34] : + (guard__h598451 == 2'b0) ? + sfdin__h606673[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h607199 : - sfdin__h606676[56:34]) ; + _theResult___sfd__h607196 : + sfdin__h606673[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13252 = - (guard__h731184 == 2'b0 || + (guard__h731181 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h739145 : - _theResult___exp__h739800 ; + _theResult___fst_exp__h739142 : + _theResult___exp__h739797 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13254 = - (guard__h731184 == 2'b0) ? - _theResult___fst_exp__h739145 : + (guard__h731181 == 2'b0) ? + _theResult___fst_exp__h739142 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h739800 : - _theResult___fst_exp__h739145) ; + _theResult___exp__h739797 : + _theResult___fst_exp__h739142) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13326 = - (guard__h749565 == 2'b0 || + (guard__h749562 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h757555 : - _theResult___exp__h758235 ; + _theResult___fst_exp__h757552 : + _theResult___exp__h758232 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13328 = - (guard__h749565 == 2'b0) ? - _theResult___fst_exp__h757555 : + (guard__h749562 == 2'b0) ? + _theResult___fst_exp__h757552 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h758235 : - _theResult___fst_exp__h757555) ; + _theResult___exp__h758232 : + _theResult___fst_exp__h757552) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13352 = - (guard__h731184 == 2'b0 || + (guard__h731181 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h739096[56:5] : - _theResult___sfd__h739801 ; + _theResult___snd__h739093[56:5] : + _theResult___sfd__h739798 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13354 = - (guard__h731184 == 2'b0) ? - _theResult___snd__h739096[56:5] : + (guard__h731181 == 2'b0) ? + _theResult___snd__h739093[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h739801 : - _theResult___snd__h739096[56:5]) ; + _theResult___sfd__h739798 : + _theResult___snd__h739093[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13398 = - (guard__h749565 == 2'b0 || + (guard__h749562 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h757501[56:5] : - _theResult___sfd__h758236 ; + _theResult___snd__h757498[56:5] : + _theResult___sfd__h758233 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13400 = - (guard__h749565 == 2'b0) ? - _theResult___snd__h757501[56:5] : + (guard__h749562 == 2'b0) ? + _theResult___snd__h757498[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h758236 : - _theResult___snd__h757501[56:5]) ; + _theResult___sfd__h758233 : + _theResult___snd__h757498[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13967 = - (guard__h809341 == 2'b0 || + (guard__h809338 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h817302 : - _theResult___exp__h817957 ; + _theResult___fst_exp__h817299 : + _theResult___exp__h817954 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13969 = - (guard__h809341 == 2'b0) ? - _theResult___fst_exp__h817302 : + (guard__h809338 == 2'b0) ? + _theResult___fst_exp__h817299 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h817957 : - _theResult___fst_exp__h817302) ; + _theResult___exp__h817954 : + _theResult___fst_exp__h817299) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14036 = - (guard__h827722 == 2'b0 || + (guard__h827719 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h835712 : - _theResult___exp__h836392 ; + _theResult___fst_exp__h835709 : + _theResult___exp__h836389 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14038 = - (guard__h827722 == 2'b0) ? - _theResult___fst_exp__h835712 : + (guard__h827719 == 2'b0) ? + _theResult___fst_exp__h835709 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h836392 : - _theResult___fst_exp__h835712) ; + _theResult___exp__h836389 : + _theResult___fst_exp__h835709) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14062 = - (guard__h809341 == 2'b0 || + (guard__h809338 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h817253[56:5] : - _theResult___sfd__h817958 ; + _theResult___snd__h817250[56:5] : + _theResult___sfd__h817955 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14064 = - (guard__h809341 == 2'b0) ? - _theResult___snd__h817253[56:5] : + (guard__h809338 == 2'b0) ? + _theResult___snd__h817250[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h817958 : - _theResult___snd__h817253[56:5]) ; + _theResult___sfd__h817955 : + _theResult___snd__h817250[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14107 = - (guard__h827722 == 2'b0 || + (guard__h827719 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h835658[56:5] : - _theResult___sfd__h836393 ; + _theResult___snd__h835655[56:5] : + _theResult___sfd__h836390 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14109 = - (guard__h827722 == 2'b0) ? - _theResult___snd__h835658[56:5] : + (guard__h827719 == 2'b0) ? + _theResult___snd__h835655[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h836393 : - _theResult___snd__h835658[56:5]) ; + _theResult___sfd__h836390 : + _theResult___snd__h835655[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14737 = - (guard__h770037 == 2'b0 || + (guard__h770034 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h777998 : - _theResult___exp__h778653 ; + _theResult___fst_exp__h777995 : + _theResult___exp__h778650 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14739 = - (guard__h770037 == 2'b0) ? - _theResult___fst_exp__h777998 : + (guard__h770034 == 2'b0) ? + _theResult___fst_exp__h777995 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h778653 : - _theResult___fst_exp__h777998) ; + _theResult___exp__h778650 : + _theResult___fst_exp__h777995) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14806 = - (guard__h788418 == 2'b0 || + (guard__h788415 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h796408 : - _theResult___exp__h797088 ; + _theResult___fst_exp__h796405 : + _theResult___exp__h797085 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14808 = - (guard__h788418 == 2'b0) ? - _theResult___fst_exp__h796408 : + (guard__h788415 == 2'b0) ? + _theResult___fst_exp__h796405 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h797088 : - _theResult___fst_exp__h796408) ; + _theResult___exp__h797085 : + _theResult___fst_exp__h796405) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14832 = - (guard__h770037 == 2'b0 || + (guard__h770034 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h777949[56:5] : - _theResult___sfd__h778654 ; + _theResult___snd__h777946[56:5] : + _theResult___sfd__h778651 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14834 = - (guard__h770037 == 2'b0) ? - _theResult___snd__h777949[56:5] : + (guard__h770034 == 2'b0) ? + _theResult___snd__h777946[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h778654 : - _theResult___snd__h777949[56:5]) ; + _theResult___sfd__h778651 : + _theResult___snd__h777946[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14877 = - (guard__h788418 == 2'b0 || + (guard__h788415 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h796354[56:5] : - _theResult___sfd__h797089 ; + _theResult___snd__h796351[56:5] : + _theResult___sfd__h797086 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14879 = - (guard__h788418 == 2'b0) ? - _theResult___snd__h796354[56:5] : + (guard__h788415 == 2'b0) ? + _theResult___snd__h796351[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h797089 : - _theResult___snd__h796354[56:5]) ; + _theResult___sfd__h797086 : + _theResult___snd__h796351[56:5]) ; assign IF_IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_ETC___d20999 = (IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404[0] || IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404[1] || @@ -19992,139 +19992,139 @@ module mkCore(CLK, IF_checkForException_0724_BITS_3_TO_0_0977_EQ__ETC___d20997 == 4'd9 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10125 = - (guard__h635273 == 2'b0 || + (guard__h635270 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h643321 : - _theResult___exp__h643763 ; + _theResult___fst_exp__h643318 : + _theResult___exp__h643760 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10127 = - (guard__h635273 == 2'b0) ? - _theResult___fst_exp__h643321 : + (guard__h635270 == 2'b0) ? + _theResult___fst_exp__h643318 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h643763 : - _theResult___fst_exp__h643321) ; + _theResult___exp__h643760 : + _theResult___fst_exp__h643318) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10519 = - (guard__h653039 == 2'b0 || + (guard__h653036 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h661116 : - _theResult___exp__h661583 ; + _theResult___fst_exp__h661113 : + _theResult___exp__h661580 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10521 = - (guard__h653039 == 2'b0) ? - _theResult___fst_exp__h661116 : + (guard__h653036 == 2'b0) ? + _theResult___fst_exp__h661113 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h661583 : - _theResult___fst_exp__h661116) ; + _theResult___exp__h661580 : + _theResult___fst_exp__h661113) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10569 = - (guard__h635273 == 2'b0 || + (guard__h635270 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h643272[56:34] : - _theResult___sfd__h643764 ; + _theResult___snd__h643269[56:34] : + _theResult___sfd__h643761 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10571 = - (guard__h635273 == 2'b0) ? - _theResult___snd__h643272[56:34] : + (guard__h635270 == 2'b0) ? + _theResult___snd__h643269[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h643764 : - _theResult___snd__h643272[56:34]) ; + _theResult___sfd__h643761 : + _theResult___snd__h643269[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10615 = - (guard__h653039 == 2'b0 || + (guard__h653036 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h661062[56:34] : - _theResult___sfd__h661584 ; + _theResult___snd__h661059[56:34] : + _theResult___sfd__h661581 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10617 = - (guard__h653039 == 2'b0) ? - _theResult___snd__h661062[56:34] : + (guard__h653036 == 2'b0) ? + _theResult___snd__h661059[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h661584 : - _theResult___snd__h661062[56:34]) ; + _theResult___sfd__h661581 : + _theResult___snd__h661059[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11522 = - (guard__h681020 == 2'b0 || + (guard__h681017 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h689068 : - _theResult___exp__h689510 ; + _theResult___fst_exp__h689065 : + _theResult___exp__h689507 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11524 = - (guard__h681020 == 2'b0) ? - _theResult___fst_exp__h689068 : + (guard__h681017 == 2'b0) ? + _theResult___fst_exp__h689065 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h689510 : - _theResult___fst_exp__h689068) ; + _theResult___exp__h689507 : + _theResult___fst_exp__h689065) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11916 = - (guard__h698786 == 2'b0 || + (guard__h698783 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h706863 : - _theResult___exp__h707330 ; + _theResult___fst_exp__h706860 : + _theResult___exp__h707327 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11918 = - (guard__h698786 == 2'b0) ? - _theResult___fst_exp__h706863 : + (guard__h698783 == 2'b0) ? + _theResult___fst_exp__h706860 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h707330 : - _theResult___fst_exp__h706863) ; + _theResult___exp__h707327 : + _theResult___fst_exp__h706860) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11966 = - (guard__h681020 == 2'b0 || + (guard__h681017 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h689019[56:34] : - _theResult___sfd__h689511 ; + _theResult___snd__h689016[56:34] : + _theResult___sfd__h689508 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11968 = - (guard__h681020 == 2'b0) ? - _theResult___snd__h689019[56:34] : + (guard__h681017 == 2'b0) ? + _theResult___snd__h689016[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h689511 : - _theResult___snd__h689019[56:34]) ; + _theResult___sfd__h689508 : + _theResult___snd__h689016[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12012 = - (guard__h698786 == 2'b0 || + (guard__h698783 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h706809[56:34] : - _theResult___sfd__h707331 ; + _theResult___snd__h706806[56:34] : + _theResult___sfd__h707328 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12014 = - (guard__h698786 == 2'b0) ? - _theResult___snd__h706809[56:34] : + (guard__h698783 == 2'b0) ? + _theResult___snd__h706806[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h707331 : - _theResult___snd__h706809[56:34]) ; + _theResult___sfd__h707328 : + _theResult___snd__h706806[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8728 = - (guard__h589524 == 2'b0 || + (guard__h589521 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h597572 : - _theResult___exp__h598014 ; + _theResult___fst_exp__h597569 : + _theResult___exp__h598011 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8730 = - (guard__h589524 == 2'b0) ? - _theResult___fst_exp__h597572 : + (guard__h589521 == 2'b0) ? + _theResult___fst_exp__h597569 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h598014 : - _theResult___fst_exp__h597572) ; + _theResult___exp__h598011 : + _theResult___fst_exp__h597569) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9122 = - (guard__h607290 == 2'b0 || + (guard__h607287 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h615367 : - _theResult___exp__h615834 ; + _theResult___fst_exp__h615364 : + _theResult___exp__h615831 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9124 = - (guard__h607290 == 2'b0) ? - _theResult___fst_exp__h615367 : + (guard__h607287 == 2'b0) ? + _theResult___fst_exp__h615364 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h615834 : - _theResult___fst_exp__h615367) ; + _theResult___exp__h615831 : + _theResult___fst_exp__h615364) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9172 = - (guard__h589524 == 2'b0 || + (guard__h589521 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h597523[56:34] : - _theResult___sfd__h598015 ; + _theResult___snd__h597520[56:34] : + _theResult___sfd__h598012 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9174 = - (guard__h589524 == 2'b0) ? - _theResult___snd__h597523[56:34] : + (guard__h589521 == 2'b0) ? + _theResult___snd__h597520[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h598015 : - _theResult___snd__h597523[56:34]) ; + _theResult___sfd__h598012 : + _theResult___snd__h597520[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9218 = - (guard__h607290 == 2'b0 || + (guard__h607287 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h615313[56:34] : - _theResult___sfd__h615835 ; + _theResult___snd__h615310[56:34] : + _theResult___sfd__h615832 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9220 = - (guard__h607290 == 2'b0) ? - _theResult___snd__h615313[56:34] : + (guard__h607287 == 2'b0) ? + _theResult___snd__h615310[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h615835 : - _theResult___snd__h615313[56:34]) ; + _theResult___sfd__h615832 : + _theResult___snd__h615310[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13224 = - (_theResult___fst_exp__h757555 == 11'd2047) ? + (_theResult___fst_exp__h757552 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20132,10 +20132,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard49565_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 : + CASE_guard49562_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13939 = - (_theResult___fst_exp__h835712 == 11'd2047) ? + (_theResult___fst_exp__h835709 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20143,10 +20143,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27722_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 : + CASE_guard27719_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14146 = - (_theResult___fst_exp__h817302 == 11'd2047) ? + (_theResult___fst_exp__h817299 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20154,10 +20154,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09341_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 : + CASE_guard09338_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14173 = - (_theResult___fst_exp__h835712 == 11'd2047) ? + (_theResult___fst_exp__h835709 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20165,10 +20165,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 : + CASE_guard27719_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14709 = - (_theResult___fst_exp__h796408 == 11'd2047) ? + (_theResult___fst_exp__h796405 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20176,10 +20176,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88418_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 : + CASE_guard88415_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14915 = - (_theResult___fst_exp__h777998 == 11'd2047) ? + (_theResult___fst_exp__h777995 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20187,10 +20187,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 : + CASE_guard70034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14942 = - (_theResult___fst_exp__h796408 == 11'd2047) ? + (_theResult___fst_exp__h796405 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20198,14 +20198,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88418_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 : + CASE_guard88415_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213) ; assign IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404 = - (_theResult____h926748 == 16'd0 && + (_theResult____h926743 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h927319 : - _theResult____h926748 ; + enabled_ints__h927314 : + _theResult____h926743 ; assign IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20746 = IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404[0] || IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404[1] || @@ -20650,148 +20650,148 @@ module mkCore(CLK, 5'd0 : IF_IF_coreFix_aluExe_1_exeToFinQ_first__7888_B_ETC___d18033 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12822 = - ((f1_exp__h719757 == 8'd0) ? - (f1_sfd__h719758[22] ? + ((f1_exp__h719754 == 8'd0) ? + (f1_sfd__h719755[22] ? 6'd2 : - (f1_sfd__h719758[21] ? + (f1_sfd__h719755[21] ? 6'd3 : - (f1_sfd__h719758[20] ? + (f1_sfd__h719755[20] ? 6'd4 : - (f1_sfd__h719758[19] ? + (f1_sfd__h719755[19] ? 6'd5 : - (f1_sfd__h719758[18] ? + (f1_sfd__h719755[18] ? 6'd6 : - (f1_sfd__h719758[17] ? + (f1_sfd__h719755[17] ? 6'd7 : - (f1_sfd__h719758[16] ? + (f1_sfd__h719755[16] ? 6'd8 : - (f1_sfd__h719758[15] ? + (f1_sfd__h719755[15] ? 6'd9 : - (f1_sfd__h719758[14] ? + (f1_sfd__h719755[14] ? 6'd10 : - (f1_sfd__h719758[13] ? + (f1_sfd__h719755[13] ? 6'd11 : - (f1_sfd__h719758[12] ? + (f1_sfd__h719755[12] ? 6'd12 : - (f1_sfd__h719758[11] ? + (f1_sfd__h719755[11] ? 6'd13 : - (f1_sfd__h719758[10] ? + (f1_sfd__h719755[10] ? 6'd14 : - (f1_sfd__h719758[9] ? + (f1_sfd__h719755[9] ? 6'd15 : - (f1_sfd__h719758[8] ? + (f1_sfd__h719755[8] ? 6'd16 : - (f1_sfd__h719758[7] ? + (f1_sfd__h719755[7] ? 6'd17 : - (f1_sfd__h719758[6] ? + (f1_sfd__h719755[6] ? 6'd18 : - (f1_sfd__h719758[5] ? + (f1_sfd__h719755[5] ? 6'd19 : - (f1_sfd__h719758[4] ? + (f1_sfd__h719755[4] ? 6'd20 : - (f1_sfd__h719758[3] ? + (f1_sfd__h719755[3] ? 6'd21 : - (f1_sfd__h719758[2] ? + (f1_sfd__h719755[2] ? 6'd22 : - (f1_sfd__h719758[1] ? + (f1_sfd__h719755[1] ? 6'd23 : - (f1_sfd__h719758[0] ? + (f1_sfd__h719755[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13228 = - (f1_exp__h719757 == 8'd255 && f1_sfd__h719758 != 23'd0 || - (f1_exp__h719757 == 8'd255 || f1_exp__h719757 == 8'd0) && - f1_sfd__h719758 == 23'd0) ? + (f1_exp__h719754 == 8'd255 && f1_sfd__h719755 != 23'd0 || + (f1_exp__h719754 == 8'd255 || f1_exp__h719754 == 8'd0) && + f1_sfd__h719755 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h719757 == 8'd0) ? + ((f1_exp__h719754 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12883 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13226) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13411 = - (f1_exp__h719757 == 8'd255 && f1_sfd__h719758 != 23'd0) ? - _theResult___snd_fst_sfd__h720073 : - _theResult___fst_sfd__h758354 ; + (f1_exp__h719754 == 8'd255 && f1_sfd__h719755 != 23'd0) ? + _theResult___snd_fst_sfd__h720070 : + _theResult___fst_sfd__h758351 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13412 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13228, - (f1_exp__h719757 == 8'd255) ? + (f1_exp__h719754 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h758350, + _theResult___fst_exp__h758347, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13411 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13552 = - ((f3_exp__h798055 == 8'd0) ? - (f3_sfd__h798056[22] ? + ((f3_exp__h798052 == 8'd0) ? + (f3_sfd__h798053[22] ? 6'd2 : - (f3_sfd__h798056[21] ? + (f3_sfd__h798053[21] ? 6'd3 : - (f3_sfd__h798056[20] ? + (f3_sfd__h798053[20] ? 6'd4 : - (f3_sfd__h798056[19] ? + (f3_sfd__h798053[19] ? 6'd5 : - (f3_sfd__h798056[18] ? + (f3_sfd__h798053[18] ? 6'd6 : - (f3_sfd__h798056[17] ? + (f3_sfd__h798053[17] ? 6'd7 : - (f3_sfd__h798056[16] ? + (f3_sfd__h798053[16] ? 6'd8 : - (f3_sfd__h798056[15] ? + (f3_sfd__h798053[15] ? 6'd9 : - (f3_sfd__h798056[14] ? + (f3_sfd__h798053[14] ? 6'd10 : - (f3_sfd__h798056[13] ? + (f3_sfd__h798053[13] ? 6'd11 : - (f3_sfd__h798056[12] ? + (f3_sfd__h798053[12] ? 6'd12 : - (f3_sfd__h798056[11] ? + (f3_sfd__h798053[11] ? 6'd13 : - (f3_sfd__h798056[10] ? + (f3_sfd__h798053[10] ? 6'd14 : - (f3_sfd__h798056[9] ? + (f3_sfd__h798053[9] ? 6'd15 : - (f3_sfd__h798056[8] ? + (f3_sfd__h798053[8] ? 6'd16 : - (f3_sfd__h798056[7] ? + (f3_sfd__h798053[7] ? 6'd17 : - (f3_sfd__h798056[6] ? + (f3_sfd__h798053[6] ? 6'd18 : - (f3_sfd__h798056[5] ? + (f3_sfd__h798053[5] ? 6'd19 : - (f3_sfd__h798056[4] ? + (f3_sfd__h798053[4] ? 6'd20 : - (f3_sfd__h798056[3] ? + (f3_sfd__h798053[3] ? 6'd21 : - (f3_sfd__h798056[2] ? + (f3_sfd__h798053[2] ? 6'd22 : - (f3_sfd__h798056[1] ? + (f3_sfd__h798053[1] ? 6'd23 : - (f3_sfd__h798056[0] ? + (f3_sfd__h798053[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13943 = - (f3_exp__h798055 == 8'd255 && f3_sfd__h798056 != 23'd0 || - (f3_exp__h798055 == 8'd255 || f3_exp__h798055 == 8'd0) && - f3_sfd__h798056 == 23'd0) ? + (f3_exp__h798052 == 8'd255 && f3_sfd__h798053 != 23'd0 || + (f3_exp__h798052 == 8'd255 || f3_exp__h798052 == 8'd0) && + f3_sfd__h798053 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h798055 == 8'd0) ? + ((f3_exp__h798052 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13598 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13941) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14120 = - (f3_exp__h798055 == 8'd255 && f3_sfd__h798056 != 23'd0) ? - _theResult___snd_fst_sfd__h798371 : - _theResult___fst_sfd__h836511 ; + (f3_exp__h798052 == 8'd255 && f3_sfd__h798053 != 23'd0) ? + _theResult___snd_fst_sfd__h798368 : + _theResult___fst_sfd__h836508 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14121 = - { (f3_exp__h798055 == 8'd255) ? + { (f3_exp__h798052 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h836507, + _theResult___fst_exp__h836504, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14120 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14176 = - (f3_exp__h798055 == 8'd0) ? + (f3_exp__h798052 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -20801,85 +20801,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14148) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14175 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14177 = - (f3_exp__h798055 == 8'd255 && f3_sfd__h798056 != 23'd0 || - (f3_exp__h798055 == 8'd255 || f3_exp__h798055 == 8'd0) && - f3_sfd__h798056 == 23'd0) ? + (f3_exp__h798052 == 8'd255 && f3_sfd__h798053 != 23'd0 || + (f3_exp__h798052 == 8'd255 || f3_exp__h798052 == 8'd0) && + f3_sfd__h798053 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14176 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14322 = - ((f2_exp__h758751 == 8'd0) ? - (f2_sfd__h758752[22] ? + ((f2_exp__h758748 == 8'd0) ? + (f2_sfd__h758749[22] ? 6'd2 : - (f2_sfd__h758752[21] ? + (f2_sfd__h758749[21] ? 6'd3 : - (f2_sfd__h758752[20] ? + (f2_sfd__h758749[20] ? 6'd4 : - (f2_sfd__h758752[19] ? + (f2_sfd__h758749[19] ? 6'd5 : - (f2_sfd__h758752[18] ? + (f2_sfd__h758749[18] ? 6'd6 : - (f2_sfd__h758752[17] ? + (f2_sfd__h758749[17] ? 6'd7 : - (f2_sfd__h758752[16] ? + (f2_sfd__h758749[16] ? 6'd8 : - (f2_sfd__h758752[15] ? + (f2_sfd__h758749[15] ? 6'd9 : - (f2_sfd__h758752[14] ? + (f2_sfd__h758749[14] ? 6'd10 : - (f2_sfd__h758752[13] ? + (f2_sfd__h758749[13] ? 6'd11 : - (f2_sfd__h758752[12] ? + (f2_sfd__h758749[12] ? 6'd12 : - (f2_sfd__h758752[11] ? + (f2_sfd__h758749[11] ? 6'd13 : - (f2_sfd__h758752[10] ? + (f2_sfd__h758749[10] ? 6'd14 : - (f2_sfd__h758752[9] ? + (f2_sfd__h758749[9] ? 6'd15 : - (f2_sfd__h758752[8] ? + (f2_sfd__h758749[8] ? 6'd16 : - (f2_sfd__h758752[7] ? + (f2_sfd__h758749[7] ? 6'd17 : - (f2_sfd__h758752[6] ? + (f2_sfd__h758749[6] ? 6'd18 : - (f2_sfd__h758752[5] ? + (f2_sfd__h758749[5] ? 6'd19 : - (f2_sfd__h758752[4] ? + (f2_sfd__h758749[4] ? 6'd20 : - (f2_sfd__h758752[3] ? + (f2_sfd__h758749[3] ? 6'd21 : - (f2_sfd__h758752[2] ? + (f2_sfd__h758749[2] ? 6'd22 : - (f2_sfd__h758752[1] ? + (f2_sfd__h758749[1] ? 6'd23 : - (f2_sfd__h758752[0] ? + (f2_sfd__h758749[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14713 = - (f2_exp__h758751 == 8'd255 && f2_sfd__h758752 != 23'd0 || - (f2_exp__h758751 == 8'd255 || f2_exp__h758751 == 8'd0) && - f2_sfd__h758752 == 23'd0) ? + (f2_exp__h758748 == 8'd255 && f2_sfd__h758749 != 23'd0 || + (f2_exp__h758748 == 8'd255 || f2_exp__h758748 == 8'd0) && + f2_sfd__h758749 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h758751 == 8'd0) ? + ((f2_exp__h758748 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14368 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14711) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14890 = - (f2_exp__h758751 == 8'd255 && f2_sfd__h758752 != 23'd0) ? - _theResult___snd_fst_sfd__h759067 : - _theResult___fst_sfd__h797207 ; + (f2_exp__h758748 == 8'd255 && f2_sfd__h758749 != 23'd0) ? + _theResult___snd_fst_sfd__h759064 : + _theResult___fst_sfd__h797204 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14891 = - { (f2_exp__h758751 == 8'd255) ? + { (f2_exp__h758748 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h797203, + _theResult___fst_exp__h797200, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14890 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14945 = - (f2_exp__h758751 == 8'd0) ? + (f2_exp__h758748 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20889,15 +20889,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14917) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14944 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14946 = - (f2_exp__h758751 == 8'd255 && f2_sfd__h758752 != 23'd0 || - (f2_exp__h758751 == 8'd255 || f2_exp__h758751 == 8'd0) && - f2_sfd__h758752 == 23'd0) ? + (f2_exp__h758748 == 8'd255 && f2_sfd__h758749 != 23'd0 || + (f2_exp__h758748 == 8'd255 || f2_exp__h758748 == 8'd0) && + f2_sfd__h758749 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14945 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15001 = - (f1_exp__h719757 == 8'd0) ? + (f1_exp__h719754 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14980[4] : @@ -20905,7 +20905,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12887 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14997[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15042 = - (f2_exp__h758751 == 8'd0) ? + (f2_exp__h758748 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15021[4] : @@ -20913,7 +20913,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14372 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15038[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15086 = - (f3_exp__h798055 == 8'd0) ? + (f3_exp__h798052 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15065[4] : @@ -20921,7 +20921,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13602 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15082[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15101 = - (f1_exp__h719757 == 8'd0) ? + (f1_exp__h719754 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14980[3] : @@ -20929,7 +20929,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12887 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14997[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15111 = - (f2_exp__h758751 == 8'd0) ? + (f2_exp__h758748 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15021[3] : @@ -20937,7 +20937,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14372 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15038[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15122 = - (f3_exp__h798055 == 8'd0) ? + (f3_exp__h798052 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15065[3] : @@ -20945,70 +20945,70 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13602 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15082[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15141 = - (f1_exp__h719757 == 8'd0) ? + (f1_exp__h719754 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14980[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12886 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15139 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15155 = - (f2_exp__h758751 == 8'd0) ? + (f2_exp__h758748 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15021[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14371 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15153 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15170 = - (f3_exp__h798055 == 8'd0) ? + (f3_exp__h798052 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15065[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13601 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15168 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15187 = - (f1_exp__h719757 == 8'd0) ? + (f1_exp__h719754 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14980[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12886 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15185 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15199 = - (f2_exp__h758751 == 8'd0) ? + (f2_exp__h758748 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15021[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14371 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15197 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15212 = - (f3_exp__h798055 == 8'd0) ? + (f3_exp__h798052 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15065[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13601 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15210 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15229 = - (f1_exp__h719757 == 8'd0) ? + (f1_exp__h719754 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14980[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12886 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15227 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15241 = - (f2_exp__h758751 == 8'd0) ? + (f2_exp__h758748 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15021[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14371 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15239 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15254 = - (f3_exp__h798055 == 8'd0) ? + (f3_exp__h798052 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15065[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13601 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15252 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7322 = - _theResult_____2__h519720 == v__h519176 ; + _theResult_____2__h519716 == v__h519172 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7330 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7322 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7300 || @@ -21023,7 +21023,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7313 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7413 = - _theResult_____2__h530497 == v__h521196 ; + _theResult_____2__h530493 == v__h521192 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7422 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7413 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7394 || @@ -21052,9 +21052,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h526027 } ; + x__h526023 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7573 = - _theResult_____2__h537590 == v__h536915 ; + _theResult_____2__h537586 == v__h536911 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7581 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7573 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7553 || @@ -21069,7 +21069,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7566 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7657 = - _theResult_____2__h548225 == v__h539364 ; + _theResult_____2__h548221 == v__h539360 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7665 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7657 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7637 || @@ -21466,7 +21466,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7943 = - _theResult_____2__h565837 == v__h564163 ; + _theResult_____2__h565833 == v__h564159 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7951 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7943 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7924 || @@ -21481,7 +21481,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7937 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7861 = - _theResult_____2__h562058 == v__h560384 ; + _theResult_____2__h562054 == v__h560380 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7869 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7861 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7842 || @@ -21499,12 +21499,12 @@ module mkCore(CLK, (csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h1009088[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1009091 } : - { x__h1009088[11:3], - x__h1009109[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1009091[13:3], - x__h1009109[2:0] } ; + { x__h1009083[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1009086 } : + { x__h1009083[11:3], + x__h1009104[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1009086[13:3], + x__h1009104[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0337_BITS__ETC___d21312 = IF_fetchStage_pipelines_0_first__0337_BITS_267_ETC___d21303 ? !csrf_rg_dcsr[2] && @@ -21745,27 +21745,27 @@ module mkCore(CLK, 4'd0 : IF_IF_renameStage_rg_m_halt_req_0364_BIT_4_036_ETC___d21054 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958 = - { INV_x85142_BITS_108_TO_90__q34[0] ? x__h185262 : 6'd0, - x__h185422, - x__h185442 } ; + { INV_x85141_BITS_108_TO_90__q34[0] ? x__h185261 : 6'd0, + x__h185421, + x__h185441 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126 = - { INV_x01306_BITS_108_TO_90__q36[0] ? x__h204325 : 6'd0, - x__h204485, - x__h204505 } ; + { INV_x01305_BITS_108_TO_90__q36[0] ? x__h204324 : 6'd0, + x__h204484, + x__h204504 } ; assign IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22727 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h1003153 : + x__h1003148 : 6'd0 ; assign IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22808 = - x__h1003333[13:11] < repBound__h1005803 ; + x__h1003328[13:11] < repBound__h1005798 ; assign IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22810 = - pc_addrBits__h1002944[13:11] < repBound__h1005803 ; + pc_addrBits__h1002939[13:11] < repBound__h1005798 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19814 = - tb__h911885 < repBound__h911888 ; + tb__h911881 < repBound__h911884 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19815 = - x__h911827[13:11] < repBound__h911888 ; + x__h911823[13:11] < repBound__h911884 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19817 = - cr_addrBits__h911420[13:11] < repBound__h911888 ; + cr_addrBits__h911416[13:11] < repBound__h911884 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19827 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19817, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19814 == @@ -21783,11 +21783,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19878 = - tb__h912433 < repBound__h912436 ; + tb__h912429 < repBound__h912432 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19879 = - x__h912375[13:11] < repBound__h912436 ; + x__h912371[13:11] < repBound__h912432 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19881 = - cr_addrBits__h911968[13:11] < repBound__h912436 ; + cr_addrBits__h911964[13:11] < repBound__h912432 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19891 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19881, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9503__ETC___d19878 == @@ -21805,11 +21805,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17676 = - tb__h871908 < repBound__h871911 ; + tb__h871905 < repBound__h871908 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17677 = - x__h871850[13:11] < repBound__h871911 ; + x__h871847[13:11] < repBound__h871908 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17679 = - cr_addrBits__h871443[13:11] < repBound__h871911 ; + cr_addrBits__h871440[13:11] < repBound__h871908 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17689 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17679, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17676 == @@ -21827,11 +21827,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17740 = - tb__h872456 < repBound__h872459 ; + tb__h872453 < repBound__h872456 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17741 = - x__h872398[13:11] < repBound__h872459 ; + x__h872395[13:11] < repBound__h872456 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17743 = - cr_addrBits__h871991[13:11] < repBound__h872459 ; + cr_addrBits__h871988[13:11] < repBound__h872456 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17753 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17743, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7365__ETC___d17740 == @@ -21850,26 +21850,26 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h219296 : + x__h219295 : 6'd0, - x__h219456, - x__h219476 } ; + x__h219455, + x__h219475 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_235__ETC___d1275 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h128337 : + x__h128336 : 6'd0, - x__h128497, - x__h128517 } ; + x__h128496, + x__h128516 } ; assign IF_INV_mmio_dataRespQ_data_0_393_BITS_108_TO_9_ETC___d1437 = { INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h141481 : + x__h141480 : 6'd0, - x__h141641, - x__h141661 } ; + x__h141640, + x__h141660 } ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12883 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 || - _theResult___fst_exp__h739145 == 11'd2047) ? + _theResult___fst_exp__h739142 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21877,12 +21877,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard31184_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard31181_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13598 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 || - _theResult___fst_exp__h817302 == 11'd2047) ? + _theResult___fst_exp__h817299 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21890,12 +21890,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09341_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 : + CASE_guard09338_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14368 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 || - _theResult___fst_exp__h777998 == 11'd2047) ? + _theResult___fst_exp__h777995 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21903,7 +21903,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 : + CASE_guard70034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3__ETC___d20975 = IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404[0] ? @@ -23618,48 +23618,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15139 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12887 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14997[2] : - _theResult___fst_exp__h758338 == 11'd2047 && - _theResult___fst_sfd__h758339 == 52'd0 ; + _theResult___fst_exp__h758335 == 11'd2047 && + _theResult___fst_sfd__h758336 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15153 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14372 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15038[2] : - _theResult___fst_exp__h797191 == 11'd2047 && - _theResult___fst_sfd__h797192 == 52'd0 ; + _theResult___fst_exp__h797188 == 11'd2047 && + _theResult___fst_sfd__h797189 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15168 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13602 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15082[2] : - _theResult___fst_exp__h836495 == 11'd2047 && - _theResult___fst_sfd__h836496 == 52'd0 ; + _theResult___fst_exp__h836492 == 11'd2047 && + _theResult___fst_sfd__h836493 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15185 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12887 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14997[1] : - _theResult___fst_exp__h757555 == 11'd0 && - guard__h749565 != 2'b0 ; + _theResult___fst_exp__h757552 == 11'd0 && + guard__h749562 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15197 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14372 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15038[1] : - _theResult___fst_exp__h796408 == 11'd0 && - guard__h788418 != 2'b0 ; + _theResult___fst_exp__h796405 == 11'd0 && + guard__h788415 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15210 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13602 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15082[1] : - _theResult___fst_exp__h835712 == 11'd0 && - guard__h827722 != 2'b0 ; + _theResult___fst_exp__h835709 == 11'd0 && + guard__h827719 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15227 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12887 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14997[0] : - _theResult___fst_exp__h757555 != 11'd2047 && - guard__h749565 != 2'b0 ; + _theResult___fst_exp__h757552 != 11'd2047 && + guard__h749562 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15239 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14372 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15038[0] : - _theResult___fst_exp__h796408 != 11'd2047 && - guard__h788418 != 2'b0 ; + _theResult___fst_exp__h796405 != 11'd2047 && + guard__h788415 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15252 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13602 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15082[0] : - _theResult___fst_exp__h835712 != 11'd2047 && - guard__h827722 != 2'b0 ; + _theResult___fst_exp__h835709 != 11'd2047 && + guard__h827719 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10465 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] == 8'd0) ? @@ -23669,35 +23669,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10692 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10146 ? - ((_theResult___fst_exp__h652431 == 8'd255) ? + ((_theResult___fst_exp__h652428 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10677) : - ((_theResult___fst_exp__h661116 == 8'd255) ? + ((_theResult___fst_exp__h661113 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10690) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10729 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10146 ? - ((_theResult___fst_exp__h652431 == 8'd255) ? + ((_theResult___fst_exp__h652428 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10720) : - ((_theResult___fst_exp__h661116 == 8'd255) ? + ((_theResult___fst_exp__h661113 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10727) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10825 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10146 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10796[2] : - _theResult___fst_exp__h661664 == 8'd255 && - _theResult___fst_sfd__h661665 == 23'd0 ; + _theResult___fst_exp__h661661 == 8'd255 && + _theResult___fst_sfd__h661662 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10838 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10146 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10796[1] : - _theResult___fst_exp__h661116 == 8'd0 && - guard__h653039 != 2'b0 ; + _theResult___fst_exp__h661113 == 8'd0 && + guard__h653036 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10851 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10146 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10796[0] : - _theResult___fst_exp__h661116 != 8'd255 && - guard__h653039 != 2'b0 ; + _theResult___fst_exp__h661113 != 8'd255 && + guard__h653036 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11862 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] == 8'd0) ? @@ -23707,35 +23707,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12089 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11543 ? - ((_theResult___fst_exp__h698178 == 8'd255) ? + ((_theResult___fst_exp__h698175 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12074) : - ((_theResult___fst_exp__h706863 == 8'd255) ? + ((_theResult___fst_exp__h706860 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12087) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12126 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11543 ? - ((_theResult___fst_exp__h698178 == 8'd255) ? + ((_theResult___fst_exp__h698175 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12117) : - ((_theResult___fst_exp__h706863 == 8'd255) ? + ((_theResult___fst_exp__h706860 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12124) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12222 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11543 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12193[2] : - _theResult___fst_exp__h707411 == 8'd255 && - _theResult___fst_sfd__h707412 == 23'd0 ; + _theResult___fst_exp__h707408 == 8'd255 && + _theResult___fst_sfd__h707409 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12235 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11543 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12193[1] : - _theResult___fst_exp__h706863 == 8'd0 && - guard__h698786 != 2'b0 ; + _theResult___fst_exp__h706860 == 8'd0 && + guard__h698783 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12248 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11543 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12193[0] : - _theResult___fst_exp__h706863 != 8'd255 && - guard__h698786 != 2'b0 ; + _theResult___fst_exp__h706860 != 8'd255 && + guard__h698783 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9068 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] == 8'd0) ? @@ -23745,41 +23745,41 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9295 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8749 ? - ((_theResult___fst_exp__h606682 == 8'd255) ? + ((_theResult___fst_exp__h606679 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9280) : - ((_theResult___fst_exp__h615367 == 8'd255) ? + ((_theResult___fst_exp__h615364 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9293) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9332 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8749 ? - ((_theResult___fst_exp__h606682 == 8'd255) ? + ((_theResult___fst_exp__h606679 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9323) : - ((_theResult___fst_exp__h615367 == 8'd255) ? + ((_theResult___fst_exp__h615364 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9330) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9428 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8749 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9399[2] : - _theResult___fst_exp__h615915 == 8'd255 && - _theResult___fst_sfd__h615916 == 23'd0 ; + _theResult___fst_exp__h615912 == 8'd255 && + _theResult___fst_sfd__h615913 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9441 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8749 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9399[1] : - _theResult___fst_exp__h615367 == 8'd0 && - guard__h607290 != 2'b0 ; + _theResult___fst_exp__h615364 == 8'd0 && + guard__h607287 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9454 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8749 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9399[0] : - _theResult___fst_exp__h615367 != 8'd255 && - guard__h607290 != 2'b0 ; + _theResult___fst_exp__h615364 != 8'd255 && + guard__h607287 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__652_BI_ETC___d4096 = - offset__h245449[63] ? - x__h245598[13:0] >= toBounds__h245477 && - repBoundBits__h245474 != + offset__h245448[63] ? + x__h245597[13:0] >= toBounds__h245476 && + repBoundBits__h245473 != coreFix_memExe_regToExeQ$first[316:303] : - x__h245598[13:0] < toBoundsM1__h245478 ; + x__h245597[13:0] < toBoundsM1__h245477 ; assign IF_basicExec_7757_BIT_325_7768_THEN_basicExec__ETC___d17776 = basicExec___d17757[325] ? { basicExec___d17757[316:308], @@ -23869,24 +23869,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d18674 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d18874 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h898574 : + res_address__h898570 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18872 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d18889 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h898575 : + res_addrBits__h898571 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18887 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19440 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h904588 : + thin_reserved__h904584 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h904589 : + thin_otype__h904585 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19428, @@ -23895,7 +23895,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19441 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h904764 : + thin_perms_soft__h904760 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19286, @@ -23926,18 +23926,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19440 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19442 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h904584 : + thin_address__h904580 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h904585 : + thin_addrBits__h904581 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19441 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19463 = - thin_bounds_topBits__h905990[13:11] < repBound__h906106 ; + thin_bounds_topBits__h905986[13:11] < repBound__h906102 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19465 = - thin_bounds_baseBits__h905991[13:11] < repBound__h906106 ; + thin_bounds_baseBits__h905987[13:11] < repBound__h906102 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19468 = - thin_addrBits__h904585[13:11] < repBound__h906106 ; + thin_addrBits__h904581[13:11] < repBound__h906102 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__0026_BIT__ETC___d20172 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -24150,24 +24150,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d16003 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d16431 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h854911 : + res_address__h854908 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16429 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d16446 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h854912 : + res_addrBits__h854909 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16444 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17276 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h863692 : + thin_reserved__h863689 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h863693 : + thin_otype__h863690 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17251, @@ -24176,7 +24176,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17277 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h863940 : + thin_perms_soft__h863937 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d16914, @@ -24207,18 +24207,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17276 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17278 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h863688 : + thin_address__h863685 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h863689 : + thin_addrBits__h863686 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17277 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17325 = - thin_bounds_topBits__h865686[13:11] < repBound__h865834 ; + thin_bounds_topBits__h865683[13:11] < repBound__h865831 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17327 = - thin_bounds_baseBits__h865687[13:11] < repBound__h865834 ; + thin_bounds_baseBits__h865684[13:11] < repBound__h865831 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17330 = - thin_addrBits__h863689[13:11] < repBound__h865834 ; + thin_addrBits__h863686[13:11] < repBound__h865831 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__7888_BIT__ETC___d18035 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -24977,8 +24977,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20278 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h922326 : - w__h922321 ; + result__h922321 : + w__h922316 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5016 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25452,15 +25452,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__689_BIT_1_ETC___d3641 } ; assign IF_coreFix_memExe_dispToRegQ_first__689_BIT_12_ETC___d3085 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h238159 : + res_addrBits__h238158 : ((coreFix_memExe_dispToRegQ$first[109] && coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3083 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__689_BIT_12_ETC___d3329 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h238158 : - x__h238581, + res_address__h238157 : + x__h238580, IF_coreFix_memExe_dispToRegQ_first__689_BIT_12_ETC___d3085, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25599,13 +25599,13 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__502_BIT_113_517_ETC___d2084 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4250 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h245459[3:0] != 4'd0 : + pointer__h245458[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h245459[2:0] != 3'd0 : + pointer__h245458[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h245459[1:0] != 2'd0 : + pointer__h245458[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h245459[0])), + pointer__h245458[0])), capChecks___d4161[11:5], CASE_capChecks_161_BITS_4_TO_0_0_capChecks_161_ETC__q289, prepareBoundsCheck___d4245 } ; @@ -25727,7 +25727,7 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; assign IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d22999 = - ((newAddrDiff__h1008362 == 64'd0) ? + ((newAddrDiff__h1008357 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d22975 ? 2'd3 : @@ -25744,12 +25744,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d23002 = IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d22999 && - (newAddrDiff__h1008362 == 64'd0 || + (newAddrDiff__h1008357 == 64'd0 || csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d22975 || - newAddrDiff__h1008362 == + newAddrDiff__h1008357 == _18446744073709551615_SL_csrf_mtcc_reg_read__68_ETC___d22978) ; assign IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d23024 = - ((newAddrDiff__h1008706 == 64'd0) ? + ((newAddrDiff__h1008701 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d23008 ? 2'd3 : @@ -25766,12 +25766,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d23027 = IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d23024 && - (newAddrDiff__h1008706 == 64'd0 || + (newAddrDiff__h1008701 == 64'd0 || csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d23008 || - newAddrDiff__h1008706 == + newAddrDiff__h1008701 == _18446744073709551615_SL_csrf_mtcc_reg_read__68_ETC___d22978) ; assign IF_csrf_mtcc_reg_read__6810_BIT_86_2960_AND_NO_ETC___d23030 = - (csrf_mtcc_reg[86] && cause_interrupt__h1003522) ? + (csrf_mtcc_reg[86] && cause_interrupt__h1003517) ? (NOT_csrf_mtcc_reg_read__6810_BITS_33_TO_28_296_ETC___d22964 || IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d23002) && csrf_mtcc_reg[152] : @@ -25779,9 +25779,9 @@ module mkCore(CLK, IF_csrf_mtcc_reg_read__6810_BITS_149_TO_86_296_ETC___d23027) && csrf_mtcc_reg[152] ; assign IF_csrf_mtcc_reg_read__6810_BIT_86_2960_AND_NO_ETC___d23064 = - (csrf_mtcc_reg[86] && cause_interrupt__h1003522) ? - address__h1007682 : - base__h1007647 ; + (csrf_mtcc_reg[86] && cause_interrupt__h1003517) ? + address__h1007677 : + base__h1007642 ; assign IF_csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_c_ETC___d23035 = csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 ? { IF_csrf_stcc_reg_read__6801_BIT_86_2883_AND_NO_ETC___d22955, @@ -25901,7 +25901,7 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; assign IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22924 = - ((newAddrDiff__h1007705 == 64'd0) ? + ((newAddrDiff__h1007700 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22900 ? 2'd3 : @@ -25918,12 +25918,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22927 = IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22924 && - (newAddrDiff__h1007705 == 64'd0 || + (newAddrDiff__h1007700 == 64'd0 || csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22900 || - newAddrDiff__h1007705 == + newAddrDiff__h1007700 == _18446744073709551615_SL_csrf_stcc_reg_read__68_ETC___d22903) ; assign IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22949 = - ((newAddrDiff__h1008049 == 64'd0) ? + ((newAddrDiff__h1008044 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22933 ? 2'd3 : @@ -25940,12 +25940,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22952 = IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22949 && - (newAddrDiff__h1008049 == 64'd0 || + (newAddrDiff__h1008044 == 64'd0 || csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22933 || - newAddrDiff__h1008049 == + newAddrDiff__h1008044 == _18446744073709551615_SL_csrf_stcc_reg_read__68_ETC___d22903) ; assign IF_csrf_stcc_reg_read__6801_BIT_86_2883_AND_NO_ETC___d22955 = - (csrf_stcc_reg[86] && cause_interrupt__h1003522) ? + (csrf_stcc_reg[86] && cause_interrupt__h1003517) ? (NOT_csrf_stcc_reg_read__6801_BITS_33_TO_28_288_ETC___d22887 || IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22927) && csrf_stcc_reg[152] : @@ -25953,9 +25953,9 @@ module mkCore(CLK, IF_csrf_stcc_reg_read__6801_BITS_149_TO_86_288_ETC___d22952) && csrf_stcc_reg[152] ; assign IF_csrf_stcc_reg_read__6801_BIT_86_2883_AND_NO_ETC___d23063 = - (csrf_stcc_reg[86] && cause_interrupt__h1003522) ? - address__h1007632 : - base__h1007593 ; + (csrf_stcc_reg[86] && cause_interrupt__h1003517) ? + address__h1007627 : + base__h1007588 ; assign IF_fetchStage_RDY_pipelines_0_first__0334_AND__ETC___d21268 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[267:265] != 3'd1 || @@ -26361,13 +26361,13 @@ module mkCore(CLK, 2'd3) } ; assign IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23678 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1022111 : + y_avValue_snd_snd_snd_snd_snd__h1022106 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23788 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1022095 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1022090 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23810 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1022105 : + y_avValue_snd_snd_snd_fst__h1022100 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__3560_THEN_IF_NOT_rob__ETC___d23802 = rob$deqPort_1_canDeq ? @@ -26501,7 +26501,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19123) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19145 = sbCons$lazyLookup_0_get[3] ? - repBound__h903761 : + repBound__h903757 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8454_8_ETC___d18481 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__845_ETC___d19141) ; @@ -26532,7 +26532,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19242 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h906088, + repBound__h906084, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19217, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19218, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19230 } : @@ -26667,7 +26667,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__578_ETC___d16680) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16702 = sbCons$lazyLookup_1_get[3] ? - repBound__h862472 : + repBound__h862469 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5783_5_ETC___d15810 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__578_ETC___d16698) ; @@ -26698,7 +26698,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16799 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h865816, + repBound__h865813, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16775, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16787 } : @@ -26833,7 +26833,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__710_7_ETC___d3319) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3341 = sbCons$lazyLookup_3_get[3] ? - repBound__h240153 : + repBound__h240152 : (NOT_coreFix_memExe_bypassWire_0_whas__710_716__ETC___d2737 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__710_7_ETC___d3337) ; @@ -26989,7 +26989,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__710_7_ETC___d3579) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3596 = sbCons$lazyLookup_3_get[2] ? - repBound__h241838 : + repBound__h241837 : (NOT_coreFix_memExe_bypassWire_0_whas__710_716__ETC___d2768 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__710_7_ETC___d3592) ; @@ -27017,64 +27017,64 @@ module mkCore(CLK, (NOT_coreFix_memExe_bypassWire_0_whas__710_716__ETC___d2768 ? coreFix_aluExe_0_bypassWire_3$wget[3:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__710_7_ETC___d3635) ; - assign IF_sfdin06676_BIT_33_THEN_2_ELSE_0__q51 = - sfdin__h606676[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin26873_BIT_4_THEN_2_ELSE_0__q167 = - sfdin__h826873[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin34659_BIT_33_THEN_2_ELSE_0__q76 = - sfdin__h634659[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin48716_BIT_4_THEN_2_ELSE_0__q150 = - sfdin__h748716[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin52425_BIT_33_THEN_2_ELSE_0__q86 = - sfdin__h652425[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin80406_BIT_33_THEN_2_ELSE_0__q111 = - sfdin__h680406[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin87569_BIT_4_THEN_2_ELSE_0__q190 = - sfdin__h787569[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin88910_BIT_33_THEN_2_ELSE_0__q41 = - sfdin__h588910[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin98172_BIT_33_THEN_2_ELSE_0__q121 = - sfdin__h698172[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06809_BIT_33_THEN_2_ELSE_0__q126 = - _theResult___snd__h706809[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd15313_BIT_33_THEN_2_ELSE_0__q56 = - _theResult___snd__h615313[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17253_BIT_4_THEN_2_ELSE_0__q163 = - _theResult___snd__h817253[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd35658_BIT_4_THEN_2_ELSE_0__q170 = - _theResult___snd__h835658[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd39096_BIT_4_THEN_2_ELSE_0__q146 = - _theResult___snd__h739096[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd43272_BIT_33_THEN_2_ELSE_0__q78 = - _theResult___snd__h643272[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd57501_BIT_4_THEN_2_ELSE_0__q153 = - _theResult___snd__h757501[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd61062_BIT_33_THEN_2_ELSE_0__q91 = - _theResult___snd__h661062[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77949_BIT_4_THEN_2_ELSE_0__q186 = - _theResult___snd__h777949[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd89019_BIT_33_THEN_2_ELSE_0__q113 = - _theResult___snd__h689019[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd96354_BIT_4_THEN_2_ELSE_0__q193 = - _theResult___snd__h796354[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd97523_BIT_33_THEN_2_ELSE_0__q43 = - _theResult___snd__h597523[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin06673_BIT_33_THEN_2_ELSE_0__q51 = + sfdin__h606673[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin26870_BIT_4_THEN_2_ELSE_0__q167 = + sfdin__h826870[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin34656_BIT_33_THEN_2_ELSE_0__q76 = + sfdin__h634656[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin48713_BIT_4_THEN_2_ELSE_0__q150 = + sfdin__h748713[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin52422_BIT_33_THEN_2_ELSE_0__q86 = + sfdin__h652422[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin80403_BIT_33_THEN_2_ELSE_0__q111 = + sfdin__h680403[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin87566_BIT_4_THEN_2_ELSE_0__q190 = + sfdin__h787566[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin88907_BIT_33_THEN_2_ELSE_0__q41 = + sfdin__h588907[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin98169_BIT_33_THEN_2_ELSE_0__q121 = + sfdin__h698169[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06806_BIT_33_THEN_2_ELSE_0__q126 = + _theResult___snd__h706806[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd15310_BIT_33_THEN_2_ELSE_0__q56 = + _theResult___snd__h615310[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17250_BIT_4_THEN_2_ELSE_0__q163 = + _theResult___snd__h817250[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd35655_BIT_4_THEN_2_ELSE_0__q170 = + _theResult___snd__h835655[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd39093_BIT_4_THEN_2_ELSE_0__q146 = + _theResult___snd__h739093[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd43269_BIT_33_THEN_2_ELSE_0__q78 = + _theResult___snd__h643269[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd57498_BIT_4_THEN_2_ELSE_0__q153 = + _theResult___snd__h757498[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd61059_BIT_33_THEN_2_ELSE_0__q91 = + _theResult___snd__h661059[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd77946_BIT_4_THEN_2_ELSE_0__q186 = + _theResult___snd__h777946[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd89016_BIT_33_THEN_2_ELSE_0__q113 = + _theResult___snd__h689016[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd96351_BIT_4_THEN_2_ELSE_0__q193 = + _theResult___snd__h796351[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd97520_BIT_33_THEN_2_ELSE_0__q43 = + _theResult___snd__h597520[33] ? 2'd2 : 2'd0 ; assign INV_commitStage_commitTrap_BITS_217_TO_199__q15 = ~commitStage_commitTrap[217:199] ; assign INV_coreFix_aluExe_0_regToExeQ_first__9503_BIT_ETC___d19807 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h911634 : + x__h911630 : 6'd0, - x__h911807, - x__h911827 } ; + x__h911803, + x__h911823 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9503_BIT_ETC___d19871 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h912182 : + x__h912178 : 6'd0, - x__h912355, - x__h912375 } ; + x__h912351, + x__h912371 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -27082,17 +27082,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7365_BIT_ETC___d17669 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h871657 : + x__h871654 : 6'd0, - x__h871830, - x__h871850 } ; + x__h871827, + x__h871847 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7365_BIT_ETC___d17733 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h872205 : + x__h872202 : 6'd0, - x__h872378, - x__h872398 } ; + x__h872375, + x__h872395 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -27103,8 +27103,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x01306_BITS_108_TO_90__q36 = ~x__h201306[108:90] ; - assign INV_x85142_BITS_108_TO_90__q34 = ~x__h185142[108:90] ; + assign INV_x01305_BITS_108_TO_90__q36 = ~x__h201305[108:90] ; + assign INV_x85141_BITS_108_TO_90__q34 = ~x__h185141[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10819 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9605 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9606 ? @@ -27193,130 +27193,130 @@ module mkCore(CLK, !checkForException___d21674[13] && NOT_csrf_fs_reg_read__6160_EQ_0_0710_0711_OR_N_ETC___d21699 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__3556_3557_OR__ETC___d23807 = - (fflags__h1022678 & csrf_fflags_reg) != fflags__h1022678 || - !r__h859151 && + (fflags__h1022673 & csrf_fflags_reg) != fflags__h1022673 || + !r__h859148 && (IF_rob_deqPort_1_canDeq__3560_THEN_IF_NOT_rob__ETC___d23802 || - fflags__h1022678 != 5'd0) ; + fflags__h1022673 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12795 = - !f1_sfd__h719758[21] && !f1_sfd__h719758[20] && - !f1_sfd__h719758[19] && - !f1_sfd__h719758[18] && - !f1_sfd__h719758[17] && - !f1_sfd__h719758[16] && - !f1_sfd__h719758[15] && - !f1_sfd__h719758[14] && - !f1_sfd__h719758[13] && - !f1_sfd__h719758[12] && - !f1_sfd__h719758[11] && - !f1_sfd__h719758[10] && - !f1_sfd__h719758[9] && - !f1_sfd__h719758[8] && - !f1_sfd__h719758[7] && - !f1_sfd__h719758[6] && - !f1_sfd__h719758[5] && - !f1_sfd__h719758[4] && - !f1_sfd__h719758[3] && - !f1_sfd__h719758[2] && - !f1_sfd__h719758[1] && - !f1_sfd__h719758[0] ; + !f1_sfd__h719755[21] && !f1_sfd__h719755[20] && + !f1_sfd__h719755[19] && + !f1_sfd__h719755[18] && + !f1_sfd__h719755[17] && + !f1_sfd__h719755[16] && + !f1_sfd__h719755[15] && + !f1_sfd__h719755[14] && + !f1_sfd__h719755[13] && + !f1_sfd__h719755[12] && + !f1_sfd__h719755[11] && + !f1_sfd__h719755[10] && + !f1_sfd__h719755[9] && + !f1_sfd__h719755[8] && + !f1_sfd__h719755[7] && + !f1_sfd__h719755[6] && + !f1_sfd__h719755[5] && + !f1_sfd__h719755[4] && + !f1_sfd__h719755[3] && + !f1_sfd__h719755[2] && + !f1_sfd__h719755[1] && + !f1_sfd__h719755[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13525 = - !f3_sfd__h798056[21] && !f3_sfd__h798056[20] && - !f3_sfd__h798056[19] && - !f3_sfd__h798056[18] && - !f3_sfd__h798056[17] && - !f3_sfd__h798056[16] && - !f3_sfd__h798056[15] && - !f3_sfd__h798056[14] && - !f3_sfd__h798056[13] && - !f3_sfd__h798056[12] && - !f3_sfd__h798056[11] && - !f3_sfd__h798056[10] && - !f3_sfd__h798056[9] && - !f3_sfd__h798056[8] && - !f3_sfd__h798056[7] && - !f3_sfd__h798056[6] && - !f3_sfd__h798056[5] && - !f3_sfd__h798056[4] && - !f3_sfd__h798056[3] && - !f3_sfd__h798056[2] && - !f3_sfd__h798056[1] && - !f3_sfd__h798056[0] ; + !f3_sfd__h798053[21] && !f3_sfd__h798053[20] && + !f3_sfd__h798053[19] && + !f3_sfd__h798053[18] && + !f3_sfd__h798053[17] && + !f3_sfd__h798053[16] && + !f3_sfd__h798053[15] && + !f3_sfd__h798053[14] && + !f3_sfd__h798053[13] && + !f3_sfd__h798053[12] && + !f3_sfd__h798053[11] && + !f3_sfd__h798053[10] && + !f3_sfd__h798053[9] && + !f3_sfd__h798053[8] && + !f3_sfd__h798053[7] && + !f3_sfd__h798053[6] && + !f3_sfd__h798053[5] && + !f3_sfd__h798053[4] && + !f3_sfd__h798053[3] && + !f3_sfd__h798053[2] && + !f3_sfd__h798053[1] && + !f3_sfd__h798053[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14295 = - !f2_sfd__h758752[21] && !f2_sfd__h758752[20] && - !f2_sfd__h758752[19] && - !f2_sfd__h758752[18] && - !f2_sfd__h758752[17] && - !f2_sfd__h758752[16] && - !f2_sfd__h758752[15] && - !f2_sfd__h758752[14] && - !f2_sfd__h758752[13] && - !f2_sfd__h758752[12] && - !f2_sfd__h758752[11] && - !f2_sfd__h758752[10] && - !f2_sfd__h758752[9] && - !f2_sfd__h758752[8] && - !f2_sfd__h758752[7] && - !f2_sfd__h758752[6] && - !f2_sfd__h758752[5] && - !f2_sfd__h758752[4] && - !f2_sfd__h758752[3] && - !f2_sfd__h758752[2] && - !f2_sfd__h758752[1] && - !f2_sfd__h758752[0] ; + !f2_sfd__h758749[21] && !f2_sfd__h758749[20] && + !f2_sfd__h758749[19] && + !f2_sfd__h758749[18] && + !f2_sfd__h758749[17] && + !f2_sfd__h758749[16] && + !f2_sfd__h758749[15] && + !f2_sfd__h758749[14] && + !f2_sfd__h758749[13] && + !f2_sfd__h758749[12] && + !f2_sfd__h758749[11] && + !f2_sfd__h758749[10] && + !f2_sfd__h758749[9] && + !f2_sfd__h758749[8] && + !f2_sfd__h758749[7] && + !f2_sfd__h758749[6] && + !f2_sfd__h758749[5] && + !f2_sfd__h758749[4] && + !f2_sfd__h758749[3] && + !f2_sfd__h758749[2] && + !f2_sfd__h758749[1] && + !f2_sfd__h758749[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15004 = - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 == 23'd0) && - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 != 23'd0) && - (f1_exp__h719757 != 8'd0 || f1_sfd__h719758 != 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 == 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 != 23'd0) && + (f1_exp__h719754 != 8'd0 || f1_sfd__h719755 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15001 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15046 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15004 | - ((f2_exp__h758751 != 8'd255 || f2_sfd__h758752 == 23'd0) && - (f2_exp__h758751 != 8'd255 || f2_sfd__h758752 != 23'd0) && - (f2_exp__h758751 != 8'd0 || f2_sfd__h758752 != 23'd0) && + ((f2_exp__h758748 != 8'd255 || f2_sfd__h758749 == 23'd0) && + (f2_exp__h758748 != 8'd255 || f2_sfd__h758749 != 23'd0) && + (f2_exp__h758748 != 8'd0 || f2_sfd__h758749 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15042) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15104 = - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 == 23'd0) && - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 != 23'd0) && - (f1_exp__h719757 != 8'd0 || f1_sfd__h719758 != 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 == 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 != 23'd0) && + (f1_exp__h719754 != 8'd0 || f1_sfd__h719755 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15101 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15104 | - ((f2_exp__h758751 != 8'd255 || f2_sfd__h758752 == 23'd0) && - (f2_exp__h758751 != 8'd255 || f2_sfd__h758752 != 23'd0) && - (f2_exp__h758751 != 8'd0 || f2_sfd__h758752 != 23'd0) && + ((f2_exp__h758748 != 8'd255 || f2_sfd__h758749 == 23'd0) && + (f2_exp__h758748 != 8'd255 || f2_sfd__h758749 != 23'd0) && + (f2_exp__h758748 != 8'd0 || f2_sfd__h758749 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15111) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 = - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 == 23'd0) && - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 != 23'd0) && - (f1_exp__h719757 != 8'd0 || f1_sfd__h719758 != 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 == 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 != 23'd0) && + (f1_exp__h719754 != 8'd0 || f1_sfd__h719755 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15141 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15159 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 | - ((f2_exp__h758751 != 8'd255 || f2_sfd__h758752 == 23'd0) && - (f2_exp__h758751 != 8'd255 || f2_sfd__h758752 != 23'd0) && - (f2_exp__h758751 != 8'd0 || f2_sfd__h758752 != 23'd0) && + ((f2_exp__h758748 != 8'd255 || f2_sfd__h758749 == 23'd0) && + (f2_exp__h758748 != 8'd255 || f2_sfd__h758749 != 23'd0) && + (f2_exp__h758748 != 8'd0 || f2_sfd__h758749 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15155) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15190 = - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 == 23'd0) && - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 != 23'd0) && - (f1_exp__h719757 != 8'd0 || f1_sfd__h719758 != 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 == 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 != 23'd0) && + (f1_exp__h719754 != 8'd0 || f1_sfd__h719755 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15187 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15203 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15190 | - ((f2_exp__h758751 != 8'd255 || f2_sfd__h758752 == 23'd0) && - (f2_exp__h758751 != 8'd255 || f2_sfd__h758752 != 23'd0) && - (f2_exp__h758751 != 8'd0 || f2_sfd__h758752 != 23'd0) && + ((f2_exp__h758748 != 8'd255 || f2_sfd__h758749 == 23'd0) && + (f2_exp__h758748 != 8'd255 || f2_sfd__h758749 != 23'd0) && + (f2_exp__h758748 != 8'd0 || f2_sfd__h758749 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15199) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15232 = - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 == 23'd0) && - (f1_exp__h719757 != 8'd255 || f1_sfd__h719758 != 23'd0) && - (f1_exp__h719757 != 8'd0 || f1_sfd__h719758 != 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 == 23'd0) && + (f1_exp__h719754 != 8'd255 || f1_sfd__h719755 != 23'd0) && + (f1_exp__h719754 != 8'd0 || f1_sfd__h719755 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15229 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15245 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15232 | - ((f2_exp__h758751 != 8'd255 || f2_sfd__h758752 == 23'd0) && - (f2_exp__h758751 != 8'd255 || f2_sfd__h758752 != 23'd0) && - (f2_exp__h758751 != 8'd0 || f2_sfd__h758752 != 23'd0) && + ((f2_exp__h758748 != 8'd255 || f2_sfd__h758749 == 23'd0) && + (f2_exp__h758748 != 8'd255 || f2_sfd__h758749 != 23'd0) && + (f2_exp__h758748 != 8'd0 || f2_sfd__h758749 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15241) ; assign NOT_commitStage_commitTrap_2410_BITS_44_TO_43__ETC___d22681 = commitStage_commitTrap[44:43] != 2'd0 && @@ -28300,7 +28300,7 @@ module mkCore(CLK, SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1273_co_ETC___d21306 ; assign NOT_fetchStage_pipelines_0_first__0337_BITS_46_ETC___d22109 = fetchStage$pipelines_0_first[461:333] != - fallthrough_pc__h946297 ; + fallthrough_pc__h946292 ; assign NOT_fetchStage_pipelines_0_first__0337_BIT_69__ETC___d20796 = !fetchStage$pipelines_0_first[69] && !IF_IF_NOT_csrf_prv_reg_read__0367_EQ_3_0368_03_ETC___d20404[0] && @@ -28380,7 +28380,7 @@ module mkCore(CLK, SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__033_ETC___d21986 ; assign NOT_fetchStage_pipelines_1_first__0346_BITS_46_ETC___d22293 = fetchStage$pipelines_1_first[461:333] != - fallthrough_pc__h970681 ; + fallthrough_pc__h970676 ; assign NOT_fetchStage_pipelines_1_first__0346_BIT_69__ETC___d22231 = !fetchStage$pipelines_1_first[69] && !checkForException___d21674[13] && @@ -28548,7 +28548,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q312, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7207, - x__h513050 } ; + x__h513047 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24324 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q315, @@ -28571,8 +28571,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q307 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12885 = - { {4{f1_exp19757_MINUS_127__q147[7]}}, - f1_exp19757_MINUS_127__q147 } ; + { {4{f1_exp19754_MINUS_127__q147[7]}}, + f1_exp19754_MINUS_127__q147 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12886 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12885 ^ 12'h800) <= @@ -28582,8 +28582,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13600 = - { {4{f3_exp98055_MINUS_127__q164[7]}}, - f3_exp98055_MINUS_127__q164 } ; + { {4{f3_exp98052_MINUS_127__q164[7]}}, + f3_exp98052_MINUS_127__q164 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13601 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13600 ^ 12'h800) <= @@ -28593,8 +28593,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14370 = - { {4{f2_exp58751_MINUS_127__q187[7]}}, - f2_exp58751_MINUS_127__q187 } ; + { {4{f2_exp58748_MINUS_127__q187[7]}}, + f2_exp58748_MINUS_127__q187 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14371 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14370 ^ 12'h800) <= @@ -28604,9 +28604,9 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d15315 = - b__h840751 * b__h840827 ; + b__h840748 * b__h840824 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d15328 = - b__h840751 * b__h840940 ; + b__h840748 * b__h840937 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12885 + 12'd1023 ; @@ -28626,11 +28626,11 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4883 = - { {64{x__h267596[63]}}, x__h267596 } ; + { {64{x__h267593[63]}}, x__h267593 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4891 = - { {96{x__h267751[31]}}, x__h267751 } ; + { {96{x__h267748[31]}}, x__h267748 } ; assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22824 = - x__h1005791 | in__h1005860[63:0] ; + x__h1005786 | in__h1005855[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10144 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83 } ; @@ -28684,15 +28684,15 @@ module mkCore(CLK, 8'd127 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10767 = { 3'd0, - _theResult___fst_exp__h634665 == 8'd0 && - (sfdin__h634659[56:34] == 23'd0 || guard__h626566 != 2'b0), + _theResult___fst_exp__h634662 == 8'd0 && + (sfdin__h634656[56:34] == 23'd0 || guard__h626563 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h635262 == 8'd255 && - _theResult___fst_sfd__h635263 == 23'd0, + _theResult___fst_exp__h635259 == 8'd255 && + _theResult___fst_sfd__h635260 == 23'd0, 1'd0, - _theResult___fst_exp__h634665 != 8'd255 && - guard__h626566 != 2'b0 } ; + _theResult___fst_exp__h634662 != 8'd255 && + guard__h626563 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11239 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11237 } ^ @@ -28700,15 +28700,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12164 = { 3'd0, - _theResult___fst_exp__h680412 == 8'd0 && - (sfdin__h680406[56:34] == 23'd0 || guard__h672313 != 2'b0), + _theResult___fst_exp__h680409 == 8'd0 && + (sfdin__h680403[56:34] == 23'd0 || guard__h672310 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h681009 == 8'd255 && - _theResult___fst_sfd__h681010 == 23'd0, + _theResult___fst_exp__h681006 == 8'd255 && + _theResult___fst_sfd__h681007 == 23'd0, 1'd0, - _theResult___fst_exp__h680412 != 8'd255 && - guard__h672313 != 2'b0 } ; + _theResult___fst_exp__h680409 != 8'd255 && + guard__h672310 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8445 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8443 } ^ @@ -28716,15 +28716,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9370 = { 3'd0, - _theResult___fst_exp__h588916 == 8'd0 && - (sfdin__h588910[56:34] == 23'd0 || guard__h580815 != 2'b0), + _theResult___fst_exp__h588913 == 8'd0 && + (sfdin__h588907[56:34] == 23'd0 || guard__h580812 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h589513 == 8'd255 && - _theResult___fst_sfd__h589514 == 23'd0, + _theResult___fst_exp__h589510 == 8'd255 && + _theResult___fst_sfd__h589511 == 23'd0, 1'd0, - _theResult___fst_exp__h588916 != 8'd255 && - guard__h580815 != 2'b0 } ; + _theResult___fst_exp__h588913 != 8'd255 && + guard__h580812 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9842 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9840 } ^ @@ -28747,37 +28747,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14997 = { 3'd0, - _theResult___fst_exp__h748722 == 11'd0 && - (sfdin__h748716[56:5] == 52'd0 || guard__h740496 != 2'b0), + _theResult___fst_exp__h748719 == 11'd0 && + (sfdin__h748713[56:5] == 52'd0 || guard__h740493 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h749554 == 11'd2047 && - _theResult___fst_sfd__h749555 == 52'd0, + _theResult___fst_exp__h749551 == 11'd2047 && + _theResult___fst_sfd__h749552 == 52'd0, 1'd0, - _theResult___fst_exp__h748722 != 11'd2047 && - guard__h740496 != 2'b0 } ; + _theResult___fst_exp__h748719 != 11'd2047 && + guard__h740493 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15038 = { 3'd0, - _theResult___fst_exp__h787575 == 11'd0 && - (sfdin__h787569[56:5] == 52'd0 || guard__h779349 != 2'b0), + _theResult___fst_exp__h787572 == 11'd0 && + (sfdin__h787566[56:5] == 52'd0 || guard__h779346 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h788407 == 11'd2047 && - _theResult___fst_sfd__h788408 == 52'd0, + _theResult___fst_exp__h788404 == 11'd2047 && + _theResult___fst_sfd__h788405 == 52'd0, 1'd0, - _theResult___fst_exp__h787575 != 11'd2047 && - guard__h779349 != 2'b0 } ; + _theResult___fst_exp__h787572 != 11'd2047 && + guard__h779346 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15082 = { 3'd0, - _theResult___fst_exp__h826879 == 11'd0 && - (sfdin__h826873[56:5] == 52'd0 || guard__h818653 != 2'b0), + _theResult___fst_exp__h826876 == 11'd0 && + (sfdin__h826870[56:5] == 52'd0 || guard__h818650 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h827711 == 11'd2047 && - _theResult___fst_sfd__h827712 == 52'd0, + _theResult___fst_exp__h827708 == 11'd2047 && + _theResult___fst_sfd__h827709 == 52'd0, 1'd0, - _theResult___fst_exp__h826879 != 11'd2047 && - guard__h818653 != 2'b0 } ; + _theResult___fst_exp__h826876 != 11'd2047 && + guard__h818650 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10393 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10391 } ^ @@ -28785,15 +28785,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10796 = { 3'd0, - _theResult___fst_exp__h652431 == 8'd0 && - (sfdin__h652425[56:34] == 23'd0 || guard__h644203 != 2'b0), + _theResult___fst_exp__h652428 == 8'd0 && + (sfdin__h652422[56:34] == 23'd0 || guard__h644200 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h653028 == 8'd255 && - _theResult___fst_sfd__h653029 == 23'd0, + _theResult___fst_exp__h653025 == 8'd255 && + _theResult___fst_sfd__h653026 == 23'd0, 1'd0, - _theResult___fst_exp__h652431 != 8'd255 && - guard__h644203 != 2'b0 } ; + _theResult___fst_exp__h652428 != 8'd255 && + guard__h644200 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11790 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11788 } ^ @@ -28801,15 +28801,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12193 = { 3'd0, - _theResult___fst_exp__h698178 == 8'd0 && - (sfdin__h698172[56:34] == 23'd0 || guard__h689950 != 2'b0), + _theResult___fst_exp__h698175 == 8'd0 && + (sfdin__h698169[56:34] == 23'd0 || guard__h689947 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h698775 == 8'd255 && - _theResult___fst_sfd__h698776 == 23'd0, + _theResult___fst_exp__h698772 == 8'd255 && + _theResult___fst_sfd__h698773 == 23'd0, 1'd0, - _theResult___fst_exp__h698178 != 8'd255 && - guard__h689950 != 2'b0 } ; + _theResult___fst_exp__h698175 != 8'd255 && + guard__h689947 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8996 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8994 } ^ @@ -28817,15 +28817,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9399 = { 3'd0, - _theResult___fst_exp__h606682 == 8'd0 && - (sfdin__h606676[56:34] == 23'd0 || guard__h598454 != 2'b0), + _theResult___fst_exp__h606679 == 8'd0 && + (sfdin__h606673[56:34] == 23'd0 || guard__h598451 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h607279 == 8'd255 && - _theResult___fst_sfd__h607280 == 23'd0, + _theResult___fst_exp__h607276 == 8'd255 && + _theResult___fst_sfd__h607277 == 23'd0, 1'd0, - _theResult___fst_exp__h606682 != 8'd255 && - guard__h598454 != 2'b0 } ; + _theResult___fst_exp__h606679 != 8'd255 && + guard__h598451 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12824 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12822 } ^ @@ -28861,37 +28861,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14980 = { 3'd0, - _theResult___fst_exp__h739145 == 11'd0 && - guard__h731184 != 2'b0, + _theResult___fst_exp__h739142 == 11'd0 && + guard__h731181 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h739903 == 11'd2047 && - _theResult___fst_sfd__h739904 == 52'd0, + _theResult___fst_exp__h739900 == 11'd2047 && + _theResult___fst_sfd__h739901 == 52'd0, 1'd0, - _theResult___fst_exp__h739145 != 11'd2047 && - guard__h731184 != 2'b0 } ; + _theResult___fst_exp__h739142 != 11'd2047 && + guard__h731181 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15021 = { 3'd0, - _theResult___fst_exp__h777998 == 11'd0 && - guard__h770037 != 2'b0, + _theResult___fst_exp__h777995 == 11'd0 && + guard__h770034 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h778756 == 11'd2047 && - _theResult___fst_sfd__h778757 == 52'd0, + _theResult___fst_exp__h778753 == 11'd2047 && + _theResult___fst_sfd__h778754 == 52'd0, 1'd0, - _theResult___fst_exp__h777998 != 11'd2047 && - guard__h770037 != 2'b0 } ; + _theResult___fst_exp__h777995 != 11'd2047 && + guard__h770034 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15065 = { 3'd0, - _theResult___fst_exp__h817302 == 11'd0 && - guard__h809341 != 2'b0, + _theResult___fst_exp__h817299 == 11'd0 && + guard__h809338 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h818060 == 11'd2047 && - _theResult___fst_sfd__h818061 == 52'd0, + _theResult___fst_exp__h818057 == 11'd2047 && + _theResult___fst_sfd__h818058 == 52'd0, 1'd0, - _theResult___fst_exp__h817302 != 11'd2047 && - guard__h809341 != 2'b0 } ; + _theResult___fst_exp__h817299 != 11'd2047 && + guard__h809338 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10073 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10071 } ^ @@ -28905,15 +28905,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10779 = { 3'd0, - _theResult___fst_exp__h643321 == 8'd0 && - guard__h635273 != 2'b0, + _theResult___fst_exp__h643318 == 8'd0 && + guard__h635270 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h643844 == 8'd255 && - _theResult___fst_sfd__h643845 == 23'd0, + _theResult___fst_exp__h643841 == 8'd255 && + _theResult___fst_sfd__h643842 == 23'd0, 1'd0, - _theResult___fst_exp__h643321 != 8'd255 && - guard__h635273 != 2'b0 } ; + _theResult___fst_exp__h643318 != 8'd255 && + guard__h635270 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11470 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11468 } ^ @@ -28927,15 +28927,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12176 = { 3'd0, - _theResult___fst_exp__h689068 == 8'd0 && - guard__h681020 != 2'b0, + _theResult___fst_exp__h689065 == 8'd0 && + guard__h681017 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h689591 == 8'd255 && - _theResult___fst_sfd__h689592 == 23'd0, + _theResult___fst_exp__h689588 == 8'd255 && + _theResult___fst_sfd__h689589 == 23'd0, 1'd0, - _theResult___fst_exp__h689068 != 8'd255 && - guard__h681020 != 2'b0 } ; + _theResult___fst_exp__h689065 != 8'd255 && + guard__h681017 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8676 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8674 } ^ @@ -28949,17 +28949,17 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9382 = { 3'd0, - _theResult___fst_exp__h597572 == 8'd0 && - guard__h589524 != 2'b0, + _theResult___fst_exp__h597569 == 8'd0 && + guard__h589521 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h598095 == 8'd255 && - _theResult___fst_sfd__h598096 == 23'd0, + _theResult___fst_exp__h598092 == 8'd255 && + _theResult___fst_sfd__h598093 == 23'd0, 1'd0, - _theResult___fst_exp__h597572 != 8'd255 && - guard__h589524 != 2'b0 } ; + _theResult___fst_exp__h597569 != 8'd255 && + guard__h589521 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d15321 = - b__h840928 * b__h840940 ; + b__h840925 * b__h840937 ; assign _0_CONCAT_IF_coreFix_memExe_dTlb_procResp__258__ETC___d4669 = { 2'd0, (coreFix_memExe_dTlb$procResp[277] && @@ -28980,17 +28980,17 @@ module mkCore(CLK, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; assign _0_CONCAT_csrf_mtcc_reg_read__6810_BITS_149_TO__ETC___d22990 = - x__h1008549[13:11] < repBound__h1008513 ; + x__h1008544[13:11] < repBound__h1008508 ; assign _0_CONCAT_csrf_mtcc_reg_read__6810_BITS_149_TO__ETC___d23016 = - x__h1008853[13:11] < repBound__h1008513 ; + x__h1008848[13:11] < repBound__h1008508 ; assign _0_CONCAT_csrf_stcc_reg_read__6801_BITS_149_TO__ETC___d22915 = - x__h1007892[13:11] < repBound__h1007856 ; + x__h1007887[13:11] < repBound__h1007851 ; assign _0_CONCAT_csrf_stcc_reg_read__6801_BITS_149_TO__ETC___d22941 = - x__h1008196[13:11] < repBound__h1007856 ; + x__h1008191[13:11] < repBound__h1007851 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0337_BI_ETC___d21911 = (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k51774_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 ; + CASE_k51769_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0346_BI_ETC___d21809 = (fetchStage$pipelines_1_first[267:265] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -29004,37 +29004,37 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__0335_AND_N_ETC__q269 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12892 = - sfd__h720119 >> + sfd__h720116 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12888 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13607 = - sfd__h798417 >> + sfd__h798414 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13603 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14377 = - sfd__h759113 >> + sfd__h759110 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14373 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10151 = - sfd__h618954 >> + sfd__h618951 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10147[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10147) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11548 = - sfd__h664701 >> + sfd__h664698 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11544[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11544) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8754 = - sfd__h573200 >> + sfd__h573197 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8750[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8750) ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__6254_6255_ETC___d22789 = - medeleg_csr__read__h856403[i__h1003540] ; + medeleg_csr__read__h856400[i__h1003535] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6262_6263_ETC___d22791 = - mideleg_csr__read__h856501[i__h1003714] ; + mideleg_csr__read__h856498[i__h1003709] ; assign _18446744073709551615_SL_csrf_mtcc_reg_read__68_ETC___d22978 = - mask__h1008361 ^ y__h1008478 ; + mask__h1008356 ^ y__h1008473 ; assign _18446744073709551615_SL_csrf_stcc_reg_read__68_ETC___d22903 = - mask__h1007704 ^ y__h1007821 ; + mask__h1007699 ^ y__h1007816 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10782 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9605 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9606 ? @@ -29440,51 +29440,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12748 = 12'd3970 - { 7'd0, - f1_sfd__h719758[22] ? + f1_sfd__h719755[22] ? 5'd0 : - (f1_sfd__h719758[21] ? + (f1_sfd__h719755[21] ? 5'd1 : - (f1_sfd__h719758[20] ? + (f1_sfd__h719755[20] ? 5'd2 : - (f1_sfd__h719758[19] ? + (f1_sfd__h719755[19] ? 5'd3 : - (f1_sfd__h719758[18] ? + (f1_sfd__h719755[18] ? 5'd4 : - (f1_sfd__h719758[17] ? + (f1_sfd__h719755[17] ? 5'd5 : - (f1_sfd__h719758[16] ? + (f1_sfd__h719755[16] ? 5'd6 : - (f1_sfd__h719758[15] ? + (f1_sfd__h719755[15] ? 5'd7 : - (f1_sfd__h719758[14] ? + (f1_sfd__h719755[14] ? 5'd8 : - (f1_sfd__h719758[13] ? + (f1_sfd__h719755[13] ? 5'd9 : - (f1_sfd__h719758[12] ? + (f1_sfd__h719755[12] ? 5'd10 : - (f1_sfd__h719758[11] ? + (f1_sfd__h719755[11] ? 5'd11 : - (f1_sfd__h719758[10] ? + (f1_sfd__h719755[10] ? 5'd12 : - (f1_sfd__h719758[9] ? + (f1_sfd__h719755[9] ? 5'd13 : - (f1_sfd__h719758[8] ? + (f1_sfd__h719755[8] ? 5'd14 : - (f1_sfd__h719758[7] ? + (f1_sfd__h719755[7] ? 5'd15 : - (f1_sfd__h719758[6] ? + (f1_sfd__h719755[6] ? 5'd16 : - (f1_sfd__h719758[5] ? + (f1_sfd__h719755[5] ? 5'd17 : - (f1_sfd__h719758[4] ? + (f1_sfd__h719755[4] ? 5'd18 : - (f1_sfd__h719758[3] ? + (f1_sfd__h719755[3] ? 5'd19 : - (f1_sfd__h719758[2] ? + (f1_sfd__h719755[2] ? 5'd20 : - (f1_sfd__h719758[1] ? + (f1_sfd__h719755[1] ? 5'd21 : - (f1_sfd__h719758[0] ? + (f1_sfd__h719755[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 = @@ -29498,51 +29498,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13478 = 12'd3970 - { 7'd0, - f3_sfd__h798056[22] ? + f3_sfd__h798053[22] ? 5'd0 : - (f3_sfd__h798056[21] ? + (f3_sfd__h798053[21] ? 5'd1 : - (f3_sfd__h798056[20] ? + (f3_sfd__h798053[20] ? 5'd2 : - (f3_sfd__h798056[19] ? + (f3_sfd__h798053[19] ? 5'd3 : - (f3_sfd__h798056[18] ? + (f3_sfd__h798053[18] ? 5'd4 : - (f3_sfd__h798056[17] ? + (f3_sfd__h798053[17] ? 5'd5 : - (f3_sfd__h798056[16] ? + (f3_sfd__h798053[16] ? 5'd6 : - (f3_sfd__h798056[15] ? + (f3_sfd__h798053[15] ? 5'd7 : - (f3_sfd__h798056[14] ? + (f3_sfd__h798053[14] ? 5'd8 : - (f3_sfd__h798056[13] ? + (f3_sfd__h798053[13] ? 5'd9 : - (f3_sfd__h798056[12] ? + (f3_sfd__h798053[12] ? 5'd10 : - (f3_sfd__h798056[11] ? + (f3_sfd__h798053[11] ? 5'd11 : - (f3_sfd__h798056[10] ? + (f3_sfd__h798053[10] ? 5'd12 : - (f3_sfd__h798056[9] ? + (f3_sfd__h798053[9] ? 5'd13 : - (f3_sfd__h798056[8] ? + (f3_sfd__h798053[8] ? 5'd14 : - (f3_sfd__h798056[7] ? + (f3_sfd__h798053[7] ? 5'd15 : - (f3_sfd__h798056[6] ? + (f3_sfd__h798053[6] ? 5'd16 : - (f3_sfd__h798056[5] ? + (f3_sfd__h798053[5] ? 5'd17 : - (f3_sfd__h798056[4] ? + (f3_sfd__h798053[4] ? 5'd18 : - (f3_sfd__h798056[3] ? + (f3_sfd__h798053[3] ? 5'd19 : - (f3_sfd__h798056[2] ? + (f3_sfd__h798053[2] ? 5'd20 : - (f3_sfd__h798056[1] ? + (f3_sfd__h798053[1] ? 5'd21 : - (f3_sfd__h798056[0] ? + (f3_sfd__h798053[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 = @@ -29556,51 +29556,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14248 = 12'd3970 - { 7'd0, - f2_sfd__h758752[22] ? + f2_sfd__h758749[22] ? 5'd0 : - (f2_sfd__h758752[21] ? + (f2_sfd__h758749[21] ? 5'd1 : - (f2_sfd__h758752[20] ? + (f2_sfd__h758749[20] ? 5'd2 : - (f2_sfd__h758752[19] ? + (f2_sfd__h758749[19] ? 5'd3 : - (f2_sfd__h758752[18] ? + (f2_sfd__h758749[18] ? 5'd4 : - (f2_sfd__h758752[17] ? + (f2_sfd__h758749[17] ? 5'd5 : - (f2_sfd__h758752[16] ? + (f2_sfd__h758749[16] ? 5'd6 : - (f2_sfd__h758752[15] ? + (f2_sfd__h758749[15] ? 5'd7 : - (f2_sfd__h758752[14] ? + (f2_sfd__h758749[14] ? 5'd8 : - (f2_sfd__h758752[13] ? + (f2_sfd__h758749[13] ? 5'd9 : - (f2_sfd__h758752[12] ? + (f2_sfd__h758749[12] ? 5'd10 : - (f2_sfd__h758752[11] ? + (f2_sfd__h758749[11] ? 5'd11 : - (f2_sfd__h758752[10] ? + (f2_sfd__h758749[10] ? 5'd12 : - (f2_sfd__h758752[9] ? + (f2_sfd__h758749[9] ? 5'd13 : - (f2_sfd__h758752[8] ? + (f2_sfd__h758749[8] ? 5'd14 : - (f2_sfd__h758752[7] ? + (f2_sfd__h758749[7] ? 5'd15 : - (f2_sfd__h758752[6] ? + (f2_sfd__h758749[6] ? 5'd16 : - (f2_sfd__h758752[5] ? + (f2_sfd__h758749[5] ? 5'd17 : - (f2_sfd__h758752[4] ? + (f2_sfd__h758749[4] ? 5'd18 : - (f2_sfd__h758752[3] ? + (f2_sfd__h758749[3] ? 5'd19 : - (f2_sfd__h758752[2] ? + (f2_sfd__h758749[2] ? 5'd20 : - (f2_sfd__h758752[1] ? + (f2_sfd__h758749[1] ? 5'd21 : - (f2_sfd__h758752[0] ? + (f2_sfd__h758749[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 = @@ -29631,7 +29631,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0335_0336_O_ETC___d22306 && fetchStage$pipelines_1_first[272:268] != 5'd19 ; assign _dfoo16 = - k__h951774 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h951769 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0337_BITS_26_ETC___d22085 || (fetchStage_pipelines_0_canDeq__0335_AND_NOT_fe_ETC___d22206 || NOT_fetchStage_pipelines_0_canDeq__0335_0336_O_ETC___d22219) == @@ -29639,7 +29639,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0335_0336_O_ETC___d22224 && NOT_fetchStage_pipelines_1_first__0346_BITS_26_ETC___d22236 ; assign _dfoo18 = - k__h951774 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h951769 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0337_BITS_26_ETC___d22085 || (fetchStage_pipelines_0_canDeq__0335_AND_NOT_fe_ETC___d22206 || NOT_fetchStage_pipelines_0_canDeq__0335_0336_O_ETC___d22219) == @@ -29746,1415 +29746,1415 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h519720 = + assign _theResult_____2__h519716 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7313 ? - next_deqP___1__h519965 : + next_deqP___1__h519961 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h530497 = + assign _theResult_____2__h530493 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7407 ? - next_deqP___1__h530742 : + next_deqP___1__h530738 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h537590 = + assign _theResult_____2__h537586 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7566 ? - next_deqP___1__h538020 : + next_deqP___1__h538016 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h548225 = + assign _theResult_____2__h548221 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7650 ? - next_deqP___1__h548655 : + next_deqP___1__h548651 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h562058 = + assign _theResult_____2__h562054 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7855 ? - next_deqP___1__h562303 : + next_deqP___1__h562299 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h565837 = + assign _theResult_____2__h565833 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7937 ? - next_deqP___1__h566082 : + next_deqP___1__h566078 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h580805 = - (value__h581427 == 54'd0) ? sfd__h573200 : 57'd1 ; - assign _theResult____h598444 = + assign _theResult____h580802 = + (value__h581424 == 54'd0) ? sfd__h573197 : 57'd1 ; + assign _theResult____h598441 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8750 ^ 12'h800) < 12'd2105) ? - result__h599057 : - _theResult____h580805 ; - assign _theResult____h626556 = - (value__h627176 == 54'd0) ? sfd__h618954 : 57'd1 ; - assign _theResult____h644193 = + result__h599054 : + _theResult____h580802 ; + assign _theResult____h626553 = + (value__h627173 == 54'd0) ? sfd__h618951 : 57'd1 ; + assign _theResult____h644190 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10147 ^ 12'h800) < 12'd2105) ? - result__h644806 : - _theResult____h626556 ; - assign _theResult____h672303 = - (value__h672923 == 54'd0) ? sfd__h664701 : 57'd1 ; - assign _theResult____h689940 = + result__h644803 : + _theResult____h626553 ; + assign _theResult____h672300 = + (value__h672920 == 54'd0) ? sfd__h664698 : 57'd1 ; + assign _theResult____h689937 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11544 ^ 12'h800) < 12'd2105) ? - result__h690553 : - _theResult____h672303 ; - assign _theResult____h740486 = + result__h690550 : + _theResult____h672300 ; + assign _theResult____h740483 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12888 ^ 12'h800) < 12'd2105) ? - result__h741099 : - ((value__h724702 == 25'd0) ? sfd__h720119 : 57'd1) ; - assign _theResult____h779339 = + result__h741096 : + ((value__h724699 == 25'd0) ? sfd__h720116 : 57'd1) ; + assign _theResult____h779336 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14373 ^ 12'h800) < 12'd2105) ? - result__h779952 : - ((value__h763555 == 25'd0) ? sfd__h759113 : 57'd1) ; - assign _theResult____h818643 = + result__h779949 : + ((value__h763552 == 25'd0) ? sfd__h759110 : 57'd1) ; + assign _theResult____h818640 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13603 ^ 12'h800) < 12'd2105) ? - result__h819256 : - ((value__h802859 == 25'd0) ? sfd__h798417 : 57'd1) ; - assign _theResult____h926748 = + result__h819253 : + ((value__h802856 == 25'd0) ? sfd__h798414 : 57'd1) ; + assign _theResult____h926743 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h927273 : + enabled_ints___1__h927268 : 16'd0 ; - assign _theResult___exp__h589432 = - sfd__h589008[24] ? - ((_theResult___fst_exp__h588916 == 8'd254) ? + assign _theResult___exp__h589429 = + sfd__h589005[24] ? + ((_theResult___fst_exp__h588913 == 8'd254) ? 8'd255 : - din_inc___2_exp__h615949) : - ((_theResult___fst_exp__h588916 == 8'd0 && - sfd__h589008[24:23] == 2'b01) ? + din_inc___2_exp__h615946) : + ((_theResult___fst_exp__h588913 == 8'd0 && + sfd__h589005[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h588916) ; - assign _theResult___exp__h598014 = - sfd__h597590[24] ? - ((_theResult___fst_exp__h597572 == 8'd254) ? + _theResult___fst_exp__h588913) ; + assign _theResult___exp__h598011 = + sfd__h597587[24] ? + ((_theResult___fst_exp__h597569 == 8'd254) ? 8'd255 : - din_inc___2_exp__h615973) : - ((_theResult___fst_exp__h597572 == 8'd0 && - sfd__h597590[24:23] == 2'b01) ? + din_inc___2_exp__h615970) : + ((_theResult___fst_exp__h597569 == 8'd0 && + sfd__h597587[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h597572) ; - assign _theResult___exp__h607198 = - sfd__h606774[24] ? - ((_theResult___fst_exp__h606682 == 8'd254) ? + _theResult___fst_exp__h597569) ; + assign _theResult___exp__h607195 = + sfd__h606771[24] ? + ((_theResult___fst_exp__h606679 == 8'd254) ? 8'd255 : - din_inc___2_exp__h616003) : - ((_theResult___fst_exp__h606682 == 8'd0 && - sfd__h606774[24:23] == 2'b01) ? + din_inc___2_exp__h616000) : + ((_theResult___fst_exp__h606679 == 8'd0 && + sfd__h606771[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h606682) ; - assign _theResult___exp__h615834 = - sfd__h615386[24] ? - ((_theResult___fst_exp__h615367 == 8'd254) ? + _theResult___fst_exp__h606679) ; + assign _theResult___exp__h615831 = + sfd__h615383[24] ? + ((_theResult___fst_exp__h615364 == 8'd254) ? 8'd255 : - din_inc___2_exp__h616027) : - ((_theResult___fst_exp__h615367 == 8'd0 && - sfd__h615386[24:23] == 2'b01) ? + din_inc___2_exp__h616024) : + ((_theResult___fst_exp__h615364 == 8'd0 && + sfd__h615383[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h615367) ; - assign _theResult___exp__h615936 = + _theResult___fst_exp__h615364) ; + assign _theResult___exp__h615933 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h615927 ; - assign _theResult___exp__h635181 = - sfd__h634757[24] ? - ((_theResult___fst_exp__h634665 == 8'd254) ? + _theResult___fst_exp__h615924 ; + assign _theResult___exp__h635178 = + sfd__h634754[24] ? + ((_theResult___fst_exp__h634662 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661698) : - ((_theResult___fst_exp__h634665 == 8'd0 && - sfd__h634757[24:23] == 2'b01) ? + din_inc___2_exp__h661695) : + ((_theResult___fst_exp__h634662 == 8'd0 && + sfd__h634754[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h634665) ; - assign _theResult___exp__h643763 = - sfd__h643339[24] ? - ((_theResult___fst_exp__h643321 == 8'd254) ? + _theResult___fst_exp__h634662) ; + assign _theResult___exp__h643760 = + sfd__h643336[24] ? + ((_theResult___fst_exp__h643318 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661722) : - ((_theResult___fst_exp__h643321 == 8'd0 && - sfd__h643339[24:23] == 2'b01) ? + din_inc___2_exp__h661719) : + ((_theResult___fst_exp__h643318 == 8'd0 && + sfd__h643336[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h643321) ; - assign _theResult___exp__h652947 = - sfd__h652523[24] ? - ((_theResult___fst_exp__h652431 == 8'd254) ? + _theResult___fst_exp__h643318) ; + assign _theResult___exp__h652944 = + sfd__h652520[24] ? + ((_theResult___fst_exp__h652428 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661752) : - ((_theResult___fst_exp__h652431 == 8'd0 && - sfd__h652523[24:23] == 2'b01) ? + din_inc___2_exp__h661749) : + ((_theResult___fst_exp__h652428 == 8'd0 && + sfd__h652520[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h652431) ; - assign _theResult___exp__h661583 = - sfd__h661135[24] ? - ((_theResult___fst_exp__h661116 == 8'd254) ? + _theResult___fst_exp__h652428) ; + assign _theResult___exp__h661580 = + sfd__h661132[24] ? + ((_theResult___fst_exp__h661113 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661776) : - ((_theResult___fst_exp__h661116 == 8'd0 && - sfd__h661135[24:23] == 2'b01) ? + din_inc___2_exp__h661773) : + ((_theResult___fst_exp__h661113 == 8'd0 && + sfd__h661132[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h661116) ; - assign _theResult___exp__h661685 = + _theResult___fst_exp__h661113) ; + assign _theResult___exp__h661682 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h661676 ; - assign _theResult___exp__h680928 = - sfd__h680504[24] ? - ((_theResult___fst_exp__h680412 == 8'd254) ? + _theResult___fst_exp__h661673 ; + assign _theResult___exp__h680925 = + sfd__h680501[24] ? + ((_theResult___fst_exp__h680409 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707445) : - ((_theResult___fst_exp__h680412 == 8'd0 && - sfd__h680504[24:23] == 2'b01) ? + din_inc___2_exp__h707442) : + ((_theResult___fst_exp__h680409 == 8'd0 && + sfd__h680501[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h680412) ; - assign _theResult___exp__h689510 = - sfd__h689086[24] ? - ((_theResult___fst_exp__h689068 == 8'd254) ? + _theResult___fst_exp__h680409) ; + assign _theResult___exp__h689507 = + sfd__h689083[24] ? + ((_theResult___fst_exp__h689065 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707469) : - ((_theResult___fst_exp__h689068 == 8'd0 && - sfd__h689086[24:23] == 2'b01) ? + din_inc___2_exp__h707466) : + ((_theResult___fst_exp__h689065 == 8'd0 && + sfd__h689083[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h689068) ; - assign _theResult___exp__h698694 = - sfd__h698270[24] ? - ((_theResult___fst_exp__h698178 == 8'd254) ? + _theResult___fst_exp__h689065) ; + assign _theResult___exp__h698691 = + sfd__h698267[24] ? + ((_theResult___fst_exp__h698175 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707499) : - ((_theResult___fst_exp__h698178 == 8'd0 && - sfd__h698270[24:23] == 2'b01) ? + din_inc___2_exp__h707496) : + ((_theResult___fst_exp__h698175 == 8'd0 && + sfd__h698267[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h698178) ; - assign _theResult___exp__h707330 = - sfd__h706882[24] ? - ((_theResult___fst_exp__h706863 == 8'd254) ? + _theResult___fst_exp__h698175) ; + assign _theResult___exp__h707327 = + sfd__h706879[24] ? + ((_theResult___fst_exp__h706860 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707523) : - ((_theResult___fst_exp__h706863 == 8'd0 && - sfd__h706882[24:23] == 2'b01) ? + din_inc___2_exp__h707520) : + ((_theResult___fst_exp__h706860 == 8'd0 && + sfd__h706879[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h706863) ; - assign _theResult___exp__h707432 = + _theResult___fst_exp__h706860) ; + assign _theResult___exp__h707429 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h707423 ; - assign _theResult___exp__h739800 = - sfd__h739163[53] ? - ((_theResult___fst_exp__h739145 == 11'd2046) ? + _theResult___fst_exp__h707420 ; + assign _theResult___exp__h739797 = + sfd__h739160[53] ? + ((_theResult___fst_exp__h739142 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h758395) : - ((_theResult___fst_exp__h739145 == 11'd0 && - sfd__h739163[53:52] == 2'b01) ? + din_inc___2_exp__h758392) : + ((_theResult___fst_exp__h739142 == 11'd0 && + sfd__h739160[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h739145) ; - assign _theResult___exp__h749451 = - sfd__h748814[53] ? - ((_theResult___fst_exp__h748722 == 11'd2046) ? + _theResult___fst_exp__h739142) ; + assign _theResult___exp__h749448 = + sfd__h748811[53] ? + ((_theResult___fst_exp__h748719 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h758430) : - ((_theResult___fst_exp__h748722 == 11'd0 && - sfd__h748814[53:52] == 2'b01) ? + din_inc___2_exp__h758427) : + ((_theResult___fst_exp__h748719 == 11'd0 && + sfd__h748811[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h748722) ; - assign _theResult___exp__h758235 = - sfd__h757574[53] ? - ((_theResult___fst_exp__h757555 == 11'd2046) ? + _theResult___fst_exp__h748719) ; + assign _theResult___exp__h758232 = + sfd__h757571[53] ? + ((_theResult___fst_exp__h757552 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h758456) : - ((_theResult___fst_exp__h757555 == 11'd0 && - sfd__h757574[53:52] == 2'b01) ? + din_inc___2_exp__h758453) : + ((_theResult___fst_exp__h757552 == 11'd0 && + sfd__h757571[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h757555) ; - assign _theResult___exp__h778653 = - sfd__h778016[53] ? - ((_theResult___fst_exp__h777998 == 11'd2046) ? + _theResult___fst_exp__h757552) ; + assign _theResult___exp__h778650 = + sfd__h778013[53] ? + ((_theResult___fst_exp__h777995 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h797248) : - ((_theResult___fst_exp__h777998 == 11'd0 && - sfd__h778016[53:52] == 2'b01) ? + din_inc___2_exp__h797245) : + ((_theResult___fst_exp__h777995 == 11'd0 && + sfd__h778013[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h777998) ; - assign _theResult___exp__h788304 = - sfd__h787667[53] ? - ((_theResult___fst_exp__h787575 == 11'd2046) ? + _theResult___fst_exp__h777995) ; + assign _theResult___exp__h788301 = + sfd__h787664[53] ? + ((_theResult___fst_exp__h787572 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h797283) : - ((_theResult___fst_exp__h787575 == 11'd0 && - sfd__h787667[53:52] == 2'b01) ? + din_inc___2_exp__h797280) : + ((_theResult___fst_exp__h787572 == 11'd0 && + sfd__h787664[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h787575) ; - assign _theResult___exp__h797088 = - sfd__h796427[53] ? - ((_theResult___fst_exp__h796408 == 11'd2046) ? + _theResult___fst_exp__h787572) ; + assign _theResult___exp__h797085 = + sfd__h796424[53] ? + ((_theResult___fst_exp__h796405 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h797309) : - ((_theResult___fst_exp__h796408 == 11'd0 && - sfd__h796427[53:52] == 2'b01) ? + din_inc___2_exp__h797306) : + ((_theResult___fst_exp__h796405 == 11'd0 && + sfd__h796424[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h796408) ; - assign _theResult___exp__h817957 = - sfd__h817320[53] ? - ((_theResult___fst_exp__h817302 == 11'd2046) ? + _theResult___fst_exp__h796405) ; + assign _theResult___exp__h817954 = + sfd__h817317[53] ? + ((_theResult___fst_exp__h817299 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h836552) : - ((_theResult___fst_exp__h817302 == 11'd0 && - sfd__h817320[53:52] == 2'b01) ? + din_inc___2_exp__h836549) : + ((_theResult___fst_exp__h817299 == 11'd0 && + sfd__h817317[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h817302) ; - assign _theResult___exp__h827608 = - sfd__h826971[53] ? - ((_theResult___fst_exp__h826879 == 11'd2046) ? + _theResult___fst_exp__h817299) ; + assign _theResult___exp__h827605 = + sfd__h826968[53] ? + ((_theResult___fst_exp__h826876 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h836587) : - ((_theResult___fst_exp__h826879 == 11'd0 && - sfd__h826971[53:52] == 2'b01) ? + din_inc___2_exp__h836584) : + ((_theResult___fst_exp__h826876 == 11'd0 && + sfd__h826968[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h826879) ; - assign _theResult___exp__h836392 = - sfd__h835731[53] ? - ((_theResult___fst_exp__h835712 == 11'd2046) ? + _theResult___fst_exp__h826876) ; + assign _theResult___exp__h836389 = + sfd__h835728[53] ? + ((_theResult___fst_exp__h835709 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h836613) : - ((_theResult___fst_exp__h835712 == 11'd0 && - sfd__h835731[53:52] == 2'b01) ? + din_inc___2_exp__h836610) : + ((_theResult___fst_exp__h835709 == 11'd0 && + sfd__h835728[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h835712) ; - assign _theResult___fst__h841151 = - a__h840603[63] ? a___1__h841156 : a__h840603 ; - assign _theResult___fst_exp__h588916 = - _theResult____h580805[56] ? + _theResult___fst_exp__h835709) ; + assign _theResult___fst__h841148 = + a__h840600[63] ? a___1__h841153 : a__h840600 ; + assign _theResult___fst_exp__h588913 = + _theResult____h580802[56] ? 8'd2 : - _theResult___fst_exp__h588990 ; - assign _theResult___fst_exp__h588981 = + _theResult___fst_exp__h588987 ; + assign _theResult___fst_exp__h588978 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8443 } ; - assign _theResult___fst_exp__h588987 = - (!_theResult____h580805[56] && !_theResult____h580805[55] && - !_theResult____h580805[54] && - !_theResult____h580805[53] && - !_theResult____h580805[52] && - !_theResult____h580805[51] && - !_theResult____h580805[50] && - !_theResult____h580805[49] && - !_theResult____h580805[48] && - !_theResult____h580805[47] && - !_theResult____h580805[46] && - !_theResult____h580805[45] && - !_theResult____h580805[44] && - !_theResult____h580805[43] && - !_theResult____h580805[42] && - !_theResult____h580805[41] && - !_theResult____h580805[40] && - !_theResult____h580805[39] && - !_theResult____h580805[38] && - !_theResult____h580805[37] && - !_theResult____h580805[36] && - !_theResult____h580805[35] && - !_theResult____h580805[34] && - !_theResult____h580805[33] && - !_theResult____h580805[32] && - !_theResult____h580805[31] && - !_theResult____h580805[30] && - !_theResult____h580805[29] && - !_theResult____h580805[28] && - !_theResult____h580805[27] && - !_theResult____h580805[26] && - !_theResult____h580805[25] && - !_theResult____h580805[24] && - !_theResult____h580805[23] && - !_theResult____h580805[22] && - !_theResult____h580805[21] && - !_theResult____h580805[20] && - !_theResult____h580805[19] && - !_theResult____h580805[18] && - !_theResult____h580805[17] && - !_theResult____h580805[16] && - !_theResult____h580805[15] && - !_theResult____h580805[14] && - !_theResult____h580805[13] && - !_theResult____h580805[12] && - !_theResult____h580805[11] && - !_theResult____h580805[10] && - !_theResult____h580805[9] && - !_theResult____h580805[8] && - !_theResult____h580805[7] && - !_theResult____h580805[6] && - !_theResult____h580805[5] && - !_theResult____h580805[4] && - !_theResult____h580805[3] && - !_theResult____h580805[2] && - !_theResult____h580805[1] && - !_theResult____h580805[0] || + assign _theResult___fst_exp__h588984 = + (!_theResult____h580802[56] && !_theResult____h580802[55] && + !_theResult____h580802[54] && + !_theResult____h580802[53] && + !_theResult____h580802[52] && + !_theResult____h580802[51] && + !_theResult____h580802[50] && + !_theResult____h580802[49] && + !_theResult____h580802[48] && + !_theResult____h580802[47] && + !_theResult____h580802[46] && + !_theResult____h580802[45] && + !_theResult____h580802[44] && + !_theResult____h580802[43] && + !_theResult____h580802[42] && + !_theResult____h580802[41] && + !_theResult____h580802[40] && + !_theResult____h580802[39] && + !_theResult____h580802[38] && + !_theResult____h580802[37] && + !_theResult____h580802[36] && + !_theResult____h580802[35] && + !_theResult____h580802[34] && + !_theResult____h580802[33] && + !_theResult____h580802[32] && + !_theResult____h580802[31] && + !_theResult____h580802[30] && + !_theResult____h580802[29] && + !_theResult____h580802[28] && + !_theResult____h580802[27] && + !_theResult____h580802[26] && + !_theResult____h580802[25] && + !_theResult____h580802[24] && + !_theResult____h580802[23] && + !_theResult____h580802[22] && + !_theResult____h580802[21] && + !_theResult____h580802[20] && + !_theResult____h580802[19] && + !_theResult____h580802[18] && + !_theResult____h580802[17] && + !_theResult____h580802[16] && + !_theResult____h580802[15] && + !_theResult____h580802[14] && + !_theResult____h580802[13] && + !_theResult____h580802[12] && + !_theResult____h580802[11] && + !_theResult____h580802[10] && + !_theResult____h580802[9] && + !_theResult____h580802[8] && + !_theResult____h580802[7] && + !_theResult____h580802[6] && + !_theResult____h580802[5] && + !_theResult____h580802[4] && + !_theResult____h580802[3] && + !_theResult____h580802[2] && + !_theResult____h580802[1] && + !_theResult____h580802[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8445) ? 8'd0 : - _theResult___fst_exp__h588981 ; - assign _theResult___fst_exp__h588990 = - (!_theResult____h580805[56] && _theResult____h580805[55]) ? + _theResult___fst_exp__h588978 ; + assign _theResult___fst_exp__h588987 = + (!_theResult____h580802[56] && _theResult____h580802[55]) ? 8'd1 : - _theResult___fst_exp__h588987 ; - assign _theResult___fst_exp__h589513 = - (_theResult___fst_exp__h588916 == 8'd255) ? - _theResult___fst_exp__h588916 : - _theResult___fst_exp__h589510 ; - assign _theResult___fst_exp__h597563 = + _theResult___fst_exp__h588984 ; + assign _theResult___fst_exp__h589510 = + (_theResult___fst_exp__h588913 == 8'd255) ? + _theResult___fst_exp__h588913 : + _theResult___fst_exp__h589507 ; + assign _theResult___fst_exp__h597560 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8674 } ; - assign _theResult___fst_exp__h597569 = + assign _theResult___fst_exp__h597566 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8619 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8676) ? 8'd0 : - _theResult___fst_exp__h597563 ; - assign _theResult___fst_exp__h597572 = + _theResult___fst_exp__h597560 ; + assign _theResult___fst_exp__h597569 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h597569 : + _theResult___fst_exp__h597566 : 8'd129 ; - assign _theResult___fst_exp__h598095 = - (_theResult___fst_exp__h597572 == 8'd255) ? - _theResult___fst_exp__h597572 : - _theResult___fst_exp__h598092 ; - assign _theResult___fst_exp__h606682 = - _theResult____h598444[56] ? + assign _theResult___fst_exp__h598092 = + (_theResult___fst_exp__h597569 == 8'd255) ? + _theResult___fst_exp__h597569 : + _theResult___fst_exp__h598089 ; + assign _theResult___fst_exp__h606679 = + _theResult____h598441[56] ? 8'd2 : - _theResult___fst_exp__h606756 ; - assign _theResult___fst_exp__h606747 = + _theResult___fst_exp__h606753 ; + assign _theResult___fst_exp__h606744 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8994 } ; - assign _theResult___fst_exp__h606753 = - (!_theResult____h598444[56] && !_theResult____h598444[55] && - !_theResult____h598444[54] && - !_theResult____h598444[53] && - !_theResult____h598444[52] && - !_theResult____h598444[51] && - !_theResult____h598444[50] && - !_theResult____h598444[49] && - !_theResult____h598444[48] && - !_theResult____h598444[47] && - !_theResult____h598444[46] && - !_theResult____h598444[45] && - !_theResult____h598444[44] && - !_theResult____h598444[43] && - !_theResult____h598444[42] && - !_theResult____h598444[41] && - !_theResult____h598444[40] && - !_theResult____h598444[39] && - !_theResult____h598444[38] && - !_theResult____h598444[37] && - !_theResult____h598444[36] && - !_theResult____h598444[35] && - !_theResult____h598444[34] && - !_theResult____h598444[33] && - !_theResult____h598444[32] && - !_theResult____h598444[31] && - !_theResult____h598444[30] && - !_theResult____h598444[29] && - !_theResult____h598444[28] && - !_theResult____h598444[27] && - !_theResult____h598444[26] && - !_theResult____h598444[25] && - !_theResult____h598444[24] && - !_theResult____h598444[23] && - !_theResult____h598444[22] && - !_theResult____h598444[21] && - !_theResult____h598444[20] && - !_theResult____h598444[19] && - !_theResult____h598444[18] && - !_theResult____h598444[17] && - !_theResult____h598444[16] && - !_theResult____h598444[15] && - !_theResult____h598444[14] && - !_theResult____h598444[13] && - !_theResult____h598444[12] && - !_theResult____h598444[11] && - !_theResult____h598444[10] && - !_theResult____h598444[9] && - !_theResult____h598444[8] && - !_theResult____h598444[7] && - !_theResult____h598444[6] && - !_theResult____h598444[5] && - !_theResult____h598444[4] && - !_theResult____h598444[3] && - !_theResult____h598444[2] && - !_theResult____h598444[1] && - !_theResult____h598444[0] || + assign _theResult___fst_exp__h606750 = + (!_theResult____h598441[56] && !_theResult____h598441[55] && + !_theResult____h598441[54] && + !_theResult____h598441[53] && + !_theResult____h598441[52] && + !_theResult____h598441[51] && + !_theResult____h598441[50] && + !_theResult____h598441[49] && + !_theResult____h598441[48] && + !_theResult____h598441[47] && + !_theResult____h598441[46] && + !_theResult____h598441[45] && + !_theResult____h598441[44] && + !_theResult____h598441[43] && + !_theResult____h598441[42] && + !_theResult____h598441[41] && + !_theResult____h598441[40] && + !_theResult____h598441[39] && + !_theResult____h598441[38] && + !_theResult____h598441[37] && + !_theResult____h598441[36] && + !_theResult____h598441[35] && + !_theResult____h598441[34] && + !_theResult____h598441[33] && + !_theResult____h598441[32] && + !_theResult____h598441[31] && + !_theResult____h598441[30] && + !_theResult____h598441[29] && + !_theResult____h598441[28] && + !_theResult____h598441[27] && + !_theResult____h598441[26] && + !_theResult____h598441[25] && + !_theResult____h598441[24] && + !_theResult____h598441[23] && + !_theResult____h598441[22] && + !_theResult____h598441[21] && + !_theResult____h598441[20] && + !_theResult____h598441[19] && + !_theResult____h598441[18] && + !_theResult____h598441[17] && + !_theResult____h598441[16] && + !_theResult____h598441[15] && + !_theResult____h598441[14] && + !_theResult____h598441[13] && + !_theResult____h598441[12] && + !_theResult____h598441[11] && + !_theResult____h598441[10] && + !_theResult____h598441[9] && + !_theResult____h598441[8] && + !_theResult____h598441[7] && + !_theResult____h598441[6] && + !_theResult____h598441[5] && + !_theResult____h598441[4] && + !_theResult____h598441[3] && + !_theResult____h598441[2] && + !_theResult____h598441[1] && + !_theResult____h598441[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8996) ? 8'd0 : - _theResult___fst_exp__h606747 ; - assign _theResult___fst_exp__h606756 = - (!_theResult____h598444[56] && _theResult____h598444[55]) ? + _theResult___fst_exp__h606744 ; + assign _theResult___fst_exp__h606753 = + (!_theResult____h598441[56] && _theResult____h598441[55]) ? 8'd1 : - _theResult___fst_exp__h606753 ; - assign _theResult___fst_exp__h607279 = - (_theResult___fst_exp__h606682 == 8'd255) ? - _theResult___fst_exp__h606682 : - _theResult___fst_exp__h607276 ; - assign _theResult___fst_exp__h615319 = + _theResult___fst_exp__h606750 ; + assign _theResult___fst_exp__h607276 = + (_theResult___fst_exp__h606679 == 8'd255) ? + _theResult___fst_exp__h606679 : + _theResult___fst_exp__h607273 ; + assign _theResult___fst_exp__h615316 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] ; - assign _theResult___fst_exp__h615358 = + assign _theResult___fst_exp__h615355 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8674 } ; - assign _theResult___fst_exp__h615364 = + assign _theResult___fst_exp__h615361 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8619 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9069) ? 8'd0 : - _theResult___fst_exp__h615358 ; - assign _theResult___fst_exp__h615367 = + _theResult___fst_exp__h615355 ; + assign _theResult___fst_exp__h615364 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h615361 : + _theResult___fst_exp__h615316 ; + assign _theResult___fst_exp__h615912 = + (_theResult___fst_exp__h615364 == 8'd255) ? _theResult___fst_exp__h615364 : - _theResult___fst_exp__h615319 ; - assign _theResult___fst_exp__h615915 = - (_theResult___fst_exp__h615367 == 8'd255) ? - _theResult___fst_exp__h615367 : - _theResult___fst_exp__h615912 ; - assign _theResult___fst_exp__h615924 = + _theResult___fst_exp__h615909 ; + assign _theResult___fst_exp__h615921 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8208 ? - _theResult___snd_fst_exp__h598098 : - _theResult___fst_exp__h580787) : + _theResult___snd_fst_exp__h598095 : + _theResult___fst_exp__h580784) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8748 ? - _theResult___snd_fst_exp__h615918 : - _theResult___fst_exp__h580787) ; - assign _theResult___fst_exp__h615927 = + _theResult___snd_fst_exp__h615915 : + _theResult___fst_exp__h580784) ; + assign _theResult___fst_exp__h615924 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h615924 ; - assign _theResult___fst_exp__h634665 = - _theResult____h626556[56] ? + _theResult___fst_exp__h615921 ; + assign _theResult___fst_exp__h634662 = + _theResult____h626553[56] ? 8'd2 : - _theResult___fst_exp__h634739 ; - assign _theResult___fst_exp__h634730 = + _theResult___fst_exp__h634736 ; + assign _theResult___fst_exp__h634727 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9840 } ; - assign _theResult___fst_exp__h634736 = - (!_theResult____h626556[56] && !_theResult____h626556[55] && - !_theResult____h626556[54] && - !_theResult____h626556[53] && - !_theResult____h626556[52] && - !_theResult____h626556[51] && - !_theResult____h626556[50] && - !_theResult____h626556[49] && - !_theResult____h626556[48] && - !_theResult____h626556[47] && - !_theResult____h626556[46] && - !_theResult____h626556[45] && - !_theResult____h626556[44] && - !_theResult____h626556[43] && - !_theResult____h626556[42] && - !_theResult____h626556[41] && - !_theResult____h626556[40] && - !_theResult____h626556[39] && - !_theResult____h626556[38] && - !_theResult____h626556[37] && - !_theResult____h626556[36] && - !_theResult____h626556[35] && - !_theResult____h626556[34] && - !_theResult____h626556[33] && - !_theResult____h626556[32] && - !_theResult____h626556[31] && - !_theResult____h626556[30] && - !_theResult____h626556[29] && - !_theResult____h626556[28] && - !_theResult____h626556[27] && - !_theResult____h626556[26] && - !_theResult____h626556[25] && - !_theResult____h626556[24] && - !_theResult____h626556[23] && - !_theResult____h626556[22] && - !_theResult____h626556[21] && - !_theResult____h626556[20] && - !_theResult____h626556[19] && - !_theResult____h626556[18] && - !_theResult____h626556[17] && - !_theResult____h626556[16] && - !_theResult____h626556[15] && - !_theResult____h626556[14] && - !_theResult____h626556[13] && - !_theResult____h626556[12] && - !_theResult____h626556[11] && - !_theResult____h626556[10] && - !_theResult____h626556[9] && - !_theResult____h626556[8] && - !_theResult____h626556[7] && - !_theResult____h626556[6] && - !_theResult____h626556[5] && - !_theResult____h626556[4] && - !_theResult____h626556[3] && - !_theResult____h626556[2] && - !_theResult____h626556[1] && - !_theResult____h626556[0] || + assign _theResult___fst_exp__h634733 = + (!_theResult____h626553[56] && !_theResult____h626553[55] && + !_theResult____h626553[54] && + !_theResult____h626553[53] && + !_theResult____h626553[52] && + !_theResult____h626553[51] && + !_theResult____h626553[50] && + !_theResult____h626553[49] && + !_theResult____h626553[48] && + !_theResult____h626553[47] && + !_theResult____h626553[46] && + !_theResult____h626553[45] && + !_theResult____h626553[44] && + !_theResult____h626553[43] && + !_theResult____h626553[42] && + !_theResult____h626553[41] && + !_theResult____h626553[40] && + !_theResult____h626553[39] && + !_theResult____h626553[38] && + !_theResult____h626553[37] && + !_theResult____h626553[36] && + !_theResult____h626553[35] && + !_theResult____h626553[34] && + !_theResult____h626553[33] && + !_theResult____h626553[32] && + !_theResult____h626553[31] && + !_theResult____h626553[30] && + !_theResult____h626553[29] && + !_theResult____h626553[28] && + !_theResult____h626553[27] && + !_theResult____h626553[26] && + !_theResult____h626553[25] && + !_theResult____h626553[24] && + !_theResult____h626553[23] && + !_theResult____h626553[22] && + !_theResult____h626553[21] && + !_theResult____h626553[20] && + !_theResult____h626553[19] && + !_theResult____h626553[18] && + !_theResult____h626553[17] && + !_theResult____h626553[16] && + !_theResult____h626553[15] && + !_theResult____h626553[14] && + !_theResult____h626553[13] && + !_theResult____h626553[12] && + !_theResult____h626553[11] && + !_theResult____h626553[10] && + !_theResult____h626553[9] && + !_theResult____h626553[8] && + !_theResult____h626553[7] && + !_theResult____h626553[6] && + !_theResult____h626553[5] && + !_theResult____h626553[4] && + !_theResult____h626553[3] && + !_theResult____h626553[2] && + !_theResult____h626553[1] && + !_theResult____h626553[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9842) ? 8'd0 : - _theResult___fst_exp__h634730 ; - assign _theResult___fst_exp__h634739 = - (!_theResult____h626556[56] && _theResult____h626556[55]) ? + _theResult___fst_exp__h634727 ; + assign _theResult___fst_exp__h634736 = + (!_theResult____h626553[56] && _theResult____h626553[55]) ? 8'd1 : - _theResult___fst_exp__h634736 ; - assign _theResult___fst_exp__h635262 = - (_theResult___fst_exp__h634665 == 8'd255) ? - _theResult___fst_exp__h634665 : - _theResult___fst_exp__h635259 ; - assign _theResult___fst_exp__h643312 = + _theResult___fst_exp__h634733 ; + assign _theResult___fst_exp__h635259 = + (_theResult___fst_exp__h634662 == 8'd255) ? + _theResult___fst_exp__h634662 : + _theResult___fst_exp__h635256 ; + assign _theResult___fst_exp__h643309 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10071 } ; - assign _theResult___fst_exp__h643318 = + assign _theResult___fst_exp__h643315 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10016 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10073) ? 8'd0 : - _theResult___fst_exp__h643312 ; - assign _theResult___fst_exp__h643321 = + _theResult___fst_exp__h643309 ; + assign _theResult___fst_exp__h643318 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h643318 : + _theResult___fst_exp__h643315 : 8'd129 ; - assign _theResult___fst_exp__h643844 = - (_theResult___fst_exp__h643321 == 8'd255) ? - _theResult___fst_exp__h643321 : - _theResult___fst_exp__h643841 ; - assign _theResult___fst_exp__h652431 = - _theResult____h644193[56] ? + assign _theResult___fst_exp__h643841 = + (_theResult___fst_exp__h643318 == 8'd255) ? + _theResult___fst_exp__h643318 : + _theResult___fst_exp__h643838 ; + assign _theResult___fst_exp__h652428 = + _theResult____h644190[56] ? 8'd2 : - _theResult___fst_exp__h652505 ; - assign _theResult___fst_exp__h652496 = + _theResult___fst_exp__h652502 ; + assign _theResult___fst_exp__h652493 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10391 } ; - assign _theResult___fst_exp__h652502 = - (!_theResult____h644193[56] && !_theResult____h644193[55] && - !_theResult____h644193[54] && - !_theResult____h644193[53] && - !_theResult____h644193[52] && - !_theResult____h644193[51] && - !_theResult____h644193[50] && - !_theResult____h644193[49] && - !_theResult____h644193[48] && - !_theResult____h644193[47] && - !_theResult____h644193[46] && - !_theResult____h644193[45] && - !_theResult____h644193[44] && - !_theResult____h644193[43] && - !_theResult____h644193[42] && - !_theResult____h644193[41] && - !_theResult____h644193[40] && - !_theResult____h644193[39] && - !_theResult____h644193[38] && - !_theResult____h644193[37] && - !_theResult____h644193[36] && - !_theResult____h644193[35] && - !_theResult____h644193[34] && - !_theResult____h644193[33] && - !_theResult____h644193[32] && - !_theResult____h644193[31] && - !_theResult____h644193[30] && - !_theResult____h644193[29] && - !_theResult____h644193[28] && - !_theResult____h644193[27] && - !_theResult____h644193[26] && - !_theResult____h644193[25] && - !_theResult____h644193[24] && - !_theResult____h644193[23] && - !_theResult____h644193[22] && - !_theResult____h644193[21] && - !_theResult____h644193[20] && - !_theResult____h644193[19] && - !_theResult____h644193[18] && - !_theResult____h644193[17] && - !_theResult____h644193[16] && - !_theResult____h644193[15] && - !_theResult____h644193[14] && - !_theResult____h644193[13] && - !_theResult____h644193[12] && - !_theResult____h644193[11] && - !_theResult____h644193[10] && - !_theResult____h644193[9] && - !_theResult____h644193[8] && - !_theResult____h644193[7] && - !_theResult____h644193[6] && - !_theResult____h644193[5] && - !_theResult____h644193[4] && - !_theResult____h644193[3] && - !_theResult____h644193[2] && - !_theResult____h644193[1] && - !_theResult____h644193[0] || + assign _theResult___fst_exp__h652499 = + (!_theResult____h644190[56] && !_theResult____h644190[55] && + !_theResult____h644190[54] && + !_theResult____h644190[53] && + !_theResult____h644190[52] && + !_theResult____h644190[51] && + !_theResult____h644190[50] && + !_theResult____h644190[49] && + !_theResult____h644190[48] && + !_theResult____h644190[47] && + !_theResult____h644190[46] && + !_theResult____h644190[45] && + !_theResult____h644190[44] && + !_theResult____h644190[43] && + !_theResult____h644190[42] && + !_theResult____h644190[41] && + !_theResult____h644190[40] && + !_theResult____h644190[39] && + !_theResult____h644190[38] && + !_theResult____h644190[37] && + !_theResult____h644190[36] && + !_theResult____h644190[35] && + !_theResult____h644190[34] && + !_theResult____h644190[33] && + !_theResult____h644190[32] && + !_theResult____h644190[31] && + !_theResult____h644190[30] && + !_theResult____h644190[29] && + !_theResult____h644190[28] && + !_theResult____h644190[27] && + !_theResult____h644190[26] && + !_theResult____h644190[25] && + !_theResult____h644190[24] && + !_theResult____h644190[23] && + !_theResult____h644190[22] && + !_theResult____h644190[21] && + !_theResult____h644190[20] && + !_theResult____h644190[19] && + !_theResult____h644190[18] && + !_theResult____h644190[17] && + !_theResult____h644190[16] && + !_theResult____h644190[15] && + !_theResult____h644190[14] && + !_theResult____h644190[13] && + !_theResult____h644190[12] && + !_theResult____h644190[11] && + !_theResult____h644190[10] && + !_theResult____h644190[9] && + !_theResult____h644190[8] && + !_theResult____h644190[7] && + !_theResult____h644190[6] && + !_theResult____h644190[5] && + !_theResult____h644190[4] && + !_theResult____h644190[3] && + !_theResult____h644190[2] && + !_theResult____h644190[1] && + !_theResult____h644190[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10393) ? 8'd0 : - _theResult___fst_exp__h652496 ; - assign _theResult___fst_exp__h652505 = - (!_theResult____h644193[56] && _theResult____h644193[55]) ? + _theResult___fst_exp__h652493 ; + assign _theResult___fst_exp__h652502 = + (!_theResult____h644190[56] && _theResult____h644190[55]) ? 8'd1 : - _theResult___fst_exp__h652502 ; - assign _theResult___fst_exp__h653028 = - (_theResult___fst_exp__h652431 == 8'd255) ? - _theResult___fst_exp__h652431 : - _theResult___fst_exp__h653025 ; - assign _theResult___fst_exp__h661068 = + _theResult___fst_exp__h652499 ; + assign _theResult___fst_exp__h653025 = + (_theResult___fst_exp__h652428 == 8'd255) ? + _theResult___fst_exp__h652428 : + _theResult___fst_exp__h653022 ; + assign _theResult___fst_exp__h661065 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] ; - assign _theResult___fst_exp__h661107 = + assign _theResult___fst_exp__h661104 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10071 } ; - assign _theResult___fst_exp__h661113 = + assign _theResult___fst_exp__h661110 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10016 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10466) ? 8'd0 : - _theResult___fst_exp__h661107 ; - assign _theResult___fst_exp__h661116 = + _theResult___fst_exp__h661104 ; + assign _theResult___fst_exp__h661113 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h661110 : + _theResult___fst_exp__h661065 ; + assign _theResult___fst_exp__h661661 = + (_theResult___fst_exp__h661113 == 8'd255) ? _theResult___fst_exp__h661113 : - _theResult___fst_exp__h661068 ; - assign _theResult___fst_exp__h661664 = - (_theResult___fst_exp__h661116 == 8'd255) ? - _theResult___fst_exp__h661116 : - _theResult___fst_exp__h661661 ; - assign _theResult___fst_exp__h661673 = + _theResult___fst_exp__h661658 ; + assign _theResult___fst_exp__h661670 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9605 ? - _theResult___snd_fst_exp__h643847 : - _theResult___fst_exp__h626538) : + _theResult___snd_fst_exp__h643844 : + _theResult___fst_exp__h626535) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10145 ? - _theResult___snd_fst_exp__h661667 : - _theResult___fst_exp__h626538) ; - assign _theResult___fst_exp__h661676 = + _theResult___snd_fst_exp__h661664 : + _theResult___fst_exp__h626535) ; + assign _theResult___fst_exp__h661673 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h661673 ; - assign _theResult___fst_exp__h680412 = - _theResult____h672303[56] ? + _theResult___fst_exp__h661670 ; + assign _theResult___fst_exp__h680409 = + _theResult____h672300[56] ? 8'd2 : - _theResult___fst_exp__h680486 ; - assign _theResult___fst_exp__h680477 = + _theResult___fst_exp__h680483 ; + assign _theResult___fst_exp__h680474 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11237 } ; - assign _theResult___fst_exp__h680483 = - (!_theResult____h672303[56] && !_theResult____h672303[55] && - !_theResult____h672303[54] && - !_theResult____h672303[53] && - !_theResult____h672303[52] && - !_theResult____h672303[51] && - !_theResult____h672303[50] && - !_theResult____h672303[49] && - !_theResult____h672303[48] && - !_theResult____h672303[47] && - !_theResult____h672303[46] && - !_theResult____h672303[45] && - !_theResult____h672303[44] && - !_theResult____h672303[43] && - !_theResult____h672303[42] && - !_theResult____h672303[41] && - !_theResult____h672303[40] && - !_theResult____h672303[39] && - !_theResult____h672303[38] && - !_theResult____h672303[37] && - !_theResult____h672303[36] && - !_theResult____h672303[35] && - !_theResult____h672303[34] && - !_theResult____h672303[33] && - !_theResult____h672303[32] && - !_theResult____h672303[31] && - !_theResult____h672303[30] && - !_theResult____h672303[29] && - !_theResult____h672303[28] && - !_theResult____h672303[27] && - !_theResult____h672303[26] && - !_theResult____h672303[25] && - !_theResult____h672303[24] && - !_theResult____h672303[23] && - !_theResult____h672303[22] && - !_theResult____h672303[21] && - !_theResult____h672303[20] && - !_theResult____h672303[19] && - !_theResult____h672303[18] && - !_theResult____h672303[17] && - !_theResult____h672303[16] && - !_theResult____h672303[15] && - !_theResult____h672303[14] && - !_theResult____h672303[13] && - !_theResult____h672303[12] && - !_theResult____h672303[11] && - !_theResult____h672303[10] && - !_theResult____h672303[9] && - !_theResult____h672303[8] && - !_theResult____h672303[7] && - !_theResult____h672303[6] && - !_theResult____h672303[5] && - !_theResult____h672303[4] && - !_theResult____h672303[3] && - !_theResult____h672303[2] && - !_theResult____h672303[1] && - !_theResult____h672303[0] || + assign _theResult___fst_exp__h680480 = + (!_theResult____h672300[56] && !_theResult____h672300[55] && + !_theResult____h672300[54] && + !_theResult____h672300[53] && + !_theResult____h672300[52] && + !_theResult____h672300[51] && + !_theResult____h672300[50] && + !_theResult____h672300[49] && + !_theResult____h672300[48] && + !_theResult____h672300[47] && + !_theResult____h672300[46] && + !_theResult____h672300[45] && + !_theResult____h672300[44] && + !_theResult____h672300[43] && + !_theResult____h672300[42] && + !_theResult____h672300[41] && + !_theResult____h672300[40] && + !_theResult____h672300[39] && + !_theResult____h672300[38] && + !_theResult____h672300[37] && + !_theResult____h672300[36] && + !_theResult____h672300[35] && + !_theResult____h672300[34] && + !_theResult____h672300[33] && + !_theResult____h672300[32] && + !_theResult____h672300[31] && + !_theResult____h672300[30] && + !_theResult____h672300[29] && + !_theResult____h672300[28] && + !_theResult____h672300[27] && + !_theResult____h672300[26] && + !_theResult____h672300[25] && + !_theResult____h672300[24] && + !_theResult____h672300[23] && + !_theResult____h672300[22] && + !_theResult____h672300[21] && + !_theResult____h672300[20] && + !_theResult____h672300[19] && + !_theResult____h672300[18] && + !_theResult____h672300[17] && + !_theResult____h672300[16] && + !_theResult____h672300[15] && + !_theResult____h672300[14] && + !_theResult____h672300[13] && + !_theResult____h672300[12] && + !_theResult____h672300[11] && + !_theResult____h672300[10] && + !_theResult____h672300[9] && + !_theResult____h672300[8] && + !_theResult____h672300[7] && + !_theResult____h672300[6] && + !_theResult____h672300[5] && + !_theResult____h672300[4] && + !_theResult____h672300[3] && + !_theResult____h672300[2] && + !_theResult____h672300[1] && + !_theResult____h672300[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11239) ? 8'd0 : - _theResult___fst_exp__h680477 ; - assign _theResult___fst_exp__h680486 = - (!_theResult____h672303[56] && _theResult____h672303[55]) ? + _theResult___fst_exp__h680474 ; + assign _theResult___fst_exp__h680483 = + (!_theResult____h672300[56] && _theResult____h672300[55]) ? 8'd1 : - _theResult___fst_exp__h680483 ; - assign _theResult___fst_exp__h681009 = - (_theResult___fst_exp__h680412 == 8'd255) ? - _theResult___fst_exp__h680412 : - _theResult___fst_exp__h681006 ; - assign _theResult___fst_exp__h689059 = + _theResult___fst_exp__h680480 ; + assign _theResult___fst_exp__h681006 = + (_theResult___fst_exp__h680409 == 8'd255) ? + _theResult___fst_exp__h680409 : + _theResult___fst_exp__h681003 ; + assign _theResult___fst_exp__h689056 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11468 } ; - assign _theResult___fst_exp__h689065 = + assign _theResult___fst_exp__h689062 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11413 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11470) ? 8'd0 : - _theResult___fst_exp__h689059 ; - assign _theResult___fst_exp__h689068 = + _theResult___fst_exp__h689056 ; + assign _theResult___fst_exp__h689065 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h689065 : + _theResult___fst_exp__h689062 : 8'd129 ; - assign _theResult___fst_exp__h689591 = - (_theResult___fst_exp__h689068 == 8'd255) ? - _theResult___fst_exp__h689068 : - _theResult___fst_exp__h689588 ; - assign _theResult___fst_exp__h698178 = - _theResult____h689940[56] ? + assign _theResult___fst_exp__h689588 = + (_theResult___fst_exp__h689065 == 8'd255) ? + _theResult___fst_exp__h689065 : + _theResult___fst_exp__h689585 ; + assign _theResult___fst_exp__h698175 = + _theResult____h689937[56] ? 8'd2 : - _theResult___fst_exp__h698252 ; - assign _theResult___fst_exp__h698243 = + _theResult___fst_exp__h698249 ; + assign _theResult___fst_exp__h698240 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11788 } ; - assign _theResult___fst_exp__h698249 = - (!_theResult____h689940[56] && !_theResult____h689940[55] && - !_theResult____h689940[54] && - !_theResult____h689940[53] && - !_theResult____h689940[52] && - !_theResult____h689940[51] && - !_theResult____h689940[50] && - !_theResult____h689940[49] && - !_theResult____h689940[48] && - !_theResult____h689940[47] && - !_theResult____h689940[46] && - !_theResult____h689940[45] && - !_theResult____h689940[44] && - !_theResult____h689940[43] && - !_theResult____h689940[42] && - !_theResult____h689940[41] && - !_theResult____h689940[40] && - !_theResult____h689940[39] && - !_theResult____h689940[38] && - !_theResult____h689940[37] && - !_theResult____h689940[36] && - !_theResult____h689940[35] && - !_theResult____h689940[34] && - !_theResult____h689940[33] && - !_theResult____h689940[32] && - !_theResult____h689940[31] && - !_theResult____h689940[30] && - !_theResult____h689940[29] && - !_theResult____h689940[28] && - !_theResult____h689940[27] && - !_theResult____h689940[26] && - !_theResult____h689940[25] && - !_theResult____h689940[24] && - !_theResult____h689940[23] && - !_theResult____h689940[22] && - !_theResult____h689940[21] && - !_theResult____h689940[20] && - !_theResult____h689940[19] && - !_theResult____h689940[18] && - !_theResult____h689940[17] && - !_theResult____h689940[16] && - !_theResult____h689940[15] && - !_theResult____h689940[14] && - !_theResult____h689940[13] && - !_theResult____h689940[12] && - !_theResult____h689940[11] && - !_theResult____h689940[10] && - !_theResult____h689940[9] && - !_theResult____h689940[8] && - !_theResult____h689940[7] && - !_theResult____h689940[6] && - !_theResult____h689940[5] && - !_theResult____h689940[4] && - !_theResult____h689940[3] && - !_theResult____h689940[2] && - !_theResult____h689940[1] && - !_theResult____h689940[0] || + assign _theResult___fst_exp__h698246 = + (!_theResult____h689937[56] && !_theResult____h689937[55] && + !_theResult____h689937[54] && + !_theResult____h689937[53] && + !_theResult____h689937[52] && + !_theResult____h689937[51] && + !_theResult____h689937[50] && + !_theResult____h689937[49] && + !_theResult____h689937[48] && + !_theResult____h689937[47] && + !_theResult____h689937[46] && + !_theResult____h689937[45] && + !_theResult____h689937[44] && + !_theResult____h689937[43] && + !_theResult____h689937[42] && + !_theResult____h689937[41] && + !_theResult____h689937[40] && + !_theResult____h689937[39] && + !_theResult____h689937[38] && + !_theResult____h689937[37] && + !_theResult____h689937[36] && + !_theResult____h689937[35] && + !_theResult____h689937[34] && + !_theResult____h689937[33] && + !_theResult____h689937[32] && + !_theResult____h689937[31] && + !_theResult____h689937[30] && + !_theResult____h689937[29] && + !_theResult____h689937[28] && + !_theResult____h689937[27] && + !_theResult____h689937[26] && + !_theResult____h689937[25] && + !_theResult____h689937[24] && + !_theResult____h689937[23] && + !_theResult____h689937[22] && + !_theResult____h689937[21] && + !_theResult____h689937[20] && + !_theResult____h689937[19] && + !_theResult____h689937[18] && + !_theResult____h689937[17] && + !_theResult____h689937[16] && + !_theResult____h689937[15] && + !_theResult____h689937[14] && + !_theResult____h689937[13] && + !_theResult____h689937[12] && + !_theResult____h689937[11] && + !_theResult____h689937[10] && + !_theResult____h689937[9] && + !_theResult____h689937[8] && + !_theResult____h689937[7] && + !_theResult____h689937[6] && + !_theResult____h689937[5] && + !_theResult____h689937[4] && + !_theResult____h689937[3] && + !_theResult____h689937[2] && + !_theResult____h689937[1] && + !_theResult____h689937[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11790) ? 8'd0 : - _theResult___fst_exp__h698243 ; - assign _theResult___fst_exp__h698252 = - (!_theResult____h689940[56] && _theResult____h689940[55]) ? + _theResult___fst_exp__h698240 ; + assign _theResult___fst_exp__h698249 = + (!_theResult____h689937[56] && _theResult____h689937[55]) ? 8'd1 : - _theResult___fst_exp__h698249 ; - assign _theResult___fst_exp__h698775 = - (_theResult___fst_exp__h698178 == 8'd255) ? - _theResult___fst_exp__h698178 : - _theResult___fst_exp__h698772 ; - assign _theResult___fst_exp__h706815 = + _theResult___fst_exp__h698246 ; + assign _theResult___fst_exp__h698772 = + (_theResult___fst_exp__h698175 == 8'd255) ? + _theResult___fst_exp__h698175 : + _theResult___fst_exp__h698769 ; + assign _theResult___fst_exp__h706812 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] ; - assign _theResult___fst_exp__h706854 = + assign _theResult___fst_exp__h706851 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11468 } ; - assign _theResult___fst_exp__h706860 = + assign _theResult___fst_exp__h706857 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11413 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11863) ? 8'd0 : - _theResult___fst_exp__h706854 ; - assign _theResult___fst_exp__h706863 = + _theResult___fst_exp__h706851 ; + assign _theResult___fst_exp__h706860 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h706857 : + _theResult___fst_exp__h706812 ; + assign _theResult___fst_exp__h707408 = + (_theResult___fst_exp__h706860 == 8'd255) ? _theResult___fst_exp__h706860 : - _theResult___fst_exp__h706815 ; - assign _theResult___fst_exp__h707411 = - (_theResult___fst_exp__h706863 == 8'd255) ? - _theResult___fst_exp__h706863 : - _theResult___fst_exp__h707408 ; - assign _theResult___fst_exp__h707420 = + _theResult___fst_exp__h707405 ; + assign _theResult___fst_exp__h707417 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11002 ? - _theResult___snd_fst_exp__h689594 : - _theResult___fst_exp__h672285) : + _theResult___snd_fst_exp__h689591 : + _theResult___fst_exp__h672282) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11542 ? - _theResult___snd_fst_exp__h707414 : - _theResult___fst_exp__h672285) ; - assign _theResult___fst_exp__h707423 = + _theResult___snd_fst_exp__h707411 : + _theResult___fst_exp__h672282) ; + assign _theResult___fst_exp__h707420 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h707420 ; - assign _theResult___fst_exp__h724072 = + _theResult___fst_exp__h707417 ; + assign _theResult___fst_exp__h724069 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 ; - assign _theResult___fst_exp__h739136 = + assign _theResult___fst_exp__h739133 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12822 } ; - assign _theResult___fst_exp__h739142 = - (f1_exp__h719757 == 8'd0 && !f1_sfd__h719758[22] && + assign _theResult___fst_exp__h739139 = + (f1_exp__h719754 == 8'd0 && !f1_sfd__h719755[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12795 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12824) ? 11'd0 : - _theResult___fst_exp__h739136 ; - assign _theResult___fst_exp__h739145 = - (f1_exp__h719757 == 8'd0) ? - _theResult___fst_exp__h739142 : + _theResult___fst_exp__h739133 ; + assign _theResult___fst_exp__h739142 = + (f1_exp__h719754 == 8'd0) ? + _theResult___fst_exp__h739139 : 11'd897 ; - assign _theResult___fst_exp__h739900 = + assign _theResult___fst_exp__h739897 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q155 : + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q155 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13258 ; - assign _theResult___fst_exp__h739903 = - (_theResult___fst_exp__h739145 == 11'd2047) ? - _theResult___fst_exp__h739145 : - _theResult___fst_exp__h739900 ; - assign _theResult___fst_exp__h748722 = - _theResult____h740486[56] ? + assign _theResult___fst_exp__h739900 = + (_theResult___fst_exp__h739142 == 11'd2047) ? + _theResult___fst_exp__h739142 : + _theResult___fst_exp__h739897 ; + assign _theResult___fst_exp__h748719 = + _theResult____h740483[56] ? 11'd2 : - _theResult___fst_exp__h748796 ; - assign _theResult___fst_exp__h748787 = + _theResult___fst_exp__h748793 ; + assign _theResult___fst_exp__h748784 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13134 } ; - assign _theResult___fst_exp__h748793 = - (!_theResult____h740486[56] && !_theResult____h740486[55] && - !_theResult____h740486[54] && - !_theResult____h740486[53] && - !_theResult____h740486[52] && - !_theResult____h740486[51] && - !_theResult____h740486[50] && - !_theResult____h740486[49] && - !_theResult____h740486[48] && - !_theResult____h740486[47] && - !_theResult____h740486[46] && - !_theResult____h740486[45] && - !_theResult____h740486[44] && - !_theResult____h740486[43] && - !_theResult____h740486[42] && - !_theResult____h740486[41] && - !_theResult____h740486[40] && - !_theResult____h740486[39] && - !_theResult____h740486[38] && - !_theResult____h740486[37] && - !_theResult____h740486[36] && - !_theResult____h740486[35] && - !_theResult____h740486[34] && - !_theResult____h740486[33] && - !_theResult____h740486[32] && - !_theResult____h740486[31] && - !_theResult____h740486[30] && - !_theResult____h740486[29] && - !_theResult____h740486[28] && - !_theResult____h740486[27] && - !_theResult____h740486[26] && - !_theResult____h740486[25] && - !_theResult____h740486[24] && - !_theResult____h740486[23] && - !_theResult____h740486[22] && - !_theResult____h740486[21] && - !_theResult____h740486[20] && - !_theResult____h740486[19] && - !_theResult____h740486[18] && - !_theResult____h740486[17] && - !_theResult____h740486[16] && - !_theResult____h740486[15] && - !_theResult____h740486[14] && - !_theResult____h740486[13] && - !_theResult____h740486[12] && - !_theResult____h740486[11] && - !_theResult____h740486[10] && - !_theResult____h740486[9] && - !_theResult____h740486[8] && - !_theResult____h740486[7] && - !_theResult____h740486[6] && - !_theResult____h740486[5] && - !_theResult____h740486[4] && - !_theResult____h740486[3] && - !_theResult____h740486[2] && - !_theResult____h740486[1] && - !_theResult____h740486[0] || + assign _theResult___fst_exp__h748790 = + (!_theResult____h740483[56] && !_theResult____h740483[55] && + !_theResult____h740483[54] && + !_theResult____h740483[53] && + !_theResult____h740483[52] && + !_theResult____h740483[51] && + !_theResult____h740483[50] && + !_theResult____h740483[49] && + !_theResult____h740483[48] && + !_theResult____h740483[47] && + !_theResult____h740483[46] && + !_theResult____h740483[45] && + !_theResult____h740483[44] && + !_theResult____h740483[43] && + !_theResult____h740483[42] && + !_theResult____h740483[41] && + !_theResult____h740483[40] && + !_theResult____h740483[39] && + !_theResult____h740483[38] && + !_theResult____h740483[37] && + !_theResult____h740483[36] && + !_theResult____h740483[35] && + !_theResult____h740483[34] && + !_theResult____h740483[33] && + !_theResult____h740483[32] && + !_theResult____h740483[31] && + !_theResult____h740483[30] && + !_theResult____h740483[29] && + !_theResult____h740483[28] && + !_theResult____h740483[27] && + !_theResult____h740483[26] && + !_theResult____h740483[25] && + !_theResult____h740483[24] && + !_theResult____h740483[23] && + !_theResult____h740483[22] && + !_theResult____h740483[21] && + !_theResult____h740483[20] && + !_theResult____h740483[19] && + !_theResult____h740483[18] && + !_theResult____h740483[17] && + !_theResult____h740483[16] && + !_theResult____h740483[15] && + !_theResult____h740483[14] && + !_theResult____h740483[13] && + !_theResult____h740483[12] && + !_theResult____h740483[11] && + !_theResult____h740483[10] && + !_theResult____h740483[9] && + !_theResult____h740483[8] && + !_theResult____h740483[7] && + !_theResult____h740483[6] && + !_theResult____h740483[5] && + !_theResult____h740483[4] && + !_theResult____h740483[3] && + !_theResult____h740483[2] && + !_theResult____h740483[1] && + !_theResult____h740483[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13136) ? 11'd0 : - _theResult___fst_exp__h748787 ; - assign _theResult___fst_exp__h748796 = - (!_theResult____h740486[56] && _theResult____h740486[55]) ? + _theResult___fst_exp__h748784 ; + assign _theResult___fst_exp__h748793 = + (!_theResult____h740483[56] && _theResult____h740483[55]) ? 11'd1 : - _theResult___fst_exp__h748793 ; - assign _theResult___fst_exp__h749551 = + _theResult___fst_exp__h748790 ; + assign _theResult___fst_exp__h749548 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q223 : + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q223 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13301 ; - assign _theResult___fst_exp__h749554 = - (_theResult___fst_exp__h748722 == 11'd2047) ? - _theResult___fst_exp__h748722 : - _theResult___fst_exp__h749551 ; - assign _theResult___fst_exp__h757507 = + assign _theResult___fst_exp__h749551 = + (_theResult___fst_exp__h748719 == 11'd2047) ? + _theResult___fst_exp__h748719 : + _theResult___fst_exp__h749548 ; + assign _theResult___fst_exp__h757504 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] ; - assign _theResult___fst_exp__h757546 = + assign _theResult___fst_exp__h757543 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12822 } ; - assign _theResult___fst_exp__h757552 = - (f1_exp__h719757 == 8'd0 && !f1_sfd__h719758[22] && + assign _theResult___fst_exp__h757549 = + (f1_exp__h719754 == 8'd0 && !f1_sfd__h719755[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12795 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13186) ? 11'd0 : - _theResult___fst_exp__h757546 ; - assign _theResult___fst_exp__h757555 = - (f1_exp__h719757 == 8'd0) ? - _theResult___fst_exp__h757552 : - _theResult___fst_exp__h757507 ; - assign _theResult___fst_exp__h758335 = + _theResult___fst_exp__h757543 ; + assign _theResult___fst_exp__h757552 = + (f1_exp__h719754 == 8'd0) ? + _theResult___fst_exp__h757549 : + _theResult___fst_exp__h757504 ; + assign _theResult___fst_exp__h758332 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q225 : + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q225 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13332 ; - assign _theResult___fst_exp__h758338 = - (_theResult___fst_exp__h757555 == 11'd2047) ? - _theResult___fst_exp__h757555 : - _theResult___fst_exp__h758335 ; - assign _theResult___fst_exp__h758347 = - (f1_exp__h719757 == 8'd0) ? + assign _theResult___fst_exp__h758335 = + (_theResult___fst_exp__h757552 == 11'd2047) ? + _theResult___fst_exp__h757552 : + _theResult___fst_exp__h758332 ; + assign _theResult___fst_exp__h758344 = + (f1_exp__h719754 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 ? - _theResult___snd_fst_exp__h739906 : - _theResult___fst_exp__h724072) : + _theResult___snd_fst_exp__h739903 : + _theResult___fst_exp__h724069) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12886 ? - _theResult___snd_fst_exp__h758341 : - _theResult___fst_exp__h724072) ; - assign _theResult___fst_exp__h758350 = - (f1_exp__h719757 == 8'd0 && f1_sfd__h719758 == 23'd0) ? + _theResult___snd_fst_exp__h758338 : + _theResult___fst_exp__h724069) ; + assign _theResult___fst_exp__h758347 = + (f1_exp__h719754 == 8'd0 && f1_sfd__h719755 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h758347 ; - assign _theResult___fst_exp__h762925 = + _theResult___fst_exp__h758344 ; + assign _theResult___fst_exp__h762922 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 ; - assign _theResult___fst_exp__h777989 = + assign _theResult___fst_exp__h777986 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14322 } ; - assign _theResult___fst_exp__h777995 = - (f2_exp__h758751 == 8'd0 && !f2_sfd__h758752[22] && + assign _theResult___fst_exp__h777992 = + (f2_exp__h758748 == 8'd0 && !f2_sfd__h758749[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14295 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14324) ? 11'd0 : - _theResult___fst_exp__h777989 ; - assign _theResult___fst_exp__h777998 = - (f2_exp__h758751 == 8'd0) ? - _theResult___fst_exp__h777995 : + _theResult___fst_exp__h777986 ; + assign _theResult___fst_exp__h777995 = + (f2_exp__h758748 == 8'd0) ? + _theResult___fst_exp__h777992 : 11'd897 ; - assign _theResult___fst_exp__h778753 = + assign _theResult___fst_exp__h778750 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q195 : + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q195 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14743 ; - assign _theResult___fst_exp__h778756 = - (_theResult___fst_exp__h777998 == 11'd2047) ? - _theResult___fst_exp__h777998 : - _theResult___fst_exp__h778753 ; - assign _theResult___fst_exp__h787575 = - _theResult____h779339[56] ? + assign _theResult___fst_exp__h778753 = + (_theResult___fst_exp__h777995 == 11'd2047) ? + _theResult___fst_exp__h777995 : + _theResult___fst_exp__h778750 ; + assign _theResult___fst_exp__h787572 = + _theResult____h779336[56] ? 11'd2 : - _theResult___fst_exp__h787649 ; - assign _theResult___fst_exp__h787640 = + _theResult___fst_exp__h787646 ; + assign _theResult___fst_exp__h787637 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14619 } ; - assign _theResult___fst_exp__h787646 = - (!_theResult____h779339[56] && !_theResult____h779339[55] && - !_theResult____h779339[54] && - !_theResult____h779339[53] && - !_theResult____h779339[52] && - !_theResult____h779339[51] && - !_theResult____h779339[50] && - !_theResult____h779339[49] && - !_theResult____h779339[48] && - !_theResult____h779339[47] && - !_theResult____h779339[46] && - !_theResult____h779339[45] && - !_theResult____h779339[44] && - !_theResult____h779339[43] && - !_theResult____h779339[42] && - !_theResult____h779339[41] && - !_theResult____h779339[40] && - !_theResult____h779339[39] && - !_theResult____h779339[38] && - !_theResult____h779339[37] && - !_theResult____h779339[36] && - !_theResult____h779339[35] && - !_theResult____h779339[34] && - !_theResult____h779339[33] && - !_theResult____h779339[32] && - !_theResult____h779339[31] && - !_theResult____h779339[30] && - !_theResult____h779339[29] && - !_theResult____h779339[28] && - !_theResult____h779339[27] && - !_theResult____h779339[26] && - !_theResult____h779339[25] && - !_theResult____h779339[24] && - !_theResult____h779339[23] && - !_theResult____h779339[22] && - !_theResult____h779339[21] && - !_theResult____h779339[20] && - !_theResult____h779339[19] && - !_theResult____h779339[18] && - !_theResult____h779339[17] && - !_theResult____h779339[16] && - !_theResult____h779339[15] && - !_theResult____h779339[14] && - !_theResult____h779339[13] && - !_theResult____h779339[12] && - !_theResult____h779339[11] && - !_theResult____h779339[10] && - !_theResult____h779339[9] && - !_theResult____h779339[8] && - !_theResult____h779339[7] && - !_theResult____h779339[6] && - !_theResult____h779339[5] && - !_theResult____h779339[4] && - !_theResult____h779339[3] && - !_theResult____h779339[2] && - !_theResult____h779339[1] && - !_theResult____h779339[0] || + assign _theResult___fst_exp__h787643 = + (!_theResult____h779336[56] && !_theResult____h779336[55] && + !_theResult____h779336[54] && + !_theResult____h779336[53] && + !_theResult____h779336[52] && + !_theResult____h779336[51] && + !_theResult____h779336[50] && + !_theResult____h779336[49] && + !_theResult____h779336[48] && + !_theResult____h779336[47] && + !_theResult____h779336[46] && + !_theResult____h779336[45] && + !_theResult____h779336[44] && + !_theResult____h779336[43] && + !_theResult____h779336[42] && + !_theResult____h779336[41] && + !_theResult____h779336[40] && + !_theResult____h779336[39] && + !_theResult____h779336[38] && + !_theResult____h779336[37] && + !_theResult____h779336[36] && + !_theResult____h779336[35] && + !_theResult____h779336[34] && + !_theResult____h779336[33] && + !_theResult____h779336[32] && + !_theResult____h779336[31] && + !_theResult____h779336[30] && + !_theResult____h779336[29] && + !_theResult____h779336[28] && + !_theResult____h779336[27] && + !_theResult____h779336[26] && + !_theResult____h779336[25] && + !_theResult____h779336[24] && + !_theResult____h779336[23] && + !_theResult____h779336[22] && + !_theResult____h779336[21] && + !_theResult____h779336[20] && + !_theResult____h779336[19] && + !_theResult____h779336[18] && + !_theResult____h779336[17] && + !_theResult____h779336[16] && + !_theResult____h779336[15] && + !_theResult____h779336[14] && + !_theResult____h779336[13] && + !_theResult____h779336[12] && + !_theResult____h779336[11] && + !_theResult____h779336[10] && + !_theResult____h779336[9] && + !_theResult____h779336[8] && + !_theResult____h779336[7] && + !_theResult____h779336[6] && + !_theResult____h779336[5] && + !_theResult____h779336[4] && + !_theResult____h779336[3] && + !_theResult____h779336[2] && + !_theResult____h779336[1] && + !_theResult____h779336[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14621) ? 11'd0 : - _theResult___fst_exp__h787640 ; - assign _theResult___fst_exp__h787649 = - (!_theResult____h779339[56] && _theResult____h779339[55]) ? + _theResult___fst_exp__h787637 ; + assign _theResult___fst_exp__h787646 = + (!_theResult____h779336[56] && _theResult____h779336[55]) ? 11'd1 : - _theResult___fst_exp__h787646 ; - assign _theResult___fst_exp__h788404 = + _theResult___fst_exp__h787643 ; + assign _theResult___fst_exp__h788401 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q197 : + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q197 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14781 ; - assign _theResult___fst_exp__h788407 = - (_theResult___fst_exp__h787575 == 11'd2047) ? - _theResult___fst_exp__h787575 : - _theResult___fst_exp__h788404 ; - assign _theResult___fst_exp__h796360 = + assign _theResult___fst_exp__h788404 = + (_theResult___fst_exp__h787572 == 11'd2047) ? + _theResult___fst_exp__h787572 : + _theResult___fst_exp__h788401 ; + assign _theResult___fst_exp__h796357 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] ; - assign _theResult___fst_exp__h796399 = + assign _theResult___fst_exp__h796396 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14322 } ; - assign _theResult___fst_exp__h796405 = - (f2_exp__h758751 == 8'd0 && !f2_sfd__h758752[22] && + assign _theResult___fst_exp__h796402 = + (f2_exp__h758748 == 8'd0 && !f2_sfd__h758749[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14295 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14671) ? 11'd0 : - _theResult___fst_exp__h796399 ; - assign _theResult___fst_exp__h796408 = - (f2_exp__h758751 == 8'd0) ? - _theResult___fst_exp__h796405 : - _theResult___fst_exp__h796360 ; - assign _theResult___fst_exp__h797188 = + _theResult___fst_exp__h796396 ; + assign _theResult___fst_exp__h796405 = + (f2_exp__h758748 == 8'd0) ? + _theResult___fst_exp__h796402 : + _theResult___fst_exp__h796357 ; + assign _theResult___fst_exp__h797185 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q199 : + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q199 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14812 ; - assign _theResult___fst_exp__h797191 = - (_theResult___fst_exp__h796408 == 11'd2047) ? - _theResult___fst_exp__h796408 : - _theResult___fst_exp__h797188 ; - assign _theResult___fst_exp__h797200 = - (f2_exp__h758751 == 8'd0) ? + assign _theResult___fst_exp__h797188 = + (_theResult___fst_exp__h796405 == 11'd2047) ? + _theResult___fst_exp__h796405 : + _theResult___fst_exp__h797185 ; + assign _theResult___fst_exp__h797197 = + (f2_exp__h758748 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 ? - _theResult___snd_fst_exp__h778759 : - _theResult___fst_exp__h762925) : + _theResult___snd_fst_exp__h778756 : + _theResult___fst_exp__h762922) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14371 ? - _theResult___snd_fst_exp__h797194 : - _theResult___fst_exp__h762925) ; - assign _theResult___fst_exp__h797203 = - (f2_exp__h758751 == 8'd0 && f2_sfd__h758752 == 23'd0) ? + _theResult___snd_fst_exp__h797191 : + _theResult___fst_exp__h762922) ; + assign _theResult___fst_exp__h797200 = + (f2_exp__h758748 == 8'd0 && f2_sfd__h758749 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h797200 ; - assign _theResult___fst_exp__h802229 = + _theResult___fst_exp__h797197 ; + assign _theResult___fst_exp__h802226 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 ; - assign _theResult___fst_exp__h817293 = + assign _theResult___fst_exp__h817290 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13552 } ; - assign _theResult___fst_exp__h817299 = - (f3_exp__h798055 == 8'd0 && !f3_sfd__h798056[22] && + assign _theResult___fst_exp__h817296 = + (f3_exp__h798052 == 8'd0 && !f3_sfd__h798053[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13525 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13554) ? 11'd0 : - _theResult___fst_exp__h817293 ; - assign _theResult___fst_exp__h817302 = - (f3_exp__h798055 == 8'd0) ? - _theResult___fst_exp__h817299 : + _theResult___fst_exp__h817290 ; + assign _theResult___fst_exp__h817299 = + (f3_exp__h798052 == 8'd0) ? + _theResult___fst_exp__h817296 : 11'd897 ; - assign _theResult___fst_exp__h818057 = + assign _theResult___fst_exp__h818054 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q172 : + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q172 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13973 ; - assign _theResult___fst_exp__h818060 = - (_theResult___fst_exp__h817302 == 11'd2047) ? - _theResult___fst_exp__h817302 : - _theResult___fst_exp__h818057 ; - assign _theResult___fst_exp__h826879 = - _theResult____h818643[56] ? + assign _theResult___fst_exp__h818057 = + (_theResult___fst_exp__h817299 == 11'd2047) ? + _theResult___fst_exp__h817299 : + _theResult___fst_exp__h818054 ; + assign _theResult___fst_exp__h826876 = + _theResult____h818640[56] ? 11'd2 : - _theResult___fst_exp__h826953 ; - assign _theResult___fst_exp__h826944 = + _theResult___fst_exp__h826950 ; + assign _theResult___fst_exp__h826941 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13849 } ; - assign _theResult___fst_exp__h826950 = - (!_theResult____h818643[56] && !_theResult____h818643[55] && - !_theResult____h818643[54] && - !_theResult____h818643[53] && - !_theResult____h818643[52] && - !_theResult____h818643[51] && - !_theResult____h818643[50] && - !_theResult____h818643[49] && - !_theResult____h818643[48] && - !_theResult____h818643[47] && - !_theResult____h818643[46] && - !_theResult____h818643[45] && - !_theResult____h818643[44] && - !_theResult____h818643[43] && - !_theResult____h818643[42] && - !_theResult____h818643[41] && - !_theResult____h818643[40] && - !_theResult____h818643[39] && - !_theResult____h818643[38] && - !_theResult____h818643[37] && - !_theResult____h818643[36] && - !_theResult____h818643[35] && - !_theResult____h818643[34] && - !_theResult____h818643[33] && - !_theResult____h818643[32] && - !_theResult____h818643[31] && - !_theResult____h818643[30] && - !_theResult____h818643[29] && - !_theResult____h818643[28] && - !_theResult____h818643[27] && - !_theResult____h818643[26] && - !_theResult____h818643[25] && - !_theResult____h818643[24] && - !_theResult____h818643[23] && - !_theResult____h818643[22] && - !_theResult____h818643[21] && - !_theResult____h818643[20] && - !_theResult____h818643[19] && - !_theResult____h818643[18] && - !_theResult____h818643[17] && - !_theResult____h818643[16] && - !_theResult____h818643[15] && - !_theResult____h818643[14] && - !_theResult____h818643[13] && - !_theResult____h818643[12] && - !_theResult____h818643[11] && - !_theResult____h818643[10] && - !_theResult____h818643[9] && - !_theResult____h818643[8] && - !_theResult____h818643[7] && - !_theResult____h818643[6] && - !_theResult____h818643[5] && - !_theResult____h818643[4] && - !_theResult____h818643[3] && - !_theResult____h818643[2] && - !_theResult____h818643[1] && - !_theResult____h818643[0] || + assign _theResult___fst_exp__h826947 = + (!_theResult____h818640[56] && !_theResult____h818640[55] && + !_theResult____h818640[54] && + !_theResult____h818640[53] && + !_theResult____h818640[52] && + !_theResult____h818640[51] && + !_theResult____h818640[50] && + !_theResult____h818640[49] && + !_theResult____h818640[48] && + !_theResult____h818640[47] && + !_theResult____h818640[46] && + !_theResult____h818640[45] && + !_theResult____h818640[44] && + !_theResult____h818640[43] && + !_theResult____h818640[42] && + !_theResult____h818640[41] && + !_theResult____h818640[40] && + !_theResult____h818640[39] && + !_theResult____h818640[38] && + !_theResult____h818640[37] && + !_theResult____h818640[36] && + !_theResult____h818640[35] && + !_theResult____h818640[34] && + !_theResult____h818640[33] && + !_theResult____h818640[32] && + !_theResult____h818640[31] && + !_theResult____h818640[30] && + !_theResult____h818640[29] && + !_theResult____h818640[28] && + !_theResult____h818640[27] && + !_theResult____h818640[26] && + !_theResult____h818640[25] && + !_theResult____h818640[24] && + !_theResult____h818640[23] && + !_theResult____h818640[22] && + !_theResult____h818640[21] && + !_theResult____h818640[20] && + !_theResult____h818640[19] && + !_theResult____h818640[18] && + !_theResult____h818640[17] && + !_theResult____h818640[16] && + !_theResult____h818640[15] && + !_theResult____h818640[14] && + !_theResult____h818640[13] && + !_theResult____h818640[12] && + !_theResult____h818640[11] && + !_theResult____h818640[10] && + !_theResult____h818640[9] && + !_theResult____h818640[8] && + !_theResult____h818640[7] && + !_theResult____h818640[6] && + !_theResult____h818640[5] && + !_theResult____h818640[4] && + !_theResult____h818640[3] && + !_theResult____h818640[2] && + !_theResult____h818640[1] && + !_theResult____h818640[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13851) ? 11'd0 : - _theResult___fst_exp__h826944 ; - assign _theResult___fst_exp__h826953 = - (!_theResult____h818643[56] && _theResult____h818643[55]) ? + _theResult___fst_exp__h826941 ; + assign _theResult___fst_exp__h826950 = + (!_theResult____h818640[56] && _theResult____h818640[55]) ? 11'd1 : - _theResult___fst_exp__h826950 ; - assign _theResult___fst_exp__h827708 = + _theResult___fst_exp__h826947 ; + assign _theResult___fst_exp__h827705 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q201 : + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q201 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14011 ; - assign _theResult___fst_exp__h827711 = - (_theResult___fst_exp__h826879 == 11'd2047) ? - _theResult___fst_exp__h826879 : - _theResult___fst_exp__h827708 ; - assign _theResult___fst_exp__h835664 = + assign _theResult___fst_exp__h827708 = + (_theResult___fst_exp__h826876 == 11'd2047) ? + _theResult___fst_exp__h826876 : + _theResult___fst_exp__h827705 ; + assign _theResult___fst_exp__h835661 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] ; - assign _theResult___fst_exp__h835703 = + assign _theResult___fst_exp__h835700 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13552 } ; - assign _theResult___fst_exp__h835709 = - (f3_exp__h798055 == 8'd0 && !f3_sfd__h798056[22] && + assign _theResult___fst_exp__h835706 = + (f3_exp__h798052 == 8'd0 && !f3_sfd__h798053[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13525 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13901) ? 11'd0 : - _theResult___fst_exp__h835703 ; - assign _theResult___fst_exp__h835712 = - (f3_exp__h798055 == 8'd0) ? - _theResult___fst_exp__h835709 : - _theResult___fst_exp__h835664 ; - assign _theResult___fst_exp__h836492 = + _theResult___fst_exp__h835700 ; + assign _theResult___fst_exp__h835709 = + (f3_exp__h798052 == 8'd0) ? + _theResult___fst_exp__h835706 : + _theResult___fst_exp__h835661 ; + assign _theResult___fst_exp__h836489 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q203 : + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q203 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14042 ; - assign _theResult___fst_exp__h836495 = - (_theResult___fst_exp__h835712 == 11'd2047) ? - _theResult___fst_exp__h835712 : - _theResult___fst_exp__h836492 ; - assign _theResult___fst_exp__h836504 = - (f3_exp__h798055 == 8'd0) ? + assign _theResult___fst_exp__h836492 = + (_theResult___fst_exp__h835709 == 11'd2047) ? + _theResult___fst_exp__h835709 : + _theResult___fst_exp__h836489 ; + assign _theResult___fst_exp__h836501 = + (f3_exp__h798052 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 ? - _theResult___snd_fst_exp__h818063 : - _theResult___fst_exp__h802229) : + _theResult___snd_fst_exp__h818060 : + _theResult___fst_exp__h802226) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13601 ? - _theResult___snd_fst_exp__h836498 : - _theResult___fst_exp__h802229) ; - assign _theResult___fst_exp__h836507 = - (f3_exp__h798055 == 8'd0 && f3_sfd__h798056 == 23'd0) ? + _theResult___snd_fst_exp__h836495 : + _theResult___fst_exp__h802226) ; + assign _theResult___fst_exp__h836504 = + (f3_exp__h798052 == 8'd0 && f3_sfd__h798053 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h836504 ; - assign _theResult___fst_sfd__h589514 = - (_theResult___fst_exp__h588916 == 8'd255) ? - sfdin__h588910[56:34] : - _theResult___fst_sfd__h589511 ; - assign _theResult___fst_sfd__h598096 = - (_theResult___fst_exp__h597572 == 8'd255) ? - _theResult___snd__h597523[56:34] : - _theResult___fst_sfd__h598093 ; - assign _theResult___fst_sfd__h607280 = - (_theResult___fst_exp__h606682 == 8'd255) ? - sfdin__h606676[56:34] : - _theResult___fst_sfd__h607277 ; - assign _theResult___fst_sfd__h615916 = - (_theResult___fst_exp__h615367 == 8'd255) ? - _theResult___snd__h615313[56:34] : - _theResult___fst_sfd__h615913 ; - assign _theResult___fst_sfd__h615925 = + _theResult___fst_exp__h836501 ; + assign _theResult___fst_sfd__h589511 = + (_theResult___fst_exp__h588913 == 8'd255) ? + sfdin__h588907[56:34] : + _theResult___fst_sfd__h589508 ; + assign _theResult___fst_sfd__h598093 = + (_theResult___fst_exp__h597569 == 8'd255) ? + _theResult___snd__h597520[56:34] : + _theResult___fst_sfd__h598090 ; + assign _theResult___fst_sfd__h607277 = + (_theResult___fst_exp__h606679 == 8'd255) ? + sfdin__h606673[56:34] : + _theResult___fst_sfd__h607274 ; + assign _theResult___fst_sfd__h615913 = + (_theResult___fst_exp__h615364 == 8'd255) ? + _theResult___snd__h615310[56:34] : + _theResult___fst_sfd__h615910 ; + assign _theResult___fst_sfd__h615922 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8208 ? - _theResult___snd_fst_sfd__h598099 : - _theResult___fst_sfd__h580788) : + _theResult___snd_fst_sfd__h598096 : + _theResult___fst_sfd__h580785) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8748 ? - _theResult___snd_fst_sfd__h615919 : - _theResult___fst_sfd__h580788) ; - assign _theResult___fst_sfd__h615931 = + _theResult___snd_fst_sfd__h615916 : + _theResult___fst_sfd__h580785) ; + assign _theResult___fst_sfd__h615928 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -31162,33 +31162,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h615925 ; - assign _theResult___fst_sfd__h635263 = - (_theResult___fst_exp__h634665 == 8'd255) ? - sfdin__h634659[56:34] : - _theResult___fst_sfd__h635260 ; - assign _theResult___fst_sfd__h643845 = - (_theResult___fst_exp__h643321 == 8'd255) ? - _theResult___snd__h643272[56:34] : - _theResult___fst_sfd__h643842 ; - assign _theResult___fst_sfd__h653029 = - (_theResult___fst_exp__h652431 == 8'd255) ? - sfdin__h652425[56:34] : - _theResult___fst_sfd__h653026 ; - assign _theResult___fst_sfd__h661665 = - (_theResult___fst_exp__h661116 == 8'd255) ? - _theResult___snd__h661062[56:34] : - _theResult___fst_sfd__h661662 ; - assign _theResult___fst_sfd__h661674 = + _theResult___fst_sfd__h615922 ; + assign _theResult___fst_sfd__h635260 = + (_theResult___fst_exp__h634662 == 8'd255) ? + sfdin__h634656[56:34] : + _theResult___fst_sfd__h635257 ; + assign _theResult___fst_sfd__h643842 = + (_theResult___fst_exp__h643318 == 8'd255) ? + _theResult___snd__h643269[56:34] : + _theResult___fst_sfd__h643839 ; + assign _theResult___fst_sfd__h653026 = + (_theResult___fst_exp__h652428 == 8'd255) ? + sfdin__h652422[56:34] : + _theResult___fst_sfd__h653023 ; + assign _theResult___fst_sfd__h661662 = + (_theResult___fst_exp__h661113 == 8'd255) ? + _theResult___snd__h661059[56:34] : + _theResult___fst_sfd__h661659 ; + assign _theResult___fst_sfd__h661671 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9605 ? - _theResult___snd_fst_sfd__h643848 : - _theResult___fst_sfd__h626539) : + _theResult___snd_fst_sfd__h643845 : + _theResult___fst_sfd__h626536) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10145 ? - _theResult___snd_fst_sfd__h661668 : - _theResult___fst_sfd__h626539) ; - assign _theResult___fst_sfd__h661680 = + _theResult___snd_fst_sfd__h661665 : + _theResult___fst_sfd__h626536) ; + assign _theResult___fst_sfd__h661677 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -31196,33 +31196,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h661674 ; - assign _theResult___fst_sfd__h681010 = - (_theResult___fst_exp__h680412 == 8'd255) ? - sfdin__h680406[56:34] : - _theResult___fst_sfd__h681007 ; - assign _theResult___fst_sfd__h689592 = - (_theResult___fst_exp__h689068 == 8'd255) ? - _theResult___snd__h689019[56:34] : - _theResult___fst_sfd__h689589 ; - assign _theResult___fst_sfd__h698776 = - (_theResult___fst_exp__h698178 == 8'd255) ? - sfdin__h698172[56:34] : - _theResult___fst_sfd__h698773 ; - assign _theResult___fst_sfd__h707412 = - (_theResult___fst_exp__h706863 == 8'd255) ? - _theResult___snd__h706809[56:34] : - _theResult___fst_sfd__h707409 ; - assign _theResult___fst_sfd__h707421 = + _theResult___fst_sfd__h661671 ; + assign _theResult___fst_sfd__h681007 = + (_theResult___fst_exp__h680409 == 8'd255) ? + sfdin__h680403[56:34] : + _theResult___fst_sfd__h681004 ; + assign _theResult___fst_sfd__h689589 = + (_theResult___fst_exp__h689065 == 8'd255) ? + _theResult___snd__h689016[56:34] : + _theResult___fst_sfd__h689586 ; + assign _theResult___fst_sfd__h698773 = + (_theResult___fst_exp__h698175 == 8'd255) ? + sfdin__h698169[56:34] : + _theResult___fst_sfd__h698770 ; + assign _theResult___fst_sfd__h707409 = + (_theResult___fst_exp__h706860 == 8'd255) ? + _theResult___snd__h706806[56:34] : + _theResult___fst_sfd__h707406 ; + assign _theResult___fst_sfd__h707418 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11002 ? - _theResult___snd_fst_sfd__h689595 : - _theResult___fst_sfd__h672286) : + _theResult___snd_fst_sfd__h689592 : + _theResult___fst_sfd__h672283) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11542 ? - _theResult___snd_fst_sfd__h707415 : - _theResult___fst_sfd__h672286) ; - assign _theResult___fst_sfd__h707427 = + _theResult___snd_fst_sfd__h707412 : + _theResult___fst_sfd__h672283) ; + assign _theResult___fst_sfd__h707424 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -31230,1431 +31230,1431 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h707421 ; - assign _theResult___fst_sfd__h724073 = + _theResult___fst_sfd__h707418 ; + assign _theResult___fst_sfd__h724070 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 ; - assign _theResult___fst_sfd__h739901 = + assign _theResult___fst_sfd__h739898 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q227 : + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q227 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13358 ; - assign _theResult___fst_sfd__h739904 = - (_theResult___fst_exp__h739145 == 11'd2047) ? - _theResult___snd__h739096[56:5] : - _theResult___fst_sfd__h739901 ; - assign _theResult___fst_sfd__h749552 = + assign _theResult___fst_sfd__h739901 = + (_theResult___fst_exp__h739142 == 11'd2047) ? + _theResult___snd__h739093[56:5] : + _theResult___fst_sfd__h739898 ; + assign _theResult___fst_sfd__h749549 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q229 : + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q229 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13385 ; - assign _theResult___fst_sfd__h749555 = - (_theResult___fst_exp__h748722 == 11'd2047) ? - sfdin__h748716[56:5] : - _theResult___fst_sfd__h749552 ; - assign _theResult___fst_sfd__h758336 = + assign _theResult___fst_sfd__h749552 = + (_theResult___fst_exp__h748719 == 11'd2047) ? + sfdin__h748713[56:5] : + _theResult___fst_sfd__h749549 ; + assign _theResult___fst_sfd__h758333 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q231 : + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q231 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13404 ; - assign _theResult___fst_sfd__h758339 = - (_theResult___fst_exp__h757555 == 11'd2047) ? - _theResult___snd__h757501[56:5] : - _theResult___fst_sfd__h758336 ; - assign _theResult___fst_sfd__h758348 = - (f1_exp__h719757 == 8'd0) ? + assign _theResult___fst_sfd__h758336 = + (_theResult___fst_exp__h757552 == 11'd2047) ? + _theResult___snd__h757498[56:5] : + _theResult___fst_sfd__h758333 ; + assign _theResult___fst_sfd__h758345 = + (f1_exp__h719754 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12749 ? - _theResult___snd_fst_sfd__h739907 : - _theResult___fst_sfd__h724073) : + _theResult___snd_fst_sfd__h739904 : + _theResult___fst_sfd__h724070) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12886 ? - _theResult___snd_fst_sfd__h758342 : - _theResult___fst_sfd__h724073) ; - assign _theResult___fst_sfd__h758354 = - ((f1_exp__h719757 == 8'd255 || f1_exp__h719757 == 8'd0) && - f1_sfd__h719758 == 23'd0) ? + _theResult___snd_fst_sfd__h758339 : + _theResult___fst_sfd__h724070) ; + assign _theResult___fst_sfd__h758351 = + ((f1_exp__h719754 == 8'd255 || f1_exp__h719754 == 8'd0) && + f1_sfd__h719755 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h758348 ; - assign _theResult___fst_sfd__h762926 = + _theResult___fst_sfd__h758345 ; + assign _theResult___fst_sfd__h762923 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 ; - assign _theResult___fst_sfd__h778754 = + assign _theResult___fst_sfd__h778751 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q217 : + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q217 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14838 ; - assign _theResult___fst_sfd__h778757 = - (_theResult___fst_exp__h777998 == 11'd2047) ? - _theResult___snd__h777949[56:5] : - _theResult___fst_sfd__h778754 ; - assign _theResult___fst_sfd__h788405 = + assign _theResult___fst_sfd__h778754 = + (_theResult___fst_exp__h777995 == 11'd2047) ? + _theResult___snd__h777946[56:5] : + _theResult___fst_sfd__h778751 ; + assign _theResult___fst_sfd__h788402 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q219 : + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q219 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14864 ; - assign _theResult___fst_sfd__h788408 = - (_theResult___fst_exp__h787575 == 11'd2047) ? - sfdin__h787569[56:5] : - _theResult___fst_sfd__h788405 ; - assign _theResult___fst_sfd__h797189 = + assign _theResult___fst_sfd__h788405 = + (_theResult___fst_exp__h787572 == 11'd2047) ? + sfdin__h787566[56:5] : + _theResult___fst_sfd__h788402 ; + assign _theResult___fst_sfd__h797186 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q221 : + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q221 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14883 ; - assign _theResult___fst_sfd__h797192 = - (_theResult___fst_exp__h796408 == 11'd2047) ? - _theResult___snd__h796354[56:5] : - _theResult___fst_sfd__h797189 ; - assign _theResult___fst_sfd__h797201 = - (f2_exp__h758751 == 8'd0) ? + assign _theResult___fst_sfd__h797189 = + (_theResult___fst_exp__h796405 == 11'd2047) ? + _theResult___snd__h796351[56:5] : + _theResult___fst_sfd__h797186 ; + assign _theResult___fst_sfd__h797198 = + (f2_exp__h758748 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14249 ? - _theResult___snd_fst_sfd__h778760 : - _theResult___fst_sfd__h762926) : + _theResult___snd_fst_sfd__h778757 : + _theResult___fst_sfd__h762923) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14371 ? - _theResult___snd_fst_sfd__h797195 : - _theResult___fst_sfd__h762926) ; - assign _theResult___fst_sfd__h797207 = - ((f2_exp__h758751 == 8'd255 || f2_exp__h758751 == 8'd0) && - f2_sfd__h758752 == 23'd0) ? + _theResult___snd_fst_sfd__h797192 : + _theResult___fst_sfd__h762923) ; + assign _theResult___fst_sfd__h797204 = + ((f2_exp__h758748 == 8'd255 || f2_exp__h758748 == 8'd0) && + f2_sfd__h758749 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h797201 ; - assign _theResult___fst_sfd__h802230 = + _theResult___fst_sfd__h797198 ; + assign _theResult___fst_sfd__h802227 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32 ; - assign _theResult___fst_sfd__h818058 = + assign _theResult___fst_sfd__h818055 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q233 : + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q233 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14068 ; - assign _theResult___fst_sfd__h818061 = - (_theResult___fst_exp__h817302 == 11'd2047) ? - _theResult___snd__h817253[56:5] : - _theResult___fst_sfd__h818058 ; - assign _theResult___fst_sfd__h827709 = + assign _theResult___fst_sfd__h818058 = + (_theResult___fst_exp__h817299 == 11'd2047) ? + _theResult___snd__h817250[56:5] : + _theResult___fst_sfd__h818055 ; + assign _theResult___fst_sfd__h827706 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q235 : + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q235 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14094 ; - assign _theResult___fst_sfd__h827712 = - (_theResult___fst_exp__h826879 == 11'd2047) ? - sfdin__h826873[56:5] : - _theResult___fst_sfd__h827709 ; - assign _theResult___fst_sfd__h836493 = + assign _theResult___fst_sfd__h827709 = + (_theResult___fst_exp__h826876 == 11'd2047) ? + sfdin__h826870[56:5] : + _theResult___fst_sfd__h827706 ; + assign _theResult___fst_sfd__h836490 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q237 : + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q237 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14113 ; - assign _theResult___fst_sfd__h836496 = - (_theResult___fst_exp__h835712 == 11'd2047) ? - _theResult___snd__h835658[56:5] : - _theResult___fst_sfd__h836493 ; - assign _theResult___fst_sfd__h836505 = - (f3_exp__h798055 == 8'd0) ? + assign _theResult___fst_sfd__h836493 = + (_theResult___fst_exp__h835709 == 11'd2047) ? + _theResult___snd__h835655[56:5] : + _theResult___fst_sfd__h836490 ; + assign _theResult___fst_sfd__h836502 = + (f3_exp__h798052 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13479 ? - _theResult___snd_fst_sfd__h818064 : - _theResult___fst_sfd__h802230) : + _theResult___snd_fst_sfd__h818061 : + _theResult___fst_sfd__h802227) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13601 ? - _theResult___snd_fst_sfd__h836499 : - _theResult___fst_sfd__h802230) ; - assign _theResult___fst_sfd__h836511 = - ((f3_exp__h798055 == 8'd255 || f3_exp__h798055 == 8'd0) && - f3_sfd__h798056 == 23'd0) ? + _theResult___snd_fst_sfd__h836496 : + _theResult___fst_sfd__h802227) ; + assign _theResult___fst_sfd__h836508 = + ((f3_exp__h798052 == 8'd255 || f3_exp__h798052 == 8'd0) && + f3_sfd__h798053 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h836505 ; - assign _theResult___sfd__h589433 = - sfd__h589008[24] ? - ((_theResult___fst_exp__h588916 == 8'd254) ? + _theResult___fst_sfd__h836502 ; + assign _theResult___sfd__h589430 = + sfd__h589005[24] ? + ((_theResult___fst_exp__h588913 == 8'd254) ? 23'd0 : - sfd__h589008[23:1]) : - sfd__h589008[22:0] ; - assign _theResult___sfd__h598015 = - sfd__h597590[24] ? - ((_theResult___fst_exp__h597572 == 8'd254) ? + sfd__h589005[23:1]) : + sfd__h589005[22:0] ; + assign _theResult___sfd__h598012 = + sfd__h597587[24] ? + ((_theResult___fst_exp__h597569 == 8'd254) ? 23'd0 : - sfd__h597590[23:1]) : - sfd__h597590[22:0] ; - assign _theResult___sfd__h607199 = - sfd__h606774[24] ? - ((_theResult___fst_exp__h606682 == 8'd254) ? + sfd__h597587[23:1]) : + sfd__h597587[22:0] ; + assign _theResult___sfd__h607196 = + sfd__h606771[24] ? + ((_theResult___fst_exp__h606679 == 8'd254) ? 23'd0 : - sfd__h606774[23:1]) : - sfd__h606774[22:0] ; - assign _theResult___sfd__h615835 = - sfd__h615386[24] ? - ((_theResult___fst_exp__h615367 == 8'd254) ? + sfd__h606771[23:1]) : + sfd__h606771[22:0] ; + assign _theResult___sfd__h615832 = + sfd__h615383[24] ? + ((_theResult___fst_exp__h615364 == 8'd254) ? 23'd0 : - sfd__h615386[23:1]) : - sfd__h615386[22:0] ; - assign _theResult___sfd__h615937 = + sfd__h615383[23:1]) : + sfd__h615383[22:0] ; + assign _theResult___sfd__h615934 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h573150 : - _theResult___fst_sfd__h615931 ; - assign _theResult___sfd__h635182 = - sfd__h634757[24] ? - ((_theResult___fst_exp__h634665 == 8'd254) ? + _theResult___snd_fst_sfd__h573147 : + _theResult___fst_sfd__h615928 ; + assign _theResult___sfd__h635179 = + sfd__h634754[24] ? + ((_theResult___fst_exp__h634662 == 8'd254) ? 23'd0 : - sfd__h634757[23:1]) : - sfd__h634757[22:0] ; - assign _theResult___sfd__h643764 = - sfd__h643339[24] ? - ((_theResult___fst_exp__h643321 == 8'd254) ? + sfd__h634754[23:1]) : + sfd__h634754[22:0] ; + assign _theResult___sfd__h643761 = + sfd__h643336[24] ? + ((_theResult___fst_exp__h643318 == 8'd254) ? 23'd0 : - sfd__h643339[23:1]) : - sfd__h643339[22:0] ; - assign _theResult___sfd__h652948 = - sfd__h652523[24] ? - ((_theResult___fst_exp__h652431 == 8'd254) ? + sfd__h643336[23:1]) : + sfd__h643336[22:0] ; + assign _theResult___sfd__h652945 = + sfd__h652520[24] ? + ((_theResult___fst_exp__h652428 == 8'd254) ? 23'd0 : - sfd__h652523[23:1]) : - sfd__h652523[22:0] ; - assign _theResult___sfd__h661584 = - sfd__h661135[24] ? - ((_theResult___fst_exp__h661116 == 8'd254) ? + sfd__h652520[23:1]) : + sfd__h652520[22:0] ; + assign _theResult___sfd__h661581 = + sfd__h661132[24] ? + ((_theResult___fst_exp__h661113 == 8'd254) ? 23'd0 : - sfd__h661135[23:1]) : - sfd__h661135[22:0] ; - assign _theResult___sfd__h661686 = + sfd__h661132[23:1]) : + sfd__h661132[22:0] ; + assign _theResult___sfd__h661683 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h618904 : - _theResult___fst_sfd__h661680 ; - assign _theResult___sfd__h680929 = - sfd__h680504[24] ? - ((_theResult___fst_exp__h680412 == 8'd254) ? + _theResult___snd_fst_sfd__h618901 : + _theResult___fst_sfd__h661677 ; + assign _theResult___sfd__h680926 = + sfd__h680501[24] ? + ((_theResult___fst_exp__h680409 == 8'd254) ? 23'd0 : - sfd__h680504[23:1]) : - sfd__h680504[22:0] ; - assign _theResult___sfd__h689511 = - sfd__h689086[24] ? - ((_theResult___fst_exp__h689068 == 8'd254) ? + sfd__h680501[23:1]) : + sfd__h680501[22:0] ; + assign _theResult___sfd__h689508 = + sfd__h689083[24] ? + ((_theResult___fst_exp__h689065 == 8'd254) ? 23'd0 : - sfd__h689086[23:1]) : - sfd__h689086[22:0] ; - assign _theResult___sfd__h698695 = - sfd__h698270[24] ? - ((_theResult___fst_exp__h698178 == 8'd254) ? + sfd__h689083[23:1]) : + sfd__h689083[22:0] ; + assign _theResult___sfd__h698692 = + sfd__h698267[24] ? + ((_theResult___fst_exp__h698175 == 8'd254) ? 23'd0 : - sfd__h698270[23:1]) : - sfd__h698270[22:0] ; - assign _theResult___sfd__h707331 = - sfd__h706882[24] ? - ((_theResult___fst_exp__h706863 == 8'd254) ? + sfd__h698267[23:1]) : + sfd__h698267[22:0] ; + assign _theResult___sfd__h707328 = + sfd__h706879[24] ? + ((_theResult___fst_exp__h706860 == 8'd254) ? 23'd0 : - sfd__h706882[23:1]) : - sfd__h706882[22:0] ; - assign _theResult___sfd__h707433 = + sfd__h706879[23:1]) : + sfd__h706879[22:0] ; + assign _theResult___sfd__h707430 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h664651 : - _theResult___fst_sfd__h707427 ; - assign _theResult___sfd__h739801 = - sfd__h739163[53] ? - ((_theResult___fst_exp__h739145 == 11'd2046) ? + _theResult___snd_fst_sfd__h664648 : + _theResult___fst_sfd__h707424 ; + assign _theResult___sfd__h739798 = + sfd__h739160[53] ? + ((_theResult___fst_exp__h739142 == 11'd2046) ? 52'd0 : - sfd__h739163[52:1]) : - sfd__h739163[51:0] ; - assign _theResult___sfd__h749452 = - sfd__h748814[53] ? - ((_theResult___fst_exp__h748722 == 11'd2046) ? + sfd__h739160[52:1]) : + sfd__h739160[51:0] ; + assign _theResult___sfd__h749449 = + sfd__h748811[53] ? + ((_theResult___fst_exp__h748719 == 11'd2046) ? 52'd0 : - sfd__h748814[52:1]) : - sfd__h748814[51:0] ; - assign _theResult___sfd__h758236 = - sfd__h757574[53] ? - ((_theResult___fst_exp__h757555 == 11'd2046) ? + sfd__h748811[52:1]) : + sfd__h748811[51:0] ; + assign _theResult___sfd__h758233 = + sfd__h757571[53] ? + ((_theResult___fst_exp__h757552 == 11'd2046) ? 52'd0 : - sfd__h757574[52:1]) : - sfd__h757574[51:0] ; - assign _theResult___sfd__h778654 = - sfd__h778016[53] ? - ((_theResult___fst_exp__h777998 == 11'd2046) ? + sfd__h757571[52:1]) : + sfd__h757571[51:0] ; + assign _theResult___sfd__h778651 = + sfd__h778013[53] ? + ((_theResult___fst_exp__h777995 == 11'd2046) ? 52'd0 : - sfd__h778016[52:1]) : - sfd__h778016[51:0] ; - assign _theResult___sfd__h788305 = - sfd__h787667[53] ? - ((_theResult___fst_exp__h787575 == 11'd2046) ? + sfd__h778013[52:1]) : + sfd__h778013[51:0] ; + assign _theResult___sfd__h788302 = + sfd__h787664[53] ? + ((_theResult___fst_exp__h787572 == 11'd2046) ? 52'd0 : - sfd__h787667[52:1]) : - sfd__h787667[51:0] ; - assign _theResult___sfd__h797089 = - sfd__h796427[53] ? - ((_theResult___fst_exp__h796408 == 11'd2046) ? + sfd__h787664[52:1]) : + sfd__h787664[51:0] ; + assign _theResult___sfd__h797086 = + sfd__h796424[53] ? + ((_theResult___fst_exp__h796405 == 11'd2046) ? 52'd0 : - sfd__h796427[52:1]) : - sfd__h796427[51:0] ; - assign _theResult___sfd__h817958 = - sfd__h817320[53] ? - ((_theResult___fst_exp__h817302 == 11'd2046) ? + sfd__h796424[52:1]) : + sfd__h796424[51:0] ; + assign _theResult___sfd__h817955 = + sfd__h817317[53] ? + ((_theResult___fst_exp__h817299 == 11'd2046) ? 52'd0 : - sfd__h817320[52:1]) : - sfd__h817320[51:0] ; - assign _theResult___sfd__h827609 = - sfd__h826971[53] ? - ((_theResult___fst_exp__h826879 == 11'd2046) ? + sfd__h817317[52:1]) : + sfd__h817317[51:0] ; + assign _theResult___sfd__h827606 = + sfd__h826968[53] ? + ((_theResult___fst_exp__h826876 == 11'd2046) ? 52'd0 : - sfd__h826971[52:1]) : - sfd__h826971[51:0] ; - assign _theResult___sfd__h836393 = - sfd__h835731[53] ? - ((_theResult___fst_exp__h835712 == 11'd2046) ? + sfd__h826968[52:1]) : + sfd__h826968[51:0] ; + assign _theResult___sfd__h836390 = + sfd__h835728[53] ? + ((_theResult___fst_exp__h835709 == 11'd2046) ? 52'd0 : - sfd__h835731[52:1]) : - sfd__h835731[51:0] ; - assign _theResult___snd__h588927 = { _theResult____h580805[55:0], 1'd0 } ; - assign _theResult___snd__h588938 = - (!_theResult____h580805[56] && _theResult____h580805[55]) ? - _theResult___snd__h588940 : - _theResult___snd__h588950 ; - assign _theResult___snd__h588940 = { _theResult____h580805[54:0], 2'd0 } ; - assign _theResult___snd__h588950 = - (!_theResult____h580805[56] && !_theResult____h580805[55] && - !_theResult____h580805[54] && - !_theResult____h580805[53] && - !_theResult____h580805[52] && - !_theResult____h580805[51] && - !_theResult____h580805[50] && - !_theResult____h580805[49] && - !_theResult____h580805[48] && - !_theResult____h580805[47] && - !_theResult____h580805[46] && - !_theResult____h580805[45] && - !_theResult____h580805[44] && - !_theResult____h580805[43] && - !_theResult____h580805[42] && - !_theResult____h580805[41] && - !_theResult____h580805[40] && - !_theResult____h580805[39] && - !_theResult____h580805[38] && - !_theResult____h580805[37] && - !_theResult____h580805[36] && - !_theResult____h580805[35] && - !_theResult____h580805[34] && - !_theResult____h580805[33] && - !_theResult____h580805[32] && - !_theResult____h580805[31] && - !_theResult____h580805[30] && - !_theResult____h580805[29] && - !_theResult____h580805[28] && - !_theResult____h580805[27] && - !_theResult____h580805[26] && - !_theResult____h580805[25] && - !_theResult____h580805[24] && - !_theResult____h580805[23] && - !_theResult____h580805[22] && - !_theResult____h580805[21] && - !_theResult____h580805[20] && - !_theResult____h580805[19] && - !_theResult____h580805[18] && - !_theResult____h580805[17] && - !_theResult____h580805[16] && - !_theResult____h580805[15] && - !_theResult____h580805[14] && - !_theResult____h580805[13] && - !_theResult____h580805[12] && - !_theResult____h580805[11] && - !_theResult____h580805[10] && - !_theResult____h580805[9] && - !_theResult____h580805[8] && - !_theResult____h580805[7] && - !_theResult____h580805[6] && - !_theResult____h580805[5] && - !_theResult____h580805[4] && - !_theResult____h580805[3] && - !_theResult____h580805[2] && - !_theResult____h580805[1] && - !_theResult____h580805[0]) ? - _theResult____h580805 : - _theResult___snd__h588956 ; - assign _theResult___snd__h588956 = + sfd__h835728[52:1]) : + sfd__h835728[51:0] ; + assign _theResult___snd__h588924 = { _theResult____h580802[55:0], 1'd0 } ; + assign _theResult___snd__h588935 = + (!_theResult____h580802[56] && _theResult____h580802[55]) ? + _theResult___snd__h588937 : + _theResult___snd__h588947 ; + assign _theResult___snd__h588937 = { _theResult____h580802[54:0], 2'd0 } ; + assign _theResult___snd__h588947 = + (!_theResult____h580802[56] && !_theResult____h580802[55] && + !_theResult____h580802[54] && + !_theResult____h580802[53] && + !_theResult____h580802[52] && + !_theResult____h580802[51] && + !_theResult____h580802[50] && + !_theResult____h580802[49] && + !_theResult____h580802[48] && + !_theResult____h580802[47] && + !_theResult____h580802[46] && + !_theResult____h580802[45] && + !_theResult____h580802[44] && + !_theResult____h580802[43] && + !_theResult____h580802[42] && + !_theResult____h580802[41] && + !_theResult____h580802[40] && + !_theResult____h580802[39] && + !_theResult____h580802[38] && + !_theResult____h580802[37] && + !_theResult____h580802[36] && + !_theResult____h580802[35] && + !_theResult____h580802[34] && + !_theResult____h580802[33] && + !_theResult____h580802[32] && + !_theResult____h580802[31] && + !_theResult____h580802[30] && + !_theResult____h580802[29] && + !_theResult____h580802[28] && + !_theResult____h580802[27] && + !_theResult____h580802[26] && + !_theResult____h580802[25] && + !_theResult____h580802[24] && + !_theResult____h580802[23] && + !_theResult____h580802[22] && + !_theResult____h580802[21] && + !_theResult____h580802[20] && + !_theResult____h580802[19] && + !_theResult____h580802[18] && + !_theResult____h580802[17] && + !_theResult____h580802[16] && + !_theResult____h580802[15] && + !_theResult____h580802[14] && + !_theResult____h580802[13] && + !_theResult____h580802[12] && + !_theResult____h580802[11] && + !_theResult____h580802[10] && + !_theResult____h580802[9] && + !_theResult____h580802[8] && + !_theResult____h580802[7] && + !_theResult____h580802[6] && + !_theResult____h580802[5] && + !_theResult____h580802[4] && + !_theResult____h580802[3] && + !_theResult____h580802[2] && + !_theResult____h580802[1] && + !_theResult____h580802[0]) ? + _theResult____h580802 : + _theResult___snd__h588953 ; + assign _theResult___snd__h588953 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40[54:0], 2'd0 } ; - assign _theResult___snd__h588979 = - _theResult____h580805 << + assign _theResult___snd__h588976 = + _theResult____h580802 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8443 ; - assign _theResult___snd__h597523 = + assign _theResult___snd__h597520 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h597532 : - _theResult___snd__h597525 ; - assign _theResult___snd__h597525 = + _theResult___snd__h597529 : + _theResult___snd__h597522 ; + assign _theResult___snd__h597522 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h597532 = + assign _theResult___snd__h597529 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8619) ? - sfd__h573200 : - _theResult___snd__h597538 ; - assign _theResult___snd__h597538 = + sfd__h573197 : + _theResult___snd__h597535 ; + assign _theResult___snd__h597535 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q42[54:0], 2'd0 } ; - assign _theResult___snd__h597561 = - sfd__h573200 << + assign _theResult___snd__h597558 = + sfd__h573197 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8674 ; - assign _theResult___snd__h606693 = { _theResult____h598444[55:0], 1'd0 } ; - assign _theResult___snd__h606704 = - (!_theResult____h598444[56] && _theResult____h598444[55]) ? - _theResult___snd__h606706 : - _theResult___snd__h606716 ; - assign _theResult___snd__h606706 = { _theResult____h598444[54:0], 2'd0 } ; - assign _theResult___snd__h606716 = - (!_theResult____h598444[56] && !_theResult____h598444[55] && - !_theResult____h598444[54] && - !_theResult____h598444[53] && - !_theResult____h598444[52] && - !_theResult____h598444[51] && - !_theResult____h598444[50] && - !_theResult____h598444[49] && - !_theResult____h598444[48] && - !_theResult____h598444[47] && - !_theResult____h598444[46] && - !_theResult____h598444[45] && - !_theResult____h598444[44] && - !_theResult____h598444[43] && - !_theResult____h598444[42] && - !_theResult____h598444[41] && - !_theResult____h598444[40] && - !_theResult____h598444[39] && - !_theResult____h598444[38] && - !_theResult____h598444[37] && - !_theResult____h598444[36] && - !_theResult____h598444[35] && - !_theResult____h598444[34] && - !_theResult____h598444[33] && - !_theResult____h598444[32] && - !_theResult____h598444[31] && - !_theResult____h598444[30] && - !_theResult____h598444[29] && - !_theResult____h598444[28] && - !_theResult____h598444[27] && - !_theResult____h598444[26] && - !_theResult____h598444[25] && - !_theResult____h598444[24] && - !_theResult____h598444[23] && - !_theResult____h598444[22] && - !_theResult____h598444[21] && - !_theResult____h598444[20] && - !_theResult____h598444[19] && - !_theResult____h598444[18] && - !_theResult____h598444[17] && - !_theResult____h598444[16] && - !_theResult____h598444[15] && - !_theResult____h598444[14] && - !_theResult____h598444[13] && - !_theResult____h598444[12] && - !_theResult____h598444[11] && - !_theResult____h598444[10] && - !_theResult____h598444[9] && - !_theResult____h598444[8] && - !_theResult____h598444[7] && - !_theResult____h598444[6] && - !_theResult____h598444[5] && - !_theResult____h598444[4] && - !_theResult____h598444[3] && - !_theResult____h598444[2] && - !_theResult____h598444[1] && - !_theResult____h598444[0]) ? - _theResult____h598444 : - _theResult___snd__h606722 ; - assign _theResult___snd__h606722 = + assign _theResult___snd__h606690 = { _theResult____h598441[55:0], 1'd0 } ; + assign _theResult___snd__h606701 = + (!_theResult____h598441[56] && _theResult____h598441[55]) ? + _theResult___snd__h606703 : + _theResult___snd__h606713 ; + assign _theResult___snd__h606703 = { _theResult____h598441[54:0], 2'd0 } ; + assign _theResult___snd__h606713 = + (!_theResult____h598441[56] && !_theResult____h598441[55] && + !_theResult____h598441[54] && + !_theResult____h598441[53] && + !_theResult____h598441[52] && + !_theResult____h598441[51] && + !_theResult____h598441[50] && + !_theResult____h598441[49] && + !_theResult____h598441[48] && + !_theResult____h598441[47] && + !_theResult____h598441[46] && + !_theResult____h598441[45] && + !_theResult____h598441[44] && + !_theResult____h598441[43] && + !_theResult____h598441[42] && + !_theResult____h598441[41] && + !_theResult____h598441[40] && + !_theResult____h598441[39] && + !_theResult____h598441[38] && + !_theResult____h598441[37] && + !_theResult____h598441[36] && + !_theResult____h598441[35] && + !_theResult____h598441[34] && + !_theResult____h598441[33] && + !_theResult____h598441[32] && + !_theResult____h598441[31] && + !_theResult____h598441[30] && + !_theResult____h598441[29] && + !_theResult____h598441[28] && + !_theResult____h598441[27] && + !_theResult____h598441[26] && + !_theResult____h598441[25] && + !_theResult____h598441[24] && + !_theResult____h598441[23] && + !_theResult____h598441[22] && + !_theResult____h598441[21] && + !_theResult____h598441[20] && + !_theResult____h598441[19] && + !_theResult____h598441[18] && + !_theResult____h598441[17] && + !_theResult____h598441[16] && + !_theResult____h598441[15] && + !_theResult____h598441[14] && + !_theResult____h598441[13] && + !_theResult____h598441[12] && + !_theResult____h598441[11] && + !_theResult____h598441[10] && + !_theResult____h598441[9] && + !_theResult____h598441[8] && + !_theResult____h598441[7] && + !_theResult____h598441[6] && + !_theResult____h598441[5] && + !_theResult____h598441[4] && + !_theResult____h598441[3] && + !_theResult____h598441[2] && + !_theResult____h598441[1] && + !_theResult____h598441[0]) ? + _theResult____h598441 : + _theResult___snd__h606719 ; + assign _theResult___snd__h606719 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q50[54:0], 2'd0 } ; - assign _theResult___snd__h606745 = - _theResult____h598444 << + assign _theResult___snd__h606742 = + _theResult____h598441 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8994 ; - assign _theResult___snd__h615313 = + assign _theResult___snd__h615310 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h615327 : - _theResult___snd__h597525 ; - assign _theResult___snd__h615327 = + _theResult___snd__h615324 : + _theResult___snd__h597522 ; + assign _theResult___snd__h615324 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8619) ? - sfd__h573200 : - _theResult___snd__h615333 ; - assign _theResult___snd__h615333 = + sfd__h573197 : + _theResult___snd__h615330 ; + assign _theResult___snd__h615330 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q55[54:0], 2'd0 } ; - assign _theResult___snd__h615351 = - sfd__h573200 << + assign _theResult___snd__h615348 = + sfd__h573197 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9068[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9068) ; - assign _theResult___snd__h634676 = { _theResult____h626556[55:0], 1'd0 } ; - assign _theResult___snd__h634687 = - (!_theResult____h626556[56] && _theResult____h626556[55]) ? - _theResult___snd__h634689 : - _theResult___snd__h634699 ; - assign _theResult___snd__h634689 = { _theResult____h626556[54:0], 2'd0 } ; - assign _theResult___snd__h634699 = - (!_theResult____h626556[56] && !_theResult____h626556[55] && - !_theResult____h626556[54] && - !_theResult____h626556[53] && - !_theResult____h626556[52] && - !_theResult____h626556[51] && - !_theResult____h626556[50] && - !_theResult____h626556[49] && - !_theResult____h626556[48] && - !_theResult____h626556[47] && - !_theResult____h626556[46] && - !_theResult____h626556[45] && - !_theResult____h626556[44] && - !_theResult____h626556[43] && - !_theResult____h626556[42] && - !_theResult____h626556[41] && - !_theResult____h626556[40] && - !_theResult____h626556[39] && - !_theResult____h626556[38] && - !_theResult____h626556[37] && - !_theResult____h626556[36] && - !_theResult____h626556[35] && - !_theResult____h626556[34] && - !_theResult____h626556[33] && - !_theResult____h626556[32] && - !_theResult____h626556[31] && - !_theResult____h626556[30] && - !_theResult____h626556[29] && - !_theResult____h626556[28] && - !_theResult____h626556[27] && - !_theResult____h626556[26] && - !_theResult____h626556[25] && - !_theResult____h626556[24] && - !_theResult____h626556[23] && - !_theResult____h626556[22] && - !_theResult____h626556[21] && - !_theResult____h626556[20] && - !_theResult____h626556[19] && - !_theResult____h626556[18] && - !_theResult____h626556[17] && - !_theResult____h626556[16] && - !_theResult____h626556[15] && - !_theResult____h626556[14] && - !_theResult____h626556[13] && - !_theResult____h626556[12] && - !_theResult____h626556[11] && - !_theResult____h626556[10] && - !_theResult____h626556[9] && - !_theResult____h626556[8] && - !_theResult____h626556[7] && - !_theResult____h626556[6] && - !_theResult____h626556[5] && - !_theResult____h626556[4] && - !_theResult____h626556[3] && - !_theResult____h626556[2] && - !_theResult____h626556[1] && - !_theResult____h626556[0]) ? - _theResult____h626556 : - _theResult___snd__h634705 ; - assign _theResult___snd__h634705 = + assign _theResult___snd__h634673 = { _theResult____h626553[55:0], 1'd0 } ; + assign _theResult___snd__h634684 = + (!_theResult____h626553[56] && _theResult____h626553[55]) ? + _theResult___snd__h634686 : + _theResult___snd__h634696 ; + assign _theResult___snd__h634686 = { _theResult____h626553[54:0], 2'd0 } ; + assign _theResult___snd__h634696 = + (!_theResult____h626553[56] && !_theResult____h626553[55] && + !_theResult____h626553[54] && + !_theResult____h626553[53] && + !_theResult____h626553[52] && + !_theResult____h626553[51] && + !_theResult____h626553[50] && + !_theResult____h626553[49] && + !_theResult____h626553[48] && + !_theResult____h626553[47] && + !_theResult____h626553[46] && + !_theResult____h626553[45] && + !_theResult____h626553[44] && + !_theResult____h626553[43] && + !_theResult____h626553[42] && + !_theResult____h626553[41] && + !_theResult____h626553[40] && + !_theResult____h626553[39] && + !_theResult____h626553[38] && + !_theResult____h626553[37] && + !_theResult____h626553[36] && + !_theResult____h626553[35] && + !_theResult____h626553[34] && + !_theResult____h626553[33] && + !_theResult____h626553[32] && + !_theResult____h626553[31] && + !_theResult____h626553[30] && + !_theResult____h626553[29] && + !_theResult____h626553[28] && + !_theResult____h626553[27] && + !_theResult____h626553[26] && + !_theResult____h626553[25] && + !_theResult____h626553[24] && + !_theResult____h626553[23] && + !_theResult____h626553[22] && + !_theResult____h626553[21] && + !_theResult____h626553[20] && + !_theResult____h626553[19] && + !_theResult____h626553[18] && + !_theResult____h626553[17] && + !_theResult____h626553[16] && + !_theResult____h626553[15] && + !_theResult____h626553[14] && + !_theResult____h626553[13] && + !_theResult____h626553[12] && + !_theResult____h626553[11] && + !_theResult____h626553[10] && + !_theResult____h626553[9] && + !_theResult____h626553[8] && + !_theResult____h626553[7] && + !_theResult____h626553[6] && + !_theResult____h626553[5] && + !_theResult____h626553[4] && + !_theResult____h626553[3] && + !_theResult____h626553[2] && + !_theResult____h626553[1] && + !_theResult____h626553[0]) ? + _theResult____h626553 : + _theResult___snd__h634702 ; + assign _theResult___snd__h634702 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75[54:0], 2'd0 } ; - assign _theResult___snd__h634728 = - _theResult____h626556 << + assign _theResult___snd__h634725 = + _theResult____h626553 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9840 ; - assign _theResult___snd__h643272 = + assign _theResult___snd__h643269 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h643281 : - _theResult___snd__h643274 ; - assign _theResult___snd__h643274 = + _theResult___snd__h643278 : + _theResult___snd__h643271 ; + assign _theResult___snd__h643271 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h643281 = + assign _theResult___snd__h643278 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10016) ? - sfd__h618954 : - _theResult___snd__h643287 ; - assign _theResult___snd__h643287 = + sfd__h618951 : + _theResult___snd__h643284 ; + assign _theResult___snd__h643284 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q77[54:0], 2'd0 } ; - assign _theResult___snd__h643310 = - sfd__h618954 << + assign _theResult___snd__h643307 = + sfd__h618951 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10071 ; - assign _theResult___snd__h652442 = { _theResult____h644193[55:0], 1'd0 } ; - assign _theResult___snd__h652453 = - (!_theResult____h644193[56] && _theResult____h644193[55]) ? - _theResult___snd__h652455 : - _theResult___snd__h652465 ; - assign _theResult___snd__h652455 = { _theResult____h644193[54:0], 2'd0 } ; - assign _theResult___snd__h652465 = - (!_theResult____h644193[56] && !_theResult____h644193[55] && - !_theResult____h644193[54] && - !_theResult____h644193[53] && - !_theResult____h644193[52] && - !_theResult____h644193[51] && - !_theResult____h644193[50] && - !_theResult____h644193[49] && - !_theResult____h644193[48] && - !_theResult____h644193[47] && - !_theResult____h644193[46] && - !_theResult____h644193[45] && - !_theResult____h644193[44] && - !_theResult____h644193[43] && - !_theResult____h644193[42] && - !_theResult____h644193[41] && - !_theResult____h644193[40] && - !_theResult____h644193[39] && - !_theResult____h644193[38] && - !_theResult____h644193[37] && - !_theResult____h644193[36] && - !_theResult____h644193[35] && - !_theResult____h644193[34] && - !_theResult____h644193[33] && - !_theResult____h644193[32] && - !_theResult____h644193[31] && - !_theResult____h644193[30] && - !_theResult____h644193[29] && - !_theResult____h644193[28] && - !_theResult____h644193[27] && - !_theResult____h644193[26] && - !_theResult____h644193[25] && - !_theResult____h644193[24] && - !_theResult____h644193[23] && - !_theResult____h644193[22] && - !_theResult____h644193[21] && - !_theResult____h644193[20] && - !_theResult____h644193[19] && - !_theResult____h644193[18] && - !_theResult____h644193[17] && - !_theResult____h644193[16] && - !_theResult____h644193[15] && - !_theResult____h644193[14] && - !_theResult____h644193[13] && - !_theResult____h644193[12] && - !_theResult____h644193[11] && - !_theResult____h644193[10] && - !_theResult____h644193[9] && - !_theResult____h644193[8] && - !_theResult____h644193[7] && - !_theResult____h644193[6] && - !_theResult____h644193[5] && - !_theResult____h644193[4] && - !_theResult____h644193[3] && - !_theResult____h644193[2] && - !_theResult____h644193[1] && - !_theResult____h644193[0]) ? - _theResult____h644193 : - _theResult___snd__h652471 ; - assign _theResult___snd__h652471 = + assign _theResult___snd__h652439 = { _theResult____h644190[55:0], 1'd0 } ; + assign _theResult___snd__h652450 = + (!_theResult____h644190[56] && _theResult____h644190[55]) ? + _theResult___snd__h652452 : + _theResult___snd__h652462 ; + assign _theResult___snd__h652452 = { _theResult____h644190[54:0], 2'd0 } ; + assign _theResult___snd__h652462 = + (!_theResult____h644190[56] && !_theResult____h644190[55] && + !_theResult____h644190[54] && + !_theResult____h644190[53] && + !_theResult____h644190[52] && + !_theResult____h644190[51] && + !_theResult____h644190[50] && + !_theResult____h644190[49] && + !_theResult____h644190[48] && + !_theResult____h644190[47] && + !_theResult____h644190[46] && + !_theResult____h644190[45] && + !_theResult____h644190[44] && + !_theResult____h644190[43] && + !_theResult____h644190[42] && + !_theResult____h644190[41] && + !_theResult____h644190[40] && + !_theResult____h644190[39] && + !_theResult____h644190[38] && + !_theResult____h644190[37] && + !_theResult____h644190[36] && + !_theResult____h644190[35] && + !_theResult____h644190[34] && + !_theResult____h644190[33] && + !_theResult____h644190[32] && + !_theResult____h644190[31] && + !_theResult____h644190[30] && + !_theResult____h644190[29] && + !_theResult____h644190[28] && + !_theResult____h644190[27] && + !_theResult____h644190[26] && + !_theResult____h644190[25] && + !_theResult____h644190[24] && + !_theResult____h644190[23] && + !_theResult____h644190[22] && + !_theResult____h644190[21] && + !_theResult____h644190[20] && + !_theResult____h644190[19] && + !_theResult____h644190[18] && + !_theResult____h644190[17] && + !_theResult____h644190[16] && + !_theResult____h644190[15] && + !_theResult____h644190[14] && + !_theResult____h644190[13] && + !_theResult____h644190[12] && + !_theResult____h644190[11] && + !_theResult____h644190[10] && + !_theResult____h644190[9] && + !_theResult____h644190[8] && + !_theResult____h644190[7] && + !_theResult____h644190[6] && + !_theResult____h644190[5] && + !_theResult____h644190[4] && + !_theResult____h644190[3] && + !_theResult____h644190[2] && + !_theResult____h644190[1] && + !_theResult____h644190[0]) ? + _theResult____h644190 : + _theResult___snd__h652468 ; + assign _theResult___snd__h652468 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q85[54:0], 2'd0 } ; - assign _theResult___snd__h652494 = - _theResult____h644193 << + assign _theResult___snd__h652491 = + _theResult____h644190 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10391 ; - assign _theResult___snd__h661062 = + assign _theResult___snd__h661059 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h661076 : - _theResult___snd__h643274 ; - assign _theResult___snd__h661076 = + _theResult___snd__h661073 : + _theResult___snd__h643271 ; + assign _theResult___snd__h661073 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10016) ? - sfd__h618954 : - _theResult___snd__h661082 ; - assign _theResult___snd__h661082 = + sfd__h618951 : + _theResult___snd__h661079 ; + assign _theResult___snd__h661079 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q90[54:0], 2'd0 } ; - assign _theResult___snd__h661100 = - sfd__h618954 << + assign _theResult___snd__h661097 = + sfd__h618951 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10465[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10465) ; - assign _theResult___snd__h680423 = { _theResult____h672303[55:0], 1'd0 } ; - assign _theResult___snd__h680434 = - (!_theResult____h672303[56] && _theResult____h672303[55]) ? - _theResult___snd__h680436 : - _theResult___snd__h680446 ; - assign _theResult___snd__h680436 = { _theResult____h672303[54:0], 2'd0 } ; - assign _theResult___snd__h680446 = - (!_theResult____h672303[56] && !_theResult____h672303[55] && - !_theResult____h672303[54] && - !_theResult____h672303[53] && - !_theResult____h672303[52] && - !_theResult____h672303[51] && - !_theResult____h672303[50] && - !_theResult____h672303[49] && - !_theResult____h672303[48] && - !_theResult____h672303[47] && - !_theResult____h672303[46] && - !_theResult____h672303[45] && - !_theResult____h672303[44] && - !_theResult____h672303[43] && - !_theResult____h672303[42] && - !_theResult____h672303[41] && - !_theResult____h672303[40] && - !_theResult____h672303[39] && - !_theResult____h672303[38] && - !_theResult____h672303[37] && - !_theResult____h672303[36] && - !_theResult____h672303[35] && - !_theResult____h672303[34] && - !_theResult____h672303[33] && - !_theResult____h672303[32] && - !_theResult____h672303[31] && - !_theResult____h672303[30] && - !_theResult____h672303[29] && - !_theResult____h672303[28] && - !_theResult____h672303[27] && - !_theResult____h672303[26] && - !_theResult____h672303[25] && - !_theResult____h672303[24] && - !_theResult____h672303[23] && - !_theResult____h672303[22] && - !_theResult____h672303[21] && - !_theResult____h672303[20] && - !_theResult____h672303[19] && - !_theResult____h672303[18] && - !_theResult____h672303[17] && - !_theResult____h672303[16] && - !_theResult____h672303[15] && - !_theResult____h672303[14] && - !_theResult____h672303[13] && - !_theResult____h672303[12] && - !_theResult____h672303[11] && - !_theResult____h672303[10] && - !_theResult____h672303[9] && - !_theResult____h672303[8] && - !_theResult____h672303[7] && - !_theResult____h672303[6] && - !_theResult____h672303[5] && - !_theResult____h672303[4] && - !_theResult____h672303[3] && - !_theResult____h672303[2] && - !_theResult____h672303[1] && - !_theResult____h672303[0]) ? - _theResult____h672303 : - _theResult___snd__h680452 ; - assign _theResult___snd__h680452 = + assign _theResult___snd__h680420 = { _theResult____h672300[55:0], 1'd0 } ; + assign _theResult___snd__h680431 = + (!_theResult____h672300[56] && _theResult____h672300[55]) ? + _theResult___snd__h680433 : + _theResult___snd__h680443 ; + assign _theResult___snd__h680433 = { _theResult____h672300[54:0], 2'd0 } ; + assign _theResult___snd__h680443 = + (!_theResult____h672300[56] && !_theResult____h672300[55] && + !_theResult____h672300[54] && + !_theResult____h672300[53] && + !_theResult____h672300[52] && + !_theResult____h672300[51] && + !_theResult____h672300[50] && + !_theResult____h672300[49] && + !_theResult____h672300[48] && + !_theResult____h672300[47] && + !_theResult____h672300[46] && + !_theResult____h672300[45] && + !_theResult____h672300[44] && + !_theResult____h672300[43] && + !_theResult____h672300[42] && + !_theResult____h672300[41] && + !_theResult____h672300[40] && + !_theResult____h672300[39] && + !_theResult____h672300[38] && + !_theResult____h672300[37] && + !_theResult____h672300[36] && + !_theResult____h672300[35] && + !_theResult____h672300[34] && + !_theResult____h672300[33] && + !_theResult____h672300[32] && + !_theResult____h672300[31] && + !_theResult____h672300[30] && + !_theResult____h672300[29] && + !_theResult____h672300[28] && + !_theResult____h672300[27] && + !_theResult____h672300[26] && + !_theResult____h672300[25] && + !_theResult____h672300[24] && + !_theResult____h672300[23] && + !_theResult____h672300[22] && + !_theResult____h672300[21] && + !_theResult____h672300[20] && + !_theResult____h672300[19] && + !_theResult____h672300[18] && + !_theResult____h672300[17] && + !_theResult____h672300[16] && + !_theResult____h672300[15] && + !_theResult____h672300[14] && + !_theResult____h672300[13] && + !_theResult____h672300[12] && + !_theResult____h672300[11] && + !_theResult____h672300[10] && + !_theResult____h672300[9] && + !_theResult____h672300[8] && + !_theResult____h672300[7] && + !_theResult____h672300[6] && + !_theResult____h672300[5] && + !_theResult____h672300[4] && + !_theResult____h672300[3] && + !_theResult____h672300[2] && + !_theResult____h672300[1] && + !_theResult____h672300[0]) ? + _theResult____h672300 : + _theResult___snd__h680449 ; + assign _theResult___snd__h680449 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110[54:0], 2'd0 } ; - assign _theResult___snd__h680475 = - _theResult____h672303 << + assign _theResult___snd__h680472 = + _theResult____h672300 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11237 ; - assign _theResult___snd__h689019 = + assign _theResult___snd__h689016 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h689028 : - _theResult___snd__h689021 ; - assign _theResult___snd__h689021 = + _theResult___snd__h689025 : + _theResult___snd__h689018 ; + assign _theResult___snd__h689018 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h689028 = + assign _theResult___snd__h689025 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11413) ? - sfd__h664701 : - _theResult___snd__h689034 ; - assign _theResult___snd__h689034 = + sfd__h664698 : + _theResult___snd__h689031 ; + assign _theResult___snd__h689031 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q112[54:0], 2'd0 } ; - assign _theResult___snd__h689057 = - sfd__h664701 << + assign _theResult___snd__h689054 = + sfd__h664698 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11468 ; - assign _theResult___snd__h698189 = { _theResult____h689940[55:0], 1'd0 } ; - assign _theResult___snd__h698200 = - (!_theResult____h689940[56] && _theResult____h689940[55]) ? - _theResult___snd__h698202 : - _theResult___snd__h698212 ; - assign _theResult___snd__h698202 = { _theResult____h689940[54:0], 2'd0 } ; - assign _theResult___snd__h698212 = - (!_theResult____h689940[56] && !_theResult____h689940[55] && - !_theResult____h689940[54] && - !_theResult____h689940[53] && - !_theResult____h689940[52] && - !_theResult____h689940[51] && - !_theResult____h689940[50] && - !_theResult____h689940[49] && - !_theResult____h689940[48] && - !_theResult____h689940[47] && - !_theResult____h689940[46] && - !_theResult____h689940[45] && - !_theResult____h689940[44] && - !_theResult____h689940[43] && - !_theResult____h689940[42] && - !_theResult____h689940[41] && - !_theResult____h689940[40] && - !_theResult____h689940[39] && - !_theResult____h689940[38] && - !_theResult____h689940[37] && - !_theResult____h689940[36] && - !_theResult____h689940[35] && - !_theResult____h689940[34] && - !_theResult____h689940[33] && - !_theResult____h689940[32] && - !_theResult____h689940[31] && - !_theResult____h689940[30] && - !_theResult____h689940[29] && - !_theResult____h689940[28] && - !_theResult____h689940[27] && - !_theResult____h689940[26] && - !_theResult____h689940[25] && - !_theResult____h689940[24] && - !_theResult____h689940[23] && - !_theResult____h689940[22] && - !_theResult____h689940[21] && - !_theResult____h689940[20] && - !_theResult____h689940[19] && - !_theResult____h689940[18] && - !_theResult____h689940[17] && - !_theResult____h689940[16] && - !_theResult____h689940[15] && - !_theResult____h689940[14] && - !_theResult____h689940[13] && - !_theResult____h689940[12] && - !_theResult____h689940[11] && - !_theResult____h689940[10] && - !_theResult____h689940[9] && - !_theResult____h689940[8] && - !_theResult____h689940[7] && - !_theResult____h689940[6] && - !_theResult____h689940[5] && - !_theResult____h689940[4] && - !_theResult____h689940[3] && - !_theResult____h689940[2] && - !_theResult____h689940[1] && - !_theResult____h689940[0]) ? - _theResult____h689940 : - _theResult___snd__h698218 ; - assign _theResult___snd__h698218 = + assign _theResult___snd__h698186 = { _theResult____h689937[55:0], 1'd0 } ; + assign _theResult___snd__h698197 = + (!_theResult____h689937[56] && _theResult____h689937[55]) ? + _theResult___snd__h698199 : + _theResult___snd__h698209 ; + assign _theResult___snd__h698199 = { _theResult____h689937[54:0], 2'd0 } ; + assign _theResult___snd__h698209 = + (!_theResult____h689937[56] && !_theResult____h689937[55] && + !_theResult____h689937[54] && + !_theResult____h689937[53] && + !_theResult____h689937[52] && + !_theResult____h689937[51] && + !_theResult____h689937[50] && + !_theResult____h689937[49] && + !_theResult____h689937[48] && + !_theResult____h689937[47] && + !_theResult____h689937[46] && + !_theResult____h689937[45] && + !_theResult____h689937[44] && + !_theResult____h689937[43] && + !_theResult____h689937[42] && + !_theResult____h689937[41] && + !_theResult____h689937[40] && + !_theResult____h689937[39] && + !_theResult____h689937[38] && + !_theResult____h689937[37] && + !_theResult____h689937[36] && + !_theResult____h689937[35] && + !_theResult____h689937[34] && + !_theResult____h689937[33] && + !_theResult____h689937[32] && + !_theResult____h689937[31] && + !_theResult____h689937[30] && + !_theResult____h689937[29] && + !_theResult____h689937[28] && + !_theResult____h689937[27] && + !_theResult____h689937[26] && + !_theResult____h689937[25] && + !_theResult____h689937[24] && + !_theResult____h689937[23] && + !_theResult____h689937[22] && + !_theResult____h689937[21] && + !_theResult____h689937[20] && + !_theResult____h689937[19] && + !_theResult____h689937[18] && + !_theResult____h689937[17] && + !_theResult____h689937[16] && + !_theResult____h689937[15] && + !_theResult____h689937[14] && + !_theResult____h689937[13] && + !_theResult____h689937[12] && + !_theResult____h689937[11] && + !_theResult____h689937[10] && + !_theResult____h689937[9] && + !_theResult____h689937[8] && + !_theResult____h689937[7] && + !_theResult____h689937[6] && + !_theResult____h689937[5] && + !_theResult____h689937[4] && + !_theResult____h689937[3] && + !_theResult____h689937[2] && + !_theResult____h689937[1] && + !_theResult____h689937[0]) ? + _theResult____h689937 : + _theResult___snd__h698215 ; + assign _theResult___snd__h698215 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q120[54:0], 2'd0 } ; - assign _theResult___snd__h698241 = - _theResult____h689940 << + assign _theResult___snd__h698238 = + _theResult____h689937 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11788 ; - assign _theResult___snd__h706809 = + assign _theResult___snd__h706806 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h706823 : - _theResult___snd__h689021 ; - assign _theResult___snd__h706823 = + _theResult___snd__h706820 : + _theResult___snd__h689018 ; + assign _theResult___snd__h706820 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11413) ? - sfd__h664701 : - _theResult___snd__h706829 ; - assign _theResult___snd__h706829 = + sfd__h664698 : + _theResult___snd__h706826 ; + assign _theResult___snd__h706826 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q125[54:0], 2'd0 } ; - assign _theResult___snd__h706847 = - sfd__h664701 << + assign _theResult___snd__h706844 = + sfd__h664698 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11862[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11862) ; - assign _theResult___snd__h739096 = - (f1_exp__h719757 == 8'd0) ? - _theResult___snd__h739105 : - _theResult___snd__h739098 ; - assign _theResult___snd__h739098 = { f1_sfd__h719758, 34'd0 } ; - assign _theResult___snd__h739105 = - (f1_exp__h719757 == 8'd0 && !f1_sfd__h719758[22] && + assign _theResult___snd__h739093 = + (f1_exp__h719754 == 8'd0) ? + _theResult___snd__h739102 : + _theResult___snd__h739095 ; + assign _theResult___snd__h739095 = { f1_sfd__h719755, 34'd0 } ; + assign _theResult___snd__h739102 = + (f1_exp__h719754 == 8'd0 && !f1_sfd__h719755[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12795) ? - sfd__h720119 : - _theResult___snd__h739111 ; - assign _theResult___snd__h739111 = + sfd__h720116 : + _theResult___snd__h739108 ; + assign _theResult___snd__h739108 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145[54:0], 2'd0 } ; - assign _theResult___snd__h739134 = - sfd__h720119 << + assign _theResult___snd__h739131 = + sfd__h720116 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12822 ; - assign _theResult___snd__h748733 = { _theResult____h740486[55:0], 1'd0 } ; - assign _theResult___snd__h748744 = - (!_theResult____h740486[56] && _theResult____h740486[55]) ? - _theResult___snd__h748746 : - _theResult___snd__h748756 ; - assign _theResult___snd__h748746 = { _theResult____h740486[54:0], 2'd0 } ; - assign _theResult___snd__h748756 = - (!_theResult____h740486[56] && !_theResult____h740486[55] && - !_theResult____h740486[54] && - !_theResult____h740486[53] && - !_theResult____h740486[52] && - !_theResult____h740486[51] && - !_theResult____h740486[50] && - !_theResult____h740486[49] && - !_theResult____h740486[48] && - !_theResult____h740486[47] && - !_theResult____h740486[46] && - !_theResult____h740486[45] && - !_theResult____h740486[44] && - !_theResult____h740486[43] && - !_theResult____h740486[42] && - !_theResult____h740486[41] && - !_theResult____h740486[40] && - !_theResult____h740486[39] && - !_theResult____h740486[38] && - !_theResult____h740486[37] && - !_theResult____h740486[36] && - !_theResult____h740486[35] && - !_theResult____h740486[34] && - !_theResult____h740486[33] && - !_theResult____h740486[32] && - !_theResult____h740486[31] && - !_theResult____h740486[30] && - !_theResult____h740486[29] && - !_theResult____h740486[28] && - !_theResult____h740486[27] && - !_theResult____h740486[26] && - !_theResult____h740486[25] && - !_theResult____h740486[24] && - !_theResult____h740486[23] && - !_theResult____h740486[22] && - !_theResult____h740486[21] && - !_theResult____h740486[20] && - !_theResult____h740486[19] && - !_theResult____h740486[18] && - !_theResult____h740486[17] && - !_theResult____h740486[16] && - !_theResult____h740486[15] && - !_theResult____h740486[14] && - !_theResult____h740486[13] && - !_theResult____h740486[12] && - !_theResult____h740486[11] && - !_theResult____h740486[10] && - !_theResult____h740486[9] && - !_theResult____h740486[8] && - !_theResult____h740486[7] && - !_theResult____h740486[6] && - !_theResult____h740486[5] && - !_theResult____h740486[4] && - !_theResult____h740486[3] && - !_theResult____h740486[2] && - !_theResult____h740486[1] && - !_theResult____h740486[0]) ? - _theResult____h740486 : - _theResult___snd__h748762 ; - assign _theResult___snd__h748762 = + assign _theResult___snd__h748730 = { _theResult____h740483[55:0], 1'd0 } ; + assign _theResult___snd__h748741 = + (!_theResult____h740483[56] && _theResult____h740483[55]) ? + _theResult___snd__h748743 : + _theResult___snd__h748753 ; + assign _theResult___snd__h748743 = { _theResult____h740483[54:0], 2'd0 } ; + assign _theResult___snd__h748753 = + (!_theResult____h740483[56] && !_theResult____h740483[55] && + !_theResult____h740483[54] && + !_theResult____h740483[53] && + !_theResult____h740483[52] && + !_theResult____h740483[51] && + !_theResult____h740483[50] && + !_theResult____h740483[49] && + !_theResult____h740483[48] && + !_theResult____h740483[47] && + !_theResult____h740483[46] && + !_theResult____h740483[45] && + !_theResult____h740483[44] && + !_theResult____h740483[43] && + !_theResult____h740483[42] && + !_theResult____h740483[41] && + !_theResult____h740483[40] && + !_theResult____h740483[39] && + !_theResult____h740483[38] && + !_theResult____h740483[37] && + !_theResult____h740483[36] && + !_theResult____h740483[35] && + !_theResult____h740483[34] && + !_theResult____h740483[33] && + !_theResult____h740483[32] && + !_theResult____h740483[31] && + !_theResult____h740483[30] && + !_theResult____h740483[29] && + !_theResult____h740483[28] && + !_theResult____h740483[27] && + !_theResult____h740483[26] && + !_theResult____h740483[25] && + !_theResult____h740483[24] && + !_theResult____h740483[23] && + !_theResult____h740483[22] && + !_theResult____h740483[21] && + !_theResult____h740483[20] && + !_theResult____h740483[19] && + !_theResult____h740483[18] && + !_theResult____h740483[17] && + !_theResult____h740483[16] && + !_theResult____h740483[15] && + !_theResult____h740483[14] && + !_theResult____h740483[13] && + !_theResult____h740483[12] && + !_theResult____h740483[11] && + !_theResult____h740483[10] && + !_theResult____h740483[9] && + !_theResult____h740483[8] && + !_theResult____h740483[7] && + !_theResult____h740483[6] && + !_theResult____h740483[5] && + !_theResult____h740483[4] && + !_theResult____h740483[3] && + !_theResult____h740483[2] && + !_theResult____h740483[1] && + !_theResult____h740483[0]) ? + _theResult____h740483 : + _theResult___snd__h748759 ; + assign _theResult___snd__h748759 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149[54:0], 2'd0 } ; - assign _theResult___snd__h748785 = - _theResult____h740486 << + assign _theResult___snd__h748782 = + _theResult____h740483 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13134 ; - assign _theResult___snd__h757501 = - (f1_exp__h719757 == 8'd0) ? - _theResult___snd__h757515 : - _theResult___snd__h739098 ; - assign _theResult___snd__h757515 = - (f1_exp__h719757 == 8'd0 && !f1_sfd__h719758[22] && + assign _theResult___snd__h757498 = + (f1_exp__h719754 == 8'd0) ? + _theResult___snd__h757512 : + _theResult___snd__h739095 ; + assign _theResult___snd__h757512 = + (f1_exp__h719754 == 8'd0 && !f1_sfd__h719755[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12795) ? - sfd__h720119 : - _theResult___snd__h757521 ; - assign _theResult___snd__h757521 = + sfd__h720116 : + _theResult___snd__h757518 ; + assign _theResult___snd__h757518 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152[54:0], 2'd0 } ; - assign _theResult___snd__h757539 = - sfd__h720119 << + assign _theResult___snd__h757536 = + sfd__h720116 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13185 ; - assign _theResult___snd__h777949 = - (f2_exp__h758751 == 8'd0) ? - _theResult___snd__h777958 : - _theResult___snd__h777951 ; - assign _theResult___snd__h777951 = { f2_sfd__h758752, 34'd0 } ; - assign _theResult___snd__h777958 = - (f2_exp__h758751 == 8'd0 && !f2_sfd__h758752[22] && + assign _theResult___snd__h777946 = + (f2_exp__h758748 == 8'd0) ? + _theResult___snd__h777955 : + _theResult___snd__h777948 ; + assign _theResult___snd__h777948 = { f2_sfd__h758749, 34'd0 } ; + assign _theResult___snd__h777955 = + (f2_exp__h758748 == 8'd0 && !f2_sfd__h758749[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14295) ? - sfd__h759113 : - _theResult___snd__h777964 ; - assign _theResult___snd__h777964 = + sfd__h759110 : + _theResult___snd__h777961 ; + assign _theResult___snd__h777961 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185[54:0], 2'd0 } ; - assign _theResult___snd__h777987 = - sfd__h759113 << + assign _theResult___snd__h777984 = + sfd__h759110 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14322 ; - assign _theResult___snd__h787586 = { _theResult____h779339[55:0], 1'd0 } ; - assign _theResult___snd__h787597 = - (!_theResult____h779339[56] && _theResult____h779339[55]) ? - _theResult___snd__h787599 : - _theResult___snd__h787609 ; - assign _theResult___snd__h787599 = { _theResult____h779339[54:0], 2'd0 } ; - assign _theResult___snd__h787609 = - (!_theResult____h779339[56] && !_theResult____h779339[55] && - !_theResult____h779339[54] && - !_theResult____h779339[53] && - !_theResult____h779339[52] && - !_theResult____h779339[51] && - !_theResult____h779339[50] && - !_theResult____h779339[49] && - !_theResult____h779339[48] && - !_theResult____h779339[47] && - !_theResult____h779339[46] && - !_theResult____h779339[45] && - !_theResult____h779339[44] && - !_theResult____h779339[43] && - !_theResult____h779339[42] && - !_theResult____h779339[41] && - !_theResult____h779339[40] && - !_theResult____h779339[39] && - !_theResult____h779339[38] && - !_theResult____h779339[37] && - !_theResult____h779339[36] && - !_theResult____h779339[35] && - !_theResult____h779339[34] && - !_theResult____h779339[33] && - !_theResult____h779339[32] && - !_theResult____h779339[31] && - !_theResult____h779339[30] && - !_theResult____h779339[29] && - !_theResult____h779339[28] && - !_theResult____h779339[27] && - !_theResult____h779339[26] && - !_theResult____h779339[25] && - !_theResult____h779339[24] && - !_theResult____h779339[23] && - !_theResult____h779339[22] && - !_theResult____h779339[21] && - !_theResult____h779339[20] && - !_theResult____h779339[19] && - !_theResult____h779339[18] && - !_theResult____h779339[17] && - !_theResult____h779339[16] && - !_theResult____h779339[15] && - !_theResult____h779339[14] && - !_theResult____h779339[13] && - !_theResult____h779339[12] && - !_theResult____h779339[11] && - !_theResult____h779339[10] && - !_theResult____h779339[9] && - !_theResult____h779339[8] && - !_theResult____h779339[7] && - !_theResult____h779339[6] && - !_theResult____h779339[5] && - !_theResult____h779339[4] && - !_theResult____h779339[3] && - !_theResult____h779339[2] && - !_theResult____h779339[1] && - !_theResult____h779339[0]) ? - _theResult____h779339 : - _theResult___snd__h787615 ; - assign _theResult___snd__h787615 = + assign _theResult___snd__h787583 = { _theResult____h779336[55:0], 1'd0 } ; + assign _theResult___snd__h787594 = + (!_theResult____h779336[56] && _theResult____h779336[55]) ? + _theResult___snd__h787596 : + _theResult___snd__h787606 ; + assign _theResult___snd__h787596 = { _theResult____h779336[54:0], 2'd0 } ; + assign _theResult___snd__h787606 = + (!_theResult____h779336[56] && !_theResult____h779336[55] && + !_theResult____h779336[54] && + !_theResult____h779336[53] && + !_theResult____h779336[52] && + !_theResult____h779336[51] && + !_theResult____h779336[50] && + !_theResult____h779336[49] && + !_theResult____h779336[48] && + !_theResult____h779336[47] && + !_theResult____h779336[46] && + !_theResult____h779336[45] && + !_theResult____h779336[44] && + !_theResult____h779336[43] && + !_theResult____h779336[42] && + !_theResult____h779336[41] && + !_theResult____h779336[40] && + !_theResult____h779336[39] && + !_theResult____h779336[38] && + !_theResult____h779336[37] && + !_theResult____h779336[36] && + !_theResult____h779336[35] && + !_theResult____h779336[34] && + !_theResult____h779336[33] && + !_theResult____h779336[32] && + !_theResult____h779336[31] && + !_theResult____h779336[30] && + !_theResult____h779336[29] && + !_theResult____h779336[28] && + !_theResult____h779336[27] && + !_theResult____h779336[26] && + !_theResult____h779336[25] && + !_theResult____h779336[24] && + !_theResult____h779336[23] && + !_theResult____h779336[22] && + !_theResult____h779336[21] && + !_theResult____h779336[20] && + !_theResult____h779336[19] && + !_theResult____h779336[18] && + !_theResult____h779336[17] && + !_theResult____h779336[16] && + !_theResult____h779336[15] && + !_theResult____h779336[14] && + !_theResult____h779336[13] && + !_theResult____h779336[12] && + !_theResult____h779336[11] && + !_theResult____h779336[10] && + !_theResult____h779336[9] && + !_theResult____h779336[8] && + !_theResult____h779336[7] && + !_theResult____h779336[6] && + !_theResult____h779336[5] && + !_theResult____h779336[4] && + !_theResult____h779336[3] && + !_theResult____h779336[2] && + !_theResult____h779336[1] && + !_theResult____h779336[0]) ? + _theResult____h779336 : + _theResult___snd__h787612 ; + assign _theResult___snd__h787612 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189[54:0], 2'd0 } ; - assign _theResult___snd__h787638 = - _theResult____h779339 << + assign _theResult___snd__h787635 = + _theResult____h779336 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14619 ; - assign _theResult___snd__h796354 = - (f2_exp__h758751 == 8'd0) ? - _theResult___snd__h796368 : - _theResult___snd__h777951 ; - assign _theResult___snd__h796368 = - (f2_exp__h758751 == 8'd0 && !f2_sfd__h758752[22] && + assign _theResult___snd__h796351 = + (f2_exp__h758748 == 8'd0) ? + _theResult___snd__h796365 : + _theResult___snd__h777948 ; + assign _theResult___snd__h796365 = + (f2_exp__h758748 == 8'd0 && !f2_sfd__h758749[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14295) ? - sfd__h759113 : - _theResult___snd__h796374 ; - assign _theResult___snd__h796374 = + sfd__h759110 : + _theResult___snd__h796371 ; + assign _theResult___snd__h796371 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192[54:0], 2'd0 } ; - assign _theResult___snd__h796392 = - sfd__h759113 << + assign _theResult___snd__h796389 = + sfd__h759110 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14670 ; - assign _theResult___snd__h817253 = - (f3_exp__h798055 == 8'd0) ? - _theResult___snd__h817262 : - _theResult___snd__h817255 ; - assign _theResult___snd__h817255 = { f3_sfd__h798056, 34'd0 } ; - assign _theResult___snd__h817262 = - (f3_exp__h798055 == 8'd0 && !f3_sfd__h798056[22] && + assign _theResult___snd__h817250 = + (f3_exp__h798052 == 8'd0) ? + _theResult___snd__h817259 : + _theResult___snd__h817252 ; + assign _theResult___snd__h817252 = { f3_sfd__h798053, 34'd0 } ; + assign _theResult___snd__h817259 = + (f3_exp__h798052 == 8'd0 && !f3_sfd__h798053[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13525) ? - sfd__h798417 : - _theResult___snd__h817268 ; - assign _theResult___snd__h817268 = + sfd__h798414 : + _theResult___snd__h817265 ; + assign _theResult___snd__h817265 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162[54:0], 2'd0 } ; - assign _theResult___snd__h817291 = - sfd__h798417 << + assign _theResult___snd__h817288 = + sfd__h798414 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13552 ; - assign _theResult___snd__h826890 = { _theResult____h818643[55:0], 1'd0 } ; - assign _theResult___snd__h826901 = - (!_theResult____h818643[56] && _theResult____h818643[55]) ? - _theResult___snd__h826903 : - _theResult___snd__h826913 ; - assign _theResult___snd__h826903 = { _theResult____h818643[54:0], 2'd0 } ; - assign _theResult___snd__h826913 = - (!_theResult____h818643[56] && !_theResult____h818643[55] && - !_theResult____h818643[54] && - !_theResult____h818643[53] && - !_theResult____h818643[52] && - !_theResult____h818643[51] && - !_theResult____h818643[50] && - !_theResult____h818643[49] && - !_theResult____h818643[48] && - !_theResult____h818643[47] && - !_theResult____h818643[46] && - !_theResult____h818643[45] && - !_theResult____h818643[44] && - !_theResult____h818643[43] && - !_theResult____h818643[42] && - !_theResult____h818643[41] && - !_theResult____h818643[40] && - !_theResult____h818643[39] && - !_theResult____h818643[38] && - !_theResult____h818643[37] && - !_theResult____h818643[36] && - !_theResult____h818643[35] && - !_theResult____h818643[34] && - !_theResult____h818643[33] && - !_theResult____h818643[32] && - !_theResult____h818643[31] && - !_theResult____h818643[30] && - !_theResult____h818643[29] && - !_theResult____h818643[28] && - !_theResult____h818643[27] && - !_theResult____h818643[26] && - !_theResult____h818643[25] && - !_theResult____h818643[24] && - !_theResult____h818643[23] && - !_theResult____h818643[22] && - !_theResult____h818643[21] && - !_theResult____h818643[20] && - !_theResult____h818643[19] && - !_theResult____h818643[18] && - !_theResult____h818643[17] && - !_theResult____h818643[16] && - !_theResult____h818643[15] && - !_theResult____h818643[14] && - !_theResult____h818643[13] && - !_theResult____h818643[12] && - !_theResult____h818643[11] && - !_theResult____h818643[10] && - !_theResult____h818643[9] && - !_theResult____h818643[8] && - !_theResult____h818643[7] && - !_theResult____h818643[6] && - !_theResult____h818643[5] && - !_theResult____h818643[4] && - !_theResult____h818643[3] && - !_theResult____h818643[2] && - !_theResult____h818643[1] && - !_theResult____h818643[0]) ? - _theResult____h818643 : - _theResult___snd__h826919 ; - assign _theResult___snd__h826919 = + assign _theResult___snd__h826887 = { _theResult____h818640[55:0], 1'd0 } ; + assign _theResult___snd__h826898 = + (!_theResult____h818640[56] && _theResult____h818640[55]) ? + _theResult___snd__h826900 : + _theResult___snd__h826910 ; + assign _theResult___snd__h826900 = { _theResult____h818640[54:0], 2'd0 } ; + assign _theResult___snd__h826910 = + (!_theResult____h818640[56] && !_theResult____h818640[55] && + !_theResult____h818640[54] && + !_theResult____h818640[53] && + !_theResult____h818640[52] && + !_theResult____h818640[51] && + !_theResult____h818640[50] && + !_theResult____h818640[49] && + !_theResult____h818640[48] && + !_theResult____h818640[47] && + !_theResult____h818640[46] && + !_theResult____h818640[45] && + !_theResult____h818640[44] && + !_theResult____h818640[43] && + !_theResult____h818640[42] && + !_theResult____h818640[41] && + !_theResult____h818640[40] && + !_theResult____h818640[39] && + !_theResult____h818640[38] && + !_theResult____h818640[37] && + !_theResult____h818640[36] && + !_theResult____h818640[35] && + !_theResult____h818640[34] && + !_theResult____h818640[33] && + !_theResult____h818640[32] && + !_theResult____h818640[31] && + !_theResult____h818640[30] && + !_theResult____h818640[29] && + !_theResult____h818640[28] && + !_theResult____h818640[27] && + !_theResult____h818640[26] && + !_theResult____h818640[25] && + !_theResult____h818640[24] && + !_theResult____h818640[23] && + !_theResult____h818640[22] && + !_theResult____h818640[21] && + !_theResult____h818640[20] && + !_theResult____h818640[19] && + !_theResult____h818640[18] && + !_theResult____h818640[17] && + !_theResult____h818640[16] && + !_theResult____h818640[15] && + !_theResult____h818640[14] && + !_theResult____h818640[13] && + !_theResult____h818640[12] && + !_theResult____h818640[11] && + !_theResult____h818640[10] && + !_theResult____h818640[9] && + !_theResult____h818640[8] && + !_theResult____h818640[7] && + !_theResult____h818640[6] && + !_theResult____h818640[5] && + !_theResult____h818640[4] && + !_theResult____h818640[3] && + !_theResult____h818640[2] && + !_theResult____h818640[1] && + !_theResult____h818640[0]) ? + _theResult____h818640 : + _theResult___snd__h826916 ; + assign _theResult___snd__h826916 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h826942 = - _theResult____h818643 << + assign _theResult___snd__h826939 = + _theResult____h818640 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13849 ; - assign _theResult___snd__h835658 = - (f3_exp__h798055 == 8'd0) ? - _theResult___snd__h835672 : - _theResult___snd__h817255 ; - assign _theResult___snd__h835672 = - (f3_exp__h798055 == 8'd0 && !f3_sfd__h798056[22] && + assign _theResult___snd__h835655 = + (f3_exp__h798052 == 8'd0) ? + _theResult___snd__h835669 : + _theResult___snd__h817252 ; + assign _theResult___snd__h835669 = + (f3_exp__h798052 == 8'd0 && !f3_sfd__h798053[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13525) ? - sfd__h798417 : - _theResult___snd__h835678 ; - assign _theResult___snd__h835678 = + sfd__h798414 : + _theResult___snd__h835675 ; + assign _theResult___snd__h835675 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169[54:0], 2'd0 } ; - assign _theResult___snd__h835696 = - sfd__h798417 << + assign _theResult___snd__h835693 = + sfd__h798414 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13900 ; - assign _theResult___snd__h841152 = - b__h840604[63] ? b___1__h841217 : b__h840604 ; - assign _theResult___snd_fst_exp__h598098 = + assign _theResult___snd__h841149 = + b__h840601[63] ? b___1__h841214 : b__h840601 ; + assign _theResult___snd_fst_exp__h598095 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8209 ? - _theResult___fst_exp__h589513 : - _theResult___fst_exp__h598095 ; - assign _theResult___snd_fst_exp__h615918 = + _theResult___fst_exp__h589510 : + _theResult___fst_exp__h598092 ; + assign _theResult___snd_fst_exp__h615915 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8749 ? - _theResult___fst_exp__h607279 : - _theResult___fst_exp__h615915 ; - assign _theResult___snd_fst_exp__h643847 = + _theResult___fst_exp__h607276 : + _theResult___fst_exp__h615912 ; + assign _theResult___snd_fst_exp__h643844 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9606 ? - _theResult___fst_exp__h635262 : - _theResult___fst_exp__h643844 ; - assign _theResult___snd_fst_exp__h661667 = + _theResult___fst_exp__h635259 : + _theResult___fst_exp__h643841 ; + assign _theResult___snd_fst_exp__h661664 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10146 ? - _theResult___fst_exp__h653028 : - _theResult___fst_exp__h661664 ; - assign _theResult___snd_fst_exp__h689594 = + _theResult___fst_exp__h653025 : + _theResult___fst_exp__h661661 ; + assign _theResult___snd_fst_exp__h689591 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11003 ? - _theResult___fst_exp__h681009 : - _theResult___fst_exp__h689591 ; - assign _theResult___snd_fst_exp__h707414 = + _theResult___fst_exp__h681006 : + _theResult___fst_exp__h689588 ; + assign _theResult___snd_fst_exp__h707411 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11543 ? - _theResult___fst_exp__h698775 : - _theResult___fst_exp__h707411 ; - assign _theResult___snd_fst_exp__h739906 = + _theResult___fst_exp__h698772 : + _theResult___fst_exp__h707408 ; + assign _theResult___snd_fst_exp__h739903 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 ? 11'd0 : - _theResult___fst_exp__h739903 ; - assign _theResult___snd_fst_exp__h758341 = + _theResult___fst_exp__h739900 ; + assign _theResult___snd_fst_exp__h758338 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12887 ? - _theResult___fst_exp__h749554 : - _theResult___fst_exp__h758338 ; - assign _theResult___snd_fst_exp__h778759 = + _theResult___fst_exp__h749551 : + _theResult___fst_exp__h758335 ; + assign _theResult___snd_fst_exp__h778756 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 ? 11'd0 : - _theResult___fst_exp__h778756 ; - assign _theResult___snd_fst_exp__h797194 = + _theResult___fst_exp__h778753 ; + assign _theResult___snd_fst_exp__h797191 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14372 ? - _theResult___fst_exp__h788407 : - _theResult___fst_exp__h797191 ; - assign _theResult___snd_fst_exp__h818063 = + _theResult___fst_exp__h788404 : + _theResult___fst_exp__h797188 ; + assign _theResult___snd_fst_exp__h818060 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 ? 11'd0 : - _theResult___fst_exp__h818060 ; - assign _theResult___snd_fst_exp__h836498 = + _theResult___fst_exp__h818057 ; + assign _theResult___snd_fst_exp__h836495 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13602 ? - _theResult___fst_exp__h827711 : - _theResult___fst_exp__h836495 ; - assign _theResult___snd_fst_sfd__h573150 = + _theResult___fst_exp__h827708 : + _theResult___fst_exp__h836492 ; + assign _theResult___snd_fst_sfd__h573147 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h598099 = + assign _theResult___snd_fst_sfd__h598096 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8209 ? - _theResult___fst_sfd__h589514 : - _theResult___fst_sfd__h598096 ; - assign _theResult___snd_fst_sfd__h615919 = + _theResult___fst_sfd__h589511 : + _theResult___fst_sfd__h598093 ; + assign _theResult___snd_fst_sfd__h615916 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8749 ? - _theResult___fst_sfd__h607280 : - _theResult___fst_sfd__h615916 ; - assign _theResult___snd_fst_sfd__h618904 = + _theResult___fst_sfd__h607277 : + _theResult___fst_sfd__h615913 ; + assign _theResult___snd_fst_sfd__h618901 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h643848 = + assign _theResult___snd_fst_sfd__h643845 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9606 ? - _theResult___fst_sfd__h635263 : - _theResult___fst_sfd__h643845 ; - assign _theResult___snd_fst_sfd__h661668 = + _theResult___fst_sfd__h635260 : + _theResult___fst_sfd__h643842 ; + assign _theResult___snd_fst_sfd__h661665 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10146 ? - _theResult___fst_sfd__h653029 : - _theResult___fst_sfd__h661665 ; - assign _theResult___snd_fst_sfd__h664651 = + _theResult___fst_sfd__h653026 : + _theResult___fst_sfd__h661662 ; + assign _theResult___snd_fst_sfd__h664648 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h689595 = + assign _theResult___snd_fst_sfd__h689592 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11003 ? - _theResult___fst_sfd__h681010 : - _theResult___fst_sfd__h689592 ; - assign _theResult___snd_fst_sfd__h707415 = + _theResult___fst_sfd__h681007 : + _theResult___fst_sfd__h689589 ; + assign _theResult___snd_fst_sfd__h707412 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11543 ? - _theResult___fst_sfd__h698776 : - _theResult___fst_sfd__h707412 ; - assign _theResult___snd_fst_sfd__h720073 = - (f1_sfd__h719758 == 23'd0) ? + _theResult___fst_sfd__h698773 : + _theResult___fst_sfd__h707409 ; + assign _theResult___snd_fst_sfd__h720070 = + (f1_sfd__h719755 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h719821 ; - assign _theResult___snd_fst_sfd__h739907 = + out___1_sfd__h719818 ; + assign _theResult___snd_fst_sfd__h739904 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12751 ? 52'd0 : - _theResult___fst_sfd__h739904 ; - assign _theResult___snd_fst_sfd__h758342 = + _theResult___fst_sfd__h739901 ; + assign _theResult___snd_fst_sfd__h758339 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12887 ? - _theResult___fst_sfd__h749555 : - _theResult___fst_sfd__h758339 ; - assign _theResult___snd_fst_sfd__h759067 = - (f2_sfd__h758752 == 23'd0) ? + _theResult___fst_sfd__h749552 : + _theResult___fst_sfd__h758336 ; + assign _theResult___snd_fst_sfd__h759064 = + (f2_sfd__h758749 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h758815 ; - assign _theResult___snd_fst_sfd__h778760 = + out___1_sfd__h758812 ; + assign _theResult___snd_fst_sfd__h778757 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14251 ? 52'd0 : - _theResult___fst_sfd__h778757 ; - assign _theResult___snd_fst_sfd__h797195 = + _theResult___fst_sfd__h778754 ; + assign _theResult___snd_fst_sfd__h797192 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14372 ? - _theResult___fst_sfd__h788408 : - _theResult___fst_sfd__h797192 ; - assign _theResult___snd_fst_sfd__h798371 = - (f3_sfd__h798056 == 23'd0) ? + _theResult___fst_sfd__h788405 : + _theResult___fst_sfd__h797189 ; + assign _theResult___snd_fst_sfd__h798368 = + (f3_sfd__h798053 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h798119 ; - assign _theResult___snd_fst_sfd__h818064 = + out___1_sfd__h798116 ; + assign _theResult___snd_fst_sfd__h818061 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13481 ? 52'd0 : - _theResult___fst_sfd__h818061 ; - assign _theResult___snd_fst_sfd__h836499 = + _theResult___fst_sfd__h818058 ; + assign _theResult___snd_fst_sfd__h836496 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13602 ? - _theResult___fst_sfd__h827712 : - _theResult___fst_sfd__h836496 ; - assign a___1__h840765 = + _theResult___fst_sfd__h827709 : + _theResult___fst_sfd__h836493 ; + assign a___1__h840762 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22 } ; - assign a___1__h841156 = 64'd0 - a__h840603 ; - assign a__h840603 = + assign a___1__h841153 = 64'd0 - a__h840600 ; + assign a__h840600 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h840765 : + a___1__h840762 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h242698 = - { {48{base__h242533[15]}}, base__h242533 } << + assign addBase__h242697 = + { {48{base__h242532[15]}}, base__h242532 } << coreFix_memExe_regToExeQ$first[264:259] ; - assign addBase__h243855 = - { {48{base__h243690[15]}}, base__h243690 } << + assign addBase__h243854 = + { {48{base__h243689[15]}}, base__h243689 } << coreFix_memExe_regToExeQ$first[101:96] ; - assign addBase__h257461 = - { {48{base__h257296[15]}}, base__h257296 } << + assign addBase__h257459 = + { {48{base__h257294[15]}}, base__h257294 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h242807 = - { {50{x__h242906[15]}}, x__h242906 } << + assign addTop__h242806 = + { {50{x__h242905[15]}}, x__h242905 } << coreFix_memExe_regToExeQ$first[264:259] ; - assign addTop__h243964 = - { {50{x__h244063[15]}}, x__h244063 } << + assign addTop__h243963 = + { {50{x__h244062[15]}}, x__h244062 } << coreFix_memExe_regToExeQ$first[101:96] ; - assign addTop__h257570 = - { {50{x__h257669[15]}}, x__h257669 } << + assign addTop__h257568 = + { {50{x__h257667[15]}}, x__h257667 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addr__h149965 = + assign addr__h149964 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0] ; - assign addr__h153541 = + assign addr__h153540 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h238152 = x__h238581[63:0] + csrf_ddc_reg[149:86] ; - assign addr__h997804 = + assign addr__h238151 = x__h238580[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h997799 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign address__h1007632 = base__h1007593 + { 57'd0, x__h1007791 } ; - assign address__h1007682 = base__h1007647 + { 57'd0, x__h1007791 } ; - assign address__h1007698 = { 2'd0, address__h1007632 } ; - assign address__h1008042 = { 2'd0, base__h1007593 } ; - assign address__h1008355 = { 2'd0, address__h1007682 } ; - assign address__h1008699 = { 2'd0, base__h1007647 } ; - assign address__h1018672 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h872898 = + assign address__h1007627 = base__h1007588 + { 57'd0, x__h1007786 } ; + assign address__h1007677 = base__h1007642 + { 57'd0, x__h1007786 } ; + assign address__h1007693 = { 2'd0, address__h1007627 } ; + assign address__h1008037 = { 2'd0, base__h1007588 } ; + assign address__h1008350 = { 2'd0, address__h1007677 } ; + assign address__h1008694 = { 2'd0, base__h1007642 } ; + assign address__h1018667 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h872895 = coreFix_aluExe_1_regToExeQ$first[241:178] + 64'd4 ; - assign address__h912839 = + assign address__h912835 = coreFix_aluExe_0_regToExeQ$first[241:178] + 64'd4 ; - assign address__h963272 = + assign address__h963267 = fetchStage$pipelines_0_first[525:462] + - { {52{inc__h963271[11]}}, inc__h963271 } ; - assign address__h988140 = + { {52{inc__h963266[11]}}, inc__h963266 } ; + assign address__h988135 = fetchStage$pipelines_1_first[525:462] + - { {52{inc__h988139[11]}}, inc__h988139 } ; - assign b___1__h840766 = + { {52{inc__h988134[11]}}, inc__h988134 } ; + assign b___1__h840763 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h841217 = 64'd0 - b__h840604 ; - assign b__h840604 = + assign b___1__h841214 = 64'd0 - b__h840601 ; + assign b__h840601 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h840766 : + b___1__h840763 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h840751 = { {64{a__h840603[63]}}, a__h840603 } ; - assign b__h840827 = { {64{b__h840604[63]}}, b__h840604 } ; - assign b__h840928 = { 64'd0, a__h840603 } ; - assign b__h840940 = { 64'd0, b__h840604 } ; - assign b_base__h1003340 = + assign b__h840748 = { {64{a__h840600[63]}}, a__h840600 } ; + assign b__h840824 = { {64{b__h840601[63]}}, b__h840601 } ; + assign b__h840925 = { 64'd0, a__h840600 } ; + assign b__h840937 = { 64'd0, b__h840601 } ; + assign b_base__h1003335 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign b_base__h128524 = + assign b_base__h128523 = { coreFix_memExe_respLrScAmoQ_data_0[77:67], ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign b_base__h141668 = + assign b_base__h141667 = { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h185449 = - { x__h185142[77:67], ~x__h185142[66], x__h185142[65:64] } ; - assign b_base__h204512 = - { x__h201306[77:67], ~x__h201306[66], x__h201306[65:64] } ; - assign b_base__h219483 = + assign b_base__h185448 = + { x__h185141[77:67], ~x__h185141[66], x__h185141[65:64] } ; + assign b_base__h204511 = + { x__h201305[77:67], ~x__h201305[66], x__h201305[65:64] } ; + assign b_base__h219482 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h871857 = + assign b_base__h871854 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h872405 = + assign b_base__h872402 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h911834 = + assign b_base__h911830 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h912382 = + assign b_base__h912378 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_top__h1003339 = + assign b_top__h1003334 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign b_top__h128523 = + assign b_top__h128522 = { coreFix_memExe_respLrScAmoQ_data_0[89:81], ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign b_top__h141667 = + assign b_top__h141666 = { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h185448 = - { x__h185142[89:81], ~x__h185142[80:79], x__h185142[78] } ; - assign b_top__h204511 = - { x__h201306[89:81], ~x__h201306[80:79], x__h201306[78] } ; - assign b_top__h219482 = + assign b_top__h185447 = + { x__h185141[89:81], ~x__h185141[80:79], x__h185141[78] } ; + assign b_top__h204510 = + { x__h201305[89:81], ~x__h201305[80:79], x__h201305[78] } ; + assign b_top__h219481 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h871856 = + assign b_top__h871853 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h872404 = + assign b_top__h872401 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h911833 = + assign b_top__h911829 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h912381 = + assign b_top__h912377 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign base__h1005778 = + assign base__h1005773 = { (IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22808 == IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22810) ? 2'd0 : @@ -32662,40 +32662,40 @@ module mkCore(CLK, !IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22810) ? 2'd1 : 2'd3), - x__h1003333 } ; - assign base__h1007593 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h1007647 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign base__h242533 = + x__h1003328 } ; + assign base__h1007588 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h1007642 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign base__h242532 = { coreFix_memExe_regToExeQ$first[222:221], coreFix_memExe_regToExeQ$first[244:231] } ; - assign base__h243690 = + assign base__h243689 = { coreFix_memExe_regToExeQ$first[59:58], coreFix_memExe_regToExeQ$first[81:68] } ; - assign base__h257296 = + assign base__h257294 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign carry_out__h1003244 = - (topBits__h1003242 < x__h1003333[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h128428 = - (topBits__h128426 < x__h128517[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h141572 = - (topBits__h141570 < x__h141661[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h185353 = - (topBits__h185351 < x__h185442[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h204416 = - (topBits__h204414 < x__h204505[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h219387 = - (topBits__h219385 < x__h219476[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h871760 = - (topBits__h871758 < x__h871850[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h872308 = - (topBits__h872306 < x__h872398[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h911737 = - (topBits__h911735 < x__h911827[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h912285 = - (topBits__h912283 < x__h912375[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h1005062 = { 1'd0, i__h1003714 } ; - assign cause_interrupt__h1003522 = + assign carry_out__h1003239 = + (topBits__h1003237 < x__h1003328[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h128427 = + (topBits__h128425 < x__h128516[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h141571 = + (topBits__h141569 < x__h141660[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h185352 = + (topBits__h185350 < x__h185441[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h204415 = + (topBits__h204413 < x__h204504[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h219386 = + (topBits__h219384 < x__h219475[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h871757 = + (topBits__h871755 < x__h871847[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h872305 = + (topBits__h872303 < x__h872395[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h911733 = + (topBits__h911731 < x__h911823[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h912281 = + (topBits__h912279 < x__h912371[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h1005057 = { 1'd0, i__h1003709 } ; + assign cause_interrupt__h1003517 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2410_BITS_44_TO_43_2608_ETC___d22648 = @@ -32779,7 +32779,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19250, IF_coreFix_aluExe_0_dispToRegQ_first__8431_BIT_ETC___d19442, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h906106 : + repBound__h906102 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8431_BI_ETC___d19482 } ; assign coreFix_aluExe_0_exeToFinQ_first__0026_BITS_14_ETC___d20060 = @@ -32841,7 +32841,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d16826, IF_coreFix_aluExe_1_dispToRegQ_first__5760_BIT_ETC___d17278, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h865834 : + repBound__h865831 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5760_BI_ETC___d17344 } ; assign coreFix_aluExe_1_exeToFinQ_first__7888_BITS_14_ETC___d17923 = @@ -32959,9 +32959,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15046 | - ((f3_exp__h798055 != 8'd255 || f3_sfd__h798056 == 23'd0) && - (f3_exp__h798055 != 8'd255 || f3_sfd__h798056 != 23'd0) && - (f3_exp__h798055 != 8'd0 || f3_sfd__h798056 != 23'd0) && + ((f3_exp__h798052 != 8'd255 || f3_sfd__h798053 == 23'd0) && + (f3_exp__h798052 != 8'd255 || f3_sfd__h798053 != 23'd0) && + (f3_exp__h798052 != 8'd0 || f3_sfd__h798053 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15086) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2610_B_ETC___d15127 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32969,9 +32969,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115 | - ((f3_exp__h798055 != 8'd255 || f3_sfd__h798056 == 23'd0) && - (f3_exp__h798055 != 8'd255 || f3_sfd__h798056 != 23'd0) && - (f3_exp__h798055 != 8'd0 || f3_sfd__h798056 != 23'd0) && + ((f3_exp__h798052 != 8'd255 || f3_sfd__h798053 == 23'd0) && + (f3_exp__h798052 != 8'd255 || f3_sfd__h798053 != 23'd0) && + (f3_exp__h798052 != 8'd0 || f3_sfd__h798053 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15122) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2610_B_ETC___d15175 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32979,9 +32979,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15159 | - ((f3_exp__h798055 != 8'd255 || f3_sfd__h798056 == 23'd0) && - (f3_exp__h798055 != 8'd255 || f3_sfd__h798056 != 23'd0) && - (f3_exp__h798055 != 8'd0 || f3_sfd__h798056 != 23'd0) && + ((f3_exp__h798052 != 8'd255 || f3_sfd__h798053 == 23'd0) && + (f3_exp__h798052 != 8'd255 || f3_sfd__h798053 != 23'd0) && + (f3_exp__h798052 != 8'd0 || f3_sfd__h798053 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15170) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2610_B_ETC___d15217 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32989,9 +32989,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15203 | - ((f3_exp__h798055 != 8'd255 || f3_sfd__h798056 == 23'd0) && - (f3_exp__h798055 != 8'd255 || f3_sfd__h798056 != 23'd0) && - (f3_exp__h798055 != 8'd0 || f3_sfd__h798056 != 23'd0) && + ((f3_exp__h798052 != 8'd255 || f3_sfd__h798053 == 23'd0) && + (f3_exp__h798052 != 8'd255 || f3_sfd__h798053 != 23'd0) && + (f3_exp__h798052 != 8'd0 || f3_sfd__h798053 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15212) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2610_B_ETC___d15259 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32999,9 +32999,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15245 | - ((f3_exp__h798055 != 8'd255 || f3_sfd__h798056 == 23'd0) && - (f3_exp__h798055 != 8'd255 || f3_sfd__h798056 != 23'd0) && - (f3_exp__h798055 != 8'd0 || f3_sfd__h798056 != 23'd0) && + ((f3_exp__h798052 != 8'd255 || f3_sfd__h798053 == 23'd0) && + (f3_exp__h798052 != 8'd255 || f3_sfd__h798053 != 23'd0) && + (f3_exp__h798052 != 8'd0 || f3_sfd__h798053 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15254) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -33046,7 +33046,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5028 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h426243 ; + y__h426240 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5637 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -35252,12 +35252,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__258_BITS_334_TO__ETC___d4421 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__258_BITS_452_TO__ETC___d4408[64:63] - - { 1'd0, x__h257738 } > + { 1'd0, x__h257736 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__258_BITS_452_TO__ETC___d4408 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h257571, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h257569, 14'd0 } + - addTop__h257570 ; + addTop__h257568 ; assign coreFix_memExe_dTlb_procResp__258_BITS_490_TO__ETC___d4766 = coreFix_memExe_dTlb$procResp[490:488] == 3'd0 && NOT_coreFix_memExe_dTlb_procResp__258_BITS_560_ETC___d4582 && @@ -35308,15 +35308,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__689_BIT_10_ETC___d3587 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4251 = - { coreFix_memExe_lsq$getOrigBE << pointer__h245459[3:0], - (highOffsetBits__h245468 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h245458[3:0], + (highOffsetBits__h245467 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__652_BI_ETC___d4096 || coreFix_memExe_regToExeQ$first[264:259] >= 6'd50) && coreFix_memExe_regToExeQ$first[383], - result_d_address__h245670, - x__h250942[13:0], + result_d_address__h245669, + x__h250940[13:0], coreFix_memExe_regToExeQ$first[302:231], - repBound__h251040, + repBound__h251038, coreFix_memExe_regToExeQ_first__652_BITS_258_T_ETC___d4111, coreFix_memExe_regToExeQ_first__652_BITS_244_T_ETC___d4112, coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d4124, @@ -35337,7 +35337,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__652_BITS_101_T_ETC___d3786 = coreFix_memExe_regToExeQ$first[101:96] < 6'd51 && coreFix_memExe_regToExeQ_first__652_BITS_219_T_ETC___d3773[64:63] - - { 1'd0, x__h244132 } > + { 1'd0, x__h244131 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__652_BITS_139_T_ETC___d4071 = { coreFix_memExe_regToExeQ$first[139:124], @@ -35350,26 +35350,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__652_BIT_102_ETC___d4018[2], IF_coreFix_memExe_regToExeQ_first__652_BIT_102_ETC___d4018[1:0], coreFix_memExe_regToExeQ$first[217:154] } << - x__h247500 ; + x__h247498 ; assign coreFix_memExe_regToExeQ_first__652_BITS_219_T_ETC___d3773 = - { coreFix_memExe_regToExeQ$first[219:168] & mask__h243965, + { coreFix_memExe_regToExeQ$first[219:168] & mask__h243964, 14'd0 } + - addTop__h243964 ; + addTop__h243963 ; assign coreFix_memExe_regToExeQ_first__652_BITS_244_T_ETC___d4112 = - coreFix_memExe_regToExeQ$first[244:242] < repBound__h251040 ; + coreFix_memExe_regToExeQ$first[244:242] < repBound__h251038 ; assign coreFix_memExe_regToExeQ_first__652_BITS_258_T_ETC___d4111 = - coreFix_memExe_regToExeQ$first[258:256] < repBound__h251040 ; + coreFix_memExe_regToExeQ$first[258:256] < repBound__h251038 ; assign coreFix_memExe_regToExeQ_first__652_BITS_264_T_ETC___d3724 = coreFix_memExe_regToExeQ$first[264:259] < 6'd51 && coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d3711[64:63] - - { 1'd0, x__h242975 } > + { 1'd0, x__h242974 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d3711 = - { coreFix_memExe_regToExeQ$first[382:331] & mask__h242808, + { coreFix_memExe_regToExeQ$first[382:331] & mask__h242807, 14'd0 } + - addTop__h242807 ; + addTop__h242806 ; assign coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d4114 = - x__h250942[13:11] < repBound__h251040 ; + x__h250940[13:11] < repBound__h251038 ; assign coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d4124 = { coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d4114, (coreFix_memExe_regToExeQ_first__652_BITS_258_T_ETC___d4111 == @@ -35410,40 +35410,40 @@ module mkCore(CLK, fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__2403_BITS_469_TO_4_ETC___d23181 ; - assign cr_addrBits__h871443 = + assign cr_addrBits__h871440 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h871619[13:0] : + x__h871616[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h871991 = + assign cr_addrBits__h871988 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h872167[13:0] : + x__h872164[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h911420 = + assign cr_addrBits__h911416 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h911596[13:0] : + x__h911592[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h911968 = + assign cr_addrBits__h911964 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h912144[13:0] : + x__h912140[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h871442 = + assign cr_address__h871439 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h871990 = + assign cr_address__h871987 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h911419 = + assign cr_address__h911415 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h911967 = + assign cr_address__h911963 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h871993 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h911970 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h871994 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h911971 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h871990 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h911966 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h871991 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h911967 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__066_BITS_13_TO_11_141_ULT_c_ETC___d4145 = - csrf_ddc_reg[13:11] < repBound__h251565 ; + csrf_ddc_reg[13:11] < repBound__h251563 ; assign csrf_ddc_reg_read__066_BITS_27_TO_25_143_ULT_c_ETC___d4144 = - csrf_ddc_reg[27:25] < repBound__h251565 ; + csrf_ddc_reg[27:25] < repBound__h251563 ; assign csrf_ddc_reg_read__066_BITS_85_TO_83_146_ULT_c_ETC___d4147 = - csrf_ddc_reg[85:83] < repBound__h251565 ; + csrf_ddc_reg[85:83] < repBound__h251563 ; assign csrf_ddc_reg_read__066_BITS_85_TO_83_146_ULT_c_ETC___d4157 = { csrf_ddc_reg_read__066_BITS_85_TO_83_146_ULT_c_ETC___d4147, (csrf_ddc_reg_read__066_BITS_27_TO_25_143_ULT_c_ETC___d4144 == @@ -35500,13 +35500,13 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d22968 = - csrf_mtcc_reg[149:86] & mask__h1008361 ; + csrf_mtcc_reg[149:86] & mask__h1008356 ; assign csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d22975 = - newAddrDiff__h1008362 == mask__h1008361 ; + newAddrDiff__h1008357 == mask__h1008356 ; assign csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d23008 = - newAddrDiff__h1008706 == mask__h1008361 ; + newAddrDiff__h1008701 == mask__h1008356 ; assign csrf_mtcc_reg_read__6810_BITS_85_TO_83_2983_UL_ETC___d22986 = - csrf_mtcc_reg[85:83] < repBound__h1008513 ; + csrf_mtcc_reg[85:83] < repBound__h1008508 ; assign csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 = csrf_prv_reg_read__0367_ULE_1___d22761 && ((commitStage_commitTrap[44:43] == 2'd1) ? @@ -35515,56 +35515,56 @@ module mkCore(CLK, _0b0_CONCAT_csrf_mideleg_11_reg_read__6262_6263_ETC___d22791) ; assign csrf_prv_reg_read__0367_ULE_1___d22761 = csrf_prv_reg <= 2'd1 ; assign csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22891 = - csrf_stcc_reg[149:86] & mask__h1007704 ; + csrf_stcc_reg[149:86] & mask__h1007699 ; assign csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22900 = - newAddrDiff__h1007705 == mask__h1007704 ; + newAddrDiff__h1007700 == mask__h1007699 ; assign csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22933 = - newAddrDiff__h1008049 == mask__h1007704 ; + newAddrDiff__h1008044 == mask__h1007699 ; assign csrf_stcc_reg_read__6801_BITS_85_TO_83_2908_UL_ETC___d22911 = - csrf_stcc_reg[85:83] < repBound__h1007856 ; - assign data09423_BITS_31_TO_0__q21 = data__h709423[31:0] ; - assign data10369_BITS_31_TO_0__q26 = data__h710369[31:0] ; - assign data___1__h709961 = - { {32{data09423_BITS_31_TO_0__q21[31]}}, - data09423_BITS_31_TO_0__q21 } ; - assign data___1__h710907 = - { {32{data10369_BITS_31_TO_0__q26[31]}}, - data10369_BITS_31_TO_0__q26 } ; - assign data__h572031 = + csrf_stcc_reg[85:83] < repBound__h1007851 ; + assign data09420_BITS_31_TO_0__q21 = data__h709420[31:0] ; + assign data10366_BITS_31_TO_0__q26 = data__h710366[31:0] ; + assign data___1__h709958 = + { {32{data09420_BITS_31_TO_0__q21[31]}}, + data09420_BITS_31_TO_0__q21 } ; + assign data___1__h710904 = + { {32{data10366_BITS_31_TO_0__q26[31]}}, + data10366_BITS_31_TO_0__q26 } ; + assign data__h572028 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h572594 : - res_data__h572589 ; - assign data__h617791 = + res_data__h572591 : + res_data__h572586 ; + assign data__h617788 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h618348 : - res_data__h618343 ; - assign data__h663538 = + res_data__h618345 : + res_data__h618340 ; + assign data__h663535 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h664095 : - res_data__h664090 ; - assign data__h709423 = + res_data__h664092 : + res_data__h664087 ; + assign data__h709420 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h709454 = + assign data__h709451 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h709961 : - data__h709423 ; - assign data__h710369 = + data___1__h709958 : + data__h709420 ; + assign data__h710366 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h710171 : - x_remainder__h710172 ; - assign data__h710400 = + x_quotient__h710168 : + x_remainder__h710169 ; + assign data__h710397 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h710907 : - data__h710369 ; - assign data_addrBits__h1025080 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1025934 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1025079 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1025933 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h1002568 = + data___1__h710904 : + data__h710366 ; + assign data_addrBits__h1025074 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1025928 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1025073 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1025927 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h1002563 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -35583,59 +35583,59 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h615949 = _theResult___fst_exp__h588916 + 8'd1 ; - assign din_inc___2_exp__h615973 = _theResult___fst_exp__h597572 + 8'd1 ; - assign din_inc___2_exp__h616003 = _theResult___fst_exp__h606682 + 8'd1 ; - assign din_inc___2_exp__h616027 = _theResult___fst_exp__h615367 + 8'd1 ; - assign din_inc___2_exp__h661698 = _theResult___fst_exp__h634665 + 8'd1 ; - assign din_inc___2_exp__h661722 = _theResult___fst_exp__h643321 + 8'd1 ; - assign din_inc___2_exp__h661752 = _theResult___fst_exp__h652431 + 8'd1 ; - assign din_inc___2_exp__h661776 = _theResult___fst_exp__h661116 + 8'd1 ; - assign din_inc___2_exp__h707445 = _theResult___fst_exp__h680412 + 8'd1 ; - assign din_inc___2_exp__h707469 = _theResult___fst_exp__h689068 + 8'd1 ; - assign din_inc___2_exp__h707499 = _theResult___fst_exp__h698178 + 8'd1 ; - assign din_inc___2_exp__h707523 = _theResult___fst_exp__h706863 + 8'd1 ; - assign din_inc___2_exp__h758395 = _theResult___fst_exp__h739145 + 11'd1 ; - assign din_inc___2_exp__h758430 = _theResult___fst_exp__h748722 + 11'd1 ; - assign din_inc___2_exp__h758456 = _theResult___fst_exp__h757555 + 11'd1 ; - assign din_inc___2_exp__h797248 = _theResult___fst_exp__h777998 + 11'd1 ; - assign din_inc___2_exp__h797283 = _theResult___fst_exp__h787575 + 11'd1 ; - assign din_inc___2_exp__h797309 = _theResult___fst_exp__h796408 + 11'd1 ; - assign din_inc___2_exp__h836552 = _theResult___fst_exp__h817302 + 11'd1 ; - assign din_inc___2_exp__h836587 = _theResult___fst_exp__h826879 + 11'd1 ; - assign din_inc___2_exp__h836613 = _theResult___fst_exp__h835712 + 11'd1 ; - assign enabled_ints___1__h927273 = pend_ints__h926746 & y__h927285 ; - assign enabled_ints__h927319 = - pend_ints__h926746 & - { r1__read_BITS_13_TO_0___h927295, csrf_mideleg_1_0_reg } ; - assign f1_exp19757_MINUS_127__q147 = f1_exp__h719757 - 8'd127 ; - assign f1_exp__h719757 = + assign din_inc___2_exp__h615946 = _theResult___fst_exp__h588913 + 8'd1 ; + assign din_inc___2_exp__h615970 = _theResult___fst_exp__h597569 + 8'd1 ; + assign din_inc___2_exp__h616000 = _theResult___fst_exp__h606679 + 8'd1 ; + assign din_inc___2_exp__h616024 = _theResult___fst_exp__h615364 + 8'd1 ; + assign din_inc___2_exp__h661695 = _theResult___fst_exp__h634662 + 8'd1 ; + assign din_inc___2_exp__h661719 = _theResult___fst_exp__h643318 + 8'd1 ; + assign din_inc___2_exp__h661749 = _theResult___fst_exp__h652428 + 8'd1 ; + assign din_inc___2_exp__h661773 = _theResult___fst_exp__h661113 + 8'd1 ; + assign din_inc___2_exp__h707442 = _theResult___fst_exp__h680409 + 8'd1 ; + assign din_inc___2_exp__h707466 = _theResult___fst_exp__h689065 + 8'd1 ; + assign din_inc___2_exp__h707496 = _theResult___fst_exp__h698175 + 8'd1 ; + assign din_inc___2_exp__h707520 = _theResult___fst_exp__h706860 + 8'd1 ; + assign din_inc___2_exp__h758392 = _theResult___fst_exp__h739142 + 11'd1 ; + assign din_inc___2_exp__h758427 = _theResult___fst_exp__h748719 + 11'd1 ; + assign din_inc___2_exp__h758453 = _theResult___fst_exp__h757552 + 11'd1 ; + assign din_inc___2_exp__h797245 = _theResult___fst_exp__h777995 + 11'd1 ; + assign din_inc___2_exp__h797280 = _theResult___fst_exp__h787572 + 11'd1 ; + assign din_inc___2_exp__h797306 = _theResult___fst_exp__h796405 + 11'd1 ; + assign din_inc___2_exp__h836549 = _theResult___fst_exp__h817299 + 11'd1 ; + assign din_inc___2_exp__h836584 = _theResult___fst_exp__h826876 + 11'd1 ; + assign din_inc___2_exp__h836610 = _theResult___fst_exp__h835709 + 11'd1 ; + assign enabled_ints___1__h927268 = pend_ints__h926741 & y__h927280 ; + assign enabled_ints__h927314 = + pend_ints__h926741 & + { r1__read_BITS_13_TO_0___h927290, csrf_mideleg_1_0_reg } ; + assign f1_exp19754_MINUS_127__q147 = f1_exp__h719754 - 8'd127 ; + assign f1_exp__h719754 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h719758 = + assign f1_sfd__h719755 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp58751_MINUS_127__q187 = f2_exp__h758751 - 8'd127 ; - assign f2_exp__h758751 = + assign f2_exp58748_MINUS_127__q187 = f2_exp__h758748 - 8'd127 ; + assign f2_exp__h758748 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h758752 = + assign f2_sfd__h758749 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp98055_MINUS_127__q164 = f3_exp__h798055 - 8'd127 ; - assign f3_exp__h798055 = + assign f3_exp98052_MINUS_127__q164 = f3_exp__h798052 - 8'd127 ; + assign f3_exp__h798052 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h798056 = + assign f3_sfd__h798053 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; @@ -35645,11 +35645,11 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fallthrough_pc__h946297 = - { fetchStage$pipelines_0_first[590:526], address__h963272 } ; - assign fallthrough_pc__h970681 = - { fetchStage$pipelines_1_first[590:526], address__h988140 } ; - assign fcsr_csr__read__h855486 = { 56'd0, x__h859104 } ; + assign fallthrough_pc__h946292 = + { fetchStage$pipelines_0_first[590:526], address__h963267 } ; + assign fallthrough_pc__h970676 = + { fetchStage$pipelines_1_first[590:526], address__h988135 } ; + assign fcsr_csr__read__h855483 = { 56'd0, x__h859101 } ; assign fetchStage_RDY_pipelines_0_first__0334_AND_fet_ETC___d21335 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[267:265] == 3'd1 && @@ -35912,83 +35912,83 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0346_BIT_180_152_ETC___d21623 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q258 } ; - assign fflags__h1022678 = + assign fflags__h1022673 = NOT_rob_deqPort_0_canDeq__3556_3557_OR_rob_deq_ETC___d23781 ? - y_avValue_snd_fst__h1022738 : + y_avValue_snd_fst__h1022733 : IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23788 ; - assign fflags_csr__read__h855461 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h855472 = { 61'd0, csrf_frm_reg } ; - assign guard__h580815 = - { IF_sfdin88910_BIT_33_THEN_2_ELSE_0__q41[1], - { sfdin__h588910[32:0], 23'd0 } != 56'd0 } ; - assign guard__h589524 = - { IF_theResult___snd97523_BIT_33_THEN_2_ELSE_0__q43[1], - { _theResult___snd__h597523[32:0], 23'd0 } != 56'd0 } ; - assign guard__h598454 = - { IF_sfdin06676_BIT_33_THEN_2_ELSE_0__q51[1], - { sfdin__h606676[32:0], 23'd0 } != 56'd0 } ; - assign guard__h599052 = x__h599154 != 57'd0 ; - assign guard__h607290 = - { IF_theResult___snd15313_BIT_33_THEN_2_ELSE_0__q56[1], - { _theResult___snd__h615313[32:0], 23'd0 } != 56'd0 } ; - assign guard__h626566 = - { IF_sfdin34659_BIT_33_THEN_2_ELSE_0__q76[1], - { sfdin__h634659[32:0], 23'd0 } != 56'd0 } ; - assign guard__h635273 = - { IF_theResult___snd43272_BIT_33_THEN_2_ELSE_0__q78[1], - { _theResult___snd__h643272[32:0], 23'd0 } != 56'd0 } ; - assign guard__h644203 = - { IF_sfdin52425_BIT_33_THEN_2_ELSE_0__q86[1], - { sfdin__h652425[32:0], 23'd0 } != 56'd0 } ; - assign guard__h644801 = x__h644903 != 57'd0 ; - assign guard__h653039 = - { IF_theResult___snd61062_BIT_33_THEN_2_ELSE_0__q91[1], - { _theResult___snd__h661062[32:0], 23'd0 } != 56'd0 } ; - assign guard__h672313 = - { IF_sfdin80406_BIT_33_THEN_2_ELSE_0__q111[1], - { sfdin__h680406[32:0], 23'd0 } != 56'd0 } ; - assign guard__h681020 = - { IF_theResult___snd89019_BIT_33_THEN_2_ELSE_0__q113[1], - { _theResult___snd__h689019[32:0], 23'd0 } != 56'd0 } ; - assign guard__h689950 = - { IF_sfdin98172_BIT_33_THEN_2_ELSE_0__q121[1], - { sfdin__h698172[32:0], 23'd0 } != 56'd0 } ; - assign guard__h690548 = x__h690650 != 57'd0 ; - assign guard__h698786 = - { IF_theResult___snd06809_BIT_33_THEN_2_ELSE_0__q126[1], - { _theResult___snd__h706809[32:0], 23'd0 } != 56'd0 } ; - assign guard__h731184 = - { IF_theResult___snd39096_BIT_4_THEN_2_ELSE_0__q146[1], - { _theResult___snd__h739096[3:0], 52'd0 } != 56'd0 } ; - assign guard__h740496 = - { IF_sfdin48716_BIT_4_THEN_2_ELSE_0__q150[1], - { sfdin__h748716[3:0], 52'd0 } != 56'd0 } ; - assign guard__h741094 = x__h741194 != 57'd0 ; - assign guard__h749565 = - { IF_theResult___snd57501_BIT_4_THEN_2_ELSE_0__q153[1], - { _theResult___snd__h757501[3:0], 52'd0 } != 56'd0 } ; - assign guard__h770037 = - { IF_theResult___snd77949_BIT_4_THEN_2_ELSE_0__q186[1], - { _theResult___snd__h777949[3:0], 52'd0 } != 56'd0 } ; - assign guard__h779349 = - { IF_sfdin87569_BIT_4_THEN_2_ELSE_0__q190[1], - { sfdin__h787569[3:0], 52'd0 } != 56'd0 } ; - assign guard__h779947 = x__h780047 != 57'd0 ; - assign guard__h788418 = - { IF_theResult___snd96354_BIT_4_THEN_2_ELSE_0__q193[1], - { _theResult___snd__h796354[3:0], 52'd0 } != 56'd0 } ; - assign guard__h809341 = - { IF_theResult___snd17253_BIT_4_THEN_2_ELSE_0__q163[1], - { _theResult___snd__h817253[3:0], 52'd0 } != 56'd0 } ; - assign guard__h818653 = - { IF_sfdin26873_BIT_4_THEN_2_ELSE_0__q167[1], - { sfdin__h826873[3:0], 52'd0 } != 56'd0 } ; - assign guard__h819251 = x__h819351 != 57'd0 ; - assign guard__h827722 = - { IF_theResult___snd35658_BIT_4_THEN_2_ELSE_0__q170[1], - { _theResult___snd__h835658[3:0], 52'd0 } != 56'd0 } ; - assign highOffsetBits__h245468 = x__h245495 & mask__h242699 ; - assign idx__h976269 = + assign fflags_csr__read__h855458 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h855469 = { 61'd0, csrf_frm_reg } ; + assign guard__h580812 = + { IF_sfdin88907_BIT_33_THEN_2_ELSE_0__q41[1], + { sfdin__h588907[32:0], 23'd0 } != 56'd0 } ; + assign guard__h589521 = + { IF_theResult___snd97520_BIT_33_THEN_2_ELSE_0__q43[1], + { _theResult___snd__h597520[32:0], 23'd0 } != 56'd0 } ; + assign guard__h598451 = + { IF_sfdin06673_BIT_33_THEN_2_ELSE_0__q51[1], + { sfdin__h606673[32:0], 23'd0 } != 56'd0 } ; + assign guard__h599049 = x__h599151 != 57'd0 ; + assign guard__h607287 = + { IF_theResult___snd15310_BIT_33_THEN_2_ELSE_0__q56[1], + { _theResult___snd__h615310[32:0], 23'd0 } != 56'd0 } ; + assign guard__h626563 = + { IF_sfdin34656_BIT_33_THEN_2_ELSE_0__q76[1], + { sfdin__h634656[32:0], 23'd0 } != 56'd0 } ; + assign guard__h635270 = + { IF_theResult___snd43269_BIT_33_THEN_2_ELSE_0__q78[1], + { _theResult___snd__h643269[32:0], 23'd0 } != 56'd0 } ; + assign guard__h644200 = + { IF_sfdin52422_BIT_33_THEN_2_ELSE_0__q86[1], + { sfdin__h652422[32:0], 23'd0 } != 56'd0 } ; + assign guard__h644798 = x__h644900 != 57'd0 ; + assign guard__h653036 = + { IF_theResult___snd61059_BIT_33_THEN_2_ELSE_0__q91[1], + { _theResult___snd__h661059[32:0], 23'd0 } != 56'd0 } ; + assign guard__h672310 = + { IF_sfdin80403_BIT_33_THEN_2_ELSE_0__q111[1], + { sfdin__h680403[32:0], 23'd0 } != 56'd0 } ; + assign guard__h681017 = + { IF_theResult___snd89016_BIT_33_THEN_2_ELSE_0__q113[1], + { _theResult___snd__h689016[32:0], 23'd0 } != 56'd0 } ; + assign guard__h689947 = + { IF_sfdin98169_BIT_33_THEN_2_ELSE_0__q121[1], + { sfdin__h698169[32:0], 23'd0 } != 56'd0 } ; + assign guard__h690545 = x__h690647 != 57'd0 ; + assign guard__h698783 = + { IF_theResult___snd06806_BIT_33_THEN_2_ELSE_0__q126[1], + { _theResult___snd__h706806[32:0], 23'd0 } != 56'd0 } ; + assign guard__h731181 = + { IF_theResult___snd39093_BIT_4_THEN_2_ELSE_0__q146[1], + { _theResult___snd__h739093[3:0], 52'd0 } != 56'd0 } ; + assign guard__h740493 = + { IF_sfdin48713_BIT_4_THEN_2_ELSE_0__q150[1], + { sfdin__h748713[3:0], 52'd0 } != 56'd0 } ; + assign guard__h741091 = x__h741191 != 57'd0 ; + assign guard__h749562 = + { IF_theResult___snd57498_BIT_4_THEN_2_ELSE_0__q153[1], + { _theResult___snd__h757498[3:0], 52'd0 } != 56'd0 } ; + assign guard__h770034 = + { IF_theResult___snd77946_BIT_4_THEN_2_ELSE_0__q186[1], + { _theResult___snd__h777946[3:0], 52'd0 } != 56'd0 } ; + assign guard__h779346 = + { IF_sfdin87566_BIT_4_THEN_2_ELSE_0__q190[1], + { sfdin__h787566[3:0], 52'd0 } != 56'd0 } ; + assign guard__h779944 = x__h780044 != 57'd0 ; + assign guard__h788415 = + { IF_theResult___snd96351_BIT_4_THEN_2_ELSE_0__q193[1], + { _theResult___snd__h796351[3:0], 52'd0 } != 56'd0 } ; + assign guard__h809338 = + { IF_theResult___snd17250_BIT_4_THEN_2_ELSE_0__q163[1], + { _theResult___snd__h817250[3:0], 52'd0 } != 56'd0 } ; + assign guard__h818650 = + { IF_sfdin26870_BIT_4_THEN_2_ELSE_0__q167[1], + { sfdin__h826870[3:0], 52'd0 } != 56'd0 } ; + assign guard__h819248 = x__h819348 != 57'd0 ; + assign guard__h827719 = + { IF_theResult___snd35655_BIT_4_THEN_2_ELSE_0__q170[1], + { _theResult___snd__h835655[3:0], 52'd0 } != 56'd0 } ; + assign highOffsetBits__h245467 = x__h245494 & mask__h242698 ; + assign idx__h976264 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0337_BITS_26_ETC___d21722 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -35996,86 +35996,86 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0337_BITS_267_TO_ETC___d21745) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1278__ETC___d21280 ; - assign impliedTopBits__h1003246 = x__h1003330 + len_correction__h1003245 ; - assign impliedTopBits__h128430 = x__h128514 + len_correction__h128429 ; - assign impliedTopBits__h141574 = x__h141658 + len_correction__h141573 ; - assign impliedTopBits__h185355 = x__h185439 + len_correction__h185354 ; - assign impliedTopBits__h204418 = x__h204502 + len_correction__h204417 ; - assign impliedTopBits__h219389 = x__h219473 + len_correction__h219388 ; - assign impliedTopBits__h871762 = x__h871847 + len_correction__h871761 ; - assign impliedTopBits__h872310 = x__h872395 + len_correction__h872309 ; - assign impliedTopBits__h911739 = x__h911824 + len_correction__h911738 ; - assign impliedTopBits__h912287 = x__h912372 + len_correction__h912286 ; - assign in__h1005860 = pc_address__h1002943 & y__h1005877 ; - assign in__h242638 = coreFix_memExe_regToExeQ$first[382:317] & y__h242655 ; - assign in__h243795 = coreFix_memExe_regToExeQ$first[219:154] & y__h243812 ; - assign in__h257401 = coreFix_memExe_dTlb$procResp[452:387] & y__h257418 ; - assign inc__h963271 = + assign impliedTopBits__h1003241 = x__h1003325 + len_correction__h1003240 ; + assign impliedTopBits__h128429 = x__h128513 + len_correction__h128428 ; + assign impliedTopBits__h141573 = x__h141657 + len_correction__h141572 ; + assign impliedTopBits__h185354 = x__h185438 + len_correction__h185353 ; + assign impliedTopBits__h204417 = x__h204501 + len_correction__h204416 ; + assign impliedTopBits__h219388 = x__h219472 + len_correction__h219387 ; + assign impliedTopBits__h871759 = x__h871844 + len_correction__h871758 ; + assign impliedTopBits__h872307 = x__h872392 + len_correction__h872306 ; + assign impliedTopBits__h911735 = x__h911820 + len_correction__h911734 ; + assign impliedTopBits__h912283 = x__h912368 + len_correction__h912282 ; + assign in__h1005855 = pc_address__h1002938 & y__h1005872 ; + assign in__h242637 = coreFix_memExe_regToExeQ$first[382:317] & y__h242654 ; + assign in__h243794 = coreFix_memExe_regToExeQ$first[219:154] & y__h243811 ; + assign in__h257399 = coreFix_memExe_dTlb$procResp[452:387] & y__h257416 ; + assign inc__h963266 = (fetchStage$pipelines_0_first[98:97] == 2'b11) ? 12'd4 : 12'd2 ; - assign inc__h988139 = + assign inc__h988134 = (fetchStage$pipelines_1_first[98:97] == 2'b11) ? 12'd4 : 12'd2 ; - assign k__h951774 = + assign k__h951769 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1278__ETC___d21280 ; - assign len_correction__h1003245 = + assign len_correction__h1003240 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? 2'b01 : 2'b0 ; - assign len_correction__h128429 = + assign len_correction__h128428 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? 2'b01 : 2'b0 ; - assign len_correction__h141573 = + assign len_correction__h141572 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h185354 = - INV_x85142_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; - assign len_correction__h204417 = - INV_x01306_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; - assign len_correction__h219388 = + assign len_correction__h185353 = + INV_x85141_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; + assign len_correction__h204416 = + INV_x01305_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; + assign len_correction__h219387 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h871761 = + assign len_correction__h871758 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h872309 = + assign len_correction__h872306 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h911738 = + assign len_correction__h911734 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h912286 = + assign len_correction__h912282 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign mask__h1007704 = 64'hFFFFFFFFFFFFFFFF << x__h1007765 ; - assign mask__h1008361 = 64'hFFFFFFFFFFFFFFFF << x__h1008422 ; - assign mask__h242699 = + assign mask__h1007699 = 64'hFFFFFFFFFFFFFFFF << x__h1007760 ; + assign mask__h1008356 = 64'hFFFFFFFFFFFFFFFF << x__h1008417 ; + assign mask__h242698 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign mask__h242808 = + assign mask__h242807 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign mask__h243856 = + assign mask__h243855 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign mask__h243965 = + assign mask__h243964 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign mask__h257462 = + assign mask__h257460 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h257571 = + assign mask__h257569 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mcause_csr__read__h856902 = - { r1__read__h860556, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h856723 = - { r1__read__h860544, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h856403 = - { r1__read__h860410, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h856501 = - { r1__read__h860427, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h856628 = { r1__read__h860451, 1'b0 } ; - assign mip_csr__read__h857141 = { r1__read__h860563, 1'b0 } ; + assign mcause_csr__read__h856899 = + { r1__read__h860553, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h856720 = + { r1__read__h860541, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h856400 = + { r1__read__h860407, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h856498 = + { r1__read__h860424, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h856625 = { r1__read__h860448, 1'b0 } ; + assign mip_csr__read__h857138 = { r1__read__h860560, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20749 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -36117,28 +36117,28 @@ module mkCore(CLK, fetchStage$pipelines_0_first[272:268] != 5'd24 && fetchStage$pipelines_0_first[272:268] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h856249 = { r1__read__h860285, csrf_ie_vec_0 } ; - assign n__read__h1020084 = + assign mstatus_csr__read__h856246 = { r1__read__h860282, csrf_ie_vec_0 } ; + assign n__read__h1020079 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1020160 : + upd__h1020155 : csrf_minstret_ehr_data_rl ; assign n__read__h7877 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7946 : csrf_mcycle_ehr_data_rl ; - assign newAddrDiff__h1007705 = + assign newAddrDiff__h1007700 = csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22891 - - (address__h1007632 & mask__h1007704) ; - assign newAddrDiff__h1008049 = + (address__h1007627 & mask__h1007699) ; + assign newAddrDiff__h1008044 = csrf_stcc_reg_read__6801_BITS_149_TO_86_2888_A_ETC___d22891 - - (base__h1007593 & mask__h1007704) ; - assign newAddrDiff__h1008362 = + (base__h1007588 & mask__h1007699) ; + assign newAddrDiff__h1008357 = csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d22968 - - (address__h1007682 & mask__h1008361) ; - assign newAddrDiff__h1008706 = + (address__h1007677 & mask__h1008356) ; + assign newAddrDiff__h1008701 = csrf_mtcc_reg_read__6810_BITS_149_TO_86_2965_A_ETC___d22968 - - (base__h1007647 & mask__h1008361) ; - assign new_pc__h879225 = + (base__h1007642 & mask__h1008356) ; + assign new_pc__h879221 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -36150,7 +36150,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7888_BIT__ETC___d18056[2], IF_coreFix_aluExe_1_exeToFinQ_first__7888_BIT__ETC___d18056[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h918535 = + assign new_pc__h918530 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -36162,266 +36162,266 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__0026_BIT__ETC___d20193[2], IF_coreFix_aluExe_0_exeToFinQ_first__0026_BIT__ETC___d20193[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h519965 = + assign next_deqP___1__h519961 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h530742 = + assign next_deqP___1__h530738 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h538020 = + assign next_deqP___1__h538016 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h548655 = + assign next_deqP___1__h548651 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h562303 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h566082 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1018619 = + assign next_deqP___1__h562299 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h566078 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1018614 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1018672 } ; - assign offset__h1005779 = { 2'd0, pc_addrBits__h1002944 } - base__h1005778 ; - assign offset__h242534 = + { rob$deqPort_0_deq_data[630:566], address__h1018667 } ; + assign offset__h1005774 = { 2'd0, pc_addrBits__h1002939 } - base__h1005773 ; + assign offset__h242533 = { 2'd0, coreFix_memExe_regToExeQ$first[316:303] } - - base__h242533 ; - assign offset__h243691 = + base__h242532 ; + assign offset__h243690 = { 2'd0, coreFix_memExe_regToExeQ$first[153:140] } - - base__h243690 ; - assign offset__h245449 = + base__h243689 ; + assign offset__h245448 = { {32{coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16[31]}}, coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16 } ; - assign offset__h257297 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h257296 ; - assign out___1_sfd__h719821 = { f1_sfd__h719758, 29'd0 } ; - assign out___1_sfd__h758815 = { f2_sfd__h758752, 29'd0 } ; - assign out___1_sfd__h798119 = { f3_sfd__h798056, 29'd0 } ; - assign out_exp__h589435 = - sfdin__h588910[34] ? - _theResult___exp__h589432 : - _theResult___fst_exp__h588916 ; - assign out_exp__h598017 = - _theResult___snd__h597523[34] ? - _theResult___exp__h598014 : - _theResult___fst_exp__h597572 ; - assign out_exp__h607201 = - sfdin__h606676[34] ? - _theResult___exp__h607198 : - _theResult___fst_exp__h606682 ; - assign out_exp__h615837 = - _theResult___snd__h615313[34] ? - _theResult___exp__h615834 : - _theResult___fst_exp__h615367 ; - assign out_exp__h635184 = - sfdin__h634659[34] ? - _theResult___exp__h635181 : - _theResult___fst_exp__h634665 ; - assign out_exp__h643766 = - _theResult___snd__h643272[34] ? - _theResult___exp__h643763 : - _theResult___fst_exp__h643321 ; - assign out_exp__h652950 = - sfdin__h652425[34] ? - _theResult___exp__h652947 : - _theResult___fst_exp__h652431 ; - assign out_exp__h661586 = - _theResult___snd__h661062[34] ? - _theResult___exp__h661583 : - _theResult___fst_exp__h661116 ; - assign out_exp__h680931 = - sfdin__h680406[34] ? - _theResult___exp__h680928 : - _theResult___fst_exp__h680412 ; - assign out_exp__h689513 = - _theResult___snd__h689019[34] ? - _theResult___exp__h689510 : - _theResult___fst_exp__h689068 ; - assign out_exp__h698697 = - sfdin__h698172[34] ? - _theResult___exp__h698694 : - _theResult___fst_exp__h698178 ; - assign out_exp__h707333 = - _theResult___snd__h706809[34] ? - _theResult___exp__h707330 : - _theResult___fst_exp__h706863 ; - assign out_exp__h739803 = - _theResult___snd__h739096[5] ? - _theResult___exp__h739800 : - _theResult___fst_exp__h739145 ; - assign out_exp__h749454 = - sfdin__h748716[5] ? - _theResult___exp__h749451 : - _theResult___fst_exp__h748722 ; - assign out_exp__h758238 = - _theResult___snd__h757501[5] ? - _theResult___exp__h758235 : - _theResult___fst_exp__h757555 ; - assign out_exp__h778656 = - _theResult___snd__h777949[5] ? - _theResult___exp__h778653 : - _theResult___fst_exp__h777998 ; - assign out_exp__h788307 = - sfdin__h787569[5] ? - _theResult___exp__h788304 : - _theResult___fst_exp__h787575 ; - assign out_exp__h797091 = - _theResult___snd__h796354[5] ? - _theResult___exp__h797088 : - _theResult___fst_exp__h796408 ; - assign out_exp__h817960 = - _theResult___snd__h817253[5] ? - _theResult___exp__h817957 : - _theResult___fst_exp__h817302 ; - assign out_exp__h827611 = - sfdin__h826873[5] ? - _theResult___exp__h827608 : - _theResult___fst_exp__h826879 ; - assign out_exp__h836395 = - _theResult___snd__h835658[5] ? - _theResult___exp__h836392 : - _theResult___fst_exp__h835712 ; - assign out_f_exp__h616213 = - (_theResult___exp__h615936 == 8'd255 && - _theResult___sfd__h615937 != 23'd0 || + assign offset__h257295 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h257294 ; + assign out___1_sfd__h719818 = { f1_sfd__h719755, 29'd0 } ; + assign out___1_sfd__h758812 = { f2_sfd__h758749, 29'd0 } ; + assign out___1_sfd__h798116 = { f3_sfd__h798053, 29'd0 } ; + assign out_exp__h589432 = + sfdin__h588907[34] ? + _theResult___exp__h589429 : + _theResult___fst_exp__h588913 ; + assign out_exp__h598014 = + _theResult___snd__h597520[34] ? + _theResult___exp__h598011 : + _theResult___fst_exp__h597569 ; + assign out_exp__h607198 = + sfdin__h606673[34] ? + _theResult___exp__h607195 : + _theResult___fst_exp__h606679 ; + assign out_exp__h615834 = + _theResult___snd__h615310[34] ? + _theResult___exp__h615831 : + _theResult___fst_exp__h615364 ; + assign out_exp__h635181 = + sfdin__h634656[34] ? + _theResult___exp__h635178 : + _theResult___fst_exp__h634662 ; + assign out_exp__h643763 = + _theResult___snd__h643269[34] ? + _theResult___exp__h643760 : + _theResult___fst_exp__h643318 ; + assign out_exp__h652947 = + sfdin__h652422[34] ? + _theResult___exp__h652944 : + _theResult___fst_exp__h652428 ; + assign out_exp__h661583 = + _theResult___snd__h661059[34] ? + _theResult___exp__h661580 : + _theResult___fst_exp__h661113 ; + assign out_exp__h680928 = + sfdin__h680403[34] ? + _theResult___exp__h680925 : + _theResult___fst_exp__h680409 ; + assign out_exp__h689510 = + _theResult___snd__h689016[34] ? + _theResult___exp__h689507 : + _theResult___fst_exp__h689065 ; + assign out_exp__h698694 = + sfdin__h698169[34] ? + _theResult___exp__h698691 : + _theResult___fst_exp__h698175 ; + assign out_exp__h707330 = + _theResult___snd__h706806[34] ? + _theResult___exp__h707327 : + _theResult___fst_exp__h706860 ; + assign out_exp__h739800 = + _theResult___snd__h739093[5] ? + _theResult___exp__h739797 : + _theResult___fst_exp__h739142 ; + assign out_exp__h749451 = + sfdin__h748713[5] ? + _theResult___exp__h749448 : + _theResult___fst_exp__h748719 ; + assign out_exp__h758235 = + _theResult___snd__h757498[5] ? + _theResult___exp__h758232 : + _theResult___fst_exp__h757552 ; + assign out_exp__h778653 = + _theResult___snd__h777946[5] ? + _theResult___exp__h778650 : + _theResult___fst_exp__h777995 ; + assign out_exp__h788304 = + sfdin__h787566[5] ? + _theResult___exp__h788301 : + _theResult___fst_exp__h787572 ; + assign out_exp__h797088 = + _theResult___snd__h796351[5] ? + _theResult___exp__h797085 : + _theResult___fst_exp__h796405 ; + assign out_exp__h817957 = + _theResult___snd__h817250[5] ? + _theResult___exp__h817954 : + _theResult___fst_exp__h817299 ; + assign out_exp__h827608 = + sfdin__h826870[5] ? + _theResult___exp__h827605 : + _theResult___fst_exp__h826876 ; + assign out_exp__h836392 = + _theResult___snd__h835655[5] ? + _theResult___exp__h836389 : + _theResult___fst_exp__h835709 ; + assign out_f_exp__h616210 = + (_theResult___exp__h615933 == 8'd255 && + _theResult___sfd__h615934 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h615927 ; - assign out_f_exp__h661962 = - (_theResult___exp__h661685 == 8'd255 && - _theResult___sfd__h661686 != 23'd0 || + _theResult___fst_exp__h615924 ; + assign out_f_exp__h661959 = + (_theResult___exp__h661682 == 8'd255 && + _theResult___sfd__h661683 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h661676 ; - assign out_f_exp__h707709 = - (_theResult___exp__h707432 == 8'd255 && - _theResult___sfd__h707433 != 23'd0 || + _theResult___fst_exp__h661673 ; + assign out_f_exp__h707706 = + (_theResult___exp__h707429 == 8'd255 && + _theResult___sfd__h707430 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h707423 ; - assign out_f_sfd__h616214 = - (_theResult___exp__h615936 == 8'd255 && - _theResult___sfd__h615937 != 23'd0) ? + _theResult___fst_exp__h707420 ; + assign out_f_sfd__h616211 = + (_theResult___exp__h615933 == 8'd255 && + _theResult___sfd__h615934 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h615937 ; - assign out_f_sfd__h661963 = - (_theResult___exp__h661685 == 8'd255 && - _theResult___sfd__h661686 != 23'd0) ? + _theResult___sfd__h615934 ; + assign out_f_sfd__h661960 = + (_theResult___exp__h661682 == 8'd255 && + _theResult___sfd__h661683 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h661686 ; - assign out_f_sfd__h707710 = - (_theResult___exp__h707432 == 8'd255 && - _theResult___sfd__h707433 != 23'd0) ? + _theResult___sfd__h661683 ; + assign out_f_sfd__h707707 = + (_theResult___exp__h707429 == 8'd255 && + _theResult___sfd__h707430 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h707433 ; - assign out_sfd__h589436 = - sfdin__h588910[34] ? - _theResult___sfd__h589433 : - sfdin__h588910[56:34] ; - assign out_sfd__h598018 = - _theResult___snd__h597523[34] ? - _theResult___sfd__h598015 : - _theResult___snd__h597523[56:34] ; - assign out_sfd__h607202 = - sfdin__h606676[34] ? - _theResult___sfd__h607199 : - sfdin__h606676[56:34] ; - assign out_sfd__h615838 = - _theResult___snd__h615313[34] ? - _theResult___sfd__h615835 : - _theResult___snd__h615313[56:34] ; - assign out_sfd__h635185 = - sfdin__h634659[34] ? - _theResult___sfd__h635182 : - sfdin__h634659[56:34] ; - assign out_sfd__h643767 = - _theResult___snd__h643272[34] ? - _theResult___sfd__h643764 : - _theResult___snd__h643272[56:34] ; - assign out_sfd__h652951 = - sfdin__h652425[34] ? - _theResult___sfd__h652948 : - sfdin__h652425[56:34] ; - assign out_sfd__h661587 = - _theResult___snd__h661062[34] ? - _theResult___sfd__h661584 : - _theResult___snd__h661062[56:34] ; - assign out_sfd__h680932 = - sfdin__h680406[34] ? - _theResult___sfd__h680929 : - sfdin__h680406[56:34] ; - assign out_sfd__h689514 = - _theResult___snd__h689019[34] ? - _theResult___sfd__h689511 : - _theResult___snd__h689019[56:34] ; - assign out_sfd__h698698 = - sfdin__h698172[34] ? - _theResult___sfd__h698695 : - sfdin__h698172[56:34] ; - assign out_sfd__h707334 = - _theResult___snd__h706809[34] ? - _theResult___sfd__h707331 : - _theResult___snd__h706809[56:34] ; - assign out_sfd__h739804 = - _theResult___snd__h739096[5] ? - _theResult___sfd__h739801 : - _theResult___snd__h739096[56:5] ; - assign out_sfd__h749455 = - sfdin__h748716[5] ? - _theResult___sfd__h749452 : - sfdin__h748716[56:5] ; - assign out_sfd__h758239 = - _theResult___snd__h757501[5] ? - _theResult___sfd__h758236 : - _theResult___snd__h757501[56:5] ; - assign out_sfd__h778657 = - _theResult___snd__h777949[5] ? - _theResult___sfd__h778654 : - _theResult___snd__h777949[56:5] ; - assign out_sfd__h788308 = - sfdin__h787569[5] ? - _theResult___sfd__h788305 : - sfdin__h787569[56:5] ; - assign out_sfd__h797092 = - _theResult___snd__h796354[5] ? - _theResult___sfd__h797089 : - _theResult___snd__h796354[56:5] ; - assign out_sfd__h817961 = - _theResult___snd__h817253[5] ? - _theResult___sfd__h817958 : - _theResult___snd__h817253[56:5] ; - assign out_sfd__h827612 = - sfdin__h826873[5] ? - _theResult___sfd__h827609 : - sfdin__h826873[56:5] ; - assign out_sfd__h836396 = - _theResult___snd__h835658[5] ? - _theResult___sfd__h836393 : - _theResult___snd__h835658[56:5] ; - assign pc__h970672 = fetchStage$pipelines_1_first[590:462] ; - assign pc_addrBits__h1002944 = + _theResult___sfd__h707430 ; + assign out_sfd__h589433 = + sfdin__h588907[34] ? + _theResult___sfd__h589430 : + sfdin__h588907[56:34] ; + assign out_sfd__h598015 = + _theResult___snd__h597520[34] ? + _theResult___sfd__h598012 : + _theResult___snd__h597520[56:34] ; + assign out_sfd__h607199 = + sfdin__h606673[34] ? + _theResult___sfd__h607196 : + sfdin__h606673[56:34] ; + assign out_sfd__h615835 = + _theResult___snd__h615310[34] ? + _theResult___sfd__h615832 : + _theResult___snd__h615310[56:34] ; + assign out_sfd__h635182 = + sfdin__h634656[34] ? + _theResult___sfd__h635179 : + sfdin__h634656[56:34] ; + assign out_sfd__h643764 = + _theResult___snd__h643269[34] ? + _theResult___sfd__h643761 : + _theResult___snd__h643269[56:34] ; + assign out_sfd__h652948 = + sfdin__h652422[34] ? + _theResult___sfd__h652945 : + sfdin__h652422[56:34] ; + assign out_sfd__h661584 = + _theResult___snd__h661059[34] ? + _theResult___sfd__h661581 : + _theResult___snd__h661059[56:34] ; + assign out_sfd__h680929 = + sfdin__h680403[34] ? + _theResult___sfd__h680926 : + sfdin__h680403[56:34] ; + assign out_sfd__h689511 = + _theResult___snd__h689016[34] ? + _theResult___sfd__h689508 : + _theResult___snd__h689016[56:34] ; + assign out_sfd__h698695 = + sfdin__h698169[34] ? + _theResult___sfd__h698692 : + sfdin__h698169[56:34] ; + assign out_sfd__h707331 = + _theResult___snd__h706806[34] ? + _theResult___sfd__h707328 : + _theResult___snd__h706806[56:34] ; + assign out_sfd__h739801 = + _theResult___snd__h739093[5] ? + _theResult___sfd__h739798 : + _theResult___snd__h739093[56:5] ; + assign out_sfd__h749452 = + sfdin__h748713[5] ? + _theResult___sfd__h749449 : + sfdin__h748713[56:5] ; + assign out_sfd__h758236 = + _theResult___snd__h757498[5] ? + _theResult___sfd__h758233 : + _theResult___snd__h757498[56:5] ; + assign out_sfd__h778654 = + _theResult___snd__h777946[5] ? + _theResult___sfd__h778651 : + _theResult___snd__h777946[56:5] ; + assign out_sfd__h788305 = + sfdin__h787566[5] ? + _theResult___sfd__h788302 : + sfdin__h787566[56:5] ; + assign out_sfd__h797089 = + _theResult___snd__h796351[5] ? + _theResult___sfd__h797086 : + _theResult___snd__h796351[56:5] ; + assign out_sfd__h817958 = + _theResult___snd__h817250[5] ? + _theResult___sfd__h817955 : + _theResult___snd__h817250[56:5] ; + assign out_sfd__h827609 = + sfdin__h826870[5] ? + _theResult___sfd__h827606 : + sfdin__h826870[56:5] ; + assign out_sfd__h836393 = + _theResult___snd__h835655[5] ? + _theResult___sfd__h836390 : + _theResult___snd__h835655[56:5] ; + assign pc__h970667 = fetchStage$pipelines_1_first[590:462] ; + assign pc_addrBits__h1002939 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h1003115[13:0] : + x__h1003110[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h1002943 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h926746 = + assign pc_address__h1002938 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h926741 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6273_ETC___d20378, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h1016884 = { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign pointer__h1036714 = { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign pointer__h245459 = + assign pointer__h1016879 = { 2'd0, rob$deqPort_0_deq_data[95:32] } ; + assign pointer__h1036708 = { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign pointer__h245458 = coreFix_memExe_regToExeQ$first[382:317] + - { 2'd0, offset__h245449 } ; - assign prv__h1023771 = csrf_prv_reg ; - assign prv__h1023815 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h710982 = + { 2'd0, offset__h245448 } ; + assign prv__h1023766 = csrf_prv_reg ; + assign prv__h1023810 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h710979 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_0___h927295 = + assign r1__read_BITS_13_TO_0___h927290 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -36429,117 +36429,117 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h932929 = csrf_fs_reg ; - assign r1__read_BIT_20___h933435 = csrf_tw_reg ; - assign r1__read__h859119 = { r1__read__h859121, csrf_ie_vec_1 } ; - assign r1__read__h859121 = { r1__read__h859123, 2'b0 } ; - assign r1__read__h859123 = { r1__read__h859125, csrf_prev_ie_vec_0 } ; - assign r1__read__h859125 = { r1__read__h859127, csrf_prev_ie_vec_1 } ; - assign r1__read__h859127 = { r1__read__h859129, 2'b0 } ; - assign r1__read__h859129 = { r1__read__h859131, csrf_spp_reg } ; - assign r1__read__h859131 = { r1__read__h859133, 4'b0 } ; - assign r1__read__h859133 = { r1__read__h859135, csrf_fs_reg } ; - assign r1__read__h859135 = { r1__read__h859137, 2'd0 } ; - assign r1__read__h859137 = { r1__read__h859139, 1'b0 } ; - assign r1__read__h859139 = { r1__read__h859141, csrf_sum_reg } ; - assign r1__read__h859141 = { r1__read__h859143, csrf_mxr_reg } ; - assign r1__read__h859143 = { r1__read__h859145, 12'b0 } ; - assign r1__read__h859145 = { r1__read__h859147, 2'b10 } ; - assign r1__read__h859147 = { r__h859151, 29'b0 } ; - assign r1__read__h859523 = - { r1__read__h859525, csrf_software_int_en_vec_1 } ; - assign r1__read__h859525 = { r1__read__h859527, 2'b0 } ; - assign r1__read__h859527 = { r1__read__h859529, 1'b0 } ; - assign r1__read__h859529 = { r1__read__h859531, csrf_timer_int_en_vec_1 } ; - assign r1__read__h859531 = { r1__read__h859533, 2'b0 } ; - assign r1__read__h859533 = { r1__read__h859535, 1'b0 } ; - assign r1__read__h859535 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h860033 = { r1__read__h860035, csrf_scounteren_tm_reg } ; - assign r1__read__h860035 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h860045 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h860052 = - { r1__read__h860054, csrf_software_int_pend_vec_1 } ; - assign r1__read__h860054 = { r1__read__h860056, 2'b0 } ; - assign r1__read__h860056 = { r1__read__h860058, 1'b0 } ; - assign r1__read__h860058 = - { r1__read__h860060, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h860060 = { r1__read__h860062, 2'b0 } ; - assign r1__read__h860062 = { r1__read__h860064, 1'b0 } ; - assign r1__read__h860064 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h860262 = { vm_mode_reg__read__h860268, 16'd0 } ; - assign r1__read__h860285 = { r1__read__h860287, csrf_ie_vec_1 } ; - assign r1__read__h860287 = { r1__read__h860289, 1'b0 } ; - assign r1__read__h860289 = { r1__read__h860291, csrf_ie_vec_3 } ; - assign r1__read__h860291 = { r1__read__h860293, csrf_prev_ie_vec_0 } ; - assign r1__read__h860293 = { r1__read__h860295, csrf_prev_ie_vec_1 } ; - assign r1__read__h860295 = { r1__read__h860297, 1'b0 } ; - assign r1__read__h860297 = { r1__read__h860299, csrf_prev_ie_vec_3 } ; - assign r1__read__h860299 = { r1__read__h860301, csrf_spp_reg } ; - assign r1__read__h860301 = { r1__read__h860303, 2'b0 } ; - assign r1__read__h860303 = { r1__read__h860305, csrf_mpp_reg } ; - assign r1__read__h860305 = { r1__read__h860307, csrf_fs_reg } ; - assign r1__read__h860307 = { r1__read__h860309, 2'd0 } ; - assign r1__read__h860309 = { r1__read__h860311, csrf_mprv_reg } ; - assign r1__read__h860311 = { r1__read__h860313, csrf_sum_reg } ; - assign r1__read__h860313 = { r1__read__h860315, csrf_mxr_reg } ; - assign r1__read__h860315 = { r1__read__h860317, csrf_tvm_reg } ; - assign r1__read__h860317 = { r1__read__h860319, csrf_tw_reg } ; - assign r1__read__h860319 = { r1__read__h860321, csrf_tsr_reg } ; - assign r1__read__h860321 = { r1__read__h860323, 9'b0 } ; - assign r1__read__h860323 = { r1__read__h860325, 2'b10 } ; - assign r1__read__h860325 = { r1__read__h860327, 2'b10 } ; - assign r1__read__h860327 = { r__h859151, 27'b0 } ; - assign r1__read__h860410 = { r1__read__h860412, 1'b0 } ; - assign r1__read__h860412 = { r1__read__h860414, csrf_medeleg_13_11_reg } ; - assign r1__read__h860414 = { r1__read__h860416, 1'b0 } ; - assign r1__read__h860416 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h860427 = { r1__read__h860429, 1'b0 } ; - assign r1__read__h860429 = { r1__read__h860431, csrf_mideleg_5_3_reg } ; - assign r1__read__h860431 = { r1__read__h860433, 1'b0 } ; - assign r1__read__h860433 = { r1__read__h860435, csrf_mideleg_9_7_reg } ; - assign r1__read__h860435 = { r1__read__h860437, 1'b0 } ; - assign r1__read__h860437 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h860451 = - { r1__read__h860453, csrf_software_int_en_vec_1 } ; - assign r1__read__h860453 = { r1__read__h860455, 1'b0 } ; - assign r1__read__h860455 = - { r1__read__h860457, csrf_software_int_en_vec_3 } ; - assign r1__read__h860457 = { r1__read__h860459, 1'b0 } ; - assign r1__read__h860459 = { r1__read__h860461, csrf_timer_int_en_vec_1 } ; - assign r1__read__h860461 = { r1__read__h860463, 1'b0 } ; - assign r1__read__h860463 = { r1__read__h860465, csrf_timer_int_en_vec_3 } ; - assign r1__read__h860465 = { r1__read__h860467, 1'b0 } ; - assign r1__read__h860467 = - { r1__read__h860469, csrf_external_int_en_vec_1 } ; - assign r1__read__h860469 = { r1__read__h860471, 1'b0 } ; - assign r1__read__h860471 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h860544 = { r1__read__h860546, csrf_mcounteren_tm_reg } ; - assign r1__read__h860546 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h860556 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h860563 = - { r1__read__h860565, csrf_software_int_pend_vec_1 } ; - assign r1__read__h860565 = { r1__read__h860567, 1'b0 } ; - assign r1__read__h860567 = - { r1__read__h860569, csrf_software_int_pend_vec_3 } ; - assign r1__read__h860569 = { r1__read__h860571, 1'b0 } ; - assign r1__read__h860571 = - { r1__read__h860573, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h860573 = { r1__read__h860575, 1'b0 } ; - assign r1__read__h860575 = - { r1__read__h860577, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h860577 = { r1__read__h860579, 1'b0 } ; - assign r1__read__h860579 = - { r1__read__h860581, csrf_external_int_pend_vec_1 } ; - assign r1__read__h860581 = { r1__read__h860583, 1'b0 } ; - assign r1__read__h860583 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h860892 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h719373 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h719374 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h711009 = + assign r1__read_BITS_13_TO_12___h932924 = csrf_fs_reg ; + assign r1__read_BIT_20___h933430 = csrf_tw_reg ; + assign r1__read__h859116 = { r1__read__h859118, csrf_ie_vec_1 } ; + assign r1__read__h859118 = { r1__read__h859120, 2'b0 } ; + assign r1__read__h859120 = { r1__read__h859122, csrf_prev_ie_vec_0 } ; + assign r1__read__h859122 = { r1__read__h859124, csrf_prev_ie_vec_1 } ; + assign r1__read__h859124 = { r1__read__h859126, 2'b0 } ; + assign r1__read__h859126 = { r1__read__h859128, csrf_spp_reg } ; + assign r1__read__h859128 = { r1__read__h859130, 4'b0 } ; + assign r1__read__h859130 = { r1__read__h859132, csrf_fs_reg } ; + assign r1__read__h859132 = { r1__read__h859134, 2'd0 } ; + assign r1__read__h859134 = { r1__read__h859136, 1'b0 } ; + assign r1__read__h859136 = { r1__read__h859138, csrf_sum_reg } ; + assign r1__read__h859138 = { r1__read__h859140, csrf_mxr_reg } ; + assign r1__read__h859140 = { r1__read__h859142, 12'b0 } ; + assign r1__read__h859142 = { r1__read__h859144, 2'b10 } ; + assign r1__read__h859144 = { r__h859148, 29'b0 } ; + assign r1__read__h859520 = + { r1__read__h859522, csrf_software_int_en_vec_1 } ; + assign r1__read__h859522 = { r1__read__h859524, 2'b0 } ; + assign r1__read__h859524 = { r1__read__h859526, 1'b0 } ; + assign r1__read__h859526 = { r1__read__h859528, csrf_timer_int_en_vec_1 } ; + assign r1__read__h859528 = { r1__read__h859530, 2'b0 } ; + assign r1__read__h859530 = { r1__read__h859532, 1'b0 } ; + assign r1__read__h859532 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h860030 = { r1__read__h860032, csrf_scounteren_tm_reg } ; + assign r1__read__h860032 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h860042 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h860049 = + { r1__read__h860051, csrf_software_int_pend_vec_1 } ; + assign r1__read__h860051 = { r1__read__h860053, 2'b0 } ; + assign r1__read__h860053 = { r1__read__h860055, 1'b0 } ; + assign r1__read__h860055 = + { r1__read__h860057, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h860057 = { r1__read__h860059, 2'b0 } ; + assign r1__read__h860059 = { r1__read__h860061, 1'b0 } ; + assign r1__read__h860061 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h860259 = { vm_mode_reg__read__h860265, 16'd0 } ; + assign r1__read__h860282 = { r1__read__h860284, csrf_ie_vec_1 } ; + assign r1__read__h860284 = { r1__read__h860286, 1'b0 } ; + assign r1__read__h860286 = { r1__read__h860288, csrf_ie_vec_3 } ; + assign r1__read__h860288 = { r1__read__h860290, csrf_prev_ie_vec_0 } ; + assign r1__read__h860290 = { r1__read__h860292, csrf_prev_ie_vec_1 } ; + assign r1__read__h860292 = { r1__read__h860294, 1'b0 } ; + assign r1__read__h860294 = { r1__read__h860296, csrf_prev_ie_vec_3 } ; + assign r1__read__h860296 = { r1__read__h860298, csrf_spp_reg } ; + assign r1__read__h860298 = { r1__read__h860300, 2'b0 } ; + assign r1__read__h860300 = { r1__read__h860302, csrf_mpp_reg } ; + assign r1__read__h860302 = { r1__read__h860304, csrf_fs_reg } ; + assign r1__read__h860304 = { r1__read__h860306, 2'd0 } ; + assign r1__read__h860306 = { r1__read__h860308, csrf_mprv_reg } ; + assign r1__read__h860308 = { r1__read__h860310, csrf_sum_reg } ; + assign r1__read__h860310 = { r1__read__h860312, csrf_mxr_reg } ; + assign r1__read__h860312 = { r1__read__h860314, csrf_tvm_reg } ; + assign r1__read__h860314 = { r1__read__h860316, csrf_tw_reg } ; + assign r1__read__h860316 = { r1__read__h860318, csrf_tsr_reg } ; + assign r1__read__h860318 = { r1__read__h860320, 9'b0 } ; + assign r1__read__h860320 = { r1__read__h860322, 2'b10 } ; + assign r1__read__h860322 = { r1__read__h860324, 2'b10 } ; + assign r1__read__h860324 = { r__h859148, 27'b0 } ; + assign r1__read__h860407 = { r1__read__h860409, 1'b0 } ; + assign r1__read__h860409 = { r1__read__h860411, csrf_medeleg_13_11_reg } ; + assign r1__read__h860411 = { r1__read__h860413, 1'b0 } ; + assign r1__read__h860413 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h860424 = { r1__read__h860426, 1'b0 } ; + assign r1__read__h860426 = { r1__read__h860428, csrf_mideleg_5_3_reg } ; + assign r1__read__h860428 = { r1__read__h860430, 1'b0 } ; + assign r1__read__h860430 = { r1__read__h860432, csrf_mideleg_9_7_reg } ; + assign r1__read__h860432 = { r1__read__h860434, 1'b0 } ; + assign r1__read__h860434 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h860448 = + { r1__read__h860450, csrf_software_int_en_vec_1 } ; + assign r1__read__h860450 = { r1__read__h860452, 1'b0 } ; + assign r1__read__h860452 = + { r1__read__h860454, csrf_software_int_en_vec_3 } ; + assign r1__read__h860454 = { r1__read__h860456, 1'b0 } ; + assign r1__read__h860456 = { r1__read__h860458, csrf_timer_int_en_vec_1 } ; + assign r1__read__h860458 = { r1__read__h860460, 1'b0 } ; + assign r1__read__h860460 = { r1__read__h860462, csrf_timer_int_en_vec_3 } ; + assign r1__read__h860462 = { r1__read__h860464, 1'b0 } ; + assign r1__read__h860464 = + { r1__read__h860466, csrf_external_int_en_vec_1 } ; + assign r1__read__h860466 = { r1__read__h860468, 1'b0 } ; + assign r1__read__h860468 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h860541 = { r1__read__h860543, csrf_mcounteren_tm_reg } ; + assign r1__read__h860543 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h860553 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h860560 = + { r1__read__h860562, csrf_software_int_pend_vec_1 } ; + assign r1__read__h860562 = { r1__read__h860564, 1'b0 } ; + assign r1__read__h860564 = + { r1__read__h860566, csrf_software_int_pend_vec_3 } ; + assign r1__read__h860566 = { r1__read__h860568, 1'b0 } ; + assign r1__read__h860568 = + { r1__read__h860570, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h860570 = { r1__read__h860572, 1'b0 } ; + assign r1__read__h860572 = + { r1__read__h860574, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h860574 = { r1__read__h860576, 1'b0 } ; + assign r1__read__h860576 = + { r1__read__h860578, csrf_external_int_pend_vec_1 } ; + assign r1__read__h860578 = { r1__read__h860580, 1'b0 } ; + assign r1__read__h860580 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h860889 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h719370 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h719371 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h711006 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h859151 = csrf_fs_reg == 2'b11 ; - assign r__h860638 = csrf_software_int_pend_vec_3 ; + assign r__h859148 = csrf_fs_reg == 2'b11 ; + assign r__h860635 = csrf_software_int_pend_vec_3 ; assign regRenamingTable_RDY_rename_0_getRename__1098__ETC___d21109 = regRenamingTable$RDY_rename_0_getRename && rob$RDY_enqPort_0_enq && @@ -36822,78 +36822,78 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20724[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h976130 = + assign renaming_spec_bits__h976125 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h970815 : + y_avValue_snd_fst__h970810 : specTagManager$currentSpecBits ; - assign repBoundBits__h245474 = + assign repBoundBits__h245473 = { coreFix_memExe_regToExeQ$first[230:228], 11'd0 } ; - assign repBound__h1005803 = x__h1003333[13:11] - 3'b001 ; - assign repBound__h1007856 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h1008513 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign repBound__h240153 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h241838 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h251040 = + assign repBound__h1005798 = x__h1003328[13:11] - 3'b001 ; + assign repBound__h1007851 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h1008508 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign repBound__h240152 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h241837 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h251038 = coreFix_memExe_regToExeQ$first[244:242] - 3'b001 ; - assign repBound__h251565 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h862472 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h865816 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h865834 = thin_bounds_baseBits__h865687[13:11] - 3'b001 ; - assign repBound__h871911 = x__h871850[13:11] - 3'b001 ; - assign repBound__h872459 = x__h872398[13:11] - 3'b001 ; - assign repBound__h903761 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h906088 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h906106 = thin_bounds_baseBits__h905991[13:11] - 3'b001 ; - assign repBound__h911888 = x__h911827[13:11] - 3'b001 ; - assign repBound__h912436 = x__h912375[13:11] - 3'b001 ; - assign res_addrBits__h127819 = + assign repBound__h251563 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h862469 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h865813 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h865831 = thin_bounds_baseBits__h865684[13:11] - 3'b001 ; + assign repBound__h871908 = x__h871847[13:11] - 3'b001 ; + assign repBound__h872456 = x__h872395[13:11] - 3'b001 ; + assign repBound__h903757 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h906084 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h906102 = thin_bounds_baseBits__h905987[13:11] - 3'b001 ; + assign repBound__h911884 = x__h911823[13:11] - 3'b001 ; + assign repBound__h912432 = x__h912371[13:11] - 3'b001 ; + assign res_addrBits__h127818 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h128299[13:0] : + x__h128298[13:0] : coreFix_memExe_respLrScAmoQ_data_0[13:0] ; - assign res_addrBits__h140959 = + assign res_addrBits__h140958 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h141443[13:0] : + x__h141442[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h180642 = - INV_x85142_BITS_108_TO_90__q34[0] ? - x__h185224[13:0] : - x__h185142[13:0] ; - assign res_addrBits__h199719 = - INV_x01306_BITS_108_TO_90__q36[0] ? - x__h204287[13:0] : - x__h201306[13:0] ; - assign res_addrBits__h218883 = + assign res_addrBits__h180641 = + INV_x85141_BITS_108_TO_90__q34[0] ? + x__h185223[13:0] : + x__h185141[13:0] ; + assign res_addrBits__h199718 = + INV_x01305_BITS_108_TO_90__q36[0] ? + x__h204286[13:0] : + x__h201305[13:0] ; + assign res_addrBits__h218882 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h219258[13:0] : + x__h219257[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h238159 = { 2'b0, addr__h238152[63:52] } ; - assign res_addrBits__h571698 = + assign res_addrBits__h238158 = { 2'b0, addr__h238151[63:52] } ; + assign res_addrBits__h571694 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; - assign res_addrBits__h572550 = { 2'b0, data__h572031[63:52] } ; - assign res_addrBits__h618307 = { 2'b0, data__h617791[63:52] } ; - assign res_addrBits__h664054 = { 2'b0, data__h663538[63:52] } ; - assign res_addrBits__h709940 = { 2'b0, data__h709454[63:52] } ; - assign res_addrBits__h710886 = { 2'b0, data__h710400[63:52] } ; - assign res_addrBits__h854912 = { 2'b0, addr__h850180[63:52] } ; - assign res_addrBits__h898575 = { 2'b0, addr__h893851[63:52] } ; - assign res_address__h127818 = + assign res_addrBits__h572547 = { 2'b0, data__h572028[63:52] } ; + assign res_addrBits__h618304 = { 2'b0, data__h617788[63:52] } ; + assign res_addrBits__h664051 = { 2'b0, data__h663535[63:52] } ; + assign res_addrBits__h709937 = { 2'b0, data__h709451[63:52] } ; + assign res_addrBits__h710883 = { 2'b0, data__h710397[63:52] } ; + assign res_addrBits__h854909 = { 2'b0, addr__h850177[63:52] } ; + assign res_addrBits__h898571 = { 2'b0, addr__h893847[63:52] } ; + assign res_address__h127817 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; - assign res_address__h140958 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h180641 = { 2'd0, x__h185142[63:0] } ; - assign res_address__h199718 = { 2'd0, x__h201306[63:0] } ; - assign res_address__h218882 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h238158 = { 2'd0, addr__h238152 } ; - assign res_address__h571697 = + assign res_address__h140957 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; + assign res_address__h180640 = { 2'd0, x__h185141[63:0] } ; + assign res_address__h199717 = { 2'd0, x__h201305[63:0] } ; + assign res_address__h218881 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h238157 = { 2'd0, addr__h238151 } ; + assign res_address__h571693 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; - assign res_address__h572549 = { 2'd0, data__h572031 } ; - assign res_address__h618306 = { 2'd0, data__h617791 } ; - assign res_address__h664053 = { 2'd0, data__h663538 } ; - assign res_address__h709939 = { 2'd0, data__h709454 } ; - assign res_address__h710885 = { 2'd0, data__h710400 } ; - assign res_address__h854911 = { 2'd0, addr__h850180 } ; - assign res_address__h898574 = { 2'd0, addr__h893851 } ; - assign res_data__h572589 = { 32'hFFFFFFFF, x__h572604 } ; - assign res_data__h572594 = + assign res_address__h572546 = { 2'd0, data__h572028 } ; + assign res_address__h618303 = { 2'd0, data__h617788 } ; + assign res_address__h664050 = { 2'd0, data__h663535 } ; + assign res_address__h709936 = { 2'd0, data__h709451 } ; + assign res_address__h710882 = { 2'd0, data__h710397 } ; + assign res_address__h854908 = { 2'd0, addr__h850177 } ; + assign res_address__h898570 = { 2'd0, addr__h893847 } ; + assign res_data__h572586 = { 32'hFFFFFFFF, x__h572601 } ; + assign res_data__h572591 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -36906,8 +36906,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h618343 = { 32'hFFFFFFFF, x__h618358 } ; - assign res_data__h618348 = + assign res_data__h618340 = { 32'hFFFFFFFF, x__h618355 } ; + assign res_data__h618345 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -36920,8 +36920,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h664090 = { 32'hFFFFFFFF, x__h664105 } ; - assign res_data__h664095 = + assign res_data__h664087 = { 32'hFFFFFFFF, x__h664102 } ; + assign res_data__h664092 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -36934,7 +36934,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h572590 = + assign res_fflags__h572587 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37002,7 +37002,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9456 } ; - assign res_fflags__h618344 = + assign res_fflags__h618341 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -37070,7 +37070,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10853 } ; - assign res_fflags__h664091 = + assign res_fflags__h664088 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -37138,69 +37138,69 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12250 } ; - assign resp_addr__h513469 = + assign resp_addr__h513466 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[53:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[168:158] } ; - assign result__h243434 = + assign result__h243433 = { 1'd0, ~coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d3711[64], coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d3711[63:0] } ; - assign result__h244591 = + assign result__h244590 = { 1'd0, ~coreFix_memExe_regToExeQ_first__652_BITS_219_T_ETC___d3773[64], coreFix_memExe_regToExeQ_first__652_BITS_219_T_ETC___d3773[63:0] } ; - assign result__h258197 = + assign result__h258195 = { 1'd0, ~coreFix_memExe_dTlb_procResp__258_BITS_452_TO__ETC___d4408[64], coreFix_memExe_dTlb_procResp__258_BITS_452_TO__ETC___d4408[63:0] } ; - assign result__h599057 = + assign result__h599054 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8754[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8754[0] | - guard__h599052 } ; - assign result__h644806 = + guard__h599049 } ; + assign result__h644803 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10151[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10151[0] | - guard__h644801 } ; - assign result__h690553 = + guard__h644798 } ; + assign result__h690550 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11548[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11548[0] | - guard__h690548 } ; - assign result__h741099 = + guard__h690545 } ; + assign result__h741096 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12892[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12892[0] | - guard__h741094 } ; - assign result__h779952 = + guard__h741091 } ; + assign result__h779949 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14377[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14377[0] | - guard__h779947 } ; - assign result__h819256 = + guard__h779944 } ; + assign result__h819253 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13607[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13607[0] | - guard__h819251 } ; - assign result__h922326 = w__h922321 & y__h922355 ; - assign result__h922377 = ~x__h922376 ; - assign result_d_address__h245670 = { 2'd0, pointer__h245459[63:0] } ; - assign ret__h242811 = + guard__h819248 } ; + assign result__h922321 = w__h922316 & y__h922350 ; + assign result__h922372 = ~x__h922371 ; + assign result_d_address__h245669 = { 2'd0, pointer__h245458[63:0] } ; + assign ret__h242810 = { 1'd0, coreFix_memExe_regToExeQ_first__652_BITS_382_T_ETC___d3711[64:0] } ; - assign ret__h243968 = + assign ret__h243967 = { 1'd0, coreFix_memExe_regToExeQ_first__652_BITS_219_T_ETC___d3773[64:0] } ; - assign ret__h257574 = + assign ret__h257572 = { 1'd0, coreFix_memExe_dTlb_procResp__258_BITS_452_TO__ETC___d4408[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19149 = - rf$read_0_rd1[27:25] < repBound__h903761 ; + rf$read_0_rd1[27:25] < repBound__h903757 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19162 = - rf$read_0_rd1[13:11] < repBound__h903761 ; + rf$read_0_rd1[13:11] < repBound__h903757 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19176 = - rf$read_0_rd1[85:83] < repBound__h903761 ; + rf$read_0_rd1[85:83] < repBound__h903757 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19217 = - rf$read_0_rd2[27:25] < repBound__h906088 ; + rf$read_0_rd2[27:25] < repBound__h906084 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19218 = - rf$read_0_rd2[13:11] < repBound__h906088 ; + rf$read_0_rd2[13:11] < repBound__h906084 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19220 = - rf$read_0_rd2[85:83] < repBound__h906088 ; + rf$read_0_rd2[85:83] < repBound__h906084 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19230 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19220, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19217 == @@ -37218,17 +37218,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16706 = - rf$read_1_rd1[27:25] < repBound__h862472 ; + rf$read_1_rd1[27:25] < repBound__h862469 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16719 = - rf$read_1_rd1[13:11] < repBound__h862472 ; + rf$read_1_rd1[13:11] < repBound__h862469 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16733 = - rf$read_1_rd1[85:83] < repBound__h862472 ; + rf$read_1_rd1[85:83] < repBound__h862469 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774 = - rf$read_1_rd2[27:25] < repBound__h865816 ; + rf$read_1_rd2[27:25] < repBound__h865813 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16775 = - rf$read_1_rd2[13:11] < repBound__h865816 ; + rf$read_1_rd2[13:11] < repBound__h865813 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16777 = - rf$read_1_rd2[85:83] < repBound__h865816 ; + rf$read_1_rd2[85:83] < repBound__h865813 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16787 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16777, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774 == @@ -37246,25 +37246,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3345 = - rf$read_3_rd1[27:25] < repBound__h240153 ; + rf$read_3_rd1[27:25] < repBound__h240152 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3358 = - rf$read_3_rd1[13:11] < repBound__h240153 ; + rf$read_3_rd1[13:11] < repBound__h240152 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3372 = - rf$read_3_rd1[85:83] < repBound__h240153 ; + rf$read_3_rd1[85:83] < repBound__h240152 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3599 = - rf$read_3_rd2[27:25] < repBound__h241838 ; + rf$read_3_rd2[27:25] < repBound__h241837 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3607 = - rf$read_3_rd2[13:11] < repBound__h241838 ; + rf$read_3_rd2[13:11] < repBound__h241837 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3616 = - rf$read_3_rd2[85:83] < repBound__h241838 ; + rf$read_3_rd2[85:83] < repBound__h241837 ; assign rg_core_run_state_read__0752_EQ_2_0753_AND_NOT_ETC___d23856 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h858242 = - { r1__read__h860892, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h858239 = + { r1__read__h860889, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1704_AND_epochManager_ch_ETC___d21709 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -37274,273 +37274,273 @@ module mkCore(CLK, IF_IF_fetchStage_pipelines_0_first__0337_BITS__ETC___d21312) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q327 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h856103 = { r1__read__h860262, csrf_ppn_reg } ; - assign sbIdx__h153542 = + assign satp_csr__read__h856100 = { r1__read__h860259, csrf_ppn_reg } ; + assign sbIdx__h153541 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h855900 = - { r1__read__h860045, csrf_scause_code_reg } ; - assign scounteren_csr__read__h855805 = - { r1__read__h860033, csrf_scounteren_cy_reg } ; - assign sfd__h573200 = { value__h581427, 3'd0 } ; - assign sfd__h589008 = + assign scause_csr__read__h855897 = + { r1__read__h860042, csrf_scause_code_reg } ; + assign scounteren_csr__read__h855802 = + { r1__read__h860030, csrf_scounteren_cy_reg } ; + assign sfd__h573197 = { value__h581424, 3'd0 } ; + assign sfd__h589005 = { 1'b0, - _theResult___fst_exp__h588916 != 8'd0, - sfdin__h588910[56:34] } + + _theResult___fst_exp__h588913 != 8'd0, + sfdin__h588907[56:34] } + 25'd1 ; - assign sfd__h597590 = + assign sfd__h597587 = { 1'b0, - _theResult___fst_exp__h597572 != 8'd0, - _theResult___snd__h597523[56:34] } + + _theResult___fst_exp__h597569 != 8'd0, + _theResult___snd__h597520[56:34] } + 25'd1 ; - assign sfd__h606774 = + assign sfd__h606771 = { 1'b0, - _theResult___fst_exp__h606682 != 8'd0, - sfdin__h606676[56:34] } + + _theResult___fst_exp__h606679 != 8'd0, + sfdin__h606673[56:34] } + 25'd1 ; - assign sfd__h615386 = + assign sfd__h615383 = { 1'b0, - _theResult___fst_exp__h615367 != 8'd0, - _theResult___snd__h615313[56:34] } + + _theResult___fst_exp__h615364 != 8'd0, + _theResult___snd__h615310[56:34] } + 25'd1 ; - assign sfd__h618954 = { value__h627176, 3'd0 } ; - assign sfd__h634757 = + assign sfd__h618951 = { value__h627173, 3'd0 } ; + assign sfd__h634754 = { 1'b0, - _theResult___fst_exp__h634665 != 8'd0, - sfdin__h634659[56:34] } + + _theResult___fst_exp__h634662 != 8'd0, + sfdin__h634656[56:34] } + 25'd1 ; - assign sfd__h643339 = + assign sfd__h643336 = { 1'b0, - _theResult___fst_exp__h643321 != 8'd0, - _theResult___snd__h643272[56:34] } + + _theResult___fst_exp__h643318 != 8'd0, + _theResult___snd__h643269[56:34] } + 25'd1 ; - assign sfd__h652523 = + assign sfd__h652520 = { 1'b0, - _theResult___fst_exp__h652431 != 8'd0, - sfdin__h652425[56:34] } + + _theResult___fst_exp__h652428 != 8'd0, + sfdin__h652422[56:34] } + 25'd1 ; - assign sfd__h661135 = + assign sfd__h661132 = { 1'b0, - _theResult___fst_exp__h661116 != 8'd0, - _theResult___snd__h661062[56:34] } + + _theResult___fst_exp__h661113 != 8'd0, + _theResult___snd__h661059[56:34] } + 25'd1 ; - assign sfd__h664701 = { value__h672923, 3'd0 } ; - assign sfd__h680504 = + assign sfd__h664698 = { value__h672920, 3'd0 } ; + assign sfd__h680501 = { 1'b0, - _theResult___fst_exp__h680412 != 8'd0, - sfdin__h680406[56:34] } + + _theResult___fst_exp__h680409 != 8'd0, + sfdin__h680403[56:34] } + 25'd1 ; - assign sfd__h689086 = + assign sfd__h689083 = { 1'b0, - _theResult___fst_exp__h689068 != 8'd0, - _theResult___snd__h689019[56:34] } + + _theResult___fst_exp__h689065 != 8'd0, + _theResult___snd__h689016[56:34] } + 25'd1 ; - assign sfd__h698270 = + assign sfd__h698267 = { 1'b0, - _theResult___fst_exp__h698178 != 8'd0, - sfdin__h698172[56:34] } + + _theResult___fst_exp__h698175 != 8'd0, + sfdin__h698169[56:34] } + 25'd1 ; - assign sfd__h706882 = + assign sfd__h706879 = { 1'b0, - _theResult___fst_exp__h706863 != 8'd0, - _theResult___snd__h706809[56:34] } + + _theResult___fst_exp__h706860 != 8'd0, + _theResult___snd__h706806[56:34] } + 25'd1 ; - assign sfd__h720119 = { value__h724702, 32'd0 } ; - assign sfd__h739163 = + assign sfd__h720116 = { value__h724699, 32'd0 } ; + assign sfd__h739160 = { 1'b0, - _theResult___fst_exp__h739145 != 11'd0, - _theResult___snd__h739096[56:5] } + + _theResult___fst_exp__h739142 != 11'd0, + _theResult___snd__h739093[56:5] } + 54'd1 ; - assign sfd__h748814 = + assign sfd__h748811 = { 1'b0, - _theResult___fst_exp__h748722 != 11'd0, - sfdin__h748716[56:5] } + + _theResult___fst_exp__h748719 != 11'd0, + sfdin__h748713[56:5] } + 54'd1 ; - assign sfd__h757574 = + assign sfd__h757571 = { 1'b0, - _theResult___fst_exp__h757555 != 11'd0, - _theResult___snd__h757501[56:5] } + + _theResult___fst_exp__h757552 != 11'd0, + _theResult___snd__h757498[56:5] } + 54'd1 ; - assign sfd__h759113 = { value__h763555, 32'd0 } ; - assign sfd__h778016 = + assign sfd__h759110 = { value__h763552, 32'd0 } ; + assign sfd__h778013 = { 1'b0, - _theResult___fst_exp__h777998 != 11'd0, - _theResult___snd__h777949[56:5] } + + _theResult___fst_exp__h777995 != 11'd0, + _theResult___snd__h777946[56:5] } + 54'd1 ; - assign sfd__h787667 = + assign sfd__h787664 = { 1'b0, - _theResult___fst_exp__h787575 != 11'd0, - sfdin__h787569[56:5] } + + _theResult___fst_exp__h787572 != 11'd0, + sfdin__h787566[56:5] } + 54'd1 ; - assign sfd__h796427 = + assign sfd__h796424 = { 1'b0, - _theResult___fst_exp__h796408 != 11'd0, - _theResult___snd__h796354[56:5] } + + _theResult___fst_exp__h796405 != 11'd0, + _theResult___snd__h796351[56:5] } + 54'd1 ; - assign sfd__h798417 = { value__h802859, 32'd0 } ; - assign sfd__h817320 = + assign sfd__h798414 = { value__h802856, 32'd0 } ; + assign sfd__h817317 = { 1'b0, - _theResult___fst_exp__h817302 != 11'd0, - _theResult___snd__h817253[56:5] } + + _theResult___fst_exp__h817299 != 11'd0, + _theResult___snd__h817250[56:5] } + 54'd1 ; - assign sfd__h826971 = + assign sfd__h826968 = { 1'b0, - _theResult___fst_exp__h826879 != 11'd0, - sfdin__h826873[56:5] } + + _theResult___fst_exp__h826876 != 11'd0, + sfdin__h826870[56:5] } + 54'd1 ; - assign sfd__h835731 = + assign sfd__h835728 = { 1'b0, - _theResult___fst_exp__h835712 != 11'd0, - _theResult___snd__h835658[56:5] } + + _theResult___fst_exp__h835709 != 11'd0, + _theResult___snd__h835655[56:5] } + 54'd1 ; - assign sfdin__h588910 = - _theResult____h580805[56] ? - _theResult___snd__h588927 : - _theResult___snd__h588938 ; - assign sfdin__h606676 = - _theResult____h598444[56] ? - _theResult___snd__h606693 : - _theResult___snd__h606704 ; - assign sfdin__h634659 = - _theResult____h626556[56] ? - _theResult___snd__h634676 : - _theResult___snd__h634687 ; - assign sfdin__h652425 = - _theResult____h644193[56] ? - _theResult___snd__h652442 : - _theResult___snd__h652453 ; - assign sfdin__h680406 = - _theResult____h672303[56] ? - _theResult___snd__h680423 : - _theResult___snd__h680434 ; - assign sfdin__h698172 = - _theResult____h689940[56] ? - _theResult___snd__h698189 : - _theResult___snd__h698200 ; - assign sfdin__h748716 = - _theResult____h740486[56] ? - _theResult___snd__h748733 : - _theResult___snd__h748744 ; - assign sfdin__h787569 = - _theResult____h779339[56] ? - _theResult___snd__h787586 : - _theResult___snd__h787597 ; - assign sfdin__h826873 = - _theResult____h818643[56] ? - _theResult___snd__h826890 : - _theResult___snd__h826901 ; - assign sie_csr__read__h855752 = { r1__read__h859523, 1'b0 } ; - assign signBits__h245465 = {50{offset__h245449[63]}} ; - assign sip_csr__read__h856040 = { r1__read__h860052, 1'b0 } ; - assign spec_bits__h981149 = specTagManager$currentSpecBits | y__h981162 ; - assign sstatus_csr__read__h855682 = { r1__read__h859119, csrf_ie_vec_0 } ; - assign tb__h871908 = { impliedTopBits__h871762, topBits__h871758[11] } ; - assign tb__h872456 = { impliedTopBits__h872310, topBits__h872306[11] } ; - assign tb__h911885 = { impliedTopBits__h911739, topBits__h911735[11] } ; - assign tb__h912433 = { impliedTopBits__h912287, topBits__h912283[11] } ; - assign thin_address__h1007586 = + assign sfdin__h588907 = + _theResult____h580802[56] ? + _theResult___snd__h588924 : + _theResult___snd__h588935 ; + assign sfdin__h606673 = + _theResult____h598441[56] ? + _theResult___snd__h606690 : + _theResult___snd__h606701 ; + assign sfdin__h634656 = + _theResult____h626553[56] ? + _theResult___snd__h634673 : + _theResult___snd__h634684 ; + assign sfdin__h652422 = + _theResult____h644190[56] ? + _theResult___snd__h652439 : + _theResult___snd__h652450 ; + assign sfdin__h680403 = + _theResult____h672300[56] ? + _theResult___snd__h680420 : + _theResult___snd__h680431 ; + assign sfdin__h698169 = + _theResult____h689937[56] ? + _theResult___snd__h698186 : + _theResult___snd__h698197 ; + assign sfdin__h748713 = + _theResult____h740483[56] ? + _theResult___snd__h748730 : + _theResult___snd__h748741 ; + assign sfdin__h787566 = + _theResult____h779336[56] ? + _theResult___snd__h787583 : + _theResult___snd__h787594 ; + assign sfdin__h826870 = + _theResult____h818640[56] ? + _theResult___snd__h826887 : + _theResult___snd__h826898 ; + assign sie_csr__read__h855749 = { r1__read__h859520, 1'b0 } ; + assign signBits__h245464 = {50{offset__h245448[63]}} ; + assign sip_csr__read__h856037 = { r1__read__h860049, 1'b0 } ; + assign spec_bits__h981144 = specTagManager$currentSpecBits | y__h981157 ; + assign sstatus_csr__read__h855679 = { r1__read__h859116, csrf_ie_vec_0 } ; + assign tb__h871905 = { impliedTopBits__h871759, topBits__h871755[11] } ; + assign tb__h872453 = { impliedTopBits__h872307, topBits__h872303[11] } ; + assign tb__h911881 = { impliedTopBits__h911735, topBits__h911731[11] } ; + assign tb__h912429 = { impliedTopBits__h912283, topBits__h912279[11] } ; + assign thin_address__h1007581 = csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 ? IF_csrf_stcc_reg_read__6801_BIT_86_2883_AND_NO_ETC___d23063 : IF_csrf_mtcc_reg_read__6810_BIT_86_2960_AND_NO_ETC___d23064 ; - assign tmpAddr__h245658 = pointer__h245459[63:0] ; - assign tmp_expBotHalf__h1003108 = + assign tmpAddr__h245657 = pointer__h245458[63:0] ; + assign tmp_expBotHalf__h1003103 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign tmp_expBotHalf__h128292 = + assign tmp_expBotHalf__h128291 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign tmp_expBotHalf__h141436 = + assign tmp_expBotHalf__h141435 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h185217 = { ~x__h185142[66], x__h185142[65:64] } ; - assign tmp_expBotHalf__h204280 = { ~x__h201306[66], x__h201306[65:64] } ; - assign tmp_expBotHalf__h219251 = + assign tmp_expBotHalf__h185216 = { ~x__h185141[66], x__h185141[65:64] } ; + assign tmp_expBotHalf__h204279 = { ~x__h201305[66], x__h201305[65:64] } ; + assign tmp_expBotHalf__h219250 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h871611 = + assign tmp_expBotHalf__h871608 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h872159 = + assign tmp_expBotHalf__h872156 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h911588 = + assign tmp_expBotHalf__h911584 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h912136 = + assign tmp_expBotHalf__h912132 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expTopHalf__h1003106 = + assign tmp_expTopHalf__h1003101 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign tmp_expTopHalf__h128290 = + assign tmp_expTopHalf__h128289 = { ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign tmp_expTopHalf__h141434 = + assign tmp_expTopHalf__h141433 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h185215 = { ~x__h185142[80:79], x__h185142[78] } ; - assign tmp_expTopHalf__h204278 = { ~x__h201306[80:79], x__h201306[78] } ; - assign tmp_expTopHalf__h219249 = + assign tmp_expTopHalf__h185214 = { ~x__h185141[80:79], x__h185141[78] } ; + assign tmp_expTopHalf__h204277 = { ~x__h201305[80:79], x__h201305[78] } ; + assign tmp_expTopHalf__h219248 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h871609 = + assign tmp_expTopHalf__h871606 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h872157 = + assign tmp_expTopHalf__h872154 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h911586 = + assign tmp_expTopHalf__h911582 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h912134 = + assign tmp_expTopHalf__h912130 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign toBoundsM1__h245478 = - repBoundBits__h245474 + + assign toBoundsM1__h245477 = + repBoundBits__h245473 + ~coreFix_memExe_regToExeQ$first[316:303] ; - assign toBounds__h245477 = - repBoundBits__h245474 - coreFix_memExe_regToExeQ$first[316:303] ; - assign topBits__h1003242 = + assign toBounds__h245476 = + repBoundBits__h245473 - coreFix_memExe_regToExeQ$first[316:303] ; + assign topBits__h1003237 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h1003339 ; - assign topBits__h128426 = + b_top__h1003334 ; + assign topBits__h128425 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : - b_top__h128523 ; - assign topBits__h141570 = + b_top__h128522 ; + assign topBits__h141569 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : - b_top__h141667 ; - assign topBits__h185351 = - INV_x85142_BITS_108_TO_90__q34[0] ? - { x__h185142[89:81], 3'd0 } : - b_top__h185448 ; - assign topBits__h204414 = - INV_x01306_BITS_108_TO_90__q36[0] ? - { x__h201306[89:81], 3'd0 } : - b_top__h204511 ; - assign topBits__h219385 = + b_top__h141666 ; + assign topBits__h185350 = + INV_x85141_BITS_108_TO_90__q34[0] ? + { x__h185141[89:81], 3'd0 } : + b_top__h185447 ; + assign topBits__h204413 = + INV_x01305_BITS_108_TO_90__q36[0] ? + { x__h201305[89:81], 3'd0 } : + b_top__h204510 ; + assign topBits__h219384 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h219482 ; - assign topBits__h871758 = + b_top__h219481 ; + assign topBits__h871755 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h871856 ; - assign topBits__h872306 = + b_top__h871853 ; + assign topBits__h872303 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h872404 ; - assign topBits__h911735 = + b_top__h872401 ; + assign topBits__h911731 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h911833 ; - assign topBits__h912283 = + b_top__h911829 ; + assign topBits__h912279 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h912381 ; - assign trap_val__h1005244 = { 53'd0, x__h1007065 } ; - assign upd__h1020160 = + b_top__h912377 ; + assign trap_val__h1005239 = { 53'd0, x__h1007060 } ; + assign upd__h1020155 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -37553,7 +37553,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1018941 = + assign v__h1018936 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], @@ -37565,7 +37565,7 @@ module mkCore(CLK, ~IF_csrf_sepcc_reg_read_wget__3477_BIT_34_3486__ETC___d23494[2], IF_csrf_sepcc_reg_read_wget__3477_BIT_34_3486__ETC___d23494[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1019394 = + assign v__h1019389 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], @@ -37577,353 +37577,353 @@ module mkCore(CLK, ~IF_csrf_mepcc_reg_read_wget__3506_BIT_34_3515__ETC___d23523[2], IF_csrf_mepcc_reg_read_wget__3506_BIT_34_3515__ETC___d23523[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h519176 = + assign v__h519172 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7300 ? - v__h519371 : + v__h519367 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h519371 = + assign v__h519367 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h521196 = + assign v__h521192 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7394 ? - v__h521576 : + v__h521572 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h521576 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h536915 = + assign v__h521572 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h536911 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7553 ? - v__h537110 : + v__h537106 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h537110 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h539364 = + assign v__h537106 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h539360 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7637 ? - v__h539559 : + v__h539555 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h539559 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h560384 = + assign v__h539555 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h560380 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7842 ? - v__h560579 : + v__h560575 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h560579 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h564163 = + assign v__h560575 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h564159 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7924 ? - v__h564358 : + v__h564354 : coreFix_memExe_forwardQ_enqP ; - assign v__h564358 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h841822 = + assign v__h564354 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h841819 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h841832 : + v__h841829 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h841832 = + assign v__h841829 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h842863 = v__h841822 - 2'd1 ; - assign value__h242528 = x__h242546 | in__h242638[63:0] ; - assign value__h242692 = - { coreFix_memExe_regToExeQ$first[380:331] & mask__h242699, + assign v__h842860 = v__h841819 - 2'd1 ; + assign value__h242527 = x__h242545 | in__h242637[63:0] ; + assign value__h242691 = + { coreFix_memExe_regToExeQ$first[380:331] & mask__h242698, 14'd0 } + - addBase__h242698 ; - assign value__h243685 = x__h243703 | in__h243795[63:0] ; - assign value__h243849 = - { coreFix_memExe_regToExeQ$first[217:168] & mask__h243856, + addBase__h242697 ; + assign value__h243684 = x__h243702 | in__h243794[63:0] ; + assign value__h243848 = + { coreFix_memExe_regToExeQ$first[217:168] & mask__h243855, 14'd0 } + - addBase__h243855 ; - assign value__h257291 = x__h257309 | in__h257401[63:0] ; - assign value__h257455 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h257462, + addBase__h243854 ; + assign value__h257289 = x__h257307 | in__h257399[63:0] ; + assign value__h257453 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h257460, 14'd0 } + - addBase__h257461 ; - assign value__h581427 = + addBase__h257459 ; + assign value__h581424 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h627176 = + assign value__h627173 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h672923 = + assign value__h672920 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h724702 = { 1'b0, f1_exp__h719757 != 8'd0, f1_sfd__h719758 } ; - assign value__h763555 = { 1'b0, f2_exp__h758751 != 8'd0, f2_sfd__h758752 } ; - assign value__h802859 = { 1'b0, f3_exp__h798055 != 8'd0, f3_sfd__h798056 } ; - assign vm_mode_reg__read__h860268 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h922321 = + assign value__h724699 = { 1'b0, f1_exp__h719754 != 8'd0, f1_sfd__h719755 } ; + assign value__h763552 = { 1'b0, f2_exp__h758748 != 8'd0, f2_sfd__h758749 } ; + assign value__h802856 = { 1'b0, f3_exp__h798052 != 8'd0, f3_sfd__h798053 } ; + assign vm_mode_reg__read__h860265 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h922316 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h922377 : + result__h922372 : 12'd4095 ; - assign wordIdx__h266096 = + assign wordIdx__h266094 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1009091 = + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1009086 = csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1003115 = commitStage_commitTrap[172:109] >> x__h1003153 ; - assign x__h1003153 = - { tmp_expTopHalf__h1003106, tmp_expBotHalf__h1003108 } ; - assign x__h1003313 = { impliedTopBits__h1003246, topBits__h1003242 } ; - assign x__h1003330 = x__h1003333[13:12] + carry_out__h1003244 ; - assign x__h1003333 = + assign x__h1003110 = commitStage_commitTrap[172:109] >> x__h1003148 ; + assign x__h1003148 = + { tmp_expTopHalf__h1003101, tmp_expBotHalf__h1003103 } ; + assign x__h1003308 = { impliedTopBits__h1003241, topBits__h1003237 } ; + assign x__h1003325 = x__h1003328[13:12] + carry_out__h1003239 ; + assign x__h1003328 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h1003340 ; - assign x__h1005791 = - x__h1005793 << + b_base__h1003335 ; + assign x__h1005786 = + x__h1005788 << IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22727 ; - assign x__h1005793 = { {48{offset__h1005779[15]}}, offset__h1005779 } ; - assign x__h1005878 = + assign x__h1005788 = { {48{offset__h1005774[15]}}, offset__h1005774 } ; + assign x__h1005873 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2410_BITS_217_TO_ETC___d22727 ; - assign x__h1007065 = + assign x__h1007060 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q25 } ; - assign x__h1007765 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h1007791 = { cause_code__h1003524, 2'b0 } ; - assign x__h1007892 = address__h1007698 >> csrf_stcc_reg[33:28] ; - assign x__h1008196 = address__h1008042 >> csrf_stcc_reg[33:28] ; - assign x__h1008422 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h1008549 = address__h1008355 >> csrf_mtcc_reg[33:28] ; - assign x__h1008853 = address__h1008699 >> csrf_mtcc_reg[33:28] ; - assign x__h1009088 = + assign x__h1007760 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h1007786 = { cause_code__h1003519, 2'b0 } ; + assign x__h1007887 = address__h1007693 >> csrf_stcc_reg[33:28] ; + assign x__h1008191 = address__h1008037 >> csrf_stcc_reg[33:28] ; + assign x__h1008417 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h1008544 = address__h1008350 >> csrf_mtcc_reg[33:28] ; + assign x__h1008848 = address__h1008694 >> csrf_mtcc_reg[33:28] ; + assign x__h1009083 = csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h1009109 = + assign x__h1009104 = csrf_prv_reg_read__0367_ULE_1_2761_AND_IF_comm_ETC___d22794 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; - assign x__h1016908 = pointer__h1016884 >> csrf_rg_dpc[33:28] ; - assign x__h1018962 = { 1'b0, csrf_spp_reg } ; - assign x__h1022926 = + assign x__h1016903 = pointer__h1016879 >> csrf_rg_dpc[33:28] ; + assign x__h1018957 = { 1'b0, csrf_spp_reg } ; + assign x__h1022921 = NOT_rob_deqPort_0_canDeq__3556_3557_OR_rob_deq_ETC___d23781 ? - y_avValue_snd_snd_snd_fst__h1022748 : + y_avValue_snd_snd_snd_fst__h1022743 : IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23810 ; - assign x__h1036737 = pointer__h1036714 >> csrf_rg_dpc[33:28] ; - assign x__h128299 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h128337 ; - assign x__h128337 = { tmp_expTopHalf__h128290, tmp_expBotHalf__h128292 } ; - assign x__h128497 = { impliedTopBits__h128430, topBits__h128426 } ; - assign x__h128514 = x__h128517[13:12] + carry_out__h128428 ; - assign x__h128517 = + assign x__h1036731 = pointer__h1036708 >> csrf_rg_dpc[33:28] ; + assign x__h128298 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h128336 ; + assign x__h128336 = { tmp_expTopHalf__h128289, tmp_expBotHalf__h128291 } ; + assign x__h128496 = { impliedTopBits__h128429, topBits__h128425 } ; + assign x__h128513 = x__h128516[13:12] + carry_out__h128427 ; + assign x__h128516 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[77:67], 3'd0 } : - b_base__h128524 ; - assign x__h141443 = mmio_dataRespQ_data_0[63:0] >> x__h141481 ; - assign x__h141481 = { tmp_expTopHalf__h141434, tmp_expBotHalf__h141436 } ; - assign x__h141641 = { impliedTopBits__h141574, topBits__h141570 } ; - assign x__h141658 = x__h141661[13:12] + carry_out__h141572 ; - assign x__h141661 = + b_base__h128523 ; + assign x__h141442 = mmio_dataRespQ_data_0[63:0] >> x__h141480 ; + assign x__h141480 = { tmp_expTopHalf__h141433, tmp_expBotHalf__h141435 } ; + assign x__h141640 = { impliedTopBits__h141573, topBits__h141569 } ; + assign x__h141657 = x__h141660[13:12] + carry_out__h141571 ; + assign x__h141660 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[77:67], 3'd0 } : - b_base__h141668 ; - assign x__h150517 = + b_base__h141667 ; + assign x__h150516 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; - assign x__h153651 = { 3'd0, sbIdx__h153542 } ; - assign x__h185142 = + assign x__h153650 = { 3'd0, sbIdx__h153541 } ; + assign x__h185141 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d1917 } ; - assign x__h185224 = x__h185142[63:0] >> x__h185262 ; - assign x__h185262 = { tmp_expTopHalf__h185215, tmp_expBotHalf__h185217 } ; - assign x__h185422 = { impliedTopBits__h185355, topBits__h185351 } ; - assign x__h185439 = x__h185442[13:12] + carry_out__h185353 ; - assign x__h185442 = - INV_x85142_BITS_108_TO_90__q34[0] ? - { x__h185142[77:67], 3'd0 } : - b_base__h185449 ; - assign x__h201306 = + assign x__h185223 = x__h185141[63:0] >> x__h185261 ; + assign x__h185261 = { tmp_expTopHalf__h185214, tmp_expBotHalf__h185216 } ; + assign x__h185421 = { impliedTopBits__h185354, topBits__h185350 } ; + assign x__h185438 = x__h185441[13:12] + carry_out__h185352 ; + assign x__h185441 = + INV_x85141_BITS_108_TO_90__q34[0] ? + { x__h185141[77:67], 3'd0 } : + b_base__h185448 ; + assign x__h201305 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d2085 } ; - assign x__h204287 = x__h201306[63:0] >> x__h204325 ; - assign x__h204325 = { tmp_expTopHalf__h204278, tmp_expBotHalf__h204280 } ; - assign x__h204485 = { impliedTopBits__h204418, topBits__h204414 } ; - assign x__h204502 = x__h204505[13:12] + carry_out__h204416 ; - assign x__h204505 = - INV_x01306_BITS_108_TO_90__q36[0] ? - { x__h201306[77:67], 3'd0 } : - b_base__h204512 ; - assign x__h219258 = coreFix_memExe_lsq$respLd[63:0] >> x__h219296 ; - assign x__h219296 = { tmp_expTopHalf__h219249, tmp_expBotHalf__h219251 } ; - assign x__h219456 = { impliedTopBits__h219389, topBits__h219385 } ; - assign x__h219473 = x__h219476[13:12] + carry_out__h219387 ; - assign x__h219476 = + assign x__h204286 = x__h201305[63:0] >> x__h204324 ; + assign x__h204324 = { tmp_expTopHalf__h204277, tmp_expBotHalf__h204279 } ; + assign x__h204484 = { impliedTopBits__h204417, topBits__h204413 } ; + assign x__h204501 = x__h204504[13:12] + carry_out__h204415 ; + assign x__h204504 = + INV_x01305_BITS_108_TO_90__q36[0] ? + { x__h201305[77:67], 3'd0 } : + b_base__h204511 ; + assign x__h219257 = coreFix_memExe_lsq$respLd[63:0] >> x__h219295 ; + assign x__h219295 = { tmp_expTopHalf__h219248, tmp_expBotHalf__h219250 } ; + assign x__h219455 = { impliedTopBits__h219388, topBits__h219384 } ; + assign x__h219472 = x__h219475[13:12] + carry_out__h219386 ; + assign x__h219475 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h219483 ; - assign x__h238581 = + b_base__h219482 ; + assign x__h238580 = (coreFix_memExe_dispToRegQ$first[109] && coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3063 : 66'd0 ; - assign x__h242546 = x__h242548 << coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h242548 = { {48{offset__h242534[15]}}, offset__h242534 } ; - assign x__h242656 = + assign x__h242545 = x__h242547 << coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h242547 = { {48{offset__h242533[15]}}, offset__h242533 } ; + assign x__h242655 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h242804 = + assign x__h242803 = coreFix_memExe_regToExeQ_first__652_BITS_264_T_ETC___d3724 ? - result__h243434 : - ret__h242811 ; - assign x__h242906 = + result__h243433 : + ret__h242810 ; + assign x__h242905 = { coreFix_memExe_regToExeQ$first[224:223], coreFix_memExe_regToExeQ$first[258:245] } ; - assign x__h242975 = + assign x__h242974 = (coreFix_memExe_regToExeQ$first[264:259] == 6'd50) ? coreFix_memExe_regToExeQ$first[244] : coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3[49] ; - assign x__h243703 = x__h243705 << coreFix_memExe_regToExeQ$first[101:96] ; - assign x__h243705 = { {48{offset__h243691[15]}}, offset__h243691 } ; - assign x__h243813 = + assign x__h243702 = x__h243704 << coreFix_memExe_regToExeQ$first[101:96] ; + assign x__h243704 = { {48{offset__h243690[15]}}, offset__h243690 } ; + assign x__h243812 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign x__h243961 = + assign x__h243960 = coreFix_memExe_regToExeQ_first__652_BITS_101_T_ETC___d3786 ? - result__h244591 : - ret__h243968 ; - assign x__h244063 = + result__h244590 : + ret__h243967 ; + assign x__h244062 = { coreFix_memExe_regToExeQ$first[61:60], coreFix_memExe_regToExeQ$first[95:82] } ; - assign x__h244132 = + assign x__h244131 = (coreFix_memExe_regToExeQ$first[101:96] == 6'd50) ? coreFix_memExe_regToExeQ$first[81] : coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q5[49] ; - assign x__h245495 = offset__h245449[63:14] ^ signBits__h245465 ; - assign x__h245598 = - offset__h245449 >> coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h247500 = { pointer__h245459[3:0], 3'b0 } ; - assign x__h250942 = - pointer__h245459 >> coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h252297 = x__h252309 + y__h252310 ; - assign x__h252309 = x__h252321 + y__h252322 ; - assign x__h252321 = x__h252333 + y__h252334 ; - assign x__h252333 = x__h252345 + y__h252346 ; - assign x__h252345 = x__h252357 + y__h252358 ; - assign x__h252357 = x__h252369 + y__h252370 ; - assign x__h252369 = x__h252381 + y__h252382 ; - assign x__h252381 = x__h252393 + y__h252394 ; - assign x__h252393 = x__h252405 + y__h252406 ; - assign x__h252405 = x__h252417 + y__h252418 ; - assign x__h252417 = x__h252429 + y__h252430 ; - assign x__h252429 = x__h252441 + y__h252442 ; - assign x__h252441 = x__h252453 + y__h252454 ; - assign x__h252453 = x__h252465 + y__h252466 ; - assign x__h252465 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h257309 = x__h257311 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h257311 = { {48{offset__h257297[15]}}, offset__h257297 } ; - assign x__h257419 = + assign x__h245494 = offset__h245448[63:14] ^ signBits__h245464 ; + assign x__h245597 = + offset__h245448 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h247498 = { pointer__h245458[3:0], 3'b0 } ; + assign x__h250940 = + pointer__h245458 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h252295 = x__h252307 + y__h252308 ; + assign x__h252307 = x__h252319 + y__h252320 ; + assign x__h252319 = x__h252331 + y__h252332 ; + assign x__h252331 = x__h252343 + y__h252344 ; + assign x__h252343 = x__h252355 + y__h252356 ; + assign x__h252355 = x__h252367 + y__h252368 ; + assign x__h252367 = x__h252379 + y__h252380 ; + assign x__h252379 = x__h252391 + y__h252392 ; + assign x__h252391 = x__h252403 + y__h252404 ; + assign x__h252403 = x__h252415 + y__h252416 ; + assign x__h252415 = x__h252427 + y__h252428 ; + assign x__h252427 = x__h252439 + y__h252440 ; + assign x__h252439 = x__h252451 + y__h252452 ; + assign x__h252451 = x__h252463 + y__h252464 ; + assign x__h252463 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h257307 = x__h257309 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h257309 = { {48{offset__h257295[15]}}, offset__h257295 } ; + assign x__h257417 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h257567 = + assign x__h257565 = coreFix_memExe_dTlb_procResp__258_BITS_334_TO__ETC___d4421 ? - result__h258197 : - ret__h257574 ; - assign x__h257669 = + result__h258195 : + ret__h257572 ; + assign x__h257667 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h257738 = + assign x__h257736 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h526027 = + assign x__h526023 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h572604 = - { (_theResult___exp__h615936 != 8'd255 || - _theResult___sfd__h615937 == 23'd0) && + assign x__h572601 = + { (_theResult___exp__h615933 != 8'd255 || + _theResult___sfd__h615934 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9336, - out_f_exp__h616213, - out_f_sfd__h616214 } ; - assign x__h599154 = - sfd__h573200 << (x__h599187[11] ? 12'hAAA : x__h599187) ; - assign x__h599187 = + out_f_exp__h616210, + out_f_sfd__h616211 } ; + assign x__h599151 = + sfd__h573197 << (x__h599184[11] ? 12'hAAA : x__h599184) ; + assign x__h599184 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8750 ; - assign x__h618358 = - { (_theResult___exp__h661685 != 8'd255 || - _theResult___sfd__h661686 == 23'd0) && + assign x__h618355 = + { (_theResult___exp__h661682 != 8'd255 || + _theResult___sfd__h661683 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10733, - out_f_exp__h661962, - out_f_sfd__h661963 } ; - assign x__h644903 = - sfd__h618954 << (x__h644936[11] ? 12'hAAA : x__h644936) ; - assign x__h644936 = + out_f_exp__h661959, + out_f_sfd__h661960 } ; + assign x__h644900 = + sfd__h618951 << (x__h644933[11] ? 12'hAAA : x__h644933) ; + assign x__h644933 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10147 ; assign x__h65608 = mmio_pRqQ_data_0[31:0] ; - assign x__h664105 = - { (_theResult___exp__h707432 != 8'd255 || - _theResult___sfd__h707433 == 23'd0) && + assign x__h664102 = + { (_theResult___exp__h707429 != 8'd255 || + _theResult___sfd__h707430 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12130, - out_f_exp__h707709, - out_f_sfd__h707710 } ; - assign x__h690650 = - sfd__h664701 << (x__h690683[11] ? 12'hAAA : x__h690683) ; - assign x__h690683 = + out_f_exp__h707706, + out_f_sfd__h707707 } ; + assign x__h690647 = + sfd__h664698 << (x__h690680[11] ? 12'hAAA : x__h690680) ; + assign x__h690680 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11544 ; - assign x__h719279 = + assign x__h719276 = sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1[149:86] : - y_avValue__h715328 ; - assign x__h719280 = + y_avValue__h715325 ; + assign x__h719277 = sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2[149:86] : - y_avValue__h716036 ; - assign x__h719281 = + y_avValue__h716033 ; + assign x__h719278 = sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3[149:86] : - y_avValue__h716738 ; - assign x__h741194 = sfd__h720119 << x__h741227 ; - assign x__h741227 = + y_avValue__h716735 ; + assign x__h741191 = sfd__h720116 << x__h741224 ; + assign x__h741224 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12888 ; - assign x__h780047 = sfd__h759113 << x__h780080 ; - assign x__h780080 = + assign x__h780044 = sfd__h759110 << x__h780077 ; + assign x__h780077 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14373 ; - assign x__h819351 = sfd__h798417 << x__h819384 ; - assign x__h819384 = + assign x__h819348 = sfd__h798414 << x__h819381 ; + assign x__h819381 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13603 ; - assign x__h841140 = + assign x__h841137 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h841151 : - a__h840603 ; - assign x__h841166 = a__h840603[63] ^ b__h840604[63] ; - assign x__h841752 = + _theResult___fst__h841148 : + a__h840600 ; + assign x__h841163 = a__h840600[63] ^ b__h840601[63] ; + assign x__h841749 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15384, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15385 } ; - assign x__h859104 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h871619 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h871657 ; - assign x__h871657 = { tmp_expTopHalf__h871609, tmp_expBotHalf__h871611 } ; - assign x__h871830 = { impliedTopBits__h871762, topBits__h871758 } ; - assign x__h871847 = x__h871850[13:12] + carry_out__h871760 ; - assign x__h871850 = + assign x__h859101 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h871616 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h871654 ; + assign x__h871654 = { tmp_expTopHalf__h871606, tmp_expBotHalf__h871608 } ; + assign x__h871827 = { impliedTopBits__h871759, topBits__h871755 } ; + assign x__h871844 = x__h871847[13:12] + carry_out__h871757 ; + assign x__h871847 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h871857 ; - assign x__h872167 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h872205 ; - assign x__h872205 = { tmp_expTopHalf__h872157, tmp_expBotHalf__h872159 } ; - assign x__h872378 = { impliedTopBits__h872310, topBits__h872306 } ; - assign x__h872395 = x__h872398[13:12] + carry_out__h872308 ; - assign x__h872398 = + b_base__h871854 ; + assign x__h872164 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h872202 ; + assign x__h872202 = { tmp_expTopHalf__h872154, tmp_expBotHalf__h872156 } ; + assign x__h872375 = { impliedTopBits__h872307, topBits__h872303 } ; + assign x__h872392 = x__h872395[13:12] + carry_out__h872305 ; + assign x__h872395 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h872405 ; - assign x__h872605 = + b_base__h872402 ; + assign x__h872602 = { basicExec___d17757[443], basicExec___d17757[362:347], basicExec___d17757[345:344], @@ -37935,7 +37935,7 @@ module mkCore(CLK, ~IF_basicExec_7757_BIT_325_7768_THEN_basicExec__ETC___d17776[2], IF_basicExec_7757_BIT_325_7768_THEN_basicExec__ETC___d17776[1:0], basicExec___d17757[440:377] } ; - assign x__h886260 = + assign x__h886256 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -37947,28 +37947,28 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7888_BIT__ETC___d18098[2], IF_coreFix_aluExe_1_exeToFinQ_first__7888_BIT__ETC___d18098[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h902154 = + assign x__h902150 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q24, 5'd3 } ; - assign x__h911596 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h911634 ; - assign x__h911634 = { tmp_expTopHalf__h911586, tmp_expBotHalf__h911588 } ; - assign x__h911807 = { impliedTopBits__h911739, topBits__h911735 } ; - assign x__h911824 = x__h911827[13:12] + carry_out__h911737 ; - assign x__h911827 = + assign x__h911592 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h911630 ; + assign x__h911630 = { tmp_expTopHalf__h911582, tmp_expBotHalf__h911584 } ; + assign x__h911803 = { impliedTopBits__h911735, topBits__h911731 } ; + assign x__h911820 = x__h911823[13:12] + carry_out__h911733 ; + assign x__h911823 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h911834 ; - assign x__h912144 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h912182 ; - assign x__h912182 = { tmp_expTopHalf__h912134, tmp_expBotHalf__h912136 } ; - assign x__h912355 = { impliedTopBits__h912287, topBits__h912283 } ; - assign x__h912372 = x__h912375[13:12] + carry_out__h912285 ; - assign x__h912375 = + b_base__h911830 ; + assign x__h912140 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h912178 ; + assign x__h912178 = { tmp_expTopHalf__h912130, tmp_expBotHalf__h912132 } ; + assign x__h912351 = { impliedTopBits__h912283, topBits__h912279 } ; + assign x__h912368 = x__h912371[13:12] + carry_out__h912281 ; + assign x__h912371 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h912382 ; - assign x__h912582 = + b_base__h912378 ; + assign x__h912578 = { basicExec___d19895[443], basicExec___d19895[362:347], basicExec___d19895[345:344], @@ -37980,7 +37980,7 @@ module mkCore(CLK, ~IF_basicExec_9895_BIT_325_9906_THEN_basicExec__ETC___d19914[2], IF_basicExec_9895_BIT_325_9906_THEN_basicExec__ETC___d19914[1:0], basicExec___d19895[440:377] } ; - assign x__h921139 = + assign x__h921134 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -37992,8 +37992,8 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__0026_BIT__ETC___d20235[2], IF_coreFix_aluExe_0_exeToFinQ_first__0026_BIT__ETC___d20235[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h922325 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h922376 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h922320 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h922371 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; assign x_addr__h19852 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[214:151] : @@ -38002,7 +38002,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h539726 = + assign x_addr__h539722 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -38010,56 +38010,56 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h932727 = csrf_frm_reg ; - assign x_quotient__h710171 = + assign x_decodeInfo_frm__h932722 = csrf_frm_reg ; + assign x_quotient__h710168 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h710982 : + q___1__h710979 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h855591 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h710172 = + assign x_reg_ifc__read__h855588 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h710169 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h711009 : + r___1__h711006 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h1005877 = ~x__h1005878 ; - assign y__h1007821 = { mask__h1007704[62:0], 1'd0 } ; - assign y__h1008478 = { mask__h1008361[62:0], 1'd0 } ; - assign y__h1022701 = + assign y__h1005872 = ~x__h1005873 ; + assign y__h1007816 = { mask__h1007699[62:0], 1'd0 } ; + assign y__h1008473 = { mask__h1008356[62:0], 1'd0 } ; + assign y__h1022696 = NOT_rob_deqPort_0_canDeq__3556_3557_OR_rob_deq_ETC___d23781 ? - y_avValue_snd_snd_snd_snd_snd__h1022754 : + y_avValue_snd_snd_snd_snd_snd__h1022749 : IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23678 ; - assign y__h242655 = ~x__h242656 ; - assign y__h243812 = ~x__h243813 ; - assign y__h252298 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h252310 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h252322 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h252334 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h252346 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h252358 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h252370 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h252382 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h252394 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h252406 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h252418 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h252430 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h252442 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h252454 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h252466 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h257418 = ~x__h257419 ; - assign y__h426243 = + assign y__h242654 = ~x__h242655 ; + assign y__h243811 = ~x__h243812 ; + assign y__h252296 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h252308 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h252320 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h252332 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h252344 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h252356 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h252368 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h252380 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h252392 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h252404 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h252416 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h252428 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h252440 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h252452 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h252464 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h257416 = ~x__h257417 ; + assign y__h426240 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[168:164] } ; - assign y__h872859 = - { coreFix_aluExe_1_regToExeQ$first[306:242], address__h872898 } ; - assign y__h912836 = - { coreFix_aluExe_0_regToExeQ$first[306:242], address__h912839 } ; - assign y__h922355 = ~x__h922325 ; - assign y__h927285 = + assign y__h872856 = + { coreFix_aluExe_1_regToExeQ$first[306:242], address__h872895 } ; + assign y__h912832 = + { coreFix_aluExe_0_regToExeQ$first[306:242], address__h912835 } ; + assign y__h922350 = ~x__h922320 ; + assign y__h927280 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -38068,20 +38068,20 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h981162 = 12'd1 << specTagManager$nextSpecTag ; - assign y_avValue__h715328 = + assign y__h981157 = 12'd1 << specTagManager$nextSpecTag ; + assign y_avValue__h715325 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12452 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12580 ; - assign y_avValue__h716036 = + assign y_avValue__h716033 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12481 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12589 ; - assign y_avValue__h716738 = + assign y_avValue__h716735 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12507 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12598 ; - assign y_avValue_snd_fst__h1022095 = + assign y_avValue_snd_fst__h1022090 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38096,7 +38096,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1022738 = + assign y_avValue_snd_fst__h1022733 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38110,25 +38110,25 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23788 : - y_avValue_snd_fst__h1022767 ; - assign y_avValue_snd_fst__h1022767 = + y_avValue_snd_fst__h1022762 ; + assign y_avValue_snd_fst__h1022762 = IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23788 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h970815 = + assign y_avValue_snd_fst__h970810 = ((fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1238_AND__ETC___d21262) ? - y_avValue_snd_fst__h970857 : + y_avValue_snd_fst__h970852 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h970857 = + assign y_avValue_snd_fst__h970852 = IF_fetchStage_pipelines_0_first__0337_BITS_267_ETC___d21303 ? - y_avValue_snd_fst__h970899 : + y_avValue_snd_fst__h970894 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h970899 = + assign y_avValue_snd_fst__h970894 = (fetchStage$pipelines_0_first[267:265] == 3'd1) ? - spec_bits__h981149 : + spec_bits__h981144 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1022105 = + assign y_avValue_snd_snd_snd_fst__h1022100 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38143,7 +38143,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1022748 = + assign y_avValue_snd_snd_snd_fst__h1022743 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38157,11 +38157,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23810 : - y_avValue_snd_snd_snd_fst__h1022777 ; - assign y_avValue_snd_snd_snd_fst__h1022777 = + y_avValue_snd_snd_snd_fst__h1022772 ; + assign y_avValue_snd_snd_snd_fst__h1022772 = IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23810 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1022111 = + assign y_avValue_snd_snd_snd_snd_snd__h1022106 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38176,7 +38176,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1022754 = + assign y_avValue_snd_snd_snd_snd_snd__h1022749 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38190,8 +38190,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23678 : - y_avValue_snd_snd_snd_snd_snd__h1022783 ; - assign y_avValue_snd_snd_snd_snd_snd__h1022783 = + y_avValue_snd_snd_snd_snd_snd__h1022778 ; + assign y_avValue_snd_snd_snd_snd_snd__h1022778 = IF_rob_deqPort_0_canDeq__3556_THEN_IF_NOT_rob__ETC___d23678 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -38217,28 +38217,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h505382 = + x__h505379 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -38248,10 +38248,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h509900 = + addr__h509897 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h509900 = + addr__h509897 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; endcase end @@ -38260,16 +38260,16 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h215234 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h215234 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h215233 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h215233 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h217587 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h217587 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h217586 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h217586 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -38328,16 +38328,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h267596 = + x__h267593 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17; 2'd1: - x__h267596 = + x__h267593 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd2: - x__h267596 = + x__h267593 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd3: - x__h267596 = + x__h267593 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; endcase end @@ -38345,8 +38345,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h1003714 = commitStage_commitTrap[35:32]; - default: i__h1003714 = 4'd15; + i__h1003709 = commitStage_commitTrap[35:32]; + default: i__h1003709 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -38419,302 +38419,302 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h513050 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h513047 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h513050 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h513047 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h855461 or - frm_csr__read__h855472 or - fcsr_csr__read__h855486 or - sstatus_csr__read__h855682 or - sie_csr__read__h855752 or - scounteren_csr__read__h855805 or + fflags_csr__read__h855458 or + frm_csr__read__h855469 or + fcsr_csr__read__h855483 or + sstatus_csr__read__h855679 or + sie_csr__read__h855749 or + scounteren_csr__read__h855802 or csrf_sscratch_csr or - scause_csr__read__h855900 or + scause_csr__read__h855897 or csrf_stval_csr or - sip_csr__read__h856040 or - satp_csr__read__h856103 or - mstatus_csr__read__h856249 or - medeleg_csr__read__h856403 or - mideleg_csr__read__h856501 or - mie_csr__read__h856628 or - mcounteren_csr__read__h856723 or + sip_csr__read__h856037 or + satp_csr__read__h856100 or + mstatus_csr__read__h856246 or + medeleg_csr__read__h856400 or + mideleg_csr__read__h856498 or + mie_csr__read__h856625 or + mcounteren_csr__read__h856720 or csrf_mscratch_csr or - mcause_csr__read__h856902 or + mcause_csr__read__h856899 or csrf_mtval_csr or - mip_csr__read__h857141 or + mip_csr__read__h857138 or csrf_rg_tselect or - rg_tdata1__read__h858242 or + rg_tdata1__read__h858239 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855591 or + x_reg_ifc__read__h855588 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h902154 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h902150 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1026352 = fflags_csr__read__h855461; - 12'd2: data_out__h1026352 = frm_csr__read__h855472; - 12'd3: data_out__h1026352 = fcsr_csr__read__h855486; - 12'd256: data_out__h1026352 = sstatus_csr__read__h855682; - 12'd260: data_out__h1026352 = sie_csr__read__h855752; - 12'd262: data_out__h1026352 = scounteren_csr__read__h855805; - 12'd320: data_out__h1026352 = csrf_sscratch_csr; - 12'd322: data_out__h1026352 = scause_csr__read__h855900; - 12'd323: data_out__h1026352 = csrf_stval_csr; - 12'd324: data_out__h1026352 = sip_csr__read__h856040; - 12'd384: data_out__h1026352 = satp_csr__read__h856103; - 12'd768: data_out__h1026352 = mstatus_csr__read__h856249; - 12'd769: data_out__h1026352 = 64'h800000000014112D; - 12'd770: data_out__h1026352 = medeleg_csr__read__h856403; - 12'd771: data_out__h1026352 = mideleg_csr__read__h856501; - 12'd772: data_out__h1026352 = mie_csr__read__h856628; - 12'd774: data_out__h1026352 = mcounteren_csr__read__h856723; - 12'd832: data_out__h1026352 = csrf_mscratch_csr; - 12'd834: data_out__h1026352 = mcause_csr__read__h856902; - 12'd835: data_out__h1026352 = csrf_mtval_csr; - 12'd836: data_out__h1026352 = mip_csr__read__h857141; - 12'd1952: data_out__h1026352 = csrf_rg_tselect; - 12'd1953: data_out__h1026352 = rg_tdata1__read__h858242; - 12'd1954: data_out__h1026352 = csrf_rg_tdata2; - 12'd1955: data_out__h1026352 = csrf_rg_tdata3; - 12'd1968: data_out__h1026352 = csrf_rg_dcsr; - 12'd1969: data_out__h1026352 = csrf_rg_dpc[149:86]; - 12'd1970: data_out__h1026352 = csrf_rg_dscratch0; - 12'd1971: data_out__h1026352 = csrf_rg_dscratch1; + 12'd1: data_out__h1026346 = fflags_csr__read__h855458; + 12'd2: data_out__h1026346 = frm_csr__read__h855469; + 12'd3: data_out__h1026346 = fcsr_csr__read__h855483; + 12'd256: data_out__h1026346 = sstatus_csr__read__h855679; + 12'd260: data_out__h1026346 = sie_csr__read__h855749; + 12'd262: data_out__h1026346 = scounteren_csr__read__h855802; + 12'd320: data_out__h1026346 = csrf_sscratch_csr; + 12'd322: data_out__h1026346 = scause_csr__read__h855897; + 12'd323: data_out__h1026346 = csrf_stval_csr; + 12'd324: data_out__h1026346 = sip_csr__read__h856037; + 12'd384: data_out__h1026346 = satp_csr__read__h856100; + 12'd768: data_out__h1026346 = mstatus_csr__read__h856246; + 12'd769: data_out__h1026346 = 64'h800000000014112D; + 12'd770: data_out__h1026346 = medeleg_csr__read__h856400; + 12'd771: data_out__h1026346 = mideleg_csr__read__h856498; + 12'd772: data_out__h1026346 = mie_csr__read__h856625; + 12'd774: data_out__h1026346 = mcounteren_csr__read__h856720; + 12'd832: data_out__h1026346 = csrf_mscratch_csr; + 12'd834: data_out__h1026346 = mcause_csr__read__h856899; + 12'd835: data_out__h1026346 = csrf_mtval_csr; + 12'd836: data_out__h1026346 = mip_csr__read__h857138; + 12'd1952: data_out__h1026346 = csrf_rg_tselect; + 12'd1953: data_out__h1026346 = rg_tdata1__read__h858239; + 12'd1954: data_out__h1026346 = csrf_rg_tdata2; + 12'd1955: data_out__h1026346 = csrf_rg_tdata3; + 12'd1968: data_out__h1026346 = csrf_rg_dcsr; + 12'd1969: data_out__h1026346 = csrf_rg_dpc[149:86]; + 12'd1970: data_out__h1026346 = csrf_rg_dscratch0; + 12'd1971: data_out__h1026346 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1026352 = 64'd0; - 12'd2049: data_out__h1026352 = x_reg_ifc__read__h855591; - 12'd2816, 12'd3072: data_out__h1026352 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1026352 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1026352 = { 48'd0, x__h902154 }; - 12'd3073: data_out__h1026352 = csrf_time_reg; - default: data_out__h1026352 = 64'b0; + data_out__h1026346 = 64'd0; + 12'd2049: data_out__h1026346 = x_reg_ifc__read__h855588; + 12'd2816, 12'd3072: data_out__h1026346 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1026346 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1026346 = { 48'd0, x__h902150 }; + 12'd3073: data_out__h1026346 = csrf_time_reg; + default: data_out__h1026346 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h855461 or - frm_csr__read__h855472 or - fcsr_csr__read__h855486 or - sstatus_csr__read__h855682 or - sie_csr__read__h855752 or - scounteren_csr__read__h855805 or + fflags_csr__read__h855458 or + frm_csr__read__h855469 or + fcsr_csr__read__h855483 or + sstatus_csr__read__h855679 or + sie_csr__read__h855749 or + scounteren_csr__read__h855802 or csrf_sscratch_csr or - scause_csr__read__h855900 or + scause_csr__read__h855897 or csrf_stval_csr or - sip_csr__read__h856040 or - satp_csr__read__h856103 or - mstatus_csr__read__h856249 or - medeleg_csr__read__h856403 or - mideleg_csr__read__h856501 or - mie_csr__read__h856628 or - mcounteren_csr__read__h856723 or + sip_csr__read__h856037 or + satp_csr__read__h856100 or + mstatus_csr__read__h856246 or + medeleg_csr__read__h856400 or + mideleg_csr__read__h856498 or + mie_csr__read__h856625 or + mcounteren_csr__read__h856720 or csrf_mscratch_csr or - mcause_csr__read__h856902 or + mcause_csr__read__h856899 or csrf_mtval_csr or - mip_csr__read__h857141 or + mip_csr__read__h857138 or csrf_rg_tselect or - rg_tdata1__read__h858242 or + rg_tdata1__read__h858239 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855591 or + x_reg_ifc__read__h855588 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h902154 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h902150 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h850180 = fflags_csr__read__h855461; - 12'd2: addr__h850180 = frm_csr__read__h855472; - 12'd3: addr__h850180 = fcsr_csr__read__h855486; - 12'd256: addr__h850180 = sstatus_csr__read__h855682; - 12'd260: addr__h850180 = sie_csr__read__h855752; - 12'd262: addr__h850180 = scounteren_csr__read__h855805; - 12'd320: addr__h850180 = csrf_sscratch_csr; - 12'd322: addr__h850180 = scause_csr__read__h855900; - 12'd323: addr__h850180 = csrf_stval_csr; - 12'd324: addr__h850180 = sip_csr__read__h856040; - 12'd384: addr__h850180 = satp_csr__read__h856103; - 12'd768: addr__h850180 = mstatus_csr__read__h856249; - 12'd769: addr__h850180 = 64'h800000000014112D; - 12'd770: addr__h850180 = medeleg_csr__read__h856403; - 12'd771: addr__h850180 = mideleg_csr__read__h856501; - 12'd772: addr__h850180 = mie_csr__read__h856628; - 12'd774: addr__h850180 = mcounteren_csr__read__h856723; - 12'd832: addr__h850180 = csrf_mscratch_csr; - 12'd834: addr__h850180 = mcause_csr__read__h856902; - 12'd835: addr__h850180 = csrf_mtval_csr; - 12'd836: addr__h850180 = mip_csr__read__h857141; - 12'd1952: addr__h850180 = csrf_rg_tselect; - 12'd1953: addr__h850180 = rg_tdata1__read__h858242; - 12'd1954: addr__h850180 = csrf_rg_tdata2; - 12'd1955: addr__h850180 = csrf_rg_tdata3; - 12'd1968: addr__h850180 = csrf_rg_dcsr; - 12'd1969: addr__h850180 = csrf_rg_dpc[149:86]; - 12'd1970: addr__h850180 = csrf_rg_dscratch0; - 12'd1971: addr__h850180 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h850180 = 64'd0; - 12'd2049: addr__h850180 = x_reg_ifc__read__h855591; - 12'd2816, 12'd3072: addr__h850180 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h850180 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h850180 = { 48'd0, x__h902154 }; - 12'd3073: addr__h850180 = csrf_time_reg; - default: addr__h850180 = 64'b0; + 12'd1: addr__h850177 = fflags_csr__read__h855458; + 12'd2: addr__h850177 = frm_csr__read__h855469; + 12'd3: addr__h850177 = fcsr_csr__read__h855483; + 12'd256: addr__h850177 = sstatus_csr__read__h855679; + 12'd260: addr__h850177 = sie_csr__read__h855749; + 12'd262: addr__h850177 = scounteren_csr__read__h855802; + 12'd320: addr__h850177 = csrf_sscratch_csr; + 12'd322: addr__h850177 = scause_csr__read__h855897; + 12'd323: addr__h850177 = csrf_stval_csr; + 12'd324: addr__h850177 = sip_csr__read__h856037; + 12'd384: addr__h850177 = satp_csr__read__h856100; + 12'd768: addr__h850177 = mstatus_csr__read__h856246; + 12'd769: addr__h850177 = 64'h800000000014112D; + 12'd770: addr__h850177 = medeleg_csr__read__h856400; + 12'd771: addr__h850177 = mideleg_csr__read__h856498; + 12'd772: addr__h850177 = mie_csr__read__h856625; + 12'd774: addr__h850177 = mcounteren_csr__read__h856720; + 12'd832: addr__h850177 = csrf_mscratch_csr; + 12'd834: addr__h850177 = mcause_csr__read__h856899; + 12'd835: addr__h850177 = csrf_mtval_csr; + 12'd836: addr__h850177 = mip_csr__read__h857138; + 12'd1952: addr__h850177 = csrf_rg_tselect; + 12'd1953: addr__h850177 = rg_tdata1__read__h858239; + 12'd1954: addr__h850177 = csrf_rg_tdata2; + 12'd1955: addr__h850177 = csrf_rg_tdata3; + 12'd1968: addr__h850177 = csrf_rg_dcsr; + 12'd1969: addr__h850177 = csrf_rg_dpc[149:86]; + 12'd1970: addr__h850177 = csrf_rg_dscratch0; + 12'd1971: addr__h850177 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h850177 = 64'd0; + 12'd2049: addr__h850177 = x_reg_ifc__read__h855588; + 12'd2816, 12'd3072: addr__h850177 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h850177 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h850177 = { 48'd0, x__h902150 }; + 12'd3073: addr__h850177 = csrf_time_reg; + default: addr__h850177 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h855461 or - frm_csr__read__h855472 or - fcsr_csr__read__h855486 or - sstatus_csr__read__h855682 or - sie_csr__read__h855752 or - scounteren_csr__read__h855805 or + fflags_csr__read__h855458 or + frm_csr__read__h855469 or + fcsr_csr__read__h855483 or + sstatus_csr__read__h855679 or + sie_csr__read__h855749 or + scounteren_csr__read__h855802 or csrf_sscratch_csr or - scause_csr__read__h855900 or + scause_csr__read__h855897 or csrf_stval_csr or - sip_csr__read__h856040 or - satp_csr__read__h856103 or - mstatus_csr__read__h856249 or - medeleg_csr__read__h856403 or - mideleg_csr__read__h856501 or - mie_csr__read__h856628 or - mcounteren_csr__read__h856723 or + sip_csr__read__h856037 or + satp_csr__read__h856100 or + mstatus_csr__read__h856246 or + medeleg_csr__read__h856400 or + mideleg_csr__read__h856498 or + mie_csr__read__h856625 or + mcounteren_csr__read__h856720 or csrf_mscratch_csr or - mcause_csr__read__h856902 or + mcause_csr__read__h856899 or csrf_mtval_csr or - mip_csr__read__h857141 or + mip_csr__read__h857138 or csrf_rg_tselect or - rg_tdata1__read__h858242 or + rg_tdata1__read__h858239 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855591 or + x_reg_ifc__read__h855588 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h902154 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h902150 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h893851 = fflags_csr__read__h855461; - 12'd2: addr__h893851 = frm_csr__read__h855472; - 12'd3: addr__h893851 = fcsr_csr__read__h855486; - 12'd256: addr__h893851 = sstatus_csr__read__h855682; - 12'd260: addr__h893851 = sie_csr__read__h855752; - 12'd262: addr__h893851 = scounteren_csr__read__h855805; - 12'd320: addr__h893851 = csrf_sscratch_csr; - 12'd322: addr__h893851 = scause_csr__read__h855900; - 12'd323: addr__h893851 = csrf_stval_csr; - 12'd324: addr__h893851 = sip_csr__read__h856040; - 12'd384: addr__h893851 = satp_csr__read__h856103; - 12'd768: addr__h893851 = mstatus_csr__read__h856249; - 12'd769: addr__h893851 = 64'h800000000014112D; - 12'd770: addr__h893851 = medeleg_csr__read__h856403; - 12'd771: addr__h893851 = mideleg_csr__read__h856501; - 12'd772: addr__h893851 = mie_csr__read__h856628; - 12'd774: addr__h893851 = mcounteren_csr__read__h856723; - 12'd832: addr__h893851 = csrf_mscratch_csr; - 12'd834: addr__h893851 = mcause_csr__read__h856902; - 12'd835: addr__h893851 = csrf_mtval_csr; - 12'd836: addr__h893851 = mip_csr__read__h857141; - 12'd1952: addr__h893851 = csrf_rg_tselect; - 12'd1953: addr__h893851 = rg_tdata1__read__h858242; - 12'd1954: addr__h893851 = csrf_rg_tdata2; - 12'd1955: addr__h893851 = csrf_rg_tdata3; - 12'd1968: addr__h893851 = csrf_rg_dcsr; - 12'd1969: addr__h893851 = csrf_rg_dpc[149:86]; - 12'd1970: addr__h893851 = csrf_rg_dscratch0; - 12'd1971: addr__h893851 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h893851 = 64'd0; - 12'd2049: addr__h893851 = x_reg_ifc__read__h855591; - 12'd2816, 12'd3072: addr__h893851 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h893851 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h893851 = { 48'd0, x__h902154 }; - 12'd3073: addr__h893851 = csrf_time_reg; - default: addr__h893851 = 64'b0; + 12'd1: addr__h893847 = fflags_csr__read__h855458; + 12'd2: addr__h893847 = frm_csr__read__h855469; + 12'd3: addr__h893847 = fcsr_csr__read__h855483; + 12'd256: addr__h893847 = sstatus_csr__read__h855679; + 12'd260: addr__h893847 = sie_csr__read__h855749; + 12'd262: addr__h893847 = scounteren_csr__read__h855802; + 12'd320: addr__h893847 = csrf_sscratch_csr; + 12'd322: addr__h893847 = scause_csr__read__h855897; + 12'd323: addr__h893847 = csrf_stval_csr; + 12'd324: addr__h893847 = sip_csr__read__h856037; + 12'd384: addr__h893847 = satp_csr__read__h856100; + 12'd768: addr__h893847 = mstatus_csr__read__h856246; + 12'd769: addr__h893847 = 64'h800000000014112D; + 12'd770: addr__h893847 = medeleg_csr__read__h856400; + 12'd771: addr__h893847 = mideleg_csr__read__h856498; + 12'd772: addr__h893847 = mie_csr__read__h856625; + 12'd774: addr__h893847 = mcounteren_csr__read__h856720; + 12'd832: addr__h893847 = csrf_mscratch_csr; + 12'd834: addr__h893847 = mcause_csr__read__h856899; + 12'd835: addr__h893847 = csrf_mtval_csr; + 12'd836: addr__h893847 = mip_csr__read__h857138; + 12'd1952: addr__h893847 = csrf_rg_tselect; + 12'd1953: addr__h893847 = rg_tdata1__read__h858239; + 12'd1954: addr__h893847 = csrf_rg_tdata2; + 12'd1955: addr__h893847 = csrf_rg_tdata3; + 12'd1968: addr__h893847 = csrf_rg_dcsr; + 12'd1969: addr__h893847 = csrf_rg_dpc[149:86]; + 12'd1970: addr__h893847 = csrf_rg_dscratch0; + 12'd1971: addr__h893847 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h893847 = 64'd0; + 12'd2049: addr__h893847 = x_reg_ifc__read__h855588; + 12'd2816, 12'd3072: addr__h893847 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h893847 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h893847 = { 48'd0, x__h902150 }; + 12'd3073: addr__h893847 = csrf_time_reg; + default: addr__h893847 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h580787 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h580784 = 8'd255; 3'd2: - _theResult___fst_exp__h580787 = + _theResult___fst_exp__h580784 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h580787 = + _theResult___fst_exp__h580784 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h580787 = 8'd254; - default: _theResult___fst_exp__h580787 = 8'd0; + 3'd4: _theResult___fst_exp__h580784 = 8'd254; + default: _theResult___fst_exp__h580784 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h580788 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h580785 = 23'd0; 3'd2: - _theResult___fst_sfd__h580788 = + _theResult___fst_sfd__h580785 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h580788 = + _theResult___fst_sfd__h580785 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h580788 = 23'd8388607; - default: _theResult___fst_sfd__h580788 = 23'd0; + 3'd4: _theResult___fst_sfd__h580785 = 23'd8388607; + default: _theResult___fst_sfd__h580785 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h626538 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h626535 = 8'd255; 3'd2: - _theResult___fst_exp__h626538 = + _theResult___fst_exp__h626535 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h626538 = + _theResult___fst_exp__h626535 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h626538 = 8'd254; - default: _theResult___fst_exp__h626538 = 8'd0; + 3'd4: _theResult___fst_exp__h626535 = 8'd254; + default: _theResult___fst_exp__h626535 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h626539 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h626536 = 23'd0; 3'd2: - _theResult___fst_sfd__h626539 = + _theResult___fst_sfd__h626536 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h626539 = + _theResult___fst_sfd__h626536 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h626539 = 23'd8388607; - default: _theResult___fst_sfd__h626539 = 23'd0; + 3'd4: _theResult___fst_sfd__h626536 = 23'd8388607; + default: _theResult___fst_sfd__h626536 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -38742,38 +38742,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h672285 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h672282 = 8'd255; 3'd2: - _theResult___fst_exp__h672285 = + _theResult___fst_exp__h672282 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h672285 = + _theResult___fst_exp__h672282 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h672285 = 8'd254; - default: _theResult___fst_exp__h672285 = 8'd0; + 3'd4: _theResult___fst_exp__h672282 = 8'd254; + default: _theResult___fst_exp__h672282 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h672286 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h672283 = 23'd0; 3'd2: - _theResult___fst_sfd__h672286 = + _theResult___fst_sfd__h672283 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h672286 = + _theResult___fst_sfd__h672283 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h672286 = 23'd8388607; - default: _theResult___fst_sfd__h672286 = 23'd0; + 3'd4: _theResult___fst_sfd__h672283 = 23'd8388607; + default: _theResult___fst_sfd__h672283 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -38904,16 +38904,16 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h1003540 = commitStage_commitTrap[36:32]; - default: i__h1003540 = 5'd28; + i__h1003535 = commitStage_commitTrap[36:32]; + default: i__h1003535 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h1005062 or i__h1003540) + always@(commitStage_commitTrap or cause_code__h1005057 or i__h1003535) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h1003524 = 5'd28; - 2'd1: cause_code__h1003524 = i__h1003540; - default: cause_code__h1003524 = cause_code__h1005062; + 2'd0: cause_code__h1003519 = 5'd28; + 2'd1: cause_code__h1003519 = i__h1003535; + default: cause_code__h1003519 = cause_code__h1005057; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -39203,16 +39203,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h267751 = + x__h267748 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4869[31:0]; 2'd1: - x__h267751 = + x__h267748 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4869[63:32]; 2'd2: - x__h267751 = + x__h267748 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4863[31:0]; 2'd3: - x__h267751 = + x__h267748 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4863[63:32]; endcase end @@ -39376,446 +39376,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[516]; endcase end - always@(guard__h589524 or - _theResult___fst_exp__h597572 or - out_exp__h598017 or _theResult___exp__h598014) + always@(guard__h589521 or + _theResult___fst_exp__h597569 or + out_exp__h598014 or _theResult___exp__h598011) begin - case (guard__h589524) + case (guard__h589521) 2'b0, 2'b01: - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q44 = - _theResult___fst_exp__h597572; + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q44 = + _theResult___fst_exp__h597569; 2'b10: - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q44 = - out_exp__h598017; + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q44 = + out_exp__h598014; 2'b11: - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q44 = - _theResult___exp__h598014; + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q44 = + _theResult___exp__h598011; endcase end - always@(guard__h589524 or - _theResult___fst_exp__h597572 or _theResult___exp__h598014) + always@(guard__h589521 or + _theResult___fst_exp__h597569 or _theResult___exp__h598011) begin - case (guard__h589524) + case (guard__h589521) 2'b0: - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q45 = - _theResult___fst_exp__h597572; + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q45 = + _theResult___fst_exp__h597569; 2'b01, 2'b10, 2'b11: - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q45 = - _theResult___exp__h598014; + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q45 = + _theResult___exp__h598011; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q44 or - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q45 or + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q44 or + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q45 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8728 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8730 or - _theResult___fst_exp__h597572) + _theResult___fst_exp__h597569) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h598092 = - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q44; + _theResult___fst_exp__h598089 = + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q44; 3'd1: - _theResult___fst_exp__h598092 = - CASE_guard89524_0b0_theResult___fst_exp97572_0_ETC__q45; + _theResult___fst_exp__h598089 = + CASE_guard89521_0b0_theResult___fst_exp97569_0_ETC__q45; 3'd2: - _theResult___fst_exp__h598092 = + _theResult___fst_exp__h598089 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8728; 3'd3: - _theResult___fst_exp__h598092 = + _theResult___fst_exp__h598089 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8730; - 3'd4: _theResult___fst_exp__h598092 = _theResult___fst_exp__h597572; - default: _theResult___fst_exp__h598092 = 8'd0; + 3'd4: _theResult___fst_exp__h598089 = _theResult___fst_exp__h597569; + default: _theResult___fst_exp__h598089 = 8'd0; endcase end - always@(guard__h580815 or - _theResult___fst_exp__h588916 or - out_exp__h589435 or _theResult___exp__h589432) + always@(guard__h580812 or + _theResult___fst_exp__h588913 or + out_exp__h589432 or _theResult___exp__h589429) begin - case (guard__h580815) + case (guard__h580812) 2'b0, 2'b01: - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q46 = - _theResult___fst_exp__h588916; + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q46 = + _theResult___fst_exp__h588913; 2'b10: - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q46 = - out_exp__h589435; + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q46 = + out_exp__h589432; 2'b11: - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q46 = - _theResult___exp__h589432; + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q46 = + _theResult___exp__h589429; endcase end - always@(guard__h580815 or - _theResult___fst_exp__h588916 or _theResult___exp__h589432) + always@(guard__h580812 or + _theResult___fst_exp__h588913 or _theResult___exp__h589429) begin - case (guard__h580815) + case (guard__h580812) 2'b0: - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q47 = - _theResult___fst_exp__h588916; + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q47 = + _theResult___fst_exp__h588913; 2'b01, 2'b10, 2'b11: - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q47 = - _theResult___exp__h589432; + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q47 = + _theResult___exp__h589429; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q46 or - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q47 or + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q46 or + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q47 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8506 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8509 or - _theResult___fst_exp__h588916) + _theResult___fst_exp__h588913) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h589510 = - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q46; + _theResult___fst_exp__h589507 = + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q46; 3'd1: - _theResult___fst_exp__h589510 = - CASE_guard80815_0b0_theResult___fst_exp88916_0_ETC__q47; + _theResult___fst_exp__h589507 = + CASE_guard80812_0b0_theResult___fst_exp88913_0_ETC__q47; 3'd2: - _theResult___fst_exp__h589510 = + _theResult___fst_exp__h589507 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8506; 3'd3: - _theResult___fst_exp__h589510 = + _theResult___fst_exp__h589507 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8509; - 3'd4: _theResult___fst_exp__h589510 = _theResult___fst_exp__h588916; - default: _theResult___fst_exp__h589510 = 8'd0; + 3'd4: _theResult___fst_exp__h589507 = _theResult___fst_exp__h588913; + default: _theResult___fst_exp__h589507 = 8'd0; endcase end - always@(guard__h598454 or - _theResult___fst_exp__h606682 or - out_exp__h607201 or _theResult___exp__h607198) + always@(guard__h598451 or + _theResult___fst_exp__h606679 or + out_exp__h607198 or _theResult___exp__h607195) begin - case (guard__h598454) + case (guard__h598451) 2'b0, 2'b01: - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q52 = - _theResult___fst_exp__h606682; + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q52 = + _theResult___fst_exp__h606679; 2'b10: - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q52 = - out_exp__h607201; + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q52 = + out_exp__h607198; 2'b11: - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q52 = - _theResult___exp__h607198; + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q52 = + _theResult___exp__h607195; endcase end - always@(guard__h598454 or - _theResult___fst_exp__h606682 or _theResult___exp__h607198) + always@(guard__h598451 or + _theResult___fst_exp__h606679 or _theResult___exp__h607195) begin - case (guard__h598454) + case (guard__h598451) 2'b0: - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q53 = - _theResult___fst_exp__h606682; + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q53 = + _theResult___fst_exp__h606679; 2'b01, 2'b10, 2'b11: - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q53 = - _theResult___exp__h607198; + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q53 = + _theResult___exp__h607195; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q52 or - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q53 or + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q52 or + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q53 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9053 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9055 or - _theResult___fst_exp__h606682) + _theResult___fst_exp__h606679) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h607276 = - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q52; + _theResult___fst_exp__h607273 = + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q52; 3'd1: - _theResult___fst_exp__h607276 = - CASE_guard98454_0b0_theResult___fst_exp06682_0_ETC__q53; + _theResult___fst_exp__h607273 = + CASE_guard98451_0b0_theResult___fst_exp06679_0_ETC__q53; 3'd2: - _theResult___fst_exp__h607276 = + _theResult___fst_exp__h607273 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9053; 3'd3: - _theResult___fst_exp__h607276 = + _theResult___fst_exp__h607273 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9055; - 3'd4: _theResult___fst_exp__h607276 = _theResult___fst_exp__h606682; - default: _theResult___fst_exp__h607276 = 8'd0; + 3'd4: _theResult___fst_exp__h607273 = _theResult___fst_exp__h606679; + default: _theResult___fst_exp__h607273 = 8'd0; endcase end - always@(guard__h607290 or - _theResult___fst_exp__h615367 or - out_exp__h615837 or _theResult___exp__h615834) + always@(guard__h607287 or + _theResult___fst_exp__h615364 or + out_exp__h615834 or _theResult___exp__h615831) begin - case (guard__h607290) + case (guard__h607287) 2'b0, 2'b01: - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q57 = - _theResult___fst_exp__h615367; + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q57 = + _theResult___fst_exp__h615364; 2'b10: - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q57 = - out_exp__h615837; + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q57 = + out_exp__h615834; 2'b11: - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q57 = - _theResult___exp__h615834; + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q57 = + _theResult___exp__h615831; endcase end - always@(guard__h607290 or - _theResult___fst_exp__h615367 or _theResult___exp__h615834) + always@(guard__h607287 or + _theResult___fst_exp__h615364 or _theResult___exp__h615831) begin - case (guard__h607290) + case (guard__h607287) 2'b0: - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q58 = - _theResult___fst_exp__h615367; + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q58 = + _theResult___fst_exp__h615364; 2'b01, 2'b10, 2'b11: - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q58 = - _theResult___exp__h615834; + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q58 = + _theResult___exp__h615831; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q57 or - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q58 or + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q57 or + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q58 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9122 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9124 or - _theResult___fst_exp__h615367) + _theResult___fst_exp__h615364) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h615912 = - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q57; + _theResult___fst_exp__h615909 = + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q57; 3'd1: - _theResult___fst_exp__h615912 = - CASE_guard07290_0b0_theResult___fst_exp15367_0_ETC__q58; + _theResult___fst_exp__h615909 = + CASE_guard07287_0b0_theResult___fst_exp15364_0_ETC__q58; 3'd2: - _theResult___fst_exp__h615912 = + _theResult___fst_exp__h615909 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9122; 3'd3: - _theResult___fst_exp__h615912 = + _theResult___fst_exp__h615909 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9124; - 3'd4: _theResult___fst_exp__h615912 = _theResult___fst_exp__h615367; - default: _theResult___fst_exp__h615912 = 8'd0; + 3'd4: _theResult___fst_exp__h615909 = _theResult___fst_exp__h615364; + default: _theResult___fst_exp__h615909 = 8'd0; endcase end - always@(guard__h589524 or - _theResult___snd__h597523 or - out_sfd__h598018 or _theResult___sfd__h598015) + always@(guard__h589521 or + _theResult___snd__h597520 or + out_sfd__h598015 or _theResult___sfd__h598012) begin - case (guard__h589524) + case (guard__h589521) 2'b0, 2'b01: - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q59 = - _theResult___snd__h597523[56:34]; + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q59 = + _theResult___snd__h597520[56:34]; 2'b10: - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q59 = - out_sfd__h598018; + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q59 = + out_sfd__h598015; 2'b11: - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q59 = - _theResult___sfd__h598015; + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q59 = + _theResult___sfd__h598012; endcase end - always@(guard__h589524 or - _theResult___snd__h597523 or _theResult___sfd__h598015) + always@(guard__h589521 or + _theResult___snd__h597520 or _theResult___sfd__h598012) begin - case (guard__h589524) + case (guard__h589521) 2'b0: - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q60 = - _theResult___snd__h597523[56:34]; + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q60 = + _theResult___snd__h597520[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q60 = - _theResult___sfd__h598015; + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q60 = + _theResult___sfd__h598012; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q59 or - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q60 or + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q59 or + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q60 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9172 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9174 or - _theResult___snd__h597523) + _theResult___snd__h597520) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h598093 = - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q59; + _theResult___fst_sfd__h598090 = + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q59; 3'd1: - _theResult___fst_sfd__h598093 = - CASE_guard89524_0b0_theResult___snd97523_BITS__ETC__q60; + _theResult___fst_sfd__h598090 = + CASE_guard89521_0b0_theResult___snd97520_BITS__ETC__q60; 3'd2: - _theResult___fst_sfd__h598093 = + _theResult___fst_sfd__h598090 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9172; 3'd3: - _theResult___fst_sfd__h598093 = + _theResult___fst_sfd__h598090 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9174; - 3'd4: _theResult___fst_sfd__h598093 = _theResult___snd__h597523[56:34]; - default: _theResult___fst_sfd__h598093 = 23'd0; + 3'd4: _theResult___fst_sfd__h598090 = _theResult___snd__h597520[56:34]; + default: _theResult___fst_sfd__h598090 = 23'd0; endcase end - always@(guard__h580815 or - sfdin__h588910 or out_sfd__h589436 or _theResult___sfd__h589433) + always@(guard__h580812 or + sfdin__h588907 or out_sfd__h589433 or _theResult___sfd__h589430) begin - case (guard__h580815) + case (guard__h580812) 2'b0, 2'b01: - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q61 = - sfdin__h588910[56:34]; + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q61 = + sfdin__h588907[56:34]; 2'b10: - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q61 = - out_sfd__h589436; + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q61 = + out_sfd__h589433; 2'b11: - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q61 = - _theResult___sfd__h589433; + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q61 = + _theResult___sfd__h589430; endcase end - always@(guard__h580815 or sfdin__h588910 or _theResult___sfd__h589433) + always@(guard__h580812 or sfdin__h588907 or _theResult___sfd__h589430) begin - case (guard__h580815) + case (guard__h580812) 2'b0: - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q62 = - sfdin__h588910[56:34]; + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q62 = + sfdin__h588907[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q62 = - _theResult___sfd__h589433; + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q62 = + _theResult___sfd__h589430; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q61 or - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q62 or + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q61 or + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q62 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9153 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9155 or - sfdin__h588910) + sfdin__h588907) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h589511 = - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q61; + _theResult___fst_sfd__h589508 = + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q61; 3'd1: - _theResult___fst_sfd__h589511 = - CASE_guard80815_0b0_sfdin88910_BITS_56_TO_34_0_ETC__q62; + _theResult___fst_sfd__h589508 = + CASE_guard80812_0b0_sfdin88907_BITS_56_TO_34_0_ETC__q62; 3'd2: - _theResult___fst_sfd__h589511 = + _theResult___fst_sfd__h589508 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9153; 3'd3: - _theResult___fst_sfd__h589511 = + _theResult___fst_sfd__h589508 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9155; - 3'd4: _theResult___fst_sfd__h589511 = sfdin__h588910[56:34]; - default: _theResult___fst_sfd__h589511 = 23'd0; + 3'd4: _theResult___fst_sfd__h589508 = sfdin__h588907[56:34]; + default: _theResult___fst_sfd__h589508 = 23'd0; endcase end - always@(guard__h598454 or - sfdin__h606676 or out_sfd__h607202 or _theResult___sfd__h607199) + always@(guard__h598451 or + sfdin__h606673 or out_sfd__h607199 or _theResult___sfd__h607196) begin - case (guard__h598454) + case (guard__h598451) 2'b0, 2'b01: - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q63 = - sfdin__h606676[56:34]; + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q63 = + sfdin__h606673[56:34]; 2'b10: - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q63 = - out_sfd__h607202; + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q63 = + out_sfd__h607199; 2'b11: - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q63 = - _theResult___sfd__h607199; + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q63 = + _theResult___sfd__h607196; endcase end - always@(guard__h598454 or sfdin__h606676 or _theResult___sfd__h607199) + always@(guard__h598451 or sfdin__h606673 or _theResult___sfd__h607196) begin - case (guard__h598454) + case (guard__h598451) 2'b0: - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q64 = - sfdin__h606676[56:34]; + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q64 = + sfdin__h606673[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q64 = - _theResult___sfd__h607199; + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q64 = + _theResult___sfd__h607196; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q63 or - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q64 or + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q63 or + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q64 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9199 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9201 or - sfdin__h606676) + sfdin__h606673) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h607277 = - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q63; + _theResult___fst_sfd__h607274 = + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q63; 3'd1: - _theResult___fst_sfd__h607277 = - CASE_guard98454_0b0_sfdin06676_BITS_56_TO_34_0_ETC__q64; + _theResult___fst_sfd__h607274 = + CASE_guard98451_0b0_sfdin06673_BITS_56_TO_34_0_ETC__q64; 3'd2: - _theResult___fst_sfd__h607277 = + _theResult___fst_sfd__h607274 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9199; 3'd3: - _theResult___fst_sfd__h607277 = + _theResult___fst_sfd__h607274 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9201; - 3'd4: _theResult___fst_sfd__h607277 = sfdin__h606676[56:34]; - default: _theResult___fst_sfd__h607277 = 23'd0; + 3'd4: _theResult___fst_sfd__h607274 = sfdin__h606673[56:34]; + default: _theResult___fst_sfd__h607274 = 23'd0; endcase end - always@(guard__h607290 or - _theResult___snd__h615313 or - out_sfd__h615838 or _theResult___sfd__h615835) + always@(guard__h607287 or + _theResult___snd__h615310 or + out_sfd__h615835 or _theResult___sfd__h615832) begin - case (guard__h607290) + case (guard__h607287) 2'b0, 2'b01: - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q65 = - _theResult___snd__h615313[56:34]; + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q65 = + _theResult___snd__h615310[56:34]; 2'b10: - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q65 = - out_sfd__h615838; + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q65 = + out_sfd__h615835; 2'b11: - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q65 = - _theResult___sfd__h615835; + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q65 = + _theResult___sfd__h615832; endcase end - always@(guard__h607290 or - _theResult___snd__h615313 or _theResult___sfd__h615835) + always@(guard__h607287 or + _theResult___snd__h615310 or _theResult___sfd__h615832) begin - case (guard__h607290) + case (guard__h607287) 2'b0: - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q66 = - _theResult___snd__h615313[56:34]; + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q66 = + _theResult___snd__h615310[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q66 = - _theResult___sfd__h615835; + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q66 = + _theResult___sfd__h615832; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q65 or - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q66 or + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q65 or + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q66 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9218 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9220 or - _theResult___snd__h615313) + _theResult___snd__h615310) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h615913 = - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q65; + _theResult___fst_sfd__h615910 = + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q65; 3'd1: - _theResult___fst_sfd__h615913 = - CASE_guard07290_0b0_theResult___snd15313_BITS__ETC__q66; + _theResult___fst_sfd__h615910 = + CASE_guard07287_0b0_theResult___snd15310_BITS__ETC__q66; 3'd2: - _theResult___fst_sfd__h615913 = + _theResult___fst_sfd__h615910 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9218; 3'd3: - _theResult___fst_sfd__h615913 = + _theResult___fst_sfd__h615910 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9220; - 3'd4: _theResult___fst_sfd__h615913 = _theResult___snd__h615313[56:34]; - default: _theResult___fst_sfd__h615913 = 23'd0; + 3'd4: _theResult___fst_sfd__h615910 = _theResult___snd__h615310[56:34]; + default: _theResult___fst_sfd__h615910 = 23'd0; endcase end - always@(guard__h580815 or + always@(guard__h580812 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h580815) + case (guard__h580812) 2'b0, 2'b01, 2'b10: - CASE_guard80815_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = + CASE_guard80812_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard80815_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = - guard__h580815 == 2'b11 && + CASE_guard80812_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = + guard__h580812 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard80815_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 or - guard__h580815) + CASE_guard80812_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 or + guard__h580812) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9306 = - CASE_guard80815_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67; + CASE_guard80812_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9306 = - (guard__h580815 == 2'b0) ? + (guard__h580812 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h580815 == 2'b01 || guard__h580815 == 2'b10 || - guard__h580815 == 2'b11) && + (guard__h580812 == 2'b01 || guard__h580812 == 2'b10 || + guard__h580812 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9306 = @@ -39826,34 +39826,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h580815 or + always@(guard__h580812 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h580815) + case (guard__h580812) 2'b0, 2'b01, 2'b10: - CASE_guard80815_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = + CASE_guard80812_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard80815_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = - guard__h580815 != 2'b11 || + CASE_guard80812_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = + guard__h580812 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard80815_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 or - guard__h580815) + CASE_guard80812_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 or + guard__h580812) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = - CASE_guard80815_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68; + CASE_guard80812_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = - (guard__h580815 == 2'b0) ? + (guard__h580812 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h580815 != 2'b01 && guard__h580815 != 2'b10 && - guard__h580815 != 2'b11 || + guard__h580812 != 2'b01 && guard__h580812 != 2'b10 && + guard__h580812 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = @@ -39864,34 +39864,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h589524 or + always@(guard__h589521 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h589524) + case (guard__h589521) 2'b0, 2'b01, 2'b10: - CASE_guard89524_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = + CASE_guard89521_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard89524_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = - guard__h589524 == 2'b11 && + CASE_guard89521_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = + guard__h589521 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard89524_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 or - guard__h589524) + CASE_guard89521_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 or + guard__h589521) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9313 = - CASE_guard89524_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69; + CASE_guard89521_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9313 = - (guard__h589524 == 2'b0) ? + (guard__h589521 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h589524 == 2'b01 || guard__h589524 == 2'b10 || - guard__h589524 == 2'b11) && + (guard__h589521 == 2'b01 || guard__h589521 == 2'b10 || + guard__h589521 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9313 = @@ -39902,34 +39902,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h589524 or + always@(guard__h589521 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h589524) + case (guard__h589521) 2'b0, 2'b01, 2'b10: - CASE_guard89524_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = + CASE_guard89521_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard89524_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = - guard__h589524 != 2'b11 || + CASE_guard89521_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = + guard__h589521 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard89524_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 or - guard__h589524) + CASE_guard89521_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 or + guard__h589521) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9263 = - CASE_guard89524_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70; + CASE_guard89521_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9263 = - (guard__h589524 == 2'b0) ? + (guard__h589521 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h589524 != 2'b01 && guard__h589524 != 2'b10 && - guard__h589524 != 2'b11 || + guard__h589521 != 2'b01 && guard__h589521 != 2'b10 && + guard__h589521 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9263 = @@ -39940,34 +39940,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h598454 or + always@(guard__h598451 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h598454) + case (guard__h598451) 2'b0, 2'b01, 2'b10: - CASE_guard98454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + CASE_guard98451_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard98454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = - guard__h598454 == 2'b11 && + CASE_guard98451_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + guard__h598451 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard98454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 or - guard__h598454) + CASE_guard98451_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 or + guard__h598451) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9323 = - CASE_guard98454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71; + CASE_guard98451_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9323 = - (guard__h598454 == 2'b0) ? + (guard__h598451 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h598454 == 2'b01 || guard__h598454 == 2'b10 || - guard__h598454 == 2'b11) && + (guard__h598451 == 2'b01 || guard__h598451 == 2'b10 || + guard__h598451 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9323 = @@ -39978,34 +39978,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h598454 or + always@(guard__h598451 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h598454) + case (guard__h598451) 2'b0, 2'b01, 2'b10: - CASE_guard98454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = + CASE_guard98451_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard98454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = - guard__h598454 != 2'b11 || + CASE_guard98451_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = + guard__h598451 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard98454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 or - guard__h598454) + CASE_guard98451_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 or + guard__h598451) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9280 = - CASE_guard98454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72; + CASE_guard98451_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9280 = - (guard__h598454 == 2'b0) ? + (guard__h598451 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h598454 != 2'b01 && guard__h598454 != 2'b10 && - guard__h598454 != 2'b11 || + guard__h598451 != 2'b01 && guard__h598451 != 2'b10 && + guard__h598451 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9280 = @@ -40016,34 +40016,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h607290 or + always@(guard__h607287 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h607290) + case (guard__h607287) 2'b0, 2'b01, 2'b10: - CASE_guard07290_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = + CASE_guard07287_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard07290_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = - guard__h607290 == 2'b11 && + CASE_guard07287_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = + guard__h607287 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard07290_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 or - guard__h607290) + CASE_guard07287_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 or + guard__h607287) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9330 = - CASE_guard07290_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73; + CASE_guard07287_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9330 = - (guard__h607290 == 2'b0) ? + (guard__h607287 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h607290 == 2'b01 || guard__h607290 == 2'b10 || - guard__h607290 == 2'b11) && + (guard__h607287 == 2'b01 || guard__h607287 == 2'b10 || + guard__h607287 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9330 = @@ -40054,34 +40054,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h607290 or + always@(guard__h607287 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h607290) + case (guard__h607287) 2'b0, 2'b01, 2'b10: - CASE_guard07290_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = + CASE_guard07287_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard07290_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = - guard__h607290 != 2'b11 || + CASE_guard07287_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = + guard__h607287 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard07290_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 or - guard__h607290) + CASE_guard07287_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 or + guard__h607287) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9293 = - CASE_guard07290_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74; + CASE_guard07287_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9293 = - (guard__h607290 == 2'b0) ? + (guard__h607287 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h607290 != 2'b01 && guard__h607290 != 2'b10 && - guard__h607290 != 2'b11 || + guard__h607287 != 2'b01 && guard__h607287 != 2'b10 && + guard__h607287 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9293 = @@ -40118,446 +40118,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h635273 or - _theResult___fst_exp__h643321 or - out_exp__h643766 or _theResult___exp__h643763) + always@(guard__h635270 or + _theResult___fst_exp__h643318 or + out_exp__h643763 or _theResult___exp__h643760) begin - case (guard__h635273) + case (guard__h635270) 2'b0, 2'b01: - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q79 = - _theResult___fst_exp__h643321; + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q79 = + _theResult___fst_exp__h643318; 2'b10: - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q79 = - out_exp__h643766; + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q79 = + out_exp__h643763; 2'b11: - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q79 = - _theResult___exp__h643763; + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q79 = + _theResult___exp__h643760; endcase end - always@(guard__h635273 or - _theResult___fst_exp__h643321 or _theResult___exp__h643763) + always@(guard__h635270 or + _theResult___fst_exp__h643318 or _theResult___exp__h643760) begin - case (guard__h635273) + case (guard__h635270) 2'b0: - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q80 = - _theResult___fst_exp__h643321; + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q80 = + _theResult___fst_exp__h643318; 2'b01, 2'b10, 2'b11: - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q80 = - _theResult___exp__h643763; + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q80 = + _theResult___exp__h643760; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q79 or - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q80 or + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q79 or + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q80 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10125 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10127 or - _theResult___fst_exp__h643321) + _theResult___fst_exp__h643318) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h643841 = - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q79; + _theResult___fst_exp__h643838 = + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q79; 3'd1: - _theResult___fst_exp__h643841 = - CASE_guard35273_0b0_theResult___fst_exp43321_0_ETC__q80; + _theResult___fst_exp__h643838 = + CASE_guard35270_0b0_theResult___fst_exp43318_0_ETC__q80; 3'd2: - _theResult___fst_exp__h643841 = + _theResult___fst_exp__h643838 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10125; 3'd3: - _theResult___fst_exp__h643841 = + _theResult___fst_exp__h643838 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10127; - 3'd4: _theResult___fst_exp__h643841 = _theResult___fst_exp__h643321; - default: _theResult___fst_exp__h643841 = 8'd0; + 3'd4: _theResult___fst_exp__h643838 = _theResult___fst_exp__h643318; + default: _theResult___fst_exp__h643838 = 8'd0; endcase end - always@(guard__h626566 or - _theResult___fst_exp__h634665 or - out_exp__h635184 or _theResult___exp__h635181) + always@(guard__h626563 or + _theResult___fst_exp__h634662 or + out_exp__h635181 or _theResult___exp__h635178) begin - case (guard__h626566) + case (guard__h626563) 2'b0, 2'b01: - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q81 = - _theResult___fst_exp__h634665; + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q81 = + _theResult___fst_exp__h634662; 2'b10: - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q81 = - out_exp__h635184; + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q81 = + out_exp__h635181; 2'b11: - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q81 = - _theResult___exp__h635181; + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q81 = + _theResult___exp__h635178; endcase end - always@(guard__h626566 or - _theResult___fst_exp__h634665 or _theResult___exp__h635181) + always@(guard__h626563 or + _theResult___fst_exp__h634662 or _theResult___exp__h635178) begin - case (guard__h626566) + case (guard__h626563) 2'b0: - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q82 = - _theResult___fst_exp__h634665; + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q82 = + _theResult___fst_exp__h634662; 2'b01, 2'b10, 2'b11: - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q82 = - _theResult___exp__h635181; + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q82 = + _theResult___exp__h635178; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q81 or - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q82 or + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q81 or + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q82 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9903 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9906 or - _theResult___fst_exp__h634665) + _theResult___fst_exp__h634662) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h635259 = - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q81; + _theResult___fst_exp__h635256 = + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q81; 3'd1: - _theResult___fst_exp__h635259 = - CASE_guard26566_0b0_theResult___fst_exp34665_0_ETC__q82; + _theResult___fst_exp__h635256 = + CASE_guard26563_0b0_theResult___fst_exp34662_0_ETC__q82; 3'd2: - _theResult___fst_exp__h635259 = + _theResult___fst_exp__h635256 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9903; 3'd3: - _theResult___fst_exp__h635259 = + _theResult___fst_exp__h635256 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9906; - 3'd4: _theResult___fst_exp__h635259 = _theResult___fst_exp__h634665; - default: _theResult___fst_exp__h635259 = 8'd0; + 3'd4: _theResult___fst_exp__h635256 = _theResult___fst_exp__h634662; + default: _theResult___fst_exp__h635256 = 8'd0; endcase end - always@(guard__h644203 or - _theResult___fst_exp__h652431 or - out_exp__h652950 or _theResult___exp__h652947) + always@(guard__h644200 or + _theResult___fst_exp__h652428 or + out_exp__h652947 or _theResult___exp__h652944) begin - case (guard__h644203) + case (guard__h644200) 2'b0, 2'b01: - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q87 = - _theResult___fst_exp__h652431; + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q87 = + _theResult___fst_exp__h652428; 2'b10: - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q87 = - out_exp__h652950; + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q87 = + out_exp__h652947; 2'b11: - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q87 = - _theResult___exp__h652947; + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q87 = + _theResult___exp__h652944; endcase end - always@(guard__h644203 or - _theResult___fst_exp__h652431 or _theResult___exp__h652947) + always@(guard__h644200 or + _theResult___fst_exp__h652428 or _theResult___exp__h652944) begin - case (guard__h644203) + case (guard__h644200) 2'b0: - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q88 = - _theResult___fst_exp__h652431; + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q88 = + _theResult___fst_exp__h652428; 2'b01, 2'b10, 2'b11: - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q88 = - _theResult___exp__h652947; + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q88 = + _theResult___exp__h652944; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q87 or - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q88 or + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q87 or + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q88 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10450 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10452 or - _theResult___fst_exp__h652431) + _theResult___fst_exp__h652428) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h653025 = - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q87; + _theResult___fst_exp__h653022 = + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q87; 3'd1: - _theResult___fst_exp__h653025 = - CASE_guard44203_0b0_theResult___fst_exp52431_0_ETC__q88; + _theResult___fst_exp__h653022 = + CASE_guard44200_0b0_theResult___fst_exp52428_0_ETC__q88; 3'd2: - _theResult___fst_exp__h653025 = + _theResult___fst_exp__h653022 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10450; 3'd3: - _theResult___fst_exp__h653025 = + _theResult___fst_exp__h653022 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10452; - 3'd4: _theResult___fst_exp__h653025 = _theResult___fst_exp__h652431; - default: _theResult___fst_exp__h653025 = 8'd0; + 3'd4: _theResult___fst_exp__h653022 = _theResult___fst_exp__h652428; + default: _theResult___fst_exp__h653022 = 8'd0; endcase end - always@(guard__h653039 or - _theResult___fst_exp__h661116 or - out_exp__h661586 or _theResult___exp__h661583) + always@(guard__h653036 or + _theResult___fst_exp__h661113 or + out_exp__h661583 or _theResult___exp__h661580) begin - case (guard__h653039) + case (guard__h653036) 2'b0, 2'b01: - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q92 = - _theResult___fst_exp__h661116; + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q92 = + _theResult___fst_exp__h661113; 2'b10: - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q92 = - out_exp__h661586; + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q92 = + out_exp__h661583; 2'b11: - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q92 = - _theResult___exp__h661583; + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q92 = + _theResult___exp__h661580; endcase end - always@(guard__h653039 or - _theResult___fst_exp__h661116 or _theResult___exp__h661583) + always@(guard__h653036 or + _theResult___fst_exp__h661113 or _theResult___exp__h661580) begin - case (guard__h653039) + case (guard__h653036) 2'b0: - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q93 = - _theResult___fst_exp__h661116; + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q93 = + _theResult___fst_exp__h661113; 2'b01, 2'b10, 2'b11: - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q93 = - _theResult___exp__h661583; + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q93 = + _theResult___exp__h661580; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q92 or - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q93 or + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q92 or + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q93 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10519 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10521 or - _theResult___fst_exp__h661116) + _theResult___fst_exp__h661113) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h661661 = - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q92; + _theResult___fst_exp__h661658 = + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q92; 3'd1: - _theResult___fst_exp__h661661 = - CASE_guard53039_0b0_theResult___fst_exp61116_0_ETC__q93; + _theResult___fst_exp__h661658 = + CASE_guard53036_0b0_theResult___fst_exp61113_0_ETC__q93; 3'd2: - _theResult___fst_exp__h661661 = + _theResult___fst_exp__h661658 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10519; 3'd3: - _theResult___fst_exp__h661661 = + _theResult___fst_exp__h661658 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10521; - 3'd4: _theResult___fst_exp__h661661 = _theResult___fst_exp__h661116; - default: _theResult___fst_exp__h661661 = 8'd0; + 3'd4: _theResult___fst_exp__h661658 = _theResult___fst_exp__h661113; + default: _theResult___fst_exp__h661658 = 8'd0; endcase end - always@(guard__h635273 or - _theResult___snd__h643272 or - out_sfd__h643767 or _theResult___sfd__h643764) + always@(guard__h635270 or + _theResult___snd__h643269 or + out_sfd__h643764 or _theResult___sfd__h643761) begin - case (guard__h635273) + case (guard__h635270) 2'b0, 2'b01: - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q94 = - _theResult___snd__h643272[56:34]; + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q94 = + _theResult___snd__h643269[56:34]; 2'b10: - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q94 = - out_sfd__h643767; + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q94 = + out_sfd__h643764; 2'b11: - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q94 = - _theResult___sfd__h643764; + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q94 = + _theResult___sfd__h643761; endcase end - always@(guard__h635273 or - _theResult___snd__h643272 or _theResult___sfd__h643764) + always@(guard__h635270 or + _theResult___snd__h643269 or _theResult___sfd__h643761) begin - case (guard__h635273) + case (guard__h635270) 2'b0: - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q95 = - _theResult___snd__h643272[56:34]; + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q95 = + _theResult___snd__h643269[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q95 = - _theResult___sfd__h643764; + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q95 = + _theResult___sfd__h643761; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q94 or - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q95 or + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q94 or + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q95 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10569 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10571 or - _theResult___snd__h643272) + _theResult___snd__h643269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h643842 = - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q94; + _theResult___fst_sfd__h643839 = + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q94; 3'd1: - _theResult___fst_sfd__h643842 = - CASE_guard35273_0b0_theResult___snd43272_BITS__ETC__q95; + _theResult___fst_sfd__h643839 = + CASE_guard35270_0b0_theResult___snd43269_BITS__ETC__q95; 3'd2: - _theResult___fst_sfd__h643842 = + _theResult___fst_sfd__h643839 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10569; 3'd3: - _theResult___fst_sfd__h643842 = + _theResult___fst_sfd__h643839 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10571; - 3'd4: _theResult___fst_sfd__h643842 = _theResult___snd__h643272[56:34]; - default: _theResult___fst_sfd__h643842 = 23'd0; + 3'd4: _theResult___fst_sfd__h643839 = _theResult___snd__h643269[56:34]; + default: _theResult___fst_sfd__h643839 = 23'd0; endcase end - always@(guard__h626566 or - sfdin__h634659 or out_sfd__h635185 or _theResult___sfd__h635182) + always@(guard__h626563 or + sfdin__h634656 or out_sfd__h635182 or _theResult___sfd__h635179) begin - case (guard__h626566) + case (guard__h626563) 2'b0, 2'b01: - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q96 = - sfdin__h634659[56:34]; + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q96 = + sfdin__h634656[56:34]; 2'b10: - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q96 = - out_sfd__h635185; + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q96 = + out_sfd__h635182; 2'b11: - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q96 = - _theResult___sfd__h635182; + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q96 = + _theResult___sfd__h635179; endcase end - always@(guard__h626566 or sfdin__h634659 or _theResult___sfd__h635182) + always@(guard__h626563 or sfdin__h634656 or _theResult___sfd__h635179) begin - case (guard__h626566) + case (guard__h626563) 2'b0: - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q97 = - sfdin__h634659[56:34]; + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q97 = + sfdin__h634656[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q97 = - _theResult___sfd__h635182; + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q97 = + _theResult___sfd__h635179; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q96 or - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q97 or + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q96 or + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q97 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10550 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10552 or - sfdin__h634659) + sfdin__h634656) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h635260 = - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q96; + _theResult___fst_sfd__h635257 = + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q96; 3'd1: - _theResult___fst_sfd__h635260 = - CASE_guard26566_0b0_sfdin34659_BITS_56_TO_34_0_ETC__q97; + _theResult___fst_sfd__h635257 = + CASE_guard26563_0b0_sfdin34656_BITS_56_TO_34_0_ETC__q97; 3'd2: - _theResult___fst_sfd__h635260 = + _theResult___fst_sfd__h635257 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10550; 3'd3: - _theResult___fst_sfd__h635260 = + _theResult___fst_sfd__h635257 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10552; - 3'd4: _theResult___fst_sfd__h635260 = sfdin__h634659[56:34]; - default: _theResult___fst_sfd__h635260 = 23'd0; + 3'd4: _theResult___fst_sfd__h635257 = sfdin__h634656[56:34]; + default: _theResult___fst_sfd__h635257 = 23'd0; endcase end - always@(guard__h644203 or - sfdin__h652425 or out_sfd__h652951 or _theResult___sfd__h652948) + always@(guard__h644200 or + sfdin__h652422 or out_sfd__h652948 or _theResult___sfd__h652945) begin - case (guard__h644203) + case (guard__h644200) 2'b0, 2'b01: - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q98 = - sfdin__h652425[56:34]; + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q98 = + sfdin__h652422[56:34]; 2'b10: - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q98 = - out_sfd__h652951; + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q98 = + out_sfd__h652948; 2'b11: - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q98 = - _theResult___sfd__h652948; + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q98 = + _theResult___sfd__h652945; endcase end - always@(guard__h644203 or sfdin__h652425 or _theResult___sfd__h652948) + always@(guard__h644200 or sfdin__h652422 or _theResult___sfd__h652945) begin - case (guard__h644203) + case (guard__h644200) 2'b0: - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q99 = - sfdin__h652425[56:34]; + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q99 = + sfdin__h652422[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q99 = - _theResult___sfd__h652948; + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q99 = + _theResult___sfd__h652945; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q98 or - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q99 or + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q98 or + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q99 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10596 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10598 or - sfdin__h652425) + sfdin__h652422) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h653026 = - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q98; + _theResult___fst_sfd__h653023 = + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q98; 3'd1: - _theResult___fst_sfd__h653026 = - CASE_guard44203_0b0_sfdin52425_BITS_56_TO_34_0_ETC__q99; + _theResult___fst_sfd__h653023 = + CASE_guard44200_0b0_sfdin52422_BITS_56_TO_34_0_ETC__q99; 3'd2: - _theResult___fst_sfd__h653026 = + _theResult___fst_sfd__h653023 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10596; 3'd3: - _theResult___fst_sfd__h653026 = + _theResult___fst_sfd__h653023 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10598; - 3'd4: _theResult___fst_sfd__h653026 = sfdin__h652425[56:34]; - default: _theResult___fst_sfd__h653026 = 23'd0; + 3'd4: _theResult___fst_sfd__h653023 = sfdin__h652422[56:34]; + default: _theResult___fst_sfd__h653023 = 23'd0; endcase end - always@(guard__h653039 or - _theResult___snd__h661062 or - out_sfd__h661587 or _theResult___sfd__h661584) + always@(guard__h653036 or + _theResult___snd__h661059 or + out_sfd__h661584 or _theResult___sfd__h661581) begin - case (guard__h653039) + case (guard__h653036) 2'b0, 2'b01: - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q100 = - _theResult___snd__h661062[56:34]; + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q100 = + _theResult___snd__h661059[56:34]; 2'b10: - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q100 = - out_sfd__h661587; + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q100 = + out_sfd__h661584; 2'b11: - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q100 = - _theResult___sfd__h661584; + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q100 = + _theResult___sfd__h661581; endcase end - always@(guard__h653039 or - _theResult___snd__h661062 or _theResult___sfd__h661584) + always@(guard__h653036 or + _theResult___snd__h661059 or _theResult___sfd__h661581) begin - case (guard__h653039) + case (guard__h653036) 2'b0: - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q101 = - _theResult___snd__h661062[56:34]; + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q101 = + _theResult___snd__h661059[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q101 = - _theResult___sfd__h661584; + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q101 = + _theResult___sfd__h661581; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q100 or - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q101 or + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q100 or + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q101 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10615 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10617 or - _theResult___snd__h661062) + _theResult___snd__h661059) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h661662 = - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q100; + _theResult___fst_sfd__h661659 = + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q100; 3'd1: - _theResult___fst_sfd__h661662 = - CASE_guard53039_0b0_theResult___snd61062_BITS__ETC__q101; + _theResult___fst_sfd__h661659 = + CASE_guard53036_0b0_theResult___snd61059_BITS__ETC__q101; 3'd2: - _theResult___fst_sfd__h661662 = + _theResult___fst_sfd__h661659 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10615; 3'd3: - _theResult___fst_sfd__h661662 = + _theResult___fst_sfd__h661659 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10617; - 3'd4: _theResult___fst_sfd__h661662 = _theResult___snd__h661062[56:34]; - default: _theResult___fst_sfd__h661662 = 23'd0; + 3'd4: _theResult___fst_sfd__h661659 = _theResult___snd__h661059[56:34]; + default: _theResult___fst_sfd__h661659 = 23'd0; endcase end - always@(guard__h626566 or + always@(guard__h626563 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h626566) + case (guard__h626563) 2'b0, 2'b01, 2'b10: - CASE_guard26566_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = + CASE_guard26563_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard26566_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = - guard__h626566 == 2'b11 && + CASE_guard26563_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = + guard__h626563 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard26566_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 or - guard__h626566) + CASE_guard26563_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 or + guard__h626563) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10703 = - CASE_guard26566_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102; + CASE_guard26563_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10703 = - (guard__h626566 == 2'b0) ? + (guard__h626563 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h626566 == 2'b01 || guard__h626566 == 2'b10 || - guard__h626566 == 2'b11) && + (guard__h626563 == 2'b01 || guard__h626563 == 2'b10 || + guard__h626563 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10703 = @@ -40568,34 +40568,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h626566 or + always@(guard__h626563 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h626566) + case (guard__h626563) 2'b0, 2'b01, 2'b10: - CASE_guard26566_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = + CASE_guard26563_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard26566_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = - guard__h626566 != 2'b11 || + CASE_guard26563_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = + guard__h626563 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard26566_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 or - guard__h626566) + CASE_guard26563_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 or + guard__h626563) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = - CASE_guard26566_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103; + CASE_guard26563_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = - (guard__h626566 == 2'b0) ? + (guard__h626563 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h626566 != 2'b01 && guard__h626566 != 2'b10 && - guard__h626566 != 2'b11 || + guard__h626563 != 2'b01 && guard__h626563 != 2'b10 && + guard__h626563 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = @@ -40606,34 +40606,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h635273 or + always@(guard__h635270 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h635273) + case (guard__h635270) 2'b0, 2'b01, 2'b10: - CASE_guard35273_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = + CASE_guard35270_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard35273_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = - guard__h635273 == 2'b11 && + CASE_guard35270_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = + guard__h635270 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard35273_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 or - guard__h635273) + CASE_guard35270_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 or + guard__h635270) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10710 = - CASE_guard35273_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104; + CASE_guard35270_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10710 = - (guard__h635273 == 2'b0) ? + (guard__h635270 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h635273 == 2'b01 || guard__h635273 == 2'b10 || - guard__h635273 == 2'b11) && + (guard__h635270 == 2'b01 || guard__h635270 == 2'b10 || + guard__h635270 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10710 = @@ -40644,34 +40644,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h635273 or + always@(guard__h635270 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h635273) + case (guard__h635270) 2'b0, 2'b01, 2'b10: - CASE_guard35273_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = + CASE_guard35270_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard35273_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = - guard__h635273 != 2'b11 || + CASE_guard35270_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = + guard__h635270 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard35273_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 or - guard__h635273) + CASE_guard35270_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 or + guard__h635270) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10660 = - CASE_guard35273_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105; + CASE_guard35270_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10660 = - (guard__h635273 == 2'b0) ? + (guard__h635270 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h635273 != 2'b01 && guard__h635273 != 2'b10 && - guard__h635273 != 2'b11 || + guard__h635270 != 2'b01 && guard__h635270 != 2'b10 && + guard__h635270 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10660 = @@ -40682,34 +40682,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h644203 or + always@(guard__h644200 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h644203) + case (guard__h644200) 2'b0, 2'b01, 2'b10: - CASE_guard44203_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = + CASE_guard44200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard44203_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = - guard__h644203 == 2'b11 && + CASE_guard44200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = + guard__h644200 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard44203_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 or - guard__h644203) + CASE_guard44200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 or + guard__h644200) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10720 = - CASE_guard44203_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106; + CASE_guard44200_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10720 = - (guard__h644203 == 2'b0) ? + (guard__h644200 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h644203 == 2'b01 || guard__h644203 == 2'b10 || - guard__h644203 == 2'b11) && + (guard__h644200 == 2'b01 || guard__h644200 == 2'b10 || + guard__h644200 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10720 = @@ -40720,34 +40720,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h644203 or + always@(guard__h644200 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h644203) + case (guard__h644200) 2'b0, 2'b01, 2'b10: - CASE_guard44203_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = + CASE_guard44200_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard44203_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = - guard__h644203 != 2'b11 || + CASE_guard44200_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = + guard__h644200 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard44203_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 or - guard__h644203) + CASE_guard44200_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 or + guard__h644200) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10677 = - CASE_guard44203_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107; + CASE_guard44200_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10677 = - (guard__h644203 == 2'b0) ? + (guard__h644200 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h644203 != 2'b01 && guard__h644203 != 2'b10 && - guard__h644203 != 2'b11 || + guard__h644200 != 2'b01 && guard__h644200 != 2'b10 && + guard__h644200 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10677 = @@ -40758,34 +40758,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h653039 or + always@(guard__h653036 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h653039) + case (guard__h653036) 2'b0, 2'b01, 2'b10: - CASE_guard53039_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = + CASE_guard53036_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard53039_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = - guard__h653039 == 2'b11 && + CASE_guard53036_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = + guard__h653036 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard53039_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 or - guard__h653039) + CASE_guard53036_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 or + guard__h653036) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10727 = - CASE_guard53039_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108; + CASE_guard53036_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10727 = - (guard__h653039 == 2'b0) ? + (guard__h653036 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h653039 == 2'b01 || guard__h653039 == 2'b10 || - guard__h653039 == 2'b11) && + (guard__h653036 == 2'b01 || guard__h653036 == 2'b10 || + guard__h653036 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10727 = @@ -40796,34 +40796,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h653039 or + always@(guard__h653036 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h653039) + case (guard__h653036) 2'b0, 2'b01, 2'b10: - CASE_guard53039_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = + CASE_guard53036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard53039_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = - guard__h653039 != 2'b11 || + CASE_guard53036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = + guard__h653036 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard53039_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 or - guard__h653039) + CASE_guard53036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 or + guard__h653036) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10690 = - CASE_guard53039_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109; + CASE_guard53036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10690 = - (guard__h653039 == 2'b0) ? + (guard__h653036 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h653039 != 2'b01 && guard__h653039 != 2'b10 && - guard__h653039 != 2'b11 || + guard__h653036 != 2'b01 && guard__h653036 != 2'b10 && + guard__h653036 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10690 = @@ -40860,446 +40860,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h681020 or - _theResult___fst_exp__h689068 or - out_exp__h689513 or _theResult___exp__h689510) + always@(guard__h681017 or + _theResult___fst_exp__h689065 or + out_exp__h689510 or _theResult___exp__h689507) begin - case (guard__h681020) + case (guard__h681017) 2'b0, 2'b01: - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q114 = - _theResult___fst_exp__h689068; + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q114 = + _theResult___fst_exp__h689065; 2'b10: - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q114 = - out_exp__h689513; + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q114 = + out_exp__h689510; 2'b11: - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q114 = - _theResult___exp__h689510; + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q114 = + _theResult___exp__h689507; endcase end - always@(guard__h681020 or - _theResult___fst_exp__h689068 or _theResult___exp__h689510) + always@(guard__h681017 or + _theResult___fst_exp__h689065 or _theResult___exp__h689507) begin - case (guard__h681020) + case (guard__h681017) 2'b0: - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q115 = - _theResult___fst_exp__h689068; + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q115 = + _theResult___fst_exp__h689065; 2'b01, 2'b10, 2'b11: - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q115 = - _theResult___exp__h689510; + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q115 = + _theResult___exp__h689507; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q114 or - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q115 or + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q114 or + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q115 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11522 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11524 or - _theResult___fst_exp__h689068) + _theResult___fst_exp__h689065) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h689588 = - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q114; + _theResult___fst_exp__h689585 = + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q114; 3'd1: - _theResult___fst_exp__h689588 = - CASE_guard81020_0b0_theResult___fst_exp89068_0_ETC__q115; + _theResult___fst_exp__h689585 = + CASE_guard81017_0b0_theResult___fst_exp89065_0_ETC__q115; 3'd2: - _theResult___fst_exp__h689588 = + _theResult___fst_exp__h689585 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11522; 3'd3: - _theResult___fst_exp__h689588 = + _theResult___fst_exp__h689585 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11524; - 3'd4: _theResult___fst_exp__h689588 = _theResult___fst_exp__h689068; - default: _theResult___fst_exp__h689588 = 8'd0; + 3'd4: _theResult___fst_exp__h689585 = _theResult___fst_exp__h689065; + default: _theResult___fst_exp__h689585 = 8'd0; endcase end - always@(guard__h672313 or - _theResult___fst_exp__h680412 or - out_exp__h680931 or _theResult___exp__h680928) + always@(guard__h672310 or + _theResult___fst_exp__h680409 or + out_exp__h680928 or _theResult___exp__h680925) begin - case (guard__h672313) + case (guard__h672310) 2'b0, 2'b01: - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q116 = - _theResult___fst_exp__h680412; + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q116 = + _theResult___fst_exp__h680409; 2'b10: - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q116 = - out_exp__h680931; + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q116 = + out_exp__h680928; 2'b11: - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q116 = - _theResult___exp__h680928; + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q116 = + _theResult___exp__h680925; endcase end - always@(guard__h672313 or - _theResult___fst_exp__h680412 or _theResult___exp__h680928) + always@(guard__h672310 or + _theResult___fst_exp__h680409 or _theResult___exp__h680925) begin - case (guard__h672313) + case (guard__h672310) 2'b0: - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q117 = - _theResult___fst_exp__h680412; + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q117 = + _theResult___fst_exp__h680409; 2'b01, 2'b10, 2'b11: - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q117 = - _theResult___exp__h680928; + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q117 = + _theResult___exp__h680925; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q116 or - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q117 or + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q116 or + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q117 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11300 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11303 or - _theResult___fst_exp__h680412) + _theResult___fst_exp__h680409) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h681006 = - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q116; + _theResult___fst_exp__h681003 = + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q116; 3'd1: - _theResult___fst_exp__h681006 = - CASE_guard72313_0b0_theResult___fst_exp80412_0_ETC__q117; + _theResult___fst_exp__h681003 = + CASE_guard72310_0b0_theResult___fst_exp80409_0_ETC__q117; 3'd2: - _theResult___fst_exp__h681006 = + _theResult___fst_exp__h681003 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11300; 3'd3: - _theResult___fst_exp__h681006 = + _theResult___fst_exp__h681003 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11303; - 3'd4: _theResult___fst_exp__h681006 = _theResult___fst_exp__h680412; - default: _theResult___fst_exp__h681006 = 8'd0; + 3'd4: _theResult___fst_exp__h681003 = _theResult___fst_exp__h680409; + default: _theResult___fst_exp__h681003 = 8'd0; endcase end - always@(guard__h689950 or - _theResult___fst_exp__h698178 or - out_exp__h698697 or _theResult___exp__h698694) + always@(guard__h689947 or + _theResult___fst_exp__h698175 or + out_exp__h698694 or _theResult___exp__h698691) begin - case (guard__h689950) + case (guard__h689947) 2'b0, 2'b01: - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q122 = - _theResult___fst_exp__h698178; + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q122 = + _theResult___fst_exp__h698175; 2'b10: - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q122 = - out_exp__h698697; + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q122 = + out_exp__h698694; 2'b11: - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q122 = - _theResult___exp__h698694; + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q122 = + _theResult___exp__h698691; endcase end - always@(guard__h689950 or - _theResult___fst_exp__h698178 or _theResult___exp__h698694) + always@(guard__h689947 or + _theResult___fst_exp__h698175 or _theResult___exp__h698691) begin - case (guard__h689950) + case (guard__h689947) 2'b0: - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q123 = - _theResult___fst_exp__h698178; + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q123 = + _theResult___fst_exp__h698175; 2'b01, 2'b10, 2'b11: - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q123 = - _theResult___exp__h698694; + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q123 = + _theResult___exp__h698691; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q122 or - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q123 or + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q122 or + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q123 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11847 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11849 or - _theResult___fst_exp__h698178) + _theResult___fst_exp__h698175) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h698772 = - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q122; + _theResult___fst_exp__h698769 = + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q122; 3'd1: - _theResult___fst_exp__h698772 = - CASE_guard89950_0b0_theResult___fst_exp98178_0_ETC__q123; + _theResult___fst_exp__h698769 = + CASE_guard89947_0b0_theResult___fst_exp98175_0_ETC__q123; 3'd2: - _theResult___fst_exp__h698772 = + _theResult___fst_exp__h698769 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11847; 3'd3: - _theResult___fst_exp__h698772 = + _theResult___fst_exp__h698769 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11849; - 3'd4: _theResult___fst_exp__h698772 = _theResult___fst_exp__h698178; - default: _theResult___fst_exp__h698772 = 8'd0; + 3'd4: _theResult___fst_exp__h698769 = _theResult___fst_exp__h698175; + default: _theResult___fst_exp__h698769 = 8'd0; endcase end - always@(guard__h698786 or - _theResult___fst_exp__h706863 or - out_exp__h707333 or _theResult___exp__h707330) + always@(guard__h698783 or + _theResult___fst_exp__h706860 or + out_exp__h707330 or _theResult___exp__h707327) begin - case (guard__h698786) + case (guard__h698783) 2'b0, 2'b01: - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q127 = - _theResult___fst_exp__h706863; + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q127 = + _theResult___fst_exp__h706860; 2'b10: - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q127 = - out_exp__h707333; + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q127 = + out_exp__h707330; 2'b11: - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q127 = - _theResult___exp__h707330; + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q127 = + _theResult___exp__h707327; endcase end - always@(guard__h698786 or - _theResult___fst_exp__h706863 or _theResult___exp__h707330) + always@(guard__h698783 or + _theResult___fst_exp__h706860 or _theResult___exp__h707327) begin - case (guard__h698786) + case (guard__h698783) 2'b0: - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q128 = - _theResult___fst_exp__h706863; + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q128 = + _theResult___fst_exp__h706860; 2'b01, 2'b10, 2'b11: - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q128 = - _theResult___exp__h707330; + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q128 = + _theResult___exp__h707327; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q127 or - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q128 or + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q127 or + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q128 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11916 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11918 or - _theResult___fst_exp__h706863) + _theResult___fst_exp__h706860) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h707408 = - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q127; + _theResult___fst_exp__h707405 = + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q127; 3'd1: - _theResult___fst_exp__h707408 = - CASE_guard98786_0b0_theResult___fst_exp06863_0_ETC__q128; + _theResult___fst_exp__h707405 = + CASE_guard98783_0b0_theResult___fst_exp06860_0_ETC__q128; 3'd2: - _theResult___fst_exp__h707408 = + _theResult___fst_exp__h707405 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11916; 3'd3: - _theResult___fst_exp__h707408 = + _theResult___fst_exp__h707405 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11918; - 3'd4: _theResult___fst_exp__h707408 = _theResult___fst_exp__h706863; - default: _theResult___fst_exp__h707408 = 8'd0; + 3'd4: _theResult___fst_exp__h707405 = _theResult___fst_exp__h706860; + default: _theResult___fst_exp__h707405 = 8'd0; endcase end - always@(guard__h681020 or - _theResult___snd__h689019 or - out_sfd__h689514 or _theResult___sfd__h689511) + always@(guard__h681017 or + _theResult___snd__h689016 or + out_sfd__h689511 or _theResult___sfd__h689508) begin - case (guard__h681020) + case (guard__h681017) 2'b0, 2'b01: - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q129 = - _theResult___snd__h689019[56:34]; + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q129 = + _theResult___snd__h689016[56:34]; 2'b10: - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q129 = - out_sfd__h689514; + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q129 = + out_sfd__h689511; 2'b11: - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q129 = - _theResult___sfd__h689511; + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q129 = + _theResult___sfd__h689508; endcase end - always@(guard__h681020 or - _theResult___snd__h689019 or _theResult___sfd__h689511) + always@(guard__h681017 or + _theResult___snd__h689016 or _theResult___sfd__h689508) begin - case (guard__h681020) + case (guard__h681017) 2'b0: - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q130 = - _theResult___snd__h689019[56:34]; + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q130 = + _theResult___snd__h689016[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q130 = - _theResult___sfd__h689511; + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q130 = + _theResult___sfd__h689508; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q129 or - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q130 or + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q129 or + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q130 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11966 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11968 or - _theResult___snd__h689019) + _theResult___snd__h689016) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h689589 = - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q129; + _theResult___fst_sfd__h689586 = + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q129; 3'd1: - _theResult___fst_sfd__h689589 = - CASE_guard81020_0b0_theResult___snd89019_BITS__ETC__q130; + _theResult___fst_sfd__h689586 = + CASE_guard81017_0b0_theResult___snd89016_BITS__ETC__q130; 3'd2: - _theResult___fst_sfd__h689589 = + _theResult___fst_sfd__h689586 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11966; 3'd3: - _theResult___fst_sfd__h689589 = + _theResult___fst_sfd__h689586 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11968; - 3'd4: _theResult___fst_sfd__h689589 = _theResult___snd__h689019[56:34]; - default: _theResult___fst_sfd__h689589 = 23'd0; + 3'd4: _theResult___fst_sfd__h689586 = _theResult___snd__h689016[56:34]; + default: _theResult___fst_sfd__h689586 = 23'd0; endcase end - always@(guard__h672313 or - sfdin__h680406 or out_sfd__h680932 or _theResult___sfd__h680929) + always@(guard__h672310 or + sfdin__h680403 or out_sfd__h680929 or _theResult___sfd__h680926) begin - case (guard__h672313) + case (guard__h672310) 2'b0, 2'b01: - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q131 = - sfdin__h680406[56:34]; + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q131 = + sfdin__h680403[56:34]; 2'b10: - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q131 = - out_sfd__h680932; + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q131 = + out_sfd__h680929; 2'b11: - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q131 = - _theResult___sfd__h680929; + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q131 = + _theResult___sfd__h680926; endcase end - always@(guard__h672313 or sfdin__h680406 or _theResult___sfd__h680929) + always@(guard__h672310 or sfdin__h680403 or _theResult___sfd__h680926) begin - case (guard__h672313) + case (guard__h672310) 2'b0: - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q132 = - sfdin__h680406[56:34]; + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q132 = + sfdin__h680403[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q132 = - _theResult___sfd__h680929; + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q132 = + _theResult___sfd__h680926; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q131 or - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q132 or + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q131 or + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q132 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11947 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11949 or - sfdin__h680406) + sfdin__h680403) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h681007 = - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q131; + _theResult___fst_sfd__h681004 = + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q131; 3'd1: - _theResult___fst_sfd__h681007 = - CASE_guard72313_0b0_sfdin80406_BITS_56_TO_34_0_ETC__q132; + _theResult___fst_sfd__h681004 = + CASE_guard72310_0b0_sfdin80403_BITS_56_TO_34_0_ETC__q132; 3'd2: - _theResult___fst_sfd__h681007 = + _theResult___fst_sfd__h681004 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11947; 3'd3: - _theResult___fst_sfd__h681007 = + _theResult___fst_sfd__h681004 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11949; - 3'd4: _theResult___fst_sfd__h681007 = sfdin__h680406[56:34]; - default: _theResult___fst_sfd__h681007 = 23'd0; + 3'd4: _theResult___fst_sfd__h681004 = sfdin__h680403[56:34]; + default: _theResult___fst_sfd__h681004 = 23'd0; endcase end - always@(guard__h689950 or - sfdin__h698172 or out_sfd__h698698 or _theResult___sfd__h698695) + always@(guard__h689947 or + sfdin__h698169 or out_sfd__h698695 or _theResult___sfd__h698692) begin - case (guard__h689950) + case (guard__h689947) 2'b0, 2'b01: - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q133 = - sfdin__h698172[56:34]; + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q133 = + sfdin__h698169[56:34]; 2'b10: - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q133 = - out_sfd__h698698; + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q133 = + out_sfd__h698695; 2'b11: - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h698695; + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q133 = + _theResult___sfd__h698692; endcase end - always@(guard__h689950 or sfdin__h698172 or _theResult___sfd__h698695) + always@(guard__h689947 or sfdin__h698169 or _theResult___sfd__h698692) begin - case (guard__h689950) + case (guard__h689947) 2'b0: - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q134 = - sfdin__h698172[56:34]; + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q134 = + sfdin__h698169[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q134 = - _theResult___sfd__h698695; + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q134 = + _theResult___sfd__h698692; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q133 or - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q134 or + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q133 or + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q134 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11993 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11995 or - sfdin__h698172) + sfdin__h698169) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h698773 = - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q133; + _theResult___fst_sfd__h698770 = + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q133; 3'd1: - _theResult___fst_sfd__h698773 = - CASE_guard89950_0b0_sfdin98172_BITS_56_TO_34_0_ETC__q134; + _theResult___fst_sfd__h698770 = + CASE_guard89947_0b0_sfdin98169_BITS_56_TO_34_0_ETC__q134; 3'd2: - _theResult___fst_sfd__h698773 = + _theResult___fst_sfd__h698770 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11993; 3'd3: - _theResult___fst_sfd__h698773 = + _theResult___fst_sfd__h698770 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11995; - 3'd4: _theResult___fst_sfd__h698773 = sfdin__h698172[56:34]; - default: _theResult___fst_sfd__h698773 = 23'd0; + 3'd4: _theResult___fst_sfd__h698770 = sfdin__h698169[56:34]; + default: _theResult___fst_sfd__h698770 = 23'd0; endcase end - always@(guard__h698786 or - _theResult___snd__h706809 or - out_sfd__h707334 or _theResult___sfd__h707331) + always@(guard__h698783 or + _theResult___snd__h706806 or + out_sfd__h707331 or _theResult___sfd__h707328) begin - case (guard__h698786) + case (guard__h698783) 2'b0, 2'b01: - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q135 = - _theResult___snd__h706809[56:34]; + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q135 = + _theResult___snd__h706806[56:34]; 2'b10: - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q135 = - out_sfd__h707334; + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q135 = + out_sfd__h707331; 2'b11: - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q135 = - _theResult___sfd__h707331; + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q135 = + _theResult___sfd__h707328; endcase end - always@(guard__h698786 or - _theResult___snd__h706809 or _theResult___sfd__h707331) + always@(guard__h698783 or + _theResult___snd__h706806 or _theResult___sfd__h707328) begin - case (guard__h698786) + case (guard__h698783) 2'b0: - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q136 = - _theResult___snd__h706809[56:34]; + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q136 = + _theResult___snd__h706806[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q136 = - _theResult___sfd__h707331; + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q136 = + _theResult___sfd__h707328; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q135 or - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q136 or + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q135 or + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q136 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12012 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12014 or - _theResult___snd__h706809) + _theResult___snd__h706806) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h707409 = - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q135; + _theResult___fst_sfd__h707406 = + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q135; 3'd1: - _theResult___fst_sfd__h707409 = - CASE_guard98786_0b0_theResult___snd06809_BITS__ETC__q136; + _theResult___fst_sfd__h707406 = + CASE_guard98783_0b0_theResult___snd06806_BITS__ETC__q136; 3'd2: - _theResult___fst_sfd__h707409 = + _theResult___fst_sfd__h707406 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12012; 3'd3: - _theResult___fst_sfd__h707409 = + _theResult___fst_sfd__h707406 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12014; - 3'd4: _theResult___fst_sfd__h707409 = _theResult___snd__h706809[56:34]; - default: _theResult___fst_sfd__h707409 = 23'd0; + 3'd4: _theResult___fst_sfd__h707406 = _theResult___snd__h706806[56:34]; + default: _theResult___fst_sfd__h707406 = 23'd0; endcase end - always@(guard__h672313 or + always@(guard__h672310 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h672313) + case (guard__h672310) 2'b0, 2'b01, 2'b10: - CASE_guard72313_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + CASE_guard72310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard72313_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = - guard__h672313 == 2'b11 && + CASE_guard72310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + guard__h672310 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard72313_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or - guard__h672313) + CASE_guard72310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or + guard__h672310) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12100 = - CASE_guard72313_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; + CASE_guard72310_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12100 = - (guard__h672313 == 2'b0) ? + (guard__h672310 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h672313 == 2'b01 || guard__h672313 == 2'b10 || - guard__h672313 == 2'b11) && + (guard__h672310 == 2'b01 || guard__h672310 == 2'b10 || + guard__h672310 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12100 = @@ -41310,34 +41310,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h672313 or + always@(guard__h672310 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h672313) + case (guard__h672310) 2'b0, 2'b01, 2'b10: - CASE_guard72313_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = + CASE_guard72310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard72313_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = - guard__h672313 != 2'b11 || + CASE_guard72310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = + guard__h672310 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard72313_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 or - guard__h672313) + CASE_guard72310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 or + guard__h672310) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = - CASE_guard72313_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138; + CASE_guard72310_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = - (guard__h672313 == 2'b0) ? + (guard__h672310 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h672313 != 2'b01 && guard__h672313 != 2'b10 && - guard__h672313 != 2'b11 || + guard__h672310 != 2'b01 && guard__h672310 != 2'b10 && + guard__h672310 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = @@ -41348,34 +41348,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h681020 or + always@(guard__h681017 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h681020) + case (guard__h681017) 2'b0, 2'b01, 2'b10: - CASE_guard81020_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = + CASE_guard81017_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard81020_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = - guard__h681020 == 2'b11 && + CASE_guard81017_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = + guard__h681017 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard81020_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 or - guard__h681020) + CASE_guard81017_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 or + guard__h681017) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12107 = - CASE_guard81020_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139; + CASE_guard81017_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12107 = - (guard__h681020 == 2'b0) ? + (guard__h681017 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h681020 == 2'b01 || guard__h681020 == 2'b10 || - guard__h681020 == 2'b11) && + (guard__h681017 == 2'b01 || guard__h681017 == 2'b10 || + guard__h681017 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12107 = @@ -41386,34 +41386,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h681020 or + always@(guard__h681017 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h681020) + case (guard__h681017) 2'b0, 2'b01, 2'b10: - CASE_guard81020_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = + CASE_guard81017_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard81020_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = - guard__h681020 != 2'b11 || + CASE_guard81017_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = + guard__h681017 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard81020_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 or - guard__h681020) + CASE_guard81017_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 or + guard__h681017) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12057 = - CASE_guard81020_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140; + CASE_guard81017_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12057 = - (guard__h681020 == 2'b0) ? + (guard__h681017 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h681020 != 2'b01 && guard__h681020 != 2'b10 && - guard__h681020 != 2'b11 || + guard__h681017 != 2'b01 && guard__h681017 != 2'b10 && + guard__h681017 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12057 = @@ -41424,34 +41424,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h689950 or + always@(guard__h689947 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h689950) + case (guard__h689947) 2'b0, 2'b01, 2'b10: - CASE_guard89950_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + CASE_guard89947_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard89950_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = - guard__h689950 == 2'b11 && + CASE_guard89947_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + guard__h689947 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard89950_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or - guard__h689950) + CASE_guard89947_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or + guard__h689947) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12117 = - CASE_guard89950_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; + CASE_guard89947_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12117 = - (guard__h689950 == 2'b0) ? + (guard__h689947 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h689950 == 2'b01 || guard__h689950 == 2'b10 || - guard__h689950 == 2'b11) && + (guard__h689947 == 2'b01 || guard__h689947 == 2'b10 || + guard__h689947 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12117 = @@ -41462,34 +41462,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h689950 or + always@(guard__h689947 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h689950) + case (guard__h689947) 2'b0, 2'b01, 2'b10: - CASE_guard89950_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + CASE_guard89947_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard89950_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = - guard__h689950 != 2'b11 || + CASE_guard89947_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + guard__h689947 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard89950_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or - guard__h689950) + CASE_guard89947_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or + guard__h689947) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12074 = - CASE_guard89950_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; + CASE_guard89947_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12074 = - (guard__h689950 == 2'b0) ? + (guard__h689947 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h689950 != 2'b01 && guard__h689950 != 2'b10 && - guard__h689950 != 2'b11 || + guard__h689947 != 2'b01 && guard__h689947 != 2'b10 && + guard__h689947 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12074 = @@ -41500,34 +41500,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h698786 or + always@(guard__h698783 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h698786) + case (guard__h698783) 2'b0, 2'b01, 2'b10: - CASE_guard98786_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = + CASE_guard98783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard98786_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = - guard__h698786 == 2'b11 && + CASE_guard98783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = + guard__h698783 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard98786_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 or - guard__h698786) + CASE_guard98783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 or + guard__h698783) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12124 = - CASE_guard98786_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143; + CASE_guard98783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12124 = - (guard__h698786 == 2'b0) ? + (guard__h698783 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h698786 == 2'b01 || guard__h698786 == 2'b10 || - guard__h698786 == 2'b11) && + (guard__h698783 == 2'b01 || guard__h698783 == 2'b10 || + guard__h698783 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12124 = @@ -41538,34 +41538,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h698786 or + always@(guard__h698783 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h698786) + case (guard__h698783) 2'b0, 2'b01, 2'b10: - CASE_guard98786_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = + CASE_guard98783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard98786_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = - guard__h698786 != 2'b11 || + CASE_guard98783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = + guard__h698783 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard98786_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 or - guard__h698786) + CASE_guard98783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 or + guard__h698783) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12087 = - CASE_guard98786_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144; + CASE_guard98783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12087 = - (guard__h698786 == 2'b0) ? + (guard__h698783 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h698786 != 2'b01 && guard__h698786 != 2'b10 && - guard__h698786 != 2'b11 || + guard__h698783 != 2'b01 && guard__h698783 != 2'b10 && + guard__h698783 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12087 = @@ -41622,28 +41622,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h731184 or - _theResult___fst_exp__h739145 or _theResult___exp__h739800) + always@(guard__h731181 or + _theResult___fst_exp__h739142 or _theResult___exp__h739797) begin - case (guard__h731184) + case (guard__h731181) 2'b0: - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q154 = - _theResult___fst_exp__h739145; + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q154 = + _theResult___fst_exp__h739142; 2'b01, 2'b10, 2'b11: - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q154 = - _theResult___exp__h739800; + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q154 = + _theResult___exp__h739797; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h739145 or + _theResult___fst_exp__h739142 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13254 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13252 or - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q154) + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q154) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13258 = - _theResult___fst_exp__h739145; + _theResult___fst_exp__h739142; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13258 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13254; @@ -41652,44 +41652,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13252; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13258 = - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q154; + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q154; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13258 = 11'd0; endcase end - always@(guard__h731184 or - _theResult___fst_exp__h739145 or - out_exp__h739803 or _theResult___exp__h739800) + always@(guard__h731181 or + _theResult___fst_exp__h739142 or + out_exp__h739800 or _theResult___exp__h739797) begin - case (guard__h731184) + case (guard__h731181) 2'b0, 2'b01: - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q155 = - _theResult___fst_exp__h739145; + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q155 = + _theResult___fst_exp__h739142; 2'b10: - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q155 = - out_exp__h739803; + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q155 = + out_exp__h739800; 2'b11: - CASE_guard31184_0b0_theResult___fst_exp39145_0_ETC__q155 = - _theResult___exp__h739800; + CASE_guard31181_0b0_theResult___fst_exp39142_0_ETC__q155 = + _theResult___exp__h739797; endcase end - always@(guard__h731184 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h731181 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h731184) + case (guard__h731181) 2'b0, 2'b01, 2'b10: - CASE_guard31184_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard31181_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard31184_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h731184 == 2'b11 && + CASE_guard31181_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h731181 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h731184) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h731181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41699,12 +41699,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h731184 == 2'b0) ? + (guard__h731181 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h731184 == 2'b01 || guard__h731184 == 2'b10 || - guard__h731184 == 2'b11) && + (guard__h731181 == 2'b01 || guard__h731181 == 2'b10 || + guard__h731181 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41715,23 +41715,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h740496 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h740493 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h740496) + case (guard__h740493) 2'b0, 2'b01, 2'b10: - CASE_guard40496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard40493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard40496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h740496 == 2'b11 && + CASE_guard40493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h740493 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h740496) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h740493) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41741,12 +41741,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h740496 == 2'b0) ? + (guard__h740493 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h740496 == 2'b01 || guard__h740496 == 2'b10 || - guard__h740496 == 2'b11) && + (guard__h740493 == 2'b01 || guard__h740493 == 2'b10 || + guard__h740493 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41757,23 +41757,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h749565 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h749562 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h749565) + case (guard__h749562) 2'b0, 2'b01, 2'b10: - CASE_guard49565_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + CASE_guard49562_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard49565_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = - guard__h749565 == 2'b11 && + CASE_guard49562_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + guard__h749562 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h749565) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h749562) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41783,12 +41783,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h749565 == 2'b0) ? + (guard__h749562 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h749565 == 2'b01 || guard__h749565 == 2'b10 || - guard__h749565 == 2'b11) && + (guard__h749562 == 2'b01 || guard__h749562 == 2'b10 || + guard__h749562 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41799,28 +41799,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h809341 or - _theResult___fst_exp__h817302 or _theResult___exp__h817957) + always@(guard__h809338 or + _theResult___fst_exp__h817299 or _theResult___exp__h817954) begin - case (guard__h809341) + case (guard__h809338) 2'b0: - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q171 = - _theResult___fst_exp__h817302; + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q171 = + _theResult___fst_exp__h817299; 2'b01, 2'b10, 2'b11: - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q171 = - _theResult___exp__h817957; + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q171 = + _theResult___exp__h817954; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h817302 or + _theResult___fst_exp__h817299 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13969 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13967 or - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q171) + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q171) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13973 = - _theResult___fst_exp__h817302; + _theResult___fst_exp__h817299; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13973 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13969; @@ -41829,42 +41829,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13967; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13973 = - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q171; + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q171; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13973 = 11'd0; endcase end - always@(guard__h809341 or - _theResult___fst_exp__h817302 or - out_exp__h817960 or _theResult___exp__h817957) + always@(guard__h809338 or + _theResult___fst_exp__h817299 or + out_exp__h817957 or _theResult___exp__h817954) begin - case (guard__h809341) + case (guard__h809338) 2'b0, 2'b01: - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q172 = - _theResult___fst_exp__h817302; + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q172 = + _theResult___fst_exp__h817299; 2'b10: - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q172 = - out_exp__h817960; + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q172 = + out_exp__h817957; 2'b11: - CASE_guard09341_0b0_theResult___fst_exp17302_0_ETC__q172 = - _theResult___exp__h817957; + CASE_guard09338_0b0_theResult___fst_exp17299_0_ETC__q172 = + _theResult___exp__h817954; endcase end - always@(guard__h809341 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h809338 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h809341) + case (guard__h809338) 2'b0, 2'b01, 2'b10: - CASE_guard09341_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + CASE_guard09338_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard09341_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = - guard__h809341 == 2'b11 && + CASE_guard09338_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + guard__h809338 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809341) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809338) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41873,12 +41873,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174 = - (guard__h809341 == 2'b0) ? + (guard__h809338 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h809341 == 2'b01 || guard__h809341 == 2'b10 || - guard__h809341 == 2'b11) && + (guard__h809338 == 2'b01 || guard__h809338 == 2'b10 || + guard__h809338 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41889,21 +41889,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h818653 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h818650 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h818653) + case (guard__h818650) 2'b0, 2'b01, 2'b10: - CASE_guard18653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + CASE_guard18650_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard18653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = - guard__h818653 == 2'b11 && + CASE_guard18650_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + guard__h818650 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818653) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818650) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41912,12 +41912,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176 = - (guard__h818653 == 2'b0) ? + (guard__h818650 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h818653 == 2'b01 || guard__h818653 == 2'b10 || - guard__h818653 == 2'b11) && + (guard__h818650 == 2'b01 || guard__h818650 == 2'b10 || + guard__h818650 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41928,21 +41928,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h827722 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h827719 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h827722) + case (guard__h827719) 2'b0, 2'b01, 2'b10: - CASE_guard27722_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + CASE_guard27719_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard27722_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = - guard__h827722 == 2'b11 && + CASE_guard27719_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + guard__h827719 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827722) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827719) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41951,12 +41951,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178 = - (guard__h827722 == 2'b0) ? + (guard__h827719 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h827722 == 2'b01 || guard__h827722 == 2'b10 || - guard__h827722 == 2'b11) && + (guard__h827719 == 2'b01 || guard__h827719 == 2'b10 || + guard__h827719 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41967,21 +41967,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h818653 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h818650 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h818653) + case (guard__h818650) 2'b0, 2'b01, 2'b10: - CASE_guard18653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + CASE_guard18650_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard18653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = - guard__h818653 != 2'b11 || + CASE_guard18650_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + guard__h818650 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818653) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818650) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41990,12 +41990,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180 = - (guard__h818653 == 2'b0) ? + (guard__h818650 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h818653 != 2'b01 && guard__h818653 != 2'b10 && - guard__h818653 != 2'b11 || + guard__h818650 != 2'b01 && guard__h818650 != 2'b10 && + guard__h818650 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42006,21 +42006,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h827722 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h827719 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h827722) + case (guard__h827719) 2'b0, 2'b01, 2'b10: - CASE_guard27722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + CASE_guard27719_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard27722_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = - guard__h827722 != 2'b11 || + CASE_guard27719_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + guard__h827719 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827722) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827719) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42029,12 +42029,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182 = - (guard__h827722 == 2'b0) ? + (guard__h827719 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h827722 != 2'b01 && guard__h827722 != 2'b10 && - guard__h827722 != 2'b11 || + guard__h827719 != 2'b01 && guard__h827719 != 2'b10 && + guard__h827719 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42045,21 +42045,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h809341 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h809338 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h809341) + case (guard__h809338) 2'b0, 2'b01, 2'b10: - CASE_guard09341_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + CASE_guard09338_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard09341_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = - guard__h809341 != 2'b11 || + CASE_guard09338_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + guard__h809338 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809341) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809338) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42068,12 +42068,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184 = - (guard__h809341 == 2'b0) ? + (guard__h809338 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h809341 != 2'b01 && guard__h809341 != 2'b10 && - guard__h809341 != 2'b11 || + guard__h809338 != 2'b01 && guard__h809338 != 2'b10 && + guard__h809338 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42084,28 +42084,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h770037 or - _theResult___fst_exp__h777998 or _theResult___exp__h778653) + always@(guard__h770034 or + _theResult___fst_exp__h777995 or _theResult___exp__h778650) begin - case (guard__h770037) + case (guard__h770034) 2'b0: - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q194 = - _theResult___fst_exp__h777998; + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q194 = + _theResult___fst_exp__h777995; 2'b01, 2'b10, 2'b11: - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q194 = - _theResult___exp__h778653; + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q194 = + _theResult___exp__h778650; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h777998 or + _theResult___fst_exp__h777995 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14739 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14737 or - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q194) + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q194) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14743 = - _theResult___fst_exp__h777998; + _theResult___fst_exp__h777995; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14743 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14739; @@ -42114,49 +42114,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14737; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14743 = - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q194; + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q194; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14743 = 11'd0; endcase end - always@(guard__h770037 or - _theResult___fst_exp__h777998 or - out_exp__h778656 or _theResult___exp__h778653) + always@(guard__h770034 or + _theResult___fst_exp__h777995 or + out_exp__h778653 or _theResult___exp__h778650) begin - case (guard__h770037) + case (guard__h770034) 2'b0, 2'b01: - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q195 = - _theResult___fst_exp__h777998; + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q195 = + _theResult___fst_exp__h777995; 2'b10: - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q195 = - out_exp__h778656; + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q195 = + out_exp__h778653; 2'b11: - CASE_guard70037_0b0_theResult___fst_exp77998_0_ETC__q195 = - _theResult___exp__h778653; + CASE_guard70034_0b0_theResult___fst_exp77995_0_ETC__q195 = + _theResult___exp__h778650; endcase end - always@(guard__h779349 or - _theResult___fst_exp__h787575 or _theResult___exp__h788304) + always@(guard__h779346 or + _theResult___fst_exp__h787572 or _theResult___exp__h788301) begin - case (guard__h779349) + case (guard__h779346) 2'b0: - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q196 = - _theResult___fst_exp__h787575; + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q196 = + _theResult___fst_exp__h787572; 2'b01, 2'b10, 2'b11: - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q196 = - _theResult___exp__h788304; + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q196 = + _theResult___exp__h788301; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h787575 or + _theResult___fst_exp__h787572 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14777 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14775 or - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q196) + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q196) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14781 = - _theResult___fst_exp__h787575; + _theResult___fst_exp__h787572; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14781 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14777; @@ -42165,49 +42165,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14775; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14781 = - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q196; + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q196; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14781 = 11'd0; endcase end - always@(guard__h779349 or - _theResult___fst_exp__h787575 or - out_exp__h788307 or _theResult___exp__h788304) + always@(guard__h779346 or + _theResult___fst_exp__h787572 or + out_exp__h788304 or _theResult___exp__h788301) begin - case (guard__h779349) + case (guard__h779346) 2'b0, 2'b01: - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q197 = - _theResult___fst_exp__h787575; + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q197 = + _theResult___fst_exp__h787572; 2'b10: - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q197 = - out_exp__h788307; + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q197 = + out_exp__h788304; 2'b11: - CASE_guard79349_0b0_theResult___fst_exp87575_0_ETC__q197 = - _theResult___exp__h788304; + CASE_guard79346_0b0_theResult___fst_exp87572_0_ETC__q197 = + _theResult___exp__h788301; endcase end - always@(guard__h788418 or - _theResult___fst_exp__h796408 or _theResult___exp__h797088) + always@(guard__h788415 or + _theResult___fst_exp__h796405 or _theResult___exp__h797085) begin - case (guard__h788418) + case (guard__h788415) 2'b0: - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q198 = - _theResult___fst_exp__h796408; + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q198 = + _theResult___fst_exp__h796405; 2'b01, 2'b10, 2'b11: - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q198 = - _theResult___exp__h797088; + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q198 = + _theResult___exp__h797085; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h796408 or + _theResult___fst_exp__h796405 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14808 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14806 or - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q198) + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q198) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14812 = - _theResult___fst_exp__h796408; + _theResult___fst_exp__h796405; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14812 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14808; @@ -42216,49 +42216,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14806; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14812 = - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q198; + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q198; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14812 = 11'd0; endcase end - always@(guard__h788418 or - _theResult___fst_exp__h796408 or - out_exp__h797091 or _theResult___exp__h797088) + always@(guard__h788415 or + _theResult___fst_exp__h796405 or + out_exp__h797088 or _theResult___exp__h797085) begin - case (guard__h788418) + case (guard__h788415) 2'b0, 2'b01: - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q199 = - _theResult___fst_exp__h796408; + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q199 = + _theResult___fst_exp__h796405; 2'b10: - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q199 = - out_exp__h797091; + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q199 = + out_exp__h797088; 2'b11: - CASE_guard88418_0b0_theResult___fst_exp96408_0_ETC__q199 = - _theResult___exp__h797088; + CASE_guard88415_0b0_theResult___fst_exp96405_0_ETC__q199 = + _theResult___exp__h797085; endcase end - always@(guard__h818653 or - _theResult___fst_exp__h826879 or _theResult___exp__h827608) + always@(guard__h818650 or + _theResult___fst_exp__h826876 or _theResult___exp__h827605) begin - case (guard__h818653) + case (guard__h818650) 2'b0: - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q200 = - _theResult___fst_exp__h826879; + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q200 = + _theResult___fst_exp__h826876; 2'b01, 2'b10, 2'b11: - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q200 = - _theResult___exp__h827608; + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q200 = + _theResult___exp__h827605; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h826879 or + _theResult___fst_exp__h826876 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14007 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14005 or - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q200) + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q200) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14011 = - _theResult___fst_exp__h826879; + _theResult___fst_exp__h826876; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14011 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14007; @@ -42267,49 +42267,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14005; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14011 = - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q200; + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q200; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14011 = 11'd0; endcase end - always@(guard__h818653 or - _theResult___fst_exp__h826879 or - out_exp__h827611 or _theResult___exp__h827608) + always@(guard__h818650 or + _theResult___fst_exp__h826876 or + out_exp__h827608 or _theResult___exp__h827605) begin - case (guard__h818653) + case (guard__h818650) 2'b0, 2'b01: - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q201 = - _theResult___fst_exp__h826879; + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q201 = + _theResult___fst_exp__h826876; 2'b10: - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q201 = - out_exp__h827611; + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q201 = + out_exp__h827608; 2'b11: - CASE_guard18653_0b0_theResult___fst_exp26879_0_ETC__q201 = - _theResult___exp__h827608; + CASE_guard18650_0b0_theResult___fst_exp26876_0_ETC__q201 = + _theResult___exp__h827605; endcase end - always@(guard__h827722 or - _theResult___fst_exp__h835712 or _theResult___exp__h836392) + always@(guard__h827719 or + _theResult___fst_exp__h835709 or _theResult___exp__h836389) begin - case (guard__h827722) + case (guard__h827719) 2'b0: - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q202 = - _theResult___fst_exp__h835712; + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q202 = + _theResult___fst_exp__h835709; 2'b01, 2'b10, 2'b11: - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q202 = - _theResult___exp__h836392; + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q202 = + _theResult___exp__h836389; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h835712 or + _theResult___fst_exp__h835709 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14038 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14036 or - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q202) + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q202) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14042 = - _theResult___fst_exp__h835712; + _theResult___fst_exp__h835709; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14042 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14038; @@ -42318,44 +42318,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14036; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14042 = - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q202; + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q202; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14042 = 11'd0; endcase end - always@(guard__h827722 or - _theResult___fst_exp__h835712 or - out_exp__h836395 or _theResult___exp__h836392) + always@(guard__h827719 or + _theResult___fst_exp__h835709 or + out_exp__h836392 or _theResult___exp__h836389) begin - case (guard__h827722) + case (guard__h827719) 2'b0, 2'b01: - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q203 = - _theResult___fst_exp__h835712; + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q203 = + _theResult___fst_exp__h835709; 2'b10: - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q203 = - out_exp__h836395; + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q203 = + out_exp__h836392; 2'b11: - CASE_guard27722_0b0_theResult___fst_exp35712_0_ETC__q203 = - _theResult___exp__h836392; + CASE_guard27719_0b0_theResult___fst_exp35709_0_ETC__q203 = + _theResult___exp__h836389; endcase end - always@(guard__h770037 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h770034 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h770037) + case (guard__h770034) 2'b0, 2'b01, 2'b10: - CASE_guard70037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + CASE_guard70034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard70037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = - guard__h770037 == 2'b11 && + CASE_guard70034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + guard__h770034 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770037) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770034) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42365,12 +42365,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205 = - (guard__h770037 == 2'b0) ? + (guard__h770034 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h770037 == 2'b01 || guard__h770037 == 2'b10 || - guard__h770037 == 2'b11) && + (guard__h770034 == 2'b01 || guard__h770034 == 2'b10 || + guard__h770034 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42381,23 +42381,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h788418 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h788415 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h788418) + case (guard__h788415) 2'b0, 2'b01, 2'b10: - CASE_guard88418_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + CASE_guard88415_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard88418_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = - guard__h788418 == 2'b11 && + CASE_guard88415_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + guard__h788415 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788418) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788415) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42407,12 +42407,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207 = - (guard__h788418 == 2'b0) ? + (guard__h788415 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h788418 == 2'b01 || guard__h788418 == 2'b10 || - guard__h788418 == 2'b11) && + (guard__h788415 == 2'b01 || guard__h788415 == 2'b10 || + guard__h788415 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42423,23 +42423,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h779349 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h779346 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h779349) + case (guard__h779346) 2'b0, 2'b01, 2'b10: - CASE_guard79349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + CASE_guard79346_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard79349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = - guard__h779349 == 2'b11 && + CASE_guard79346_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + guard__h779346 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779349) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779346) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42449,12 +42449,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209 = - (guard__h779349 == 2'b0) ? + (guard__h779346 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h779349 == 2'b01 || guard__h779349 == 2'b10 || - guard__h779349 == 2'b11) && + (guard__h779346 == 2'b01 || guard__h779346 == 2'b10 || + guard__h779346 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42465,23 +42465,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h779349 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h779346 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h779349) + case (guard__h779346) 2'b0, 2'b01, 2'b10: - CASE_guard79349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + CASE_guard79346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard79349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = - guard__h779349 != 2'b11 || + CASE_guard79346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + guard__h779346 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779349) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779346) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42491,12 +42491,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211 = - (guard__h779349 == 2'b0) ? + (guard__h779346 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h779349 != 2'b01 && guard__h779349 != 2'b10 && - guard__h779349 != 2'b11 || + guard__h779346 != 2'b01 && guard__h779346 != 2'b10 && + guard__h779346 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42507,23 +42507,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h788418 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h788415 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h788418) + case (guard__h788415) 2'b0, 2'b01, 2'b10: - CASE_guard88418_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + CASE_guard88415_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard88418_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = - guard__h788418 != 2'b11 || + CASE_guard88415_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + guard__h788415 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788418) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788415) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42533,12 +42533,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213 = - (guard__h788418 == 2'b0) ? + (guard__h788415 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h788418 != 2'b01 && guard__h788418 != 2'b10 && - guard__h788418 != 2'b11 || + guard__h788415 != 2'b01 && guard__h788415 != 2'b10 && + guard__h788415 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42549,23 +42549,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h770037 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h770034 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h770037) + case (guard__h770034) 2'b0, 2'b01, 2'b10: - CASE_guard70037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + CASE_guard70034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard70037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = - guard__h770037 != 2'b11 || + CASE_guard70034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + guard__h770034 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770037) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770034) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42575,12 +42575,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215 = - (guard__h770037 == 2'b0) ? + (guard__h770034 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h770037 != 2'b01 && guard__h770037 != 2'b10 && - guard__h770037 != 2'b11 || + guard__h770034 != 2'b01 && guard__h770034 != 2'b10 && + guard__h770034 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42591,28 +42591,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h770037 or - _theResult___snd__h777949 or _theResult___sfd__h778654) + always@(guard__h770034 or + _theResult___snd__h777946 or _theResult___sfd__h778651) begin - case (guard__h770037) + case (guard__h770034) 2'b0: - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q216 = - _theResult___snd__h777949[56:5]; + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q216 = + _theResult___snd__h777946[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q216 = - _theResult___sfd__h778654; + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q216 = + _theResult___sfd__h778651; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h777949 or + _theResult___snd__h777946 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14834 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14832 or - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q216) + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q216) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14838 = - _theResult___snd__h777949[56:5]; + _theResult___snd__h777946[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14838 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14834; @@ -42621,48 +42621,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14832; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14838 = - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q216; + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q216; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14838 = 52'd0; endcase end - always@(guard__h770037 or - _theResult___snd__h777949 or - out_sfd__h778657 or _theResult___sfd__h778654) + always@(guard__h770034 or + _theResult___snd__h777946 or + out_sfd__h778654 or _theResult___sfd__h778651) begin - case (guard__h770037) + case (guard__h770034) 2'b0, 2'b01: - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q217 = - _theResult___snd__h777949[56:5]; + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q217 = + _theResult___snd__h777946[56:5]; 2'b10: - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q217 = - out_sfd__h778657; + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q217 = + out_sfd__h778654; 2'b11: - CASE_guard70037_0b0_theResult___snd77949_BITS__ETC__q217 = - _theResult___sfd__h778654; + CASE_guard70034_0b0_theResult___snd77946_BITS__ETC__q217 = + _theResult___sfd__h778651; endcase end - always@(guard__h779349 or sfdin__h787569 or _theResult___sfd__h788305) + always@(guard__h779346 or sfdin__h787566 or _theResult___sfd__h788302) begin - case (guard__h779349) + case (guard__h779346) 2'b0: - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h787569[56:5]; + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h787566[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h788305; + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h788302; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h787569 or + sfdin__h787566 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14860 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14858 or - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q218) + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q218) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14864 = - sfdin__h787569[56:5]; + sfdin__h787566[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14864 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14860; @@ -42671,48 +42671,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14858; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14864 = - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q218; + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q218; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14864 = 52'd0; endcase end - always@(guard__h779349 or - sfdin__h787569 or out_sfd__h788308 or _theResult___sfd__h788305) + always@(guard__h779346 or + sfdin__h787566 or out_sfd__h788305 or _theResult___sfd__h788302) begin - case (guard__h779349) + case (guard__h779346) 2'b0, 2'b01: - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q219 = - sfdin__h787569[56:5]; + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h787566[56:5]; 2'b10: - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q219 = - out_sfd__h788308; + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q219 = + out_sfd__h788305; 2'b11: - CASE_guard79349_0b0_sfdin87569_BITS_56_TO_5_0b_ETC__q219 = - _theResult___sfd__h788305; + CASE_guard79346_0b0_sfdin87566_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h788302; endcase end - always@(guard__h788418 or - _theResult___snd__h796354 or _theResult___sfd__h797089) + always@(guard__h788415 or + _theResult___snd__h796351 or _theResult___sfd__h797086) begin - case (guard__h788418) + case (guard__h788415) 2'b0: - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q220 = - _theResult___snd__h796354[56:5]; + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q220 = + _theResult___snd__h796351[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q220 = - _theResult___sfd__h797089; + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q220 = + _theResult___sfd__h797086; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h796354 or + _theResult___snd__h796351 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14879 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14877 or - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q220) + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q220) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14883 = - _theResult___snd__h796354[56:5]; + _theResult___snd__h796351[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14883 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14879; @@ -42721,49 +42721,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14877; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14883 = - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q220; + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q220; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14883 = 52'd0; endcase end - always@(guard__h788418 or - _theResult___snd__h796354 or - out_sfd__h797092 or _theResult___sfd__h797089) + always@(guard__h788415 or + _theResult___snd__h796351 or + out_sfd__h797089 or _theResult___sfd__h797086) begin - case (guard__h788418) + case (guard__h788415) 2'b0, 2'b01: - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q221 = - _theResult___snd__h796354[56:5]; + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q221 = + _theResult___snd__h796351[56:5]; 2'b10: - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q221 = - out_sfd__h797092; + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q221 = + out_sfd__h797089; 2'b11: - CASE_guard88418_0b0_theResult___snd96354_BITS__ETC__q221 = - _theResult___sfd__h797089; + CASE_guard88415_0b0_theResult___snd96351_BITS__ETC__q221 = + _theResult___sfd__h797086; endcase end - always@(guard__h740496 or - _theResult___fst_exp__h748722 or _theResult___exp__h749451) + always@(guard__h740493 or + _theResult___fst_exp__h748719 or _theResult___exp__h749448) begin - case (guard__h740496) + case (guard__h740493) 2'b0: - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q222 = - _theResult___fst_exp__h748722; + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q222 = + _theResult___fst_exp__h748719; 2'b01, 2'b10, 2'b11: - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q222 = - _theResult___exp__h749451; + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q222 = + _theResult___exp__h749448; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h748722 or + _theResult___fst_exp__h748719 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13297 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13295 or - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q222) + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q222) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13301 = - _theResult___fst_exp__h748722; + _theResult___fst_exp__h748719; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13301 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13297; @@ -42772,49 +42772,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13295; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13301 = - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q222; + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q222; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13301 = 11'd0; endcase end - always@(guard__h740496 or - _theResult___fst_exp__h748722 or - out_exp__h749454 or _theResult___exp__h749451) + always@(guard__h740493 or + _theResult___fst_exp__h748719 or + out_exp__h749451 or _theResult___exp__h749448) begin - case (guard__h740496) + case (guard__h740493) 2'b0, 2'b01: - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q223 = - _theResult___fst_exp__h748722; + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q223 = + _theResult___fst_exp__h748719; 2'b10: - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q223 = - out_exp__h749454; + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q223 = + out_exp__h749451; 2'b11: - CASE_guard40496_0b0_theResult___fst_exp48722_0_ETC__q223 = - _theResult___exp__h749451; + CASE_guard40493_0b0_theResult___fst_exp48719_0_ETC__q223 = + _theResult___exp__h749448; endcase end - always@(guard__h749565 or - _theResult___fst_exp__h757555 or _theResult___exp__h758235) + always@(guard__h749562 or + _theResult___fst_exp__h757552 or _theResult___exp__h758232) begin - case (guard__h749565) + case (guard__h749562) 2'b0: - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q224 = - _theResult___fst_exp__h757555; + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q224 = + _theResult___fst_exp__h757552; 2'b01, 2'b10, 2'b11: - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q224 = - _theResult___exp__h758235; + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q224 = + _theResult___exp__h758232; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h757555 or + _theResult___fst_exp__h757552 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13328 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13326 or - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q224) + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q224) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13332 = - _theResult___fst_exp__h757555; + _theResult___fst_exp__h757552; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13332 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13328; @@ -42823,49 +42823,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13326; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13332 = - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q224; + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q224; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13332 = 11'd0; endcase end - always@(guard__h749565 or - _theResult___fst_exp__h757555 or - out_exp__h758238 or _theResult___exp__h758235) + always@(guard__h749562 or + _theResult___fst_exp__h757552 or + out_exp__h758235 or _theResult___exp__h758232) begin - case (guard__h749565) + case (guard__h749562) 2'b0, 2'b01: - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q225 = - _theResult___fst_exp__h757555; + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q225 = + _theResult___fst_exp__h757552; 2'b10: - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q225 = - out_exp__h758238; + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q225 = + out_exp__h758235; 2'b11: - CASE_guard49565_0b0_theResult___fst_exp57555_0_ETC__q225 = - _theResult___exp__h758235; + CASE_guard49562_0b0_theResult___fst_exp57552_0_ETC__q225 = + _theResult___exp__h758232; endcase end - always@(guard__h731184 or - _theResult___snd__h739096 or _theResult___sfd__h739801) + always@(guard__h731181 or + _theResult___snd__h739093 or _theResult___sfd__h739798) begin - case (guard__h731184) + case (guard__h731181) 2'b0: - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q226 = - _theResult___snd__h739096[56:5]; + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q226 = + _theResult___snd__h739093[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q226 = - _theResult___sfd__h739801; + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q226 = + _theResult___sfd__h739798; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h739096 or + _theResult___snd__h739093 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13354 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13352 or - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q226) + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q226) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13358 = - _theResult___snd__h739096[56:5]; + _theResult___snd__h739093[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13358 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13354; @@ -42874,48 +42874,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13352; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13358 = - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q226; + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q226; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13358 = 52'd0; endcase end - always@(guard__h731184 or - _theResult___snd__h739096 or - out_sfd__h739804 or _theResult___sfd__h739801) + always@(guard__h731181 or + _theResult___snd__h739093 or + out_sfd__h739801 or _theResult___sfd__h739798) begin - case (guard__h731184) + case (guard__h731181) 2'b0, 2'b01: - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q227 = - _theResult___snd__h739096[56:5]; + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q227 = + _theResult___snd__h739093[56:5]; 2'b10: - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q227 = - out_sfd__h739804; + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q227 = + out_sfd__h739801; 2'b11: - CASE_guard31184_0b0_theResult___snd39096_BITS__ETC__q227 = - _theResult___sfd__h739801; + CASE_guard31181_0b0_theResult___snd39093_BITS__ETC__q227 = + _theResult___sfd__h739798; endcase end - always@(guard__h740496 or sfdin__h748716 or _theResult___sfd__h749452) + always@(guard__h740493 or sfdin__h748713 or _theResult___sfd__h749449) begin - case (guard__h740496) + case (guard__h740493) 2'b0: - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q228 = - sfdin__h748716[56:5]; + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q228 = + sfdin__h748713[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q228 = - _theResult___sfd__h749452; + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q228 = + _theResult___sfd__h749449; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h748716 or + sfdin__h748713 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13381 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13379 or - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q228) + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q228) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13385 = - sfdin__h748716[56:5]; + sfdin__h748713[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13385 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13381; @@ -42924,48 +42924,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13379; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13385 = - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q228; + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q228; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13385 = 52'd0; endcase end - always@(guard__h740496 or - sfdin__h748716 or out_sfd__h749455 or _theResult___sfd__h749452) + always@(guard__h740493 or + sfdin__h748713 or out_sfd__h749452 or _theResult___sfd__h749449) begin - case (guard__h740496) + case (guard__h740493) 2'b0, 2'b01: - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q229 = - sfdin__h748716[56:5]; + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q229 = + sfdin__h748713[56:5]; 2'b10: - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q229 = - out_sfd__h749455; + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q229 = + out_sfd__h749452; 2'b11: - CASE_guard40496_0b0_sfdin48716_BITS_56_TO_5_0b_ETC__q229 = - _theResult___sfd__h749452; + CASE_guard40493_0b0_sfdin48713_BITS_56_TO_5_0b_ETC__q229 = + _theResult___sfd__h749449; endcase end - always@(guard__h749565 or - _theResult___snd__h757501 or _theResult___sfd__h758236) + always@(guard__h749562 or + _theResult___snd__h757498 or _theResult___sfd__h758233) begin - case (guard__h749565) + case (guard__h749562) 2'b0: - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q230 = - _theResult___snd__h757501[56:5]; + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q230 = + _theResult___snd__h757498[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q230 = - _theResult___sfd__h758236; + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q230 = + _theResult___sfd__h758233; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h757501 or + _theResult___snd__h757498 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13400 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13398 or - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q230) + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q230) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13404 = - _theResult___snd__h757501[56:5]; + _theResult___snd__h757498[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13404 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13400; @@ -42974,49 +42974,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13398; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13404 = - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q230; + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q230; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d13404 = 52'd0; endcase end - always@(guard__h749565 or - _theResult___snd__h757501 or - out_sfd__h758239 or _theResult___sfd__h758236) + always@(guard__h749562 or + _theResult___snd__h757498 or + out_sfd__h758236 or _theResult___sfd__h758233) begin - case (guard__h749565) + case (guard__h749562) 2'b0, 2'b01: - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q231 = - _theResult___snd__h757501[56:5]; + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q231 = + _theResult___snd__h757498[56:5]; 2'b10: - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q231 = - out_sfd__h758239; + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q231 = + out_sfd__h758236; 2'b11: - CASE_guard49565_0b0_theResult___snd57501_BITS__ETC__q231 = - _theResult___sfd__h758236; + CASE_guard49562_0b0_theResult___snd57498_BITS__ETC__q231 = + _theResult___sfd__h758233; endcase end - always@(guard__h809341 or - _theResult___snd__h817253 or _theResult___sfd__h817958) + always@(guard__h809338 or + _theResult___snd__h817250 or _theResult___sfd__h817955) begin - case (guard__h809341) + case (guard__h809338) 2'b0: - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q232 = - _theResult___snd__h817253[56:5]; + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q232 = + _theResult___snd__h817250[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q232 = - _theResult___sfd__h817958; + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q232 = + _theResult___sfd__h817955; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h817253 or + _theResult___snd__h817250 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14064 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14062 or - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q232) + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q232) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14068 = - _theResult___snd__h817253[56:5]; + _theResult___snd__h817250[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14068 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14064; @@ -43025,48 +43025,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14062; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14068 = - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q232; + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q232; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14068 = 52'd0; endcase end - always@(guard__h809341 or - _theResult___snd__h817253 or - out_sfd__h817961 or _theResult___sfd__h817958) + always@(guard__h809338 or + _theResult___snd__h817250 or + out_sfd__h817958 or _theResult___sfd__h817955) begin - case (guard__h809341) + case (guard__h809338) 2'b0, 2'b01: - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q233 = - _theResult___snd__h817253[56:5]; + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q233 = + _theResult___snd__h817250[56:5]; 2'b10: - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q233 = - out_sfd__h817961; + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q233 = + out_sfd__h817958; 2'b11: - CASE_guard09341_0b0_theResult___snd17253_BITS__ETC__q233 = - _theResult___sfd__h817958; + CASE_guard09338_0b0_theResult___snd17250_BITS__ETC__q233 = + _theResult___sfd__h817955; endcase end - always@(guard__h818653 or sfdin__h826873 or _theResult___sfd__h827609) + always@(guard__h818650 or sfdin__h826870 or _theResult___sfd__h827606) begin - case (guard__h818653) + case (guard__h818650) 2'b0: - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q234 = - sfdin__h826873[56:5]; + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q234 = + sfdin__h826870[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q234 = - _theResult___sfd__h827609; + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q234 = + _theResult___sfd__h827606; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h826873 or + sfdin__h826870 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14090 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14088 or - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q234) + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q234) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14094 = - sfdin__h826873[56:5]; + sfdin__h826870[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14094 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14090; @@ -43075,24 +43075,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14088; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14094 = - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q234; + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q234; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14094 = 52'd0; endcase end - always@(guard__h818653 or - sfdin__h826873 or out_sfd__h827612 or _theResult___sfd__h827609) + always@(guard__h818650 or + sfdin__h826870 or out_sfd__h827609 or _theResult___sfd__h827606) begin - case (guard__h818653) + case (guard__h818650) 2'b0, 2'b01: - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q235 = - sfdin__h826873[56:5]; + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q235 = + sfdin__h826870[56:5]; 2'b10: - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q235 = - out_sfd__h827612; + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q235 = + out_sfd__h827609; 2'b11: - CASE_guard18653_0b0_sfdin26873_BITS_56_TO_5_0b_ETC__q235 = - _theResult___sfd__h827609; + CASE_guard18650_0b0_sfdin26870_BITS_56_TO_5_0b_ETC__q235 = + _theResult___sfd__h827606; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43127,28 +43127,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__2610_B_ETC___d15091; endcase end - always@(guard__h827722 or - _theResult___snd__h835658 or _theResult___sfd__h836393) + always@(guard__h827719 or + _theResult___snd__h835655 or _theResult___sfd__h836390) begin - case (guard__h827722) + case (guard__h827719) 2'b0: - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q236 = - _theResult___snd__h835658[56:5]; + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q236 = + _theResult___snd__h835655[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q236 = - _theResult___sfd__h836393; + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q236 = + _theResult___sfd__h836390; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h835658 or + _theResult___snd__h835655 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14109 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14107 or - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q236) + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q236) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14113 = - _theResult___snd__h835658[56:5]; + _theResult___snd__h835655[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14113 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14109; @@ -43157,25 +43157,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14107; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14113 = - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q236; + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q236; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__261_ETC___d14113 = 52'd0; endcase end - always@(guard__h827722 or - _theResult___snd__h835658 or - out_sfd__h836396 or _theResult___sfd__h836393) + always@(guard__h827719 or + _theResult___snd__h835655 or + out_sfd__h836393 or _theResult___sfd__h836390) begin - case (guard__h827722) + case (guard__h827719) 2'b0, 2'b01: - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q237 = - _theResult___snd__h835658[56:5]; + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q237 = + _theResult___snd__h835655[56:5]; 2'b10: - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q237 = - out_sfd__h836396; + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q237 = + out_sfd__h836393; 2'b11: - CASE_guard27722_0b0_theResult___snd35658_BITS__ETC__q237 = - _theResult___sfd__h836393; + CASE_guard27719_0b0_theResult___snd35655_BITS__ETC__q237 = + _theResult___sfd__h836390; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43727,10 +43727,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h951774 or + always@(k__h951769 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h951774) + case (k__h951769) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__127_ETC___d21284 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -43750,10 +43750,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h951774 or + always@(k__h951769 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h951774) + case (k__h951769) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1273_co_ETC___d21306 = coreFix_aluExe_0_rsAlu$canEnq; @@ -43970,7 +43970,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h976269 or + always@(idx__h976264 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0337_BITS_26_ETC___d21722 or coreFix_aluExe_0_rsAlu$canEnq or @@ -43980,7 +43980,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0337_BITS_267_TO_ETC___d21727 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h976269) + case (idx__h976264) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0335_AN_ETC___d21750 = fetchStage$pipelines_0_canDeq && @@ -44084,15 +44084,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1367_AND__ETC___d21712; endcase end - always@(k__h951774 or + always@(k__h951769 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h951774) + case (k__h951769) 1'd0: - CASE_k51774_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = + CASE_k51769_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k51774_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = + CASE_k51769_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -44128,7 +44128,7 @@ module mkCore(CLK, regRenamingTable_RDY_rename_0_getRename__1098__ETC___d21924; endcase end - always@(idx__h976269 or + always@(idx__h976264 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -44138,7 +44138,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0337_BITS_26_ETC___d21981 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h976269) + case (idx__h976264) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__033_ETC___d21986 = (!fetchStage$pipelines_0_canDeq || @@ -44510,6 +44510,18 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end always@(coreFix_memExe_memRespLdQ_deqP or coreFix_memExe_memRespLdQ_data_0 or coreFix_memExe_memRespLdQ_data_1) @@ -44523,18 +44535,6 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1[127:64]; endcase end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = - coreFix_memExe_forwardQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = - coreFix_memExe_forwardQ_data_1[127:64]; - endcase - end always@(coreFix_memExe_memRespLdQ_deqP or coreFix_memExe_memRespLdQ_data_0 or coreFix_memExe_memRespLdQ_data_1) @@ -44565,12 +44565,12 @@ module mkCore(CLK, begin case (commitStage_commitTrap[36:32]) 5'd0, 5'd3: - trap_val__h1005091 = + trap_val__h1005086 = SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22824; 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h1005091 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h1005091 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h1005091 = 64'd0; + trap_val__h1005086 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h1005086 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h1005086 = 64'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -46288,17 +46288,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h863692 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h863692 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h863692 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h863692 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h863689 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h863689 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h863689 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h863689 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h863692 = + thin_reserved__h863689 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17192; - 5'd28: thin_reserved__h863692 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h863692 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h863692 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h863692 = + 5'd28: thin_reserved__h863689 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h863689 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h863689 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h863689 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17198; endcase end @@ -46312,17 +46312,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h904588 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h904588 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h904588 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h904588 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h904584 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h904584 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h904584 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h904584 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h904588 = + thin_reserved__h904584 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17192; - 5'd28: thin_reserved__h904588 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h904588 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h904588 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h904588 = + 5'd28: thin_reserved__h904584 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h904584 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h904584 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h904584 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17198; endcase end @@ -46336,17 +46336,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h863940 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h863940 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h863940 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h863940 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h863937 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h863937 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h863937 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h863937 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h863940 = + thin_perms_soft__h863937 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16878; - 5'd28: thin_perms_soft__h863940 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h863940 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h863940 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h863940 = + 5'd28: thin_perms_soft__h863937 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h863937 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h863937 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h863937 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16884; endcase end @@ -46360,17 +46360,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h904764 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h904764 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h904764 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h904764 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h904760 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h904760 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h904760 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h904760 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h904764 = + thin_perms_soft__h904760 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16878; - 5'd28: thin_perms_soft__h904764 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h904764 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h904764 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h904764 = + 5'd28: thin_perms_soft__h904760 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h904760 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h904760 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h904760 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16884; endcase end @@ -46384,17 +46384,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h863688 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h863688 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h863688 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h863688 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h863685 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h863685 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h863685 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h863685 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h863688 = + thin_address__h863685 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16834; - 5'd28: thin_address__h863688 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h863688 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h863688 = csrf_mScratchC_reg[151:86]; - default: thin_address__h863688 = + 5'd28: thin_address__h863685 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h863685 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h863685 = csrf_mScratchC_reg[151:86]; + default: thin_address__h863685 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16840; endcase end @@ -46408,17 +46408,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h904584 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h904584 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h904584 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h904584 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h904580 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h904580 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h904580 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h904580 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h904584 = + thin_address__h904580 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16834; - 5'd28: thin_address__h904584 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h904584 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h904584 = csrf_mScratchC_reg[151:86]; - default: thin_address__h904584 = + 5'd28: thin_address__h904580 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h904580 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h904580 = csrf_mScratchC_reg[151:86]; + default: thin_address__h904580 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16840; endcase end @@ -46432,17 +46432,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h865687 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h865687 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h865687 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h865687 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h865684 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h865684 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h865684 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h865684 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h865687 = + thin_bounds_baseBits__h865684 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_baseBits__h865687 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h865687 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h865687 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h865687 = + 5'd28: thin_bounds_baseBits__h865684 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h865684 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h865684 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h865684 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -46456,17 +46456,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h905991 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h905991 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h905991 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h905991 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h905987 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h905987 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h905987 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h905987 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h905991 = + thin_bounds_baseBits__h905987 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_baseBits__h905991 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h905991 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h905991 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h905991 = + 5'd28: thin_bounds_baseBits__h905987 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h905987 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h905987 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h905987 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -46480,17 +46480,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h865686 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h865686 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h865686 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h865686 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h865683 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h865683 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h865683 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h865683 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h865686 = + thin_bounds_topBits__h865683 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17309; - 5'd28: thin_bounds_topBits__h865686 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h865686 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h865686 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h865686 = + 5'd28: thin_bounds_topBits__h865683 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h865683 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h865683 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h865683 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17315; endcase end @@ -46504,17 +46504,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h905990 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h905990 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h905990 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h905990 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h905986 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h905986 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h905986 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h905986 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h905990 = + thin_bounds_topBits__h905986 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17309; - 5'd28: thin_bounds_topBits__h905990 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h905990 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h905990 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h905990 = + 5'd28: thin_bounds_topBits__h905986 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h905986 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h905986 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h905986 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17315; endcase end @@ -46528,17 +46528,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h863689 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h863689 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h863689 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h863689 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h863686 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h863686 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h863686 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h863686 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h863689 = + thin_addrBits__h863686 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16856; - 5'd28: thin_addrBits__h863689 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h863689 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h863689 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h863689 = + 5'd28: thin_addrBits__h863686 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h863686 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h863686 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h863686 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16862; endcase end @@ -46552,17 +46552,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h904585 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h904585 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h904585 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h904585 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h904581 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h904581 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h904581 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h904581 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h904585 = + thin_addrBits__h904581 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16856; - 5'd28: thin_addrBits__h904585 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h904585 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h904585 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h904585 = + 5'd28: thin_addrBits__h904581 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h904581 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h904581 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h904581 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16862; endcase end @@ -47146,17 +47146,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h863693 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h863693 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h863693 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h863693 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h863690 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h863690 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h863690 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h863690 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h863693 = + thin_otype__h863690 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17214; - 5'd28: thin_otype__h863693 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h863693 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h863693 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h863693 = + 5'd28: thin_otype__h863690 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h863690 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h863690 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h863690 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17220; endcase end @@ -47170,17 +47170,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h904589 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h904589 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h904589 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h904589 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h904585 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h904585 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h904585 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h904585 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h904589 = + thin_otype__h904585 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17214; - 5'd28: thin_otype__h904589 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h904589 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h904589 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h904589 = + 5'd28: thin_otype__h904585 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h904585 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h904585 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h904585 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17220; endcase end @@ -53579,7 +53579,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - next_pc__h1018619[63:0] != address__h1018672) + next_pc__h1018614[63:0] != address__h1018667) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -53981,8 +53981,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[729] && - (x__h872605 != coreFix_aluExe_1_regToExeQ$first[177:49] || - coreFix_aluExe_1_regToExeQ$first[177:49] != y__h872859)) + (x__h872602 != coreFix_aluExe_1_regToExeQ$first[177:49] || + coreFix_aluExe_1_regToExeQ$first[177:49] != y__h872856)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && @@ -53992,8 +53992,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[716] && - (x__h872605 != coreFix_aluExe_1_regToExeQ$first[177:49] || - coreFix_aluExe_1_regToExeQ$first[177:49] != y__h872859)) + (x__h872602 != coreFix_aluExe_1_regToExeQ$first[177:49] || + coreFix_aluExe_1_regToExeQ$first[177:49] != y__h872856)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -54008,8 +54008,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[729] && - (x__h912582 != coreFix_aluExe_0_regToExeQ$first[177:49] || - coreFix_aluExe_0_regToExeQ$first[177:49] != y__h912836)) + (x__h912578 != coreFix_aluExe_0_regToExeQ$first[177:49] || + coreFix_aluExe_0_regToExeQ$first[177:49] != y__h912832)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -54019,8 +54019,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[716] && - (x__h912582 != coreFix_aluExe_0_regToExeQ$first[177:49] || - coreFix_aluExe_0_regToExeQ$first[177:49] != y__h912836)) + (x__h912578 != coreFix_aluExe_0_regToExeQ$first[177:49] || + coreFix_aluExe_0_regToExeQ$first[177:49] != y__h912832)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -56568,17 +56568,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h257291); + $write("'h%h", value__h257289); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h257455); + $write("'h%h", value__h257453); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h257567[64:0]); + $write("'h%h", x__h257565[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -63518,14 +63518,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h215806 = $time; + v__h215805 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h215806, "[doRespLdMem]", " "); + $write("%t : ", v__h215805, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h215234); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h215233); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -63669,15 +63669,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h218142 = $time; + v__h218141 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h218142, "[doRespLdForward]", " "); + $write("%t : ", v__h218141, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h217587); + $write("'h%h", t__h217586); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -63846,14 +63846,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5596) begin - v__h275333 = $time; + v__h275330 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5596) - $write("%t : [Ld resp] ", v__h275333); + $write("%t : [Ld resp] ", v__h275330); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -65543,13 +65543,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5600) begin - v__h351091 = $time; + v__h351088 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5600) - $write("%t : [Ld resp] ", v__h351091); + $write("%t : [Ld resp] ", v__h351088); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5600) @@ -67449,7 +67449,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h427707 = $time; + v__h427704 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -67457,7 +67457,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h427707); + $write("%t : [Ld resp] ", v__h427704); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -69966,17 +69966,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h242528); + $write("'h%h", value__h242527); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h242692); + $write("'h%h", value__h242691); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h242804[64:0]); + $write("'h%h", x__h242803[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -70016,17 +70016,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h243685); + $write("'h%h", value__h243684); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h243849); + $write("'h%h", value__h243848); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h243961[64:0]); + $write("'h%h", x__h243960[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -73139,7 +73139,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h841822 == 2'd0) + v__h841819 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index bf519bc..724f0b6 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:03 BST 2020 +// On Wed Jun 24 20:23:02 BST 2020 // // // Ports: @@ -81,18 +81,22 @@ // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 +// cpu_imem_master_bvalid I 1 // cpu_imem_master_bid I 6 // cpu_imem_master_bresp I 2 // cpu_imem_master_arready I 1 +// cpu_imem_master_rvalid I 1 // cpu_imem_master_rid I 6 // cpu_imem_master_rdata I 64 // cpu_imem_master_rresp I 2 // cpu_imem_master_rlast I 1 // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 +// cpu_dmem_master_bvalid I 1 // cpu_dmem_master_bid I 6 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 +// cpu_dmem_master_rvalid I 1 // cpu_dmem_master_rid I 6 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg @@ -120,10 +124,6 @@ // ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 // EN_start I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_rvalid I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_rvalid I 1 // EN_dmi_read_addr I 1 // EN_dmi_write I 1 // EN_ndm_reset_client_response_put I 1 @@ -197,9 +197,9 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_imem_master_wready, + cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, - cpu_imem_master_bvalid, cpu_imem_master_bready, @@ -227,11 +227,11 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_imem_master_arready, + cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, - cpu_imem_master_rvalid, cpu_imem_master_rready, @@ -269,9 +269,9 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_dmem_master_wready, + cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, - cpu_dmem_master_bvalid, cpu_dmem_master_bready, @@ -299,11 +299,11 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_dmem_master_arready, + cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, - cpu_dmem_master_rvalid, cpu_dmem_master_rready, @@ -434,9 +434,9 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_imem_master_wready; // action method cpu_imem_master_b_bflit + input cpu_imem_master_bvalid; input [5 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; - input cpu_imem_master_bvalid; // value method cpu_imem_master_b_bready output cpu_imem_master_bready; @@ -480,11 +480,11 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_imem_master_arready; // action method cpu_imem_master_r_rflit + input cpu_imem_master_rvalid; input [5 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; - input cpu_imem_master_rvalid; // value method cpu_imem_master_r_rready output cpu_imem_master_rready; @@ -545,9 +545,9 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_dmem_master_wready; // action method cpu_dmem_master_b_bflit + input cpu_dmem_master_bvalid; input [5 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; - input cpu_dmem_master_bvalid; // value method cpu_dmem_master_b_bready output cpu_dmem_master_bready; @@ -591,11 +591,11 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_dmem_master_arready; // action method cpu_dmem_master_r_rflit + input cpu_dmem_master_rvalid; input [5 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; - input cpu_dmem_master_rvalid; // value method cpu_dmem_master_r_rready output cpu_dmem_master_rready; @@ -746,6 +746,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // inlined wires wire [172 : 0] split_0_doPut$wget, split_1_doPut$wget, split_2_doPut$wget; + wire [171 : 0] merged_0_outflit$wget, merged_1_outflit$wget; wire [99 : 0] tagController_tmp_shimMaster_arff_rv$port0__write_1, tagController_tmp_shimMaster_arff_rv$port1__read, tagController_tmp_shimMaster_arff_rv$port2__read, @@ -762,29 +763,36 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_awff_rv$port1__read, tagController_tmp_shimSlave_awff_rv$port2__read, tagController_tmp_shimSlave_awff_rv$port3__read, - ug_uncached_mem_shim_master_u_ar_peekWire$wget, - ug_uncached_mem_shim_master_u_aw_peekWire$wget; - wire [97 : 0] ssNoSynth_0_ar_buffer_enqw$wget, - ssNoSynth_1_ar_buffer_enqw$wget, - ssNoSynth_1_aw_buffer_enqw$wget, - ssNoSynth_2_ar_buffer_enqw$wget, - ssNoSynth_2_aw_buffer_enqw$wget, + uncached_mem_master_arSynth_src_peekWire$wget, + uncached_mem_master_awSynth_src_peekWire$wget; + wire [97 : 0] slave_vector_0_arSynth_snk_putWire$wget, + slave_vector_0_awSynth_snk_putWire$wget, + ssNoSynth_0_arNoSynth_buffer_enqw$wget, + ssNoSynth_1_arNoSynth_buffer_enqw$wget, + ssNoSynth_1_arNoSynth_src_peekWire$wget, + ssNoSynth_1_awNoSynth_src_peekWire$wget, + ssNoSynth_2_arNoSynth_buffer_enqw$wget, + ssNoSynth_2_arNoSynth_src_peekWire$wget, + ssNoSynth_2_awNoSynth_src_peekWire$wget, tagController_tmp_ug_slave_u_ar_putWire$wget, - tagController_tmp_ug_slave_u_aw_putWire$wget; - wire [96 : 0] ifcs_0_1_noRoute_currentReq$port0__write_1, - ifcs_0_1_noRoute_currentReq$port1__read, - ifcs_0_noRoute_inner_currentReq$port0__write_1, + tagController_tmp_ug_slave_u_aw_putWire$wget, + tmp2_arNoSynth_buffer_enqw$wget, + tmp2_awNoSynth_buffer_enqw$wget; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$port1__read, ifcs_0_noRoute_inner_currentReq$port1__read, - ifcs_1_1_noRoute_currentReq$port0__write_1, ifcs_1_1_noRoute_currentReq$port1__read, - ifcs_1_noRoute_inner_currentReq$port0__write_1, - ifcs_1_noRoute_inner_currentReq$port1__read; + ifcs_1_noRoute_inner_currentReq$port1__read, + msNoSynth_1_arNoSynth_buffer_enqw$wget, + msNoSynth_1_awNoSynth_buffer_enqw$wget; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, tagController_tmp_shimSlave_wff_rv$port1__read, tagController_tmp_shimSlave_wff_rv$port2__read, tagController_tmp_shimSlave_wff_rv$port3__read; - wire [73 : 0] ssNoSynth_1_w_buffer_enqw$wget, - ssNoSynth_2_w_buffer_enqw$wget, + wire [73 : 0] msNoSynth_1_wNoSynth_buffer_enqw$wget, + proc_uncached_wSynth_src_peekWire$wget, + slave_vector_0_wSynth_snk_putWire$wget, + ssNoSynth_1_wNoSynth_src_peekWire$wget, + ssNoSynth_2_wNoSynth_src_peekWire$wget, tagController_tmp_shimMaster_rff_rv$port0__write_1, tagController_tmp_shimMaster_rff_rv$port1__read, tagController_tmp_shimMaster_rff_rv$port2__read, @@ -797,13 +805,17 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_rff_rv$port1__read, tagController_tmp_shimSlave_rff_rv$port2__read, tagController_tmp_shimSlave_rff_rv$port3__read, - tagController_tmp_ug_slave_u_w_putWire$wget; - wire [72 : 0] tagController_tmp_ug_master_u_r_putWire$wget, - tmp2_r_buffer_enqw$wget, - ug_uncached_mem_shim_master_u_r_putWire$wget; - wire [71 : 0] msNoSynth_0_r_buffer_enqw$wget, - msNoSynth_1_r_buffer_enqw$wget, - tmp0_r_buffer_enqw$wget; + tagController_tmp_ug_slave_u_w_putWire$wget, + tmp2_wNoSynth_buffer_enqw$wget; + wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_enqw$wget, + ssNoSynth_2_rNoSynth_buffer_enqw$wget, + tagController_tmp_ug_master_u_r_putWire$wget, + tmp2_rNoSynth_src_peekWire$wget, + uncached_mem_master_rSynth_snk_putWire$wget; + wire [71 : 0] msNoSynth_0_rNoSynth_buffer_enqw$wget, + msNoSynth_1_rNoSynth_buffer_enqw$wget, + msNoSynth_1_rNoSynth_src_peekWire$wget, + proc_uncached_rSynth_snk_putWire$wget; wire [8 : 0] ifcs_0_1_noRoute_flitCount$port0__write_1, ifcs_0_1_noRoute_flitCount$port1__write_1, ifcs_0_1_noRoute_flitCount$port2__read, @@ -819,12 +831,18 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_bff_rv$port2__read, tagController_tmp_shimSlave_bff_rv$port3__read, tagController_tmp_ug_master_u_b_putWire$wget, - ug_uncached_mem_shim_master_u_b_putWire$wget; - wire [6 : 0] tmp2_b_buffer_enqw$wget; - wire [5 : 0] msNoSynth_0_b_buffer_enqw$wget, - msNoSynth_1_b_buffer_enqw$wget, - tmp0_b_buffer_enqw$wget; - wire flitToSink_0$whas, + uncached_mem_master_bSynth_snk_putWire$wget; + wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_enqw$wget, + ssNoSynth_2_bNoSynth_buffer_enqw$wget, + tmp2_bNoSynth_src_peekWire$wget; + wire [5 : 0] msNoSynth_0_bNoSynth_buffer_enqw$wget, + msNoSynth_1_bNoSynth_buffer_enqw$wget, + msNoSynth_1_bNoSynth_src_peekWire$wget, + proc_uncached_bSynth_snk_putWire$wget; + wire cached_mem_master_arSynth_src_dropWire$whas, + cached_mem_master_awSynth_src_dropWire$whas, + cached_mem_master_wSynth_src_dropWire$whas, + flitToSink_0$whas, flitToSink_1$whas, flitToSink_1_0$whas, flitToSink_1_0_1$whas, @@ -834,24 +852,22 @@ module mkCoreW(RST_N_dm_power_on_reset, flitToSink_1_1_1_1$whas, flitToSink_1_2$whas, flitToSink_2$whas, + ifcs_0_1_snk_putWire$whas, ifcs_0_noRoute_inner_currentReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$port1__read, ifcs_0_noRoute_inner_pendingReq$port2__read, + ifcs_0_snk_putWire$whas, + ifcs_1_1_snk_putWire$whas, ifcs_1_noRoute_inner_currentReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$port1__read, ifcs_1_noRoute_inner_pendingReq$port2__read, + ifcs_1_snk_putWire$whas, merged_0_doDrop$whas, merged_1_doDrop$whas, - msNoSynth_0_ar_dwReady$whas, - msNoSynth_0_b_buffer_enqw$whas, - msNoSynth_0_r_buffer_enqw$whas, - msNoSynth_0_w_dwReady$whas, - msNoSynth_1_ar_dwReady$whas, - msNoSynth_1_b_buffer_enqw$whas, - msNoSynth_1_r_buffer_enqw$whas, - msNoSynth_1_w_dwReady$whas, + msNoSynth_0_arNoSynth_buffer_dequeueing$whas, + msNoSynth_1_arNoSynth_buffer_dequeueing$whas, reqWires_0$wget, reqWires_1$wget, reqWires_1_0$wget, @@ -867,35 +883,25 @@ module mkCoreW(RST_N_dm_power_on_reset, sourceSelect_1_1$whas, sourceSelect_1_1_1$whas, sourceSelect_1_2$whas, - ssNoSynth_0_b_dwReady$whas, - ssNoSynth_0_r_dwReady$whas, - ssNoSynth_0_w_buffer_enqw$whas, - ssNoSynth_1_b_dwReady$whas, - ssNoSynth_1_r_dwReady$whas, - ssNoSynth_1_w_buffer_enqw$whas, - ssNoSynth_2_b_dwReady$whas, - ssNoSynth_2_r_dwReady$whas, - ssNoSynth_2_w_buffer_enqw$whas, + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_0_wNoSynth_buffer_enqw$whas, + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_1_wNoSynth_buffer_enqw$whas, + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_2_wNoSynth_buffer_enqw$whas, tagController_tmp_shimMaster_arff_rv$EN_port0__write, tagController_tmp_shimMaster_awff_rv$EN_port0__write, tagController_tmp_shimMaster_wff_rv$EN_port0__write, tagController_tmp_shimSlave_bff_rv$EN_port0__write, tagController_tmp_shimSlave_rff_rv$EN_port0__write, - tagController_tmp_ug_master_u_ar_dropWire$whas, - tagController_tmp_ug_master_u_aw_dropWire$whas, - tagController_tmp_ug_master_u_b_putWire$whas, - tagController_tmp_ug_master_u_r_putWire$whas, - tagController_tmp_ug_master_u_w_dropWire$whas, - tmp0_ar_dwReady$whas, - tmp0_aw_dwReady$whas, - tmp0_b_buffer_enqw$whas, - tmp0_r_buffer_enqw$whas, - tmp0_w_dwReady$whas, - ug_uncached_mem_shim_master_u_ar_dropWire$whas, - ug_uncached_mem_shim_master_u_aw_dropWire$whas, - ug_uncached_mem_shim_master_u_b_putWire$whas, - ug_uncached_mem_shim_master_u_r_putWire$whas, - ug_uncached_mem_shim_master_u_w_dropWire$whas; + uncached_mem_master_arSynth_src_dropWire$whas, + uncached_mem_master_awSynth_src_dropWire$whas, + uncached_mem_master_bSynth_snk_putWire$whas, + uncached_mem_master_rSynth_snk_putWire$whas, + uncached_mem_master_wSynth_src_dropWire$whas; // register activeSource_0 reg activeSource_0; @@ -1469,57 +1475,177 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_2_rspBack$ENQ, ifcs_2_rspBack$FULL_N; - // ports of submodule msNoSynth_0_b_buffer_ff - wire [5 : 0] msNoSynth_0_b_buffer_ff$D_IN, msNoSynth_0_b_buffer_ff$D_OUT; - wire msNoSynth_0_b_buffer_ff$CLR, - msNoSynth_0_b_buffer_ff$DEQ, - msNoSynth_0_b_buffer_ff$EMPTY_N, - msNoSynth_0_b_buffer_ff$ENQ, - msNoSynth_0_b_buffer_ff$FULL_N; + // ports of submodule merged_0_awff + wire [96 : 0] merged_0_awff$D_IN, merged_0_awff$D_OUT; + wire merged_0_awff$CLR, + merged_0_awff$DEQ, + merged_0_awff$EMPTY_N, + merged_0_awff$ENQ, + merged_0_awff$FULL_N; - // ports of submodule msNoSynth_0_b_buffer_firstValid - wire msNoSynth_0_b_buffer_firstValid$D_IN, - msNoSynth_0_b_buffer_firstValid$EN, - msNoSynth_0_b_buffer_firstValid$Q_OUT; + // ports of submodule merged_0_wff + wire [73 : 0] merged_0_wff$D_IN, merged_0_wff$D_OUT; + wire merged_0_wff$CLR, + merged_0_wff$DEQ, + merged_0_wff$EMPTY_N, + merged_0_wff$ENQ, + merged_0_wff$FULL_N; - // ports of submodule msNoSynth_0_r_buffer_ff - wire [71 : 0] msNoSynth_0_r_buffer_ff$D_IN, msNoSynth_0_r_buffer_ff$D_OUT; - wire msNoSynth_0_r_buffer_ff$CLR, - msNoSynth_0_r_buffer_ff$DEQ, - msNoSynth_0_r_buffer_ff$EMPTY_N, - msNoSynth_0_r_buffer_ff$ENQ, - msNoSynth_0_r_buffer_ff$FULL_N; + // ports of submodule merged_1_awff + wire [96 : 0] merged_1_awff$D_IN, merged_1_awff$D_OUT; + wire merged_1_awff$CLR, + merged_1_awff$DEQ, + merged_1_awff$EMPTY_N, + merged_1_awff$ENQ, + merged_1_awff$FULL_N; - // ports of submodule msNoSynth_0_r_buffer_firstValid - wire msNoSynth_0_r_buffer_firstValid$D_IN, - msNoSynth_0_r_buffer_firstValid$EN, - msNoSynth_0_r_buffer_firstValid$Q_OUT; + // ports of submodule merged_1_wff + wire [73 : 0] merged_1_wff$D_IN, merged_1_wff$D_OUT; + wire merged_1_wff$CLR, + merged_1_wff$DEQ, + merged_1_wff$EMPTY_N, + merged_1_wff$ENQ, + merged_1_wff$FULL_N; - // ports of submodule msNoSynth_1_b_buffer_ff - wire [5 : 0] msNoSynth_1_b_buffer_ff$D_IN, msNoSynth_1_b_buffer_ff$D_OUT; - wire msNoSynth_1_b_buffer_ff$CLR, - msNoSynth_1_b_buffer_ff$DEQ, - msNoSynth_1_b_buffer_ff$EMPTY_N, - msNoSynth_1_b_buffer_ff$ENQ, - msNoSynth_1_b_buffer_ff$FULL_N; + // ports of submodule msNoSynth_0_arNoSynth_buffer_ff + wire [96 : 0] msNoSynth_0_arNoSynth_buffer_ff$D_IN, + msNoSynth_0_arNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_arNoSynth_buffer_ff$CLR, + msNoSynth_0_arNoSynth_buffer_ff$DEQ, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_arNoSynth_buffer_ff$ENQ, + msNoSynth_0_arNoSynth_buffer_ff$FULL_N; - // ports of submodule msNoSynth_1_b_buffer_firstValid - wire msNoSynth_1_b_buffer_firstValid$D_IN, - msNoSynth_1_b_buffer_firstValid$EN, - msNoSynth_1_b_buffer_firstValid$Q_OUT; + // ports of submodule msNoSynth_0_arNoSynth_buffer_firstValid + wire msNoSynth_0_arNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_arNoSynth_buffer_firstValid$EN, + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule msNoSynth_1_r_buffer_ff - wire [71 : 0] msNoSynth_1_r_buffer_ff$D_IN, msNoSynth_1_r_buffer_ff$D_OUT; - wire msNoSynth_1_r_buffer_ff$CLR, - msNoSynth_1_r_buffer_ff$DEQ, - msNoSynth_1_r_buffer_ff$EMPTY_N, - msNoSynth_1_r_buffer_ff$ENQ, - msNoSynth_1_r_buffer_ff$FULL_N; + // ports of submodule msNoSynth_0_awNoSynth_buffer_ff + wire [96 : 0] msNoSynth_0_awNoSynth_buffer_ff$D_IN, + msNoSynth_0_awNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_awNoSynth_buffer_ff$CLR, + msNoSynth_0_awNoSynth_buffer_ff$DEQ, + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_awNoSynth_buffer_ff$ENQ, + msNoSynth_0_awNoSynth_buffer_ff$FULL_N; - // ports of submodule msNoSynth_1_r_buffer_firstValid - wire msNoSynth_1_r_buffer_firstValid$D_IN, - msNoSynth_1_r_buffer_firstValid$EN, - msNoSynth_1_r_buffer_firstValid$Q_OUT; + // ports of submodule msNoSynth_0_awNoSynth_buffer_firstValid + wire msNoSynth_0_awNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_awNoSynth_buffer_firstValid$EN, + msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_bNoSynth_buffer_ff + wire [5 : 0] msNoSynth_0_bNoSynth_buffer_ff$D_IN, + msNoSynth_0_bNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_bNoSynth_buffer_ff$CLR, + msNoSynth_0_bNoSynth_buffer_ff$DEQ, + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_bNoSynth_buffer_ff$ENQ, + msNoSynth_0_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_bNoSynth_buffer_firstValid + wire msNoSynth_0_bNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_bNoSynth_buffer_firstValid$EN, + msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_rNoSynth_buffer_ff + wire [71 : 0] msNoSynth_0_rNoSynth_buffer_ff$D_IN, + msNoSynth_0_rNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_rNoSynth_buffer_ff$CLR, + msNoSynth_0_rNoSynth_buffer_ff$DEQ, + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_rNoSynth_buffer_ff$ENQ, + msNoSynth_0_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_rNoSynth_buffer_firstValid + wire msNoSynth_0_rNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_rNoSynth_buffer_firstValid$EN, + msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_wNoSynth_buffer_ff + wire [73 : 0] msNoSynth_0_wNoSynth_buffer_ff$D_IN, + msNoSynth_0_wNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_wNoSynth_buffer_ff$CLR, + msNoSynth_0_wNoSynth_buffer_ff$DEQ, + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_wNoSynth_buffer_ff$ENQ, + msNoSynth_0_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_wNoSynth_buffer_firstValid + wire msNoSynth_0_wNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_wNoSynth_buffer_firstValid$EN, + msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_arNoSynth_buffer_ff + wire [96 : 0] msNoSynth_1_arNoSynth_buffer_ff$D_IN, + msNoSynth_1_arNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_arNoSynth_buffer_ff$CLR, + msNoSynth_1_arNoSynth_buffer_ff$DEQ, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_arNoSynth_buffer_ff$ENQ, + msNoSynth_1_arNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_arNoSynth_buffer_firstValid + wire msNoSynth_1_arNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_arNoSynth_buffer_firstValid$EN, + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_awNoSynth_buffer_ff + wire [96 : 0] msNoSynth_1_awNoSynth_buffer_ff$D_IN, + msNoSynth_1_awNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_awNoSynth_buffer_ff$CLR, + msNoSynth_1_awNoSynth_buffer_ff$DEQ, + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_awNoSynth_buffer_ff$ENQ, + msNoSynth_1_awNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_awNoSynth_buffer_firstValid + wire msNoSynth_1_awNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_awNoSynth_buffer_firstValid$EN, + msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_bNoSynth_buffer_ff + wire [5 : 0] msNoSynth_1_bNoSynth_buffer_ff$D_IN, + msNoSynth_1_bNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_bNoSynth_buffer_ff$CLR, + msNoSynth_1_bNoSynth_buffer_ff$DEQ, + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_bNoSynth_buffer_ff$ENQ, + msNoSynth_1_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_bNoSynth_buffer_firstValid + wire msNoSynth_1_bNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_bNoSynth_buffer_firstValid$EN, + msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_rNoSynth_buffer_ff + wire [71 : 0] msNoSynth_1_rNoSynth_buffer_ff$D_IN, + msNoSynth_1_rNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_rNoSynth_buffer_ff$CLR, + msNoSynth_1_rNoSynth_buffer_ff$DEQ, + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_rNoSynth_buffer_ff$ENQ, + msNoSynth_1_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_rNoSynth_buffer_firstValid + wire msNoSynth_1_rNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_rNoSynth_buffer_firstValid$EN, + msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_wNoSynth_buffer_ff + wire [73 : 0] msNoSynth_1_wNoSynth_buffer_ff$D_IN, + msNoSynth_1_wNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_wNoSynth_buffer_ff$CLR, + msNoSynth_1_wNoSynth_buffer_ff$DEQ, + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_wNoSynth_buffer_ff$ENQ, + msNoSynth_1_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_wNoSynth_buffer_firstValid + wire msNoSynth_1_wNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_wNoSynth_buffer_firstValid$EN, + msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, @@ -1591,7 +1717,10 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip; // ports of submodule proc + wire [96 : 0] proc$master1_ar_peek, proc$master1_aw_peek; wire [76 : 0] proc$hart0_csr_mem_server_request_put; + wire [73 : 0] proc$master1_w_peek; + wire [71 : 0] proc$master1_r_put_val; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; wire [64 : 0] proc$hart0_csr_mem_server_response_get, @@ -1604,10 +1733,6 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awaddr, proc$master0_rdata, proc$master0_wdata, - proc$master1_araddr, - proc$master1_awaddr, - proc$master1_rdata, - proc$master1_wdata, proc$start_fromhostAddr, proc$start_startpc, proc$start_tohostAddr; @@ -1616,10 +1741,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$debug_module_mem_server_wstrb, proc$master0_arlen, proc$master0_awlen, - proc$master0_wstrb, - proc$master1_arlen, - proc$master1_awlen, - proc$master1_wstrb; + proc$master0_wstrb; + wire [5 : 0] proc$master1_b_put_val; wire [4 : 0] proc$debug_module_mem_server_arid, proc$debug_module_mem_server_awid, proc$debug_module_mem_server_bid, @@ -1641,16 +1764,6 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awcache, proc$master0_awqos, proc$master0_awregion, - proc$master1_arcache, - proc$master1_arid, - proc$master1_arqos, - proc$master1_arregion, - proc$master1_awcache, - proc$master1_awid, - proc$master1_awqos, - proc$master1_awregion, - proc$master1_bid, - proc$master1_rid, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, @@ -1659,11 +1772,7 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arprot, proc$master0_arsize, proc$master0_awprot, - proc$master0_awsize, - proc$master1_arprot, - proc$master1_arsize, - proc$master1_awprot, - proc$master1_awsize; + proc$master0_awsize; wire [1 : 0] proc$debug_module_mem_server_arburst, proc$debug_module_mem_server_awburst, proc$debug_module_mem_server_bresp, @@ -1671,11 +1780,7 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arburst, proc$master0_awburst, proc$master0_bresp, - proc$master0_rresp, - proc$master1_arburst, - proc$master1_awburst, - proc$master1_bresp, - proc$master1_rresp; + proc$master0_rresp; wire proc$EN_hart0_csr_mem_server_request_put, proc$EN_hart0_csr_mem_server_response_get, proc$EN_hart0_fpr_mem_server_request_put, @@ -1685,6 +1790,11 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$EN_hart0_put_other_req_put, proc$EN_hart0_run_halt_server_request_put, proc$EN_hart0_run_halt_server_response_get, + proc$EN_master1_ar_drop, + proc$EN_master1_aw_drop, + proc$EN_master1_b_put, + proc$EN_master1_r_put, + proc$EN_master1_w_drop, proc$EN_set_verbosity, proc$EN_start, proc$RDY_hart0_csr_mem_server_request_put, @@ -1693,6 +1803,14 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$RDY_hart0_gpr_mem_server_response_get, proc$RDY_hart0_run_halt_server_request_put, proc$RDY_hart0_run_halt_server_response_get, + proc$RDY_master1_ar_drop, + proc$RDY_master1_ar_peek, + proc$RDY_master1_aw_drop, + proc$RDY_master1_aw_peek, + proc$RDY_master1_b_put, + proc$RDY_master1_r_put, + proc$RDY_master1_w_drop, + proc$RDY_master1_w_peek, proc$RDY_start, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, @@ -1729,21 +1847,11 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_wready, proc$master0_wuser, proc$master0_wvalid, - proc$master1_arlock, - proc$master1_arready, - proc$master1_arvalid, - proc$master1_awlock, - proc$master1_awready, - proc$master1_awvalid, - proc$master1_bready, - proc$master1_bvalid, - proc$master1_rlast, - proc$master1_rready, - proc$master1_ruser, - proc$master1_rvalid, - proc$master1_wlast, - proc$master1_wready, - proc$master1_wvalid, + proc$master1_ar_canPeek, + proc$master1_aw_canPeek, + proc$master1_b_canPut, + proc$master1_r_canPut, + proc$master1_w_canPeek, proc$non_maskable_interrupt_req_set_not_clear, proc$s_external_interrupt_req_set_not_clear, proc$start_running; @@ -1755,122 +1863,215 @@ module mkCoreW(RST_N_dm_power_on_reset, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr; - // ports of submodule ssNoSynth_0_ar_buffer_ff - wire [97 : 0] ssNoSynth_0_ar_buffer_ff$D_IN, ssNoSynth_0_ar_buffer_ff$D_OUT; - wire ssNoSynth_0_ar_buffer_ff$CLR, - ssNoSynth_0_ar_buffer_ff$DEQ, - ssNoSynth_0_ar_buffer_ff$EMPTY_N, - ssNoSynth_0_ar_buffer_ff$ENQ, - ssNoSynth_0_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_0_arNoSynth_buffer_ff$D_IN, + ssNoSynth_0_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_arNoSynth_buffer_ff$CLR, + ssNoSynth_0_arNoSynth_buffer_ff$DEQ, + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_arNoSynth_buffer_ff$ENQ, + ssNoSynth_0_arNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_ar_buffer_firstValid - wire ssNoSynth_0_ar_buffer_firstValid$D_IN, - ssNoSynth_0_ar_buffer_firstValid$EN, - ssNoSynth_0_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_arNoSynth_buffer_firstValid + wire ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_arNoSynth_buffer_firstValid$EN, + ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_0_aw_buffer_ff - wire [97 : 0] ssNoSynth_0_aw_buffer_ff$D_IN, ssNoSynth_0_aw_buffer_ff$D_OUT; - wire ssNoSynth_0_aw_buffer_ff$CLR, - ssNoSynth_0_aw_buffer_ff$DEQ, - ssNoSynth_0_aw_buffer_ff$EMPTY_N, - ssNoSynth_0_aw_buffer_ff$ENQ, - ssNoSynth_0_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_0_awNoSynth_buffer_ff$D_IN, + ssNoSynth_0_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_awNoSynth_buffer_ff$CLR, + ssNoSynth_0_awNoSynth_buffer_ff$DEQ, + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_awNoSynth_buffer_ff$ENQ, + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_aw_buffer_firstValid - wire ssNoSynth_0_aw_buffer_firstValid$D_IN, - ssNoSynth_0_aw_buffer_firstValid$EN, - ssNoSynth_0_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_awNoSynth_buffer_firstValid + wire ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_awNoSynth_buffer_firstValid$EN, + ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_0_w_buffer_ff - wire [73 : 0] ssNoSynth_0_w_buffer_ff$D_IN, ssNoSynth_0_w_buffer_ff$D_OUT; - wire ssNoSynth_0_w_buffer_ff$CLR, - ssNoSynth_0_w_buffer_ff$DEQ, - ssNoSynth_0_w_buffer_ff$EMPTY_N, - ssNoSynth_0_w_buffer_ff$ENQ, - ssNoSynth_0_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_0_bNoSynth_buffer_ff$D_IN, + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_bNoSynth_buffer_ff$CLR, + ssNoSynth_0_bNoSynth_buffer_ff$DEQ, + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_bNoSynth_buffer_ff$ENQ, + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_w_buffer_firstValid - wire ssNoSynth_0_w_buffer_firstValid$D_IN, - ssNoSynth_0_w_buffer_firstValid$EN, - ssNoSynth_0_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_bNoSynth_buffer_firstValid + wire ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_bNoSynth_buffer_firstValid$EN, + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_ar_buffer_ff - wire [97 : 0] ssNoSynth_1_ar_buffer_ff$D_IN, ssNoSynth_1_ar_buffer_ff$D_OUT; - wire ssNoSynth_1_ar_buffer_ff$CLR, - ssNoSynth_1_ar_buffer_ff$DEQ, - ssNoSynth_1_ar_buffer_ff$EMPTY_N, - ssNoSynth_1_ar_buffer_ff$ENQ, - ssNoSynth_1_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_0_rNoSynth_buffer_ff$D_IN, + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_rNoSynth_buffer_ff$CLR, + ssNoSynth_0_rNoSynth_buffer_ff$DEQ, + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_rNoSynth_buffer_ff$ENQ, + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_ar_buffer_firstValid - wire ssNoSynth_1_ar_buffer_firstValid$D_IN, - ssNoSynth_1_ar_buffer_firstValid$EN, - ssNoSynth_1_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_rNoSynth_buffer_firstValid + wire ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_rNoSynth_buffer_firstValid$EN, + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_aw_buffer_ff - wire [97 : 0] ssNoSynth_1_aw_buffer_ff$D_IN, ssNoSynth_1_aw_buffer_ff$D_OUT; - wire ssNoSynth_1_aw_buffer_ff$CLR, - ssNoSynth_1_aw_buffer_ff$DEQ, - ssNoSynth_1_aw_buffer_ff$EMPTY_N, - ssNoSynth_1_aw_buffer_ff$ENQ, - ssNoSynth_1_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_0_wNoSynth_buffer_ff$D_IN, + ssNoSynth_0_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_wNoSynth_buffer_ff$CLR, + ssNoSynth_0_wNoSynth_buffer_ff$DEQ, + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_wNoSynth_buffer_ff$ENQ, + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_aw_buffer_firstValid - wire ssNoSynth_1_aw_buffer_firstValid$D_IN, - ssNoSynth_1_aw_buffer_firstValid$EN, - ssNoSynth_1_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_wNoSynth_buffer_firstValid + wire ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_wNoSynth_buffer_firstValid$EN, + ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_w_buffer_ff - wire [73 : 0] ssNoSynth_1_w_buffer_ff$D_IN, ssNoSynth_1_w_buffer_ff$D_OUT; - wire ssNoSynth_1_w_buffer_ff$CLR, - ssNoSynth_1_w_buffer_ff$DEQ, - ssNoSynth_1_w_buffer_ff$EMPTY_N, - ssNoSynth_1_w_buffer_ff$ENQ, - ssNoSynth_1_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_1_arNoSynth_buffer_ff$D_IN, + ssNoSynth_1_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_arNoSynth_buffer_ff$CLR, + ssNoSynth_1_arNoSynth_buffer_ff$DEQ, + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_arNoSynth_buffer_ff$ENQ, + ssNoSynth_1_arNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_w_buffer_firstValid - wire ssNoSynth_1_w_buffer_firstValid$D_IN, - ssNoSynth_1_w_buffer_firstValid$EN, - ssNoSynth_1_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_arNoSynth_buffer_firstValid + wire ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_arNoSynth_buffer_firstValid$EN, + ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_ar_buffer_ff - wire [97 : 0] ssNoSynth_2_ar_buffer_ff$D_IN, ssNoSynth_2_ar_buffer_ff$D_OUT; - wire ssNoSynth_2_ar_buffer_ff$CLR, - ssNoSynth_2_ar_buffer_ff$DEQ, - ssNoSynth_2_ar_buffer_ff$EMPTY_N, - ssNoSynth_2_ar_buffer_ff$ENQ, - ssNoSynth_2_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_1_awNoSynth_buffer_ff$D_IN, + ssNoSynth_1_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_awNoSynth_buffer_ff$CLR, + ssNoSynth_1_awNoSynth_buffer_ff$DEQ, + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_awNoSynth_buffer_ff$ENQ, + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_ar_buffer_firstValid - wire ssNoSynth_2_ar_buffer_firstValid$D_IN, - ssNoSynth_2_ar_buffer_firstValid$EN, - ssNoSynth_2_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_awNoSynth_buffer_firstValid + wire ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_awNoSynth_buffer_firstValid$EN, + ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_aw_buffer_ff - wire [97 : 0] ssNoSynth_2_aw_buffer_ff$D_IN, ssNoSynth_2_aw_buffer_ff$D_OUT; - wire ssNoSynth_2_aw_buffer_ff$CLR, - ssNoSynth_2_aw_buffer_ff$DEQ, - ssNoSynth_2_aw_buffer_ff$EMPTY_N, - ssNoSynth_2_aw_buffer_ff$ENQ, - ssNoSynth_2_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_ff$D_IN, + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_bNoSynth_buffer_ff$CLR, + ssNoSynth_1_bNoSynth_buffer_ff$DEQ, + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_bNoSynth_buffer_ff$ENQ, + ssNoSynth_1_bNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_aw_buffer_firstValid - wire ssNoSynth_2_aw_buffer_firstValid$D_IN, - ssNoSynth_2_aw_buffer_firstValid$EN, - ssNoSynth_2_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_bNoSynth_buffer_firstValid + wire ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_bNoSynth_buffer_firstValid$EN, + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_w_buffer_ff - wire [73 : 0] ssNoSynth_2_w_buffer_ff$D_IN, ssNoSynth_2_w_buffer_ff$D_OUT; - wire ssNoSynth_2_w_buffer_ff$CLR, - ssNoSynth_2_w_buffer_ff$DEQ, - ssNoSynth_2_w_buffer_ff$EMPTY_N, - ssNoSynth_2_w_buffer_ff$ENQ, - ssNoSynth_2_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_ff$D_IN, + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_rNoSynth_buffer_ff$CLR, + ssNoSynth_1_rNoSynth_buffer_ff$DEQ, + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_rNoSynth_buffer_ff$ENQ, + ssNoSynth_1_rNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_w_buffer_firstValid - wire ssNoSynth_2_w_buffer_firstValid$D_IN, - ssNoSynth_2_w_buffer_firstValid$EN, - ssNoSynth_2_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_rNoSynth_buffer_firstValid + wire ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_rNoSynth_buffer_firstValid$EN, + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_1_wNoSynth_buffer_ff$D_IN, + ssNoSynth_1_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_wNoSynth_buffer_ff$CLR, + ssNoSynth_1_wNoSynth_buffer_ff$DEQ, + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_wNoSynth_buffer_ff$ENQ, + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_wNoSynth_buffer_firstValid + wire ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_wNoSynth_buffer_firstValid$EN, + ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_2_arNoSynth_buffer_ff$D_IN, + ssNoSynth_2_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_arNoSynth_buffer_ff$CLR, + ssNoSynth_2_arNoSynth_buffer_ff$DEQ, + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_arNoSynth_buffer_ff$ENQ, + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_arNoSynth_buffer_firstValid + wire ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_arNoSynth_buffer_firstValid$EN, + ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_2_awNoSynth_buffer_ff$D_IN, + ssNoSynth_2_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_awNoSynth_buffer_ff$CLR, + ssNoSynth_2_awNoSynth_buffer_ff$DEQ, + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_awNoSynth_buffer_ff$ENQ, + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_awNoSynth_buffer_firstValid + wire ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_awNoSynth_buffer_firstValid$EN, + ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_2_bNoSynth_buffer_ff$D_IN, + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_bNoSynth_buffer_ff$CLR, + ssNoSynth_2_bNoSynth_buffer_ff$DEQ, + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_bNoSynth_buffer_ff$ENQ, + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_bNoSynth_buffer_firstValid + wire ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_bNoSynth_buffer_firstValid$EN, + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_2_rNoSynth_buffer_ff$D_IN, + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_rNoSynth_buffer_ff$CLR, + ssNoSynth_2_rNoSynth_buffer_ff$DEQ, + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_rNoSynth_buffer_ff$ENQ, + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_rNoSynth_buffer_firstValid + wire ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_rNoSynth_buffer_firstValid$EN, + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_2_wNoSynth_buffer_ff$D_IN, + ssNoSynth_2_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_wNoSynth_buffer_ff$CLR, + ssNoSynth_2_wNoSynth_buffer_ff$DEQ, + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_wNoSynth_buffer_ff$ENQ, + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_wNoSynth_buffer_firstValid + wire ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_wNoSynth_buffer_firstValid$EN, + ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tagController_tmp_awreqff wire [97 : 0] tagController_tmp_awreqff$D_IN, @@ -1898,57 +2099,70 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_tagCon$RDY_memory_request_get, tagController_tmp_tagCon$RDY_memory_response_put; - // ports of submodule tmp0_b_buffer_ff - wire [5 : 0] tmp0_b_buffer_ff$D_IN, tmp0_b_buffer_ff$D_OUT; - wire tmp0_b_buffer_ff$CLR, - tmp0_b_buffer_ff$DEQ, - tmp0_b_buffer_ff$EMPTY_N, - tmp0_b_buffer_ff$ENQ, - tmp0_b_buffer_ff$FULL_N; + // ports of submodule tmp2_arNoSynth_buffer_ff + wire [97 : 0] tmp2_arNoSynth_buffer_ff$D_IN, tmp2_arNoSynth_buffer_ff$D_OUT; + wire tmp2_arNoSynth_buffer_ff$CLR, + tmp2_arNoSynth_buffer_ff$DEQ, + tmp2_arNoSynth_buffer_ff$EMPTY_N, + tmp2_arNoSynth_buffer_ff$ENQ, + tmp2_arNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp0_b_buffer_firstValid - wire tmp0_b_buffer_firstValid$D_IN, - tmp0_b_buffer_firstValid$EN, - tmp0_b_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_arNoSynth_buffer_firstValid + wire tmp2_arNoSynth_buffer_firstValid$D_IN, + tmp2_arNoSynth_buffer_firstValid$EN, + tmp2_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp0_r_buffer_ff - wire [71 : 0] tmp0_r_buffer_ff$D_IN, tmp0_r_buffer_ff$D_OUT; - wire tmp0_r_buffer_ff$CLR, - tmp0_r_buffer_ff$DEQ, - tmp0_r_buffer_ff$EMPTY_N, - tmp0_r_buffer_ff$ENQ, - tmp0_r_buffer_ff$FULL_N; + // ports of submodule tmp2_awNoSynth_buffer_ff + wire [97 : 0] tmp2_awNoSynth_buffer_ff$D_IN, tmp2_awNoSynth_buffer_ff$D_OUT; + wire tmp2_awNoSynth_buffer_ff$CLR, + tmp2_awNoSynth_buffer_ff$DEQ, + tmp2_awNoSynth_buffer_ff$EMPTY_N, + tmp2_awNoSynth_buffer_ff$ENQ, + tmp2_awNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp0_r_buffer_firstValid - wire tmp0_r_buffer_firstValid$D_IN, - tmp0_r_buffer_firstValid$EN, - tmp0_r_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_awNoSynth_buffer_firstValid + wire tmp2_awNoSynth_buffer_firstValid$D_IN, + tmp2_awNoSynth_buffer_firstValid$EN, + tmp2_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp2_b_buffer_ff - wire [6 : 0] tmp2_b_buffer_ff$D_IN, tmp2_b_buffer_ff$D_OUT; - wire tmp2_b_buffer_ff$CLR, - tmp2_b_buffer_ff$DEQ, - tmp2_b_buffer_ff$EMPTY_N, - tmp2_b_buffer_ff$ENQ, - tmp2_b_buffer_ff$FULL_N; + // ports of submodule tmp2_bNoSynth_buffer_ff + wire [6 : 0] tmp2_bNoSynth_buffer_ff$D_IN, tmp2_bNoSynth_buffer_ff$D_OUT; + wire tmp2_bNoSynth_buffer_ff$CLR, + tmp2_bNoSynth_buffer_ff$DEQ, + tmp2_bNoSynth_buffer_ff$EMPTY_N, + tmp2_bNoSynth_buffer_ff$ENQ, + tmp2_bNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp2_b_buffer_firstValid - wire tmp2_b_buffer_firstValid$D_IN, - tmp2_b_buffer_firstValid$EN, - tmp2_b_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_bNoSynth_buffer_firstValid + wire tmp2_bNoSynth_buffer_firstValid$D_IN, + tmp2_bNoSynth_buffer_firstValid$EN, + tmp2_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp2_r_buffer_ff - wire [72 : 0] tmp2_r_buffer_ff$D_IN, tmp2_r_buffer_ff$D_OUT; - wire tmp2_r_buffer_ff$CLR, - tmp2_r_buffer_ff$DEQ, - tmp2_r_buffer_ff$EMPTY_N, - tmp2_r_buffer_ff$ENQ, - tmp2_r_buffer_ff$FULL_N; + // ports of submodule tmp2_rNoSynth_buffer_ff + wire [72 : 0] tmp2_rNoSynth_buffer_ff$D_IN, tmp2_rNoSynth_buffer_ff$D_OUT; + wire tmp2_rNoSynth_buffer_ff$CLR, + tmp2_rNoSynth_buffer_ff$DEQ, + tmp2_rNoSynth_buffer_ff$EMPTY_N, + tmp2_rNoSynth_buffer_ff$ENQ, + tmp2_rNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp2_r_buffer_firstValid - wire tmp2_r_buffer_firstValid$D_IN, - tmp2_r_buffer_firstValid$EN, - tmp2_r_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_rNoSynth_buffer_firstValid + wire tmp2_rNoSynth_buffer_firstValid$D_IN, + tmp2_rNoSynth_buffer_firstValid$EN, + tmp2_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule tmp2_wNoSynth_buffer_ff + wire [73 : 0] tmp2_wNoSynth_buffer_ff$D_IN, tmp2_wNoSynth_buffer_ff$D_OUT; + wire tmp2_wNoSynth_buffer_ff$CLR, + tmp2_wNoSynth_buffer_ff$DEQ, + tmp2_wNoSynth_buffer_ff$EMPTY_N, + tmp2_wNoSynth_buffer_ff$ENQ, + tmp2_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule tmp2_wNoSynth_buffer_firstValid + wire tmp2_wNoSynth_buffer_firstValid$D_IN, + tmp2_wNoSynth_buffer_firstValid$EN, + tmp2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule uncached_mem_shim_arff wire [97 : 0] uncached_mem_shim_arff$D_IN, uncached_mem_shim_arff$D_OUT; @@ -1997,11 +2211,36 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_ClientServerResponse, CAN_FIRE_RL_ClientServerResponse_1, CAN_FIRE_RL_ClientServerResponse_2, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, CAN_FIRE_RL_arbitrate, CAN_FIRE_RL_arbitrate_1, CAN_FIRE_RL_arbitrate_2, @@ -2016,6 +2255,19 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_burst_7, CAN_FIRE_RL_burst_8, CAN_FIRE_RL_burst_9, + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut, + CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut, + CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_checkSinkReady, CAN_FIRE_RL_checkSinkReady_1, CAN_FIRE_RL_checkSinkReady_2, @@ -2042,67 +2294,132 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_ifcs_0_1_firstFlit_1, CAN_FIRE_RL_ifcs_0_1_followFlits, CAN_FIRE_RL_ifcs_0_1_followFlits_1, - CAN_FIRE_RL_ifcs_0_1_forwardRsp, CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_1_snk_doPut, + CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_0_drainFlits, CAN_FIRE_RL_ifcs_0_drainNoRouteResponse, CAN_FIRE_RL_ifcs_0_firstFlit, CAN_FIRE_RL_ifcs_0_firstFlit_1, CAN_FIRE_RL_ifcs_0_followFlits, CAN_FIRE_RL_ifcs_0_followFlits_1, - CAN_FIRE_RL_ifcs_0_forwardRsp, CAN_FIRE_RL_ifcs_0_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_snk_doPut, + CAN_FIRE_RL_ifcs_0_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_1_drainFlits, CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_1_firstFlit, CAN_FIRE_RL_ifcs_1_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_1_followFlits, CAN_FIRE_RL_ifcs_1_1_followFlits_1, - CAN_FIRE_RL_ifcs_1_1_forwardRsp, CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_1_snk_doPut, + CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_drainFlits, CAN_FIRE_RL_ifcs_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_firstFlit, CAN_FIRE_RL_ifcs_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_followFlits, CAN_FIRE_RL_ifcs_1_followFlits_1, - CAN_FIRE_RL_ifcs_1_forwardRsp, CAN_FIRE_RL_ifcs_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_snk_doPut, + CAN_FIRE_RL_ifcs_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_2_1_firstFlit, CAN_FIRE_RL_ifcs_2_1_followFlits, CAN_FIRE_RL_ifcs_2_firstFlit, CAN_FIRE_RL_ifcs_2_followFlits, + CAN_FIRE_RL_merged_0_awFlit, CAN_FIRE_RL_merged_0_genFirst, CAN_FIRE_RL_merged_0_genOther, + CAN_FIRE_RL_merged_0_passFlit, + CAN_FIRE_RL_merged_0_wFlit, + CAN_FIRE_RL_merged_1_awFlit, CAN_FIRE_RL_merged_1_genFirst, CAN_FIRE_RL_merged_1_genOther, + CAN_FIRE_RL_merged_1_passFlit, + CAN_FIRE_RL_merged_1_wFlit, CAN_FIRE_RL_mkConnectionGetPut, - CAN_FIRE_RL_msNoSynth_0_ar_forwardReady, - CAN_FIRE_RL_msNoSynth_0_aw_forwardReady, - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_0_b_dropFlit, - CAN_FIRE_RL_msNoSynth_0_b_forwardFlit, - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_0_r_dropFlit, - CAN_FIRE_RL_msNoSynth_0_r_forwardFlit, - CAN_FIRE_RL_msNoSynth_0_w_forwardReady, - CAN_FIRE_RL_msNoSynth_1_ar_forwardReady, - CAN_FIRE_RL_msNoSynth_1_aw_forwardReady, - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_1_b_dropFlit, - CAN_FIRE_RL_msNoSynth_1_b_forwardFlit, - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_1_r_dropFlit, - CAN_FIRE_RL_msNoSynth_1_r_forwardFlit, - CAN_FIRE_RL_msNoSynth_1_w_forwardReady, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, + CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut, + CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut, + CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, CAN_FIRE_RL_rl_dm_hart0_reset, CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_relay_external_interrupts, @@ -2116,6 +2433,38 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_sink_selected_7, CAN_FIRE_RL_sink_selected_8, CAN_FIRE_RL_sink_selected_9, + CAN_FIRE_RL_sinks_0_doPut, + CAN_FIRE_RL_sinks_0_warnDoPut, + CAN_FIRE_RL_sinks_1_0_doPut, + CAN_FIRE_RL_sinks_1_0_doPut_1, + CAN_FIRE_RL_sinks_1_0_warnDoPut, + CAN_FIRE_RL_sinks_1_0_warnDoPut_1, + CAN_FIRE_RL_sinks_1_1_0_doPut, + CAN_FIRE_RL_sinks_1_1_0_warnDoPut, + CAN_FIRE_RL_sinks_1_1_1_doPut, + CAN_FIRE_RL_sinks_1_1_1_warnDoPut, + CAN_FIRE_RL_sinks_1_1_doPut, + CAN_FIRE_RL_sinks_1_1_doPut_1, + CAN_FIRE_RL_sinks_1_1_warnDoPut, + CAN_FIRE_RL_sinks_1_1_warnDoPut_1, + CAN_FIRE_RL_sinks_1_2_doPut, + CAN_FIRE_RL_sinks_1_2_warnDoPut, + CAN_FIRE_RL_sinks_1_doPut, + CAN_FIRE_RL_sinks_1_warnDoPut, + CAN_FIRE_RL_sinks_2_doPut, + CAN_FIRE_RL_sinks_2_warnDoPut, + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop, + CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek, + CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop, + CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek, + CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, CAN_FIRE_RL_source_selected, CAN_FIRE_RL_source_selected_1, CAN_FIRE_RL_source_selected_2, @@ -2132,48 +2481,105 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_split_1_putOther, CAN_FIRE_RL_split_2_putFirst, CAN_FIRE_RL_split_2_putOther, - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_0_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_0_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_1_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_2_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, CAN_FIRE_RL_tagController_tmp_getCacheAW, CAN_FIRE_RL_tagController_tmp_passCacheRead, CAN_FIRE_RL_tagController_tmp_passCacheResponse, @@ -2207,77 +2613,87 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, - CAN_FIRE_RL_tmp0_ar_forwardReady, - CAN_FIRE_RL_tmp0_aw_forwardReady, - CAN_FIRE_RL_tmp0_b_buffer_dequeue, - CAN_FIRE_RL_tmp0_b_buffer_enqueue, - CAN_FIRE_RL_tmp0_b_dropFlit, - CAN_FIRE_RL_tmp0_b_forwardFlit, - CAN_FIRE_RL_tmp0_r_buffer_dequeue, - CAN_FIRE_RL_tmp0_r_buffer_enqueue, - CAN_FIRE_RL_tmp0_r_dropFlit, - CAN_FIRE_RL_tmp0_r_forwardFlit, - CAN_FIRE_RL_tmp0_w_forwardReady, - CAN_FIRE_RL_tmp2_ar_forwardReady, - CAN_FIRE_RL_tmp2_aw_forwardReady, - CAN_FIRE_RL_tmp2_b_buffer_dequeue, - CAN_FIRE_RL_tmp2_b_buffer_enqueue, - CAN_FIRE_RL_tmp2_b_dropFlit, - CAN_FIRE_RL_tmp2_b_forwardFlit, - CAN_FIRE_RL_tmp2_r_buffer_dequeue, - CAN_FIRE_RL_tmp2_r_buffer_enqueue, - CAN_FIRE_RL_tmp2_r_dropFlit, - CAN_FIRE_RL_tmp2_r_forwardFlit, - CAN_FIRE_RL_tmp2_w_forwardReady, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, - CAN_FIRE___me_check_156, - CAN_FIRE___me_check_157, - CAN_FIRE___me_check_158, - CAN_FIRE___me_check_160, - CAN_FIRE___me_check_163, - CAN_FIRE___me_check_164, - CAN_FIRE___me_check_165, - CAN_FIRE___me_check_167, - CAN_FIRE___me_check_170, - CAN_FIRE___me_check_172, - CAN_FIRE___me_check_174, - CAN_FIRE___me_check_182, - CAN_FIRE___me_check_184, - CAN_FIRE___me_check_186, - CAN_FIRE___me_check_195, - CAN_FIRE___me_check_197, - CAN_FIRE___me_check_199, - CAN_FIRE___me_check_201, - CAN_FIRE___me_check_203, - CAN_FIRE___me_check_204, - CAN_FIRE___me_check_205, - CAN_FIRE___me_check_207, - CAN_FIRE___me_check_210, - CAN_FIRE___me_check_211, - CAN_FIRE___me_check_212, - CAN_FIRE___me_check_214, - CAN_FIRE___me_check_217, - CAN_FIRE___me_check_219, - CAN_FIRE___me_check_221, - CAN_FIRE___me_check_229, - CAN_FIRE___me_check_231, - CAN_FIRE___me_check_233, - CAN_FIRE___me_check_242, - CAN_FIRE___me_check_244, - CAN_FIRE___me_check_246, - CAN_FIRE___me_check_248, + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_arNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_awNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit, + CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop, + CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek, + CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit, + CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop, + CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek, + CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_wNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, + CAN_FIRE___me_check_323, + CAN_FIRE___me_check_324, + CAN_FIRE___me_check_325, + CAN_FIRE___me_check_327, + CAN_FIRE___me_check_331, + CAN_FIRE___me_check_332, + CAN_FIRE___me_check_333, + CAN_FIRE___me_check_335, + CAN_FIRE___me_check_337, + CAN_FIRE___me_check_339, + CAN_FIRE___me_check_341, + CAN_FIRE___me_check_355, + CAN_FIRE___me_check_357, + CAN_FIRE___me_check_359, + CAN_FIRE___me_check_372, + CAN_FIRE___me_check_374, + CAN_FIRE___me_check_376, + CAN_FIRE___me_check_378, + CAN_FIRE___me_check_382, + CAN_FIRE___me_check_383, + CAN_FIRE___me_check_384, + CAN_FIRE___me_check_386, + CAN_FIRE___me_check_390, + CAN_FIRE___me_check_391, + CAN_FIRE___me_check_392, + CAN_FIRE___me_check_394, + CAN_FIRE___me_check_396, + CAN_FIRE___me_check_398, + CAN_FIRE___me_check_400, + CAN_FIRE___me_check_414, + CAN_FIRE___me_check_416, + CAN_FIRE___me_check_418, + CAN_FIRE___me_check_431, + CAN_FIRE___me_check_433, + CAN_FIRE___me_check_435, + CAN_FIRE___me_check_437, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -2318,11 +2734,36 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ClientServerResponse, WILL_FIRE_RL_ClientServerResponse_1, WILL_FIRE_RL_ClientServerResponse_2, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, WILL_FIRE_RL_arbitrate, WILL_FIRE_RL_arbitrate_1, WILL_FIRE_RL_arbitrate_2, @@ -2337,6 +2778,19 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_burst_7, WILL_FIRE_RL_burst_8, WILL_FIRE_RL_burst_9, + WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut, + WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut, + WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_checkSinkReady, WILL_FIRE_RL_checkSinkReady_1, WILL_FIRE_RL_checkSinkReady_2, @@ -2363,67 +2817,132 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ifcs_0_1_firstFlit_1, WILL_FIRE_RL_ifcs_0_1_followFlits, WILL_FIRE_RL_ifcs_0_1_followFlits_1, - WILL_FIRE_RL_ifcs_0_1_forwardRsp, WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_1_snk_doPut, + WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_0_drainFlits, WILL_FIRE_RL_ifcs_0_drainNoRouteResponse, WILL_FIRE_RL_ifcs_0_firstFlit, WILL_FIRE_RL_ifcs_0_firstFlit_1, WILL_FIRE_RL_ifcs_0_followFlits, WILL_FIRE_RL_ifcs_0_followFlits_1, - WILL_FIRE_RL_ifcs_0_forwardRsp, WILL_FIRE_RL_ifcs_0_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_snk_doPut, + WILL_FIRE_RL_ifcs_0_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_1_drainFlits, WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_1_firstFlit, WILL_FIRE_RL_ifcs_1_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_1_followFlits, WILL_FIRE_RL_ifcs_1_1_followFlits_1, - WILL_FIRE_RL_ifcs_1_1_forwardRsp, WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_1_snk_doPut, + WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_drainFlits, WILL_FIRE_RL_ifcs_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_firstFlit, WILL_FIRE_RL_ifcs_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_followFlits, WILL_FIRE_RL_ifcs_1_followFlits_1, - WILL_FIRE_RL_ifcs_1_forwardRsp, WILL_FIRE_RL_ifcs_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_snk_doPut, + WILL_FIRE_RL_ifcs_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_2_1_firstFlit, WILL_FIRE_RL_ifcs_2_1_followFlits, WILL_FIRE_RL_ifcs_2_firstFlit, WILL_FIRE_RL_ifcs_2_followFlits, + WILL_FIRE_RL_merged_0_awFlit, WILL_FIRE_RL_merged_0_genFirst, WILL_FIRE_RL_merged_0_genOther, + WILL_FIRE_RL_merged_0_passFlit, + WILL_FIRE_RL_merged_0_wFlit, + WILL_FIRE_RL_merged_1_awFlit, WILL_FIRE_RL_merged_1_genFirst, WILL_FIRE_RL_merged_1_genOther, + WILL_FIRE_RL_merged_1_passFlit, + WILL_FIRE_RL_merged_1_wFlit, WILL_FIRE_RL_mkConnectionGetPut, - WILL_FIRE_RL_msNoSynth_0_ar_forwardReady, - WILL_FIRE_RL_msNoSynth_0_aw_forwardReady, - WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_0_b_dropFlit, - WILL_FIRE_RL_msNoSynth_0_b_forwardFlit, - WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_0_r_dropFlit, - WILL_FIRE_RL_msNoSynth_0_r_forwardFlit, - WILL_FIRE_RL_msNoSynth_0_w_forwardReady, - WILL_FIRE_RL_msNoSynth_1_ar_forwardReady, - WILL_FIRE_RL_msNoSynth_1_aw_forwardReady, - WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_1_b_dropFlit, - WILL_FIRE_RL_msNoSynth_1_b_forwardFlit, - WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_1_r_dropFlit, - WILL_FIRE_RL_msNoSynth_1_r_forwardFlit, - WILL_FIRE_RL_msNoSynth_1_w_forwardReady, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, + WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, + WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut, + WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut, + WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, WILL_FIRE_RL_rl_dm_hart0_reset, WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_relay_external_interrupts, @@ -2437,6 +2956,38 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_sink_selected_7, WILL_FIRE_RL_sink_selected_8, WILL_FIRE_RL_sink_selected_9, + WILL_FIRE_RL_sinks_0_doPut, + WILL_FIRE_RL_sinks_0_warnDoPut, + WILL_FIRE_RL_sinks_1_0_doPut, + WILL_FIRE_RL_sinks_1_0_doPut_1, + WILL_FIRE_RL_sinks_1_0_warnDoPut, + WILL_FIRE_RL_sinks_1_0_warnDoPut_1, + WILL_FIRE_RL_sinks_1_1_0_doPut, + WILL_FIRE_RL_sinks_1_1_0_warnDoPut, + WILL_FIRE_RL_sinks_1_1_1_doPut, + WILL_FIRE_RL_sinks_1_1_1_warnDoPut, + WILL_FIRE_RL_sinks_1_1_doPut, + WILL_FIRE_RL_sinks_1_1_doPut_1, + WILL_FIRE_RL_sinks_1_1_warnDoPut, + WILL_FIRE_RL_sinks_1_1_warnDoPut_1, + WILL_FIRE_RL_sinks_1_2_doPut, + WILL_FIRE_RL_sinks_1_2_warnDoPut, + WILL_FIRE_RL_sinks_1_doPut, + WILL_FIRE_RL_sinks_1_warnDoPut, + WILL_FIRE_RL_sinks_2_doPut, + WILL_FIRE_RL_sinks_2_warnDoPut, + WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, + WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, + WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop, + WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek, + WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, + WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop, + WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek, + WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, + WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, WILL_FIRE_RL_source_selected, WILL_FIRE_RL_source_selected_1, WILL_FIRE_RL_source_selected_2, @@ -2453,48 +3004,105 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_split_1_putOther, WILL_FIRE_RL_split_2_putFirst, WILL_FIRE_RL_split_2_putOther, - WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_0_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_0_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_1_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_2_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, WILL_FIRE_RL_tagController_tmp_getCacheAW, WILL_FIRE_RL_tagController_tmp_passCacheRead, WILL_FIRE_RL_tagController_tmp_passCacheResponse, @@ -2528,77 +3136,87 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, - WILL_FIRE_RL_tmp0_ar_forwardReady, - WILL_FIRE_RL_tmp0_aw_forwardReady, - WILL_FIRE_RL_tmp0_b_buffer_dequeue, - WILL_FIRE_RL_tmp0_b_buffer_enqueue, - WILL_FIRE_RL_tmp0_b_dropFlit, - WILL_FIRE_RL_tmp0_b_forwardFlit, - WILL_FIRE_RL_tmp0_r_buffer_dequeue, - WILL_FIRE_RL_tmp0_r_buffer_enqueue, - WILL_FIRE_RL_tmp0_r_dropFlit, - WILL_FIRE_RL_tmp0_r_forwardFlit, - WILL_FIRE_RL_tmp0_w_forwardReady, - WILL_FIRE_RL_tmp2_ar_forwardReady, - WILL_FIRE_RL_tmp2_aw_forwardReady, - WILL_FIRE_RL_tmp2_b_buffer_dequeue, - WILL_FIRE_RL_tmp2_b_buffer_enqueue, - WILL_FIRE_RL_tmp2_b_dropFlit, - WILL_FIRE_RL_tmp2_b_forwardFlit, - WILL_FIRE_RL_tmp2_r_buffer_dequeue, - WILL_FIRE_RL_tmp2_r_buffer_enqueue, - WILL_FIRE_RL_tmp2_r_dropFlit, - WILL_FIRE_RL_tmp2_r_forwardFlit, - WILL_FIRE_RL_tmp2_w_forwardReady, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, - WILL_FIRE___me_check_156, - WILL_FIRE___me_check_157, - WILL_FIRE___me_check_158, - WILL_FIRE___me_check_160, - WILL_FIRE___me_check_163, - WILL_FIRE___me_check_164, - WILL_FIRE___me_check_165, - WILL_FIRE___me_check_167, - WILL_FIRE___me_check_170, - WILL_FIRE___me_check_172, - WILL_FIRE___me_check_174, - WILL_FIRE___me_check_182, - WILL_FIRE___me_check_184, - WILL_FIRE___me_check_186, - WILL_FIRE___me_check_195, - WILL_FIRE___me_check_197, - WILL_FIRE___me_check_199, - WILL_FIRE___me_check_201, - WILL_FIRE___me_check_203, - WILL_FIRE___me_check_204, - WILL_FIRE___me_check_205, - WILL_FIRE___me_check_207, - WILL_FIRE___me_check_210, - WILL_FIRE___me_check_211, - WILL_FIRE___me_check_212, - WILL_FIRE___me_check_214, - WILL_FIRE___me_check_217, - WILL_FIRE___me_check_219, - WILL_FIRE___me_check_221, - WILL_FIRE___me_check_229, - WILL_FIRE___me_check_231, - WILL_FIRE___me_check_233, - WILL_FIRE___me_check_242, - WILL_FIRE___me_check_244, - WILL_FIRE___me_check_246, - WILL_FIRE___me_check_248, + WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_arNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_awNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_bNoSynth_dropFlit, + WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop, + WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek, + WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_rNoSynth_dropFlit, + WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop, + WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek, + WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_wNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, + WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, + WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, + WILL_FIRE___me_check_323, + WILL_FIRE___me_check_324, + WILL_FIRE___me_check_325, + WILL_FIRE___me_check_327, + WILL_FIRE___me_check_331, + WILL_FIRE___me_check_332, + WILL_FIRE___me_check_333, + WILL_FIRE___me_check_335, + WILL_FIRE___me_check_337, + WILL_FIRE___me_check_339, + WILL_FIRE___me_check_341, + WILL_FIRE___me_check_355, + WILL_FIRE___me_check_357, + WILL_FIRE___me_check_359, + WILL_FIRE___me_check_372, + WILL_FIRE___me_check_374, + WILL_FIRE___me_check_376, + WILL_FIRE___me_check_378, + WILL_FIRE___me_check_382, + WILL_FIRE___me_check_383, + WILL_FIRE___me_check_384, + WILL_FIRE___me_check_386, + WILL_FIRE___me_check_390, + WILL_FIRE___me_check_391, + WILL_FIRE___me_check_392, + WILL_FIRE___me_check_394, + WILL_FIRE___me_check_396, + WILL_FIRE___me_check_398, + WILL_FIRE___me_check_400, + WILL_FIRE___me_check_414, + WILL_FIRE___me_check_416, + WILL_FIRE___me_check_418, + WILL_FIRE___me_check_431, + WILL_FIRE___me_check_433, + WILL_FIRE___me_check_435, + WILL_FIRE___me_check_437, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -2635,16 +3253,16 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_start; // inputs to muxes for submodule ports - reg [71 : 0] MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2, - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2; - reg [5 : 0] MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2, - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2; + reg [71 : 0] MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1, + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1; + reg [5 : 0] MUX_ifcs_0_snk_putWire$wset_1__VAL_1, + MUX_ifcs_1_snk_putWire$wset_1__VAL_1; wire [140 : 0] MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1, MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2; wire [76 : 0] MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1, MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2; - wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_1, - MUX_merged_1_flitLeft$write_1__VAL_1, + wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_2, + MUX_merged_1_flitLeft$write_1__VAL_2, MUX_rg_hart0_reset_delay$write_1__VAL_1, MUX_split_0_flitLeft$write_1__VAL_1, MUX_split_1_flitLeft$write_1__VAL_1, @@ -2720,99 +3338,105 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h22825; - reg [31 : 0] v__h22968; - reg [63 : 0] v__h50461; - reg [63 : 0] v__h49850; - reg [63 : 0] v__h54470; - reg [63 : 0] v__h53859; - reg [63 : 0] v__h84222; - reg [63 : 0] v__h83611; - reg [63 : 0] v__h87115; - reg [63 : 0] v__h86504; - reg [63 : 0] v__h65165; - reg [63 : 0] v__h64784; - reg [63 : 0] v__h67235; - reg [63 : 0] v__h66854; - reg [63 : 0] v__h69134; - reg [63 : 0] v__h68753; - reg [63 : 0] v__h96395; - reg [63 : 0] v__h96014; - reg [63 : 0] v__h98886; - reg [63 : 0] v__h98505; - reg [63 : 0] v__h101196; - reg [63 : 0] v__h100815; - reg [31 : 0] v__h103640; - reg [31 : 0] v__h22819; - reg [31 : 0] v__h22962; - reg [31 : 0] v__h103634; + reg [31 : 0] v__h27371; + reg [31 : 0] v__h27514; + reg [63 : 0] v__h71925; + reg [63 : 0] v__h71314; + reg [63 : 0] v__h75934; + reg [63 : 0] v__h75323; + reg [63 : 0] v__h87100; + reg [63 : 0] v__h86719; + reg [63 : 0] v__h89170; + reg [63 : 0] v__h88789; + reg [63 : 0] v__h91069; + reg [63 : 0] v__h90688; + reg [63 : 0] v__h107698; + reg [63 : 0] v__h107087; + reg [63 : 0] v__h110591; + reg [63 : 0] v__h109980; + reg [63 : 0] v__h120378; + reg [63 : 0] v__h119997; + reg [63 : 0] v__h122869; + reg [63 : 0] v__h122488; + reg [63 : 0] v__h125179; + reg [63 : 0] v__h124798; + reg [31 : 0] v__h128907; + reg [31 : 0] v__h27365; + reg [31 : 0] v__h27508; + reg [31 : 0] v__h128901; // synopsys translate_on // remaining internal signals + wire [171 : 0] IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645; wire [98 : 0] tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4, tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2; wire [72 : 0] tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3, uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1; - wire [63 : 0] araddr__h15540, - aw_awaddr__h10808, - tmp__h10591, - tmp__h8366, - v_araddr__h15557, - x__h37445, - x__h37480, - x__h40162, - x__h40187, - x__h71737, - x__h71762, - x__h74126, - x__h74151, - x__h8207, - x_rdata__h25045; - wire [39 : 0] x__h10840; - wire [8 : 0] x_port1__read__h72781, x_port1__read__h75154; - wire [7 : 0] arlen__h15541, v_arlen__h15558; - wire [5 : 0] v_arid__h15556; - wire [4 : 0] a_awid__h38523, - a_awid__h41194, - fatReq_arid__h72223, - fatReq_arid__h74597; - wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245, - arcache__h15545, - x__h10883, - x__h12617, - x__h12629, - x__h12641, - x__h12653, - x__h12665, - x__h12677, - x__h12689, - x__h14213, - x__h15621, - x_rid__h25044, - y__h12618, - y__h12630, - y__h12642, - y__h12654, - y__h12666, - y__h12678, - y__h12690; - wire [2 : 0] aw_awsize_val__h12547, v_arsize_val__h15603; - wire [1 : 0] IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207, - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211, - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863, - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22, - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17, - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12, - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7, + wire [63 : 0] addr__h93758, + addr__h96375, + araddr__h15343, + aw_awaddr__h10611, + tmp__h10394, + tmp__h8169, + v_araddr__h15360, + x__h56232, + x__h56267, + x__h59744, + x__h59769, + x__h8010, + x__h93834, + x__h93859, + x__h96451, + x__h96476; + wire [39 : 0] x__h10643; + wire [8 : 0] x__h95023, x__h97622; + wire [7 : 0] arlen__h15344, v_arlen__h15361, x__h94920, x__h97519; + wire [5 : 0] v_arid__h15359; + wire [4 : 0] fatReq_arid__h94342, + fatReq_arid__h96944, + x__h100325, + x__h62625, + x__h63516, + x__h64407, + x__h98415, + x__h99370; + wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224, + arcache__h15348, + x__h10686, + x__h12420, + x__h12432, + x__h12444, + x__h12456, + x__h12468, + x__h12480, + x__h12492, + x__h14016, + x__h15424, + y__h12421, + y__h12433, + y__h12445, + y__h12457, + y__h12469, + y__h12481, + y__h12493; + wire [2 : 0] aw_awsize_val__h12350, v_arsize_val__h15406; + wire [1 : 0] IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531, + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535, + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331, + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22, + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12, + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17, + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7, SEXT_arbiter_1_1_firstHot__q19, SEXT_arbiter_1_1_lastSelect_1__q21, SEXT_arbiter_1_1_lastSelect__q20, @@ -2823,146 +3447,146 @@ module mkCoreW(RST_N_dm_power_on_reset, SEXT_arbiter_1_lastSelect__q10, SEXT_arbiter_firstHot__q5, SEXT_arbiter_lastSelect__q6, - SEXT_x2747__q18, - SEXT_x3466__q13, - SEXT_x3500__q14, - SEXT_x4692__q23, - SEXT_x4726__q24, - SEXT_x8980__q8; - wire IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098, - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455, - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114, - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362, - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150, - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729, - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507, - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302, - IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425, - IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426, - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427, - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331, - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325, - SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319, - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138, - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698, - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692, - SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134, - SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686, - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495, - SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491, - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932, - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937, - debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930, - debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935, - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845, - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850, - proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843, - proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848, - reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669, - reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302, - split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093, - split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122, - split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151, - state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193, - state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233, - state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400, - state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436, - state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472, - state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761, - state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794, - state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828, - state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556, - state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600, - x__h48453, - x__h48556, - x__h48921, - x__h48980, - x__h49062, - x__h62645, - x__h62647, - x__h62796, - x__h62798, - x__h62932, - x__h62934, - x__h63404, - x__h63406, - x__h63466, - x__h63500, - x__h63592, - x__h63594, - x__h63773, - x__h63775, - x__h82220, - x__h82323, - x__h82688, - x__h82747, - x__h82829, - x__h93871, - x__h93873, - x__h94022, - x__h94024, - x__h94158, - x__h94160, - x__h94630, - x__h94632, - x__h94692, - x__h94726, - x__h94818, - x__h94820, - x__h94999, - x__h95001, - y__h48454, - y__h48557, - y__h48922, - y__h49063, - y__h62646, - y__h62648, - y__h62797, - y__h62799, - y__h62933, - y__h62935, - y__h63405, - y__h63407, - y__h63593, - y__h63595, - y__h63774, - y__h63776, - y__h82221, - y__h82324, - y__h82689, - y__h82830, - y__h93872, - y__h93874, - y__h94023, - y__h94025, - y__h94159, - y__h94161, - y__h94631, - y__h94633, - y__h94819, - y__h94821, - y__h95000, - y__h95002; + SEXT_x0450__q8, + SEXT_x06223__q18, + SEXT_x18675__q23, + SEXT_x18709__q24, + SEXT_x5401__q13, + SEXT_x5435__q14; + wire IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513, + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812, + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529, + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090, + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565, + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569, + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864, + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868, + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556, + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561, + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650, + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764, + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773, + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782, + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750, + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744, + SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738, + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059, + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553, + SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047, + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053, + SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549, + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852, + SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848, + reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030, + reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721, + split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409, + split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438, + split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467, + state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122, + state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155, + state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189, + state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819, + state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855, + state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891, + state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608, + state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648, + state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913, + state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957, + x__h105696, + x__h105799, + x__h106164, + x__h106223, + x__h106305, + x__h117854, + x__h117856, + x__h118005, + x__h118007, + x__h118141, + x__h118143, + x__h118613, + x__h118615, + x__h118675, + x__h118709, + x__h118801, + x__h118803, + x__h118982, + x__h118984, + x__h69923, + x__h70026, + x__h70391, + x__h70450, + x__h70532, + x__h84580, + x__h84582, + x__h84731, + x__h84733, + x__h84867, + x__h84869, + x__h85339, + x__h85341, + x__h85401, + x__h85435, + x__h85527, + x__h85529, + x__h85708, + x__h85710, + y__h105697, + y__h105800, + y__h106165, + y__h106306, + y__h117855, + y__h117857, + y__h118006, + y__h118008, + y__h118142, + y__h118144, + y__h118614, + y__h118616, + y__h118802, + y__h118804, + y__h118983, + y__h118985, + y__h69924, + y__h70027, + y__h70392, + y__h70533, + y__h84581, + y__h84583, + y__h84732, + y__h84734, + y__h84868, + y__h84870, + y__h85340, + y__h85342, + y__h85528, + y__h85530, + y__h85709, + y__h85711; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; @@ -3044,7 +3668,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_imem_master_b_bflit assign CAN_FIRE_cpu_imem_master_b_bflit = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_b_bflit = cpu_imem_master_bvalid ; + assign WILL_FIRE_cpu_imem_master_b_bflit = 1'd1 ; // value method cpu_imem_master_b_bready assign cpu_imem_master_bready = !tagController_tmp_shimMaster_bff_rv[8] ; @@ -3099,50 +3723,50 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_imem_master_r_rflit assign CAN_FIRE_cpu_imem_master_r_rflit = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_r_rflit = cpu_imem_master_rvalid ; + assign WILL_FIRE_cpu_imem_master_r_rflit = 1'd1 ; // value method cpu_imem_master_r_rready assign cpu_imem_master_rready = !tagController_tmp_shimMaster_rff_rv[73] ; // value method cpu_dmem_master_aw_awid assign cpu_dmem_master_awid = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[98:93] ; + uncached_mem_master_awSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_aw_awaddr assign cpu_dmem_master_awaddr = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[92:29] ; + uncached_mem_master_awSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_aw_awlen assign cpu_dmem_master_awlen = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[28:21] ; + uncached_mem_master_awSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_aw_awsize assign cpu_dmem_master_awsize = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[20:18] ; + uncached_mem_master_awSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_aw_awburst assign cpu_dmem_master_awburst = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[17:16] ; + uncached_mem_master_awSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_aw_awlock assign cpu_dmem_master_awlock = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[15] ; + uncached_mem_master_awSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_aw_awcache assign cpu_dmem_master_awcache = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[14:11] ; + uncached_mem_master_awSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_aw_awprot assign cpu_dmem_master_awprot = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[10:8] ; + uncached_mem_master_awSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_aw_awqos assign cpu_dmem_master_awqos = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[7:4] ; + uncached_mem_master_awSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_aw_awregion assign cpu_dmem_master_awregion = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[3:0] ; + uncached_mem_master_awSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_aw_awvalid assign cpu_dmem_master_awvalid = uncached_mem_shim_awff$EMPTY_N ; @@ -3172,50 +3796,50 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_dmem_master_b_bflit assign CAN_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_b_bflit = cpu_dmem_master_bvalid ; + assign WILL_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; // value method cpu_dmem_master_b_bready assign cpu_dmem_master_bready = uncached_mem_shim_bff$FULL_N ; // value method cpu_dmem_master_ar_arid assign cpu_dmem_master_arid = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[98:93] ; + uncached_mem_master_arSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_ar_araddr assign cpu_dmem_master_araddr = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[92:29] ; + uncached_mem_master_arSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_ar_arlen assign cpu_dmem_master_arlen = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[28:21] ; + uncached_mem_master_arSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_ar_arsize assign cpu_dmem_master_arsize = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[20:18] ; + uncached_mem_master_arSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_ar_arburst assign cpu_dmem_master_arburst = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[17:16] ; + uncached_mem_master_arSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_ar_arlock assign cpu_dmem_master_arlock = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[15] ; + uncached_mem_master_arSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_ar_arcache assign cpu_dmem_master_arcache = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[14:11] ; + uncached_mem_master_arSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_ar_arprot assign cpu_dmem_master_arprot = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[10:8] ; + uncached_mem_master_arSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_ar_arqos assign cpu_dmem_master_arqos = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[7:4] ; + uncached_mem_master_arSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_ar_arregion assign cpu_dmem_master_arregion = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[3:0] ; + uncached_mem_master_arSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_ar_arvalid assign cpu_dmem_master_arvalid = uncached_mem_shim_arff$EMPTY_N ; @@ -3226,7 +3850,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_dmem_master_r_rflit assign CAN_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_r_rflit = cpu_dmem_master_rvalid ; + assign WILL_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; // value method cpu_dmem_master_r_rready assign cpu_dmem_master_rready = uncached_mem_shim_rff$FULL_N ; @@ -3348,11 +3972,13 @@ module mkCoreW(RST_N_dm_power_on_reset, .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), .master_bresp(debug_module$master_bresp), + .master_bvalid(debug_module$master_bvalid), .master_rdata(debug_module$master_rdata), .master_rid(debug_module$master_rid), .master_rlast(debug_module$master_rlast), .master_rresp(debug_module$master_rresp), .master_ruser(debug_module$master_ruser), + .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), @@ -3371,8 +3997,6 @@ module mkCoreW(RST_N_dm_power_on_reset, .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), - .master_bvalid(debug_module$master_bvalid), - .master_rvalid(debug_module$master_rvalid), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), @@ -3705,79 +4329,239 @@ module mkCoreW(RST_N_dm_power_on_reset, .FULL_N(ifcs_2_rspBack$FULL_N), .EMPTY_N(ifcs_2_rspBack$EMPTY_N)); - // submodule msNoSynth_0_b_buffer_ff - FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_0_b_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_0_b_buffer_ff$D_IN), - .ENQ(msNoSynth_0_b_buffer_ff$ENQ), - .DEQ(msNoSynth_0_b_buffer_ff$DEQ), - .CLR(msNoSynth_0_b_buffer_ff$CLR), - .D_OUT(msNoSynth_0_b_buffer_ff$D_OUT), - .FULL_N(msNoSynth_0_b_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_0_b_buffer_ff$EMPTY_N)); + // submodule merged_0_awff + FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_0_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_0_awff$D_IN), + .ENQ(merged_0_awff$ENQ), + .DEQ(merged_0_awff$DEQ), + .CLR(merged_0_awff$CLR), + .D_OUT(merged_0_awff$D_OUT), + .FULL_N(merged_0_awff$FULL_N), + .EMPTY_N(merged_0_awff$EMPTY_N)); - // submodule msNoSynth_0_b_buffer_firstValid + // submodule merged_0_wff + FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_0_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_0_wff$D_IN), + .ENQ(merged_0_wff$ENQ), + .DEQ(merged_0_wff$DEQ), + .CLR(merged_0_wff$CLR), + .D_OUT(merged_0_wff$D_OUT), + .FULL_N(merged_0_wff$FULL_N), + .EMPTY_N(merged_0_wff$EMPTY_N)); + + // submodule merged_1_awff + FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_1_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_1_awff$D_IN), + .ENQ(merged_1_awff$ENQ), + .DEQ(merged_1_awff$DEQ), + .CLR(merged_1_awff$CLR), + .D_OUT(merged_1_awff$D_OUT), + .FULL_N(merged_1_awff$FULL_N), + .EMPTY_N(merged_1_awff$EMPTY_N)); + + // submodule merged_1_wff + FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_1_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_1_wff$D_IN), + .ENQ(merged_1_wff$ENQ), + .DEQ(merged_1_wff$DEQ), + .CLR(merged_1_wff$CLR), + .D_OUT(merged_1_wff$D_OUT), + .FULL_N(merged_1_wff$FULL_N), + .EMPTY_N(merged_1_wff$EMPTY_N)); + + // submodule msNoSynth_0_arNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_arNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_arNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_arNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_arNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_arNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_0_b_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_0_b_buffer_firstValid$D_IN), - .EN(msNoSynth_0_b_buffer_firstValid$EN), - .Q_OUT(msNoSynth_0_b_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_arNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_arNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_0_r_buffer_ff + // submodule msNoSynth_0_awNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_awNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_awNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_awNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_awNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_awNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_awNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_awNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_bNoSynth_buffer_ff + FIFO1 #(.width(32'd6), + .guarded(32'd0)) msNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_bNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_bNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_bNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_bNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_bNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_bNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_bNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), - .guarded(32'd0)) msNoSynth_0_r_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_0_r_buffer_ff$D_IN), - .ENQ(msNoSynth_0_r_buffer_ff$ENQ), - .DEQ(msNoSynth_0_r_buffer_ff$DEQ), - .CLR(msNoSynth_0_r_buffer_ff$CLR), - .D_OUT(msNoSynth_0_r_buffer_ff$D_OUT), - .FULL_N(msNoSynth_0_r_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_0_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) msNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_rNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_rNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_rNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_rNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_rNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_0_r_buffer_firstValid + // submodule msNoSynth_0_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_0_r_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_0_r_buffer_firstValid$D_IN), - .EN(msNoSynth_0_r_buffer_firstValid$EN), - .Q_OUT(msNoSynth_0_r_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_rNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_rNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_1_b_buffer_ff - FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_1_b_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_1_b_buffer_ff$D_IN), - .ENQ(msNoSynth_1_b_buffer_ff$ENQ), - .DEQ(msNoSynth_1_b_buffer_ff$DEQ), - .CLR(msNoSynth_1_b_buffer_ff$CLR), - .D_OUT(msNoSynth_1_b_buffer_ff$D_OUT), - .FULL_N(msNoSynth_1_b_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_1_b_buffer_ff$EMPTY_N)); + // submodule msNoSynth_0_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) msNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_wNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_wNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_wNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_wNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_wNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_1_b_buffer_firstValid + // submodule msNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_1_b_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_1_b_buffer_firstValid$D_IN), - .EN(msNoSynth_1_b_buffer_firstValid$EN), - .Q_OUT(msNoSynth_1_b_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_wNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_wNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_1_r_buffer_ff + // submodule msNoSynth_1_arNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_arNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_arNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_arNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_arNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_arNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_arNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_arNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_arNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_awNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_awNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_awNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_awNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_awNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_awNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_awNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_awNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_bNoSynth_buffer_ff + FIFO1 #(.width(32'd6), + .guarded(32'd0)) msNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_bNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_bNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_bNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_bNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_bNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_bNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_bNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), - .guarded(32'd0)) msNoSynth_1_r_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_1_r_buffer_ff$D_IN), - .ENQ(msNoSynth_1_r_buffer_ff$ENQ), - .DEQ(msNoSynth_1_r_buffer_ff$DEQ), - .CLR(msNoSynth_1_r_buffer_ff$CLR), - .D_OUT(msNoSynth_1_r_buffer_ff$D_OUT), - .FULL_N(msNoSynth_1_r_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_1_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) msNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_rNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_rNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_rNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_rNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_rNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_1_r_buffer_firstValid + // submodule msNoSynth_1_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_1_r_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_1_r_buffer_firstValid$D_IN), - .EN(msNoSynth_1_r_buffer_firstValid$EN), - .Q_OUT(msNoSynth_1_r_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_rNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_rNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) msNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_wNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_wNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_wNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_wNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_wNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_wNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_wNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_wNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), @@ -3792,6 +4576,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), + .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), @@ -3802,12 +4587,14 @@ module mkCoreW(RST_N_dm_power_on_reset, .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), + .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wuser(plic$axi4_slave_wuser), + .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), @@ -3832,9 +4619,6 @@ module mkCoreW(RST_N_dm_power_on_reset, .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(), @@ -3868,6 +4652,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .debug_module_mem_server_arqos(proc$debug_module_mem_server_arqos), .debug_module_mem_server_arregion(proc$debug_module_mem_server_arregion), .debug_module_mem_server_arsize(proc$debug_module_mem_server_arsize), + .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), .debug_module_mem_server_awaddr(proc$debug_module_mem_server_awaddr), .debug_module_mem_server_awburst(proc$debug_module_mem_server_awburst), .debug_module_mem_server_awcache(proc$debug_module_mem_server_awcache), @@ -3878,12 +4663,14 @@ module mkCoreW(RST_N_dm_power_on_reset, .debug_module_mem_server_awqos(proc$debug_module_mem_server_awqos), .debug_module_mem_server_awregion(proc$debug_module_mem_server_awregion), .debug_module_mem_server_awsize(proc$debug_module_mem_server_awsize), + .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wuser(proc$debug_module_mem_server_wuser), + .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), .hart0_csr_mem_server_request_put(proc$hart0_csr_mem_server_request_put), .hart0_fpr_mem_server_request_put(proc$hart0_fpr_mem_server_request_put), .hart0_gpr_mem_server_request_put(proc$hart0_gpr_mem_server_request_put), @@ -3894,22 +4681,16 @@ module mkCoreW(RST_N_dm_power_on_reset, .master0_awready(proc$master0_awready), .master0_bid(proc$master0_bid), .master0_bresp(proc$master0_bresp), + .master0_bvalid(proc$master0_bvalid), .master0_rdata(proc$master0_rdata), .master0_rid(proc$master0_rid), .master0_rlast(proc$master0_rlast), .master0_rresp(proc$master0_rresp), .master0_ruser(proc$master0_ruser), + .master0_rvalid(proc$master0_rvalid), .master0_wready(proc$master0_wready), - .master1_arready(proc$master1_arready), - .master1_awready(proc$master1_awready), - .master1_bid(proc$master1_bid), - .master1_bresp(proc$master1_bresp), - .master1_rdata(proc$master1_rdata), - .master1_rid(proc$master1_rid), - .master1_rlast(proc$master1_rlast), - .master1_rresp(proc$master1_rresp), - .master1_ruser(proc$master1_ruser), - .master1_wready(proc$master1_wready), + .master1_b_put_val(proc$master1_b_put_val), + .master1_r_put_val(proc$master1_r_put_val), .non_maskable_interrupt_req_set_not_clear(proc$non_maskable_interrupt_req_set_not_clear), .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), @@ -3918,14 +4699,12 @@ module mkCoreW(RST_N_dm_power_on_reset, .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), - .master0_bvalid(proc$master0_bvalid), - .master0_rvalid(proc$master0_rvalid), - .master1_bvalid(proc$master1_bvalid), - .master1_rvalid(proc$master1_rvalid), + .EN_master1_aw_drop(proc$EN_master1_aw_drop), + .EN_master1_w_drop(proc$EN_master1_w_drop), + .EN_master1_b_put(proc$EN_master1_b_put), + .EN_master1_ar_drop(proc$EN_master1_ar_drop), + .EN_master1_r_put(proc$EN_master1_r_put), .EN_set_verbosity(proc$EN_set_verbosity), - .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), - .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), - .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), .EN_hart0_run_halt_server_response_get(proc$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(proc$EN_hart0_gpr_mem_server_request_put), @@ -3965,35 +4744,22 @@ module mkCoreW(RST_N_dm_power_on_reset, .master0_arregion(proc$master0_arregion), .master0_arvalid(proc$master0_arvalid), .master0_rready(proc$master0_rready), - .master1_awid(proc$master1_awid), - .master1_awaddr(proc$master1_awaddr), - .master1_awlen(proc$master1_awlen), - .master1_awsize(proc$master1_awsize), - .master1_awburst(proc$master1_awburst), - .master1_awlock(proc$master1_awlock), - .master1_awcache(proc$master1_awcache), - .master1_awprot(proc$master1_awprot), - .master1_awqos(proc$master1_awqos), - .master1_awregion(proc$master1_awregion), - .master1_awvalid(proc$master1_awvalid), - .master1_wdata(proc$master1_wdata), - .master1_wstrb(proc$master1_wstrb), - .master1_wlast(proc$master1_wlast), - .master1_wuser(), - .master1_wvalid(proc$master1_wvalid), - .master1_bready(proc$master1_bready), - .master1_arid(proc$master1_arid), - .master1_araddr(proc$master1_araddr), - .master1_arlen(proc$master1_arlen), - .master1_arsize(proc$master1_arsize), - .master1_arburst(proc$master1_arburst), - .master1_arlock(proc$master1_arlock), - .master1_arcache(proc$master1_arcache), - .master1_arprot(proc$master1_arprot), - .master1_arqos(proc$master1_arqos), - .master1_arregion(proc$master1_arregion), - .master1_arvalid(proc$master1_arvalid), - .master1_rready(proc$master1_rready), + .master1_aw_canPeek(proc$master1_aw_canPeek), + .master1_aw_peek(proc$master1_aw_peek), + .RDY_master1_aw_peek(proc$RDY_master1_aw_peek), + .RDY_master1_aw_drop(proc$RDY_master1_aw_drop), + .master1_w_canPeek(proc$master1_w_canPeek), + .master1_w_peek(proc$master1_w_peek), + .RDY_master1_w_peek(proc$RDY_master1_w_peek), + .RDY_master1_w_drop(proc$RDY_master1_w_drop), + .master1_b_canPut(proc$master1_b_canPut), + .RDY_master1_b_put(proc$RDY_master1_b_put), + .master1_ar_canPeek(proc$master1_ar_canPeek), + .master1_ar_peek(proc$master1_ar_peek), + .RDY_master1_ar_peek(proc$RDY_master1_ar_peek), + .RDY_master1_ar_drop(proc$RDY_master1_ar_drop), + .master1_r_canPut(proc$master1_r_canPut), + .RDY_master1_r_put(proc$RDY_master1_r_put), .RDY_set_verbosity(), .debug_module_mem_server_awready(proc$debug_module_mem_server_awready), .debug_module_mem_server_wready(proc$debug_module_mem_server_wready), @@ -4045,176 +4811,290 @@ module mkCoreW(RST_N_dm_power_on_reset, .m_mtvec_reset_value(), .m_nmivec_reset_value()); - // submodule ssNoSynth_0_ar_buffer_ff + // submodule ssNoSynth_0_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_0_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_0_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_ar_buffer_firstValid + // submodule ssNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_0_aw_buffer_ff + // submodule ssNoSynth_0_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_0_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_0_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_aw_buffer_firstValid + // submodule ssNoSynth_0_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_0_w_buffer_ff + // submodule ssNoSynth_0_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_0_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_w_buffer_ff$DEQ), - .CLR(ssNoSynth_0_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_w_buffer_firstValid + // submodule ssNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_ar_buffer_ff + // submodule ssNoSynth_1_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_1_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_1_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_ar_buffer_firstValid + // submodule ssNoSynth_1_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_aw_buffer_ff + // submodule ssNoSynth_1_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_1_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_1_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_aw_buffer_firstValid + // submodule ssNoSynth_1_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_w_buffer_ff + // submodule ssNoSynth_1_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_1_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_w_buffer_ff$DEQ), - .CLR(ssNoSynth_1_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_w_buffer_firstValid + // submodule ssNoSynth_1_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_ar_buffer_ff + // submodule ssNoSynth_2_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_2_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_2_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_ar_buffer_firstValid + // submodule ssNoSynth_2_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_aw_buffer_ff + // submodule ssNoSynth_2_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_2_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_2_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_aw_buffer_firstValid + // submodule ssNoSynth_2_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_w_buffer_ff + // submodule ssNoSynth_2_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_2_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_2_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_2_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_w_buffer_ff$DEQ), - .CLR(ssNoSynth_2_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_w_buffer_firstValid + // submodule ssNoSynth_2_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule tagController_tmp_awreqff FIFO2 #(.width(32'd98), @@ -4259,77 +5139,100 @@ module mkCoreW(RST_N_dm_power_on_reset, .memory_response_canPut(), .RDY_memory_response_put(tagController_tmp_tagCon$RDY_memory_response_put)); - // submodule tmp0_b_buffer_ff - FIFO1 #(.width(32'd6), - .guarded(32'd0)) tmp0_b_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp0_b_buffer_ff$D_IN), - .ENQ(tmp0_b_buffer_ff$ENQ), - .DEQ(tmp0_b_buffer_ff$DEQ), - .CLR(tmp0_b_buffer_ff$CLR), - .D_OUT(tmp0_b_buffer_ff$D_OUT), - .FULL_N(tmp0_b_buffer_ff$FULL_N), - .EMPTY_N(tmp0_b_buffer_ff$EMPTY_N)); + // submodule tmp2_arNoSynth_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) tmp2_arNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_arNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_arNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_arNoSynth_buffer_ff$DEQ), + .CLR(tmp2_arNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_arNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_arNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp0_b_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp0_b_buffer_firstValid(.CLK(CLK), - .D_IN(tmp0_b_buffer_firstValid$D_IN), - .EN(tmp0_b_buffer_firstValid$EN), - .Q_OUT(tmp0_b_buffer_firstValid$Q_OUT)); + // submodule tmp2_arNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_arNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_arNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp0_r_buffer_ff - FIFO1 #(.width(32'd72), - .guarded(32'd0)) tmp0_r_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp0_r_buffer_ff$D_IN), - .ENQ(tmp0_r_buffer_ff$ENQ), - .DEQ(tmp0_r_buffer_ff$DEQ), - .CLR(tmp0_r_buffer_ff$CLR), - .D_OUT(tmp0_r_buffer_ff$D_OUT), - .FULL_N(tmp0_r_buffer_ff$FULL_N), - .EMPTY_N(tmp0_r_buffer_ff$EMPTY_N)); + // submodule tmp2_awNoSynth_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) tmp2_awNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_awNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_awNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_awNoSynth_buffer_ff$DEQ), + .CLR(tmp2_awNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_awNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_awNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp0_r_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp0_r_buffer_firstValid(.CLK(CLK), - .D_IN(tmp0_r_buffer_firstValid$D_IN), - .EN(tmp0_r_buffer_firstValid$EN), - .Q_OUT(tmp0_r_buffer_firstValid$Q_OUT)); + // submodule tmp2_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_awNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_awNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp2_b_buffer_ff + // submodule tmp2_bNoSynth_buffer_ff FIFO1 #(.width(32'd7), - .guarded(32'd0)) tmp2_b_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp2_b_buffer_ff$D_IN), - .ENQ(tmp2_b_buffer_ff$ENQ), - .DEQ(tmp2_b_buffer_ff$DEQ), - .CLR(tmp2_b_buffer_ff$CLR), - .D_OUT(tmp2_b_buffer_ff$D_OUT), - .FULL_N(tmp2_b_buffer_ff$FULL_N), - .EMPTY_N(tmp2_b_buffer_ff$EMPTY_N)); + .guarded(32'd0)) tmp2_bNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_bNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_bNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_bNoSynth_buffer_ff$DEQ), + .CLR(tmp2_bNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_bNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_bNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp2_b_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp2_b_buffer_firstValid(.CLK(CLK), - .D_IN(tmp2_b_buffer_firstValid$D_IN), - .EN(tmp2_b_buffer_firstValid$EN), - .Q_OUT(tmp2_b_buffer_firstValid$Q_OUT)); + // submodule tmp2_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_bNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_bNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_bNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp2_r_buffer_ff + // submodule tmp2_rNoSynth_buffer_ff FIFO1 #(.width(32'd73), - .guarded(32'd0)) tmp2_r_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp2_r_buffer_ff$D_IN), - .ENQ(tmp2_r_buffer_ff$ENQ), - .DEQ(tmp2_r_buffer_ff$DEQ), - .CLR(tmp2_r_buffer_ff$CLR), - .D_OUT(tmp2_r_buffer_ff$D_OUT), - .FULL_N(tmp2_r_buffer_ff$FULL_N), - .EMPTY_N(tmp2_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) tmp2_rNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_rNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_rNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_rNoSynth_buffer_ff$DEQ), + .CLR(tmp2_rNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_rNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_rNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp2_r_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp2_r_buffer_firstValid(.CLK(CLK), - .D_IN(tmp2_r_buffer_firstValid$D_IN), - .EN(tmp2_r_buffer_firstValid$EN), - .Q_OUT(tmp2_r_buffer_firstValid$Q_OUT)); + // submodule tmp2_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_rNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_rNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule tmp2_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) tmp2_wNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_wNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_wNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_wNoSynth_buffer_ff$DEQ), + .CLR(tmp2_wNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_wNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_wNoSynth_buffer_ff$EMPTY_N)); + + // submodule tmp2_wNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_wNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_wNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule uncached_mem_shim_arff FIFO2 #(.width(32'd98), @@ -4478,7 +5381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst assign CAN_FIRE_RL_burst = ifcs_0_innerReq$EMPTY_N && ifcs_0_innerRoute$EMPTY_N && - state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556 ; + state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 ; assign WILL_FIRE_RL_burst = CAN_FIRE_RL_burst ; // rule RL_source_selected_1 @@ -4491,38 +5394,132 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_1 assign CAN_FIRE_RL_burst_1 = ifcs_1_innerReq$EMPTY_N && ifcs_1_innerRoute$EMPTY_N && - state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600 ; + state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 ; assign WILL_FIRE_RL_burst_1 = CAN_FIRE_RL_burst_1 ; - // rule __me_check_182 - assign CAN_FIRE___me_check_182 = 1'b1 ; - assign WILL_FIRE___me_check_182 = 1'b1 ; + // rule __me_check_355 + assign CAN_FIRE___me_check_355 = 1'b1 ; + assign WILL_FIRE___me_check_355 = 1'b1 ; - // rule __me_check_184 - assign CAN_FIRE___me_check_184 = 1'b1 ; - assign WILL_FIRE___me_check_184 = 1'b1 ; + // rule __me_check_357 + assign CAN_FIRE___me_check_357 = 1'b1 ; + assign WILL_FIRE___me_check_357 = 1'b1 ; // rule RL_sink_selected assign CAN_FIRE_RL_sink_selected = - IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425 && - flitToSink_0$whas ; + flitToSink_0$whas && + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 ; assign WILL_FIRE_RL_sink_selected = CAN_FIRE_RL_sink_selected ; // rule RL_sink_selected_1 assign CAN_FIRE_RL_sink_selected_1 = - IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426 && - flitToSink_1$whas ; + flitToSink_1$whas && + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 ; assign WILL_FIRE_RL_sink_selected_1 = CAN_FIRE_RL_sink_selected_1 ; // rule RL_sink_selected_2 assign CAN_FIRE_RL_sink_selected_2 = - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 && - flitToSink_2$whas ; + flitToSink_2$whas && + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 ; assign WILL_FIRE_RL_sink_selected_2 = CAN_FIRE_RL_sink_selected_2 ; - // rule __me_check_186 - assign CAN_FIRE___me_check_186 = 1'b1 ; - assign WILL_FIRE___me_check_186 = 1'b1 ; + // rule __me_check_359 + assign CAN_FIRE___me_check_359 = 1'b1 ; + assign WILL_FIRE___me_check_359 = 1'b1 ; + + // rule RL_checkSinkReady_3 + assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + + // rule RL_checkSinkReady_4 + assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + + // rule RL_craftReq_2 + assign CAN_FIRE_RL_craftReq_2 = + ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; + + // rule RL_craftReq_3 + assign CAN_FIRE_RL_craftReq_3 = + ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; + + // rule RL_craftReq_4 + assign CAN_FIRE_RL_craftReq_4 = + ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; + + // rule RL_arbitrate_1 + assign CAN_FIRE_RL_arbitrate_1 = + reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 && + !state_1 ; + assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; + + // rule RL_source_selected_2 + assign CAN_FIRE_RL_source_selected_2 = + (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_0$whas ; + assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; + + // rule RL_burst_2 + assign CAN_FIRE_RL_burst_2 = + ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 ; + assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; + + // rule RL_source_selected_3 + assign CAN_FIRE_RL_source_selected_3 = + (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_1$whas ; + assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; + + // rule RL_burst_3 + assign CAN_FIRE_RL_burst_3 = + ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 ; + assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; + + // rule __me_check_374 + assign CAN_FIRE___me_check_374 = 1'b1 ; + assign WILL_FIRE___me_check_374 = 1'b1 ; + + // rule RL_source_selected_4 + assign CAN_FIRE_RL_source_selected_4 = + (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_2$whas ; + assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; + + // rule RL_burst_4 + assign CAN_FIRE_RL_burst_4 = + ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 ; + assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; + + // rule __me_check_372 + assign CAN_FIRE___me_check_372 = 1'b1 ; + assign WILL_FIRE___me_check_372 = 1'b1 ; + + // rule __me_check_376 + assign CAN_FIRE___me_check_376 = 1'b1 ; + assign WILL_FIRE___me_check_376 = 1'b1 ; + + // rule RL_sink_selected_3 + assign CAN_FIRE_RL_sink_selected_3 = + flitToSink_1_0$whas && msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; + + // rule RL_sink_selected_4 + assign CAN_FIRE_RL_sink_selected_4 = + flitToSink_1_1$whas && msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; + + // rule __me_check_378 + assign CAN_FIRE___me_check_378 = 1'b1 ; + assign WILL_FIRE___me_check_378 = 1'b1 ; // rule RL_checkSinkReady_5 assign CAN_FIRE_RL_checkSinkReady_5 = 1'd1 ; @@ -4563,7 +5560,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_5 assign CAN_FIRE_RL_burst_5 = ifcs_0_1_innerReq$EMPTY_N && ifcs_0_1_innerRoute$EMPTY_N && - state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193 ; + state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 ; assign WILL_FIRE_RL_burst_5 = CAN_FIRE_RL_burst_5 ; // rule RL_source_selected_6 @@ -4576,92 +5573,205 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_6 assign CAN_FIRE_RL_burst_6 = ifcs_1_1_innerReq$EMPTY_N && ifcs_1_1_innerRoute$EMPTY_N && - state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233 ; + state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 ; assign WILL_FIRE_RL_burst_6 = CAN_FIRE_RL_burst_6 ; - // rule __me_check_229 - assign CAN_FIRE___me_check_229 = 1'b1 ; - assign WILL_FIRE___me_check_229 = 1'b1 ; + // rule __me_check_414 + assign CAN_FIRE___me_check_414 = 1'b1 ; + assign WILL_FIRE___me_check_414 = 1'b1 ; - // rule __me_check_231 - assign CAN_FIRE___me_check_231 = 1'b1 ; - assign WILL_FIRE___me_check_231 = 1'b1 ; + // rule __me_check_416 + assign CAN_FIRE___me_check_416 = 1'b1 ; + assign WILL_FIRE___me_check_416 = 1'b1 ; // rule RL_sink_selected_5 assign CAN_FIRE_RL_sink_selected_5 = - ssNoSynth_0_ar_buffer_ff$FULL_N && flitToSink_1_0_1$whas ; + flitToSink_1_0_1$whas && ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_5 = CAN_FIRE_RL_sink_selected_5 ; // rule RL_sink_selected_6 assign CAN_FIRE_RL_sink_selected_6 = - ssNoSynth_1_ar_buffer_ff$FULL_N && flitToSink_1_1_1$whas ; + flitToSink_1_1_1$whas && ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_6 = CAN_FIRE_RL_sink_selected_6 ; // rule RL_sink_selected_7 assign CAN_FIRE_RL_sink_selected_7 = - ssNoSynth_2_ar_buffer_ff$FULL_N && flitToSink_1_2$whas ; + flitToSink_1_2$whas && ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_7 = CAN_FIRE_RL_sink_selected_7 ; - // rule __me_check_233 - assign CAN_FIRE___me_check_233 = 1'b1 ; - assign WILL_FIRE___me_check_233 = 1'b1 ; + // rule __me_check_418 + assign CAN_FIRE___me_check_418 = 1'b1 ; + assign WILL_FIRE___me_check_418 = 1'b1 ; + + // rule RL_checkSinkReady_8 + assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; + + // rule RL_checkSinkReady_9 + assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; + + // rule RL_craftReq_7 + assign CAN_FIRE_RL_craftReq_7 = + ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; + + // rule RL_craftReq_8 + assign CAN_FIRE_RL_craftReq_8 = + ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; + + // rule RL_craftReq_9 + assign CAN_FIRE_RL_craftReq_9 = + ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; + + // rule RL_arbitrate_3 + assign CAN_FIRE_RL_arbitrate_3 = + reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 && + !state_1_1_1 ; + assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; + + // rule RL_source_selected_7 + assign CAN_FIRE_RL_source_selected_7 = + (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; + + // rule RL_burst_7 + assign CAN_FIRE_RL_burst_7 = + ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 ; + assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; + + // rule RL_source_selected_8 + assign CAN_FIRE_RL_source_selected_8 = + (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_1_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; + + // rule RL_burst_8 + assign CAN_FIRE_RL_burst_8 = + ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 ; + assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; + + // rule __me_check_433 + assign CAN_FIRE___me_check_433 = 1'b1 ; + assign WILL_FIRE___me_check_433 = 1'b1 ; + + // rule RL_source_selected_9 + assign CAN_FIRE_RL_source_selected_9 = + (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_2$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; + + // rule RL_burst_9 + assign CAN_FIRE_RL_burst_9 = + ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 ; + assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; + + // rule __me_check_431 + assign CAN_FIRE___me_check_431 = 1'b1 ; + assign WILL_FIRE___me_check_431 = 1'b1 ; + + // rule __me_check_435 + assign CAN_FIRE___me_check_435 = 1'b1 ; + assign WILL_FIRE___me_check_435 = 1'b1 ; + + // rule RL_sink_selected_8 + assign CAN_FIRE_RL_sink_selected_8 = + flitToSink_1_1_0$whas && msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; + + // rule RL_sink_selected_9 + assign CAN_FIRE_RL_sink_selected_9 = + flitToSink_1_1_1_1$whas && + msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; + + // rule __me_check_437 + assign CAN_FIRE___me_check_437 = 1'b1 ; + assign WILL_FIRE___me_check_437 = 1'b1 ; // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_ug_uncached_mem_shim_master_u_aw_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + // rule RL_proc_uncached_awSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek = + proc$RDY_master1_aw_peek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek = + proc$RDY_master1_aw_peek ; + + // rule RL_proc_uncached_wSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek = + proc$RDY_master1_w_peek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek = + proc$RDY_master1_w_peek ; + + // rule RL_proc_uncached_arSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek = + proc$RDY_master1_ar_peek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek = + proc$RDY_master1_ar_peek ; + + // rule RL_uncached_mem_master_awSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = - ug_uncached_mem_shim_master_u_aw_dropWire$whas && + // rule RL_uncached_mem_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = + uncached_mem_master_awSynth_src_dropWire$whas && !uncached_mem_shim_awff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_w_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + // rule RL_uncached_mem_master_wSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_w_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = - ug_uncached_mem_shim_master_u_w_dropWire$whas && + // rule RL_uncached_mem_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = + uncached_mem_master_wSynth_src_dropWire$whas && !uncached_mem_shim_wff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_b_warnDoPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = - ug_uncached_mem_shim_master_u_b_putWire$whas && + // rule RL_uncached_mem_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = + uncached_mem_master_bSynth_snk_putWire$whas && !uncached_mem_shim_bff$FULL_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut ; - // rule RL_ug_uncached_mem_shim_master_u_ar_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + // rule RL_uncached_mem_master_arSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = - ug_uncached_mem_shim_master_u_ar_dropWire$whas && + // rule RL_uncached_mem_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = + uncached_mem_master_arSynth_src_dropWire$whas && !uncached_mem_shim_arff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_r_warnDoPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = - ug_uncached_mem_shim_master_u_r_putWire$whas && + // rule RL_uncached_mem_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = + uncached_mem_master_rSynth_snk_putWire$whas && !uncached_mem_shim_rff$FULL_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut ; // rule RL_tagController_tmp_passCacheResponse assign CAN_FIRE_RL_tagController_tmp_passCacheResponse = @@ -4699,113 +5809,176 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek ; - // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = - tagController_tmp_ug_master_u_aw_dropWire$whas && - !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; - - // rule RL_tagController_tmp_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = - tagController_tmp_shimMaster_awff_rv$port1__read[99] && - tagController_tmp_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; - // rule RL_tagController_tmp_ug_master_u_w_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = tagController_tmp_shimMaster_wff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek ; - // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = - tagController_tmp_ug_master_u_w_dropWire$whas && - !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; - - // rule RL_tagController_tmp_ug_master_u_w_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = - tagController_tmp_shimMaster_wff_rv$port1__read[73] && - tagController_tmp_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; - - // rule RL_tagController_tmp_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = - tagController_tmp_ug_master_u_b_putWire$whas && - tagController_tmp_shimMaster_bff_rv[8] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; - - // rule RL_tagController_tmp_ug_master_u_b_doPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = - !tagController_tmp_shimMaster_bff_rv[8] && - tagController_tmp_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; - // rule RL_tagController_tmp_ug_master_u_ar_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = tagController_tmp_shimMaster_arff_rv$port1__read[99] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek ; - // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = - tagController_tmp_ug_master_u_ar_dropWire$whas && - !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; + // rule RL_tmp2_awNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit = + proc$master0_awvalid && tmp2_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; - // rule RL_tagController_tmp_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = - tagController_tmp_shimMaster_arff_rv$port1__read[99] && - tagController_tmp_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; + // rule RL_tmp2_awNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; - // rule RL_tagController_tmp_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = - tagController_tmp_ug_master_u_r_putWire$whas && - tagController_tmp_shimMaster_rff_rv[73] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; + // rule RL_tmp2_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit && + !tmp2_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut ; - // rule RL_tagController_tmp_ug_master_u_r_doPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = - !tagController_tmp_shimMaster_rff_rv[73] && - tagController_tmp_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; + // rule RL_tmp2_awNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut = + tmp2_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut ; - // rule RL_tagController_tmp_passMemoryResponseWrite - assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = - tagController_tmp_shimMaster_bff_rv$port1__read[8] && - tagController_tmp_tagCon$RDY_memory_response_put ; - assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = - CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && - !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + // rule RL_tmp2_wNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit = + proc$master0_wvalid && tmp2_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; - // rule RL_tagController_tmp_passMemoryResponseRead - assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = - tagController_tmp_shimMaster_rff_rv$port1__read[73] && - tagController_tmp_tagCon$RDY_memory_response_put ; - assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = - CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + // rule RL_tmp2_wNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = - !tagController_tmp_shimSlave_awff_rv[98] && - proc$master0_awvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + // rule RL_tmp2_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit && + !tmp2_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut ; + + // rule RL_tmp2_wNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut = + tmp2_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut ; + + // rule RL_tmp2_bNoSynth_dropFlit + assign CAN_FIRE_RL_tmp2_bNoSynth_dropFlit = + tmp2_bNoSynth_buffer_ff$EMPTY_N && proc$master0_bready ; + assign WILL_FIRE_RL_tmp2_bNoSynth_dropFlit = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit ; + + // rule RL_tmp2_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && + !tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop ; + + // rule RL_tmp2_arNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit = + proc$master0_arvalid && tmp2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; + + // rule RL_tmp2_arNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_tmp2_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit && + !tmp2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut ; + + // rule RL_tmp2_arNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut = + tmp2_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut ; + + // rule RL_tmp2_rNoSynth_dropFlit + assign CAN_FIRE_RL_tmp2_rNoSynth_dropFlit = + tmp2_rNoSynth_buffer_ff$EMPTY_N && proc$master0_rready ; + assign WILL_FIRE_RL_tmp2_rNoSynth_dropFlit = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit ; + + // rule RL_tmp2_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && + !tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = + tmp2_awNoSynth_buffer_firstValid$Q_OUT && + (tmp2_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek ; + + // rule RL_Prelude_inst_changeSpecialWires_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + !tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; + + // rule RL_tmp2_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop || + tmp2_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; + + // rule RL_tmp2_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop && + tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + tagController_tmp_shimSlave_awff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = + tmp2_awNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_awff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_aw_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && tagController_tmp_shimSlave_awff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut ; @@ -4813,7 +5986,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_aw_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = !tagController_tmp_shimSlave_awff_rv[98] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut ; @@ -4824,19 +5997,66 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_getCacheAW = CAN_FIRE_RL_tagController_tmp_getCacheAW ; - // rule RL_tmp2_aw_forwardReady - assign CAN_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = + tmp2_wNoSynth_buffer_firstValid$Q_OUT && + (tmp2_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek ; - // rule RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = - !tagController_tmp_shimSlave_wff_rv[74] && proc$master0_wvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + // rule RL_Prelude_inst_changeSpecialWires_1_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + !tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; + + // rule RL_tmp2_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop || + tmp2_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; + + // rule RL_tmp2_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop && + tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + tagController_tmp_shimSlave_wff_rv[74] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = + tmp2_wNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_wff_rv[74] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_w_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && tagController_tmp_shimSlave_wff_rv[74] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut ; @@ -4844,24 +6064,39 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_w_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = !tagController_tmp_shimSlave_wff_rv[74] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut ; - // rule RL_tmp2_w_forwardReady - assign CAN_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = + 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = + // rule RL_Prelude_inst_changeSpecialWires_2_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = tagController_tmp_shimSlave_bff_rv$port1__read[7] && - tmp2_b_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + tmp2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; + + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_b_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop && !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop ; @@ -4869,47 +6104,118 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_b_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = tagController_tmp_shimSlave_bff_rv$port1__read[7] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop ; - // rule RL_tmp2_b_forwardFlit - assign CAN_FIRE_RL_tmp2_b_forwardFlit = - tmp2_b_buffer_firstValid$Q_OUT && - (tmp2_b_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) ; - assign WILL_FIRE_RL_tmp2_b_forwardFlit = CAN_FIRE_RL_tmp2_b_forwardFlit ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + !tmp2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut ; - // rule RL_tmp2_b_dropFlit - assign CAN_FIRE_RL_tmp2_b_dropFlit = - (tmp2_b_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) && - proc$master0_bready ; - assign WILL_FIRE_RL_tmp2_b_dropFlit = CAN_FIRE_RL_tmp2_b_dropFlit ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = + tmp2_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut ; - // rule RL_tmp2_b_buffer_enqueue - assign CAN_FIRE_RL_tmp2_b_buffer_enqueue = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && - (!CAN_FIRE_RL_tmp2_b_dropFlit || tmp2_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp2_b_buffer_enqueue = - CAN_FIRE_RL_tmp2_b_buffer_enqueue ; + // rule RL_tmp2_bNoSynth_src_setPeek + assign CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek = + tmp2_bNoSynth_buffer_firstValid$Q_OUT && + (tmp2_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut) ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek = + CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek ; - // rule RL_tmp2_b_buffer_dequeue - assign CAN_FIRE_RL_tmp2_b_buffer_dequeue = - CAN_FIRE_RL_tmp2_b_dropFlit && tmp2_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp2_b_buffer_dequeue = - CAN_FIRE_RL_tmp2_b_buffer_dequeue ; + // rule RL_tmp2_bNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = - !tagController_tmp_shimSlave_arff_rv[98] && - proc$master0_arvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + // rule RL_tmp2_bNoSynth_src_doDrop + assign CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && + tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; + + // rule RL_tmp2_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut && + (!CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop || + tmp2_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; + + // rule RL_tmp2_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop && + tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = + tmp2_arNoSynth_buffer_firstValid$Q_OUT && + (tmp2_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek ; + + // rule RL_Prelude_inst_changeSpecialWires_3_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + !tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; + + // rule RL_tmp2_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop || + tmp2_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; + + // rule RL_tmp2_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop && + tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + tagController_tmp_shimSlave_arff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = + tmp2_arNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_arff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_ar_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && tagController_tmp_shimSlave_arff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut ; @@ -4917,7 +6223,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_ar_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = !tagController_tmp_shimSlave_arff_rv[98] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut ; @@ -4937,20 +6243,35 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_passCacheRead = CAN_FIRE_RL_tagController_tmp_passCacheRead ; - // rule RL_tmp2_ar_forwardReady - assign CAN_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = + 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = + // rule RL_Prelude_inst_changeSpecialWires_4_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = tagController_tmp_shimSlave_rff_rv$port1__read[73] && - tmp2_r_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + tmp2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; + + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_r_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop && !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop ; @@ -4958,1182 +6279,1319 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_r_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = tagController_tmp_shimSlave_rff_rv$port1__read[73] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop ; - // rule RL_tagController_tmp_propagateReset - assign CAN_FIRE_RL_tagController_tmp_propagateReset = - !tagController_tmp_reset_done ; - assign WILL_FIRE_RL_tagController_tmp_propagateReset = - CAN_FIRE_RL_tagController_tmp_propagateReset ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + !tmp2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut ; - // rule RL_tmp2_r_forwardFlit - assign CAN_FIRE_RL_tmp2_r_forwardFlit = - tmp2_r_buffer_firstValid$Q_OUT && - (tmp2_r_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) ; - assign WILL_FIRE_RL_tmp2_r_forwardFlit = CAN_FIRE_RL_tmp2_r_forwardFlit ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = + tmp2_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut ; - // rule RL_tmp2_r_dropFlit - assign CAN_FIRE_RL_tmp2_r_dropFlit = - (tmp2_r_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) && - proc$master0_rready ; - assign WILL_FIRE_RL_tmp2_r_dropFlit = CAN_FIRE_RL_tmp2_r_dropFlit ; + // rule RL_tmp2_rNoSynth_src_setPeek + assign CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek = + tmp2_rNoSynth_buffer_firstValid$Q_OUT && + (tmp2_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut) ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek = + CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek ; - // rule RL_tmp2_r_buffer_enqueue - assign CAN_FIRE_RL_tmp2_r_buffer_enqueue = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && - (!CAN_FIRE_RL_tmp2_r_dropFlit || tmp2_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp2_r_buffer_enqueue = - CAN_FIRE_RL_tmp2_r_buffer_enqueue ; + // rule RL_tmp2_rNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; - // rule RL_tmp2_r_buffer_dequeue - assign CAN_FIRE_RL_tmp2_r_buffer_dequeue = - CAN_FIRE_RL_tmp2_r_dropFlit && tmp2_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp2_r_buffer_dequeue = - CAN_FIRE_RL_tmp2_r_buffer_dequeue ; + // rule RL_tmp2_rNoSynth_src_doDrop + assign CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && + tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; - // rule RL_ssNoSynth_0_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit = - !uncached_mem_shim_arff$FULL_N || - ssNoSynth_0_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_0_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_5) && - uncached_mem_shim_arff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + // rule RL_tmp2_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut && + (!CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop || + tmp2_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; - // rule RL_ssNoSynth_0_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit = - (ssNoSynth_0_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_5) && - uncached_mem_shim_arff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit ; + // rule RL_tmp2_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop && + tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; - // rule RL_ug_uncached_mem_shim_master_u_ar_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = - uncached_mem_shim_arff$EMPTY_N && - ug_uncached_mem_shim_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + // rule RL_slave_vector_0_bSynth_src_setPeek + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek = + uncached_mem_shim_bff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek = + uncached_mem_shim_bff$EMPTY_N ; - // rule RL_ssNoSynth_0_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_5 && - (!WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit || - ssNoSynth_0_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + // rule RL_slave_vector_0_rSynth_src_setPeek + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek = + uncached_mem_shim_rff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek = + uncached_mem_shim_rff$EMPTY_N ; - // rule RL_ssNoSynth_0_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit && - ssNoSynth_0_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + // rule RL_msNoSynth_0_awNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = + proc$master1_aw_canPeek && + msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; - // rule RL_ssNoSynth_1_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit = - ssNoSynth_1_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_1_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_6) ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; + // rule RL_msNoSynth_0_awNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_1_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit = - (ssNoSynth_1_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_6) && - plic$axi4_slave_arready ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + // rule RL_proc_uncached_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + !proc$master1_aw_canPeek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_6 && - (!CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit || - ssNoSynth_1_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + // rule RL_proc_uncached_awSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop = + proc$RDY_master1_aw_drop && + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + proc$master1_aw_canPeek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; - // rule RL_ssNoSynth_1_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit && - ssNoSynth_1_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + // rule RL_msNoSynth_0_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + !msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut ; - // rule RL_ssNoSynth_2_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit = - ssNoSynth_2_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_2_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_7) ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + // rule RL_msNoSynth_0_awNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = + msNoSynth_0_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut ; - // rule RL_ssNoSynth_2_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit = - (ssNoSynth_2_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_7) && - proc$debug_module_mem_server_arready ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + // rule RL_msNoSynth_0_wNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = + proc$master1_w_canPeek && msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; - // rule RL_ssNoSynth_2_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_7 && - (!CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit || - ssNoSynth_2_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + // rule RL_msNoSynth_0_wNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_2_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit && - ssNoSynth_2_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + // rule RL_proc_uncached_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + !proc$master1_w_canPeek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop ; - // rule RL_split_0_putFirst - assign CAN_FIRE_RL_split_0_putFirst = - split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 && - split_0_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + // rule RL_proc_uncached_wSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop = + proc$RDY_master1_w_drop && + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + proc$master1_w_canPeek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; - // rule RL_ssNoSynth_0_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit = - !uncached_mem_shim_awff$FULL_N || - ssNoSynth_0_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_0_aw_buffer_ff$EMPTY_N || - MUX_split_0_flitLeft$write_1__SEL_2) && + // rule RL_msNoSynth_0_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + !msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_0_wNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = + msNoSynth_0_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && proc$master1_b_canPut ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; + + // rule RL_msNoSynth_0_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + !msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_0_arNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = + proc$master1_ar_canPeek && + msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; + + // rule RL_msNoSynth_0_arNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_proc_uncached_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + !proc$master1_ar_canPeek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop ; + + // rule RL_proc_uncached_arSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop = + proc$RDY_master1_ar_drop && + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + proc$master1_ar_canPeek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; + + // rule RL_msNoSynth_0_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + !msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_0_arNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = + msNoSynth_0_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && proc$master1_r_canPut ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; + + // rule RL_msNoSynth_0_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + !msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_1_bNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + debug_module$master_bready ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit ; + + // rule RL_msNoSynth_1_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && + !msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_1_rNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + debug_module$master_rready ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit ; + + // rule RL_msNoSynth_1_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && + !msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_0_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_awff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_0_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit = - (ssNoSynth_0_aw_buffer_ff$EMPTY_N || - MUX_split_0_flitLeft$write_1__SEL_2) && - uncached_mem_shim_awff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit ; + // rule RL_ssNoSynth_0_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + !ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_aw_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = - uncached_mem_shim_awff$EMPTY_N && - ug_uncached_mem_shim_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; - - // rule RL_ssNoSynth_0_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = - MUX_split_0_flitLeft$write_1__SEL_2 && - (!WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit || - ssNoSynth_0_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; - - // rule RL_ssNoSynth_0_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit && - ssNoSynth_0_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; - - // rule RL_split_0_putOther - assign CAN_FIRE_RL_split_0_putOther = - CAN_FIRE_RL_sink_selected && - (!split_0_doPut$wget[172] || ssNoSynth_0_w_buffer_ff$FULL_N) && - split_0_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; - - // rule RL_ssNoSynth_0_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit = - !uncached_mem_shim_wff$FULL_N || - ssNoSynth_0_w_buffer_firstValid$Q_OUT && - (ssNoSynth_0_w_buffer_ff$EMPTY_N || - ssNoSynth_0_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_0_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_wff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_0_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_w_dropFlit = - (ssNoSynth_0_w_buffer_ff$EMPTY_N || - ssNoSynth_0_w_buffer_enqw$whas) && - uncached_mem_shim_wff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_w_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit ; + // rule RL_ssNoSynth_0_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + !ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_w_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = - uncached_mem_shim_wff$EMPTY_N && - ug_uncached_mem_shim_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + // rule RL_ssNoSynth_0_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = + uncached_mem_shim_bff$EMPTY_N && + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; - // rule RL_ssNoSynth_0_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = - ssNoSynth_0_w_buffer_enqw$whas && - (!WILL_FIRE_RL_ssNoSynth_0_w_dropFlit || - ssNoSynth_0_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + // rule RL_ssNoSynth_0_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_0_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit && - ssNoSynth_0_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + // rule RL_slave_vector_0_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && + !uncached_mem_shim_bff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = + CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop ; - // rule RL_split_1_putFirst - assign CAN_FIRE_RL_split_1_putFirst = - split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 && - split_1_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + // rule RL_slave_vector_0_bSynth_src_doDrop + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop = + uncached_mem_shim_bff$EMPTY_N && + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop = + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; - // rule RL_ssNoSynth_1_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit = - ssNoSynth_1_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_1_aw_buffer_ff$EMPTY_N || - MUX_split_1_flitLeft$write_1__SEL_2) ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + // rule RL_uncached_mem_master_bSynth_snk_doPut + assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = + uncached_mem_shim_bff$FULL_N && + uncached_mem_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; - // rule RL_ssNoSynth_1_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit = - (ssNoSynth_1_aw_buffer_ff$EMPTY_N || - MUX_split_1_flitLeft$write_1__SEL_2) && + // rule RL_ssNoSynth_0_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && + !ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_0_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_0_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + !ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_0_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = + uncached_mem_shim_rff$EMPTY_N && + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_0_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_slave_vector_0_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && + !uncached_mem_shim_rff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = + CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop ; + + // rule RL_slave_vector_0_rSynth_src_doDrop + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop = + uncached_mem_shim_rff$EMPTY_N && + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop = + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; + + // rule RL_uncached_mem_master_rSynth_snk_doPut + assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = + uncached_mem_shim_rff$FULL_N && + uncached_mem_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && + !ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_0_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_1_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_awready ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_1_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = - MUX_split_1_flitLeft$write_1__SEL_2 && - (!CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit || - ssNoSynth_1_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + // rule RL_ssNoSynth_1_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && + !ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit && - ssNoSynth_1_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; - - // rule RL_split_1_putOther - assign CAN_FIRE_RL_split_1_putOther = - CAN_FIRE_RL_sink_selected_1 && - (!split_1_doPut$wget[172] || ssNoSynth_1_w_buffer_ff$FULL_N) && - split_1_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; - - // rule RL_ssNoSynth_1_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit = - ssNoSynth_1_w_buffer_firstValid$Q_OUT && - (ssNoSynth_1_w_buffer_ff$EMPTY_N || - ssNoSynth_1_w_buffer_enqw$whas) ; - assign WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; - - // rule RL_ssNoSynth_1_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_w_dropFlit = - (ssNoSynth_1_w_buffer_ff$EMPTY_N || - ssNoSynth_1_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_1_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_wready ; - assign WILL_FIRE_RL_ssNoSynth_1_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_1_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = - ssNoSynth_1_w_buffer_enqw$whas && - (!CAN_FIRE_RL_ssNoSynth_1_w_dropFlit || - ssNoSynth_1_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + // rule RL_ssNoSynth_1_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && + !ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit && - ssNoSynth_1_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + // rule RL_ssNoSynth_1_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = + plic$axi4_slave_bvalid && ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; - // rule RL_split_2_putFirst - assign CAN_FIRE_RL_split_2_putFirst = - split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 && - split_2_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + // rule RL_ssNoSynth_1_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_2_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit = - ssNoSynth_2_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_2_aw_buffer_ff$EMPTY_N || - MUX_split_2_flitLeft$write_1__SEL_2) ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + // rule RL_ssNoSynth_1_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit && + !ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut ; - // rule RL_ssNoSynth_2_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit = - (ssNoSynth_2_aw_buffer_ff$EMPTY_N || - MUX_split_2_flitLeft$write_1__SEL_2) && + // rule RL_ssNoSynth_1_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = + ssNoSynth_1_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_1_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + plic$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_1_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && + !ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_1_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = + plic$axi4_slave_rvalid && ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_1_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_1_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit && + !ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_1_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = + ssNoSynth_1_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_2_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_awready ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_2_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = - MUX_split_2_flitLeft$write_1__SEL_2 && - (!CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit || - ssNoSynth_2_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + // rule RL_ssNoSynth_2_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && + !ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_2_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit && - ssNoSynth_2_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; - - // rule RL_split_2_putOther - assign CAN_FIRE_RL_split_2_putOther = - CAN_FIRE_RL_sink_selected_2 && - (!split_2_doPut$wget[172] || ssNoSynth_2_w_buffer_ff$FULL_N) && - split_2_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; - - // rule RL_ssNoSynth_2_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit = - ssNoSynth_2_w_buffer_firstValid$Q_OUT && - (ssNoSynth_2_w_buffer_ff$EMPTY_N || - ssNoSynth_2_w_buffer_enqw$whas) ; - assign WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; - - // rule RL_ssNoSynth_2_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_w_dropFlit = - (ssNoSynth_2_w_buffer_ff$EMPTY_N || - ssNoSynth_2_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_2_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_wready ; - assign WILL_FIRE_RL_ssNoSynth_2_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_2_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = - ssNoSynth_2_w_buffer_enqw$whas && - (!CAN_FIRE_RL_ssNoSynth_2_w_dropFlit || - ssNoSynth_2_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + // rule RL_ssNoSynth_2_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && + !ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_2_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit && - ssNoSynth_2_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + // rule RL_ssNoSynth_2_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N && + proc$debug_module_mem_server_arready ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_2_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && + !ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop ; + + // rule RL_merged_0_passFlit + assign CAN_FIRE_RL_merged_0_passFlit = + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_passFlit = CAN_FIRE_RL_merged_0_passFlit ; + + // rule RL_merged_1_passFlit + assign CAN_FIRE_RL_merged_1_passFlit = + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_passFlit = CAN_FIRE_RL_merged_1_passFlit ; // rule RL_ifcs_0_firstFlit assign CAN_FIRE_RL_ifcs_0_firstFlit = - proc$master1_wvalid && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && ifcs_0_innerRoute$FULL_N && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd0 && - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 == + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit = CAN_FIRE_RL_ifcs_0_firstFlit ; // rule RL_ifcs_0_followFlits assign CAN_FIRE_RL_ifcs_0_followFlits = - proc$master1_wvalid && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_followFlits = CAN_FIRE_RL_ifcs_0_followFlits ; // rule RL_ifcs_0_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_nonRoutableFlit = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + (!CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171] || + !ifcs_0_noRoute_inner_pendingReq) && ifcs_0_state == 2'd0 && - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 != + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_nonRoutableFlit ; // rule RL_ifcs_0_drainFlits assign CAN_FIRE_RL_ifcs_0_drainFlits = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - proc$master1_wvalid && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_drainFlits = CAN_FIRE_RL_ifcs_0_drainFlits ; - // rule __me_check_158 - assign CAN_FIRE___me_check_158 = 1'b1 ; - assign WILL_FIRE___me_check_158 = 1'b1 ; + // rule __me_check_325 + assign CAN_FIRE___me_check_325 = 1'b1 ; + assign WILL_FIRE___me_check_325 = 1'b1 ; - // rule RL_ifcs_0_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = - msNoSynth_0_b_buffer_ff$FULL_N && ifcs_0_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + // rule RL_ifcs_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_firstFlit = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_innerReq$FULL_N && + ifcs_1_innerRoute$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; - // rule RL_checkSinkReady_3 - assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + // rule RL_ifcs_1_followFlits + assign CAN_FIRE_RL_ifcs_1_followFlits = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_innerReq$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; - // rule RL_ifcs_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = - msNoSynth_1_b_buffer_ff$FULL_N && ifcs_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + // rule RL_ifcs_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + (!CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171] || + !ifcs_1_noRoute_inner_pendingReq) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; - // rule RL_checkSinkReady_4 - assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + // rule RL_ifcs_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_drainFlits = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; - // rule RL_craftReq_2 - assign CAN_FIRE_RL_craftReq_2 = - ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; - - // rule RL_craftReq_3 - assign CAN_FIRE_RL_craftReq_3 = - ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; - - // rule RL_craftReq_4 - assign CAN_FIRE_RL_craftReq_4 = - ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; - - // rule RL_arbitrate_1 - assign CAN_FIRE_RL_arbitrate_1 = - reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669 && - !state_1 ; - assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; - - // rule RL_source_selected_2 - assign CAN_FIRE_RL_source_selected_2 = - (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_0$whas ; - assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; - - // rule RL_burst_2 - assign CAN_FIRE_RL_burst_2 = - ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761 ; - assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; - - // rule RL_source_selected_3 - assign CAN_FIRE_RL_source_selected_3 = - (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_1$whas ; - assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; - - // rule RL_burst_3 - assign CAN_FIRE_RL_burst_3 = - ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794 ; - assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; - - // rule __me_check_197 - assign CAN_FIRE___me_check_197 = 1'b1 ; - assign WILL_FIRE___me_check_197 = 1'b1 ; - - // rule RL_source_selected_4 - assign CAN_FIRE_RL_source_selected_4 = - (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_2$whas ; - assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; - - // rule RL_burst_4 - assign CAN_FIRE_RL_burst_4 = - ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828 ; - assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; - - // rule __me_check_195 - assign CAN_FIRE___me_check_195 = 1'b1 ; - assign WILL_FIRE___me_check_195 = 1'b1 ; - - // rule __me_check_199 - assign CAN_FIRE___me_check_199 = 1'b1 ; - assign WILL_FIRE___me_check_199 = 1'b1 ; - - // rule RL_sink_selected_3 - assign CAN_FIRE_RL_sink_selected_3 = - !CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && flitToSink_1_0$whas ; - assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; - - // rule RL_sink_selected_4 - assign CAN_FIRE_RL_sink_selected_4 = - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && flitToSink_1_1$whas ; - assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; - - // rule __me_check_201 - assign CAN_FIRE___me_check_201 = 1'b1 ; - assign WILL_FIRE___me_check_201 = 1'b1 ; - - // rule RL_ifcs_0_forwardRsp - assign CAN_FIRE_RL_ifcs_0_forwardRsp = - msNoSynth_0_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_3 && - !ifcs_0_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_forwardRsp = CAN_FIRE_RL_ifcs_0_forwardRsp ; - - // rule RL_msNoSynth_0_b_forwardFlit - assign CAN_FIRE_RL_msNoSynth_0_b_forwardFlit = - !tmp0_b_buffer_ff$FULL_N || - msNoSynth_0_b_buffer_firstValid$Q_OUT && - (msNoSynth_0_b_buffer_ff$EMPTY_N || - msNoSynth_0_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_0_b_forwardFlit = - CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; - - // rule RL_tmp0_b_forwardFlit - assign CAN_FIRE_RL_tmp0_b_forwardFlit = - tmp0_b_buffer_firstValid$Q_OUT && - (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_tmp0_b_forwardFlit = CAN_FIRE_RL_tmp0_b_forwardFlit ; - - // rule RL_tmp0_b_dropFlit - assign CAN_FIRE_RL_tmp0_b_dropFlit = - (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) && - proc$master1_bready ; - assign WILL_FIRE_RL_tmp0_b_dropFlit = CAN_FIRE_RL_tmp0_b_dropFlit ; - - // rule RL_tmp0_b_buffer_enqueue - assign CAN_FIRE_RL_tmp0_b_buffer_enqueue = - tmp0_b_buffer_enqw$whas && - (!CAN_FIRE_RL_tmp0_b_dropFlit || tmp0_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp0_b_buffer_enqueue = - CAN_FIRE_RL_tmp0_b_buffer_enqueue ; - - // rule RL_tmp0_b_buffer_dequeue - assign CAN_FIRE_RL_tmp0_b_buffer_dequeue = - CAN_FIRE_RL_tmp0_b_dropFlit && tmp0_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp0_b_buffer_dequeue = - CAN_FIRE_RL_tmp0_b_buffer_dequeue ; - - // rule RL_msNoSynth_0_b_dropFlit - assign CAN_FIRE_RL_msNoSynth_0_b_dropFlit = - (msNoSynth_0_b_buffer_ff$EMPTY_N || - msNoSynth_0_b_buffer_enqw$whas) && - tmp0_b_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_msNoSynth_0_b_dropFlit = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; - - // rule RL_msNoSynth_0_b_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue = - msNoSynth_0_b_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_0_b_dropFlit || - msNoSynth_0_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; - - // rule RL_msNoSynth_0_b_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit && - msNoSynth_0_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; - - // rule RL_ifcs_0_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - ifcs_0_noRoute_inner_pendingReq$port1__read && - ifcs_0_noRouteRsp$FULL_N && - proc$master1_wvalid ; - assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; - - // rule __me_check_156 - assign CAN_FIRE___me_check_156 = 1'b1 ; - assign WILL_FIRE___me_check_156 = 1'b1 ; - - // rule __me_check_157 - assign CAN_FIRE___me_check_157 = 1'b1 ; - assign WILL_FIRE___me_check_157 = 1'b1 ; - - // rule __me_check_160 - assign CAN_FIRE___me_check_160 = 1'b1 ; - assign WILL_FIRE___me_check_160 = 1'b1 ; - - // rule RL_merged_0_genFirst - assign CAN_FIRE_RL_merged_0_genFirst = - proc$master1_awvalid && proc$master1_wvalid && - merged_0_doDrop$whas && - merged_0_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; - - // rule RL_msNoSynth_0_aw_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; - - // rule RL_tmp0_aw_forwardReady - assign CAN_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; - - // rule RL_merged_0_genOther - assign CAN_FIRE_RL_merged_0_genOther = - proc$master1_wvalid && merged_0_doDrop$whas && - merged_0_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; - - // rule RL_msNoSynth_0_w_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; - - // rule RL_tmp0_w_forwardReady - assign CAN_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_forwardRsp - assign CAN_FIRE_RL_ifcs_1_forwardRsp = - msNoSynth_1_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_4 && - !ifcs_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_forwardRsp = CAN_FIRE_RL_ifcs_1_forwardRsp ; - - // rule RL_msNoSynth_1_b_forwardFlit - assign CAN_FIRE_RL_msNoSynth_1_b_forwardFlit = - msNoSynth_1_b_buffer_firstValid$Q_OUT && - (msNoSynth_1_b_buffer_ff$EMPTY_N || - msNoSynth_1_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_1_b_forwardFlit = - CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; - - // rule RL_msNoSynth_1_b_dropFlit - assign CAN_FIRE_RL_msNoSynth_1_b_dropFlit = - (msNoSynth_1_b_buffer_ff$EMPTY_N || - msNoSynth_1_b_buffer_enqw$whas) && - debug_module$master_bready ; - assign WILL_FIRE_RL_msNoSynth_1_b_dropFlit = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; - - // rule RL_msNoSynth_1_b_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue = - msNoSynth_1_b_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_1_b_dropFlit || - msNoSynth_1_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; - - // rule RL_msNoSynth_1_b_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit && - msNoSynth_1_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + // rule __me_check_333 + assign CAN_FIRE___me_check_333 = 1'b1 ; + assign WILL_FIRE___me_check_333 = 1'b1 ; // rule RL_ifcs_0_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_firstFlit_1 = - uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && + ifcs_0_rspBack$FULL_N && ifcs_0_routeBack$FULL_N && !ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit_1 = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; // rule RL_ifcs_0_followFlits_1 assign CAN_FIRE_RL_ifcs_0_followFlits_1 = - uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && + ifcs_0_rspBack$FULL_N && ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_followFlits_1 = CAN_FIRE_RL_ifcs_0_followFlits_1 ; - // rule __me_check_170 - assign CAN_FIRE___me_check_170 = 1'b1 ; - assign WILL_FIRE___me_check_170 = 1'b1 ; + // rule __me_check_337 + assign CAN_FIRE___me_check_337 = 1'b1 ; + assign WILL_FIRE___me_check_337 = 1'b1 ; - // rule RL_ssNoSynth_0_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; - assign WILL_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; + // rule RL_ssNoSynth_0_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut && + (!ssNoSynth_0_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; - // rule RL_ug_uncached_mem_shim_master_u_b_doPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = - uncached_mem_shim_bff$FULL_N && - ug_uncached_mem_shim_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + // rule RL_ssNoSynth_0_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; // rule RL_ifcs_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_firstFlit_1 = - plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + ifcs_1_rspBack$FULL_N && ifcs_1_routeBack$FULL_N && !ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; // rule RL_ifcs_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_followFlits_1 = - plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + ifcs_1_rspBack$FULL_N && ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_followFlits_1 ; - // rule __me_check_172 - assign CAN_FIRE___me_check_172 = 1'b1 ; - assign WILL_FIRE___me_check_172 = 1'b1 ; + // rule __me_check_339 + assign CAN_FIRE___me_check_339 = 1'b1 ; + assign WILL_FIRE___me_check_339 = 1'b1 ; - // rule RL_ssNoSynth_1_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_1_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut && + (!ssNoSynth_1_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; - // rule RL_ifcs_2_firstFlit - assign CAN_FIRE_RL_ifcs_2_firstFlit = - proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && - ifcs_2_routeBack$FULL_N && - !ifcs_2_state ; - assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + // rule RL_ssNoSynth_1_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; - // rule RL_ifcs_2_followFlits - assign CAN_FIRE_RL_ifcs_2_followFlits = - proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && - ifcs_2_state ; - assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + // rule RL_sinks_0_warnDoPut + assign CAN_FIRE_RL_sinks_0_warnDoPut = + CAN_FIRE_RL_sink_selected && + ((split_0_flitLeft == 8'd0) ? + !ssNoSynth_0_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_0_warnDoPut = CAN_FIRE_RL_sinks_0_warnDoPut ; - // rule __me_check_174 - assign CAN_FIRE___me_check_174 = 1'b1 ; - assign WILL_FIRE___me_check_174 = 1'b1 ; + // rule RL_sinks_0_doPut + assign CAN_FIRE_RL_sinks_0_doPut = + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 && + CAN_FIRE_RL_sink_selected ; + assign WILL_FIRE_RL_sinks_0_doPut = CAN_FIRE_RL_sinks_0_doPut ; - // rule RL_ssNoSynth_2_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + // rule RL_split_0_putFirst + assign CAN_FIRE_RL_split_0_putFirst = + split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 && + split_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + + // rule RL_ssNoSynth_0_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = + ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + !uncached_mem_shim_awff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_awSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = + uncached_mem_shim_awff$EMPTY_N && + uncached_mem_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; + + // rule RL_slave_vector_0_awSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut = + uncached_mem_shim_awff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = + MUX_split_0_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop || + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop && + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; + + // rule RL_split_0_putOther + assign CAN_FIRE_RL_split_0_putOther = + CAN_FIRE_RL_sinks_0_doPut && + (!split_0_doPut$wget[172] || + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) && + split_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; + + // rule RL_ssNoSynth_0_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = + ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_0_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + !uncached_mem_shim_wff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_wSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = + uncached_mem_shim_wff$EMPTY_N && + uncached_mem_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; + + // rule RL_slave_vector_0_wSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut = + uncached_mem_shim_wff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = + ssNoSynth_0_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop || + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop && + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_warnDoPut = + CAN_FIRE_RL_sink_selected_1 && + ((split_1_flitLeft == 8'd0) ? + !ssNoSynth_1_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_1_warnDoPut = CAN_FIRE_RL_sinks_1_warnDoPut ; + + // rule RL_sinks_1_doPut + assign CAN_FIRE_RL_sinks_1_doPut = + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 && + CAN_FIRE_RL_sink_selected_1 ; + assign WILL_FIRE_RL_sinks_1_doPut = CAN_FIRE_RL_sinks_1_doPut ; + + // rule RL_split_1_putFirst + assign CAN_FIRE_RL_split_1_putFirst = + split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 && + split_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + + // rule RL_ssNoSynth_1_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = + ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_1_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = + MUX_split_1_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop || + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop && + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; + + // rule RL_split_1_putOther + assign CAN_FIRE_RL_split_1_putOther = + CAN_FIRE_RL_sinks_1_doPut && + (!split_1_doPut$wget[172] || + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) && + split_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; + + // rule RL_ssNoSynth_1_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = + ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_1_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_1_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = + ssNoSynth_1_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop || + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop && + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_2_warnDoPut + assign CAN_FIRE_RL_sinks_2_warnDoPut = + CAN_FIRE_RL_sink_selected_2 && + ((split_2_flitLeft == 8'd0) ? + !ssNoSynth_2_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_2_warnDoPut = CAN_FIRE_RL_sinks_2_warnDoPut ; + + // rule RL_sinks_2_doPut + assign CAN_FIRE_RL_sinks_2_doPut = + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 && + CAN_FIRE_RL_sink_selected_2 ; + assign WILL_FIRE_RL_sinks_2_doPut = CAN_FIRE_RL_sinks_2_doPut ; + + // rule RL_split_2_putFirst + assign CAN_FIRE_RL_split_2_putFirst = + split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 && + split_2_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + + // rule RL_ssNoSynth_2_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = + ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = + MUX_split_2_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop || + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop && + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; + + // rule RL_split_2_putOther + assign CAN_FIRE_RL_split_2_putOther = + CAN_FIRE_RL_sinks_2_doPut && + (!split_2_doPut$wget[172] || + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) && + split_2_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; + + // rule RL_ssNoSynth_2_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = + ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_2_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = + ssNoSynth_2_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop || + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop && + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_0_warnDoPut + assign CAN_FIRE_RL_sinks_1_0_warnDoPut = + CAN_FIRE_RL_sink_selected_3 && + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_0_warnDoPut = CAN_FIRE_RL_sinks_1_0_warnDoPut ; + + // rule RL_sinks_1_0_doPut + assign CAN_FIRE_RL_sinks_1_0_doPut = + msNoSynth_0_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_3 ; + assign WILL_FIRE_RL_sinks_1_0_doPut = CAN_FIRE_RL_sinks_1_0_doPut ; + + // rule RL_ifcs_0_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = + ifcs_0_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_0_doPut && + msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_0_doPut ; + + // rule RL_ifcs_0_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + ifcs_0_noRoute_inner_pendingReq$port1__read && + ifcs_0_noRouteRsp$FULL_N && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + + // rule __me_check_323 + assign CAN_FIRE___me_check_323 = 1'b1 ; + assign WILL_FIRE___me_check_323 = 1'b1 ; + + // rule __me_check_324 + assign CAN_FIRE___me_check_324 = 1'b1 ; + assign WILL_FIRE___me_check_324 = 1'b1 ; + + // rule __me_check_327 + assign CAN_FIRE___me_check_327 = 1'b1 ; + assign WILL_FIRE___me_check_327 = 1'b1 ; + + // rule RL_merged_0_awFlit + assign CAN_FIRE_RL_merged_0_awFlit = + msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut) && + merged_0_awff$FULL_N ; + assign WILL_FIRE_RL_merged_0_awFlit = CAN_FIRE_RL_merged_0_awFlit ; + + // rule RL_msNoSynth_0_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_0_awFlit || + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_0_awFlit && + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; + + // rule RL_merged_0_wFlit + assign CAN_FIRE_RL_merged_0_wFlit = + msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut) && + merged_0_wff$FULL_N ; + assign WILL_FIRE_RL_merged_0_wFlit = CAN_FIRE_RL_merged_0_wFlit ; + + // rule RL_msNoSynth_0_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_0_wFlit || + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_0_wFlit && + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; + + // rule RL_merged_0_genFirst + assign CAN_FIRE_RL_merged_0_genFirst = + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && + merged_0_doDrop$whas && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; + + // rule RL_merged_0_genOther + assign CAN_FIRE_RL_merged_0_genOther = + merged_0_wff$EMPTY_N && merged_0_doDrop$whas && + merged_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; + + // rule RL_ifcs_0_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_0_snk_warnDoPut = + ifcs_0_snk_putWire$whas && + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_snk_warnDoPut = + CAN_FIRE_RL_ifcs_0_snk_warnDoPut ; + + // rule RL_ifcs_0_snk_doPut + assign CAN_FIRE_RL_ifcs_0_snk_doPut = + msNoSynth_0_bNoSynth_buffer_ff$FULL_N && + ifcs_0_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_0_snk_doPut = CAN_FIRE_RL_ifcs_0_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = + msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_0_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek ; + + // rule RL_msNoSynth_0_bNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; + + // rule RL_proc_uncached_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + !proc$master1_b_canPut ; + assign WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = + CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut ; + + // rule RL_proc_uncached_bSynth_snk_doPut + assign CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut = + proc$RDY_master1_b_put && + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; + assign WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut = + CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; + + // rule RL_msNoSynth_0_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_0_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop || + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop && + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_warnDoPut = + CAN_FIRE_RL_sink_selected_4 && + !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_warnDoPut = CAN_FIRE_RL_sinks_1_1_warnDoPut ; + + // rule RL_sinks_1_1_doPut + assign CAN_FIRE_RL_sinks_1_1_doPut = + msNoSynth_1_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_4 ; + assign WILL_FIRE_RL_sinks_1_1_doPut = CAN_FIRE_RL_sinks_1_1_doPut ; + + // rule RL_ifcs_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = + ifcs_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_doPut && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_doPut ; + + // rule RL_ifcs_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_noRoute_inner_pendingReq$port1__read && + ifcs_1_noRouteRsp$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + + // rule __me_check_331 + assign CAN_FIRE___me_check_331 = 1'b1 ; + assign WILL_FIRE___me_check_331 = 1'b1 ; + + // rule __me_check_332 + assign CAN_FIRE___me_check_332 = 1'b1 ; + assign WILL_FIRE___me_check_332 = 1'b1 ; + + // rule __me_check_335 + assign CAN_FIRE___me_check_335 = 1'b1 ; + assign WILL_FIRE___me_check_335 = 1'b1 ; + + // rule RL_merged_1_genFirst + assign CAN_FIRE_RL_merged_1_genFirst = + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && + merged_1_doDrop$whas && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; + + // rule RL_merged_1_genOther + assign CAN_FIRE_RL_merged_1_genOther = + merged_1_wff$EMPTY_N && merged_1_doDrop$whas && + merged_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; + + // rule RL_ifcs_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_1_snk_warnDoPut = + ifcs_1_snk_putWire$whas && + !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_1_snk_warnDoPut ; + + // rule RL_ifcs_1_snk_doPut + assign CAN_FIRE_RL_ifcs_1_snk_doPut = + msNoSynth_1_bNoSynth_buffer_ff$FULL_N && + ifcs_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_1_snk_doPut = CAN_FIRE_RL_ifcs_1_snk_doPut ; + + // rule RL_msNoSynth_1_bNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = + msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek ; + + // rule RL_msNoSynth_1_bNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; + + // rule RL_msNoSynth_1_bNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; + + // rule RL_msNoSynth_1_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop || + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop && + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; // rule RL_ifcs_0_1_firstFlit assign CAN_FIRE_RL_ifcs_0_1_firstFlit = - proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_innerReq$FULL_N && ifcs_0_1_innerRoute$FULL_N && ifcs_0_1_state == 2'd0 && - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 == + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit = CAN_FIRE_RL_ifcs_0_1_firstFlit ; // rule RL_ifcs_0_1_followFlits assign CAN_FIRE_RL_ifcs_0_1_followFlits = - proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && - ifcs_0_1_state == 2'd1 ; + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_state == 2'd1 && + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ifcs_0_1_followFlits = CAN_FIRE_RL_ifcs_0_1_followFlits ; // rule RL_ifcs_0_1_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit = - ifcs_0_1_noRoute_flitCount == 9'd0 && proc$master1_arvalid && + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_noRoute_flitCount == 9'd0 && ifcs_0_1_state == 2'd0 && - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 != + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ; // rule RL_ifcs_0_1_drainFlits assign CAN_FIRE_RL_ifcs_0_1_drainFlits = - proc$master1_arvalid && ifcs_0_1_state == 2'd2 ; + (msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) && + ifcs_0_1_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_1_drainFlits = CAN_FIRE_RL_ifcs_0_1_drainFlits ; - // rule __me_check_205 - assign CAN_FIRE___me_check_205 = 1'b1 ; - assign WILL_FIRE___me_check_205 = 1'b1 ; - - // rule RL_ifcs_0_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = - msNoSynth_0_r_buffer_ff$FULL_N && ifcs_0_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; - - // rule RL_checkSinkReady_8 - assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; - - // rule RL_ifcs_1_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = - msNoSynth_1_r_buffer_ff$FULL_N && ifcs_1_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; - - // rule RL_checkSinkReady_9 - assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; - - // rule RL_craftReq_7 - assign CAN_FIRE_RL_craftReq_7 = - ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; - - // rule RL_craftReq_8 - assign CAN_FIRE_RL_craftReq_8 = - ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; - - // rule RL_craftReq_9 - assign CAN_FIRE_RL_craftReq_9 = - ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; - - // rule RL_arbitrate_3 - assign CAN_FIRE_RL_arbitrate_3 = - reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302 && - !state_1_1_1 ; - assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; - - // rule RL_source_selected_7 - assign CAN_FIRE_RL_source_selected_7 = - (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_0$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; - - // rule RL_burst_7 - assign CAN_FIRE_RL_burst_7 = - ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400 ; - assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; - - // rule RL_source_selected_8 - assign CAN_FIRE_RL_source_selected_8 = - (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_1_1$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; - - // rule RL_burst_8 - assign CAN_FIRE_RL_burst_8 = - ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436 ; - assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; - - // rule __me_check_244 - assign CAN_FIRE___me_check_244 = 1'b1 ; - assign WILL_FIRE___me_check_244 = 1'b1 ; - - // rule RL_source_selected_9 - assign CAN_FIRE_RL_source_selected_9 = - (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_2$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; - - // rule RL_burst_9 - assign CAN_FIRE_RL_burst_9 = - ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472 ; - assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; - - // rule __me_check_242 - assign CAN_FIRE___me_check_242 = 1'b1 ; - assign WILL_FIRE___me_check_242 = 1'b1 ; - - // rule __me_check_246 - assign CAN_FIRE___me_check_246 = 1'b1 ; - assign WILL_FIRE___me_check_246 = 1'b1 ; - - // rule RL_sink_selected_8 - assign CAN_FIRE_RL_sink_selected_8 = - !CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && - flitToSink_1_1_0$whas ; - assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; - - // rule RL_sink_selected_9 - assign CAN_FIRE_RL_sink_selected_9 = - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && - flitToSink_1_1_1_1$whas ; - assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; - - // rule __me_check_248 - assign CAN_FIRE___me_check_248 = 1'b1 ; - assign WILL_FIRE___me_check_248 = 1'b1 ; - - // rule RL_ifcs_0_1_forwardRsp - assign CAN_FIRE_RL_ifcs_0_1_forwardRsp = - msNoSynth_0_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_8 && - !ifcs_0_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_1_forwardRsp = CAN_FIRE_RL_ifcs_0_1_forwardRsp ; - - // rule RL_msNoSynth_0_r_forwardFlit - assign CAN_FIRE_RL_msNoSynth_0_r_forwardFlit = - !tmp0_r_buffer_ff$FULL_N || - msNoSynth_0_r_buffer_firstValid$Q_OUT && - (msNoSynth_0_r_buffer_ff$EMPTY_N || - msNoSynth_0_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_0_r_forwardFlit = - CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; - - // rule RL_tmp0_r_forwardFlit - assign CAN_FIRE_RL_tmp0_r_forwardFlit = - tmp0_r_buffer_firstValid$Q_OUT && - (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_tmp0_r_forwardFlit = CAN_FIRE_RL_tmp0_r_forwardFlit ; - - // rule RL_tmp0_r_dropFlit - assign CAN_FIRE_RL_tmp0_r_dropFlit = - (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) && - proc$master1_rready ; - assign WILL_FIRE_RL_tmp0_r_dropFlit = CAN_FIRE_RL_tmp0_r_dropFlit ; - - // rule RL_tmp0_r_buffer_enqueue - assign CAN_FIRE_RL_tmp0_r_buffer_enqueue = - tmp0_r_buffer_enqw$whas && - (!CAN_FIRE_RL_tmp0_r_dropFlit || tmp0_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp0_r_buffer_enqueue = - CAN_FIRE_RL_tmp0_r_buffer_enqueue ; - - // rule RL_tmp0_r_buffer_dequeue - assign CAN_FIRE_RL_tmp0_r_buffer_dequeue = - CAN_FIRE_RL_tmp0_r_dropFlit && tmp0_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp0_r_buffer_dequeue = - CAN_FIRE_RL_tmp0_r_buffer_dequeue ; - - // rule RL_msNoSynth_0_r_dropFlit - assign CAN_FIRE_RL_msNoSynth_0_r_dropFlit = - (msNoSynth_0_r_buffer_ff$EMPTY_N || - msNoSynth_0_r_buffer_enqw$whas) && - tmp0_r_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_msNoSynth_0_r_dropFlit = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; - - // rule RL_msNoSynth_0_r_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue = - msNoSynth_0_r_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_0_r_dropFlit || - msNoSynth_0_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; - - // rule RL_msNoSynth_0_r_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit && - msNoSynth_0_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; - - // rule RL_ifcs_0_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = - x_port1__read__h72781 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && - (x_port1__read__h72781 != 9'd1 || proc$master1_arvalid) ; - assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; - - // rule __me_check_203 - assign CAN_FIRE___me_check_203 = 1'b1 ; - assign WILL_FIRE___me_check_203 = 1'b1 ; - - // rule __me_check_204 - assign CAN_FIRE___me_check_204 = 1'b1 ; - assign WILL_FIRE___me_check_204 = 1'b1 ; - - // rule __me_check_207 - assign CAN_FIRE___me_check_207 = 1'b1 ; - assign WILL_FIRE___me_check_207 = 1'b1 ; - - // rule RL_msNoSynth_0_ar_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; - - // rule RL_tmp0_ar_forwardReady - assign CAN_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_1_forwardRsp - assign CAN_FIRE_RL_ifcs_1_1_forwardRsp = - msNoSynth_1_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_9 && - !ifcs_1_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_1_forwardRsp = CAN_FIRE_RL_ifcs_1_1_forwardRsp ; - - // rule RL_msNoSynth_1_r_forwardFlit - assign CAN_FIRE_RL_msNoSynth_1_r_forwardFlit = - msNoSynth_1_r_buffer_firstValid$Q_OUT && - (msNoSynth_1_r_buffer_ff$EMPTY_N || - msNoSynth_1_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_1_r_forwardFlit = - CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; - - // rule RL_msNoSynth_1_r_dropFlit - assign CAN_FIRE_RL_msNoSynth_1_r_dropFlit = - (msNoSynth_1_r_buffer_ff$EMPTY_N || - msNoSynth_1_r_buffer_enqw$whas) && - debug_module$master_rready ; - assign WILL_FIRE_RL_msNoSynth_1_r_dropFlit = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; - - // rule RL_msNoSynth_1_r_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue = - msNoSynth_1_r_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_1_r_dropFlit || - msNoSynth_1_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; - - // rule RL_msNoSynth_1_r_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit && - msNoSynth_1_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; - - // rule RL_ifcs_1_firstFlit - assign CAN_FIRE_RL_ifcs_1_firstFlit = - debug_module$master_wvalid && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_innerReq$FULL_N && - ifcs_1_innerRoute$FULL_N && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - ifcs_1_state == 2'd0 && - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 == - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; - - // rule RL_ifcs_1_followFlits - assign CAN_FIRE_RL_ifcs_1_followFlits = - debug_module$master_wvalid && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_innerReq$FULL_N && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - ifcs_1_state == 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; - - // rule RL_ifcs_1_nonRoutableFlit - assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350 && - ifcs_1_state == 2'd0 && - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 != - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = - CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; - - // rule RL_ifcs_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_noRoute_inner_pendingReq$port1__read && - ifcs_1_noRouteRsp$FULL_N && - debug_module$master_wvalid ; - assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; - - // rule RL_ifcs_1_drainFlits - assign CAN_FIRE_RL_ifcs_1_drainFlits = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - debug_module$master_wvalid && - ifcs_1_state == 2'd2 ; - assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; - - // rule __me_check_163 - assign CAN_FIRE___me_check_163 = 1'b1 ; - assign WILL_FIRE___me_check_163 = 1'b1 ; - - // rule __me_check_164 - assign CAN_FIRE___me_check_164 = 1'b1 ; - assign WILL_FIRE___me_check_164 = 1'b1 ; - - // rule __me_check_165 - assign CAN_FIRE___me_check_165 = 1'b1 ; - assign WILL_FIRE___me_check_165 = 1'b1 ; - - // rule __me_check_167 - assign CAN_FIRE___me_check_167 = 1'b1 ; - assign WILL_FIRE___me_check_167 = 1'b1 ; - - // rule RL_merged_1_genFirst - assign CAN_FIRE_RL_merged_1_genFirst = - debug_module$master_awvalid && debug_module$master_wvalid && - merged_1_doDrop$whas && - merged_1_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; - - // rule RL_msNoSynth_1_aw_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; - - // rule RL_merged_1_genOther - assign CAN_FIRE_RL_merged_1_genOther = - debug_module$master_wvalid && merged_1_doDrop$whas && - merged_1_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; - - // rule RL_msNoSynth_1_w_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_1_firstFlit - assign CAN_FIRE_RL_ifcs_1_1_firstFlit = - debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && - ifcs_1_1_innerRoute$FULL_N && - ifcs_1_1_state == 2'd0 && - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 == - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; - - // rule RL_ifcs_1_1_followFlits - assign CAN_FIRE_RL_ifcs_1_1_followFlits = - debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && - ifcs_1_1_state == 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_followFlits = - CAN_FIRE_RL_ifcs_1_1_followFlits ; - - // rule RL_ifcs_1_1_nonRoutableFlit - assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = - ifcs_1_1_noRoute_flitCount == 9'd0 && - debug_module$master_arvalid && - ifcs_1_1_state == 2'd0 && - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 != - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = - CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; - - // rule RL_ifcs_1_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = - x_port1__read__h75154 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && - (x_port1__read__h75154 != 9'd1 || debug_module$master_arvalid) ; - assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; - - // rule RL_ifcs_1_1_drainFlits - assign CAN_FIRE_RL_ifcs_1_1_drainFlits = - debug_module$master_arvalid && ifcs_1_1_state == 2'd2 ; - assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; - - // rule __me_check_210 - assign CAN_FIRE___me_check_210 = 1'b1 ; - assign WILL_FIRE___me_check_210 = 1'b1 ; - - // rule __me_check_211 - assign CAN_FIRE___me_check_211 = 1'b1 ; - assign WILL_FIRE___me_check_211 = 1'b1 ; - - // rule __me_check_212 - assign CAN_FIRE___me_check_212 = 1'b1 ; - assign WILL_FIRE___me_check_212 = 1'b1 ; - - // rule __me_check_214 - assign CAN_FIRE___me_check_214 = 1'b1 ; - assign WILL_FIRE___me_check_214 = 1'b1 ; - - // rule RL_msNoSynth_1_ar_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + // rule __me_check_384 + assign CAN_FIRE___me_check_384 = 1'b1 ; + assign WILL_FIRE___me_check_384 = 1'b1 ; // rule RL_ifcs_0_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_1_firstFlit_1 = - uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && + ifcs_0_1_rspBack$FULL_N && ifcs_0_1_routeBack$FULL_N && !ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit_1 = @@ -6141,29 +7599,37 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ifcs_0_1_followFlits_1 assign CAN_FIRE_RL_ifcs_0_1_followFlits_1 = - uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && + ifcs_0_1_rspBack$FULL_N && ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_followFlits_1 = CAN_FIRE_RL_ifcs_0_1_followFlits_1 ; - // rule __me_check_217 - assign CAN_FIRE___me_check_217 = 1'b1 ; - assign WILL_FIRE___me_check_217 = 1'b1 ; + // rule __me_check_396 + assign CAN_FIRE___me_check_396 = 1'b1 ; + assign WILL_FIRE___me_check_396 = 1'b1 ; - // rule RL_ssNoSynth_0_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; - assign WILL_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; + // rule RL_ssNoSynth_0_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut && + (!ssNoSynth_0_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; - // rule RL_ug_uncached_mem_shim_master_u_r_doPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = - uncached_mem_shim_rff$FULL_N && - ug_uncached_mem_shim_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + // rule RL_ssNoSynth_0_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; // rule RL_ifcs_1_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_1_firstFlit_1 = - plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + ifcs_1_1_rspBack$FULL_N && ifcs_1_1_routeBack$FULL_N && !ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_firstFlit_1 = @@ -6171,18 +7637,124 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ifcs_1_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_1_followFlits_1 = - plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + ifcs_1_1_rspBack$FULL_N && ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_1_followFlits_1 ; - // rule __me_check_219 - assign CAN_FIRE___me_check_219 = 1'b1 ; - assign WILL_FIRE___me_check_219 = 1'b1 ; + // rule __me_check_398 + assign CAN_FIRE___me_check_398 = 1'b1 ; + assign WILL_FIRE___me_check_398 = 1'b1 ; - // rule RL_ssNoSynth_1_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_1_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut && + (!ssNoSynth_1_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_0_warnDoPut_1 + assign CAN_FIRE_RL_sinks_1_0_warnDoPut_1 = + CAN_FIRE_RL_sink_selected_5 && + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_0_warnDoPut_1 = + CAN_FIRE_RL_sinks_1_0_warnDoPut_1 ; + + // rule RL_sinks_1_0_doPut_1 + assign CAN_FIRE_RL_sinks_1_0_doPut_1 = + ssNoSynth_0_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_5 ; + assign WILL_FIRE_RL_sinks_1_0_doPut_1 = CAN_FIRE_RL_sinks_1_0_doPut_1 ; + + // rule RL_ssNoSynth_0_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = + ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_0_doPut_1) ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + !uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_arSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = + uncached_mem_shim_arff$EMPTY_N && + uncached_mem_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; + + // rule RL_slave_vector_0_arSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut = + uncached_mem_shim_arff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_0_doPut_1 && + (!CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop || + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop && + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_warnDoPut_1 + assign CAN_FIRE_RL_sinks_1_1_warnDoPut_1 = + CAN_FIRE_RL_sink_selected_6 && + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_warnDoPut_1 = + CAN_FIRE_RL_sinks_1_1_warnDoPut_1 ; + + // rule RL_sinks_1_1_doPut_1 + assign CAN_FIRE_RL_sinks_1_1_doPut_1 = + ssNoSynth_1_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_6 ; + assign WILL_FIRE_RL_sinks_1_1_doPut_1 = CAN_FIRE_RL_sinks_1_1_doPut_1 ; + + // rule RL_ssNoSynth_1_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = + ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_1_doPut_1) ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = @@ -6198,27 +7770,752 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; + // rule RL_ssNoSynth_1_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_1_doPut_1 && + (!CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop || + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop && + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_2_warnDoPut + assign CAN_FIRE_RL_sinks_1_2_warnDoPut = + CAN_FIRE_RL_sink_selected_7 && + !ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_2_warnDoPut = CAN_FIRE_RL_sinks_1_2_warnDoPut ; + + // rule RL_sinks_1_2_doPut + assign CAN_FIRE_RL_sinks_1_2_doPut = + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_7 ; + assign WILL_FIRE_RL_sinks_1_2_doPut = CAN_FIRE_RL_sinks_1_2_doPut ; + + // rule RL_ssNoSynth_2_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = + ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_2_doPut) ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = + proc$debug_module_mem_server_bvalid && + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_2_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_2_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit && + !ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_2_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_2_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_2_doPut && + (!CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop || + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop && + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; + + // rule RL_ssNoSynth_2_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = + proc$debug_module_mem_server_rvalid && + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_2_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_2_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit && + !ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_2_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut ; + + // rule RL_ifcs_2_firstFlit + assign CAN_FIRE_RL_ifcs_2_firstFlit = + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && + ifcs_2_rspBack$FULL_N && + ifcs_2_routeBack$FULL_N && + !ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + + // rule RL_ifcs_2_followFlits + assign CAN_FIRE_RL_ifcs_2_followFlits = + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && + ifcs_2_rspBack$FULL_N && + ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + + // rule __me_check_341 + assign CAN_FIRE___me_check_341 = 1'b1 ; + assign WILL_FIRE___me_check_341 = 1'b1 ; + + // rule RL_ssNoSynth_2_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut && + (!ssNoSynth_2_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; + // rule RL_ifcs_2_1_firstFlit assign CAN_FIRE_RL_ifcs_2_1_firstFlit = - proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && + ifcs_2_1_rspBack$FULL_N && ifcs_2_1_routeBack$FULL_N && !ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_firstFlit = CAN_FIRE_RL_ifcs_2_1_firstFlit ; // rule RL_ifcs_2_1_followFlits assign CAN_FIRE_RL_ifcs_2_1_followFlits = - proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && + ifcs_2_1_rspBack$FULL_N && ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_followFlits = CAN_FIRE_RL_ifcs_2_1_followFlits ; - // rule __me_check_221 - assign CAN_FIRE___me_check_221 = 1'b1 ; - assign WILL_FIRE___me_check_221 = 1'b1 ; + // rule __me_check_400 + assign CAN_FIRE___me_check_400 = 1'b1 ; + assign WILL_FIRE___me_check_400 = 1'b1 ; - // rule RL_ssNoSynth_2_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_2_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut && + (!ssNoSynth_2_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_0_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_0_warnDoPut = + CAN_FIRE_RL_sink_selected_8 && + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_0_warnDoPut = + CAN_FIRE_RL_sinks_1_1_0_warnDoPut ; + + // rule RL_sinks_1_1_0_doPut + assign CAN_FIRE_RL_sinks_1_1_0_doPut = + msNoSynth_0_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_8 ; + assign WILL_FIRE_RL_sinks_1_1_0_doPut = CAN_FIRE_RL_sinks_1_1_0_doPut ; + + // rule RL_ifcs_0_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + ifcs_0_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_0_doPut && + msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_0_doPut ; + + // rule RL_ifcs_0_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + x__h95023 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && + (x__h95023 != 9'd1 || msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + + // rule __me_check_382 + assign CAN_FIRE___me_check_382 = 1'b1 ; + assign WILL_FIRE___me_check_382 = 1'b1 ; + + // rule __me_check_383 + assign CAN_FIRE___me_check_383 = 1'b1 ; + assign WILL_FIRE___me_check_383 = 1'b1 ; + + // rule __me_check_386 + assign CAN_FIRE___me_check_386 = 1'b1 ; + assign WILL_FIRE___me_check_386 = 1'b1 ; + + // rule RL_msNoSynth_0_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut && + (!msNoSynth_0_arNoSynth_buffer_dequeueing$whas || + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = + msNoSynth_0_arNoSynth_buffer_dequeueing$whas && + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; + + // rule RL_ifcs_0_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut = + ifcs_0_1_snk_putWire$whas && + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut ; + + // rule RL_ifcs_0_1_snk_doPut + assign CAN_FIRE_RL_ifcs_0_1_snk_doPut = + msNoSynth_0_rNoSynth_buffer_ff$FULL_N && + ifcs_0_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_0_1_snk_doPut = CAN_FIRE_RL_ifcs_0_1_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = + msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_0_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek ; + + // rule RL_msNoSynth_0_rNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; + + // rule RL_proc_uncached_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + !proc$master1_r_canPut ; + assign WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = + CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut ; + + // rule RL_proc_uncached_rSynth_snk_doPut + assign CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut = + proc$RDY_master1_r_put && + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; + assign WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut = + CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; + + // rule RL_msNoSynth_0_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_0_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop || + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop && + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_1_warnDoPut = + CAN_FIRE_RL_sink_selected_9 && + !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_1_warnDoPut = + CAN_FIRE_RL_sinks_1_1_1_warnDoPut ; + + // rule RL_sinks_1_1_1_doPut + assign CAN_FIRE_RL_sinks_1_1_1_doPut = + msNoSynth_1_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_9 ; + assign WILL_FIRE_RL_sinks_1_1_1_doPut = CAN_FIRE_RL_sinks_1_1_1_doPut ; + + // rule RL_ifcs_1_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + ifcs_1_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_1_doPut && + msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_1_doPut ; + + // rule RL_ifcs_1_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut = + ifcs_1_1_snk_putWire$whas && + !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut ; + + // rule RL_ifcs_1_1_snk_doPut + assign CAN_FIRE_RL_ifcs_1_1_snk_doPut = + msNoSynth_1_rNoSynth_buffer_ff$FULL_N && + ifcs_1_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_1_1_snk_doPut = CAN_FIRE_RL_ifcs_1_1_snk_doPut ; + + // rule RL_msNoSynth_1_rNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = + msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_1_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek ; + + // rule RL_msNoSynth_1_rNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; + + // rule RL_msNoSynth_1_awNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = + debug_module$master_awvalid && + msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_awNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit && + !msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_awNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = + msNoSynth_1_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_wNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = + debug_module$master_wvalid && + msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_wNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit && + !msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_wNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = + msNoSynth_1_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_arNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = + debug_module$master_arvalid && + msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_arNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit && + !msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_arNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = + msNoSynth_1_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_rNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; + + // rule RL_msNoSynth_1_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_1_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop || + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop && + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; + + // rule RL_merged_1_awFlit + assign CAN_FIRE_RL_merged_1_awFlit = + msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut) && + merged_1_awff$FULL_N ; + assign WILL_FIRE_RL_merged_1_awFlit = CAN_FIRE_RL_merged_1_awFlit ; + + // rule RL_msNoSynth_1_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_1_awFlit || + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_1_awFlit && + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; + + // rule RL_merged_1_wFlit + assign CAN_FIRE_RL_merged_1_wFlit = + msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut) && + merged_1_wff$FULL_N ; + assign WILL_FIRE_RL_merged_1_wFlit = CAN_FIRE_RL_merged_1_wFlit ; + + // rule RL_msNoSynth_1_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_1_wFlit || + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_1_wFlit && + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; + + // rule RL_ifcs_1_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_1_firstFlit = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_innerRoute$FULL_N && + ifcs_1_1_state == 2'd0 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + + // rule RL_ifcs_1_1_followFlits + assign CAN_FIRE_RL_ifcs_1_1_followFlits = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_state == 2'd1 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits = + CAN_FIRE_RL_ifcs_1_1_followFlits ; + + // rule RL_ifcs_1_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_noRoute_flitCount == 9'd0 && + ifcs_1_1_state == 2'd0 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; + + // rule RL_ifcs_1_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + x__h97622 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && + (x__h97622 != 9'd1 || msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_1_drainFlits = + (msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) && + ifcs_1_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; + + // rule __me_check_390 + assign CAN_FIRE___me_check_390 = 1'b1 ; + assign WILL_FIRE___me_check_390 = 1'b1 ; + + // rule __me_check_391 + assign CAN_FIRE___me_check_391 = 1'b1 ; + assign WILL_FIRE___me_check_391 = 1'b1 ; + + // rule __me_check_392 + assign CAN_FIRE___me_check_392 = 1'b1 ; + assign WILL_FIRE___me_check_392 = 1'b1 ; + + // rule __me_check_394 + assign CAN_FIRE___me_check_394 = 1'b1 ; + assign WILL_FIRE___me_check_394 = 1'b1 ; + + // rule RL_msNoSynth_1_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut && + (!msNoSynth_1_arNoSynth_buffer_dequeueing$whas || + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = + msNoSynth_1_arNoSynth_buffer_dequeueing$whas && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; + + // rule RL_cached_mem_master_awSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = + cached_mem_master_awSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_awSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop = + cached_mem_master_awSynth_src_dropWire$whas && + tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop && + !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; + + // rule RL_cached_mem_master_wSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = + cached_mem_master_wSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_wSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop = + cached_mem_master_wSynth_src_dropWire$whas && + tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop && + !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; + + // rule RL_cached_mem_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && + tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut ; + + // rule RL_cached_mem_master_bSynth_snk_doPut + assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut = + cpu_imem_master_bvalid && + !tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; + + // rule RL_tagController_tmp_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && + tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_b_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + !tagController_tmp_shimMaster_bff_rv[8] && + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; + + // rule RL_cached_mem_master_arSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = + cached_mem_master_arSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_arSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop = + cached_mem_master_arSynth_src_dropWire$whas && + tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop && + !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; + + // rule RL_cached_mem_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && + tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut ; + + // rule RL_cached_mem_master_rSynth_snk_doPut + assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut = + cpu_imem_master_rvalid && + !tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; + + // rule RL_tagController_tmp_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && + tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_r_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + !tagController_tmp_shimMaster_rff_rv[73] && + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; + + // rule RL_tagController_tmp_passMemoryResponseWrite + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + tagController_tmp_shimMaster_bff_rv$port1__read[8] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && + !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_tagController_tmp_passMemoryResponseRead + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = + tagController_tmp_shimMaster_rff_rv$port1__read[73] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_tagController_tmp_propagateReset + assign CAN_FIRE_RL_tagController_tmp_propagateReset = + !tagController_tmp_reset_done ; + assign WILL_FIRE_RL_tagController_tmp_propagateReset = + CAN_FIRE_RL_tagController_tmp_propagateReset ; // inputs to muxes for submodule ports assign MUX_activeSource_0$write_1__SEL_1 = @@ -6325,31 +8622,37 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_0_innerRoute$D_OUT[2] ; assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && - uncached_mem_shim_rff$D_OUT[1] ; + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_0_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits ; assign MUX_ifcs_0_state$write_1__SEL_1 = - MUX_ifcs_0_state$write_1__PSEL_1 && proc$master1_wlast ; + MUX_ifcs_0_state$write_1__PSEL_1 && + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; assign MUX_ifcs_0_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast ; + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_0_state$write_1__SEL_3 = - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast ; + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_1_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits ; assign MUX_ifcs_1_state$write_1__SEL_1 = - MUX_ifcs_1_state$write_1__PSEL_1 && debug_module$master_wlast ; + MUX_ifcs_1_state$write_1__PSEL_1 && + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; assign MUX_ifcs_1_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast ; + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_1_state$write_1__SEL_3 = WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - !debug_module$master_wlast ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_2_1_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_2_1_followFlits && - proc$debug_module_mem_server_rlast ; + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_proc$start_1__SEL_1 = WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 ; @@ -6377,41 +8680,19 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] ; assign MUX_activeSource_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign MUX_activeSource_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign MUX_activeSource_1_1_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign MUX_activeSource_1_1_1_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign MUX_activeSource_1_1_2$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 ; - assign MUX_merged_0_flitLeft$write_1__VAL_1 = merged_0_flitLeft - 8'd1 ; - assign MUX_merged_1_flitLeft$write_1__VAL_1 = merged_1_flitLeft - 8'd1 ; - always@(MUX_flitToSink_1_0$wset_1__SEL_1 or - MUX_flitToSink_1_0$wset_1__SEL_4 or - ifcs_0_rspBack$D_OUT or - MUX_flitToSink_1_0$wset_1__SEL_2 or - MUX_flitToSink_1_0$wset_1__SEL_5 or - ifcs_1_rspBack$D_OUT or - MUX_flitToSink_1_0$wset_1__SEL_3 or - MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) - begin - case (1'b1) // synopsys parallel_case - MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; - MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; - MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; - default: MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = - 6'b101010 /* unspecified value */ ; - endcase - end + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; always@(MUX_flitToSink_1_1_0$wset_1__SEL_1 or MUX_flitToSink_1_1_0$wset_1__SEL_4 or ifcs_0_1_rspBack$D_OUT or @@ -6424,37 +8705,34 @@ module mkCoreW(RST_N_dm_power_on_reset, case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_0$wset_1__SEL_1 || MUX_flitToSink_1_1_0$wset_1__SEL_4: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_0_1_rspBack$D_OUT; + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_2 || MUX_flitToSink_1_1_0$wset_1__SEL_5: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_1_1_rspBack$D_OUT; + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_3 || MUX_flitToSink_1_1_0$wset_1__SEL_6: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_2_1_rspBack$D_OUT; - default: MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; + default: MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(MUX_flitToSink_1_1$wset_1__SEL_1 or - MUX_flitToSink_1_1$wset_1__SEL_4 or + always@(MUX_flitToSink_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_0$wset_1__SEL_4 or ifcs_0_rspBack$D_OUT or - MUX_flitToSink_1_1$wset_1__SEL_2 or - MUX_flitToSink_1_1$wset_1__SEL_5 or + MUX_flitToSink_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_0$wset_1__SEL_5 or ifcs_1_rspBack$D_OUT or - MUX_flitToSink_1_1$wset_1__SEL_3 or - MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + MUX_flitToSink_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) begin case (1'b1) // synopsys parallel_case - MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; - MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; - MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; - default: MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = + MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = 6'b101010 /* unspecified value */ ; endcase end @@ -6470,27 +8748,46 @@ module mkCoreW(RST_N_dm_power_on_reset, case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1_1$wset_1__SEL_4: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_0_1_rspBack$D_OUT; + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1_1_1$wset_1__SEL_5: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_1_1_rspBack$D_OUT; + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1_1_1$wset_1__SEL_6: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_2_1_rspBack$D_OUT; - default: MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; + default: MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + always@(MUX_flitToSink_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = + 6'b101010 /* unspecified value */ ; + endcase + end + assign MUX_merged_0_flitLeft$write_1__VAL_2 = merged_0_flitLeft - 8'd1 ; + assign MUX_merged_1_flitLeft$write_1__VAL_2 = merged_1_flitLeft - 8'd1 ; assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = rg_hart0_reset_delay - 8'd1 ; assign MUX_split_0_flitLeft$write_1__VAL_1 = split_0_flitLeft - 8'd1 ; assign MUX_split_1_flitLeft$write_1__VAL_1 = split_1_flitLeft - 8'd1 ; assign MUX_split_2_flitLeft$write_1__VAL_1 = split_2_flitLeft - 8'd1 ; assign MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1 = - { tmp__h8366[39:3], + { tmp__h8169[39:3], 4'd0, tagController_tmp_awreqff$D_OUT[97:93], 3'd1, @@ -6521,48 +8818,51 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_rff_rv$port1__read[67:3] } ; // inlined wires - assign tmp0_aw_dwReady$whas = - proc$master1_awvalid && CAN_FIRE_RL_merged_0_genFirst ; - assign tmp0_w_dwReady$whas = - proc$master1_wvalid && msNoSynth_0_w_dwReady$whas ; - assign tmp0_b_buffer_enqw$wget = - msNoSynth_0_b_buffer_ff$EMPTY_N ? - msNoSynth_0_b_buffer_ff$D_OUT : - msNoSynth_0_b_buffer_enqw$wget ; - assign tmp0_b_buffer_enqw$whas = - WILL_FIRE_RL_msNoSynth_0_b_forwardFlit && - tmp0_b_buffer_ff$FULL_N ; - assign tmp0_ar_dwReady$whas = - proc$master1_arvalid && msNoSynth_0_ar_dwReady$whas ; - assign tmp0_r_buffer_enqw$wget = - { x_rid__h25044, - x_rdata__h25045, - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[3:2] : - msNoSynth_0_r_buffer_enqw$wget[3:2], - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[1] : - msNoSynth_0_r_buffer_enqw$wget[1], - 1'd0 } ; - assign tmp0_r_buffer_enqw$whas = - WILL_FIRE_RL_msNoSynth_0_r_forwardFlit && - tmp0_r_buffer_ff$FULL_N ; - assign ug_uncached_mem_shim_master_u_aw_peekWire$wget = + assign proc_uncached_wSynth_src_peekWire$wget = + { proc$master1_w_peek[73:1], 1'd0 } ; + assign proc_uncached_bSynth_snk_putWire$wget = + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_bNoSynth_buffer_ff$D_OUT : + msNoSynth_0_bNoSynth_buffer_enqw$wget ; + assign proc_uncached_rSynth_snk_putWire$wget = + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_rNoSynth_buffer_ff$D_OUT : + msNoSynth_0_rNoSynth_buffer_enqw$wget ; + assign uncached_mem_master_awSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_awff$D_OUT } ; - assign ug_uncached_mem_shim_master_u_b_putWire$wget = + assign uncached_mem_master_bSynth_snk_putWire$wget = { cpu_dmem_master_bid, cpu_dmem_master_bresp } ; - assign ug_uncached_mem_shim_master_u_b_putWire$whas = + assign uncached_mem_master_bSynth_snk_putWire$whas = cpu_dmem_master_bvalid && uncached_mem_shim_bff$FULL_N ; - assign ug_uncached_mem_shim_master_u_ar_peekWire$wget = + assign uncached_mem_master_arSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_arff$D_OUT } ; - assign ug_uncached_mem_shim_master_u_r_putWire$wget = + assign uncached_mem_master_rSynth_snk_putWire$wget = { cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast } ; - assign ug_uncached_mem_shim_master_u_r_putWire$whas = + assign uncached_mem_master_rSynth_snk_putWire$whas = cpu_dmem_master_rvalid && uncached_mem_shim_rff$FULL_N ; assign tagController_tmp_ug_slave_u_aw_putWire$wget = + tmp2_awNoSynth_buffer_ff$EMPTY_N ? + tmp2_awNoSynth_buffer_ff$D_OUT : + tmp2_awNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_slave_u_w_putWire$wget = + tmp2_wNoSynth_buffer_ff$EMPTY_N ? + tmp2_wNoSynth_buffer_ff$D_OUT : + tmp2_wNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_slave_u_ar_putWire$wget = + tmp2_arNoSynth_buffer_ff$EMPTY_N ? + tmp2_arNoSynth_buffer_ff$D_OUT : + tmp2_arNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_master_u_b_putWire$wget = + { cpu_imem_master_bid, cpu_imem_master_bresp } ; + assign tagController_tmp_ug_master_u_r_putWire$wget = + { cpu_imem_master_rid, + cpu_imem_master_rdata, + cpu_imem_master_rresp, + cpu_imem_master_rlast } ; + assign tmp2_awNoSynth_buffer_enqw$wget = { proc$master0_awid, proc$master0_awaddr, proc$master0_awlen, @@ -6573,12 +8873,16 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awprot, proc$master0_awqos, proc$master0_awregion } ; - assign tagController_tmp_ug_slave_u_w_putWire$wget = + assign tmp2_wNoSynth_buffer_enqw$wget = { proc$master0_wdata, proc$master0_wstrb, proc$master0_wlast, proc$master0_wuser } ; - assign tagController_tmp_ug_slave_u_ar_putWire$wget = + assign tmp2_bNoSynth_src_peekWire$wget = + tmp2_bNoSynth_buffer_ff$EMPTY_N ? + tmp2_bNoSynth_buffer_ff$D_OUT : + tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; + assign tmp2_arNoSynth_buffer_enqw$wget = { proc$master0_arid, proc$master0_araddr, proc$master0_arlen, @@ -6589,115 +8893,142 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arprot, proc$master0_arqos, proc$master0_arregion } ; - assign tagController_tmp_ug_master_u_b_putWire$wget = - { cpu_imem_master_bid, cpu_imem_master_bresp } ; - assign tagController_tmp_ug_master_u_b_putWire$whas = - cpu_imem_master_bvalid && - !tagController_tmp_shimMaster_bff_rv[8] ; - assign tagController_tmp_ug_master_u_r_putWire$wget = - { cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast } ; - assign tagController_tmp_ug_master_u_r_putWire$whas = - cpu_imem_master_rvalid && - !tagController_tmp_shimMaster_rff_rv[73] ; - assign tmp2_b_buffer_enqw$wget = - tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; - assign tmp2_r_buffer_enqw$wget = - tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; - assign msNoSynth_0_w_dwReady$whas = - WILL_FIRE_RL_merged_0_genOther || - WILL_FIRE_RL_merged_0_genFirst ; - assign msNoSynth_0_b_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ? - ifcs_0_noRouteRsp$D_OUT : - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_0_b_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_0_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_0_forwardRsp ; - assign msNoSynth_0_ar_dwReady$whas = - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && - x_port1__read__h72781 == 9'd1 || - WILL_FIRE_RL_ifcs_0_1_drainFlits || - WILL_FIRE_RL_ifcs_0_1_followFlits || - WILL_FIRE_RL_ifcs_0_1_firstFlit ; - assign msNoSynth_0_r_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ? - ifcs_0_1_noRouteRsp$D_OUT : - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_0_r_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_0_1_forwardRsp ; - assign msNoSynth_1_w_dwReady$whas = - WILL_FIRE_RL_merged_1_genOther || - WILL_FIRE_RL_merged_1_genFirst ; - assign msNoSynth_1_b_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ? - ifcs_1_noRouteRsp$D_OUT : - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_1_b_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_1_forwardRsp ; - assign msNoSynth_1_ar_dwReady$whas = - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && - x_port1__read__h75154 == 9'd1 || - WILL_FIRE_RL_ifcs_1_1_drainFlits || - WILL_FIRE_RL_ifcs_1_1_followFlits || - WILL_FIRE_RL_ifcs_1_1_firstFlit ; - assign msNoSynth_1_r_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ? - ifcs_1_1_noRouteRsp$D_OUT : - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_1_r_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_1_1_forwardRsp ; - assign ssNoSynth_0_w_buffer_enqw$whas = + assign tmp2_rNoSynth_src_peekWire$wget = + tmp2_rNoSynth_buffer_ff$EMPTY_N ? + tmp2_rNoSynth_buffer_ff$D_OUT : + tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; + assign slave_vector_0_awSynth_snk_putWire$wget = + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_awNoSynth_buffer_ff$D_OUT : + split_0_doPut$wget[171:74] ; + assign slave_vector_0_wSynth_snk_putWire$wget = + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_wNoSynth_buffer_ff$D_OUT : + split_0_doPut$wget[73:0] ; + assign slave_vector_0_arSynth_snk_putWire$wget = + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_0_arNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_bNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_0_doPut ? + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 : + ifcs_0_noRouteRsp$D_OUT ; + assign msNoSynth_0_rNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_0_doPut ? + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 : + ifcs_0_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_awNoSynth_buffer_enqw$wget = + { debug_module$master_awid, + debug_module$master_awaddr, + debug_module$master_awlen, + debug_module$master_awsize, + debug_module$master_awburst, + debug_module$master_awlock, + debug_module$master_awcache, + debug_module$master_awprot, + debug_module$master_awqos, + debug_module$master_awregion } ; + assign msNoSynth_1_wNoSynth_buffer_enqw$wget = + { debug_module$master_wdata, + debug_module$master_wstrb, + debug_module$master_wlast, + debug_module$master_wuser } ; + assign msNoSynth_1_bNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_doPut ? + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 : + ifcs_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_bNoSynth_src_peekWire$wget = + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_bNoSynth_buffer_ff$D_OUT : + msNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_arNoSynth_buffer_enqw$wget = + { debug_module$master_arid, + debug_module$master_araddr, + debug_module$master_arlen, + debug_module$master_arsize, + debug_module$master_arburst, + debug_module$master_arlock, + debug_module$master_arcache, + debug_module$master_arprot, + debug_module$master_arqos, + debug_module$master_arregion } ; + assign msNoSynth_1_rNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_1_doPut ? + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 : + ifcs_1_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_rNoSynth_src_peekWire$wget = + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_rNoSynth_buffer_ff$D_OUT : + msNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_0_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] || WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[172] ; - assign ssNoSynth_0_b_dwReady$whas = - WILL_FIRE_RL_ifcs_0_followFlits_1 || - WILL_FIRE_RL_ifcs_0_firstFlit_1 ; - assign ssNoSynth_0_ar_buffer_enqw$wget = + assign ssNoSynth_0_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_0_1$wset_1__SEL_1 || MUX_flitToSink_1_0_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_0_r_dwReady$whas = - WILL_FIRE_RL_ifcs_0_1_followFlits_1 || - WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; - assign ssNoSynth_1_aw_buffer_enqw$wget = split_1_doPut$wget[171:74] ; - assign ssNoSynth_1_w_buffer_enqw$wget = split_1_doPut$wget[73:0] ; - assign ssNoSynth_1_w_buffer_enqw$whas = + assign ssNoSynth_1_awNoSynth_src_peekWire$wget = + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_awNoSynth_buffer_ff$D_OUT : + split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] || WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[172] ; - assign ssNoSynth_1_b_dwReady$whas = - WILL_FIRE_RL_ifcs_1_followFlits_1 || - WILL_FIRE_RL_ifcs_1_firstFlit_1 ; - assign ssNoSynth_1_ar_buffer_enqw$wget = + assign ssNoSynth_1_wNoSynth_src_peekWire$wget = + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_wNoSynth_buffer_ff$D_OUT : + split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_bNoSynth_buffer_enqw$wget = + { plic$axi4_slave_bid, plic$axi4_slave_bresp } ; + assign ssNoSynth_1_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_1_r_dwReady$whas = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 || - WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; - assign ssNoSynth_2_aw_buffer_enqw$wget = split_2_doPut$wget[171:74] ; - assign ssNoSynth_2_w_buffer_enqw$wget = split_2_doPut$wget[73:0] ; - assign ssNoSynth_2_w_buffer_enqw$whas = + assign ssNoSynth_1_arNoSynth_src_peekWire$wget = + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_rNoSynth_buffer_enqw$wget = + { plic$axi4_slave_rid, + plic$axi4_slave_rdata, + plic$axi4_slave_rresp, + plic$axi4_slave_rlast, + plic$axi4_slave_ruser } ; + assign ssNoSynth_2_awNoSynth_src_peekWire$wget = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_awNoSynth_buffer_ff$D_OUT : + split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] || WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[172] ; - assign ssNoSynth_2_b_dwReady$whas = - WILL_FIRE_RL_ifcs_2_followFlits || - WILL_FIRE_RL_ifcs_2_firstFlit ; - assign ssNoSynth_2_ar_buffer_enqw$wget = + assign ssNoSynth_2_wNoSynth_src_peekWire$wget = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_wNoSynth_buffer_ff$D_OUT : + split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_bNoSynth_buffer_enqw$wget = + { proc$debug_module_mem_server_bid, + proc$debug_module_mem_server_bresp } ; + assign ssNoSynth_2_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_2$wset_1__SEL_1 || MUX_flitToSink_1_2$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_2_r_dwReady$whas = - WILL_FIRE_RL_ifcs_2_1_followFlits || - WILL_FIRE_RL_ifcs_2_1_firstFlit ; + assign ssNoSynth_2_arNoSynth_src_peekWire$wget = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_2_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_rNoSynth_buffer_enqw$wget = + { proc$debug_module_mem_server_rid, + proc$debug_module_mem_server_rdata, + proc$debug_module_mem_server_rresp, + proc$debug_module_mem_server_rlast, + proc$debug_module_mem_server_ruser } ; + assign merged_0_outflit$wget = + { 1'd0, merged_0_awff$D_OUT, merged_0_wff$D_OUT } ; + assign merged_1_outflit$wget = + { 1'd0, merged_1_awff$D_OUT, merged_1_wff$D_OUT } ; assign split_0_doPut$wget = (MUX_flitToSink_0$wset_1__SEL_1 || MUX_flitToSink_0$wset_1__SEL_3) ? @@ -6713,15 +9044,21 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_flitToSink_2$wset_1__SEL_3) ? ifcs_0_innerReq$D_OUT : ifcs_1_innerReq$D_OUT ; + assign ifcs_0_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_0_doPut || + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_doPut || + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign reqWires_0$wget = (!ifcs_0_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0] ; assign reqWires_1$wget = (!ifcs_1_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0] ; assign flitToSink_0$whas = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] || @@ -6746,21 +9083,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_innerRoute$D_OUT[2] ; assign reqWires_1_0$wget = (!ifcs_0_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_0_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_0_routeBack$D_OUT[0] ; assign reqWires_1_1$wget = (!ifcs_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_1_routeBack$D_OUT[0] ; assign reqWires_1_2$wget = (!ifcs_2_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_2_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_2_routeBack$D_OUT[0] ; assign flitToSink_1_0$whas = WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] || @@ -6782,15 +9119,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && ifcs_2_routeBack$D_OUT[1] ; + assign ifcs_0_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_0_doPut || + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_1_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_1_doPut || + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign reqWires_1_0_1$wget = (!ifcs_0_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 : + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : ifcs_0_1_innerRoute$D_OUT[0] ; assign reqWires_1_1_1$wget = (!ifcs_1_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 : + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : ifcs_1_1_innerRoute$D_OUT[0] ; assign flitToSink_1_0_1$whas = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] || @@ -6815,21 +9158,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_innerRoute$D_OUT[2] ; assign reqWires_1_1_0$wget = (!ifcs_0_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0] ; assign reqWires_1_1_1_1$wget = (!ifcs_1_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0] ; assign reqWires_1_1_2$wget = (!ifcs_2_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0] ; assign flitToSink_1_1_0$whas = WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] || @@ -6851,21 +9194,40 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_routeBack$D_OUT[1] ; - assign ug_uncached_mem_shim_master_u_aw_dropWire$whas = + assign uncached_mem_master_awSynth_src_dropWire$whas = uncached_mem_shim_awff$EMPTY_N && cpu_dmem_master_awready ; - assign ug_uncached_mem_shim_master_u_w_dropWire$whas = + assign uncached_mem_master_wSynth_src_dropWire$whas = uncached_mem_shim_wff$EMPTY_N && cpu_dmem_master_wready ; - assign ug_uncached_mem_shim_master_u_ar_dropWire$whas = + assign uncached_mem_master_arSynth_src_dropWire$whas = uncached_mem_shim_arff$EMPTY_N && cpu_dmem_master_arready ; - assign tagController_tmp_ug_master_u_aw_dropWire$whas = - tagController_tmp_shimMaster_awff_rv$port1__read[99] && - cpu_imem_master_awready ; - assign tagController_tmp_ug_master_u_w_dropWire$whas = - tagController_tmp_shimMaster_wff_rv$port1__read[73] && - cpu_imem_master_wready ; - assign tagController_tmp_ug_master_u_ar_dropWire$whas = - tagController_tmp_shimMaster_arff_rv$port1__read[99] && - cpu_imem_master_arready ; + assign msNoSynth_0_arNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && x__h95023 == 9'd1 || + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign msNoSynth_1_arNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && x__h97622 == 9'd1 || + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign ssNoSynth_0_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_followFlits_1 || + WILL_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ssNoSynth_0_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ssNoSynth_1_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ssNoSynth_1_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ssNoSynth_2_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_2_followFlits || + WILL_FIRE_RL_ifcs_2_firstFlit ; + assign ssNoSynth_2_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_2_1_followFlits || + WILL_FIRE_RL_ifcs_2_1_firstFlit ; assign merged_0_doDrop$whas = WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp || WILL_FIRE_RL_ifcs_0_drainFlits || @@ -6878,19 +9240,28 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ifcs_1_firstFlit ; assign sourceSelect_1_0$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign sourceSelect_1_1$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign sourceSelect_1_2$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign sourceSelect_1_0_1$whas = WILL_FIRE_RL_arbitrate_2 && - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign sourceSelect_1_1_1$whas = WILL_FIRE_RL_arbitrate_2 && - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; + assign cached_mem_master_awSynth_src_dropWire$whas = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + cpu_imem_master_awready ; + assign cached_mem_master_wSynth_src_dropWire$whas = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + cpu_imem_master_wready ; + assign cached_mem_master_arSynth_src_dropWire$whas = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + cpu_imem_master_arready ; assign tagController_tmp_shimSlave_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_slave_u_aw_putWire$wget } ; assign tagController_tmp_shimSlave_awff_rv$port1__read = @@ -6983,11 +9354,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign tagController_tmp_shimMaster_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_tagCon$memory_request_get[100:95], - aw_awaddr__h10808, + aw_awaddr__h10611, tagController_tmp_tagCon$memory_request_get[7:0], - aw_awsize_val__h12547, + aw_awsize_val__h12350, 3'd2, - x__h14213, + x__h14016, 11'd0 } ; assign tagController_tmp_shimMaster_awff_rv$port1__read = tagController_tmp_shimMaster_awff_rv$EN_port0__write ? @@ -7040,12 +9411,12 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_tagCon$memory_request_get[93:92] != 2'd1 ; assign tagController_tmp_shimMaster_arff_rv$port0__write_1 = { 1'd1, - v_arid__h15556, - v_araddr__h15557, - v_arlen__h15558, - v_arsize_val__h15603, + v_arid__h15359, + v_araddr__h15360, + v_arlen__h15361, + v_arsize_val__h15406, 3'd2, - x__h15621, + x__h15424, 11'd0 } ; assign tagController_tmp_shimMaster_arff_rv$port1__read = tagController_tmp_shimMaster_arff_rv$EN_port0__write ? @@ -7075,25 +9446,16 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_rff_rv$port2__read ; assign ifcs_0_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - merged_0_flitLeft == 8'd0 ; - assign ifcs_0_noRoute_inner_currentReq$port0__write_1 = - { proc$master1_awid, - proc$master1_awaddr, - proc$master1_awlen, - proc$master1_awsize, - proc$master1_awburst, - proc$master1_awlock, - proc$master1_awcache, - proc$master1_awprot, - proc$master1_awqos, - proc$master1_awregion } ; + CAN_FIRE_RL_merged_0_passFlit && + !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_currentReq$port1__read = ifcs_0_noRoute_inner_currentReq$EN_port0__write ? - ifcs_0_noRoute_inner_currentReq$port0__write_1 : + merged_0_outflit$wget[170:74] : ifcs_0_noRoute_inner_currentReq ; assign ifcs_0_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - merged_0_flitLeft == 8'd0 ; + CAN_FIRE_RL_merged_0_passFlit && + !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_pendingReq$port1__read = ifcs_0_noRoute_inner_pendingReq$EN_port0__write || ifcs_0_noRoute_inner_pendingReq ; @@ -7102,77 +9464,44 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_0_noRoute_inner_pendingReq$port1__read ; assign ifcs_1_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - merged_1_flitLeft == 8'd0 ; - assign ifcs_1_noRoute_inner_currentReq$port0__write_1 = - { debug_module$master_awid, - debug_module$master_awaddr, - debug_module$master_awlen, - debug_module$master_awsize, - debug_module$master_awburst, - debug_module$master_awlock, - debug_module$master_awcache, - debug_module$master_awprot, - debug_module$master_awqos, - debug_module$master_awregion } ; + CAN_FIRE_RL_merged_1_passFlit && + !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_currentReq$port1__read = ifcs_1_noRoute_inner_currentReq$EN_port0__write ? - ifcs_1_noRoute_inner_currentReq$port0__write_1 : + merged_1_outflit$wget[170:74] : ifcs_1_noRoute_inner_currentReq ; assign ifcs_1_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - merged_1_flitLeft == 8'd0 ; + CAN_FIRE_RL_merged_1_passFlit && + !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_pendingReq$port1__read = ifcs_1_noRoute_inner_pendingReq$EN_port0__write || ifcs_1_noRoute_inner_pendingReq ; assign ifcs_1_noRoute_inner_pendingReq$port2__read = !CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp && ifcs_1_noRoute_inner_pendingReq$port1__read ; - assign ifcs_0_1_noRoute_currentReq$port0__write_1 = - { proc$master1_arid, - proc$master1_araddr, - proc$master1_arlen, - proc$master1_arsize, - proc$master1_arburst, - proc$master1_arlock, - proc$master1_arcache, - proc$master1_arprot, - proc$master1_arqos, - proc$master1_arregion } ; assign ifcs_0_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? - ifcs_0_1_noRoute_currentReq$port0__write_1 : + msNoSynth_0_arNoSynth_buffer_ff$D_OUT : ifcs_0_1_noRoute_currentReq ; assign ifcs_0_1_noRoute_flitCount$port0__write_1 = - { 1'd0, proc$master1_arlen } + 9'd1 ; - assign ifcs_0_1_noRoute_flitCount$port1__write_1 = - x_port1__read__h72781 - 9'd1 ; + { 1'd0, x__h94920 } + 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port1__write_1 = x__h95023 - 9'd1 ; assign ifcs_0_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ? ifcs_0_1_noRoute_flitCount$port1__write_1 : - x_port1__read__h72781 ; - assign ifcs_1_1_noRoute_currentReq$port0__write_1 = - { debug_module$master_arid, - debug_module$master_araddr, - debug_module$master_arlen, - debug_module$master_arsize, - debug_module$master_arburst, - debug_module$master_arlock, - debug_module$master_arcache, - debug_module$master_arprot, - debug_module$master_arqos, - debug_module$master_arregion } ; + x__h95023 ; assign ifcs_1_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? - ifcs_1_1_noRoute_currentReq$port0__write_1 : + msNoSynth_1_arNoSynth_buffer_ff$D_OUT : ifcs_1_1_noRoute_currentReq ; assign ifcs_1_1_noRoute_flitCount$port0__write_1 = - { 1'd0, debug_module$master_arlen } + 9'd1 ; - assign ifcs_1_1_noRoute_flitCount$port1__write_1 = - x_port1__read__h75154 - 9'd1 ; + { 1'd0, x__h97519 } + 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port1__write_1 = x__h97622 - 9'd1 ; assign ifcs_1_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ? ifcs_1_1_noRoute_flitCount$port1__write_1 : - x_port1__read__h75154 ; + x__h97622 ; // register activeSource_0 assign activeSource_0$D_IN = @@ -7290,52 +9619,52 @@ module mkCoreW(RST_N_dm_power_on_reset, // register arbiter_1_1_firstHot assign arbiter_1_1_firstHot$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; assign arbiter_1_1_firstHot$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect assign arbiter_1_1_lastSelect$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign arbiter_1_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect_1 assign arbiter_1_1_lastSelect_1$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign arbiter_1_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_firstHot assign arbiter_1_firstHot$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign arbiter_1_firstHot$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_firstHot_1 assign arbiter_1_firstHot_1$D_IN = - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; assign arbiter_1_firstHot_1$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_1_lastSelect assign arbiter_1_lastSelect$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign arbiter_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_1 assign arbiter_1_lastSelect_1$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign arbiter_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_2 assign arbiter_1_lastSelect_2$D_IN = - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign arbiter_1_lastSelect_2$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_firstHot assign arbiter_firstHot$D_IN = - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign arbiter_firstHot$EN = CAN_FIRE_RL_arbitrate ; // register arbiter_lastSelect assign arbiter_lastSelect$D_IN = - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign arbiter_lastSelect$EN = CAN_FIRE_RL_arbitrate ; // register ifcs_0_1_noRoute_currentReq @@ -7358,9 +9687,9 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_state_1$D_IN = !MUX_ifcs_0_1_state_1$write_1__SEL_1 ; assign ifcs_0_1_state_1$EN = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && - uncached_mem_shim_rff$D_OUT[1] || + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && - !uncached_mem_shim_rff$D_OUT[1] ; + !ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_0_noRoute_inner_currentReq assign ifcs_0_noRoute_inner_currentReq$D_IN = @@ -7386,9 +9715,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_state$EN = (WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits) && - proc$master1_wlast || - WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast || - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 || + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; // register ifcs_0_state_1 assign ifcs_0_state_1$D_IN = 1'd0 ; @@ -7413,8 +9744,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // register ifcs_1_1_state_1 assign ifcs_1_1_state_1$D_IN = !MUX_ifcs_1_1_state_1$write_1__SEL_1 ; assign ifcs_1_1_state_1$EN = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast || - WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && !plic$axi4_slave_rlast ; + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + !ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_1_noRoute_inner_currentReq assign ifcs_1_noRoute_inner_currentReq$D_IN = @@ -7440,10 +9773,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_state$EN = (WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits) && - debug_module$master_wlast || - WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast || + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 || + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - !debug_module$master_wlast ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; // register ifcs_1_state_1 assign ifcs_1_state_1$D_IN = 1'd0 ; @@ -7453,9 +9787,9 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_2_1_state$D_IN = !MUX_ifcs_2_1_state$write_1__SEL_1 ; assign ifcs_2_1_state$EN = WILL_FIRE_RL_ifcs_2_1_followFlits && - proc$debug_module_mem_server_rlast || + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_2_1_firstFlit && - !proc$debug_module_mem_server_rlast ; + !ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_2_state assign ifcs_2_state$D_IN = 1'd0 ; @@ -7463,17 +9797,21 @@ module mkCoreW(RST_N_dm_power_on_reset, // register merged_0_flitLeft assign merged_0_flitLeft$D_IN = - WILL_FIRE_RL_merged_0_genOther ? - MUX_merged_0_flitLeft$write_1__VAL_1 : - proc$master1_awlen ; - assign merged_0_flitLeft$EN = msNoSynth_0_w_dwReady$whas ; + WILL_FIRE_RL_merged_0_genFirst ? + merged_0_awff$D_OUT[28:21] : + MUX_merged_0_flitLeft$write_1__VAL_2 ; + assign merged_0_flitLeft$EN = + WILL_FIRE_RL_merged_0_genFirst || + WILL_FIRE_RL_merged_0_genOther ; // register merged_1_flitLeft assign merged_1_flitLeft$D_IN = - WILL_FIRE_RL_merged_1_genOther ? - MUX_merged_1_flitLeft$write_1__VAL_1 : - debug_module$master_awlen ; - assign merged_1_flitLeft$EN = msNoSynth_1_w_dwReady$whas ; + WILL_FIRE_RL_merged_1_genFirst ? + merged_1_awff$D_OUT[28:21] : + MUX_merged_1_flitLeft$write_1__VAL_2 ; + assign merged_1_flitLeft$EN = + WILL_FIRE_RL_merged_1_genFirst || + WILL_FIRE_RL_merged_1_genOther ; // register rg_fromhost_addr assign rg_fromhost_addr$D_IN = start_fromhost_addr ; @@ -7497,21 +9835,21 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_split_0_flitLeft$write_1__SEL_1 ? MUX_split_0_flitLeft$write_1__VAL_1 : split_0_doPut$wget[102:95] ; - assign split_0_flitLeft$EN = ssNoSynth_0_w_buffer_enqw$whas ; + assign split_0_flitLeft$EN = ssNoSynth_0_wNoSynth_buffer_enqw$whas ; // register split_1_flitLeft assign split_1_flitLeft$D_IN = MUX_split_1_flitLeft$write_1__SEL_1 ? MUX_split_1_flitLeft$write_1__VAL_1 : split_1_doPut$wget[102:95] ; - assign split_1_flitLeft$EN = ssNoSynth_1_w_buffer_enqw$whas ; + assign split_1_flitLeft$EN = ssNoSynth_1_wNoSynth_buffer_enqw$whas ; // register split_2_flitLeft assign split_2_flitLeft$D_IN = MUX_split_2_flitLeft$write_1__SEL_1 ? MUX_split_2_flitLeft$write_1__VAL_1 : split_2_doPut$wget[102:95] ; - assign split_2_flitLeft$EN = ssNoSynth_2_w_buffer_enqw$whas ; + assign split_2_flitLeft$EN = ssNoSynth_2_wNoSynth_buffer_enqw$whas ; // register state assign state$D_IN = !MUX_state$write_1__SEL_1 && !MUX_state$write_1__SEL_2 ; @@ -7553,7 +9891,7 @@ module mkCoreW(RST_N_dm_power_on_reset, assign tagController_tmp_addrOffset$D_IN = tagController_tmp_shimSlave_wff_rv$port1__read[1] ? 64'd0 : - x__h8207 ; + x__h8010 ; assign tagController_tmp_addrOffset$EN = WILL_FIRE_RL_tagController_tmp_passCacheWrite ; @@ -7631,37 +9969,27 @@ module mkCoreW(RST_N_dm_power_on_reset, assign debug_module$hart0_gpr_mem_client_response_put = proc$hart0_gpr_mem_server_response_get ; assign debug_module$hart0_reset_client_response_put = 1'd1 ; - assign debug_module$master_arready = msNoSynth_1_ar_dwReady$whas ; - assign debug_module$master_awready = CAN_FIRE_RL_merged_1_genFirst ; + assign debug_module$master_arready = + msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign debug_module$master_awready = + msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; assign debug_module$master_bid = - msNoSynth_1_b_buffer_ff$EMPTY_N ? - msNoSynth_1_b_buffer_ff$D_OUT[5:2] : - msNoSynth_1_b_buffer_enqw$wget[5:2] ; + msNoSynth_1_bNoSynth_src_peekWire$wget[5:2] ; assign debug_module$master_bresp = - msNoSynth_1_b_buffer_ff$EMPTY_N ? - msNoSynth_1_b_buffer_ff$D_OUT[1:0] : - msNoSynth_1_b_buffer_enqw$wget[1:0] ; + msNoSynth_1_bNoSynth_src_peekWire$wget[1:0] ; + assign debug_module$master_bvalid = msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign debug_module$master_rdata = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[67:4] : - msNoSynth_1_r_buffer_enqw$wget[67:4] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[67:4] ; assign debug_module$master_rid = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[71:68] : - msNoSynth_1_r_buffer_enqw$wget[71:68] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[71:68] ; assign debug_module$master_rlast = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[1] : - msNoSynth_1_r_buffer_enqw$wget[1] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[1] ; assign debug_module$master_rresp = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[3:2] : - msNoSynth_1_r_buffer_enqw$wget[3:2] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[3:2] ; assign debug_module$master_ruser = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[0] : - msNoSynth_1_r_buffer_enqw$wget[0] ; - assign debug_module$master_wready = msNoSynth_1_w_dwReady$whas ; + msNoSynth_1_rNoSynth_src_peekWire$wget[0] ; + assign debug_module$master_rvalid = msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign debug_module$master_wready = msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; assign debug_module$ndm_reset_client_response_put = ndm_reset_client_response_put ; assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; @@ -7691,24 +10019,16 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_ndm_reset_client_request_get ; assign debug_module$EN_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; - assign debug_module$master_bvalid = CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; - assign debug_module$master_rvalid = CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; // submodule dm_hart0_reset_controller assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; // submodule ifcs_0_1_innerReq assign ifcs_0_1_innerReq$D_IN = - { fatReq_arid__h72223, - proc$master1_araddr, - proc$master1_arlen, - proc$master1_arsize, - proc$master1_arburst, - proc$master1_arlock, - proc$master1_arcache, - proc$master1_arprot, - proc$master1_arqos, - proc$master1_arregion } ; + { fatReq_arid__h94342, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:0] : + proc$master1_ar_peek[92:0] } ; assign ifcs_0_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_1_followFlits || WILL_FIRE_RL_ifcs_0_1_firstFlit ; @@ -7719,16 +10039,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_1_innerRoute assign ifcs_0_1_innerRoute$D_IN = - { !proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845, - (proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - !proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850, - (proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - (proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850) } ; + { !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) } ; assign ifcs_0_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit ; assign ifcs_0_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || @@ -7739,14 +10059,15 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_noRouteRsp$D_IN = { ifcs_0_1_noRoute_currentReq$port1__read[96:93], 66'h2AAAAAAAAAAAAAAAB, - x_port1__read__h72781 == 9'd1, + x__h95023 == 9'd1, 1'h0 } ; assign ifcs_0_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; - assign ifcs_0_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_0_1_noRouteRsp$DEQ = + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; assign ifcs_0_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_1_routeBack - assign ifcs_0_1_routeBack$D_IN = 2'd1 << uncached_mem_shim_rff$D_OUT[72] ; + assign ifcs_0_1_routeBack$D_IN = 2'd1 << x__h98415[4] ; assign ifcs_0_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; assign ifcs_0_1_routeBack$DEQ = WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] || @@ -7755,8 +10076,12 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_routeBack$CLR = 1'b0 ; // submodule ifcs_0_1_rspBack - assign ifcs_0_1_rspBack$D_IN = uncached_mem_shim_rff$D_OUT[71:0] ; - assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_r_dwReady$whas ; + assign ifcs_0_1_rspBack$D_IN = + { x__h98415[3:0], + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[67:0] : + uncached_mem_shim_rff$D_OUT[67:0] } ; + assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; assign ifcs_0_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_7 ; @@ -7764,21 +10089,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_innerReq assign ifcs_0_innerReq$D_IN = - { merged_0_flitLeft != 8'd0, - a_awid__h38523, - proc$master1_awaddr, - proc$master1_awlen, - proc$master1_awsize, - proc$master1_awburst, - proc$master1_awlock, - proc$master1_awcache, - proc$master1_awprot, - proc$master1_awqos, - proc$master1_awregion, - proc$master1_wdata, - proc$master1_wstrb, - proc$master1_wlast, - 1'd0 } ; + { !CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171], + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 } ; assign ifcs_0_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_followFlits || WILL_FIRE_RL_ifcs_0_firstFlit ; @@ -7789,16 +10101,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_innerRoute assign ifcs_0_innerRoute$D_IN = - { !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195, - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203, - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203) } ; + { !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) } ; assign ifcs_0_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit ; assign ifcs_0_innerRoute$DEQ = WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] || @@ -7810,11 +10122,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_noRouteRsp$D_IN = { ifcs_0_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_0_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; - assign ifcs_0_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_0_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; assign ifcs_0_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_routeBack - assign ifcs_0_routeBack$D_IN = 2'd1 << uncached_mem_shim_bff$D_OUT[6] ; + assign ifcs_0_routeBack$D_IN = 2'd1 << x__h62625[4] ; assign ifcs_0_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; assign ifcs_0_routeBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || @@ -7822,8 +10134,12 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_routeBack$CLR = 1'b0 ; // submodule ifcs_0_rspBack - assign ifcs_0_rspBack$D_IN = uncached_mem_shim_bff$D_OUT[5:0] ; - assign ifcs_0_rspBack$ENQ = ssNoSynth_0_b_dwReady$whas ; + assign ifcs_0_rspBack$D_IN = + { x__h62625[3:0], + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[1:0] : + uncached_mem_shim_bff$D_OUT[1:0] } ; + assign ifcs_0_rspBack$ENQ = ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; assign ifcs_0_rspBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || WILL_FIRE_RL_burst_2 ; @@ -7831,16 +10147,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_innerReq assign ifcs_1_1_innerReq$D_IN = - { fatReq_arid__h74597, - debug_module$master_araddr, - debug_module$master_arlen, - debug_module$master_arsize, - debug_module$master_arburst, - debug_module$master_arlock, - debug_module$master_arcache, - debug_module$master_arprot, - debug_module$master_arqos, - debug_module$master_arregion } ; + { fatReq_arid__h96944, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:0] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[92:0] } ; assign ifcs_1_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_1_followFlits || WILL_FIRE_RL_ifcs_1_1_firstFlit ; @@ -7851,16 +10161,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_innerRoute assign ifcs_1_1_innerRoute$D_IN = - { !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932, - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937, - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937) } ; + { !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) } ; assign ifcs_1_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit ; assign ifcs_1_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || @@ -7871,14 +10181,15 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_1_noRouteRsp$D_IN = { ifcs_1_1_noRoute_currentReq$port1__read[96:93], 66'h2AAAAAAAAAAAAAAAB, - x_port1__read__h75154 == 9'd1, + x__h97622 == 9'd1, 1'h0 } ; assign ifcs_1_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; - assign ifcs_1_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ifcs_1_1_noRouteRsp$DEQ = + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign ifcs_1_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_1_routeBack - assign ifcs_1_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_rid[4] ; + assign ifcs_1_1_routeBack$D_IN = 2'd1 << x__h99370[4] ; assign ifcs_1_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; assign ifcs_1_1_routeBack$DEQ = WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] || @@ -7888,12 +10199,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_rspBack assign ifcs_1_1_rspBack$D_IN = - { plic$axi4_slave_rid[3:0], - plic$axi4_slave_rdata, - plic$axi4_slave_rresp, - plic$axi4_slave_rlast, - plic$axi4_slave_ruser } ; - assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_r_dwReady$whas ; + { x__h99370[3:0], + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[67:0] : + ssNoSynth_1_rNoSynth_buffer_enqw$wget[67:0] } ; + assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; assign ifcs_1_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_8 ; @@ -7901,21 +10211,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_innerReq assign ifcs_1_innerReq$D_IN = - { merged_1_flitLeft != 8'd0, - a_awid__h41194, - debug_module$master_awaddr, - debug_module$master_awlen, - debug_module$master_awsize, - debug_module$master_awburst, - debug_module$master_awlock, - debug_module$master_awcache, - debug_module$master_awprot, - debug_module$master_awqos, - debug_module$master_awregion, - debug_module$master_wdata, - debug_module$master_wstrb, - debug_module$master_wlast, - debug_module$master_wuser } ; + { !CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171], + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 } ; assign ifcs_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_followFlits || WILL_FIRE_RL_ifcs_1_firstFlit ; @@ -7926,16 +10223,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_innerRoute assign ifcs_1_innerRoute$D_IN = - { !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297, - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302, - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302) } ; + { !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) } ; assign ifcs_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit ; assign ifcs_1_innerRoute$DEQ = WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] || @@ -7947,11 +10244,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_noRouteRsp$D_IN = { ifcs_1_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; - assign ifcs_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign ifcs_1_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign ifcs_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_routeBack - assign ifcs_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_bid[4] ; + assign ifcs_1_routeBack$D_IN = 2'd1 << x__h63516[4] ; assign ifcs_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; assign ifcs_1_routeBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || @@ -7960,16 +10257,18 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_rspBack assign ifcs_1_rspBack$D_IN = - { plic$axi4_slave_bid[3:0], plic$axi4_slave_bresp } ; - assign ifcs_1_rspBack$ENQ = ssNoSynth_1_b_dwReady$whas ; + { x__h63516[3:0], + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[1:0] : + ssNoSynth_1_bNoSynth_buffer_enqw$wget[1:0] } ; + assign ifcs_1_rspBack$ENQ = ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; assign ifcs_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_3 ; assign ifcs_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_1_routeBack - assign ifcs_2_1_routeBack$D_IN = - 2'd1 << proc$debug_module_mem_server_rid[4] ; + assign ifcs_2_1_routeBack$D_IN = 2'd1 << x__h100325[4] ; assign ifcs_2_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_1_firstFlit ; assign ifcs_2_1_routeBack$DEQ = WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] || @@ -7979,19 +10278,18 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_2_1_rspBack assign ifcs_2_1_rspBack$D_IN = - { proc$debug_module_mem_server_rid[3:0], - proc$debug_module_mem_server_rdata, - proc$debug_module_mem_server_rresp, - proc$debug_module_mem_server_rlast, - proc$debug_module_mem_server_ruser } ; - assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_r_dwReady$whas ; + { x__h100325[3:0], + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[67:0] : + ssNoSynth_2_rNoSynth_buffer_enqw$wget[67:0] } ; + assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; assign ifcs_2_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_9 ; assign ifcs_2_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_routeBack - assign ifcs_2_routeBack$D_IN = 2'd1 << proc$debug_module_mem_server_bid[4] ; + assign ifcs_2_routeBack$D_IN = 2'd1 << x__h64407[4] ; assign ifcs_2_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_firstFlit ; assign ifcs_2_routeBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || @@ -8000,165 +10298,245 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_2_rspBack assign ifcs_2_rspBack$D_IN = - { proc$debug_module_mem_server_bid[3:0], - proc$debug_module_mem_server_bresp } ; - assign ifcs_2_rspBack$ENQ = ssNoSynth_2_b_dwReady$whas ; + { x__h64407[3:0], + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[1:0] : + ssNoSynth_2_bNoSynth_buffer_enqw$wget[1:0] } ; + assign ifcs_2_rspBack$ENQ = ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; assign ifcs_2_rspBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || WILL_FIRE_RL_burst_4 ; assign ifcs_2_rspBack$CLR = 1'b0 ; - // submodule msNoSynth_0_b_buffer_ff - assign msNoSynth_0_b_buffer_ff$D_IN = msNoSynth_0_b_buffer_enqw$wget ; - assign msNoSynth_0_b_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; - assign msNoSynth_0_b_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; - assign msNoSynth_0_b_buffer_ff$CLR = 1'b0 ; + // submodule merged_0_awff + assign merged_0_awff$D_IN = + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_awNoSynth_buffer_ff$D_OUT : + proc$master1_aw_peek ; + assign merged_0_awff$ENQ = CAN_FIRE_RL_merged_0_awFlit ; + assign merged_0_awff$DEQ = CAN_FIRE_RL_merged_0_genFirst ; + assign merged_0_awff$CLR = 1'b0 ; - // submodule msNoSynth_0_b_buffer_firstValid - assign msNoSynth_0_b_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_0_b_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + // submodule merged_0_wff + assign merged_0_wff$D_IN = + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_wNoSynth_buffer_ff$D_OUT : + proc_uncached_wSynth_src_peekWire$wget ; + assign merged_0_wff$ENQ = CAN_FIRE_RL_merged_0_wFlit ; + assign merged_0_wff$DEQ = + WILL_FIRE_RL_merged_0_genOther || + WILL_FIRE_RL_merged_0_genFirst ; + assign merged_0_wff$CLR = 1'b0 ; - // submodule msNoSynth_0_r_buffer_ff - assign msNoSynth_0_r_buffer_ff$D_IN = msNoSynth_0_r_buffer_enqw$wget ; - assign msNoSynth_0_r_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; - assign msNoSynth_0_r_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; - assign msNoSynth_0_r_buffer_ff$CLR = 1'b0 ; + // submodule merged_1_awff + assign merged_1_awff$D_IN = + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_awNoSynth_buffer_ff$D_OUT : + msNoSynth_1_awNoSynth_buffer_enqw$wget ; + assign merged_1_awff$ENQ = CAN_FIRE_RL_merged_1_awFlit ; + assign merged_1_awff$DEQ = CAN_FIRE_RL_merged_1_genFirst ; + assign merged_1_awff$CLR = 1'b0 ; - // submodule msNoSynth_0_r_buffer_firstValid - assign msNoSynth_0_r_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_0_r_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; + // submodule merged_1_wff + assign merged_1_wff$D_IN = + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_wNoSynth_buffer_ff$D_OUT : + msNoSynth_1_wNoSynth_buffer_enqw$wget ; + assign merged_1_wff$ENQ = CAN_FIRE_RL_merged_1_wFlit ; + assign merged_1_wff$DEQ = + WILL_FIRE_RL_merged_1_genOther || + WILL_FIRE_RL_merged_1_genFirst ; + assign merged_1_wff$CLR = 1'b0 ; - // submodule msNoSynth_1_b_buffer_ff - assign msNoSynth_1_b_buffer_ff$D_IN = msNoSynth_1_b_buffer_enqw$wget ; - assign msNoSynth_1_b_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; - assign msNoSynth_1_b_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; - assign msNoSynth_1_b_buffer_ff$CLR = 1'b0 ; + // submodule msNoSynth_0_arNoSynth_buffer_ff + assign msNoSynth_0_arNoSynth_buffer_ff$D_IN = proc$master1_ar_peek ; + assign msNoSynth_0_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; + assign msNoSynth_0_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; + assign msNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule msNoSynth_1_b_buffer_firstValid - assign msNoSynth_1_b_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_1_b_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + // submodule msNoSynth_0_arNoSynth_buffer_firstValid + assign msNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_arNoSynth_buffer_firstValid$EN = + msNoSynth_0_arNoSynth_buffer_dequeueing$whas ; - // submodule msNoSynth_1_r_buffer_ff - assign msNoSynth_1_r_buffer_ff$D_IN = msNoSynth_1_r_buffer_enqw$wget ; - assign msNoSynth_1_r_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; - assign msNoSynth_1_r_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; - assign msNoSynth_1_r_buffer_ff$CLR = 1'b0 ; + // submodule msNoSynth_0_awNoSynth_buffer_ff + assign msNoSynth_0_awNoSynth_buffer_ff$D_IN = proc$master1_aw_peek ; + assign msNoSynth_0_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; + assign msNoSynth_0_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; + assign msNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule msNoSynth_1_r_buffer_firstValid - assign msNoSynth_1_r_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_1_r_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; + // submodule msNoSynth_0_awNoSynth_buffer_firstValid + assign msNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_0_awFlit ; + + // submodule msNoSynth_0_bNoSynth_buffer_ff + assign msNoSynth_0_bNoSynth_buffer_ff$D_IN = + msNoSynth_0_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; + assign msNoSynth_0_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; + assign msNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_bNoSynth_buffer_firstValid + assign msNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; + + // submodule msNoSynth_0_rNoSynth_buffer_ff + assign msNoSynth_0_rNoSynth_buffer_ff$D_IN = + msNoSynth_0_rNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; + assign msNoSynth_0_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; + assign msNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_rNoSynth_buffer_firstValid + assign msNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; + + // submodule msNoSynth_0_wNoSynth_buffer_ff + assign msNoSynth_0_wNoSynth_buffer_ff$D_IN = + proc_uncached_wSynth_src_peekWire$wget ; + assign msNoSynth_0_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; + assign msNoSynth_0_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; + assign msNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_wNoSynth_buffer_firstValid + assign msNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_0_wFlit ; + + // submodule msNoSynth_1_arNoSynth_buffer_ff + assign msNoSynth_1_arNoSynth_buffer_ff$D_IN = + msNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; + assign msNoSynth_1_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; + assign msNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_arNoSynth_buffer_firstValid + assign msNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_arNoSynth_buffer_firstValid$EN = + msNoSynth_1_arNoSynth_buffer_dequeueing$whas ; + + // submodule msNoSynth_1_awNoSynth_buffer_ff + assign msNoSynth_1_awNoSynth_buffer_ff$D_IN = + msNoSynth_1_awNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; + assign msNoSynth_1_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; + assign msNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_awNoSynth_buffer_firstValid + assign msNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_1_awFlit ; + + // submodule msNoSynth_1_bNoSynth_buffer_ff + assign msNoSynth_1_bNoSynth_buffer_ff$D_IN = + msNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; + assign msNoSynth_1_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; + assign msNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_bNoSynth_buffer_firstValid + assign msNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; + + // submodule msNoSynth_1_rNoSynth_buffer_ff + assign msNoSynth_1_rNoSynth_buffer_ff$D_IN = + msNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; + assign msNoSynth_1_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; + assign msNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_rNoSynth_buffer_firstValid + assign msNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; + + // submodule msNoSynth_1_wNoSynth_buffer_ff + assign msNoSynth_1_wNoSynth_buffer_ff$D_IN = + msNoSynth_1_wNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; + assign msNoSynth_1_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; + assign msNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_wNoSynth_buffer_firstValid + assign msNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_1_wFlit ; // submodule plic assign plic$axi4_slave_araddr = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[92:29] : - ssNoSynth_1_ar_buffer_enqw$wget[92:29] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_arburst = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[17:16] : - ssNoSynth_1_ar_buffer_enqw$wget[17:16] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_arcache = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[14:11] : - ssNoSynth_1_ar_buffer_enqw$wget[14:11] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_arid = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[97:93] : - ssNoSynth_1_ar_buffer_enqw$wget[97:93] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_arlen = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[28:21] : - ssNoSynth_1_ar_buffer_enqw$wget[28:21] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_arlock = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[15] : - ssNoSynth_1_ar_buffer_enqw$wget[15] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_arprot = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[10:8] : - ssNoSynth_1_ar_buffer_enqw$wget[10:8] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_arqos = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[7:4] : - ssNoSynth_1_ar_buffer_enqw$wget[7:4] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_arregion = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[3:0] : - ssNoSynth_1_ar_buffer_enqw$wget[3:0] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_arsize = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[20:18] : - ssNoSynth_1_ar_buffer_enqw$wget[20:18] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[20:18] ; + assign plic$axi4_slave_arvalid = ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign plic$axi4_slave_awaddr = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[92:29] : - ssNoSynth_1_aw_buffer_enqw$wget[92:29] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_awburst = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[17:16] : - ssNoSynth_1_aw_buffer_enqw$wget[17:16] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_awcache = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[14:11] : - ssNoSynth_1_aw_buffer_enqw$wget[14:11] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_awid = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[97:93] : - ssNoSynth_1_aw_buffer_enqw$wget[97:93] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_awlen = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[28:21] : - ssNoSynth_1_aw_buffer_enqw$wget[28:21] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_awlock = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[15] : - ssNoSynth_1_aw_buffer_enqw$wget[15] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_awprot = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[10:8] : - ssNoSynth_1_aw_buffer_enqw$wget[10:8] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_awqos = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[7:4] : - ssNoSynth_1_aw_buffer_enqw$wget[7:4] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_awregion = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[3:0] : - ssNoSynth_1_aw_buffer_enqw$wget[3:0] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_awsize = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[20:18] : - ssNoSynth_1_aw_buffer_enqw$wget[20:18] ; - assign plic$axi4_slave_bready = ssNoSynth_1_b_dwReady$whas ; - assign plic$axi4_slave_rready = ssNoSynth_1_r_dwReady$whas ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[20:18] ; + assign plic$axi4_slave_awvalid = ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign plic$axi4_slave_bready = ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign plic$axi4_slave_rready = ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign plic$axi4_slave_wdata = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[73:10] : - ssNoSynth_1_w_buffer_enqw$wget[73:10] ; - assign plic$axi4_slave_wlast = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[1] : - ssNoSynth_1_w_buffer_enqw$wget[1] ; - assign plic$axi4_slave_wstrb = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[9:2] : - ssNoSynth_1_w_buffer_enqw$wget[9:2] ; - assign plic$axi4_slave_wuser = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[0] : - ssNoSynth_1_w_buffer_enqw$wget[0] ; + ssNoSynth_1_wNoSynth_src_peekWire$wget[73:10] ; + assign plic$axi4_slave_wlast = ssNoSynth_1_wNoSynth_src_peekWire$wget[1] ; + assign plic$axi4_slave_wstrb = ssNoSynth_1_wNoSynth_src_peekWire$wget[9:2] ; + assign plic$axi4_slave_wuser = ssNoSynth_1_wNoSynth_src_peekWire$wget[0] ; + assign plic$axi4_slave_wvalid = ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_range[127:64] ; assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_range[127:64] + @@ -8201,109 +10579,66 @@ module mkCoreW(RST_N_dm_power_on_reset, assign plic$EN_server_reset_request_put = 1'b0 ; assign plic$EN_server_reset_response_get = 1'b0 ; assign plic$EN_set_addr_map = EN_start ; - assign plic$axi4_slave_awvalid = CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; - assign plic$axi4_slave_wvalid = CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; - assign plic$axi4_slave_arvalid = CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; // submodule proc assign proc$debug_module_mem_server_araddr = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[92:29] : - ssNoSynth_2_ar_buffer_enqw$wget[92:29] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_arburst = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[17:16] : - ssNoSynth_2_ar_buffer_enqw$wget[17:16] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_arcache = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[14:11] : - ssNoSynth_2_ar_buffer_enqw$wget[14:11] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_arid = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[97:93] : - ssNoSynth_2_ar_buffer_enqw$wget[97:93] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_arlen = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[28:21] : - ssNoSynth_2_ar_buffer_enqw$wget[28:21] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_arlock = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[15] : - ssNoSynth_2_ar_buffer_enqw$wget[15] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_arprot = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[10:8] : - ssNoSynth_2_ar_buffer_enqw$wget[10:8] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_arqos = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[7:4] : - ssNoSynth_2_ar_buffer_enqw$wget[7:4] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_arregion = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[3:0] : - ssNoSynth_2_ar_buffer_enqw$wget[3:0] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_arsize = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[20:18] : - ssNoSynth_2_ar_buffer_enqw$wget[20:18] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[20:18] ; + assign proc$debug_module_mem_server_arvalid = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; assign proc$debug_module_mem_server_awaddr = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[92:29] : - ssNoSynth_2_aw_buffer_enqw$wget[92:29] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_awburst = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[17:16] : - ssNoSynth_2_aw_buffer_enqw$wget[17:16] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_awcache = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[14:11] : - ssNoSynth_2_aw_buffer_enqw$wget[14:11] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_awid = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[97:93] : - ssNoSynth_2_aw_buffer_enqw$wget[97:93] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_awlen = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[28:21] : - ssNoSynth_2_aw_buffer_enqw$wget[28:21] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_awlock = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[15] : - ssNoSynth_2_aw_buffer_enqw$wget[15] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_awprot = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[10:8] : - ssNoSynth_2_aw_buffer_enqw$wget[10:8] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_awqos = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[7:4] : - ssNoSynth_2_aw_buffer_enqw$wget[7:4] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_awregion = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[3:0] : - ssNoSynth_2_aw_buffer_enqw$wget[3:0] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_awsize = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[20:18] : - ssNoSynth_2_aw_buffer_enqw$wget[20:18] ; - assign proc$debug_module_mem_server_bready = ssNoSynth_2_b_dwReady$whas ; - assign proc$debug_module_mem_server_rready = ssNoSynth_2_r_dwReady$whas ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[20:18] ; + assign proc$debug_module_mem_server_awvalid = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign proc$debug_module_mem_server_bready = + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign proc$debug_module_mem_server_rready = + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; assign proc$debug_module_mem_server_wdata = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[73:10] : - ssNoSynth_2_w_buffer_enqw$wget[73:10] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[73:10] ; assign proc$debug_module_mem_server_wlast = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[1] : - ssNoSynth_2_w_buffer_enqw$wget[1] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[1] ; assign proc$debug_module_mem_server_wstrb = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[9:2] : - ssNoSynth_2_w_buffer_enqw$wget[9:2] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[9:2] ; assign proc$debug_module_mem_server_wuser = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[0] : - ssNoSynth_2_w_buffer_enqw$wget[0] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[0] ; + assign proc$debug_module_mem_server_wvalid = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; assign proc$hart0_csr_mem_server_request_put = debug_module$hart0_csr_mem_client_request_get ; assign proc$hart0_fpr_mem_server_request_put = 70'h0 ; @@ -8314,71 +10649,21 @@ module mkCoreW(RST_N_dm_power_on_reset, debug_module$hart0_client_run_halt_request_get ; assign proc$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign proc$master0_arready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; - assign proc$master0_awready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; - assign proc$master0_bid = - tmp2_b_buffer_ff$EMPTY_N ? - tmp2_b_buffer_ff$D_OUT[6:2] : - tmp2_b_buffer_enqw$wget[6:2] ; - assign proc$master0_bresp = - tmp2_b_buffer_ff$EMPTY_N ? - tmp2_b_buffer_ff$D_OUT[1:0] : - tmp2_b_buffer_enqw$wget[1:0] ; - assign proc$master0_rdata = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[67:4] : - tmp2_r_buffer_enqw$wget[67:4] ; - assign proc$master0_rid = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[72:68] : - tmp2_r_buffer_enqw$wget[72:68] ; - assign proc$master0_rlast = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[1] : - tmp2_r_buffer_enqw$wget[1] ; - assign proc$master0_rresp = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[3:2] : - tmp2_r_buffer_enqw$wget[3:2] ; - assign proc$master0_ruser = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[0] : - tmp2_r_buffer_enqw$wget[0] ; - assign proc$master0_wready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; - assign proc$master1_arready = tmp0_ar_dwReady$whas ; - assign proc$master1_awready = tmp0_aw_dwReady$whas ; - assign proc$master1_bid = - tmp0_b_buffer_ff$EMPTY_N ? - tmp0_b_buffer_ff$D_OUT[5:2] : - tmp0_b_buffer_enqw$wget[5:2] ; - assign proc$master1_bresp = - tmp0_b_buffer_ff$EMPTY_N ? - tmp0_b_buffer_ff$D_OUT[1:0] : - tmp0_b_buffer_enqw$wget[1:0] ; - assign proc$master1_rdata = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[67:4] : - tmp0_r_buffer_enqw$wget[67:4] ; - assign proc$master1_rid = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[71:68] : - tmp0_r_buffer_enqw$wget[71:68] ; - assign proc$master1_rlast = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[1] : - tmp0_r_buffer_enqw$wget[1] ; - assign proc$master1_rresp = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[3:2] : - tmp0_r_buffer_enqw$wget[3:2] ; - assign proc$master1_ruser = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[0] : - tmp0_r_buffer_enqw$wget[0] ; - assign proc$master1_wready = tmp0_w_dwReady$whas ; + assign proc$master0_arready = tmp2_arNoSynth_buffer_ff$FULL_N ; + assign proc$master0_awready = tmp2_awNoSynth_buffer_ff$FULL_N ; + assign proc$master0_bid = tmp2_bNoSynth_src_peekWire$wget[6:2] ; + assign proc$master0_bresp = tmp2_bNoSynth_src_peekWire$wget[1:0] ; + assign proc$master0_bvalid = tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign proc$master0_rdata = tmp2_rNoSynth_src_peekWire$wget[67:4] ; + assign proc$master0_rid = tmp2_rNoSynth_src_peekWire$wget[72:68] ; + assign proc$master0_rlast = tmp2_rNoSynth_src_peekWire$wget[1] ; + assign proc$master0_rresp = tmp2_rNoSynth_src_peekWire$wget[3:2] ; + assign proc$master0_ruser = tmp2_rNoSynth_src_peekWire$wget[0] ; + assign proc$master0_rvalid = tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign proc$master0_wready = tmp2_wNoSynth_buffer_ff$FULL_N ; + assign proc$master1_b_put_val = proc_uncached_bSynth_snk_putWire$wget ; + assign proc$master1_r_put_val = + { proc_uncached_rSynth_snk_putWire$wget[71:1], 1'd0 } ; assign proc$non_maskable_interrupt_req_set_not_clear = 1'd0 ; assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; @@ -8395,17 +10680,15 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 || EN_start ; - assign proc$master0_bvalid = CAN_FIRE_RL_tmp2_b_forwardFlit ; - assign proc$master0_rvalid = CAN_FIRE_RL_tmp2_r_forwardFlit ; - assign proc$master1_bvalid = CAN_FIRE_RL_tmp0_b_forwardFlit ; - assign proc$master1_rvalid = CAN_FIRE_RL_tmp0_r_forwardFlit ; + assign proc$EN_master1_aw_drop = + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; + assign proc$EN_master1_w_drop = + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; + assign proc$EN_master1_b_put = CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; + assign proc$EN_master1_ar_drop = + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; + assign proc$EN_master1_r_put = CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; assign proc$EN_set_verbosity = EN_set_verbosity ; - assign proc$debug_module_mem_server_awvalid = - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; - assign proc$debug_module_mem_server_wvalid = - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; - assign proc$debug_module_mem_server_arvalid = - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; assign proc$EN_hart0_run_halt_server_request_put = CAN_FIRE_RL_ClientServerRequest ; assign proc$EN_hart0_run_halt_server_response_get = @@ -8428,122 +10711,207 @@ module mkCoreW(RST_N_dm_power_on_reset, assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - // submodule ssNoSynth_0_ar_buffer_ff - assign ssNoSynth_0_ar_buffer_ff$D_IN = ssNoSynth_0_ar_buffer_enqw$wget ; - assign ssNoSynth_0_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; - assign ssNoSynth_0_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; - assign ssNoSynth_0_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_arNoSynth_buffer_ff + assign ssNoSynth_0_arNoSynth_buffer_ff$D_IN = + ssNoSynth_0_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_0_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; + assign ssNoSynth_0_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; + assign ssNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_ar_buffer_firstValid - assign ssNoSynth_0_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_ar_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + // submodule ssNoSynth_0_arNoSynth_buffer_firstValid + assign ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; - // submodule ssNoSynth_0_aw_buffer_ff - assign ssNoSynth_0_aw_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; - assign ssNoSynth_0_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; - assign ssNoSynth_0_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; - assign ssNoSynth_0_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_awNoSynth_buffer_ff + assign ssNoSynth_0_awNoSynth_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; + assign ssNoSynth_0_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; + assign ssNoSynth_0_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; + assign ssNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_aw_buffer_firstValid - assign ssNoSynth_0_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_aw_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + // submodule ssNoSynth_0_awNoSynth_buffer_firstValid + assign ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; - // submodule ssNoSynth_0_w_buffer_ff - assign ssNoSynth_0_w_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; - assign ssNoSynth_0_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; - assign ssNoSynth_0_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; - assign ssNoSynth_0_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_bNoSynth_buffer_ff + assign ssNoSynth_0_bNoSynth_buffer_ff$D_IN = uncached_mem_shim_bff$D_OUT ; + assign ssNoSynth_0_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; + assign ssNoSynth_0_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; + assign ssNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_w_buffer_firstValid - assign ssNoSynth_0_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_w_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit ; + // submodule ssNoSynth_0_bNoSynth_buffer_firstValid + assign ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_bNoSynth_buffer_firstValid$EN = + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_1_ar_buffer_ff - assign ssNoSynth_1_ar_buffer_ff$D_IN = ssNoSynth_1_ar_buffer_enqw$wget ; - assign ssNoSynth_1_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; - assign ssNoSynth_1_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; - assign ssNoSynth_1_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_rNoSynth_buffer_ff + assign ssNoSynth_0_rNoSynth_buffer_ff$D_IN = uncached_mem_shim_rff$D_OUT ; + assign ssNoSynth_0_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; + assign ssNoSynth_0_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; + assign ssNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_ar_buffer_firstValid - assign ssNoSynth_1_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_ar_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + // submodule ssNoSynth_0_rNoSynth_buffer_firstValid + assign ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_rNoSynth_buffer_firstValid$EN = + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_1_aw_buffer_ff - assign ssNoSynth_1_aw_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; - assign ssNoSynth_1_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; - assign ssNoSynth_1_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; - assign ssNoSynth_1_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_wNoSynth_buffer_ff + assign ssNoSynth_0_wNoSynth_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; + assign ssNoSynth_0_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; + assign ssNoSynth_0_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; + assign ssNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_aw_buffer_firstValid - assign ssNoSynth_1_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_aw_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + // submodule ssNoSynth_0_wNoSynth_buffer_firstValid + assign ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; - // submodule ssNoSynth_1_w_buffer_ff - assign ssNoSynth_1_w_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; - assign ssNoSynth_1_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; - assign ssNoSynth_1_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; - assign ssNoSynth_1_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_arNoSynth_buffer_ff + assign ssNoSynth_1_arNoSynth_buffer_ff$D_IN = + ssNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; + assign ssNoSynth_1_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; + assign ssNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_w_buffer_firstValid - assign ssNoSynth_1_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_w_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + // submodule ssNoSynth_1_arNoSynth_buffer_firstValid + assign ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; - // submodule ssNoSynth_2_ar_buffer_ff - assign ssNoSynth_2_ar_buffer_ff$D_IN = ssNoSynth_2_ar_buffer_enqw$wget ; - assign ssNoSynth_2_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; - assign ssNoSynth_2_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; - assign ssNoSynth_2_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_awNoSynth_buffer_ff + assign ssNoSynth_1_awNoSynth_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; + assign ssNoSynth_1_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; + assign ssNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_ar_buffer_firstValid - assign ssNoSynth_2_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_ar_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + // submodule ssNoSynth_1_awNoSynth_buffer_firstValid + assign ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; - // submodule ssNoSynth_2_aw_buffer_ff - assign ssNoSynth_2_aw_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; - assign ssNoSynth_2_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; - assign ssNoSynth_2_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; - assign ssNoSynth_2_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_bNoSynth_buffer_ff + assign ssNoSynth_1_bNoSynth_buffer_ff$D_IN = + ssNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; + assign ssNoSynth_1_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; + assign ssNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_aw_buffer_firstValid - assign ssNoSynth_2_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_aw_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + // submodule ssNoSynth_1_bNoSynth_buffer_firstValid + assign ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_bNoSynth_buffer_firstValid$EN = + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_2_w_buffer_ff - assign ssNoSynth_2_w_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; - assign ssNoSynth_2_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; - assign ssNoSynth_2_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; - assign ssNoSynth_2_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_rNoSynth_buffer_ff + assign ssNoSynth_1_rNoSynth_buffer_ff$D_IN = + ssNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; + assign ssNoSynth_1_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; + assign ssNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_w_buffer_firstValid - assign ssNoSynth_2_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_w_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + // submodule ssNoSynth_1_rNoSynth_buffer_firstValid + assign ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_rNoSynth_buffer_firstValid$EN = + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_1_wNoSynth_buffer_ff + assign ssNoSynth_1_wNoSynth_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; + assign ssNoSynth_1_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; + assign ssNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_wNoSynth_buffer_firstValid + assign ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_arNoSynth_buffer_ff + assign ssNoSynth_2_arNoSynth_buffer_ff$D_IN = + ssNoSynth_2_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; + assign ssNoSynth_2_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; + assign ssNoSynth_2_arNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_arNoSynth_buffer_firstValid + assign ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_awNoSynth_buffer_ff + assign ssNoSynth_2_awNoSynth_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; + assign ssNoSynth_2_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; + assign ssNoSynth_2_awNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_awNoSynth_buffer_firstValid + assign ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_bNoSynth_buffer_ff + assign ssNoSynth_2_bNoSynth_buffer_ff$D_IN = + ssNoSynth_2_bNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; + assign ssNoSynth_2_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; + assign ssNoSynth_2_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_bNoSynth_buffer_firstValid + assign ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_bNoSynth_buffer_firstValid$EN = + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_2_rNoSynth_buffer_ff + assign ssNoSynth_2_rNoSynth_buffer_ff$D_IN = + ssNoSynth_2_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; + assign ssNoSynth_2_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; + assign ssNoSynth_2_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_rNoSynth_buffer_firstValid + assign ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_rNoSynth_buffer_firstValid$EN = + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_2_wNoSynth_buffer_ff + assign ssNoSynth_2_wNoSynth_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; + assign ssNoSynth_2_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; + assign ssNoSynth_2_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_wNoSynth_buffer_firstValid + assign ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; // submodule tagController_tmp_awreqff assign tagController_tmp_awreqff$D_IN = @@ -8579,505 +10947,543 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite || WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; - // submodule tmp0_b_buffer_ff - assign tmp0_b_buffer_ff$D_IN = tmp0_b_buffer_enqw$wget ; - assign tmp0_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_b_buffer_enqueue ; - assign tmp0_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_b_buffer_dequeue ; - assign tmp0_b_buffer_ff$CLR = 1'b0 ; + // submodule tmp2_arNoSynth_buffer_ff + assign tmp2_arNoSynth_buffer_ff$D_IN = tmp2_arNoSynth_buffer_enqw$wget ; + assign tmp2_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; + assign tmp2_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; + assign tmp2_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp0_b_buffer_firstValid - assign tmp0_b_buffer_firstValid$D_IN = 1'd1 ; - assign tmp0_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_b_dropFlit ; + // submodule tmp2_arNoSynth_buffer_firstValid + assign tmp2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; - // submodule tmp0_r_buffer_ff - assign tmp0_r_buffer_ff$D_IN = tmp0_r_buffer_enqw$wget ; - assign tmp0_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_r_buffer_enqueue ; - assign tmp0_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_r_buffer_dequeue ; - assign tmp0_r_buffer_ff$CLR = 1'b0 ; + // submodule tmp2_awNoSynth_buffer_ff + assign tmp2_awNoSynth_buffer_ff$D_IN = tmp2_awNoSynth_buffer_enqw$wget ; + assign tmp2_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; + assign tmp2_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; + assign tmp2_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp0_r_buffer_firstValid - assign tmp0_r_buffer_firstValid$D_IN = 1'd1 ; - assign tmp0_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_r_dropFlit ; + // submodule tmp2_awNoSynth_buffer_firstValid + assign tmp2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; - // submodule tmp2_b_buffer_ff - assign tmp2_b_buffer_ff$D_IN = + // submodule tmp2_bNoSynth_buffer_ff + assign tmp2_bNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; - assign tmp2_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_b_buffer_enqueue ; - assign tmp2_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_b_buffer_dequeue ; - assign tmp2_b_buffer_ff$CLR = 1'b0 ; + assign tmp2_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; + assign tmp2_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; + assign tmp2_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp2_b_buffer_firstValid - assign tmp2_b_buffer_firstValid$D_IN = 1'd1 ; - assign tmp2_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_b_dropFlit ; + // submodule tmp2_bNoSynth_buffer_firstValid + assign tmp2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; - // submodule tmp2_r_buffer_ff - assign tmp2_r_buffer_ff$D_IN = + // submodule tmp2_rNoSynth_buffer_ff + assign tmp2_rNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; - assign tmp2_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_r_buffer_enqueue ; - assign tmp2_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_r_buffer_dequeue ; - assign tmp2_r_buffer_ff$CLR = 1'b0 ; + assign tmp2_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; + assign tmp2_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; + assign tmp2_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp2_r_buffer_firstValid - assign tmp2_r_buffer_firstValid$D_IN = 1'd1 ; - assign tmp2_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_r_dropFlit ; + // submodule tmp2_rNoSynth_buffer_firstValid + assign tmp2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; + + // submodule tmp2_wNoSynth_buffer_ff + assign tmp2_wNoSynth_buffer_ff$D_IN = tmp2_wNoSynth_buffer_enqw$wget ; + assign tmp2_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; + assign tmp2_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; + assign tmp2_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule tmp2_wNoSynth_buffer_firstValid + assign tmp2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; // submodule uncached_mem_shim_arff assign uncached_mem_shim_arff$D_IN = - ssNoSynth_0_ar_buffer_ff$EMPTY_N ? - ssNoSynth_0_ar_buffer_ff$D_OUT : - ssNoSynth_0_ar_buffer_enqw$wget ; + slave_vector_0_arSynth_snk_putWire$wget ; assign uncached_mem_shim_arff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit && - uncached_mem_shim_arff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; assign uncached_mem_shim_arff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; assign uncached_mem_shim_arff$CLR = 1'b0 ; // submodule uncached_mem_shim_awff assign uncached_mem_shim_awff$D_IN = - ssNoSynth_0_aw_buffer_ff$EMPTY_N ? - ssNoSynth_0_aw_buffer_ff$D_OUT : - split_0_doPut$wget[171:74] ; + slave_vector_0_awSynth_snk_putWire$wget ; assign uncached_mem_shim_awff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit && - uncached_mem_shim_awff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; assign uncached_mem_shim_awff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; assign uncached_mem_shim_awff$CLR = 1'b0 ; // submodule uncached_mem_shim_bff assign uncached_mem_shim_bff$D_IN = - ug_uncached_mem_shim_master_u_b_putWire$wget[6:0] ; + uncached_mem_master_bSynth_snk_putWire$wget[6:0] ; assign uncached_mem_shim_bff$ENQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; assign uncached_mem_shim_bff$DEQ = - uncached_mem_shim_bff$EMPTY_N && ssNoSynth_0_b_dwReady$whas ; + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; assign uncached_mem_shim_bff$CLR = 1'b0 ; // submodule uncached_mem_shim_rff assign uncached_mem_shim_rff$D_IN = - { ug_uncached_mem_shim_master_u_r_putWire$wget[71:0], 1'd0 } ; + { uncached_mem_master_rSynth_snk_putWire$wget[71:0], 1'd0 } ; assign uncached_mem_shim_rff$ENQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; assign uncached_mem_shim_rff$DEQ = - uncached_mem_shim_rff$EMPTY_N && ssNoSynth_0_r_dwReady$whas ; + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; assign uncached_mem_shim_rff$CLR = 1'b0 ; // submodule uncached_mem_shim_wff - assign uncached_mem_shim_wff$D_IN = - ssNoSynth_0_w_buffer_ff$EMPTY_N ? - ssNoSynth_0_w_buffer_ff$D_OUT : - split_0_doPut$wget[73:0] ; + assign uncached_mem_shim_wff$D_IN = slave_vector_0_wSynth_snk_putWire$wget ; assign uncached_mem_shim_wff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit && - uncached_mem_shim_wff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; assign uncached_mem_shim_wff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; assign uncached_mem_shim_wff$CLR = 1'b0 ; // remaining internal signals - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207 = - ((IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203)) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 = + ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527)) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211 = - ((IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 = + ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 = - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207 + - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211 + - ((!IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 = + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 + + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 + + ((!IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) ? 2'd1 : 2'd0) ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306 = - ((IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302)) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 = + ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621)) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310 = - ((IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 = + ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 = - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306 + - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310 + - ((!IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 = + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 + + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 + + ((!IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) ? 2'd1 : 2'd0) ; - assign IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 = + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 = + ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 = + ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 = + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 + + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 + + ((!IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) ? + 2'd1 : + 2'd0) ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 = + ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 = + ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 = + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 + + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 + + ((!IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) ? + 2'd1 : + 2'd0) ; + assign IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 = (!ifcs_0_1_innerRoute$D_OUT[1] || - !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_innerRoute$D_OUT[2] && - ssNoSynth_2_ar_buffer_ff$FULL_N : + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_0_1_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 = + assign IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 = (!ifcs_0_innerRoute$D_OUT[1] || - !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426) ? + !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_0_innerRoute$D_OUT[2] && - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 : + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_0_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 = + assign IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 = (!ifcs_1_1_innerRoute$D_OUT[1] || - !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_innerRoute$D_OUT[2] && - ssNoSynth_2_ar_buffer_ff$FULL_N : + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_1_1_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 = + assign IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 = (!ifcs_1_innerRoute$D_OUT[1] || - !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426) ? + !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_1_innerRoute$D_OUT[2] && - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 : + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_1_innerRoute$D_OUT[1] ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94630 | y__h94631 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118613 | y__h118614 : arbiter_1_1_lastSelect ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94818 | y__h94819 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118801 | y__h118802 : arbiter_1_1_lastSelect_1 ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94999 | y__h95000 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118982 | y__h118983 : arbiter_1_1_firstHot ; - assign IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 = - (SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 || - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) ? - x__h82688 | y__h82689 : - arbiter_1_lastSelect_2 ; - assign IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 = - (SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 || - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) ? - x__h82829 | y__h82830 : - arbiter_1_firstHot_1 ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63404 | y__h63405 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85339 | y__h85340 : arbiter_1_lastSelect ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63592 | y__h63593 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85527 | y__h85528 : arbiter_1_lastSelect_1 ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63773 | y__h63774 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85708 | y__h85709 : arbiter_1_firstHot ; - assign IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 = - (SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 || - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) ? - x__h48921 | y__h48922 : + assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 = + (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? + x__h106164 | y__h106165 : + arbiter_1_lastSelect_2 ; + assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 = + (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? + x__h106305 | y__h106306 : + arbiter_1_firstHot_1 ; + assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 = + (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? + x__h70391 | y__h70392 : arbiter_lastSelect ; - assign IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 = - (SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 || - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) ? - x__h49062 | y__h49063 : + assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 = + (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? + x__h70532 | y__h70533 : arbiter_firstHot ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941 = - ((debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937)) ? - 2'd1 : - 2'd0 ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945 = - ((debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937) ? - 2'd1 : - 2'd0 ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 = - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941 + - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945 + - ((!debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) ? - 2'd1 : - 2'd0) ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 = - ((merged_0_flitLeft == 8'd0) ? - !proc$master1_awvalid || !proc$master1_wvalid : - !proc$master1_wvalid) || - merged_0_flitLeft != 8'd0 ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250 = - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && - (merged_0_flitLeft != 8'd0 || - !ifcs_0_noRoute_inner_pendingReq && proc$master1_awvalid) ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 = + assign IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 = (merged_0_flitLeft == 8'd0) ? - proc$master1_awvalid && proc$master1_wvalid : - proc$master1_wvalid ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 = - proc$master1_awaddr < + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N : + merged_0_wff$EMPTY_N ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 = + merged_0_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195 = - x__h37445 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 = - proc$master1_awaddr < soc_map$m_plic_addr_range[127:64] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203 = - x__h37480 < soc_map$m_plic_addr_range[63:0] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 = - ((merged_1_flitLeft == 8'd0) ? - !debug_module$master_awvalid || !debug_module$master_wvalid : - !debug_module$master_wvalid) || - merged_1_flitLeft != 8'd0 ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350 = - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - (merged_1_flitLeft != 8'd0 || - !ifcs_1_noRoute_inner_pendingReq && - debug_module$master_awvalid) ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 = + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519 = + x__h56232 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 = + merged_0_outflit$wget[166:103] < + soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527 = + x__h56267 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 = + (CAN_FIRE_RL_merged_0_passFlit && !merged_0_outflit$wget[171]) ? + { 1'd0, merged_0_outflit$wget[170:0] } : + { 98'h2AAAAAAAAAAAAAAAAAAAAAAAA, + CAN_FIRE_RL_merged_0_passFlit ? + merged_0_outflit$wget[73:0] : + merged_0_wff$D_OUT } ; + assign IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 = + CAN_FIRE_RL_merged_0_passFlit ? + !merged_0_outflit$wget[1] : + !merged_0_wff$D_OUT[1] ; + assign IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 = + CAN_FIRE_RL_merged_0_passFlit ? + merged_0_outflit$wget[1] : + merged_0_wff$D_OUT[1] ; + assign IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 = (merged_1_flitLeft == 8'd0) ? - debug_module$master_awvalid && debug_module$master_wvalid : - debug_module$master_wvalid ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 = - debug_module$master_awaddr < + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N : + merged_1_wff$EMPTY_N ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 = + merged_1_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297 = - x__h40162 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 = - debug_module$master_awaddr < soc_map$m_plic_addr_range[127:64] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 = - x__h40187 < soc_map$m_plic_addr_range[63:0] ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854 = - ((proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - (proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850)) ? - 2'd1 : - 2'd0 ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858 = - ((proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - !proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850) ? - 2'd1 : - 2'd0 ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 = - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854 + - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858 + - ((!proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) ? - 2'd1 : - 2'd0) ; - assign IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425 = + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616 = + x__h59744 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 = + merged_1_outflit$wget[166:103] < + soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621 = + x__h59769 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 = + (CAN_FIRE_RL_merged_1_passFlit && !merged_1_outflit$wget[171]) ? + { 1'd1, merged_1_outflit$wget[170:0] } : + { 98'h2AAAAAAAAAAAAAAAAAAAAAAAA, + CAN_FIRE_RL_merged_1_passFlit ? + merged_1_outflit$wget[73:0] : + merged_1_wff$D_OUT } ; + assign IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 = + CAN_FIRE_RL_merged_1_passFlit ? + !merged_1_outflit$wget[1] : + !merged_1_wff$D_OUT[1] ; + assign IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 = + CAN_FIRE_RL_merged_1_passFlit ? + merged_1_outflit$wget[1] : + merged_1_wff$D_OUT[1] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 = + addr__h93758 < soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218 = + x__h93834 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 = + addr__h93758 < soc_map$m_plic_addr_range[127:64] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223 = + x__h93859 < soc_map$m_plic_addr_range[63:0] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 = + addr__h96375 < soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313 = + x__h96451 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 = + addr__h96375 < soc_map$m_plic_addr_range[127:64] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318 = + x__h96476 < soc_map$m_plic_addr_range[63:0] ; + assign IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 = (split_0_flitLeft == 8'd0) ? - ssNoSynth_0_aw_buffer_ff$FULL_N && - ssNoSynth_0_w_buffer_ff$FULL_N : - ssNoSynth_0_w_buffer_ff$FULL_N ; - assign IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426 = + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 = (split_1_flitLeft == 8'd0) ? - ssNoSynth_1_aw_buffer_ff$FULL_N && - ssNoSynth_1_w_buffer_ff$FULL_N : - ssNoSynth_1_w_buffer_ff$FULL_N ; - assign IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 = + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 = (split_2_flitLeft == 8'd0) ? - ssNoSynth_2_aw_buffer_ff$FULL_N && - ssNoSynth_2_w_buffer_ff$FULL_N : - ssNoSynth_2_w_buffer_ff$FULL_N ; - assign SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22 = - {2{SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331}} ; - assign SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17 = - {2{SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138}} ; - assign SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12 = - {2{SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698}} ; - assign SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7 = - {2{SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495}} ; - assign SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 = - x__h94158 | y__h94159 ; + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N ; + assign SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22 = + {2{SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750}} ; + assign SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12 = + {2{SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059}} ; + assign SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17 = + {2{SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553}} ; + assign SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7 = + {2{SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852}} ; + assign SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 = + x__h118141 | y__h118142 ; assign SEXT_arbiter_1_1_firstHot__q19 = {2{arbiter_1_1_firstHot}} ; - assign SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 = - x__h94022 | y__h94023 ; + assign SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 = + x__h118005 | y__h118006 ; assign SEXT_arbiter_1_1_lastSelect_1__q21 = {2{arbiter_1_1_lastSelect_1}} ; - assign SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 = - x__h93871 | y__h93872 ; + assign SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 = + x__h117854 | y__h117855 ; assign SEXT_arbiter_1_1_lastSelect__q20 = {2{arbiter_1_1_lastSelect}} ; - assign SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138 = - x__h82323 | y__h82324 ; + assign SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 = + x__h84867 | y__h84868 ; + assign SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 = + x__h105799 | y__h105800 ; assign SEXT_arbiter_1_firstHot_1__q15 = {2{arbiter_1_firstHot_1}} ; - assign SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 = - x__h62932 | y__h62933 ; assign SEXT_arbiter_1_firstHot__q9 = {2{arbiter_1_firstHot}} ; - assign SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 = - x__h62796 | y__h62797 ; + assign SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 = + x__h84580 | y__h84581 ; + assign SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 = + x__h84731 | y__h84732 ; assign SEXT_arbiter_1_lastSelect_1__q11 = {2{arbiter_1_lastSelect_1}} ; - assign SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 = - x__h82220 | y__h82221 ; + assign SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 = + x__h105696 | y__h105697 ; assign SEXT_arbiter_1_lastSelect_2__q16 = {2{arbiter_1_lastSelect_2}} ; - assign SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 = - x__h62645 | y__h62646 ; assign SEXT_arbiter_1_lastSelect__q10 = {2{arbiter_1_lastSelect}} ; - assign SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495 = - x__h48556 | y__h48557 ; + assign SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 = + x__h70026 | y__h70027 ; assign SEXT_arbiter_firstHot__q5 = {2{arbiter_firstHot}} ; - assign SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 = - x__h48453 | y__h48454 ; + assign SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 = + x__h69923 | y__h69924 ; assign SEXT_arbiter_lastSelect__q6 = {2{arbiter_lastSelect}} ; - assign SEXT_x2747__q18 = {2{x__h82747}} ; - assign SEXT_x3466__q13 = {2{x__h63466}} ; - assign SEXT_x3500__q14 = {2{x__h63500}} ; - assign SEXT_x4692__q23 = {2{x__h94692}} ; - assign SEXT_x4726__q24 = {2{x__h94726}} ; - assign SEXT_x8980__q8 = {2{x__h48980}} ; - assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245 = - x__h12617 + y__h12618 ; - assign a_awid__h38523 = { 1'd0, proc$master1_awid } ; - assign a_awid__h41194 = { 1'd1, debug_module$master_awid } ; - assign araddr__h15540 = + assign SEXT_x0450__q8 = {2{x__h70450}} ; + assign SEXT_x06223__q18 = {2{x__h106223}} ; + assign SEXT_x18675__q23 = {2{x__h118675}} ; + assign SEXT_x18709__q24 = {2{x__h118709}} ; + assign SEXT_x5401__q13 = {2{x__h85401}} ; + assign SEXT_x5435__q14 = {2{x__h85435}} ; + assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224 = + x__h12420 + y__h12421 ; + assign addr__h93758 = + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:29] : + proc$master1_ar_peek[92:29] ; + assign addr__h96375 = + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:29] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[92:29] ; + assign araddr__h15343 = { 24'd0, tagController_tmp_tagCon$memory_request_get[140:101] } ; - assign arcache__h15545 = + assign arcache__h15348 = tagController_tmp_tagCon$memory_request_get[8] ? 4'd0 : 4'd15 ; - assign arlen__h15541 = + assign arlen__h15344 = { 5'd0, tagController_tmp_tagCon$memory_request_get[5:3] } ; - assign aw_awaddr__h10808 = tmp__h10591 + { 60'd0, x__h10883 } ; - assign aw_awsize_val__h12547 = - _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[0] ? + assign aw_awaddr__h10611 = tmp__h10394 + { 60'd0, x__h10686 } ; + assign aw_awsize_val__h12350 = + _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[0] ? 3'd0 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[1] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[1] ? 3'd1 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[2] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[2] ? 3'd2 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[3] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[3] ? 3'd3 : 3'd4))) ; - assign debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932 = - x__h74126 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937 = - x__h74151 < soc_map$m_plic_addr_range[63:0] ; - assign debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 = - debug_module$master_araddr < - soc_map$m_mem0_controller_addr_range[127:64] ; - assign debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 = - debug_module$master_araddr < soc_map$m_plic_addr_range[127:64] ; - assign fatReq_arid__h72223 = { 1'd0, proc$master1_arid } ; - assign fatReq_arid__h74597 = { 1'd1, debug_module$master_arid } ; - assign proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845 = - x__h71737 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850 = - x__h71762 < soc_map$m_plic_addr_range[63:0] ; - assign proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 = - proc$master1_araddr < - soc_map$m_mem0_controller_addr_range[127:64] ; - assign proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 = - proc$master1_araddr < soc_map$m_plic_addr_range[127:64] ; - assign reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669 = + assign fatReq_arid__h94342 = + { 1'd0, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[96:93] : + proc$master1_ar_peek[96:93] } ; + assign fatReq_arid__h96944 = + { 1'd1, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[96:93] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[96:93] } ; + assign reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 = CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget || CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget || CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget ; - assign reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302 = + assign reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 = CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget || CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget || CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget ; - assign split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 = - CAN_FIRE_RL_sink_selected && + assign split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 = + CAN_FIRE_RL_sinks_0_doPut && (split_0_doPut$wget[172] || - ssNoSynth_0_aw_buffer_ff$FULL_N && - ssNoSynth_0_w_buffer_ff$FULL_N) ; - assign split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 = - CAN_FIRE_RL_sink_selected_1 && + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; + assign split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 = + CAN_FIRE_RL_sinks_1_doPut && (split_1_doPut$wget[172] || - ssNoSynth_1_aw_buffer_ff$FULL_N && - ssNoSynth_1_w_buffer_ff$FULL_N) ; - assign split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 = - CAN_FIRE_RL_sink_selected_2 && + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; + assign split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 = + CAN_FIRE_RL_sinks_2_doPut && (split_2_doPut$wget[172] || - ssNoSynth_2_aw_buffer_ff$FULL_N && - ssNoSynth_2_w_buffer_ff$FULL_N) ; - assign state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193 = - state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && - ((!ifcs_0_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 : - ifcs_0_1_innerRoute$D_OUT[0]) ; - assign state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233 = - state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && - ((!ifcs_1_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 : - ifcs_1_1_innerRoute$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400 = + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; + assign state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 = + state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && + ((!ifcs_0_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_0_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_0_routeBack$D_OUT[0]) ; + assign state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 = + state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && + ((!ifcs_1_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_1_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_1_routeBack$D_OUT[0]) ; + assign state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 = + state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && + ((!ifcs_2_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_2_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_2_routeBack$D_OUT[0]) ; + assign state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 = state_1_1_1 && activeSource_1_1_0 && ifcs_0_1_routeBack$EMPTY_N && ((!ifcs_0_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436 = + assign state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 = state_1_1_1 && activeSource_1_1_1_1 && ifcs_1_1_routeBack$EMPTY_N && ((!ifcs_1_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472 = + assign state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 = state_1_1_1 && activeSource_1_1_2 && ifcs_2_1_routeBack$EMPTY_N && ((!ifcs_2_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761 = - state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && - ((!ifcs_0_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_0_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_0_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794 = - state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && - ((!ifcs_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_1_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828 = - state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && - ((!ifcs_2_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_2_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_2_routeBack$D_OUT[0]) ; - assign state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556 = + assign state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 = + state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && + ((!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : + ifcs_0_1_innerRoute$D_OUT[0]) ; + assign state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 = + state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && + ((!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : + ifcs_1_1_innerRoute$D_OUT[0]) ; + assign state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 = state && activeSource_0 && ifcs_0_innerRoute$EMPTY_N && ((!ifcs_0_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0]) ; - assign state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600 = + assign state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 = state && activeSource_1 && ifcs_1_innerRoute$EMPTY_N && ((!ifcs_1_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0]) ; assign tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4 = tagController_tmp_shimMaster_arff_rv$port1__read[98:0] ; @@ -9085,31 +11491,48 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_awff_rv$port1__read[98:0] ; assign tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3 = tagController_tmp_shimMaster_wff_rv$port1__read[72:0] ; - assign tmp__h10591 = { 24'd0, x__h10840 } ; - assign tmp__h8366 = + assign tmp__h10394 = { 24'd0, x__h10643 } ; + assign tmp__h8169 = tagController_tmp_awreqff$D_OUT[92:29] + tagController_tmp_addrOffset ; assign uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1 = uncached_mem_shim_wff$D_OUT[73:1] ; - assign v_araddr__h15557 = + assign v_araddr__h15360 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - araddr__h15540 : + araddr__h15343 : 64'hAAAAAAAAAAAAAAAA ; - assign v_arid__h15556 = + assign v_arid__h15359 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[100:95] : 6'd0 ; - assign v_arlen__h15558 = + assign v_arlen__h15361 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - arlen__h15541 : + arlen__h15344 : 8'd0 ; - assign v_arsize_val__h15603 = + assign v_arsize_val__h15406 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[2:0] : 3'b0 ; - assign x__h10840 = + assign x__h100325 = + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[72:68] : + ssNoSynth_2_rNoSynth_buffer_enqw$wget[72:68] ; + assign x__h105696 = + SEXT_arbiter_1_lastSelect_2__q16[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h105799 = + SEXT_arbiter_1_firstHot_1__q15[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h106164 = + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & + arbiter_1_firstHot_1 ; + assign x__h106223 = + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 && + SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 ; + assign x__h106305 = SEXT_x06223__q18[0] & arbiter_1_firstHot_1 ; + assign x__h10643 = { tagController_tmp_tagCon$memory_request_get[140:104], 3'd0 } ; - assign x__h10883 = + assign x__h10686 = tagController_tmp_tagCon$memory_request_get[81] ? 4'd0 : (tagController_tmp_tagCon$memory_request_get[82] ? @@ -9127,227 +11550,234 @@ module mkCoreW(RST_N_dm_power_on_reset, (tagController_tmp_tagCon$memory_request_get[88] ? 4'd7 : 4'd8))))))) ; - assign x__h12617 = x__h12629 + y__h12630 ; - assign x__h12629 = x__h12641 + y__h12642 ; - assign x__h12641 = x__h12653 + y__h12654 ; - assign x__h12653 = x__h12665 + y__h12666 ; - assign x__h12665 = x__h12677 + y__h12678 ; - assign x__h12677 = x__h12689 + y__h12690 ; - assign x__h12689 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; - assign x__h14213 = - tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; - assign x__h15621 = - (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - arcache__h15545 : - 4'd0 ; - assign x__h37445 = - proc$master1_awaddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h37480 = proc$master1_awaddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h40162 = - debug_module$master_awaddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h40187 = - debug_module$master_awaddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h48453 = - SEXT_arbiter_lastSelect__q6[0] & - (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; - assign x__h48556 = - SEXT_arbiter_firstHot__q5[0] & - (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; - assign x__h48921 = - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7[0] & - arbiter_firstHot ; - assign x__h48980 = - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495 && - SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 ; - assign x__h49062 = SEXT_x8980__q8[0] & arbiter_firstHot ; - assign x__h62645 = x__h62647 | y__h62648 ; - assign x__h62647 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h62796 = x__h62798 | y__h62799 ; - assign x__h62798 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h62932 = x__h62934 | y__h62935 ; - assign x__h62934 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h63404 = x__h63406 | y__h63407 ; - assign x__h63406 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_firstHot ; - assign x__h63466 = - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 && - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 ; - assign x__h63500 = - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 && - SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 ; - assign x__h63592 = x__h63594 | y__h63595 ; - assign x__h63594 = SEXT_x3466__q13[0] & arbiter_1_firstHot ; - assign x__h63773 = x__h63775 | y__h63776 ; - assign x__h63775 = SEXT_x3500__q14[0] & arbiter_1_firstHot ; - assign x__h71737 = - proc$master1_araddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h71762 = proc$master1_araddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h74126 = - debug_module$master_araddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h74151 = - debug_module$master_araddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h8207 = - tagController_tmp_addrOffset + - (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; - assign x__h82220 = - SEXT_arbiter_1_lastSelect_2__q16[0] & - (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; - assign x__h82323 = - SEXT_arbiter_1_firstHot_1__q15[0] & - (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; - assign x__h82688 = - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17[0] & - arbiter_1_firstHot_1 ; - assign x__h82747 = - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138 && - SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 ; - assign x__h82829 = SEXT_x2747__q18[0] & arbiter_1_firstHot_1 ; - assign x__h93871 = x__h93873 | y__h93874 ; - assign x__h93873 = + assign x__h117854 = x__h117856 | y__h117857 ; + assign x__h117856 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94022 = x__h94024 | y__h94025 ; - assign x__h94024 = + assign x__h118005 = x__h118007 | y__h118008 ; + assign x__h118007 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94158 = x__h94160 | y__h94161 ; - assign x__h94160 = + assign x__h118141 = x__h118143 | y__h118144 ; + assign x__h118143 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94630 = x__h94632 | y__h94633 ; - assign x__h94632 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign x__h118613 = x__h118615 | y__h118616 ; + assign x__h118615 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_firstHot ; - assign x__h94692 = - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 && - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 ; - assign x__h94726 = - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 && - SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 ; - assign x__h94818 = x__h94820 | y__h94821 ; - assign x__h94820 = SEXT_x4692__q23[0] & arbiter_1_1_firstHot ; - assign x__h94999 = x__h95001 | y__h95002 ; - assign x__h95001 = SEXT_x4726__q24[0] & arbiter_1_1_firstHot ; - assign x_port1__read__h72781 = + assign x__h118675 = + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 ; + assign x__h118709 = + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && + SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 ; + assign x__h118801 = x__h118803 | y__h118804 ; + assign x__h118803 = SEXT_x18675__q23[0] & arbiter_1_1_firstHot ; + assign x__h118982 = x__h118984 | y__h118985 ; + assign x__h118984 = SEXT_x18709__q24[0] & arbiter_1_1_firstHot ; + assign x__h12420 = x__h12432 + y__h12433 ; + assign x__h12432 = x__h12444 + y__h12445 ; + assign x__h12444 = x__h12456 + y__h12457 ; + assign x__h12456 = x__h12468 + y__h12469 ; + assign x__h12468 = x__h12480 + y__h12481 ; + assign x__h12480 = x__h12492 + y__h12493 ; + assign x__h12492 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; + assign x__h14016 = + tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; + assign x__h15424 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + arcache__h15348 : + 4'd0 ; + assign x__h56232 = + merged_0_outflit$wget[166:103] - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h56267 = + merged_0_outflit$wget[166:103] - + soc_map$m_plic_addr_range[127:64] ; + assign x__h59744 = + merged_1_outflit$wget[166:103] - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h59769 = + merged_1_outflit$wget[166:103] - + soc_map$m_plic_addr_range[127:64] ; + assign x__h62625 = + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[6:2] : + uncached_mem_shim_bff$D_OUT[6:2] ; + assign x__h63516 = + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[6:2] : + ssNoSynth_1_bNoSynth_buffer_enqw$wget[6:2] ; + assign x__h64407 = + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[6:2] : + ssNoSynth_2_bNoSynth_buffer_enqw$wget[6:2] ; + assign x__h69923 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h70026 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h70391 = + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & + arbiter_firstHot ; + assign x__h70450 = + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 && + SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 ; + assign x__h70532 = SEXT_x0450__q8[0] & arbiter_firstHot ; + assign x__h8010 = + tagController_tmp_addrOffset + + (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; + assign x__h84580 = x__h84582 | y__h84583 ; + assign x__h84582 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h84731 = x__h84733 | y__h84734 ; + assign x__h84733 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h84867 = x__h84869 | y__h84870 ; + assign x__h84869 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h85339 = x__h85341 | y__h85342 ; + assign x__h85341 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_firstHot ; + assign x__h85401 = + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 ; + assign x__h85435 = + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && + SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 ; + assign x__h85527 = x__h85529 | y__h85530 ; + assign x__h85529 = SEXT_x5401__q13[0] & arbiter_1_firstHot ; + assign x__h85708 = x__h85710 | y__h85711 ; + assign x__h85710 = SEXT_x5435__q14[0] & arbiter_1_firstHot ; + assign x__h93834 = + addr__h93758 - soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h93859 = addr__h93758 - soc_map$m_plic_addr_range[127:64] ; + assign x__h94920 = + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[28:21] : + proc$master1_ar_peek[28:21] ; + assign x__h95023 = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? ifcs_0_1_noRoute_flitCount$port0__write_1 : ifcs_0_1_noRoute_flitCount ; - assign x_port1__read__h75154 = + assign x__h96451 = + addr__h96375 - soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h96476 = addr__h96375 - soc_map$m_plic_addr_range[127:64] ; + assign x__h97519 = + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[28:21] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[28:21] ; + assign x__h97622 = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? ifcs_1_1_noRoute_flitCount$port0__write_1 : ifcs_1_1_noRoute_flitCount ; - assign x_rdata__h25045 = - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[67:4] : - msNoSynth_0_r_buffer_enqw$wget[67:4] ; - assign x_rid__h25044 = - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[71:68] : - msNoSynth_0_r_buffer_enqw$wget[71:68] ; - assign y__h12618 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; - assign y__h12630 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; - assign y__h12642 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; - assign y__h12654 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; - assign y__h12666 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; - assign y__h12678 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; - assign y__h12690 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; - assign y__h48454 = - SEXT_arbiter_firstHot__q5[0] & - (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; - assign y__h48557 = - SEXT_arbiter_lastSelect__q6[0] & - (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; - assign y__h48922 = SEXT_x8980__q8[0] & arbiter_lastSelect ; - assign y__h49063 = - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7[0] & - arbiter_lastSelect ; - assign y__h62646 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62648 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h62797 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62799 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h62933 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62935 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h63405 = SEXT_x3500__q14[0] & arbiter_1_lastSelect ; - assign y__h63407 = SEXT_x3466__q13[0] & arbiter_1_lastSelect_1 ; - assign y__h63593 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_lastSelect ; - assign y__h63595 = SEXT_x3500__q14[0] & arbiter_1_lastSelect_1 ; - assign y__h63774 = SEXT_x3466__q13[0] & arbiter_1_lastSelect ; - assign y__h63776 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_lastSelect_1 ; - assign y__h82221 = + assign x__h98415 = + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[72:68] : + uncached_mem_shim_rff$D_OUT[72:68] ; + assign x__h99370 = + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[72:68] : + ssNoSynth_1_rNoSynth_buffer_enqw$wget[72:68] ; + assign y__h105697 = SEXT_arbiter_1_firstHot_1__q15[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; - assign y__h82324 = + assign y__h105800 = SEXT_arbiter_1_lastSelect_2__q16[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; - assign y__h82689 = SEXT_x2747__q18[0] & arbiter_1_lastSelect_2 ; - assign y__h82830 = - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17[0] & + assign y__h106165 = SEXT_x06223__q18[0] & arbiter_1_lastSelect_2 ; + assign y__h106306 = + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & arbiter_1_lastSelect_2 ; - assign y__h93872 = + assign y__h117855 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h93874 = + assign y__h117857 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94023 = + assign y__h118006 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h94025 = + assign y__h118008 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94159 = + assign y__h118142 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h94161 = + assign y__h118144 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94631 = SEXT_x4726__q24[0] & arbiter_1_1_lastSelect ; - assign y__h94633 = SEXT_x4692__q23[0] & arbiter_1_1_lastSelect_1 ; - assign y__h94819 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign y__h118614 = SEXT_x18709__q24[0] & arbiter_1_1_lastSelect ; + assign y__h118616 = SEXT_x18675__q23[0] & arbiter_1_1_lastSelect_1 ; + assign y__h118802 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect ; - assign y__h94821 = SEXT_x4726__q24[0] & arbiter_1_1_lastSelect_1 ; - assign y__h95000 = SEXT_x4692__q23[0] & arbiter_1_1_lastSelect ; - assign y__h95002 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign y__h118804 = SEXT_x18709__q24[0] & arbiter_1_1_lastSelect_1 ; + assign y__h118983 = SEXT_x18675__q23[0] & arbiter_1_1_lastSelect ; + assign y__h118985 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect_1 ; + assign y__h12421 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; + assign y__h12433 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; + assign y__h12445 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; + assign y__h12457 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; + assign y__h12469 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; + assign y__h12481 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; + assign y__h12493 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; + assign y__h69924 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h70027 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h70392 = SEXT_x0450__q8[0] & arbiter_lastSelect ; + assign y__h70533 = + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & + arbiter_lastSelect ; + assign y__h84581 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84583 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h84732 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84734 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h84868 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84870 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h85340 = SEXT_x5435__q14[0] & arbiter_1_lastSelect ; + assign y__h85342 = SEXT_x5401__q13[0] & arbiter_1_lastSelect_1 ; + assign y__h85528 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_lastSelect ; + assign y__h85530 = SEXT_x5435__q14[0] & arbiter_1_lastSelect_1 ; + assign y__h85709 = SEXT_x5401__q13[0] & arbiter_1_lastSelect ; + assign y__h85711 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_lastSelect_1 ; // handling of inlined registers @@ -9677,15 +12107,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h22825 = $stime; + v__h27371 = $stime; #0; end - v__h22819 = v__h22825 / 32'd10; + v__h27365 = v__h27371 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h22819, + v__h27365, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -9693,29 +12123,29 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h22968 = $stime; + v__h27514 = $stime; #0; end - v__h22962 = v__h22968 / 32'd10; + v__h27508 = v__h27514 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h22962, + v__h27508, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && - !SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 && - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) + !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && - !SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 && - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) + !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && @@ -9724,7 +12154,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h50461 = $time; + v__h71925 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -9734,7 +12164,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h50461, + v__h71925, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && @@ -9843,13 +12273,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) begin - v__h49850 = $time; + v__h71314 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h49850, + v__h71314, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) @@ -9861,7 +12291,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h54470 = $time; + v__h75934 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -9871,7 +12301,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h54470, + v__h75934, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && @@ -9980,13 +12410,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) begin - v__h53859 = $time; + v__h75323 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h53859, + v__h75323, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) @@ -10008,15 +12438,352 @@ module mkCoreW(RST_N_dm_power_on_reset, if ((WILL_FIRE_RL_sink_selected || WILL_FIRE_RL_sink_selected_1) && WILL_FIRE_RL_sink_selected_2) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected,\n RL_sink_selected_1] and [RL_sink_selected_2] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h87100 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h87100, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + begin + v__h86719 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h86719, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h89170 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h89170, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + begin + v__h88789 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h88789, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h91069 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h91069, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + begin + v__h90688 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h90688, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && + (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || + WILL_FIRE_RL_source_selected_3 || + WILL_FIRE_RL_burst_3) && + (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && - !SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 && - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) + !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && - !SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 && - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) + !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && @@ -10025,7 +12792,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h84222 = $time; + v__h107698 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10035,7 +12802,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h84222, + v__h107698, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && @@ -10144,13 +12911,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) begin - v__h83611 = $time; + v__h107087 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h83611, + v__h107087, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) @@ -10162,7 +12929,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h87115 = $time; + v__h110591 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10172,7 +12939,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h87115, + v__h110591, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && @@ -10281,13 +13048,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) begin - v__h86504 = $time; + v__h109980 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h86504, + v__h109980, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) @@ -10309,575 +13076,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if ((WILL_FIRE_RL_sink_selected_5 || WILL_FIRE_RL_sink_selected_6) && WILL_FIRE_RL_sink_selected_7) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5,\n RL_sink_selected_6] and [RL_sink_selected_7] ) fired in the same clock\n cycle.\n"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - split_0_doPut$wget[1] && - split_0_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - split_0_doPut$wget[1] && - split_0_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - !split_0_doPut$wget[1] && - split_0_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - !split_0_doPut$wget[1] && - split_0_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - split_1_doPut$wget[1] && - split_1_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - split_1_doPut$wget[1] && - split_1_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - !split_1_doPut$wget[1] && - split_1_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - !split_1_doPut$wget[1] && - split_1_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - split_2_doPut$wget[1] && - split_2_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - split_2_doPut$wget[1] && - split_2_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - !split_2_doPut$wget[1] && - split_2_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - !split_2_doPut$wget[1] && - split_2_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_arbitrate_1 && - !SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 && - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) - $display("mkOneHotArbiter: next method should not be run with no pending request"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_arbitrate_1 && - !SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 && - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h65165 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h65165, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - begin - v__h64784 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h64784, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h67235 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h67235, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - begin - v__h66854 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h66854, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h69134 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h69134, - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - begin - v__h68753 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h68753, - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && - (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || - WILL_FIRE_RL_source_selected_3 || - WILL_FIRE_RL_burst_3) && - (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && - WILL_FIRE_RL_ifcs_0_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_drainFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && - merged_0_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && - merged_0_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && - merged_0_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && - merged_0_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && - WILL_FIRE_RL_ifcs_0_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && - WILL_FIRE_RL_ifcs_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && - !SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 && - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) + !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && - !SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 && - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) + !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && @@ -10885,7 +13094,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h96395 = $time; + v__h120378 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10894,7 +13103,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h96395, + v__h120378, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && @@ -10969,13 +13178,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) begin - v__h96014 = $time; + v__h119997 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h96014, + v__h119997, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) @@ -10986,7 +13195,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h98886 = $time; + v__h122869 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10995,7 +13204,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h98886, + v__h122869, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && @@ -11070,13 +13279,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) begin - v__h98505 = $time; + v__h122488 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h98505, + v__h122488, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) @@ -11090,7 +13299,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h101196 = $time; + v__h125179 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -11099,7 +13308,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h101196, + v__h125179, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && @@ -11174,13 +13383,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) begin - v__h100815 = $time; + v__h124798 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h100815, + v__h124798, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) @@ -11204,183 +13413,576 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sink_selected_8 && WILL_FIRE_RL_sink_selected_9) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_8] and\n [RL_sink_selected_9] ) fired in the same clock cycle.\n"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_2_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_drainFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && + merged_0_flitLeft > 8'd1) + $display("%m - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && + merged_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && + merged_0_flitLeft == 8'd1) + $display("%m - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && + merged_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_drainFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_sinks_1_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && - WILL_FIRE_RL_ifcs_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_drainFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_drainFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && - merged_1_flitLeft > 8'd1) - $display("Expecting more write data flits"); + if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && + merged_1_flitLeft > 8'd1) + $display("%m - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && - merged_1_flitLeft > 8'd1) - $finish(32'd0); + if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && + merged_1_flitLeft > 8'd1) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && - merged_1_flitLeft == 8'd1) - $display("Expecting last write data flit"); + if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && + merged_1_flitLeft == 8'd1) + $display("%m - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && - merged_1_flitLeft == 8'd1) - $finish(32'd0); + if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && + merged_1_flitLeft == 8'd1) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_drainFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && - WILL_FIRE_RL_ifcs_0_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && WILL_FIRE_RL_ifcs_1_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_0_warnDoPut_1) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_warnDoPut_1) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h103640 = $stime; + v__h128907 = $stime; #0; end - v__h103634 = v__h103640 / 32'd10; + v__h128901 = v__h128907 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h103634, + v__h128901, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_2_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_1_firstFlit && + WILL_FIRE_RL_ifcs_2_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_drainFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_2_1_firstFlit && - WILL_FIRE_RL_ifcs_2_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_drainFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v index 7f9992f..dcd475e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:17 BST 2020 +// On Wed Jun 24 20:17:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v index 5e7c23b..7c9f3fb 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:41 BST 2020 +// On Wed Jun 24 20:09:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v index cbaeaa8..36c61c8 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:40 BST 2020 +// On Wed Jun 24 20:09:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v index 4c90df8..fb0d30f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:56 BST 2020 +// On Wed Jun 24 20:10:11 BST 2020 // // // Ports: @@ -46,9 +46,11 @@ // write_dm_word I 32 // master_awready I 1 // master_wready I 1 +// master_bvalid I 1 // master_bid I 4 // master_bresp I 2 // master_arready I 1 +// master_rvalid I 1 // master_rid I 4 // master_rdata I 64 // master_rresp I 2 @@ -56,154 +58,153 @@ // master_ruser I 1 // EN_reset I 1 // EN_write I 1 -// master_bvalid I 1 -// master_rvalid I 1 // EN_av_read I 1 // // Combinational paths from inputs to outputs: // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awid +// EN_write) -> master_awid // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awaddr +// EN_write) -> master_awaddr // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awlen +// EN_write) -> master_awlen // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awsize +// EN_write) -> master_awsize // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awburst +// EN_write) -> master_awburst // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awlock +// EN_write) -> master_awlock // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awcache +// EN_write) -> master_awcache // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awprot +// EN_write) -> master_awprot // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awqos +// EN_write) -> master_awqos // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awregion +// EN_write) -> master_awregion // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awuser +// EN_write) -> master_awuser // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awvalid +// EN_write) -> master_awvalid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wdata +// EN_write) -> master_wdata // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wstrb +// EN_write) -> master_wstrb // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wlast +// EN_write) -> master_wlast // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wuser +// EN_write) -> master_wuser // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wvalid +// EN_write) -> master_wvalid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -211,10 +212,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -222,10 +223,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_araddr // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -233,10 +234,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arlen // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -244,10 +245,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arsize // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -255,10 +256,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arburst // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -266,10 +267,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arlock // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -277,10 +278,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arcache // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -288,10 +289,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arprot // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -299,10 +300,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arqos // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -310,10 +311,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arregion // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -321,10 +322,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_aruser // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -332,7 +333,6 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arvalid // av_read_dm_addr -> av_read // @@ -403,9 +403,9 @@ module mkDM_System_Bus(CLK, master_wready, + master_bvalid, master_bid, master_bresp, - master_bvalid, master_bready, @@ -433,12 +433,12 @@ module mkDM_System_Bus(CLK, master_arready, + master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, master_ruser, - master_rvalid, master_rready); input CLK; @@ -517,9 +517,9 @@ module mkDM_System_Bus(CLK, input master_wready; // action method master_b_bflit + input master_bvalid; input [3 : 0] master_bid; input [1 : 0] master_bresp; - input master_bvalid; // value method master_b_bready output master_bready; @@ -563,12 +563,12 @@ module mkDM_System_Bus(CLK, input master_arready; // action method master_r_rflit + input master_rvalid; input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; input master_ruser; - input master_rvalid; // value method master_r_rready output master_rready; @@ -617,18 +617,18 @@ module mkDM_System_Bus(CLK, master_xactor_shim_rff_rv$port1__read, master_xactor_shim_rff_rv$port2__read, master_xactor_shim_rff_rv$port3__read; - wire [71 : 0] master_xactor_ug_master_u_r_putWire$wget; + wire [71 : 0] master_xactor_master_rSynth_snk_putWire$wget; wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1, master_xactor_shim_bff_rv$port1__read, master_xactor_shim_bff_rv$port2__read, master_xactor_shim_bff_rv$port3__read; - wire [5 : 0] master_xactor_ug_master_u_b_putWire$wget; - wire master_xactor_shim_arff_rv$EN_port0__write, - master_xactor_ug_master_u_ar_dropWire$whas, - master_xactor_ug_master_u_aw_dropWire$whas, - master_xactor_ug_master_u_b_putWire$whas, - master_xactor_ug_master_u_r_putWire$whas, - master_xactor_ug_master_u_w_dropWire$whas; + wire [5 : 0] master_xactor_master_bSynth_snk_putWire$wget; + wire master_xactor_master_arSynth_src_dropWire$whas, + master_xactor_master_awSynth_src_dropWire$whas, + master_xactor_master_bSynth_snk_putWire$whas, + master_xactor_master_rSynth_snk_putWire$whas, + master_xactor_master_wSynth_src_dropWire$whas, + master_xactor_shim_arff_rv$EN_port0__write; // register master_xactor_clearing reg master_xactor_clearing; @@ -713,19 +713,19 @@ module mkDM_System_Bus(CLK, // rule scheduling signals wire CAN_FIRE_RL_master_xactor_do_clear, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut, + CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut, + CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, CAN_FIRE_av_read, @@ -737,19 +737,19 @@ module mkDM_System_Bus(CLK, CAN_FIRE_reset, CAN_FIRE_write, WILL_FIRE_RL_master_xactor_do_clear, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut, + WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut, + WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_rl_sb_read_finish, WILL_FIRE_RL_rl_sb_write_response, WILL_FIRE_av_read, @@ -784,38 +784,38 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117, IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155, IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130, - wrd_wdata__h7269; - reg [7 : 0] wrd_wstrb__h7270; - reg [2 : 0] _theResult___snd_snd_val__h7160, axi4_size_val__h5415; + wrd_wdata__h7347; + reg [7 : 0] wrd_wstrb__h7348; + reg [2 : 0] _theResult___snd_snd_val__h7238, axi4_size_val__h5493; wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3, master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1; wire [73 : 0] master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2; - wire [63 : 0] _theResult___fst__h7145, - addr64__h6432, - result__h3808, - result__h3838, - result__h3865, - result__h3892, - result__h3919, - result__h3946, - result__h3973, - result__h4000, - result__h4045, - result__h4072, - result__h4099, - result__h4126, - result__h4167, - result__h4194, + wire [63 : 0] _theResult___fst__h7223, + addr64__h6510, + result__h3886, + result__h3916, + result__h3943, + result__h3970, + result__h3997, + result__h4024, + result__h4051, + result__h4078, + result__h4123, + result__h4150, + result__h4177, + result__h4204, + result__h4245, + result__h4272, rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156, rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354, - sbaddress__h3099, - word64__h7090; + sbaddress__h3177, + word64__h7168; wire [31 : 0] IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365, IF_write_dm_addr_EQ_0x39_13_THEN_rg_sbaddress1_ETC___d356, - v__h4807, - v__h4941; - wire [7 : 0] strobe64__h7143, strobe64__h7147, strobe64__h7151; - wire [5 : 0] shift_bits__h7093; + v__h4885, + v__h5019; + wire [7 : 0] strobe64__h7221, strobe64__h7225, strobe64__h7229; + wire [5 : 0] shift_bits__h7171; wire rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147, rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162, rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371, @@ -834,13 +834,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h4807 or rg_sbaddress0 or rg_sbaddress1 or v__h4941) + v__h4885 or rg_sbaddress0 or rg_sbaddress1 or v__h5019) begin case (av_read_dm_addr) - 7'h38: av_read = v__h4807; + 7'h38: av_read = v__h4885; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h4941; + 7'h3C: av_read = v__h5019; default: av_read = 32'd0; endcase end @@ -906,7 +906,8 @@ module mkDM_System_Bus(CLK, master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[3:0] ; // value method master_aw_awvalid - assign master_awvalid = CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + assign master_awvalid = + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ; // action method master_aw_awready assign CAN_FIRE_master_aw_awready = 1'd1 ; @@ -929,7 +930,7 @@ module mkDM_System_Bus(CLK, master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2[0] ; // value method master_w_wvalid - assign master_wvalid = CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + assign master_wvalid = CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ; // action method master_w_wready assign CAN_FIRE_master_w_wready = 1'd1 ; @@ -937,7 +938,7 @@ module mkDM_System_Bus(CLK, // action method master_b_bflit assign CAN_FIRE_master_b_bflit = 1'd1 ; - assign WILL_FIRE_master_b_bflit = master_bvalid ; + assign WILL_FIRE_master_b_bflit = 1'd1 ; // value method master_b_bready assign master_bready = !master_xactor_shim_bff_rv[6] ; @@ -983,7 +984,8 @@ module mkDM_System_Bus(CLK, master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[3:0] ; // value method master_ar_arvalid - assign master_arvalid = CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + assign master_arvalid = + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ; // action method master_ar_arready assign CAN_FIRE_master_ar_arready = 1'd1 ; @@ -991,38 +993,38 @@ module mkDM_System_Bus(CLK, // action method master_r_rflit assign CAN_FIRE_master_r_rflit = 1'd1 ; - assign WILL_FIRE_master_r_rflit = master_rvalid ; + assign WILL_FIRE_master_r_rflit = 1'd1 ; // value method master_r_rready assign master_rready = !master_xactor_shim_rff_rv[72] ; - // rule RL_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = - master_xactor_ug_master_u_b_putWire$whas && + // rule RL_master_xactor_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut = + master_xactor_master_bSynth_snk_putWire$whas && master_xactor_shim_bff_rv[6] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut ; - // rule RL_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut = + // rule RL_master_xactor_master_bSynth_snk_doPut + assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut = !master_xactor_shim_bff_rv[6] && - master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ; + master_xactor_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut = + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ; - // rule RL_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = - master_xactor_ug_master_u_r_putWire$whas && + // rule RL_master_xactor_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut = + master_xactor_master_rSynth_snk_putWire$whas && master_xactor_shim_rff_rv[72] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut ; - // rule RL_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut = + // rule RL_master_xactor_master_rSynth_snk_doPut + assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut = !master_xactor_shim_rff_rv[72] && - master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ; + master_xactor_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut = + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ; // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = @@ -1039,65 +1041,65 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_RL_rl_sb_write_response = CAN_FIRE_RL_rl_sb_write_response ; - // rule RL_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + // rule RL_master_xactor_master_awSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek = master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = - master_xactor_ug_master_u_aw_dropWire$whas && + // rule RL_master_xactor_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop = + master_xactor_master_awSynth_src_dropWire$whas && !master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + // rule RL_master_xactor_master_awSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop = master_xactor_shim_awff_rv$port1__read[97] && - master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ; + master_xactor_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ; - // rule RL_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + // rule RL_master_xactor_master_wSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek = master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = - master_xactor_ug_master_u_w_dropWire$whas && + // rule RL_master_xactor_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop = + master_xactor_master_wSynth_src_dropWire$whas && !master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + // rule RL_master_xactor_master_wSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop = master_xactor_shim_wff_rv$port1__read[74] && - master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ; + master_xactor_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ; - // rule RL_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + // rule RL_master_xactor_master_arSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek = master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = - master_xactor_ug_master_u_ar_dropWire$whas && + // rule RL_master_xactor_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop = + master_xactor_master_arSynth_src_dropWire$whas && !master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + // rule RL_master_xactor_master_arSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop = master_xactor_shim_arff_rv$port1__read[97] && - master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ; + master_xactor_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ; // rule RL_master_xactor_do_clear assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; @@ -1144,12 +1146,12 @@ module mkDM_System_Bus(CLK, write_dm_addr_EQ_0x3C_16_AND_rg_sb_state_7_EQ__ETC___d381 ; assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = { 5'd16, - sbaddress__h3099, + sbaddress__h3177, 8'd0, - axi4_size_val__h5415, + axi4_size_val__h5493, 18'd65536 } ; assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = - { 5'd16, addr64__h6432, 8'd0, axi4_size_val__h5415, 18'd65536 } ; + { 5'd16, addr64__h6510, 8'd0, axi4_size_val__h5493, 18'd65536 } ; always@(write_dm_addr or rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 or IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365) @@ -1183,36 +1185,36 @@ module mkDM_System_Bus(CLK, end // inlined wires - assign master_xactor_ug_master_u_b_putWire$wget = + assign master_xactor_master_bSynth_snk_putWire$wget = { master_bid, master_bresp } ; - assign master_xactor_ug_master_u_b_putWire$whas = + assign master_xactor_master_bSynth_snk_putWire$whas = master_bvalid && !master_xactor_shim_bff_rv[6] ; - assign master_xactor_ug_master_u_r_putWire$wget = + assign master_xactor_master_rSynth_snk_putWire$wget = { master_rid, master_rdata, master_rresp, master_rlast, master_ruser } ; - assign master_xactor_ug_master_u_r_putWire$whas = + assign master_xactor_master_rSynth_snk_putWire$whas = master_rvalid && !master_xactor_shim_rff_rv[72] ; - assign master_xactor_ug_master_u_aw_dropWire$whas = + assign master_xactor_master_awSynth_src_dropWire$whas = master_xactor_shim_awff_rv$port1__read[97] && master_awready ; - assign master_xactor_ug_master_u_w_dropWire$whas = + assign master_xactor_master_wSynth_src_dropWire$whas = master_xactor_shim_wff_rv$port1__read[74] && master_wready ; - assign master_xactor_ug_master_u_ar_dropWire$whas = + assign master_xactor_master_arSynth_src_dropWire$whas = master_xactor_shim_arff_rv$port1__read[97] && master_arready ; assign master_xactor_shim_awff_rv$port0__write_1 = { 5'd16, - sbaddress__h3099, + sbaddress__h3177, 8'd0, - _theResult___snd_snd_val__h7160, + _theResult___snd_snd_val__h7238, 18'd65536 } ; assign master_xactor_shim_awff_rv$port1__read = MUX_rg_sbdata0$write_1__SEL_3 ? master_xactor_shim_awff_rv$port0__write_1 : master_xactor_shim_awff_rv ; assign master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ? + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ? 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_awff_rv$port1__read ; assign master_xactor_shim_awff_rv$port3__read = @@ -1220,13 +1222,13 @@ module mkDM_System_Bus(CLK, 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_awff_rv$port2__read ; assign master_xactor_shim_wff_rv$port0__write_1 = - { 1'd1, wrd_wdata__h7269, wrd_wstrb__h7270, 2'd2 } ; + { 1'd1, wrd_wdata__h7347, wrd_wstrb__h7348, 2'd2 } ; assign master_xactor_shim_wff_rv$port1__read = MUX_rg_sbdata0$write_1__SEL_3 ? master_xactor_shim_wff_rv$port0__write_1 : master_xactor_shim_wff_rv ; assign master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ? + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ? 75'h2AAAAAAAAAAAAAAAAAA : master_xactor_shim_wff_rv$port1__read ; assign master_xactor_shim_wff_rv$port3__read = @@ -1234,9 +1236,9 @@ module mkDM_System_Bus(CLK, 75'h2AAAAAAAAAAAAAAAAAA : master_xactor_shim_wff_rv$port2__read ; assign master_xactor_shim_bff_rv$port0__write_1 = - { 1'd1, master_xactor_ug_master_u_b_putWire$wget } ; + { 1'd1, master_xactor_master_bSynth_snk_putWire$wget } ; assign master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ? + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ? master_xactor_shim_bff_rv$port0__write_1 : master_xactor_shim_bff_rv ; assign master_xactor_shim_bff_rv$port2__read = @@ -1261,7 +1263,7 @@ module mkDM_System_Bus(CLK, master_xactor_shim_arff_rv$port0__write_1 : master_xactor_shim_arff_rv ; assign master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ? + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ? 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_arff_rv$port1__read ; assign master_xactor_shim_arff_rv$port3__read = @@ -1269,9 +1271,9 @@ module mkDM_System_Bus(CLK, 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_arff_rv$port2__read ; assign master_xactor_shim_rff_rv$port0__write_1 = - { 1'd1, master_xactor_ug_master_u_r_putWire$wget } ; + { 1'd1, master_xactor_master_rSynth_snk_putWire$wget } ; assign master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ? + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ? master_xactor_shim_rff_rv$port0__write_1 : master_xactor_shim_rff_rv ; assign master_xactor_shim_rff_rv$port2__read = @@ -1368,8 +1370,8 @@ module mkDM_System_Bus(CLK, // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? - sbaddress__h3099 : - addr64__h6432 ; + sbaddress__h3177 : + addr64__h6510 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 || @@ -1474,41 +1476,41 @@ module mkDM_System_Bus(CLK, (write_dm_addr == 7'h39) ? rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354[63:32] : write_dm_word ; - assign _theResult___fst__h7145 = word64__h7090 << shift_bits__h7093 ; - assign addr64__h6432 = { rg_sbaddress1, write_dm_word } ; + assign _theResult___fst__h7223 = word64__h7168 << shift_bits__h7171 ; + assign addr64__h6510 = { rg_sbaddress1, write_dm_word } ; assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3 = master_xactor_shim_arff_rv$port1__read[96:0] ; assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1 = master_xactor_shim_awff_rv$port1__read[96:0] ; assign master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2 = master_xactor_shim_wff_rv$port1__read[73:0] ; - assign result__h3808 = + assign result__h3886 = { 56'd0, master_xactor_shim_rff_rv$port1__read[11:4] } ; - assign result__h3838 = + assign result__h3916 = { 56'd0, master_xactor_shim_rff_rv$port1__read[19:12] } ; - assign result__h3865 = + assign result__h3943 = { 56'd0, master_xactor_shim_rff_rv$port1__read[27:20] } ; - assign result__h3892 = + assign result__h3970 = { 56'd0, master_xactor_shim_rff_rv$port1__read[35:28] } ; - assign result__h3919 = + assign result__h3997 = { 56'd0, master_xactor_shim_rff_rv$port1__read[43:36] } ; - assign result__h3946 = + assign result__h4024 = { 56'd0, master_xactor_shim_rff_rv$port1__read[51:44] } ; - assign result__h3973 = + assign result__h4051 = { 56'd0, master_xactor_shim_rff_rv$port1__read[59:52] } ; - assign result__h4000 = + assign result__h4078 = { 56'd0, master_xactor_shim_rff_rv$port1__read[67:60] } ; - assign result__h4045 = + assign result__h4123 = { 48'd0, master_xactor_shim_rff_rv$port1__read[19:4] } ; - assign result__h4072 = + assign result__h4150 = { 48'd0, master_xactor_shim_rff_rv$port1__read[35:20] } ; - assign result__h4099 = + assign result__h4177 = { 48'd0, master_xactor_shim_rff_rv$port1__read[51:36] } ; - assign result__h4126 = + assign result__h4204 = { 48'd0, master_xactor_shim_rff_rv$port1__read[67:52] } ; - assign result__h4167 = + assign result__h4245 = { 32'd0, master_xactor_shim_rff_rv$port1__read[35:4] } ; - assign result__h4194 = + assign result__h4272 = { 32'd0, master_xactor_shim_rff_rv$port1__read[67:36] } ; assign rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && @@ -1523,21 +1525,21 @@ module mkDM_System_Bus(CLK, rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadonaddr ; assign rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 = - sbaddress__h3099 + + sbaddress__h3177 + IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ; assign rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354 = - addr64__h6432 + + addr64__h6510 + IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ; assign rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d346 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress__h3099 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h7093 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h7143 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h7147 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h7151 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h4807 = + assign sbaddress__h3177 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h7171 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h7221 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h7225 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h7229 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h4885 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1547,12 +1549,12 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd2055 } ; - assign v__h4941 = + assign v__h5019 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h7090 = { 32'd0, write_dm_word } ; + assign word64__h7168 = { 32'd0, write_dm_word } ; assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && @@ -1585,34 +1587,34 @@ module mkDM_System_Bus(CLK, always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: axi4_size_val__h5415 = rg_sbcs_sbaccess; - default: axi4_size_val__h5415 = 3'b011; + 3'd0, 3'd1, 3'd2: axi4_size_val__h5493 = rg_sbcs_sbaccess; + default: axi4_size_val__h5493 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) 3'd0, 3'd1, 3'd2, 3'd3: - _theResult___snd_snd_val__h7160 = rg_sbcs_sbaccess; - default: _theResult___snd_snd_val__h7160 = 3'b111; + _theResult___snd_snd_val__h7238 = rg_sbcs_sbaccess; + default: _theResult___snd_snd_val__h7238 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h7143 or strobe64__h7147 or strobe64__h7151) + strobe64__h7221 or strobe64__h7225 or strobe64__h7229) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h7270 = strobe64__h7143; - 3'd1: wrd_wstrb__h7270 = strobe64__h7147; - 3'd2: wrd_wstrb__h7270 = strobe64__h7151; - 3'd3: wrd_wstrb__h7270 = 8'b11111111; - default: wrd_wstrb__h7270 = 8'd0; + 3'd0: wrd_wstrb__h7348 = strobe64__h7221; + 3'd1: wrd_wstrb__h7348 = strobe64__h7225; + 3'd2: wrd_wstrb__h7348 = strobe64__h7229; + 3'd3: wrd_wstrb__h7348 = 8'b11111111; + default: wrd_wstrb__h7348 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h7090 or _theResult___fst__h7145) + always@(rg_sbcs_sbaccess or word64__h7168 or _theResult___fst__h7223) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h7269 = _theResult___fst__h7145; - default: wrd_wdata__h7269 = word64__h7090; + 3'd0, 3'd1, 3'd2: wrd_wdata__h7347 = _theResult___fst__h7223; + default: wrd_wdata__h7347 = word64__h7168; endcase end always@(rg_sbcs_sbaccess) @@ -1627,68 +1629,68 @@ module mkDM_System_Bus(CLK, endcase end always@(rg_sbaddress_reading or - result__h3808 or - result__h3838 or - result__h3865 or - result__h3892 or - result__h3919 or result__h3946 or result__h3973 or result__h4000) + result__h3886 or + result__h3916 or + result__h3943 or + result__h3970 or + result__h3997 or result__h4024 or result__h4051 or result__h4078) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3808; + result__h3886; 3'h1: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3838; + result__h3916; 3'h2: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3865; + result__h3943; 3'h3: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3892; + result__h3970; 3'h4: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3919; + result__h3997; 3'h5: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3946; + result__h4024; 3'h6: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3973; + result__h4051; 3'h7: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h4000; + result__h4078; endcase end always@(rg_sbaddress_reading or - result__h4045 or result__h4072 or result__h4099 or result__h4126) + result__h4123 or result__h4150 or result__h4177 or result__h4204) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4045; + result__h4123; 3'h2: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4072; + result__h4150; 3'h4: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4099; + result__h4177; 3'h6: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4126; + result__h4204; default: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h4167 or result__h4194) + always@(rg_sbaddress_reading or result__h4245 or result__h4272) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = - result__h4167; + result__h4245; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = - result__h4194; + result__h4272; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = 64'd0; endcase end @@ -1943,11 +1945,11 @@ module mkDM_System_Bus(CLK, av_read_dm_addr != 7'h3C) $write("] not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 && write_dm_word[14:12] == 3'd0) @@ -2204,14 +2206,14 @@ module mkDM_System_Bus(CLK, master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkDM_System_Bus diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v index 5512233..3ada258 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:19 BST 2020 +// On Wed Jun 24 20:17:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v index 16786af..ed08644 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:22 BST 2020 +// On Wed Jun 24 20:17:32 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v index eff2db3..d323026 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:53 BST 2020 +// On Wed Jun 24 20:18:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v index 6ed3a2e..17f7094 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:57 BST 2020 +// On Wed Jun 24 20:10:12 BST 2020 // // // Ports: @@ -72,9 +72,11 @@ // ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 +// master_bvalid I 1 // master_bid I 4 // master_bresp I 2 // master_arready I 1 +// master_rvalid I 1 // master_rid I 4 // master_rdata I 64 // master_rresp I 2 @@ -88,8 +90,6 @@ // EN_hart0_fpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 // EN_ndm_reset_client_response_put I 1 -// master_bvalid I 1 -// master_rvalid I 1 // EN_dmi_read_data I 1 // EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 @@ -101,265 +101,265 @@ // // Combinational paths from inputs to outputs: // (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awid -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awaddr -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awlen -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awsize -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awburst -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awlock -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awcache -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awprot -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awqos -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awregion -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awuser -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awvalid -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wdata -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wstrb -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wlast -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wuser -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wvalid -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, // master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awid +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awaddr +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awlen +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awsize +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awburst +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awlock +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awcache +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awprot +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awqos +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awregion +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awuser +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wdata +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wstrb +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wlast +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wuser +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write, // EN_dmi_read_data) -> master_arid // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_araddr // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arlen // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arsize // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arburst // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arlock // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arcache // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arprot // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arqos // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arregion // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_aruser // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arvalid // EN_dmi_read_data -> dmi_read_data // @@ -482,9 +482,9 @@ module mkDebug_Module(CLK, master_wready, + master_bvalid, master_bid, master_bresp, - master_bvalid, master_bready, @@ -512,12 +512,12 @@ module mkDebug_Module(CLK, master_arready, + master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, master_ruser, - master_rvalid, master_rready); input CLK; @@ -661,9 +661,9 @@ module mkDebug_Module(CLK, input master_wready; // action method master_b_bflit + input master_bvalid; input [3 : 0] master_bid; input [1 : 0] master_bresp; - input master_bvalid; // value method master_b_bready output master_bready; @@ -707,12 +707,12 @@ module mkDebug_Module(CLK, input master_arready; // action method master_r_rflit + input master_rvalid; input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; input master_ruser; - input master_rvalid; // value method master_r_rready output master_rready; @@ -928,8 +928,8 @@ module mkDebug_Module(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h756; - reg [31 : 0] v__h750; + reg [31 : 0] v__h772; + reg [31 : 0] v__h766; // synopsys translate_on // action method dmi_read_addr @@ -1173,7 +1173,7 @@ module mkDebug_Module(CLK, // action method master_b_bflit assign CAN_FIRE_master_b_bflit = 1'd1 ; - assign WILL_FIRE_master_b_bflit = master_bvalid ; + assign WILL_FIRE_master_b_bflit = 1'd1 ; // value method master_b_bready assign master_bready = dm_system_bus$master_bready ; @@ -1217,7 +1217,7 @@ module mkDebug_Module(CLK, // action method master_r_rflit assign CAN_FIRE_master_r_rflit = 1'd1 ; - assign WILL_FIRE_master_r_rflit = master_rvalid ; + assign WILL_FIRE_master_r_rflit = 1'd1 ; // value method master_r_rready assign master_rready = dm_system_bus$master_rready ; @@ -1299,19 +1299,19 @@ module mkDebug_Module(CLK, .master_awready(dm_system_bus$master_awready), .master_bid(dm_system_bus$master_bid), .master_bresp(dm_system_bus$master_bresp), + .master_bvalid(dm_system_bus$master_bvalid), .master_rdata(dm_system_bus$master_rdata), .master_rid(dm_system_bus$master_rid), .master_rlast(dm_system_bus$master_rlast), .master_rresp(dm_system_bus$master_rresp), .master_ruser(dm_system_bus$master_ruser), + .master_rvalid(dm_system_bus$master_rvalid), .master_wready(dm_system_bus$master_wready), .write_dm_addr(dm_system_bus$write_dm_addr), .write_dm_word(dm_system_bus$write_dm_word), .EN_reset(dm_system_bus$EN_reset), .EN_av_read(dm_system_bus$EN_av_read), .EN_write(dm_system_bus$EN_write), - .master_bvalid(dm_system_bus$master_bvalid), - .master_rvalid(dm_system_bus$master_rvalid), .RDY_reset(dm_system_bus$RDY_reset), .av_read(dm_system_bus$av_read), .RDY_av_read(dm_system_bus$RDY_av_read), @@ -1474,11 +1474,13 @@ module mkDebug_Module(CLK, assign dm_system_bus$master_awready = master_awready ; assign dm_system_bus$master_bid = master_bid ; assign dm_system_bus$master_bresp = master_bresp ; + assign dm_system_bus$master_bvalid = master_bvalid ; assign dm_system_bus$master_rdata = master_rdata ; assign dm_system_bus$master_rid = master_rid ; assign dm_system_bus$master_rlast = master_rlast ; assign dm_system_bus$master_rresp = master_rresp ; assign dm_system_bus$master_ruser = master_ruser ; + assign dm_system_bus$master_rvalid = master_rvalid ; assign dm_system_bus$master_wready = master_wready ; assign dm_system_bus$write_dm_addr = dmi_write_dm_addr ; assign dm_system_bus$write_dm_word = dmi_write_dm_word ; @@ -1501,8 +1503,6 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h3D || dmi_write_dm_addr == 7'h3E || dmi_write_dm_addr == 7'h3F) ; - assign dm_system_bus$master_bvalid = master_bvalid ; - assign dm_system_bus$master_rvalid = master_rvalid ; // submodule f_read_addr assign f_read_addr$D_IN = dmi_read_addr_dm_addr ; @@ -1519,12 +1519,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h756 = $stime; + v__h772 = $stime; #0; end - v__h750 = v__h756 / 32'd10; + v__h766 = v__h772 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h750); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h766); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v index 7cb0ed3..7f61bcd 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:22 BST 2020 +// On Wed Jun 24 20:20:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v index a88d385..74b7fa9 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:21 BST 2020 +// On Wed Jun 24 20:19:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v index cc15ac6..bf1bd16 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:58 BST 2020 +// On Wed Jun 24 20:19:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v index 4f9f709..72afd07 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:05 BST 2020 +// On Wed Jun 24 20:19:13 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v index daec152..dec9642 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:02 BST 2020 +// On Wed Jun 24 20:19:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v index 6ee5ee9..7ded0cd 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:48 BST 2020 +// On Wed Jun 24 20:11:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v index 5e71f2c..9ee3e0e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:38 BST 2020 +// On Wed Jun 24 20:10:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v index 13e1c37..c6e316a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:37 BST 2020 +// On Wed Jun 24 20:20:41 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v index 4ddbf8d..401829c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:08 BST 2020 +// On Wed Jun 24 20:19:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v index be19866..a865770 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:22 BST 2020 +// On Wed Jun 24 20:19:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v index d89af73..1c5a61f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:22 BST 2020 +// On Wed Jun 24 20:19:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v index be2b7e1..d1c84b3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:19 BST 2020 +// On Wed Jun 24 20:20:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v index 65a443d..18fe9b4 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:19 BST 2020 +// On Wed Jun 24 20:20:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v index 69f5b23..954c755 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:20 BST 2020 +// On Wed Jun 24 20:20:24 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v index 1d12ba6..05bc3e9 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:20 BST 2020 +// On Wed Jun 24 20:20:24 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v index 3eec7a1..c52c0a7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:29 BST 2020 +// On Wed Jun 24 20:17:39 BST 2020 // // // Ports: @@ -587,7 +587,7 @@ module mkIBankWrapper(CLK, SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425, addr__h42425; reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37, - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31, x__h45568; reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38, @@ -620,7 +620,7 @@ module mkIBankWrapper(CLK, IF_m_pipeline_first__60_BITS_518_TO_516_65_EQ__ETC___d608; wire [5 : 0] IF_m_pipeline_first__60_BITS_521_TO_520_71_EQ__ETC___d613, SEL_ARR_m_rqToPQ_data_0_32_BITS_5_TO_4_42_m_rq_ETC___d854; - wire [3 : 0] sel__h51595; + wire [3 : 0] sel__h51594; wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d628, SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461, SEL_ARR_m_rsToPQ_data_0_58_BIT_515_75_m_rsToPQ_ETC___d787, @@ -1054,7 +1054,7 @@ module mkIBankWrapper(CLK, WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[575] ; assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 = { 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0, - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, 1'd1, CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ; assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 = @@ -1713,7 +1713,7 @@ module mkIBankWrapper(CLK, assign resp_addr__h45889 = { m_cRqMshr$sendRsToP_cRq_getSlot[53:1], m_cRqMshr$sendRsToP_cRq_getRq[10:0] } ; - assign sel__h51595 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; + assign sel__h51594 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; assign v__h10212 = IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ? v__h10363 : @@ -2149,56 +2149,56 @@ module mkIBankWrapper(CLK, m_fromPQ_data_1[586]; endcase end - always@(sel__h51595 or m_pipeline$first) + always@(sel__h51594 or m_pipeline$first) begin - case (sel__h51595) + case (sel__h51594) 4'd0: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[31:0]; 4'd1: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[63:32]; 4'd2: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[95:64]; 4'd3: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[127:96]; 4'd4: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[159:128]; 4'd5: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[191:160]; 4'd6: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[223:192]; 4'd7: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[255:224]; 4'd8: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[287:256]; 4'd9: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[319:288]; 4'd10: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[351:320]; 4'd11: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[383:352]; 4'd12: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[415:384]; 4'd13: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[447:416]; 4'd14: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[479:448]; 4'd15: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[511:480]; endcase end diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v index 52ddfae..e70f592 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:23 BST 2020 +// On Wed Jun 24 20:17:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v index 9aaf592..dc3145e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:29 BST 2020 +// On Wed Jun 24 20:17:39 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v index 17b4619..78bf38b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:24 BST 2020 +// On Wed Jun 24 20:17:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v index 7eaa665..366b0c8 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:26 BST 2020 +// On Wed Jun 24 20:17:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v b/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v index 37c5fe7..ee42319 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:36 BST 2020 +// On Wed Jun 24 20:10:51 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v index adb043d..5c2261b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:09 BST 2020 +// On Wed Jun 24 20:09:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v index 338e674..66f98b2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:27:53 BST 2020 +// On Wed Jun 24 20:17:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v index 51cc3d8..124dbb5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:50 BST 2020 +// On Wed Jun 24 20:18:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v index 8ed24e0..10742f9 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:37 BST 2020 +// On Wed Jun 24 20:18:47 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v index fbec986..72122f8 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:26:06 BST 2020 +// On Wed Jun 24 20:15:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v index 718dfbd..8778313 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:28 BST 2020 +// On Wed Jun 24 20:18:38 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v index 34e9f1d..c672e7b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:26 BST 2020 +// On Wed Jun 24 20:10:41 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v index a5e0b2f..e977ccd 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:44 BST 2020 +// On Wed Jun 24 20:17:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v index d9dd132..76123e1 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:03 BST 2020 +// On Wed Jun 24 20:18:13 BST 2020 // // // Ports: @@ -635,12 +635,12 @@ module mkMemLoader(CLK_portalClk, wire [31 : 0] IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187, IF_hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_X_ETC___d157, IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114, - IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84, IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230, IF_mmio_req_wrBE_BIT_7_27_THEN_mmio_req_wrData_ETC___d853, x__h10335, x__h1110, - x__h1965; + x__h1965, + x__h3902; wire [7 : 0] IF_reqSel_33_EQ_1_64_THEN_hostWrDataQ_q_wDataO_ETC___d467, IF_reqSel_33_EQ_2_99_THEN_hostWrDataQ_q_wDataO_ETC___d501, IF_reqSel_33_EQ_3_18_THEN_hostWrDataQ_q_wDataO_ETC___d520, @@ -1181,7 +1181,7 @@ module mkMemLoader(CLK_portalClk, hostWrDataQ_q_rRdPtr_rsCounter | x__h4592 : hostWrDataQ_q_rRdPtr_rsCounter & y__h4779 ; assign MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 = - (~hostWrDataQ_q_rWrPtr_rsCounter[IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84[0]]) ? + (~hostWrDataQ_q_rWrPtr_rsCounter[x__h3902[0]]) ? hostWrDataQ_q_rWrPtr_rsCounter | x__h3737 : hostWrDataQ_q_rWrPtr_rsCounter & y__h3924 ; assign MUX_hostWrDoneQ_q_rRdPtr_rsCounter$write_1__VAL_1 = @@ -1584,10 +1584,6 @@ module mkMemLoader(CLK_portalClk, hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? 32'd1 : 32'd0 ; - assign IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 = - hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? - 32'd1 : - 32'd0 ; assign IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230 = hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27_XOR_ETC___d229 ? 32'd1 : @@ -1900,9 +1896,11 @@ module mkMemLoader(CLK_portalClk, 32'd1 : 32'd0 ; assign x__h2761 = x_sReadBin__h2209 + 2'd1 ; - assign x__h3737 = - 2'd1 << - IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 ; + assign x__h3737 = 2'd1 << x__h3902 ; + assign x__h3902 = + hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? + 32'd1 : + 32'd0 ; assign x__h4592 = 2'd1 << IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 ; diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v index dc45d19..750450e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:44 BST 2020 +// On Wed Jun 24 20:17:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v index 57d76ae..0f4daab 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:07 BST 2020 +// On Wed Jun 24 20:19:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v index 4899479..cd93c71 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:20 BST 2020 +// On Wed Jun 24 20:19:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v index 006c757..cbc97b9 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:20 BST 2020 +// On Wed Jun 24 20:10:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v index c031101..dba9d5b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:14 BST 2020 +// On Wed Jun 24 20:23:12 BST 2020 // // // Ports: @@ -69,18 +69,22 @@ // RST_N I 1 reset // master0_awready I 1 // master0_wready I 1 +// master0_bvalid I 1 // master0_bid I 6 // master0_bresp I 2 // master0_arready I 1 +// master0_rvalid I 1 // master0_rid I 6 // master0_rdata I 64 // master0_rresp I 2 // master0_rlast I 1 // master1_awready I 1 // master1_wready I 1 +// master1_bvalid I 1 // master1_bid I 6 reg // master1_bresp I 2 reg // master1_arready I 1 +// master1_rvalid I 1 // master1_rid I 6 reg // master1_rdata I 64 reg // master1_rresp I 2 reg @@ -89,10 +93,6 @@ // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 -// master0_bvalid I 1 -// master0_rvalid I 1 -// master1_bvalid I 1 -// master1_rvalid I 1 // // No combinational paths from inputs to outputs // @@ -148,9 +148,9 @@ module mkP3_Core(CLK, master0_wready, + master0_bvalid, master0_bid, master0_bresp, - master0_bvalid, master0_bready, @@ -178,11 +178,11 @@ module mkP3_Core(CLK, master0_arready, + master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, - master0_rvalid, master0_rready, @@ -220,9 +220,9 @@ module mkP3_Core(CLK, master1_wready, + master1_bvalid, master1_bid, master1_bresp, - master1_bvalid, master1_bready, @@ -250,11 +250,11 @@ module mkP3_Core(CLK, master1_arready, + master1_rvalid, master1_rid, master1_rdata, master1_rresp, master1_rlast, - master1_rvalid, master1_rready, @@ -329,9 +329,9 @@ module mkP3_Core(CLK, input master0_wready; // action method master0_b_bflit + input master0_bvalid; input [5 : 0] master0_bid; input [1 : 0] master0_bresp; - input master0_bvalid; // value method master0_b_bready output master0_bready; @@ -375,11 +375,11 @@ module mkP3_Core(CLK, input master0_arready; // action method master0_r_rflit + input master0_rvalid; input [5 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; - input master0_rvalid; // value method master0_r_rready output master0_rready; @@ -440,9 +440,9 @@ module mkP3_Core(CLK, input master1_wready; // action method master1_b_bflit + input master1_bvalid; input [5 : 0] master1_bid; input [1 : 0] master1_bresp; - input master1_bvalid; // value method master1_b_bready output master1_bready; @@ -486,11 +486,11 @@ module mkP3_Core(CLK, input master1_arready; // action method master1_r_rflit + input master1_rvalid; input [5 : 0] master1_rid; input [63 : 0] master1_rdata; input [1 : 0] master1_rresp; input master1_rlast; - input master1_rvalid; // value method master1_r_rready output master1_rready; @@ -574,7 +574,7 @@ module mkP3_Core(CLK, // inlined wires wire [40 : 0] bus_dmi_req_data_wire$wget; - wire bus_dmi_rsp_fifof_x_wire$whas; + wire bus_dmi_rsp_fifof_enqueueing$whas; // register bus_dmi_rsp_fifof_cntr_r reg [1 : 0] bus_dmi_rsp_fifof_cntr_r; @@ -846,10 +846,10 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1321; - reg [31 : 0] v__h1469; - reg [31 : 0] v__h1315; - reg [31 : 0] v__h1463; + reg [31 : 0] v__h1353; + reg [31 : 0] v__h1501; + reg [31 : 0] v__h1347; + reg [31 : 0] v__h1495; // synopsys translate_on // remaining internal signals @@ -917,7 +917,7 @@ module mkP3_Core(CLK, // action method master0_b_bflit assign CAN_FIRE_master0_b_bflit = 1'd1 ; - assign WILL_FIRE_master0_b_bflit = master0_bvalid ; + assign WILL_FIRE_master0_b_bflit = 1'd1 ; // value method master0_b_bready assign master0_bready = corew$cpu_imem_master_bready ; @@ -961,7 +961,7 @@ module mkP3_Core(CLK, // action method master0_r_rflit assign CAN_FIRE_master0_r_rflit = 1'd1 ; - assign WILL_FIRE_master0_r_rflit = master0_rvalid ; + assign WILL_FIRE_master0_r_rflit = 1'd1 ; // value method master0_r_rready assign master0_rready = corew$cpu_imem_master_rready ; @@ -1021,7 +1021,7 @@ module mkP3_Core(CLK, // action method master1_b_bflit assign CAN_FIRE_master1_b_bflit = 1'd1 ; - assign WILL_FIRE_master1_b_bflit = master1_bvalid ; + assign WILL_FIRE_master1_b_bflit = 1'd1 ; // value method master1_b_bready assign master1_bready = corew$cpu_dmem_master_bready ; @@ -1065,7 +1065,7 @@ module mkP3_Core(CLK, // action method master1_r_rflit assign CAN_FIRE_master1_r_rflit = 1'd1 ; - assign WILL_FIRE_master1_r_rflit = master1_rvalid ; + assign WILL_FIRE_master1_r_rflit = 1'd1 ; // value method master1_r_rready assign master1_rready = corew$cpu_dmem_master_rready ; @@ -1124,19 +1124,23 @@ module mkP3_Core(CLK, .cpu_dmem_master_awready(corew$cpu_dmem_master_awready), .cpu_dmem_master_bid(corew$cpu_dmem_master_bid), .cpu_dmem_master_bresp(corew$cpu_dmem_master_bresp), + .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), .cpu_dmem_master_rdata(corew$cpu_dmem_master_rdata), .cpu_dmem_master_rid(corew$cpu_dmem_master_rid), .cpu_dmem_master_rlast(corew$cpu_dmem_master_rlast), .cpu_dmem_master_rresp(corew$cpu_dmem_master_rresp), + .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), .cpu_dmem_master_wready(corew$cpu_dmem_master_wready), .cpu_imem_master_arready(corew$cpu_imem_master_arready), .cpu_imem_master_awready(corew$cpu_imem_master_awready), .cpu_imem_master_bid(corew$cpu_imem_master_bid), .cpu_imem_master_bresp(corew$cpu_imem_master_bresp), + .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), .cpu_imem_master_rdata(corew$cpu_imem_master_rdata), .cpu_imem_master_rid(corew$cpu_imem_master_rid), .cpu_imem_master_rlast(corew$cpu_imem_master_rlast), .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), + .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), .dmi_read_addr_dm_addr(corew$dmi_read_addr_dm_addr), .dmi_write_dm_addr(corew$dmi_write_dm_addr), @@ -1150,10 +1154,6 @@ module mkP3_Core(CLK, .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), - .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), - .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), - .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), - .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), .EN_dmi_read_addr(corew$EN_dmi_read_addr), .EN_dmi_read_data(corew$EN_dmi_read_data), .EN_dmi_write(corew$EN_dmi_write), @@ -1354,7 +1354,8 @@ module mkP3_Core(CLK, // rule RL_bus_dmi_rsp_fifof_incCtr assign CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr = - bus_dmi_rsp_fifof_x_wire$whas && bus_dmi_rsp_fifof_x_wire$whas && + bus_dmi_rsp_fifof_enqueueing$whas && + bus_dmi_rsp_fifof_enqueueing$whas && !CAN_FIRE_RL_bus_dmi_rsp_do_deq ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr = CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr ; @@ -1362,15 +1363,15 @@ module mkP3_Core(CLK, // rule RL_bus_dmi_rsp_fifof_decCtr assign CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr = CAN_FIRE_RL_bus_dmi_rsp_do_deq && - !bus_dmi_rsp_fifof_x_wire$whas ; + !bus_dmi_rsp_fifof_enqueueing$whas ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr = CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // rule RL_bus_dmi_rsp_fifof_both assign CAN_FIRE_RL_bus_dmi_rsp_fifof_both = - bus_dmi_rsp_fifof_x_wire$whas && + bus_dmi_rsp_fifof_enqueueing$whas && CAN_FIRE_RL_bus_dmi_rsp_do_deq && - bus_dmi_rsp_fifof_x_wire$whas ; + bus_dmi_rsp_fifof_enqueueing$whas ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_both = CAN_FIRE_RL_bus_dmi_rsp_fifof_both ; @@ -1412,7 +1413,7 @@ module mkP3_Core(CLK, assign MUX_rg_ndm_reset_delay$write_1__VAL_1 = rg_ndm_reset_delay - 8'd1 ; // inlined wires - assign bus_dmi_rsp_fifof_x_wire$whas = + assign bus_dmi_rsp_fifof_enqueueing$whas = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 || WILL_FIRE_RL_rl_dmi_rsp_cpu ; @@ -1541,19 +1542,23 @@ module mkP3_Core(CLK, assign corew$cpu_dmem_master_awready = master1_awready ; assign corew$cpu_dmem_master_bid = master1_bid ; assign corew$cpu_dmem_master_bresp = master1_bresp ; + assign corew$cpu_dmem_master_bvalid = master1_bvalid ; assign corew$cpu_dmem_master_rdata = master1_rdata ; assign corew$cpu_dmem_master_rid = master1_rid ; assign corew$cpu_dmem_master_rlast = master1_rlast ; assign corew$cpu_dmem_master_rresp = master1_rresp ; + assign corew$cpu_dmem_master_rvalid = master1_rvalid ; assign corew$cpu_dmem_master_wready = master1_wready ; assign corew$cpu_imem_master_arready = master0_arready ; assign corew$cpu_imem_master_awready = master0_awready ; assign corew$cpu_imem_master_bid = master0_bid ; assign corew$cpu_imem_master_bresp = master0_bresp ; + assign corew$cpu_imem_master_bvalid = master0_bvalid ; assign corew$cpu_imem_master_rdata = master0_rdata ; assign corew$cpu_imem_master_rid = master0_rid ; assign corew$cpu_imem_master_rlast = master0_rlast ; assign corew$cpu_imem_master_rresp = master0_rresp ; + assign corew$cpu_imem_master_rvalid = master0_rvalid ; assign corew$cpu_imem_master_wready = master0_wready ; assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; @@ -1569,10 +1574,6 @@ module mkP3_Core(CLK, assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; - assign corew$cpu_imem_master_bvalid = master0_bvalid ; - assign corew$cpu_imem_master_rvalid = master0_rvalid ; - assign corew$cpu_dmem_master_bvalid = master1_bvalid ; - assign corew$cpu_dmem_master_rvalid = master1_rvalid ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1669,31 +1670,31 @@ module mkP3_Core(CLK, if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1321 = $stime; + v__h1353 = $stime; #0; end - v__h1315 = v__h1321 / 32'd10; + v__h1347 = v__h1353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset) $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1315, + v__h1347, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) begin - v__h1469 = $stime; + v__h1501 = $stime; #0; end - v__h1463 = v__h1469 / 32'd10; + v__h1495 = v__h1501 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1463); + v__h1495); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v index 9efa2cb..05f7c17 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:49 BST 2020 +// On Wed Jun 24 20:10:04 BST 2020 // // // Ports: @@ -30,6 +30,7 @@ // set_verbosity_verbosity I 4 reg // set_addr_map_addr_base I 64 reg // set_addr_map_addr_lim I 64 reg +// axi4_slave_awvalid I 1 // axi4_slave_awid I 5 reg // axi4_slave_awaddr I 64 reg // axi4_slave_awlen I 8 reg @@ -40,11 +41,13 @@ // axi4_slave_awprot I 3 reg // axi4_slave_awqos I 4 reg // axi4_slave_awregion I 4 reg +// axi4_slave_wvalid I 1 // axi4_slave_wdata I 64 reg // axi4_slave_wstrb I 8 reg // axi4_slave_wlast I 1 reg // axi4_slave_wuser I 1 reg // axi4_slave_bready I 1 +// axi4_slave_arvalid I 1 // axi4_slave_arid I 5 reg // axi4_slave_araddr I 64 reg // axi4_slave_arlen I 8 reg @@ -77,9 +80,6 @@ // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_set_addr_map I 1 -// axi4_slave_awvalid I 1 -// axi4_slave_wvalid I 1 -// axi4_slave_arvalid I 1 // // No combinational paths from inputs to outputs // @@ -119,6 +119,7 @@ module mkPLIC_16_2_7(CLK, EN_set_addr_map, RDY_set_addr_map, + axi4_slave_awvalid, axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -129,15 +130,14 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion, - axi4_slave_awvalid, axi4_slave_awready, + axi4_slave_wvalid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, axi4_slave_wuser, - axi4_slave_wvalid, axi4_slave_wready, @@ -149,6 +149,7 @@ module mkPLIC_16_2_7(CLK, axi4_slave_bready, + axi4_slave_arvalid, axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -159,7 +160,6 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion, - axi4_slave_arvalid, axi4_slave_arready, @@ -239,6 +239,7 @@ module mkPLIC_16_2_7(CLK, output RDY_set_addr_map; // action method axi4_slave_aw_awflit + input axi4_slave_awvalid; input [4 : 0] axi4_slave_awid; input [63 : 0] axi4_slave_awaddr; input [7 : 0] axi4_slave_awlen; @@ -249,17 +250,16 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_awprot; input [3 : 0] axi4_slave_awqos; input [3 : 0] axi4_slave_awregion; - input axi4_slave_awvalid; // value method axi4_slave_aw_awready output axi4_slave_awready; // action method axi4_slave_w_wflit + input axi4_slave_wvalid; input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; input axi4_slave_wuser; - input axi4_slave_wvalid; // value method axi4_slave_w_wready output axi4_slave_wready; @@ -279,6 +279,7 @@ module mkPLIC_16_2_7(CLK, input axi4_slave_bready; // action method axi4_slave_ar_arflit + input axi4_slave_arvalid; input [4 : 0] axi4_slave_arid; input [63 : 0] axi4_slave_araddr; input [7 : 0] axi4_slave_arlen; @@ -289,7 +290,6 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_arprot; input [3 : 0] axi4_slave_arqos; input [3 : 0] axi4_slave_arregion; - input axi4_slave_arvalid; // value method axi4_slave_ar_arready output axi4_slave_arready; @@ -389,15 +389,15 @@ module mkPLIC_16_2_7(CLK, v_targets_1_m_eip; // inlined wires - wire [97 : 0] m_slave_xactor_ug_slave_u_ar_putWire$wget, - m_slave_xactor_ug_slave_u_aw_putWire$wget; - wire [73 : 0] m_slave_xactor_ug_slave_u_w_putWire$wget; - wire [72 : 0] m_slave_xactor_ug_slave_u_r_peekWire$wget; - wire m_slave_xactor_ug_slave_u_ar_putWire$whas, - m_slave_xactor_ug_slave_u_aw_putWire$whas, - m_slave_xactor_ug_slave_u_b_dropWire$whas, - m_slave_xactor_ug_slave_u_r_dropWire$whas, - m_slave_xactor_ug_slave_u_w_putWire$whas; + wire [97 : 0] m_slave_xactor_slvSynth_arSynth_snk_putWire$wget, + m_slave_xactor_slvSynth_awSynth_snk_putWire$wget; + wire [73 : 0] m_slave_xactor_slvSynth_wSynth_snk_putWire$wget; + wire [72 : 0] m_slave_xactor_slvSynth_rSynth_src_peekWire$wget; + wire m_slave_xactor_slvSynth_arSynth_snk_putWire$whas, + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas, + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas, + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas, + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas; // register m_cfg_verbosity reg [3 : 0] m_cfg_verbosity; @@ -854,18 +854,18 @@ module mkPLIC_16_2_7(CLK, CAN_FIRE_RL_m_rl_process_wr_req, CAN_FIRE_RL_m_rl_reset, CAN_FIRE_RL_m_slave_xactor_do_clear, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut, CAN_FIRE_axi4_slave_ar_arflit, CAN_FIRE_axi4_slave_aw_awflit, CAN_FIRE_axi4_slave_b_bready, @@ -896,18 +896,18 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_wr_req, WILL_FIRE_RL_m_rl_reset, WILL_FIRE_RL_m_slave_xactor_do_clear, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut, WILL_FIRE_axi4_slave_ar_arflit, WILL_FIRE_axi4_slave_aw_awflit, WILL_FIRE_axi4_slave_b_bready, @@ -1061,142 +1061,142 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h77333; - reg [31 : 0] v__h77531; - reg [31 : 0] v__h77729; - reg [31 : 0] v__h77927; - reg [31 : 0] v__h78125; - reg [31 : 0] v__h78323; - reg [31 : 0] v__h78521; - reg [31 : 0] v__h78719; - reg [31 : 0] v__h78917; - reg [31 : 0] v__h79115; - reg [31 : 0] v__h79313; - reg [31 : 0] v__h79511; - reg [31 : 0] v__h79709; - reg [31 : 0] v__h79907; - reg [31 : 0] v__h80105; - reg [31 : 0] v__h80303; - reg [31 : 0] v__h7530; - reg [31 : 0] v__h28194; - reg [31 : 0] v__h28448; - reg [31 : 0] v__h29372; - reg [31 : 0] v__h29558; - reg [31 : 0] v__h68542; - reg [31 : 0] v__h68832; - reg [31 : 0] v__h69364; - reg [31 : 0] v__h69450; - reg [31 : 0] v__h69661; - reg [31 : 0] v__h69907; - reg [31 : 0] v__h14375; - reg [31 : 0] v__h14590; - reg [31 : 0] v__h14818; - reg [31 : 0] v__h15069; - reg [31 : 0] v__h19543; - reg [31 : 0] v__h25160; - reg [31 : 0] v__h27336; - reg [31 : 0] v__h25416; - reg [31 : 0] v__h27627; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h76288; - reg [31 : 0] v__h76398; - reg [31 : 0] v__h76511; - reg [31 : 0] v__h7524; - reg [31 : 0] v__h14369; - reg [31 : 0] v__h14584; - reg [31 : 0] v__h14812; - reg [31 : 0] v__h15063; - reg [31 : 0] v__h19537; - reg [31 : 0] v__h25154; - reg [31 : 0] v__h25410; - reg [31 : 0] v__h27330; - reg [31 : 0] v__h27621; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28188; - reg [31 : 0] v__h28442; - reg [31 : 0] v__h29366; - reg [31 : 0] v__h29552; - reg [31 : 0] v__h68536; - reg [31 : 0] v__h68826; - reg [31 : 0] v__h69358; - reg [31 : 0] v__h69444; - reg [31 : 0] v__h69655; - reg [31 : 0] v__h69901; - reg [31 : 0] v__h76282; - reg [31 : 0] v__h76392; - reg [31 : 0] v__h76505; - reg [31 : 0] v__h77327; - reg [31 : 0] v__h77525; - reg [31 : 0] v__h77723; - reg [31 : 0] v__h77921; - reg [31 : 0] v__h78119; - reg [31 : 0] v__h78317; - reg [31 : 0] v__h78515; - reg [31 : 0] v__h78713; - reg [31 : 0] v__h78911; - reg [31 : 0] v__h79109; - reg [31 : 0] v__h79307; - reg [31 : 0] v__h79505; - reg [31 : 0] v__h79703; - reg [31 : 0] v__h79901; - reg [31 : 0] v__h80099; - reg [31 : 0] v__h80297; + reg [31 : 0] v__h77354; + reg [31 : 0] v__h77552; + reg [31 : 0] v__h77750; + reg [31 : 0] v__h77948; + reg [31 : 0] v__h78146; + reg [31 : 0] v__h78344; + reg [31 : 0] v__h78542; + reg [31 : 0] v__h78740; + reg [31 : 0] v__h78938; + reg [31 : 0] v__h79136; + reg [31 : 0] v__h79334; + reg [31 : 0] v__h79532; + reg [31 : 0] v__h79730; + reg [31 : 0] v__h79928; + reg [31 : 0] v__h80126; + reg [31 : 0] v__h80324; + reg [31 : 0] v__h7589; + reg [31 : 0] v__h28253; + reg [31 : 0] v__h28507; + reg [31 : 0] v__h29431; + reg [31 : 0] v__h29617; + reg [31 : 0] v__h68601; + reg [31 : 0] v__h68891; + reg [31 : 0] v__h69423; + reg [31 : 0] v__h69509; + reg [31 : 0] v__h69720; + reg [31 : 0] v__h69966; + reg [31 : 0] v__h14434; + reg [31 : 0] v__h14649; + reg [31 : 0] v__h14877; + reg [31 : 0] v__h15128; + reg [31 : 0] v__h19602; + reg [31 : 0] v__h25219; + reg [31 : 0] v__h27395; + reg [31 : 0] v__h25475; + reg [31 : 0] v__h27686; + reg [31 : 0] v__h27924; + reg [31 : 0] v__h76347; + reg [31 : 0] v__h76457; + reg [31 : 0] v__h76570; + reg [31 : 0] v__h7583; + reg [31 : 0] v__h14428; + reg [31 : 0] v__h14643; + reg [31 : 0] v__h14871; + reg [31 : 0] v__h15122; + reg [31 : 0] v__h19596; + reg [31 : 0] v__h25213; + reg [31 : 0] v__h25469; + reg [31 : 0] v__h27389; + reg [31 : 0] v__h27680; + reg [31 : 0] v__h27918; + reg [31 : 0] v__h28247; + reg [31 : 0] v__h28501; + reg [31 : 0] v__h29425; + reg [31 : 0] v__h29611; + reg [31 : 0] v__h68595; + reg [31 : 0] v__h68885; + reg [31 : 0] v__h69417; + reg [31 : 0] v__h69503; + reg [31 : 0] v__h69714; + reg [31 : 0] v__h69960; + reg [31 : 0] v__h76341; + reg [31 : 0] v__h76451; + reg [31 : 0] v__h76564; + reg [31 : 0] v__h77348; + reg [31 : 0] v__h77546; + reg [31 : 0] v__h77744; + reg [31 : 0] v__h77942; + reg [31 : 0] v__h78140; + reg [31 : 0] v__h78338; + reg [31 : 0] v__h78536; + reg [31 : 0] v__h78734; + reg [31 : 0] v__h78932; + reg [31 : 0] v__h79130; + reg [31 : 0] v__h79328; + reg [31 : 0] v__h79526; + reg [31 : 0] v__h79724; + reg [31 : 0] v__h79922; + reg [31 : 0] v__h80120; + reg [31 : 0] v__h80318; // synopsys translate_on // remaining internal signals - reg [63 : 0] y_avValue_fst__h27509; - reg [4 : 0] x__h25371, x__h69004; - reg [2 : 0] x__h14848, x__h25190; - reg [1 : 0] CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49, - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50; - reg CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, + reg [63 : 0] y_avValue_fst__h27568; + reg [4 : 0] x__h25430, x__h69063; + reg [2 : 0] x__h14907, x__h25249; + reg [1 : 0] CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49, + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50; + reg CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029, SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164, SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168, @@ -1294,127 +1294,127 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586; - wire [63 : 0] addr_offset__h14540, - addr_offset__h28408, - rdata___1__h27806, - rdata__h27563, - v__h14777, - v__h15027, - v__h19501, - v__h25119, - v__h26816, - v__h26835, - x__h27766, - y_avValue_fst__h27455, - y_avValue_fst__h27476, - y_avValue_fst__h27488, - y_avValue_fst__h27504, - y_avValue_fst__h27520, - y_avValue_fst__h27525, - y_avValue_fst__h27536, - y_avValue_fst__h27541, - y_avValue_fst__h27555; - wire [31 : 0] v_ie__h19504, - v_ip__h15030, - wdata32__h28409, - x__h25030, - x__h68623; - wire [9 : 0] source_id__h17021, - source_id__h17128, - source_id__h17201, - source_id__h17274, - source_id__h17347, - source_id__h17420, - source_id__h17493, - source_id__h17566, - source_id__h17639, - source_id__h17712, - source_id__h17785, - source_id__h17858, - source_id__h17931, - source_id__h18004, - source_id__h18077, - source_id__h18150, - source_id__h18223, - source_id__h18296, - source_id__h18369, - source_id__h18442, - source_id__h18515, - source_id__h18588, - source_id__h18661, - source_id__h18734, - source_id__h18807, - source_id__h18880, - source_id__h18953, - source_id__h19026, - source_id__h19099, - source_id__h19172, - source_id__h19245, - source_id__h21494, - source_id__h21670, - source_id__h21778, - source_id__h21886, - source_id__h21994, - source_id__h22102, - source_id__h22210, - source_id__h22318, - source_id__h22426, - source_id__h22534, - source_id__h22642, - source_id__h22750, - source_id__h22858, - source_id__h22966, - source_id__h23074, - source_id__h23182, - source_id__h23290, - source_id__h23398, - source_id__h23506, - source_id__h23614, - source_id__h23722, - source_id__h23830, - source_id__h23938, - source_id__h24046, - source_id__h24154, - source_id__h24262, - source_id__h24370, - source_id__h24478, - source_id__h24586, - source_id__h24694, - source_id__h24802, - source_id__h30987, - source_id__h32197, - source_id__h33407, - source_id__h34617, - source_id__h35827, - source_id__h37037, - source_id__h38247, - source_id__h39457, - source_id__h40667, - source_id__h41877, - source_id__h43087, - source_id__h44297, - source_id__h45507, - source_id__h46717, - source_id__h47927, - source_id__h49137, - source_id__h50347, - source_id__h51557, - source_id__h52767, - source_id__h53977, - source_id__h55187, - source_id__h56397, - source_id__h57607, - source_id__h58817, - source_id__h60027, - source_id__h61237, - source_id__h62447, - source_id__h63657, - source_id__h64867, - source_id__h66077, - source_id__h67287, - source_id__h68952, - source_id_base__h14985, - source_id_base__h29659; + wire [63 : 0] addr_offset__h14599, + addr_offset__h28467, + rdata___1__h27865, + rdata__h27622, + v__h14836, + v__h15086, + v__h19560, + v__h25178, + v__h26875, + v__h26894, + x__h27825, + y_avValue_fst__h27514, + y_avValue_fst__h27535, + y_avValue_fst__h27547, + y_avValue_fst__h27563, + y_avValue_fst__h27579, + y_avValue_fst__h27584, + y_avValue_fst__h27595, + y_avValue_fst__h27600, + y_avValue_fst__h27614; + wire [31 : 0] v_ie__h19563, + v_ip__h15089, + wdata32__h28468, + x__h25089, + x__h68682; + wire [9 : 0] source_id__h17080, + source_id__h17187, + source_id__h17260, + source_id__h17333, + source_id__h17406, + source_id__h17479, + source_id__h17552, + source_id__h17625, + source_id__h17698, + source_id__h17771, + source_id__h17844, + source_id__h17917, + source_id__h17990, + source_id__h18063, + source_id__h18136, + source_id__h18209, + source_id__h18282, + source_id__h18355, + source_id__h18428, + source_id__h18501, + source_id__h18574, + source_id__h18647, + source_id__h18720, + source_id__h18793, + source_id__h18866, + source_id__h18939, + source_id__h19012, + source_id__h19085, + source_id__h19158, + source_id__h19231, + source_id__h19304, + source_id__h21553, + source_id__h21729, + source_id__h21837, + source_id__h21945, + source_id__h22053, + source_id__h22161, + source_id__h22269, + source_id__h22377, + source_id__h22485, + source_id__h22593, + source_id__h22701, + source_id__h22809, + source_id__h22917, + source_id__h23025, + source_id__h23133, + source_id__h23241, + source_id__h23349, + source_id__h23457, + source_id__h23565, + source_id__h23673, + source_id__h23781, + source_id__h23889, + source_id__h23997, + source_id__h24105, + source_id__h24213, + source_id__h24321, + source_id__h24429, + source_id__h24537, + source_id__h24645, + source_id__h24753, + source_id__h24861, + source_id__h31046, + source_id__h32256, + source_id__h33466, + source_id__h34676, + source_id__h35886, + source_id__h37096, + source_id__h38306, + source_id__h39516, + source_id__h40726, + source_id__h41936, + source_id__h43146, + source_id__h44356, + source_id__h45566, + source_id__h46776, + source_id__h47986, + source_id__h49196, + source_id__h50406, + source_id__h51616, + source_id__h52826, + source_id__h54036, + source_id__h55246, + source_id__h56456, + source_id__h57666, + source_id__h58876, + source_id__h60086, + source_id__h61296, + source_id__h62506, + source_id__h63716, + source_id__h64926, + source_id__h66136, + source_id__h67346, + source_id__h69011, + source_id_base__h15044, + source_id_base__h29718; wire [4 : 0] IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d3227, IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d3321, IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d733, @@ -1436,9 +1436,9 @@ module mkPLIC_16_2_7(CLK, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3225, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3319, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d731, - b__h72911, - b__h74916, - max_id__h25318; + b__h72970, + b__h74975, + max_id__h25377; wire [2 : 0] IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d3186, IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d3280, IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d681, @@ -1483,8 +1483,8 @@ module mkPLIC_16_2_7(CLK, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3181, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3275, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d674, - a__h72910, - a__h74915; + a__h72969, + a__h74974; wire [1 : 0] IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d875, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d876, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877, @@ -1546,22 +1546,22 @@ module mkPLIC_16_2_7(CLK, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962, - NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439, - NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447, - NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455, - NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463, - NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471, - NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479, - NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487, - NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368, - NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375, - NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383, - NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391, - NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399, - NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407, - NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415, - NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423, - NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431, + NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442, + NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450, + NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458, + NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466, + NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474, + NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482, + NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490, + NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371, + NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378, + NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386, + NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394, + NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402, + NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410, + NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418, + NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426, + NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434, _dfoo1, _dfoo10, _dfoo100, @@ -3242,14 +3242,14 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_aw_awflit assign CAN_FIRE_axi4_slave_aw_awflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_aw_awflit = axi4_slave_awvalid ; + assign WILL_FIRE_axi4_slave_aw_awflit = 1'd1 ; // value method axi4_slave_aw_awready assign axi4_slave_awready = m_slave_xactor_shim_awff$FULL_N ; // action method axi4_slave_w_wflit assign CAN_FIRE_axi4_slave_w_wflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_w_wflit = axi4_slave_wvalid ; + assign WILL_FIRE_axi4_slave_w_wflit = 1'd1 ; // value method axi4_slave_w_wready assign axi4_slave_wready = m_slave_xactor_shim_wff$FULL_N ; @@ -3269,25 +3269,30 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_ar_arflit assign CAN_FIRE_axi4_slave_ar_arflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_ar_arflit = axi4_slave_arvalid ; + assign WILL_FIRE_axi4_slave_ar_arflit = 1'd1 ; // value method axi4_slave_ar_arready assign axi4_slave_arready = m_slave_xactor_shim_arff$FULL_N ; // value method axi4_slave_r_rid - assign axi4_slave_rid = m_slave_xactor_ug_slave_u_r_peekWire$wget[72:68] ; + assign axi4_slave_rid = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[72:68] ; // value method axi4_slave_r_rdata - assign axi4_slave_rdata = m_slave_xactor_ug_slave_u_r_peekWire$wget[67:4] ; + assign axi4_slave_rdata = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[67:4] ; // value method axi4_slave_r_rresp - assign axi4_slave_rresp = m_slave_xactor_ug_slave_u_r_peekWire$wget[3:2] ; + assign axi4_slave_rresp = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[3:2] ; // value method axi4_slave_r_rlast - assign axi4_slave_rlast = m_slave_xactor_ug_slave_u_r_peekWire$wget[1] ; + assign axi4_slave_rlast = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[1] ; // value method axi4_slave_r_ruser - assign axi4_slave_ruser = m_slave_xactor_ug_slave_u_r_peekWire$wget[0] ; + assign axi4_slave_ruser = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[0] ; // value method axi4_slave_r_rvalid assign axi4_slave_rvalid = m_slave_xactor_shim_rff$EMPTY_N ; @@ -3361,10 +3366,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h72910 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h72969 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h74915 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h74974 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3460,39 +3465,39 @@ module mkPLIC_16_2_7(CLK, m_f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - // rule RL_m_slave_xactor_ug_slave_u_aw_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = - m_slave_xactor_ug_slave_u_aw_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas && !m_slave_xactor_shim_awff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_w_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = - m_slave_xactor_ug_slave_u_w_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas && !m_slave_xactor_shim_wff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_b_setPeek - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + // rule RL_m_slave_xactor_slvSynth_bSynth_src_setPeek + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek = m_slave_xactor_shim_bff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek = m_slave_xactor_shim_bff$EMPTY_N ; - // rule RL_m_slave_xactor_ug_slave_u_b_warnDoDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = - m_slave_xactor_ug_slave_u_b_dropWire$whas && + // rule RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas && !m_slave_xactor_shim_bff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop ; - // rule RL_m_slave_xactor_ug_slave_u_b_doDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = + // rule RL_m_slave_xactor_slvSynth_bSynth_src_doDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop = m_slave_xactor_shim_bff$EMPTY_N && - m_slave_xactor_ug_slave_u_b_dropWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop ; // rule RL_m_rl_process_wr_req assign CAN_FIRE_RL_m_rl_process_wr_req = @@ -3504,46 +3509,46 @@ module mkPLIC_16_2_7(CLK, CAN_FIRE_RL_m_rl_process_wr_req && !WILL_FIRE_RL_m_rl_process_rd_req ; - // rule RL_m_slave_xactor_ug_slave_u_aw_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = + // rule RL_m_slave_xactor_slvSynth_awSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut = m_slave_xactor_shim_awff$FULL_N && - m_slave_xactor_ug_slave_u_aw_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut ; - // rule RL_m_slave_xactor_ug_slave_u_w_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = + // rule RL_m_slave_xactor_slvSynth_wSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut = m_slave_xactor_shim_wff$FULL_N && - m_slave_xactor_ug_slave_u_w_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut ; - // rule RL_m_slave_xactor_ug_slave_u_ar_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = - m_slave_xactor_ug_slave_u_ar_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_arSynth_snk_putWire$whas && !m_slave_xactor_shim_arff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_r_setPeek - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + // rule RL_m_slave_xactor_slvSynth_rSynth_src_setPeek + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek = m_slave_xactor_shim_rff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek = m_slave_xactor_shim_rff$EMPTY_N ; - // rule RL_m_slave_xactor_ug_slave_u_r_warnDoDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = - m_slave_xactor_ug_slave_u_r_dropWire$whas && + // rule RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas && !m_slave_xactor_shim_rff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop ; - // rule RL_m_slave_xactor_ug_slave_u_r_doDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = + // rule RL_m_slave_xactor_slvSynth_rSynth_src_doDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop = m_slave_xactor_shim_rff$EMPTY_N && - m_slave_xactor_ug_slave_u_r_dropWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop ; // rule RL_m_rl_process_rd_req assign CAN_FIRE_RL_m_rl_process_rd_req = @@ -3552,12 +3557,12 @@ module mkPLIC_16_2_7(CLK, !m_f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - // rule RL_m_slave_xactor_ug_slave_u_ar_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = + // rule RL_m_slave_xactor_slvSynth_arSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut = m_slave_xactor_shim_arff$FULL_N && - m_slave_xactor_ug_slave_u_ar_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + m_slave_xactor_slvSynth_arSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut ; // rule RL_m_slave_xactor_do_clear assign CAN_FIRE_RL_m_slave_xactor_do_clear = m_slave_xactor_clearing ; @@ -3566,139 +3571,139 @@ module mkPLIC_16_2_7(CLK, // inputs to muxes for submodule ports assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd0 && + addr_offset__h14599[16:12] == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd1 && + addr_offset__h14599[16:12] == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd0 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd1 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd10 && + source_id__h69011 == 10'd10 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd11 && + source_id__h69011 == 10'd11 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd12 && + source_id__h69011 == 10'd12 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd13 && + source_id__h69011 == 10'd13 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd14 && + source_id__h69011 == 10'd14 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd15 && + source_id__h69011 == 10'd15 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd16 && + source_id__h69011 == 10'd16 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd2 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd2 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd3 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd3 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd4 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd4 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd5 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd5 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd6 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd6 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd7 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd7 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd8 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd8 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd9 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd9 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[11:2] == 10'd0 && + addr_offset__h28467[11:2] == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && @@ -3823,178 +3828,178 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h29659 == 10'd0 && + (source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h29659 == 10'd1 && + (source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h29659 == 10'd10 && + (source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h29659 == 10'd11 && + (source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h29659 == 10'd12 && + (source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h29659 == 10'd13 && + (source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h29659 == 10'd14 && + (source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h29659 == 10'd15 && + (source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h29659 == 10'd16 && + (source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h29659 == 10'd2 && + (source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h29659 == 10'd3 && + (source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h29659 == 10'd4 && + (source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h29659 == 10'd5 && + (source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h29659 == 10'd6 && + (source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h29659 == 10'd7 && + (source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h29659 == 10'd8 && + (source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h29659 == 10'd9 && + (source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h29659 == 10'd0 && + (source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h29659 == 10'd1 && + (source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h29659 == 10'd10 && + (source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h29659 == 10'd11 && + (source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h29659 == 10'd12 && + (source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h29659 == 10'd13 && + (source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h29659 == 10'd14 && + (source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h29659 == 10'd15 && + (source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h29659 == 10'd16 && + (source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h29659 == 10'd2 && + (source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h29659 == 10'd3 && + (source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h29659 == 10'd4 && + (source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h29659 == 10'd5 && + (source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h29659 == 10'd6 && + (source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h29659 == 10'd7 && + (source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h29659 == 10'd8 && + (source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h29659 == 10'd9 && + (source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1988 ; // inlined wires - assign m_slave_xactor_ug_slave_u_aw_putWire$wget = + assign m_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -4005,16 +4010,16 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion } ; - assign m_slave_xactor_ug_slave_u_aw_putWire$whas = + assign m_slave_xactor_slvSynth_awSynth_snk_putWire$whas = axi4_slave_awvalid && m_slave_xactor_shim_awff$FULL_N ; - assign m_slave_xactor_ug_slave_u_w_putWire$wget = + assign m_slave_xactor_slvSynth_wSynth_snk_putWire$wget = { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, axi4_slave_wuser } ; - assign m_slave_xactor_ug_slave_u_w_putWire$whas = + assign m_slave_xactor_slvSynth_wSynth_snk_putWire$whas = axi4_slave_wvalid && m_slave_xactor_shim_wff$FULL_N ; - assign m_slave_xactor_ug_slave_u_ar_putWire$wget = + assign m_slave_xactor_slvSynth_arSynth_snk_putWire$wget = { axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -4025,13 +4030,13 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion } ; - assign m_slave_xactor_ug_slave_u_ar_putWire$whas = + assign m_slave_xactor_slvSynth_arSynth_snk_putWire$whas = axi4_slave_arvalid && m_slave_xactor_shim_arff$FULL_N ; - assign m_slave_xactor_ug_slave_u_r_peekWire$wget = + assign m_slave_xactor_slvSynth_rSynth_src_peekWire$wget = { m_slave_xactor_shim_rff$D_OUT, 1'd0 } ; - assign m_slave_xactor_ug_slave_u_b_dropWire$whas = + assign m_slave_xactor_slvSynth_bSynth_src_dropWire$whas = m_slave_xactor_shim_bff$EMPTY_N && axi4_slave_bready ; - assign m_slave_xactor_ug_slave_u_r_dropWire$whas = + assign m_slave_xactor_slvSynth_rSynth_src_dropWire$whas = m_slave_xactor_shim_rff$EMPTY_N && axi4_slave_rready ; // register m_cfg_verbosity @@ -4054,30 +4059,30 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_servicing_source_0 assign m_vrg_servicing_source_0$D_IN = MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h25318 : + max_id__h25377 : 5'd0 ; assign m_vrg_servicing_source_0$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd0 && + addr_offset__h14599[16:12] == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[16:12] == 5'd0 && + addr_offset__h28467[16:12] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 assign m_vrg_servicing_source_1$D_IN = MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h25318 : + max_id__h25377 : 5'd0 ; assign m_vrg_servicing_source_1$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd1 && + addr_offset__h14599[16:12] == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[16:12] == 5'd1 && + addr_offset__h28467[16:12] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4086,10 +4091,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_0$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd0 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd0 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4098,10 +4103,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_1$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd1 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4110,11 +4115,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_10$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd10 && + source_id__h69011 == 10'd10 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4123,11 +4128,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_11$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd11 && + source_id__h69011 == 10'd11 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4136,11 +4141,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_12$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd12 && + source_id__h69011 == 10'd12 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4149,11 +4154,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_13$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd13 && + source_id__h69011 == 10'd13 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4162,11 +4167,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_14$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd14 && + source_id__h69011 == 10'd14 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4175,11 +4180,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_15$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd15 && + source_id__h69011 == 10'd15 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4188,11 +4193,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_16$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd16 && + source_id__h69011 == 10'd16 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4201,10 +4206,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_2$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd2 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd2 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4213,10 +4218,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_3$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd3 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd3 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4225,10 +4230,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_4$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd4 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd4 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4237,10 +4242,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_5$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd5 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd5 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4249,10 +4254,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_6$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd6 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd6 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4261,10 +4266,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_7$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd7 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd7 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4273,10 +4278,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_8$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd8 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd8 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4285,17 +4290,17 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_9$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd9 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd9 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 assign m_vrg_source_ip_0$D_IN = 1'd0 ; assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd0 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4307,7 +4312,7 @@ module mkPLIC_16_2_7(CLK, v_sources_0_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_1$EN = !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4319,7 +4324,7 @@ module mkPLIC_16_2_7(CLK, v_sources_9_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_10$EN = !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4331,7 +4336,7 @@ module mkPLIC_16_2_7(CLK, v_sources_10_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_11$EN = !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4343,7 +4348,7 @@ module mkPLIC_16_2_7(CLK, v_sources_11_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_12$EN = !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4355,7 +4360,7 @@ module mkPLIC_16_2_7(CLK, v_sources_12_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_13$EN = !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4367,7 +4372,7 @@ module mkPLIC_16_2_7(CLK, v_sources_13_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_14$EN = !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4379,7 +4384,7 @@ module mkPLIC_16_2_7(CLK, v_sources_14_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_15$EN = !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4391,7 +4396,7 @@ module mkPLIC_16_2_7(CLK, v_sources_15_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_16$EN = !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4403,7 +4408,7 @@ module mkPLIC_16_2_7(CLK, v_sources_1_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_2$EN = !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4415,7 +4420,7 @@ module mkPLIC_16_2_7(CLK, v_sources_2_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_3$EN = !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4427,7 +4432,7 @@ module mkPLIC_16_2_7(CLK, v_sources_3_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_4$EN = !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4439,7 +4444,7 @@ module mkPLIC_16_2_7(CLK, v_sources_4_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_5$EN = !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4451,7 +4456,7 @@ module mkPLIC_16_2_7(CLK, v_sources_5_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_6$EN = !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4463,7 +4468,7 @@ module mkPLIC_16_2_7(CLK, v_sources_6_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_7$EN = !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4475,7 +4480,7 @@ module mkPLIC_16_2_7(CLK, v_sources_7_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_8$EN = !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4487,7 +4492,7 @@ module mkPLIC_16_2_7(CLK, v_sources_8_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_9$EN = !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4495,18 +4500,18 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[11:2] == 10'd0 && + addr_offset__h28467[11:2] == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4516,7 +4521,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4526,7 +4531,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4536,7 +4541,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4546,7 +4551,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4556,7 +4561,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4566,7 +4571,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4576,7 +4581,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4586,7 +4591,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4596,7 +4601,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4606,7 +4611,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4616,7 +4621,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4626,7 +4631,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4636,7 +4641,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4646,7 +4651,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4656,7 +4661,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4666,7 +4671,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4676,7 +4681,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4967,17 +4972,17 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_shim_arff assign m_slave_xactor_shim_arff$D_IN = - m_slave_xactor_ug_slave_u_ar_putWire$wget ; + m_slave_xactor_slvSynth_arSynth_snk_putWire$wget ; assign m_slave_xactor_shim_arff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut ; assign m_slave_xactor_shim_arff$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; assign m_slave_xactor_shim_arff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_awff assign m_slave_xactor_shim_awff$D_IN = - m_slave_xactor_ug_slave_u_aw_putWire$wget ; + m_slave_xactor_slvSynth_awSynth_snk_putWire$wget ; assign m_slave_xactor_shim_awff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut ; assign m_slave_xactor_shim_awff$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_awff$CLR = m_slave_xactor_clearing ; @@ -4989,27 +4994,27 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3123 } ; assign m_slave_xactor_shim_bff$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_bff$DEQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop ; assign m_slave_xactor_shim_bff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_rff assign m_slave_xactor_shim_rff$D_IN = { m_slave_xactor_shim_arff$D_OUT[97:93], - x__h27766, + x__h27825, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 ? 2'd3 : IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877, 1'd1 } ; assign m_slave_xactor_shim_rff$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; assign m_slave_xactor_shim_rff$DEQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop ; assign m_slave_xactor_shim_rff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_wff assign m_slave_xactor_shim_wff$D_IN = - m_slave_xactor_ug_slave_u_w_putWire$wget[73:1] ; + m_slave_xactor_slvSynth_wSynth_snk_putWire$wget[73:1] ; assign m_slave_xactor_shim_wff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut ; assign m_slave_xactor_shim_wff$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_wff$CLR = m_slave_xactor_clearing ; @@ -5018,14 +5023,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 : - ((x__h25030 == 32'h00200000) ? + ((x__h25089 == 32'h00200000) ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 : - x__h25030 != 32'h00200004 || + x__h25089 != 32'h00200004 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 || - x__h25371 != 5'd0) ; + x__h25430 != 5'd0) ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - addr_offset__h14540[11:2] == 10'd0 || + addr_offset__h14599[11:2] == 10'd0 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 : (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 : @@ -5036,7 +5041,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308) ? 2'd0 : 2'd2) : - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 ; + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d876 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 ? @@ -5045,7 +5050,7 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d875 ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - ((addr_offset__h14540[11:2] != 10'd0 && + ((addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106) ? 2'd0 : 2'd2) : @@ -5054,14 +5059,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 : - ((x__h25030 == 32'h00200000) ? + ((x__h25089 == 32'h00200000) ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 : - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0) ; + x__h25430 == 5'd0) ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d888 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - addr_offset__h14540[11:2] != 10'd0 && + addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 : (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 : @@ -5070,14 +5075,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 : - ((x__h68623 == 32'h00200000) ? + ((x__h68682 == 32'h00200000) ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 : - x__h68623 != 32'h00200004 || + x__h68682 != 32'h00200004 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 || !SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - addr_offset__h28408[11:2] == 10'd0 || + addr_offset__h28467[11:2] == 10'd0 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 : (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 : @@ -5088,7 +5093,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025) ? 2'd0 : 2'd2) : - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 ; + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3122 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 ? @@ -5097,7 +5102,7 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3121 ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3123 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - ((addr_offset__h28408[11:2] != 10'd0 && + ((addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959) ? 2'd0 : 2'd2) : @@ -5106,14 +5111,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 : - ((x__h68623 == 32'h00200000) ? + ((x__h68682 == 32'h00200000) ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 : - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3131 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 : (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 : @@ -5449,23 +5454,23 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200000 && + x__h25089 == 32'h00200000 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 = !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0 && + x__h25430 == 5'd0 && m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810 = !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0 && + x__h25430 == 5'd0 && m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822 = @@ -5473,9 +5478,9 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 != 5'd0 ; + x__h25430 != 5'd0 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && @@ -5493,7 +5498,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h30987 <= 10'd16 ; + source_id__h31046 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5501,7 +5506,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h32197 <= 10'd16 ; + source_id__h32256 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5509,7 +5514,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h33407 <= 10'd16 ; + source_id__h33466 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5517,7 +5522,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h34617 <= 10'd16 ; + source_id__h34676 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5525,7 +5530,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h35827 <= 10'd16 ; + source_id__h35886 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5533,7 +5538,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h37037 <= 10'd16 ; + source_id__h37096 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5541,7 +5546,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h38247 <= 10'd16 ; + source_id__h38306 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5549,7 +5554,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h39457 <= 10'd16 ; + source_id__h39516 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5557,7 +5562,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h40667 <= 10'd16 ; + source_id__h40726 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5565,7 +5570,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h41877 <= 10'd16 ; + source_id__h41936 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5573,7 +5578,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h43087 <= 10'd16 ; + source_id__h43146 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5581,7 +5586,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h44297 <= 10'd16 ; + source_id__h44356 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5589,7 +5594,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h45507 <= 10'd16 ; + source_id__h45566 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5597,7 +5602,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h46717 <= 10'd16 ; + source_id__h46776 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5605,7 +5610,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h47927 <= 10'd16 ; + source_id__h47986 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5613,7 +5618,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h49137 <= 10'd16 ; + source_id__h49196 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5621,7 +5626,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h50347 <= 10'd16 ; + source_id__h50406 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5629,7 +5634,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h51557 <= 10'd16 ; + source_id__h51616 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5637,7 +5642,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h52767 <= 10'd16 ; + source_id__h52826 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5645,7 +5650,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h53977 <= 10'd16 ; + source_id__h54036 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5653,7 +5658,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h55187 <= 10'd16 ; + source_id__h55246 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5661,7 +5666,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h56397 <= 10'd16 ; + source_id__h56456 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5669,7 +5674,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h57607 <= 10'd16 ; + source_id__h57666 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5677,7 +5682,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h58817 <= 10'd16 ; + source_id__h58876 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5685,7 +5690,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h60027 <= 10'd16 ; + source_id__h60086 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5693,7 +5698,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h61237 <= 10'd16 ; + source_id__h61296 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5701,7 +5706,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h62447 <= 10'd16 ; + source_id__h62506 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5709,7 +5714,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h63657 <= 10'd16 ; + source_id__h63716 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5717,7 +5722,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h64867 <= 10'd16 ; + source_id__h64926 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5725,7 +5730,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h66077 <= 10'd16 ; + source_id__h66136 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5733,7 +5738,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h67287 <= 10'd16 ; + source_id__h67346 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5745,14 +5750,14 @@ module mkPLIC_16_2_7(CLK, assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200000 && + x__h68682 == 32'h00200000 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200000 && + x__h68682 == 32'h00200000 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 = @@ -5760,14 +5765,14 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 && m_cfg_verbosity != 4'd0 ; @@ -5776,10631 +5781,10631 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && !SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; - assign NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439 = + assign NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447 = + assign NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455 = + assign NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463 = + assign NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471 = + assign NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479 = + assign NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487 = + assign NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490 = !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_16 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368 = + assign NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375 = + assign NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383 = + assign NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391 = + assign NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399 = + assign NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407 = + assign NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415 = + assign NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423 = + assign NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431 = + assign NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo10 = - (source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo100 = - (source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo865 ; assign _dfoo1002 = - (source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo867 ; assign _dfoo1004 = - (source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo869 ; assign _dfoo1006 = - (source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo871 ; assign _dfoo1008 = - (source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo873 ; assign _dfoo1010 = - (source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo875 ; assign _dfoo1012 = - (source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo877 ; assign _dfoo1014 = - (source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo879 ; assign _dfoo1016 = - (source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo881 ; assign _dfoo1018 = - (source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo883 ; assign _dfoo102 = - (source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo953 ; assign _dfoo1090 = - (source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo955 ; assign _dfoo1092 = - (source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo957 ; assign _dfoo1094 = - (source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo959 ; assign _dfoo1096 = - (source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo961 ; assign _dfoo1098 = - (source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo963 ; assign _dfoo11 = - source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo110 = - (source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo965 ; assign _dfoo1102 = - (source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo967 ; assign _dfoo1104 = - (source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo969 ; assign _dfoo1106 = - (source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo971 ; assign _dfoo1108 = - (source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo973 ; assign _dfoo1110 = - (source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo975 ; assign _dfoo1112 = - (source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo977 ; assign _dfoo1114 = - (source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo979 ; assign _dfoo1116 = - (source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo981 ; assign _dfoo1118 = - (source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo983 ; assign _dfoo112 = - (source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo985 ; assign _dfoo1122 = - (source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo987 ; assign _dfoo1124 = - (source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo989 ; assign _dfoo1126 = - (source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo991 ; assign _dfoo1128 = - (source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo993 ; assign _dfoo1130 = - (source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo995 ; assign _dfoo1132 = - (source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo997 ; assign _dfoo1134 = - (source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo999 ; assign _dfoo1136 = - (source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1003 ; assign _dfoo114 = - (source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo120 = - (source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1103 ; assign _dfoo124 = - (source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1123 ; assign _dfoo126 = - (source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1143 ; assign _dfoo128 = - (source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo130 = - (source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1233 ; assign _dfoo137 = - source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo1 ; assign _dfoo1370 = - (source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1243 ; assign _dfoo138 = - (source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1253 ; assign _dfoo139 = - source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo3 ; assign _dfoo1390 = - (source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1263 ; assign _dfoo14 = - (source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo140 = - (source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1273 ; assign _dfoo141 = - source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo5 ; assign _dfoo1410 = - (source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1283 ; assign _dfoo142 = - (source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo7 ; assign _dfoo1430 = - (source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo9 ; assign _dfoo1450 = - (source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo11 ; assign _dfoo1470 = - (source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo13 ; assign _dfoo1490 = - (source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1363 ; assign _dfoo15 = - source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo150 = - (source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1373 ; assign _dfoo151 = - source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo15 ; assign _dfoo1510 = - (source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1383 ; assign _dfoo152 = - (source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1393 ; assign _dfoo153 = - source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo17 ; assign _dfoo1530 = - (source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1403 ; assign _dfoo154 = - (source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1413 ; assign _dfoo155 = - source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo19 ; assign _dfoo1550 = - (source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1423 ; assign _dfoo156 = - (source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo21 ; assign _dfoo1570 = - (source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo23 ; assign _dfoo1590 = - (source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo160 = - (source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo25 ; assign _dfoo1610 = - (source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo27 ; assign _dfoo1630 = - (source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1503 ; assign _dfoo164 = - (source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1513 ; assign _dfoo165 = - source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo29 ; assign _dfoo1650 = - (source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1523 ; assign _dfoo166 = - (source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1533 ; assign _dfoo167 = - source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo31 ; assign _dfoo1670 = - (source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1543 ; assign _dfoo168 = - (source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1553 ; assign _dfoo169 = - source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo33 ; assign _dfoo1690 = - (source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1563 ; assign _dfoo17 = - source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo170 = - (source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo35 ; assign _dfoo1710 = - (source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo37 ; assign _dfoo1730 = - (source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo39 ; assign _dfoo1750 = - (source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1633 ; assign _dfoo177 = - source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo41 ; assign _dfoo1770 = - (source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1643 ; assign _dfoo178 = - (source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1653 ; assign _dfoo179 = - source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo43 ; assign _dfoo1790 = - (source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1663 ; assign _dfoo18 = - (source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo180 = - (source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1673 ; assign _dfoo181 = - source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo45 ; assign _dfoo1810 = - (source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1683 ; assign _dfoo182 = - (source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1693 ; assign _dfoo183 = - source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo47 ; assign _dfoo1830 = - (source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo49 ; assign _dfoo1850 = - (source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo51 ; assign _dfoo1870 = - (source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo53 ; assign _dfoo1890 = - (source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo190 = - (source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1773 ; assign _dfoo191 = - source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo55 ; assign _dfoo1910 = - (source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1783 ; assign _dfoo192 = - (source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1793 ; assign _dfoo193 = - source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo57 ; assign _dfoo1930 = - (source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1803 ; assign _dfoo194 = - (source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1813 ; assign _dfoo195 = - source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo59 ; assign _dfoo1950 = - (source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1823 ; assign _dfoo196 = - (source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1833 ; assign _dfoo197 = - source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo61 ; assign _dfoo1970 = - (source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo63 ; assign _dfoo1990 = - (source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo20 = - (source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo200 = - (source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo65 ; assign _dfoo2010 = - (source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo67 ; assign _dfoo2030 = - (source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h29659 == 10'd16 && + source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h29659 == 10'd15 && + source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h29659 == 10'd14 && + source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h29659 == 10'd13 && + source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h29659 == 10'd12 && + source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h29659 == 10'd11 && + source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h29659 == 10'd10 && + source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h29659 == 10'd9 && + source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h29659 == 10'd8 && + source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h29659 == 10'd7 && + source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1923 ; assign _dfoo206 = - (source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h29659 == 10'd6 && + source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h29659 == 10'd5 && + source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h29659 == 10'd4 && + source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h29659 == 10'd3 && + source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h29659 == 10'd2 && + source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h29659 == 10'd1 && + source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h29659 == 10'd0 && + source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h29659 == 10'd16 && + source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h29659 == 10'd15 && + source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h29659 == 10'd14 && + source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1943 ; assign _dfoo208 = - (source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h29659 == 10'd13 && + source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h29659 == 10'd12 && + source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h29659 == 10'd11 && + source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h29659 == 10'd10 && + source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h29659 == 10'd9 && + source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h29659 == 10'd8 && + source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h29659 == 10'd7 && + source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h29659 == 10'd6 && + source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h29659 == 10'd5 && + source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h29659 == 10'd4 && + source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1963 ; assign _dfoo21 = - source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo210 = - (source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h29659 == 10'd3 && + source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h29659 == 10'd2 && + source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h29659 == 10'd1 && + source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h29659 == 10'd0 && + source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1971 ; assign _dfoo212 = - (source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo220 = - (source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo160 ; assign _dfoo23 = - source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo230 = - (source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo240 = - (source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo180 ; assign _dfoo25 = - source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo250 = - (source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo260 = - (source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo200 ; assign _dfoo27 = - source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo270 = - (source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo204 ; assign _dfoo273 = - source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo137 ; assign _dfoo274 = - (source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo206 ; assign _dfoo275 = - source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo139 ; assign _dfoo276 = - (source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo208 ; assign _dfoo277 = - source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo141 ; assign _dfoo278 = - (source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo210 ; assign _dfoo279 = - source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo143 ; assign _dfoo28 = - (source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo280 = - (source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo212 ; assign _dfoo281 = - source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo145 ; assign _dfoo282 = - (source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo214 ; assign _dfoo283 = - source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo147 ; assign _dfoo284 = - (source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo216 ; assign _dfoo285 = - source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo149 ; assign _dfoo286 = - (source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo218 ; assign _dfoo287 = - source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo151 ; assign _dfoo288 = - (source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo220 ; assign _dfoo289 = - source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo153 ; assign _dfoo29 = - source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo290 = - (source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo222 ; assign _dfoo291 = - source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo155 ; assign _dfoo292 = - (source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo224 ; assign _dfoo293 = - source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo157 ; assign _dfoo294 = - (source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo226 ; assign _dfoo295 = - source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo159 ; assign _dfoo296 = - (source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo228 ; assign _dfoo297 = - source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo161 ; assign _dfoo298 = - (source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo230 ; assign _dfoo299 = - source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo163 ; assign _dfoo3 = - source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo30 = - (source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo300 = - (source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo232 ; assign _dfoo301 = - source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo165 ; assign _dfoo302 = - (source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo234 ; assign _dfoo303 = - source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo167 ; assign _dfoo304 = - (source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo236 ; assign _dfoo305 = - source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo169 ; assign _dfoo306 = - (source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo238 ; assign _dfoo307 = - source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo171 ; assign _dfoo308 = - (source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo240 ; assign _dfoo309 = - source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo173 ; assign _dfoo31 = - source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo310 = - (source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo242 ; assign _dfoo311 = - source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo175 ; assign _dfoo312 = - (source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo244 ; assign _dfoo313 = - source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo177 ; assign _dfoo314 = - (source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo246 ; assign _dfoo315 = - source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo179 ; assign _dfoo316 = - (source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo248 ; assign _dfoo317 = - source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo181 ; assign _dfoo318 = - (source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo250 ; assign _dfoo319 = - source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo183 ; assign _dfoo32 = - (source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo320 = - (source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo252 ; assign _dfoo321 = - source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo185 ; assign _dfoo322 = - (source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo254 ; assign _dfoo323 = - source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo187 ; assign _dfoo324 = - (source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo256 ; assign _dfoo325 = - source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo189 ; assign _dfoo326 = - (source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo258 ; assign _dfoo327 = - source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo191 ; assign _dfoo328 = - (source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo260 ; assign _dfoo329 = - source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo193 ; assign _dfoo33 = - source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo330 = - (source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo262 ; assign _dfoo331 = - source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo195 ; assign _dfoo332 = - (source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo264 ; assign _dfoo333 = - source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo197 ; assign _dfoo334 = - (source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo266 ; assign _dfoo335 = - source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo199 ; assign _dfoo336 = - (source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo268 ; assign _dfoo337 = - source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo201 ; assign _dfoo338 = - (source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo270 ; assign _dfoo339 = - source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo203 ; assign _dfoo34 = - (source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo340 = - (source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo280 ; assign _dfoo35 = - source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo350 = - (source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo360 = - (source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo300 ; assign _dfoo37 = - source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo370 = - (source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo380 = - (source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo320 ; assign _dfoo39 = - source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo390 = - (source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo40 = - (source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo400 = - (source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo340 ; assign _dfoo409 = - source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo273 ; assign _dfoo41 = - source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo410 = - (source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo342 ; assign _dfoo411 = - source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo275 ; assign _dfoo412 = - (source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo344 ; assign _dfoo413 = - source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo277 ; assign _dfoo414 = - (source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo346 ; assign _dfoo415 = - source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo279 ; assign _dfoo416 = - (source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo348 ; assign _dfoo417 = - source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo281 ; assign _dfoo418 = - (source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo350 ; assign _dfoo419 = - source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo283 ; assign _dfoo42 = - (source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo420 = - (source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo352 ; assign _dfoo421 = - source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo285 ; assign _dfoo422 = - (source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo354 ; assign _dfoo423 = - source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo287 ; assign _dfoo424 = - (source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo356 ; assign _dfoo425 = - source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo289 ; assign _dfoo426 = - (source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo358 ; assign _dfoo427 = - source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo291 ; assign _dfoo428 = - (source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo360 ; assign _dfoo429 = - source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo293 ; assign _dfoo43 = - source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo430 = - (source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo362 ; assign _dfoo431 = - source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo295 ; assign _dfoo432 = - (source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo364 ; assign _dfoo433 = - source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo297 ; assign _dfoo434 = - (source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo366 ; assign _dfoo435 = - source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo299 ; assign _dfoo436 = - (source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo368 ; assign _dfoo437 = - source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo301 ; assign _dfoo438 = - (source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo370 ; assign _dfoo439 = - source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo303 ; assign _dfoo44 = - (source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo440 = - (source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo372 ; assign _dfoo441 = - source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo305 ; assign _dfoo442 = - (source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo374 ; assign _dfoo443 = - source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo307 ; assign _dfoo444 = - (source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo376 ; assign _dfoo445 = - source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo309 ; assign _dfoo446 = - (source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo378 ; assign _dfoo447 = - source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo311 ; assign _dfoo448 = - (source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo380 ; assign _dfoo449 = - source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo313 ; assign _dfoo45 = - source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo450 = - (source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo382 ; assign _dfoo451 = - source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo315 ; assign _dfoo452 = - (source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo384 ; assign _dfoo453 = - source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo317 ; assign _dfoo454 = - (source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo386 ; assign _dfoo455 = - source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo319 ; assign _dfoo456 = - (source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo388 ; assign _dfoo457 = - source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo321 ; assign _dfoo458 = - (source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo390 ; assign _dfoo459 = - source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo323 ; assign _dfoo46 = - (source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo460 = - (source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo392 ; assign _dfoo461 = - source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo325 ; assign _dfoo462 = - (source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo394 ; assign _dfoo463 = - source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo327 ; assign _dfoo464 = - (source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo396 ; assign _dfoo465 = - source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo329 ; assign _dfoo466 = - (source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo398 ; assign _dfoo467 = - source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo331 ; assign _dfoo468 = - (source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo400 ; assign _dfoo469 = - source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo333 ; assign _dfoo47 = - source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo470 = - (source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo402 ; assign _dfoo471 = - source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo335 ; assign _dfoo472 = - (source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo404 ; assign _dfoo473 = - source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo337 ; assign _dfoo474 = - (source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo406 ; assign _dfoo475 = - source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo339 ; assign _dfoo476 = - (source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo480 = - (source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo420 ; assign _dfoo49 = - source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo490 = - (source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo430 ; assign _dfoo5 = - source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo50 = - (source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo500 = - (source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo440 ; assign _dfoo51 = - source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo510 = - (source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo520 = - (source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo460 ; assign _dfoo53 = - source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo530 = - (source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo540 = - (source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo476 ; assign _dfoo545 = - source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo409 ; assign _dfoo546 = - (source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo478 ; assign _dfoo547 = - source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo411 ; assign _dfoo548 = - (source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo480 ; assign _dfoo549 = - source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo413 ; assign _dfoo55 = - source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo550 = - (source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo482 ; assign _dfoo551 = - source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo415 ; assign _dfoo552 = - (source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo484 ; assign _dfoo553 = - source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo417 ; assign _dfoo554 = - (source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo486 ; assign _dfoo555 = - source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo419 ; assign _dfoo556 = - (source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo488 ; assign _dfoo557 = - source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo421 ; assign _dfoo558 = - (source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo490 ; assign _dfoo559 = - source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo423 ; assign _dfoo56 = - (source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo560 = - (source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo492 ; assign _dfoo561 = - source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo425 ; assign _dfoo562 = - (source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo494 ; assign _dfoo563 = - source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo427 ; assign _dfoo564 = - (source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo496 ; assign _dfoo565 = - source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo429 ; assign _dfoo566 = - (source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo498 ; assign _dfoo567 = - source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo431 ; assign _dfoo568 = - (source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo500 ; assign _dfoo569 = - source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo433 ; assign _dfoo57 = - source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo570 = - (source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo502 ; assign _dfoo571 = - source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo435 ; assign _dfoo572 = - (source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo504 ; assign _dfoo573 = - source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo437 ; assign _dfoo574 = - (source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo506 ; assign _dfoo575 = - source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo439 ; assign _dfoo576 = - (source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo508 ; assign _dfoo577 = - source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo441 ; assign _dfoo578 = - (source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo510 ; assign _dfoo579 = - source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo443 ; assign _dfoo58 = - (source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo580 = - (source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo512 ; assign _dfoo581 = - source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo445 ; assign _dfoo582 = - (source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo514 ; assign _dfoo583 = - source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo447 ; assign _dfoo584 = - (source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo516 ; assign _dfoo585 = - source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo449 ; assign _dfoo586 = - (source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo518 ; assign _dfoo587 = - source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo451 ; assign _dfoo588 = - (source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo520 ; assign _dfoo589 = - source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo453 ; assign _dfoo59 = - source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo590 = - (source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo522 ; assign _dfoo591 = - source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo455 ; assign _dfoo592 = - (source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo524 ; assign _dfoo593 = - source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo457 ; assign _dfoo594 = - (source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo526 ; assign _dfoo595 = - source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo459 ; assign _dfoo596 = - (source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo528 ; assign _dfoo597 = - source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo461 ; assign _dfoo598 = - (source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo530 ; assign _dfoo599 = - source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo463 ; assign _dfoo6 = - (source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo60 = - (source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo600 = - (source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo532 ; assign _dfoo601 = - source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo465 ; assign _dfoo602 = - (source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo534 ; assign _dfoo603 = - source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo467 ; assign _dfoo604 = - (source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo536 ; assign _dfoo605 = - source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo469 ; assign _dfoo606 = - (source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo538 ; assign _dfoo607 = - source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo471 ; assign _dfoo608 = - (source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo540 ; assign _dfoo609 = - source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo473 ; assign _dfoo61 = - source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo610 = - (source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo542 ; assign _dfoo611 = - source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo475 ; assign _dfoo612 = - (source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo620 = - (source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo560 ; assign _dfoo63 = - source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo630 = - (source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo640 = - (source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo580 ; assign _dfoo65 = - source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo650 = - (source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo660 = - (source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo600 ; assign _dfoo67 = - source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo670 = - (source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo680 = - (source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo612 ; assign _dfoo681 = - source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo545 ; assign _dfoo682 = - (source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo614 ; assign _dfoo683 = - source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo547 ; assign _dfoo684 = - (source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo616 ; assign _dfoo685 = - source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo549 ; assign _dfoo686 = - (source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo618 ; assign _dfoo687 = - source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo551 ; assign _dfoo688 = - (source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo620 ; assign _dfoo689 = - source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo553 ; assign _dfoo690 = - (source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo622 ; assign _dfoo691 = - source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo555 ; assign _dfoo692 = - (source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo624 ; assign _dfoo693 = - source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo557 ; assign _dfoo694 = - (source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo626 ; assign _dfoo695 = - source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo559 ; assign _dfoo696 = - (source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo628 ; assign _dfoo697 = - source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo561 ; assign _dfoo698 = - (source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo630 ; assign _dfoo699 = - source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo563 ; assign _dfoo7 = - source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo70 = - (source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo632 ; assign _dfoo701 = - source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo565 ; assign _dfoo702 = - (source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo634 ; assign _dfoo703 = - source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo567 ; assign _dfoo704 = - (source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo636 ; assign _dfoo705 = - source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo569 ; assign _dfoo706 = - (source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo638 ; assign _dfoo707 = - source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo571 ; assign _dfoo708 = - (source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo640 ; assign _dfoo709 = - source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo573 ; assign _dfoo710 = - (source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo642 ; assign _dfoo711 = - source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo575 ; assign _dfoo712 = - (source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo644 ; assign _dfoo713 = - source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo577 ; assign _dfoo714 = - (source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo646 ; assign _dfoo715 = - source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo579 ; assign _dfoo716 = - (source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo648 ; assign _dfoo717 = - source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo581 ; assign _dfoo718 = - (source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo650 ; assign _dfoo719 = - source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo583 ; assign _dfoo72 = - (source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo652 ; assign _dfoo721 = - source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo585 ; assign _dfoo722 = - (source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo654 ; assign _dfoo723 = - source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo587 ; assign _dfoo724 = - (source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo656 ; assign _dfoo725 = - source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo589 ; assign _dfoo726 = - (source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo658 ; assign _dfoo727 = - source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo591 ; assign _dfoo728 = - (source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo660 ; assign _dfoo729 = - source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo593 ; assign _dfoo730 = - (source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo662 ; assign _dfoo731 = - source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo595 ; assign _dfoo732 = - (source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo664 ; assign _dfoo733 = - source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo597 ; assign _dfoo734 = - (source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo666 ; assign _dfoo735 = - source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo599 ; assign _dfoo736 = - (source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo668 ; assign _dfoo737 = - source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo601 ; assign _dfoo738 = - (source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo670 ; assign _dfoo739 = - source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo603 ; assign _dfoo74 = - (source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo672 ; assign _dfoo741 = - source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo605 ; assign _dfoo742 = - (source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo674 ; assign _dfoo743 = - source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo607 ; assign _dfoo744 = - (source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo676 ; assign _dfoo745 = - source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo609 ; assign _dfoo746 = - (source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo678 ; assign _dfoo747 = - source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo611 ; assign _dfoo748 = - (source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo80 = - (source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo748 ; assign _dfoo817 = - source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo681 ; assign _dfoo818 = - (source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo750 ; assign _dfoo819 = - source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo683 ; assign _dfoo82 = - (source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo752 ; assign _dfoo821 = - source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo685 ; assign _dfoo822 = - (source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo754 ; assign _dfoo823 = - source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo687 ; assign _dfoo824 = - (source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo756 ; assign _dfoo825 = - source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo689 ; assign _dfoo826 = - (source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo758 ; assign _dfoo827 = - source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo691 ; assign _dfoo828 = - (source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo760 ; assign _dfoo829 = - source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo693 ; assign _dfoo830 = - (source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo762 ; assign _dfoo831 = - source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo695 ; assign _dfoo832 = - (source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo764 ; assign _dfoo833 = - source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo697 ; assign _dfoo834 = - (source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo766 ; assign _dfoo835 = - source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo699 ; assign _dfoo836 = - (source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo768 ; assign _dfoo837 = - source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo701 ; assign _dfoo838 = - (source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo770 ; assign _dfoo839 = - source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo703 ; assign _dfoo84 = - (source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo772 ; assign _dfoo841 = - source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo705 ; assign _dfoo842 = - (source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo774 ; assign _dfoo843 = - source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo707 ; assign _dfoo844 = - (source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo776 ; assign _dfoo845 = - source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo709 ; assign _dfoo846 = - (source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo778 ; assign _dfoo847 = - source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo711 ; assign _dfoo848 = - (source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo780 ; assign _dfoo849 = - source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo713 ; assign _dfoo850 = - (source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo782 ; assign _dfoo851 = - source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo715 ; assign _dfoo852 = - (source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo784 ; assign _dfoo853 = - source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo717 ; assign _dfoo854 = - (source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo786 ; assign _dfoo855 = - source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo719 ; assign _dfoo856 = - (source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo788 ; assign _dfoo857 = - source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo721 ; assign _dfoo858 = - (source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo790 ; assign _dfoo859 = - source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo723 ; assign _dfoo86 = - (source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo792 ; assign _dfoo861 = - source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo725 ; assign _dfoo862 = - (source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo794 ; assign _dfoo863 = - source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo727 ; assign _dfoo864 = - (source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo796 ; assign _dfoo865 = - source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo729 ; assign _dfoo866 = - (source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo798 ; assign _dfoo867 = - source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo731 ; assign _dfoo868 = - (source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo800 ; assign _dfoo869 = - source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo733 ; assign _dfoo870 = - (source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo802 ; assign _dfoo871 = - source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo735 ; assign _dfoo872 = - (source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo804 ; assign _dfoo873 = - source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo737 ; assign _dfoo874 = - (source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo806 ; assign _dfoo875 = - source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo739 ; assign _dfoo876 = - (source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo808 ; assign _dfoo877 = - source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo741 ; assign _dfoo878 = - (source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo810 ; assign _dfoo879 = - source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo743 ; assign _dfoo88 = - (source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo812 ; assign _dfoo881 = - source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo745 ; assign _dfoo882 = - (source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo814 ; assign _dfoo883 = - source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo747 ; assign _dfoo884 = - (source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo830 ; assign _dfoo9 = - source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo90 = - (source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo884 ; assign _dfoo953 = - source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo817 ; assign _dfoo954 = - (source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo886 ; assign _dfoo955 = - source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo819 ; assign _dfoo956 = - (source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo888 ; assign _dfoo957 = - source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo821 ; assign _dfoo958 = - (source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo890 ; assign _dfoo959 = - source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo823 ; assign _dfoo96 = - (source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo892 ; assign _dfoo961 = - source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo825 ; assign _dfoo962 = - (source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo894 ; assign _dfoo963 = - source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo827 ; assign _dfoo964 = - (source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo896 ; assign _dfoo965 = - source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo829 ; assign _dfoo966 = - (source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo898 ; assign _dfoo967 = - source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo831 ; assign _dfoo968 = - (source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo900 ; assign _dfoo969 = - source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo833 ; assign _dfoo970 = - (source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo902 ; assign _dfoo971 = - source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo835 ; assign _dfoo972 = - (source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo904 ; assign _dfoo973 = - source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo837 ; assign _dfoo974 = - (source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo906 ; assign _dfoo975 = - source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo839 ; assign _dfoo976 = - (source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo908 ; assign _dfoo977 = - source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo841 ; assign _dfoo978 = - (source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo910 ; assign _dfoo979 = - source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo843 ; assign _dfoo98 = - (source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo912 ; assign _dfoo981 = - source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo845 ; assign _dfoo982 = - (source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo914 ; assign _dfoo983 = - source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo847 ; assign _dfoo984 = - (source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo916 ; assign _dfoo985 = - source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo849 ; assign _dfoo986 = - (source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo918 ; assign _dfoo987 = - source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo851 ; assign _dfoo988 = - (source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo920 ; assign _dfoo989 = - source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo853 ; assign _dfoo990 = - (source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo922 ; assign _dfoo991 = - source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo855 ; assign _dfoo992 = - (source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo924 ; assign _dfoo993 = - source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo857 ; assign _dfoo994 = - (source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo926 ; assign _dfoo995 = - source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo859 ; assign _dfoo996 = - (source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo928 ; assign _dfoo997 = - source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo861 ; assign _dfoo998 = - (source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo930 ; assign _dfoo999 = - source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo863 ; - assign a__h72910 = + assign a__h72969 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 ? m_vrg_source_prio_16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3211 ; - assign a__h74915 = + assign a__h74974 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3309 ? m_vrg_source_prio_16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3305 ; - assign addr_offset__h14540 = + assign addr_offset__h14599 = m_slave_xactor_shim_arff$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h28408 = + assign addr_offset__h28467 = m_slave_xactor_shim_awff$D_OUT[92:29] - m_rg_addr_base ; - assign b__h72911 = + assign b__h72970 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3231 ; - assign b__h74916 = + assign b__h74975 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3309 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3325 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 = - addr_offset__h14540 < 64'h0000000000001000 ; + addr_offset__h14599 < 64'h0000000000001000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 = - addr_offset__h14540[11:2] <= 10'd16 ; + addr_offset__h14599[11:2] <= 10'd16 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && - addr_offset__h14540[11:2] != 10'd0 && + addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 && m_cfg_verbosity != 4'd0 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 = - addr_offset__h14540 < 64'h0000000000002000 ; + addr_offset__h14599 < 64'h0000000000002000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 = - source_id_base__h14985 <= 10'd16 ; + source_id_base__h15044 <= 10'd16 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 = - addr_offset__h14540 < 64'h0000000000003000 ; + addr_offset__h14599 < 64'h0000000000003000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 = - addr_offset__h14540[11:7] <= 5'd1 ; + addr_offset__h14599[11:7] <= 5'd1 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 = - addr_offset__h14540[16:12] <= 5'd1 ; + addr_offset__h14599[16:12] <= 5'd1 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 = m_slave_xactor_shim_arff$D_OUT[92:29] < m_rg_addr_base ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1001 = - addr_offset__h28408[11:2] == 10'd15 && + addr_offset__h28467[11:2] == 10'd15 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1003 = - addr_offset__h28408[11:2] == 10'd16 && + addr_offset__h28467[11:2] == 10'd16 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 && m_cfg_verbosity != 4'd0 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 = - addr_offset__h28408 < 64'h0000000000002000 ; + addr_offset__h28467 < 64'h0000000000002000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 = - source_id_base__h29659 <= 10'd16 ; + source_id_base__h29718 <= 10'd16 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 = - addr_offset__h28408 < 64'h0000000000003000 ; + addr_offset__h28467 < 64'h0000000000003000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 = - addr_offset__h28408[11:7] <= 5'd1 ; + addr_offset__h28467[11:7] <= 5'd1 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 = - addr_offset__h28408[11:7] == 5'd0 && + addr_offset__h28467[11:7] == 5'd0 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1028 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 = - addr_offset__h28408[11:7] == 5'd1 && + addr_offset__h28467[11:7] == 5'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1028 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 = - addr_offset__h28408[16:12] <= 5'd1 ; + addr_offset__h28467[16:12] <= 5'd1 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2996 = - addr_offset__h28408[16:12] == 5'd0 && + addr_offset__h28467[16:12] == 5'd0 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2998 = - addr_offset__h28408[16:12] == 5'd1 && + addr_offset__h28467[16:12] == 5'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 = m_slave_xactor_shim_awff$D_OUT[92:29] < m_rg_addr_base ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 = - addr_offset__h28408 < 64'h0000000000001000 ; + addr_offset__h28467 < 64'h0000000000001000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 = - addr_offset__h28408[11:2] <= 10'd16 ; + addr_offset__h28467[11:2] <= 10'd16 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d973 = - addr_offset__h28408[11:2] == 10'd1 && + addr_offset__h28467[11:2] == 10'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d975 = - addr_offset__h28408[11:2] == 10'd2 && + addr_offset__h28467[11:2] == 10'd2 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d977 = - addr_offset__h28408[11:2] == 10'd3 && + addr_offset__h28467[11:2] == 10'd3 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d979 = - addr_offset__h28408[11:2] == 10'd4 && + addr_offset__h28467[11:2] == 10'd4 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d981 = - addr_offset__h28408[11:2] == 10'd5 && + addr_offset__h28467[11:2] == 10'd5 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d983 = - addr_offset__h28408[11:2] == 10'd6 && + addr_offset__h28467[11:2] == 10'd6 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d985 = - addr_offset__h28408[11:2] == 10'd7 && + addr_offset__h28467[11:2] == 10'd7 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d987 = - addr_offset__h28408[11:2] == 10'd8 && + addr_offset__h28467[11:2] == 10'd8 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d989 = - addr_offset__h28408[11:2] == 10'd9 && + addr_offset__h28467[11:2] == 10'd9 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d991 = - addr_offset__h28408[11:2] == 10'd10 && + addr_offset__h28467[11:2] == 10'd10 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d993 = - addr_offset__h28408[11:2] == 10'd11 && + addr_offset__h28467[11:2] == 10'd11 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d995 = - addr_offset__h28408[11:2] == 10'd12 && + addr_offset__h28467[11:2] == 10'd12 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d997 = - addr_offset__h28408[11:2] == 10'd13 && + addr_offset__h28467[11:2] == 10'd13 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d999 = - addr_offset__h28408[11:2] == 10'd14 && + addr_offset__h28467[11:2] == 10'd14 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; @@ -16418,7 +16423,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_10 && m_vrg_source_prio_10 > IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d674 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; assign m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_sour_ETC___d3190 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > @@ -16433,7 +16438,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_11 && m_vrg_source_prio_11 > IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d681 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; assign m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_sour_ETC___d3195 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > @@ -16448,7 +16453,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_12 && m_vrg_source_prio_12 > IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d688 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; assign m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d3200 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > @@ -16463,7 +16468,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 && m_vrg_source_prio_13 > IF_m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_s_ETC___d695 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; assign m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d757 = m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d701 || m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_sour_ETC___d694 || @@ -16486,7 +16491,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_14 && m_vrg_source_prio_14 > IF_m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_s_ETC___d702 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; assign m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d3210 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > @@ -16501,7 +16506,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_15 && m_vrg_source_prio_15 > IF_m_vrg_source_ip_14_read__60_AND_NOT_m_vrg_s_ETC___d709 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > @@ -16515,7 +16520,7 @@ module mkPLIC_16_2_7(CLK, assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 = m_vrg_source_ip_16 && !m_vrg_source_prio_16_29_ULE_IF_m_vrg_source_ip_ETC___d717 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 || m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d715 || @@ -16523,7 +16528,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d757 ; assign m_vrg_source_ip_1_read__47_AND_NOT_m_vrg_sourc_ETC___d617 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; assign m_vrg_source_ip_2_read__48_AND_NOT_m_vrg_sourc_ETC___d3145 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > @@ -16538,7 +16543,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_2 && m_vrg_source_prio_2 > IF_m_vrg_source_ip_1_read__47_AND_NOT_m_vrg_so_ETC___d618 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; assign m_vrg_source_ip_3_read__49_AND_NOT_m_vrg_sourc_ETC___d3150 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > @@ -16553,7 +16558,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_3 && m_vrg_source_prio_3 > IF_m_vrg_source_ip_2_read__48_AND_NOT_m_vrg_so_ETC___d625 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; assign m_vrg_source_ip_4_read__50_AND_NOT_m_vrg_sourc_ETC___d3155 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > @@ -16568,7 +16573,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_4 && m_vrg_source_prio_4 > IF_m_vrg_source_ip_3_read__49_AND_NOT_m_vrg_so_ETC___d632 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; assign m_vrg_source_ip_5_read__51_AND_NOT_m_vrg_sourc_ETC___d3160 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > @@ -16583,7 +16588,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_5 && m_vrg_source_prio_5 > IF_m_vrg_source_ip_4_read__50_AND_NOT_m_vrg_so_ETC___d639 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; assign m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_sourc_ETC___d3165 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > @@ -16598,7 +16603,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_6 && m_vrg_source_prio_6 > IF_m_vrg_source_ip_5_read__51_AND_NOT_m_vrg_so_ETC___d646 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; assign m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d3170 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > @@ -16613,7 +16618,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_7 && m_vrg_source_prio_7 > IF_m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_so_ETC___d653 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; assign m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d751 = m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d659 || m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_sourc_ETC___d652 || @@ -16636,7 +16641,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_8 && m_vrg_source_prio_8 > IF_m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_so_ETC___d660 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; assign m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_sourc_ETC___d3180 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > @@ -16651,306 +16656,306 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_9 && m_vrg_source_prio_9 > IF_m_vrg_source_ip_8_read__54_AND_NOT_m_vrg_so_ETC___d667 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; assign m_vrg_source_prio_16_29_ULE_IF_m_vrg_source_ip_ETC___d717 = m_vrg_source_prio_16 <= (m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d715 ? m_vrg_source_prio_15 : IF_m_vrg_source_ip_14_read__60_AND_NOT_m_vrg_s_ETC___d709) ; - assign max_id__h25318 = + assign max_id__h25377 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d737 ; - assign rdata___1__h27806 = { rdata__h27563[31:0], 32'h0 } ; - assign rdata__h27563 = + assign rdata___1__h27865 = { rdata__h27622[31:0], 32'h0 } ; + assign rdata__h27622 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 ? 64'd0 : - y_avValue_fst__h27555 ; - assign source_id__h17021 = { addr_offset__h14540[4:0], 5'd31 } ; - assign source_id__h17128 = { addr_offset__h14540[4:0], 5'd30 } ; - assign source_id__h17201 = { addr_offset__h14540[4:0], 5'd29 } ; - assign source_id__h17274 = { addr_offset__h14540[4:0], 5'd28 } ; - assign source_id__h17347 = { addr_offset__h14540[4:0], 5'd27 } ; - assign source_id__h17420 = { addr_offset__h14540[4:0], 5'd26 } ; - assign source_id__h17493 = { addr_offset__h14540[4:0], 5'd25 } ; - assign source_id__h17566 = { addr_offset__h14540[4:0], 5'd24 } ; - assign source_id__h17639 = { addr_offset__h14540[4:0], 5'd23 } ; - assign source_id__h17712 = { addr_offset__h14540[4:0], 5'd22 } ; - assign source_id__h17785 = { addr_offset__h14540[4:0], 5'd21 } ; - assign source_id__h17858 = { addr_offset__h14540[4:0], 5'd20 } ; - assign source_id__h17931 = { addr_offset__h14540[4:0], 5'd19 } ; - assign source_id__h18004 = { addr_offset__h14540[4:0], 5'd18 } ; - assign source_id__h18077 = { addr_offset__h14540[4:0], 5'd17 } ; - assign source_id__h18150 = { addr_offset__h14540[4:0], 5'd16 } ; - assign source_id__h18223 = { addr_offset__h14540[4:0], 5'd15 } ; - assign source_id__h18296 = { addr_offset__h14540[4:0], 5'd14 } ; - assign source_id__h18369 = { addr_offset__h14540[4:0], 5'd13 } ; - assign source_id__h18442 = { addr_offset__h14540[4:0], 5'd12 } ; - assign source_id__h18515 = { addr_offset__h14540[4:0], 5'd11 } ; - assign source_id__h18588 = { addr_offset__h14540[4:0], 5'd10 } ; - assign source_id__h18661 = { addr_offset__h14540[4:0], 5'd9 } ; - assign source_id__h18734 = { addr_offset__h14540[4:0], 5'd8 } ; - assign source_id__h18807 = { addr_offset__h14540[4:0], 5'd7 } ; - assign source_id__h18880 = { addr_offset__h14540[4:0], 5'd6 } ; - assign source_id__h18953 = { addr_offset__h14540[4:0], 5'd5 } ; - assign source_id__h19026 = { addr_offset__h14540[4:0], 5'd4 } ; - assign source_id__h19099 = { addr_offset__h14540[4:0], 5'd3 } ; - assign source_id__h19172 = { addr_offset__h14540[4:0], 5'd2 } ; - assign source_id__h19245 = { addr_offset__h14540[4:0], 5'd1 } ; - assign source_id__h21494 = 10'd31 + source_id_base__h14985 ; - assign source_id__h21670 = 10'd30 + source_id_base__h14985 ; - assign source_id__h21778 = 10'd29 + source_id_base__h14985 ; - assign source_id__h21886 = 10'd28 + source_id_base__h14985 ; - assign source_id__h21994 = 10'd27 + source_id_base__h14985 ; - assign source_id__h22102 = 10'd26 + source_id_base__h14985 ; - assign source_id__h22210 = 10'd25 + source_id_base__h14985 ; - assign source_id__h22318 = 10'd24 + source_id_base__h14985 ; - assign source_id__h22426 = 10'd23 + source_id_base__h14985 ; - assign source_id__h22534 = 10'd22 + source_id_base__h14985 ; - assign source_id__h22642 = 10'd21 + source_id_base__h14985 ; - assign source_id__h22750 = 10'd20 + source_id_base__h14985 ; - assign source_id__h22858 = 10'd19 + source_id_base__h14985 ; - assign source_id__h22966 = 10'd18 + source_id_base__h14985 ; - assign source_id__h23074 = 10'd17 + source_id_base__h14985 ; - assign source_id__h23182 = 10'd16 + source_id_base__h14985 ; - assign source_id__h23290 = 10'd15 + source_id_base__h14985 ; - assign source_id__h23398 = 10'd14 + source_id_base__h14985 ; - assign source_id__h23506 = 10'd13 + source_id_base__h14985 ; - assign source_id__h23614 = 10'd12 + source_id_base__h14985 ; - assign source_id__h23722 = 10'd11 + source_id_base__h14985 ; - assign source_id__h23830 = 10'd10 + source_id_base__h14985 ; - assign source_id__h23938 = 10'd9 + source_id_base__h14985 ; - assign source_id__h24046 = 10'd8 + source_id_base__h14985 ; - assign source_id__h24154 = 10'd7 + source_id_base__h14985 ; - assign source_id__h24262 = 10'd6 + source_id_base__h14985 ; - assign source_id__h24370 = 10'd5 + source_id_base__h14985 ; - assign source_id__h24478 = 10'd4 + source_id_base__h14985 ; - assign source_id__h24586 = 10'd3 + source_id_base__h14985 ; - assign source_id__h24694 = 10'd2 + source_id_base__h14985 ; - assign source_id__h24802 = 10'd1 + source_id_base__h14985 ; - assign source_id__h30987 = { addr_offset__h28408[4:0], 5'd1 } ; - assign source_id__h32197 = { addr_offset__h28408[4:0], 5'd2 } ; - assign source_id__h33407 = { addr_offset__h28408[4:0], 5'd3 } ; - assign source_id__h34617 = { addr_offset__h28408[4:0], 5'd4 } ; - assign source_id__h35827 = { addr_offset__h28408[4:0], 5'd5 } ; - assign source_id__h37037 = { addr_offset__h28408[4:0], 5'd6 } ; - assign source_id__h38247 = { addr_offset__h28408[4:0], 5'd7 } ; - assign source_id__h39457 = { addr_offset__h28408[4:0], 5'd8 } ; - assign source_id__h40667 = { addr_offset__h28408[4:0], 5'd9 } ; - assign source_id__h41877 = { addr_offset__h28408[4:0], 5'd10 } ; - assign source_id__h43087 = { addr_offset__h28408[4:0], 5'd11 } ; - assign source_id__h44297 = { addr_offset__h28408[4:0], 5'd12 } ; - assign source_id__h45507 = { addr_offset__h28408[4:0], 5'd13 } ; - assign source_id__h46717 = { addr_offset__h28408[4:0], 5'd14 } ; - assign source_id__h47927 = { addr_offset__h28408[4:0], 5'd15 } ; - assign source_id__h49137 = { addr_offset__h28408[4:0], 5'd16 } ; - assign source_id__h50347 = { addr_offset__h28408[4:0], 5'd17 } ; - assign source_id__h51557 = { addr_offset__h28408[4:0], 5'd18 } ; - assign source_id__h52767 = { addr_offset__h28408[4:0], 5'd19 } ; - assign source_id__h53977 = { addr_offset__h28408[4:0], 5'd20 } ; - assign source_id__h55187 = { addr_offset__h28408[4:0], 5'd21 } ; - assign source_id__h56397 = { addr_offset__h28408[4:0], 5'd22 } ; - assign source_id__h57607 = { addr_offset__h28408[4:0], 5'd23 } ; - assign source_id__h58817 = { addr_offset__h28408[4:0], 5'd24 } ; - assign source_id__h60027 = { addr_offset__h28408[4:0], 5'd25 } ; - assign source_id__h61237 = { addr_offset__h28408[4:0], 5'd26 } ; - assign source_id__h62447 = { addr_offset__h28408[4:0], 5'd27 } ; - assign source_id__h63657 = { addr_offset__h28408[4:0], 5'd28 } ; - assign source_id__h64867 = { addr_offset__h28408[4:0], 5'd29 } ; - assign source_id__h66077 = { addr_offset__h28408[4:0], 5'd30 } ; - assign source_id__h67287 = { addr_offset__h28408[4:0], 5'd31 } ; - assign source_id__h68952 = { 5'd0, x__h69004 } ; - assign source_id_base__h14985 = { addr_offset__h14540[4:0], 5'h0 } ; - assign source_id_base__h29659 = { addr_offset__h28408[4:0], 5'h0 } ; - assign v__h14777 = { 61'd0, x__h14848 } ; - assign v__h15027 = { 32'd0, v_ip__h15030 } ; - assign v__h19501 = { 32'd0, v_ie__h19504 } ; - assign v__h25119 = { 61'd0, x__h25190 } ; - assign v__h26816 = + y_avValue_fst__h27614 ; + assign source_id__h17080 = { addr_offset__h14599[4:0], 5'd31 } ; + assign source_id__h17187 = { addr_offset__h14599[4:0], 5'd30 } ; + assign source_id__h17260 = { addr_offset__h14599[4:0], 5'd29 } ; + assign source_id__h17333 = { addr_offset__h14599[4:0], 5'd28 } ; + assign source_id__h17406 = { addr_offset__h14599[4:0], 5'd27 } ; + assign source_id__h17479 = { addr_offset__h14599[4:0], 5'd26 } ; + assign source_id__h17552 = { addr_offset__h14599[4:0], 5'd25 } ; + assign source_id__h17625 = { addr_offset__h14599[4:0], 5'd24 } ; + assign source_id__h17698 = { addr_offset__h14599[4:0], 5'd23 } ; + assign source_id__h17771 = { addr_offset__h14599[4:0], 5'd22 } ; + assign source_id__h17844 = { addr_offset__h14599[4:0], 5'd21 } ; + assign source_id__h17917 = { addr_offset__h14599[4:0], 5'd20 } ; + assign source_id__h17990 = { addr_offset__h14599[4:0], 5'd19 } ; + assign source_id__h18063 = { addr_offset__h14599[4:0], 5'd18 } ; + assign source_id__h18136 = { addr_offset__h14599[4:0], 5'd17 } ; + assign source_id__h18209 = { addr_offset__h14599[4:0], 5'd16 } ; + assign source_id__h18282 = { addr_offset__h14599[4:0], 5'd15 } ; + assign source_id__h18355 = { addr_offset__h14599[4:0], 5'd14 } ; + assign source_id__h18428 = { addr_offset__h14599[4:0], 5'd13 } ; + assign source_id__h18501 = { addr_offset__h14599[4:0], 5'd12 } ; + assign source_id__h18574 = { addr_offset__h14599[4:0], 5'd11 } ; + assign source_id__h18647 = { addr_offset__h14599[4:0], 5'd10 } ; + assign source_id__h18720 = { addr_offset__h14599[4:0], 5'd9 } ; + assign source_id__h18793 = { addr_offset__h14599[4:0], 5'd8 } ; + assign source_id__h18866 = { addr_offset__h14599[4:0], 5'd7 } ; + assign source_id__h18939 = { addr_offset__h14599[4:0], 5'd6 } ; + assign source_id__h19012 = { addr_offset__h14599[4:0], 5'd5 } ; + assign source_id__h19085 = { addr_offset__h14599[4:0], 5'd4 } ; + assign source_id__h19158 = { addr_offset__h14599[4:0], 5'd3 } ; + assign source_id__h19231 = { addr_offset__h14599[4:0], 5'd2 } ; + assign source_id__h19304 = { addr_offset__h14599[4:0], 5'd1 } ; + assign source_id__h21553 = 10'd31 + source_id_base__h15044 ; + assign source_id__h21729 = 10'd30 + source_id_base__h15044 ; + assign source_id__h21837 = 10'd29 + source_id_base__h15044 ; + assign source_id__h21945 = 10'd28 + source_id_base__h15044 ; + assign source_id__h22053 = 10'd27 + source_id_base__h15044 ; + assign source_id__h22161 = 10'd26 + source_id_base__h15044 ; + assign source_id__h22269 = 10'd25 + source_id_base__h15044 ; + assign source_id__h22377 = 10'd24 + source_id_base__h15044 ; + assign source_id__h22485 = 10'd23 + source_id_base__h15044 ; + assign source_id__h22593 = 10'd22 + source_id_base__h15044 ; + assign source_id__h22701 = 10'd21 + source_id_base__h15044 ; + assign source_id__h22809 = 10'd20 + source_id_base__h15044 ; + assign source_id__h22917 = 10'd19 + source_id_base__h15044 ; + assign source_id__h23025 = 10'd18 + source_id_base__h15044 ; + assign source_id__h23133 = 10'd17 + source_id_base__h15044 ; + assign source_id__h23241 = 10'd16 + source_id_base__h15044 ; + assign source_id__h23349 = 10'd15 + source_id_base__h15044 ; + assign source_id__h23457 = 10'd14 + source_id_base__h15044 ; + assign source_id__h23565 = 10'd13 + source_id_base__h15044 ; + assign source_id__h23673 = 10'd12 + source_id_base__h15044 ; + assign source_id__h23781 = 10'd11 + source_id_base__h15044 ; + assign source_id__h23889 = 10'd10 + source_id_base__h15044 ; + assign source_id__h23997 = 10'd9 + source_id_base__h15044 ; + assign source_id__h24105 = 10'd8 + source_id_base__h15044 ; + assign source_id__h24213 = 10'd7 + source_id_base__h15044 ; + assign source_id__h24321 = 10'd6 + source_id_base__h15044 ; + assign source_id__h24429 = 10'd5 + source_id_base__h15044 ; + assign source_id__h24537 = 10'd4 + source_id_base__h15044 ; + assign source_id__h24645 = 10'd3 + source_id_base__h15044 ; + assign source_id__h24753 = 10'd2 + source_id_base__h15044 ; + assign source_id__h24861 = 10'd1 + source_id_base__h15044 ; + assign source_id__h31046 = { addr_offset__h28467[4:0], 5'd1 } ; + assign source_id__h32256 = { addr_offset__h28467[4:0], 5'd2 } ; + assign source_id__h33466 = { addr_offset__h28467[4:0], 5'd3 } ; + assign source_id__h34676 = { addr_offset__h28467[4:0], 5'd4 } ; + assign source_id__h35886 = { addr_offset__h28467[4:0], 5'd5 } ; + assign source_id__h37096 = { addr_offset__h28467[4:0], 5'd6 } ; + assign source_id__h38306 = { addr_offset__h28467[4:0], 5'd7 } ; + assign source_id__h39516 = { addr_offset__h28467[4:0], 5'd8 } ; + assign source_id__h40726 = { addr_offset__h28467[4:0], 5'd9 } ; + assign source_id__h41936 = { addr_offset__h28467[4:0], 5'd10 } ; + assign source_id__h43146 = { addr_offset__h28467[4:0], 5'd11 } ; + assign source_id__h44356 = { addr_offset__h28467[4:0], 5'd12 } ; + assign source_id__h45566 = { addr_offset__h28467[4:0], 5'd13 } ; + assign source_id__h46776 = { addr_offset__h28467[4:0], 5'd14 } ; + assign source_id__h47986 = { addr_offset__h28467[4:0], 5'd15 } ; + assign source_id__h49196 = { addr_offset__h28467[4:0], 5'd16 } ; + assign source_id__h50406 = { addr_offset__h28467[4:0], 5'd17 } ; + assign source_id__h51616 = { addr_offset__h28467[4:0], 5'd18 } ; + assign source_id__h52826 = { addr_offset__h28467[4:0], 5'd19 } ; + assign source_id__h54036 = { addr_offset__h28467[4:0], 5'd20 } ; + assign source_id__h55246 = { addr_offset__h28467[4:0], 5'd21 } ; + assign source_id__h56456 = { addr_offset__h28467[4:0], 5'd22 } ; + assign source_id__h57666 = { addr_offset__h28467[4:0], 5'd23 } ; + assign source_id__h58876 = { addr_offset__h28467[4:0], 5'd24 } ; + assign source_id__h60086 = { addr_offset__h28467[4:0], 5'd25 } ; + assign source_id__h61296 = { addr_offset__h28467[4:0], 5'd26 } ; + assign source_id__h62506 = { addr_offset__h28467[4:0], 5'd27 } ; + assign source_id__h63716 = { addr_offset__h28467[4:0], 5'd28 } ; + assign source_id__h64926 = { addr_offset__h28467[4:0], 5'd29 } ; + assign source_id__h66136 = { addr_offset__h28467[4:0], 5'd30 } ; + assign source_id__h67346 = { addr_offset__h28467[4:0], 5'd31 } ; + assign source_id__h69011 = { 5'd0, x__h69063 } ; + assign source_id_base__h15044 = { addr_offset__h14599[4:0], 5'h0 } ; + assign source_id_base__h29718 = { addr_offset__h28467[4:0], 5'h0 } ; + assign v__h14836 = { 61'd0, x__h14907 } ; + assign v__h15086 = { 32'd0, v_ip__h15089 } ; + assign v__h19560 = { 32'd0, v_ie__h19563 } ; + assign v__h25178 = { 61'd0, x__h25249 } ; + assign v__h26875 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 ? - v__h26835 : + v__h26894 : 64'd0 ; - assign v__h26835 = { 59'd0, max_id__h25318 } ; - assign v_ie__h19504 = - { source_id__h21494 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h21670 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h21778 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h21886 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h21994 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h22102 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h22210 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h22318 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h22426 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h22534 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h22642 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h22750 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h22858 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h22966 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h23074 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h23182 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h23290 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h23398 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h23506 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h23614 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h23722 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h23830 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h23938 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h24046 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h24154 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h24262 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h24370 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h24478 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h24586 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h24694 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h24802 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + assign v__h26894 = { 59'd0, max_id__h25377 } ; + assign v_ie__h19563 = + { source_id__h21553 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, + source_id__h21729 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + source_id__h21837 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + source_id__h21945 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + source_id__h22053 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + source_id__h22161 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + source_id__h22269 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + source_id__h22377 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + source_id__h22485 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + source_id__h22593 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + source_id__h22701 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + source_id__h22809 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + source_id__h22917 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + source_id__h23025 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + source_id__h23133 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + source_id__h23241 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + source_id__h23349 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + source_id__h23457 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + source_id__h23565 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + source_id__h23673 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + source_id__h23781 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + source_id__h23889 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + source_id__h23997 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + source_id__h24105 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + source_id__h24213 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + source_id__h24321 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + source_id__h24429 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + source_id__h24537 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + source_id__h24645 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + source_id__h24753 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + source_id__h24861 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h15030 = - { source_id__h17021 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; + assign v_ip__h15089 = + { source_id__h17080 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164, - source_id__h17128 <= 10'd16 && + source_id__h17187 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168, - source_id__h17201 <= 10'd16 && + source_id__h17260 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d173, - source_id__h17274 <= 10'd16 && + source_id__h17333 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d177, - source_id__h17347 <= 10'd16 && + source_id__h17406 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d182, - source_id__h17420 <= 10'd16 && + source_id__h17479 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d186, - source_id__h17493 <= 10'd16 && + source_id__h17552 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d191, - source_id__h17566 <= 10'd16 && + source_id__h17625 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d195, - source_id__h17639 <= 10'd16 && + source_id__h17698 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d200, - source_id__h17712 <= 10'd16 && + source_id__h17771 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d204, - source_id__h17785 <= 10'd16 && + source_id__h17844 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d209, - source_id__h17858 <= 10'd16 && + source_id__h17917 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d213, - source_id__h17931 <= 10'd16 && + source_id__h17990 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d218, - source_id__h18004 <= 10'd16 && + source_id__h18063 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d222, - source_id__h18077 <= 10'd16 && + source_id__h18136 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d227, - source_id__h18150 <= 10'd16 && + source_id__h18209 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d231, - source_id__h18223 <= 10'd16 && + source_id__h18282 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d236, - source_id__h18296 <= 10'd16 && + source_id__h18355 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d240, - source_id__h18369 <= 10'd16 && + source_id__h18428 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d245, - source_id__h18442 <= 10'd16 && + source_id__h18501 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d249, - source_id__h18515 <= 10'd16 && + source_id__h18574 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d254, - source_id__h18588 <= 10'd16 && + source_id__h18647 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d258, - source_id__h18661 <= 10'd16 && + source_id__h18720 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d263, - source_id__h18734 <= 10'd16 && + source_id__h18793 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d267, - source_id__h18807 <= 10'd16 && + source_id__h18866 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d272, - source_id__h18880 <= 10'd16 && + source_id__h18939 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d276, - source_id__h18953 <= 10'd16 && + source_id__h19012 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d281, - source_id__h19026 <= 10'd16 && + source_id__h19085 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d285, - source_id__h19099 <= 10'd16 && + source_id__h19158 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d290, - source_id__h19172 <= 10'd16 && + source_id__h19231 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d294, - source_id__h19245 <= 10'd16 && + source_id__h19304 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d299, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d301 } ; - assign wdata32__h28409 = - (addr_offset__h28408[2:0] == 3'd4) ? + assign wdata32__h28468 = + (addr_offset__h28467[2:0] == 3'd4) ? m_slave_xactor_shim_wff$D_OUT[72:41] : m_slave_xactor_shim_wff$D_OUT[40:9] ; - assign x__h25030 = - { addr_offset__h14540[31:16], 4'd0, addr_offset__h14540[11:0] } ; - assign x__h27766 = - (addr_offset__h14540[2:0] == 3'd4) ? - rdata___1__h27806 : - rdata__h27563 ; - assign x__h68623 = - { addr_offset__h28408[31:16], 4'd0, addr_offset__h28408[11:0] } ; - assign y_avValue_fst__h27455 = (x__h25371 == 5'd0) ? v__h26816 : 64'd0 ; - assign y_avValue_fst__h27476 = + assign x__h25089 = + { addr_offset__h14599[31:16], 4'd0, addr_offset__h14599[11:0] } ; + assign x__h27825 = + (addr_offset__h14599[2:0] == 3'd4) ? + rdata___1__h27865 : + rdata__h27622 ; + assign x__h68682 = + { addr_offset__h28467[31:16], 4'd0, addr_offset__h28467[11:0] } ; + assign y_avValue_fst__h27514 = (x__h25430 == 5'd0) ? v__h26875 : 64'd0 ; + assign y_avValue_fst__h27535 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - y_avValue_fst__h27455 : + y_avValue_fst__h27514 : 64'd0 ; - assign y_avValue_fst__h27488 = + assign y_avValue_fst__h27547 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - v__h25119 : + v__h25178 : 64'd0 ; - assign y_avValue_fst__h27504 = + assign y_avValue_fst__h27563 = (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308) ? - v__h19501 : + v__h19560 : 64'd0 ; - assign y_avValue_fst__h27520 = + assign y_avValue_fst__h27579 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 ? - v__h15027 : + v__h15086 : 64'd0 ; - assign y_avValue_fst__h27525 = + assign y_avValue_fst__h27584 = (!m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306) ? - y_avValue_fst__h27504 : - y_avValue_fst__h27509 ; - assign y_avValue_fst__h27536 = - (addr_offset__h14540[11:2] != 10'd0 && + y_avValue_fst__h27563 : + y_avValue_fst__h27568 ; + assign y_avValue_fst__h27595 = + (addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106) ? - v__h14777 : + v__h14836 : 64'd0 ; - assign y_avValue_fst__h27541 = + assign y_avValue_fst__h27600 = (!m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134) ? - y_avValue_fst__h27520 : - y_avValue_fst__h27525 ; - assign y_avValue_fst__h27555 = + y_avValue_fst__h27579 : + y_avValue_fst__h27584 ; + assign y_avValue_fst__h27614 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - y_avValue_fst__h27536 : - y_avValue_fst__h27541 ; - always@(addr_offset__h14540 or + y_avValue_fst__h27595 : + y_avValue_fst__h27600 ; + always@(addr_offset__h14599 or m_vrg_source_prio_0 or m_vrg_source_prio_1 or m_vrg_source_prio_2 or @@ -16968,55 +16973,55 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_prio_14 or m_vrg_source_prio_15 or m_vrg_source_prio_16) begin - case (addr_offset__h14540[11:2]) - 10'd0: x__h14848 = m_vrg_source_prio_0; - 10'd1: x__h14848 = m_vrg_source_prio_1; - 10'd2: x__h14848 = m_vrg_source_prio_2; - 10'd3: x__h14848 = m_vrg_source_prio_3; - 10'd4: x__h14848 = m_vrg_source_prio_4; - 10'd5: x__h14848 = m_vrg_source_prio_5; - 10'd6: x__h14848 = m_vrg_source_prio_6; - 10'd7: x__h14848 = m_vrg_source_prio_7; - 10'd8: x__h14848 = m_vrg_source_prio_8; - 10'd9: x__h14848 = m_vrg_source_prio_9; - 10'd10: x__h14848 = m_vrg_source_prio_10; - 10'd11: x__h14848 = m_vrg_source_prio_11; - 10'd12: x__h14848 = m_vrg_source_prio_12; - 10'd13: x__h14848 = m_vrg_source_prio_13; - 10'd14: x__h14848 = m_vrg_source_prio_14; - 10'd15: x__h14848 = m_vrg_source_prio_15; - 10'd16: x__h14848 = m_vrg_source_prio_16; - default: x__h14848 = 3'b010 /* unspecified value */ ; + case (addr_offset__h14599[11:2]) + 10'd0: x__h14907 = m_vrg_source_prio_0; + 10'd1: x__h14907 = m_vrg_source_prio_1; + 10'd2: x__h14907 = m_vrg_source_prio_2; + 10'd3: x__h14907 = m_vrg_source_prio_3; + 10'd4: x__h14907 = m_vrg_source_prio_4; + 10'd5: x__h14907 = m_vrg_source_prio_5; + 10'd6: x__h14907 = m_vrg_source_prio_6; + 10'd7: x__h14907 = m_vrg_source_prio_7; + 10'd8: x__h14907 = m_vrg_source_prio_8; + 10'd9: x__h14907 = m_vrg_source_prio_9; + 10'd10: x__h14907 = m_vrg_source_prio_10; + 10'd11: x__h14907 = m_vrg_source_prio_11; + 10'd12: x__h14907 = m_vrg_source_prio_12; + 10'd13: x__h14907 = m_vrg_source_prio_13; + 10'd14: x__h14907 = m_vrg_source_prio_14; + 10'd15: x__h14907 = m_vrg_source_prio_15; + 10'd16: x__h14907 = m_vrg_source_prio_16; + default: x__h14907 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or m_vrg_target_threshold_0 or m_vrg_target_threshold_1) begin - case (addr_offset__h14540[16:12]) - 5'd0: x__h25190 = m_vrg_target_threshold_0; - 5'd1: x__h25190 = m_vrg_target_threshold_1; - default: x__h25190 = 3'b010 /* unspecified value */ ; + case (addr_offset__h14599[16:12]) + 5'd0: x__h25249 = m_vrg_target_threshold_0; + 5'd1: x__h25249 = m_vrg_target_threshold_1; + default: x__h25249 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h14540[16:12]) - 5'd0: x__h25371 = m_vrg_servicing_source_0; - 5'd1: x__h25371 = m_vrg_servicing_source_1; - default: x__h25371 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h14599[16:12]) + 5'd0: x__h25430 = m_vrg_servicing_source_0; + 5'd1: x__h25430 = m_vrg_servicing_source_1; + default: x__h25430 = 5'b01010 /* unspecified value */ ; endcase end - always@(addr_offset__h28408 or + always@(addr_offset__h28467 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h28408[16:12]) - 5'd0: x__h69004 = m_vrg_servicing_source_0; - 5'd1: x__h69004 = m_vrg_servicing_source_1; - default: x__h69004 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h28467[16:12]) + 5'd0: x__h69063 = m_vrg_servicing_source_0; + 5'd1: x__h69063 = m_vrg_servicing_source_1; + default: x__h69063 = 5'b01010 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17033,7 +17038,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d301 = m_vrg_source_ip_0; @@ -17089,7 +17094,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21670 or + always@(source_id__h21729 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17106,7 +17111,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21670) + case (source_id__h21729) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362 = m_vvrg_ie_0_0; @@ -17162,7 +17167,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21670 or + always@(source_id__h21729 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17179,7 +17184,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21670) + case (source_id__h21729) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363 = m_vvrg_ie_1_0; @@ -17235,7 +17240,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21494 or + always@(source_id__h21553 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17252,7 +17257,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21494) + case (source_id__h21553) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337 = m_vvrg_ie_0_0; @@ -17308,7 +17313,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21494 or + always@(source_id__h21553 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17325,7 +17330,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21494) + case (source_id__h21553) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356 = m_vvrg_ie_1_0; @@ -17381,7 +17386,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21778 or + always@(source_id__h21837 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17398,7 +17403,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21778) + case (source_id__h21837) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370 = m_vvrg_ie_0_0; @@ -17454,7 +17459,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17021 or + always@(source_id__h17080 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17471,7 +17476,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17021) + case (source_id__h17080) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164 = m_vrg_source_ip_0; @@ -17527,7 +17532,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21778 or + always@(source_id__h21837 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17544,7 +17549,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21778) + case (source_id__h21837) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371 = m_vvrg_ie_1_0; @@ -17600,7 +17605,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21886 or + always@(source_id__h21945 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17617,7 +17622,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21886) + case (source_id__h21945) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378 = m_vvrg_ie_1_0; @@ -17673,7 +17678,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21886 or + always@(source_id__h21945 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17690,7 +17695,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21886) + case (source_id__h21945) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377 = m_vvrg_ie_0_0; @@ -17746,7 +17751,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17128 or + always@(source_id__h17187 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17763,7 +17768,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17128) + case (source_id__h17187) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168 = m_vrg_source_ip_0; @@ -17819,7 +17824,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21994 or + always@(source_id__h22053 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17836,7 +17841,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21994) + case (source_id__h22053) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385 = m_vvrg_ie_0_0; @@ -17892,7 +17897,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21994 or + always@(source_id__h22053 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17909,7 +17914,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21994) + case (source_id__h22053) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386 = m_vvrg_ie_1_0; @@ -17965,7 +17970,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17201 or + always@(source_id__h17260 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17982,7 +17987,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17201) + case (source_id__h17260) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d173 = m_vrg_source_ip_0; @@ -18038,7 +18043,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22102 or + always@(source_id__h22161 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18055,7 +18060,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22102) + case (source_id__h22161) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392 = m_vvrg_ie_0_0; @@ -18111,7 +18116,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22102 or + always@(source_id__h22161 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18128,7 +18133,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22102) + case (source_id__h22161) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393 = m_vvrg_ie_1_0; @@ -18184,7 +18189,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17274 or + always@(source_id__h17333 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18201,7 +18206,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17274) + case (source_id__h17333) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d177 = m_vrg_source_ip_0; @@ -18257,7 +18262,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22210 or + always@(source_id__h22269 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18274,7 +18279,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22210) + case (source_id__h22269) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400 = m_vvrg_ie_0_0; @@ -18330,7 +18335,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22210 or + always@(source_id__h22269 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18347,7 +18352,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22210) + case (source_id__h22269) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401 = m_vvrg_ie_1_0; @@ -18403,7 +18408,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22318 or + always@(source_id__h22377 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18420,7 +18425,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22318) + case (source_id__h22377) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407 = m_vvrg_ie_0_0; @@ -18476,7 +18481,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17347 or + always@(source_id__h17406 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18493,7 +18498,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17347) + case (source_id__h17406) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d182 = m_vrg_source_ip_0; @@ -18549,7 +18554,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22318 or + always@(source_id__h22377 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18566,7 +18571,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22318) + case (source_id__h22377) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408 = m_vvrg_ie_1_0; @@ -18622,7 +18627,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17420 or + always@(source_id__h17479 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18639,7 +18644,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17420) + case (source_id__h17479) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d186 = m_vrg_source_ip_0; @@ -18695,7 +18700,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22426 or + always@(source_id__h22485 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18712,7 +18717,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22426) + case (source_id__h22485) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415 = m_vvrg_ie_0_0; @@ -18768,7 +18773,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22426 or + always@(source_id__h22485 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18785,7 +18790,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22426) + case (source_id__h22485) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416 = m_vvrg_ie_1_0; @@ -18841,7 +18846,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22534 or + always@(source_id__h22593 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18858,7 +18863,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22534) + case (source_id__h22593) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422 = m_vvrg_ie_0_0; @@ -18914,7 +18919,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17493 or + always@(source_id__h17552 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18931,7 +18936,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17493) + case (source_id__h17552) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d191 = m_vrg_source_ip_0; @@ -18987,7 +18992,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22534 or + always@(source_id__h22593 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19004,7 +19009,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22534) + case (source_id__h22593) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423 = m_vvrg_ie_1_0; @@ -19060,7 +19065,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17566 or + always@(source_id__h17625 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19077,7 +19082,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17566) + case (source_id__h17625) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d195 = m_vrg_source_ip_0; @@ -19133,7 +19138,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22642 or + always@(source_id__h22701 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19150,7 +19155,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22642) + case (source_id__h22701) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431 = m_vvrg_ie_1_0; @@ -19206,7 +19211,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22642 or + always@(source_id__h22701 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19223,7 +19228,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22642) + case (source_id__h22701) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430 = m_vvrg_ie_0_0; @@ -19279,7 +19284,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22750 or + always@(source_id__h22809 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19296,7 +19301,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22750) + case (source_id__h22809) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437 = m_vvrg_ie_0_0; @@ -19352,7 +19357,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17639 or + always@(source_id__h17698 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19369,7 +19374,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17639) + case (source_id__h17698) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d200 = m_vrg_source_ip_0; @@ -19425,7 +19430,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22750 or + always@(source_id__h22809 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19442,7 +19447,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22750) + case (source_id__h22809) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438 = m_vvrg_ie_1_0; @@ -19498,7 +19503,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17712 or + always@(source_id__h17771 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19515,7 +19520,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17712) + case (source_id__h17771) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d204 = m_vrg_source_ip_0; @@ -19571,7 +19576,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22858 or + always@(source_id__h22917 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19588,7 +19593,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22858) + case (source_id__h22917) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445 = m_vvrg_ie_0_0; @@ -19644,7 +19649,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22858 or + always@(source_id__h22917 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19661,7 +19666,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22858) + case (source_id__h22917) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446 = m_vvrg_ie_1_0; @@ -19717,7 +19722,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17785 or + always@(source_id__h17844 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19734,7 +19739,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17785) + case (source_id__h17844) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d209 = m_vrg_source_ip_0; @@ -19790,7 +19795,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22966 or + always@(source_id__h23025 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19807,7 +19812,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22966) + case (source_id__h23025) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452 = m_vvrg_ie_0_0; @@ -19863,7 +19868,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22966 or + always@(source_id__h23025 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19880,7 +19885,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22966) + case (source_id__h23025) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453 = m_vvrg_ie_1_0; @@ -19936,7 +19941,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18442 or + always@(source_id__h18501 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19953,7 +19958,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18442) + case (source_id__h18501) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d249 = m_vrg_source_ip_0; @@ -20009,7 +20014,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17858 or + always@(source_id__h17917 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20026,7 +20031,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17858) + case (source_id__h17917) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d213 = m_vrg_source_ip_0; @@ -20082,7 +20087,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23074 or + always@(source_id__h23133 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20099,7 +20104,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23074) + case (source_id__h23133) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460 = m_vvrg_ie_0_0; @@ -20155,7 +20160,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23074 or + always@(source_id__h23133 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20172,7 +20177,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23074) + case (source_id__h23133) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461 = m_vvrg_ie_1_0; @@ -20228,7 +20233,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23182 or + always@(source_id__h23241 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20245,7 +20250,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23182) + case (source_id__h23241) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467 = m_vvrg_ie_0_0; @@ -20301,7 +20306,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17931 or + always@(source_id__h17990 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20318,7 +20323,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17931) + case (source_id__h17990) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d218 = m_vrg_source_ip_0; @@ -20374,7 +20379,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23182 or + always@(source_id__h23241 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20391,7 +20396,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23182) + case (source_id__h23241) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468 = m_vvrg_ie_1_0; @@ -20447,7 +20452,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18004 or + always@(source_id__h18063 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20464,7 +20469,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18004) + case (source_id__h18063) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d222 = m_vrg_source_ip_0; @@ -20520,7 +20525,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23290 or + always@(source_id__h23349 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20537,7 +20542,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23290) + case (source_id__h23349) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475 = m_vvrg_ie_0_0; @@ -20593,7 +20598,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23290 or + always@(source_id__h23349 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20610,7 +20615,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23290) + case (source_id__h23349) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476 = m_vvrg_ie_1_0; @@ -20666,7 +20671,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23398 or + always@(source_id__h23457 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20683,7 +20688,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23398) + case (source_id__h23457) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482 = m_vvrg_ie_0_0; @@ -20739,7 +20744,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18077 or + always@(source_id__h18136 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20756,7 +20761,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18077) + case (source_id__h18136) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d227 = m_vrg_source_ip_0; @@ -20812,7 +20817,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23398 or + always@(source_id__h23457 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20829,7 +20834,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23398) + case (source_id__h23457) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483 = m_vvrg_ie_1_0; @@ -20885,7 +20890,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18150 or + always@(source_id__h18209 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20902,7 +20907,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18150) + case (source_id__h18209) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d231 = m_vrg_source_ip_0; @@ -20958,7 +20963,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23506 or + always@(source_id__h23565 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20975,7 +20980,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23506) + case (source_id__h23565) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491 = m_vvrg_ie_1_0; @@ -21031,7 +21036,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23506 or + always@(source_id__h23565 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21048,7 +21053,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23506) + case (source_id__h23565) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490 = m_vvrg_ie_0_0; @@ -21104,7 +21109,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23614 or + always@(source_id__h23673 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21121,7 +21126,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23614) + case (source_id__h23673) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497 = m_vvrg_ie_0_0; @@ -21177,7 +21182,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18223 or + always@(source_id__h18282 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21194,7 +21199,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18223) + case (source_id__h18282) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d236 = m_vrg_source_ip_0; @@ -21250,7 +21255,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23614 or + always@(source_id__h23673 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21267,7 +21272,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23614) + case (source_id__h23673) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498 = m_vvrg_ie_1_0; @@ -21323,7 +21328,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18296 or + always@(source_id__h18355 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21340,7 +21345,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18296) + case (source_id__h18355) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d240 = m_vrg_source_ip_0; @@ -21396,7 +21401,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23722 or + always@(source_id__h23781 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21413,7 +21418,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23722) + case (source_id__h23781) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505 = m_vvrg_ie_0_0; @@ -21469,7 +21474,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23722 or + always@(source_id__h23781 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21486,7 +21491,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23722) + case (source_id__h23781) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506 = m_vvrg_ie_1_0; @@ -21542,7 +21547,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23830 or + always@(source_id__h23889 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21559,7 +21564,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23830) + case (source_id__h23889) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512 = m_vvrg_ie_0_0; @@ -21615,7 +21620,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18369 or + always@(source_id__h18428 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21632,7 +21637,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18369) + case (source_id__h18428) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d245 = m_vrg_source_ip_0; @@ -21688,7 +21693,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23830 or + always@(source_id__h23889 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21705,7 +21710,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23830) + case (source_id__h23889) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513 = m_vvrg_ie_1_0; @@ -21761,7 +21766,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23938 or + always@(source_id__h23997 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21778,7 +21783,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23938) + case (source_id__h23997) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520 = m_vvrg_ie_0_0; @@ -21834,7 +21839,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23938 or + always@(source_id__h23997 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21851,7 +21856,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23938) + case (source_id__h23997) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521 = m_vvrg_ie_1_0; @@ -21907,7 +21912,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24046 or + always@(source_id__h24105 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21924,7 +21929,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24046) + case (source_id__h24105) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527 = m_vvrg_ie_0_0; @@ -21980,7 +21985,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24046 or + always@(source_id__h24105 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21997,7 +22002,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24046) + case (source_id__h24105) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528 = m_vvrg_ie_1_0; @@ -22053,7 +22058,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18588 or + always@(source_id__h18647 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22070,7 +22075,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18588) + case (source_id__h18647) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d258 = m_vrg_source_ip_0; @@ -22126,7 +22131,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18515 or + always@(source_id__h18574 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22143,7 +22148,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18515) + case (source_id__h18574) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d254 = m_vrg_source_ip_0; @@ -22199,7 +22204,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24154 or + always@(source_id__h24213 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22216,7 +22221,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24154) + case (source_id__h24213) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535 = m_vvrg_ie_0_0; @@ -22272,7 +22277,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24154 or + always@(source_id__h24213 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22289,7 +22294,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24154) + case (source_id__h24213) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536 = m_vvrg_ie_1_0; @@ -22345,7 +22350,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24262 or + always@(source_id__h24321 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22362,7 +22367,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24262) + case (source_id__h24321) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542 = m_vvrg_ie_0_0; @@ -22418,7 +22423,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24262 or + always@(source_id__h24321 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22435,7 +22440,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24262) + case (source_id__h24321) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543 = m_vvrg_ie_1_0; @@ -22491,7 +22496,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18734 or + always@(source_id__h18793 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22508,7 +22513,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18734) + case (source_id__h18793) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d267 = m_vrg_source_ip_0; @@ -22564,7 +22569,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18661 or + always@(source_id__h18720 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22581,7 +22586,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18661) + case (source_id__h18720) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d263 = m_vrg_source_ip_0; @@ -22637,7 +22642,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24370 or + always@(source_id__h24429 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22654,7 +22659,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24370) + case (source_id__h24429) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550 = m_vvrg_ie_0_0; @@ -22710,7 +22715,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24478 or + always@(source_id__h24537 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22727,7 +22732,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24478) + case (source_id__h24537) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557 = m_vvrg_ie_0_0; @@ -22783,7 +22788,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24370 or + always@(source_id__h24429 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22800,7 +22805,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24370) + case (source_id__h24429) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551 = m_vvrg_ie_1_0; @@ -22856,7 +22861,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24478 or + always@(source_id__h24537 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22873,7 +22878,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24478) + case (source_id__h24537) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558 = m_vvrg_ie_1_0; @@ -22929,7 +22934,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18880 or + always@(source_id__h18939 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22946,7 +22951,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18880) + case (source_id__h18939) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d276 = m_vrg_source_ip_0; @@ -23002,7 +23007,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18807 or + always@(source_id__h18866 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23019,7 +23024,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18807) + case (source_id__h18866) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d272 = m_vrg_source_ip_0; @@ -23075,7 +23080,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24586 or + always@(source_id__h24645 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23092,7 +23097,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24586) + case (source_id__h24645) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565 = m_vvrg_ie_0_0; @@ -23148,7 +23153,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24586 or + always@(source_id__h24645 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23165,7 +23170,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24586) + case (source_id__h24645) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566 = m_vvrg_ie_1_0; @@ -23221,7 +23226,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24694 or + always@(source_id__h24753 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23238,7 +23243,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24694) + case (source_id__h24753) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572 = m_vvrg_ie_0_0; @@ -23294,7 +23299,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24694 or + always@(source_id__h24753 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23311,7 +23316,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24694) + case (source_id__h24753) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573 = m_vvrg_ie_1_0; @@ -23367,7 +23372,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18953 or + always@(source_id__h19012 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23384,7 +23389,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18953) + case (source_id__h19012) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d281 = m_vrg_source_ip_0; @@ -23440,7 +23445,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19026 or + always@(source_id__h19085 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23457,7 +23462,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19026) + case (source_id__h19085) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d285 = m_vrg_source_ip_0; @@ -23513,7 +23518,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24802 or + always@(source_id__h24861 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23530,7 +23535,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24802) + case (source_id__h24861) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580 = m_vvrg_ie_0_0; @@ -23586,7 +23591,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24802 or + always@(source_id__h24861 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23603,7 +23608,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24802) + case (source_id__h24861) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581 = m_vvrg_ie_1_0; @@ -23659,7 +23664,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23676,7 +23681,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585 = m_vvrg_ie_0_0; @@ -23732,7 +23737,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23749,7 +23754,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586 = m_vvrg_ie_1_0; @@ -23805,487 +23810,487 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19172 or + always@(source_id__h19231 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24302,7 +24307,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19172) + case (source_id__h19231) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d294 = m_vrg_source_ip_0; @@ -24358,7 +24363,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19099 or + always@(source_id__h19158 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24375,7 +24380,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19099) + case (source_id__h19158) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d290 = m_vrg_source_ip_0; @@ -24431,7 +24436,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19245 or + always@(source_id__h19304 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24448,7 +24453,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19245) + case (source_id__h19304) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d299 = m_vrg_source_ip_0; @@ -24504,223 +24509,223 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) + always@(addr_offset__h14599 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = m_vvrg_ie_0_1; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = m_vvrg_ie_1_1; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) + always@(addr_offset__h14599 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_0_2; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_1_2; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) + always@(addr_offset__h14599 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_0_3; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_1_3; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) + always@(addr_offset__h14599 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_0_4; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_1_4; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) + always@(addr_offset__h14599 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_0_5; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_1_5; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) + always@(addr_offset__h14599 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_0_6; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_1_6; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) + always@(addr_offset__h14599 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_0_7; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_1_7; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) + always@(addr_offset__h14599 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_0_8; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_1_8; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) + always@(addr_offset__h14599 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_0_9; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_1_9; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) + always@(addr_offset__h14599 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_0_10; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_1_10; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) + always@(addr_offset__h14599 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_0_11; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_1_11; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) + always@(addr_offset__h14599 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_0_12; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_1_12; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) + always@(addr_offset__h14599 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_0_13; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_1_13; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) + always@(addr_offset__h14599 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_0_14; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_1_14; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) + always@(addr_offset__h14599 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_0_15; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_1_15; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) + always@(addr_offset__h14599 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_0_16; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_1_16; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h25030 or y_avValue_fst__h27488 or y_avValue_fst__h27476) + always@(x__h25089 or y_avValue_fst__h27547 or y_avValue_fst__h27535) begin - case (x__h25030) - 32'h00200000: y_avValue_fst__h27509 = y_avValue_fst__h27488; - 32'h00200004: y_avValue_fst__h27509 = y_avValue_fst__h27476; - default: y_avValue_fst__h27509 = 64'd0; + case (x__h25089) + 32'h00200000: y_avValue_fst__h27568 = y_avValue_fst__h27547; + 32'h00200004: y_avValue_fst__h27568 = y_avValue_fst__h27535; + default: y_avValue_fst__h27568 = 64'd0; endcase end - always@(source_id__h68952 or + always@(source_id__h69011 or m_vrg_source_busy_0 or m_vrg_source_busy_1 or m_vrg_source_busy_2 or @@ -24738,7 +24743,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_busy_14 or m_vrg_source_busy_15 or m_vrg_source_busy_16) begin - case (source_id__h68952) + case (source_id__h69011) 10'd0: SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 = m_vrg_source_busy_0; @@ -24794,42 +24799,42 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h25030 or + always@(x__h25089 or m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 or - x__h25371) + x__h25430) begin - case (x__h25030) + case (x__h25089) 32'h00200000: - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? 2'd0 : 2'd2; 32'h00200004: - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - ((x__h25371 == 5'd0) ? 2'd0 : 2'd2) : + ((x__h25430 == 5'd0) ? 2'd0 : 2'd2) : 2'd2; - default: CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = 2'd2; + default: CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = 2'd2; endcase end - always@(x__h68623 or + always@(x__h68682 or m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 or SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) begin - case (x__h68623) + case (x__h68682) 32'h00200000: - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ? 2'd0 : 2'd2; 32'h00200004: - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ? (SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ? 2'd0 : 2'd2) : 2'd2; - default: CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = 2'd2; + default: CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = 2'd2; endcase end @@ -25421,9 +25426,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h72910, + a__h72969, m_vrg_target_threshold_0, - b__h72911, + b__h72970, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25464,249 +25469,249 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h74915, + a__h74974, m_vrg_target_threshold_1, - b__h74916, + b__h74975, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368) + if (NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371) begin - v__h77333 = $stime; + v__h77354 = $stime; #0; end - v__h77327 = v__h77333 / 32'd10; + v__h77348 = v__h77354 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368) + if (NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77327, + v__h77348, $signed(32'd1), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375) + if (NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378) begin - v__h77531 = $stime; + v__h77552 = $stime; #0; end - v__h77525 = v__h77531 / 32'd10; + v__h77546 = v__h77552 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375) + if (NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77525, + v__h77546, $signed(32'd2), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383) + if (NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386) begin - v__h77729 = $stime; + v__h77750 = $stime; #0; end - v__h77723 = v__h77729 / 32'd10; + v__h77744 = v__h77750 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383) + if (NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77723, + v__h77744, $signed(32'd3), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391) + if (NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394) begin - v__h77927 = $stime; + v__h77948 = $stime; #0; end - v__h77921 = v__h77927 / 32'd10; + v__h77942 = v__h77948 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391) + if (NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77921, + v__h77942, $signed(32'd4), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399) + if (NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402) begin - v__h78125 = $stime; + v__h78146 = $stime; #0; end - v__h78119 = v__h78125 / 32'd10; + v__h78140 = v__h78146 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399) + if (NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78119, + v__h78140, $signed(32'd5), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407) + if (NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410) begin - v__h78323 = $stime; + v__h78344 = $stime; #0; end - v__h78317 = v__h78323 / 32'd10; + v__h78338 = v__h78344 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407) + if (NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78317, + v__h78338, $signed(32'd6), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415) + if (NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418) begin - v__h78521 = $stime; + v__h78542 = $stime; #0; end - v__h78515 = v__h78521 / 32'd10; + v__h78536 = v__h78542 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415) + if (NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78515, + v__h78536, $signed(32'd7), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423) + if (NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426) begin - v__h78719 = $stime; + v__h78740 = $stime; #0; end - v__h78713 = v__h78719 / 32'd10; + v__h78734 = v__h78740 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423) + if (NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78713, + v__h78734, $signed(32'd8), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431) + if (NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434) begin - v__h78917 = $stime; + v__h78938 = $stime; #0; end - v__h78911 = v__h78917 / 32'd10; + v__h78932 = v__h78938 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431) + if (NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78911, + v__h78932, $signed(32'd9), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439) + if (NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442) begin - v__h79115 = $stime; + v__h79136 = $stime; #0; end - v__h79109 = v__h79115 / 32'd10; + v__h79130 = v__h79136 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439) + if (NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79109, + v__h79130, $signed(32'd10), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447) + if (NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450) begin - v__h79313 = $stime; + v__h79334 = $stime; #0; end - v__h79307 = v__h79313 / 32'd10; + v__h79328 = v__h79334 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447) + if (NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79307, + v__h79328, $signed(32'd11), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455) + if (NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458) begin - v__h79511 = $stime; + v__h79532 = $stime; #0; end - v__h79505 = v__h79511 / 32'd10; + v__h79526 = v__h79532 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455) + if (NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79505, + v__h79526, $signed(32'd12), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463) + if (NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466) begin - v__h79709 = $stime; + v__h79730 = $stime; #0; end - v__h79703 = v__h79709 / 32'd10; + v__h79724 = v__h79730 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463) + if (NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79703, + v__h79724, $signed(32'd13), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471) + if (NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474) begin - v__h79907 = $stime; + v__h79928 = $stime; #0; end - v__h79901 = v__h79907 / 32'd10; + v__h79922 = v__h79928 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471) + if (NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79901, + v__h79922, $signed(32'd14), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479) + if (NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482) begin - v__h80105 = $stime; + v__h80126 = $stime; #0; end - v__h80099 = v__h80105 / 32'd10; + v__h80120 = v__h80126 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479) + if (NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h80099, + v__h80120, $signed(32'd15), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487) + if (NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490) begin - v__h80303 = $stime; + v__h80324 = $stime; #0; end - v__h80297 = v__h80303 / 32'd10; + v__h80318 = v__h80324 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487) + if (NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h80297, + v__h80318, $signed(32'd16), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) begin - v__h7530 = $stime; + v__h7589 = $stime; #0; end - v__h7524 = v__h7530 / 32'd10; + v__h7583 = v__h7589 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h7524); + $display("%0d: PLIC.rl_reset", v__h7583); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h28194 = $stime; + v__h28253 = $stime; #0; end - v__h28188 = v__h28194 / 32'd10; + v__h28247 = v__h28253 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_wr_req", v__h28188); + $display("%0d: PLIC.rl_process_wr_req", v__h28247); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -25881,15 +25886,15 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) begin - v__h28448 = $stime; + v__h28507 = $stime; #0; end - v__h28442 = v__h28448 / 32'd10; + v__h28501 = v__h28507 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h28442); + v__h28501); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) @@ -26065,101 +26070,101 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005) begin - v__h29372 = $stime; + v__h29431 = $stime; #0; end - v__h29366 = v__h29372 / 32'd10; + v__h29425 = v__h29431 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h29366, - addr_offset__h28408[11:2], - wdata32__h28409); + v__h29425, + addr_offset__h28467[11:2], + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016) begin - v__h29558 = $stime; + v__h29617 = $stime; #0; end - v__h29552 = v__h29558 / 32'd10; + v__h29611 = v__h29617 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h29552, - source_id_base__h29659); + v__h29611, + source_id_base__h29718); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980) begin - v__h68542 = $stime; + v__h68601 = $stime; #0; end - v__h68536 = v__h68542 / 32'd10; + v__h68595 = v__h68601 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h68536, - addr_offset__h28408[11:7], - source_id_base__h29659, - wdata32__h28409); + v__h68595, + addr_offset__h28467[11:7], + source_id_base__h29718, + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004) begin - v__h68832 = $stime; + v__h68891 = $stime; #0; end - v__h68826 = v__h68832 / 32'd10; + v__h68885 = v__h68891 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h68826, - addr_offset__h28408[16:12], - wdata32__h28409); + v__h68885, + addr_offset__h28467[16:12], + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076) begin - v__h69364 = $stime; + v__h69423 = $stime; #0; end - v__h69358 = v__h69364 / 32'd10; + v__h69417 = v__h69423 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h69358, - addr_offset__h28408[16:12], - source_id__h68952); + v__h69417, + addr_offset__h28467[16:12], + source_id__h69011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) begin - v__h69450 = $stime; + v__h69509 = $stime; #0; end - v__h69444 = v__h69450 / 32'd10; + v__h69503 = v__h69509 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h69444); + v__h69503); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) $display(" Completion message from target %0d to source %0d", - addr_offset__h28408[16:12], - source_id__h68952); + addr_offset__h28467[16:12], + source_id__h69011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) @@ -26169,16 +26174,16 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101)) begin - v__h69661 = $stime; + v__h69720 = $stime; #0; end - v__h69655 = v__h69661 / 32'd10; + v__h69714 = v__h69720 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h69655); + v__h69714); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || @@ -26393,14 +26398,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h69907 = $stime; + v__h69966 = $stime; #0; end - v__h69901 = v__h69907 / 32'd10; + v__h69960 = v__h69966 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h69901); + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h69960); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -26620,23 +26625,23 @@ module mkPLIC_16_2_7(CLK, NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h14375 = $stime; + v__h14434 = $stime; #0; end - v__h14369 = v__h14375 / 32'd10; + v__h14428 = v__h14434 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_rd_req:", v__h14369); + $display("%0d: PLIC.rl_process_rd_req:", v__h14428); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -26765,15 +26770,15 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) begin - v__h14590 = $stime; + v__h14649 = $stime; #0; end - v__h14584 = v__h14590 / 32'd10; + v__h14643 = v__h14649 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h14584); + v__h14643); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) @@ -26903,107 +26908,107 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109) begin - v__h14818 = $stime; + v__h14877 = $stime; #0; end - v__h14812 = v__h14818 / 32'd10; + v__h14871 = v__h14877 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109) $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h14812, - addr_offset__h14540[11:2], - v__h14777); + v__h14871, + addr_offset__h14599[11:2], + v__h14836); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d140) begin - v__h15069 = $stime; + v__h15128 = $stime; #0; end - v__h15063 = v__h15069 / 32'd10; + v__h15122 = v__h15128 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d140) $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h15063, - source_id_base__h14985, - v__h15027); + v__h15122, + source_id_base__h15044, + v__h15086); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d314) begin - v__h19543 = $stime; + v__h19602 = $stime; #0; end - v__h19537 = v__h19543 / 32'd10; + v__h19596 = v__h19602 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d314) $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h19537, - source_id_base__h14985, - v__h19501); + v__h19596, + source_id_base__h15044, + v__h19560); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d604) begin - v__h25160 = $stime; + v__h25219 = $stime; #0; end - v__h25154 = v__h25160 / 32'd10; + v__h25213 = v__h25219 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d604) $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h25154, - addr_offset__h14540[16:12], - v__h25119); + v__h25213, + addr_offset__h14599[16:12], + v__h25178); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810) begin - v__h27336 = $stime; + v__h27395 = $stime; #0; end - v__h27330 = v__h27336 / 32'd10; + v__h27389 = v__h27395 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810) $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h27330, - addr_offset__h14540[16:12], - v__h26835); + v__h27389, + addr_offset__h14599[16:12], + v__h26894); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) begin - v__h25416 = $stime; + v__h25475 = $stime; #0; end - v__h25410 = v__h25416 / 32'd10; + v__h25469 = v__h25475 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h25410, - addr_offset__h14540[16:12]); + v__h25469, + addr_offset__h14599[16:12]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) - $display(" Still servicing interrupt from source %0d", x__h25371); + $display(" Still servicing interrupt from source %0d", x__h25430); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) $display(" Trying to claim service for source %0d", - max_id__h25318); + max_id__h25377); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) @@ -27013,16 +27018,16 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837)) begin - v__h27627 = $stime; + v__h27686 = $stime; #0; end - v__h27621 = v__h27627 / 32'd10; + v__h27680 = v__h27686 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837)) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h27621); + v__h27680); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || @@ -27180,14 +27185,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h27865 = $stime; + v__h27924 = $stime; #0; end - v__h27859 = v__h27865 / 32'd10; + v__h27918 = v__h27924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_rd_req", v__h27859); + $display("%0d: PLIC.rl_process_rd_req", v__h27918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -27331,7 +27336,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $write("'h%h", x__h27766); + $write("'h%h", x__h27825); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -27379,38 +27384,38 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h76288 = $stime; + v__h76347 = $stime; #0; end - v__h76282 = v__h76288 / 32'd10; + v__h76341 = v__h76347 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h76282, + v__h76341, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h76398 = $stime; + v__h76457 = $stime; #0; end - v__h76392 = v__h76398 / 32'd10; + v__h76451 = v__h76457 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h76392, + v__h76451, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h76511 = $stime; + v__h76570 = $stime; #0; end - v__h76505 = v__h76511 / 32'd10; + v__h76564 = v__h76570 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h76505, + v__h76564, set_addr_map_addr_base, set_addr_map_addr_lim); end diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v index af6ea1f..05a0e23 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:05 BST 2020 +// On Wed Jun 24 20:09:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index 43b725d..e557c2c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:33:52 BST 2020 +// On Wed Jun 24 20:22:50 BST 2020 // // // Ports: @@ -36,35 +36,22 @@ // master0_arregion O 4 // master0_arvalid O 1 // master0_rready O 1 -// master1_awid O 4 -// master1_awaddr O 64 -// master1_awlen O 8 -// master1_awsize O 3 -// master1_awburst O 2 -// master1_awlock O 1 -// master1_awcache O 4 -// master1_awprot O 3 -// master1_awqos O 4 -// master1_awregion O 4 -// master1_awvalid O 1 -// master1_wdata O 64 -// master1_wstrb O 8 -// master1_wlast O 1 -// master1_wuser O 1 -// master1_wvalid O 1 -// master1_bready O 1 -// master1_arid O 4 -// master1_araddr O 64 -// master1_arlen O 8 -// master1_arsize O 3 -// master1_arburst O 2 -// master1_arlock O 1 -// master1_arcache O 4 -// master1_arprot O 3 -// master1_arqos O 4 -// master1_arregion O 4 -// master1_arvalid O 1 -// master1_rready O 1 +// master1_aw_canPeek O 1 reg +// master1_aw_peek O 97 reg +// RDY_master1_aw_peek O 1 reg +// RDY_master1_aw_drop O 1 reg +// master1_w_canPeek O 1 reg +// master1_w_peek O 74 reg +// RDY_master1_w_peek O 1 reg +// RDY_master1_w_drop O 1 reg +// master1_b_canPut O 1 reg +// RDY_master1_b_put O 1 reg +// master1_ar_canPeek O 1 reg +// master1_ar_peek O 97 reg +// RDY_master1_ar_peek O 1 reg +// RDY_master1_ar_drop O 1 reg +// master1_r_canPut O 1 reg +// RDY_master1_r_put O 1 reg // RDY_set_verbosity O 1 const // debug_module_mem_server_awready O 1 // debug_module_mem_server_wready O 1 @@ -99,28 +86,23 @@ // start_fromhostAddr I 64 reg // master0_awready I 1 // master0_wready I 1 +// master0_bvalid I 1 // master0_bid I 5 // master0_bresp I 2 // master0_arready I 1 +// master0_rvalid I 1 // master0_rid I 5 // master0_rdata I 64 // master0_rresp I 2 // master0_rlast I 1 // master0_ruser I 1 -// master1_awready I 1 -// master1_wready I 1 -// master1_bid I 4 -// master1_bresp I 2 -// master1_arready I 1 -// master1_rid I 4 -// master1_rdata I 64 -// master1_rresp I 2 -// master1_rlast I 1 -// master1_ruser I 1 +// master1_b_put_val I 6 reg +// master1_r_put_val I 72 reg // m_external_interrupt_req_set_not_clear I 1 reg // s_external_interrupt_req_set_not_clear I 1 // non_maskable_interrupt_req_set_not_clear I 1 unused // set_verbosity_verbosity I 4 +// debug_module_mem_server_awvalid I 1 // debug_module_mem_server_awid I 5 // debug_module_mem_server_awaddr I 64 // debug_module_mem_server_awlen I 8 @@ -131,11 +113,13 @@ // debug_module_mem_server_awprot I 3 // debug_module_mem_server_awqos I 4 // debug_module_mem_server_awregion I 4 +// debug_module_mem_server_wvalid I 1 // debug_module_mem_server_wdata I 64 // debug_module_mem_server_wstrb I 8 // debug_module_mem_server_wlast I 1 // debug_module_mem_server_wuser I 1 // debug_module_mem_server_bready I 1 +// debug_module_mem_server_arvalid I 1 // debug_module_mem_server_arid I 5 // debug_module_mem_server_araddr I 64 // debug_module_mem_server_arlen I 8 @@ -153,14 +137,12 @@ // hart0_csr_mem_server_request_put I 77 reg // hart0_put_other_req_put I 4 // EN_start I 1 -// master0_bvalid I 1 -// master0_rvalid I 1 -// master1_bvalid I 1 -// master1_rvalid I 1 +// EN_master1_aw_drop I 1 +// EN_master1_w_drop I 1 +// EN_master1_b_put I 1 +// EN_master1_ar_drop I 1 +// EN_master1_r_put I 1 // EN_set_verbosity I 1 -// debug_module_mem_server_awvalid I 1 -// debug_module_mem_server_wvalid I 1 -// debug_module_mem_server_arvalid I 1 // EN_hart0_run_halt_server_request_put I 1 // EN_hart0_gpr_mem_server_request_put I 1 // EN_hart0_fpr_mem_server_request_put I 1 @@ -172,7 +154,8 @@ // EN_hart0_csr_mem_server_response_get I 1 // // Combinational paths from inputs to outputs: -// (debug_module_mem_server_awid, +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -182,13 +165,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bid -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bid +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -198,13 +181,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bresp -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bresp +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -214,13 +197,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_buser -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_buser +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -230,13 +213,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bvalid -// (debug_module_mem_server_arid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bvalid +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -245,9 +228,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rid -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rid +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -256,9 +239,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rdata -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rdata +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -267,9 +250,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rresp -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rresp +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -278,9 +261,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rlast -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rlast +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -289,9 +272,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_ruser -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_ruser +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -300,8 +283,7 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rvalid +// debug_module_mem_server_arregion) -> debug_module_mem_server_rvalid // // @@ -364,9 +346,9 @@ module mkProc(CLK, master0_wready, + master0_bvalid, master0_bid, master0_bresp, - master0_bvalid, master0_bready, @@ -394,89 +376,50 @@ module mkProc(CLK, master0_arready, + master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, master0_ruser, - master0_rvalid, master0_rready, - master1_awid, + master1_aw_canPeek, - master1_awaddr, + master1_aw_peek, + RDY_master1_aw_peek, - master1_awlen, + EN_master1_aw_drop, + RDY_master1_aw_drop, - master1_awsize, + master1_w_canPeek, - master1_awburst, + master1_w_peek, + RDY_master1_w_peek, - master1_awlock, + EN_master1_w_drop, + RDY_master1_w_drop, - master1_awcache, + master1_b_canPut, - master1_awprot, + master1_b_put_val, + EN_master1_b_put, + RDY_master1_b_put, - master1_awqos, + master1_ar_canPeek, - master1_awregion, + master1_ar_peek, + RDY_master1_ar_peek, - master1_awvalid, + EN_master1_ar_drop, + RDY_master1_ar_drop, - master1_awready, + master1_r_canPut, - master1_wdata, - - master1_wstrb, - - master1_wlast, - - master1_wuser, - - master1_wvalid, - - master1_wready, - - master1_bid, - master1_bresp, - master1_bvalid, - - master1_bready, - - master1_arid, - - master1_araddr, - - master1_arlen, - - master1_arsize, - - master1_arburst, - - master1_arlock, - - master1_arcache, - - master1_arprot, - - master1_arqos, - - master1_arregion, - - master1_arvalid, - - master1_arready, - - master1_rid, - master1_rdata, - master1_rresp, - master1_rlast, - master1_ruser, - master1_rvalid, - - master1_rready, + master1_r_put_val, + EN_master1_r_put, + RDY_master1_r_put, m_external_interrupt_req_set_not_clear, @@ -488,6 +431,7 @@ module mkProc(CLK, EN_set_verbosity, RDY_set_verbosity, + debug_module_mem_server_awvalid, debug_module_mem_server_awid, debug_module_mem_server_awaddr, debug_module_mem_server_awlen, @@ -498,15 +442,14 @@ module mkProc(CLK, debug_module_mem_server_awprot, debug_module_mem_server_awqos, debug_module_mem_server_awregion, - debug_module_mem_server_awvalid, debug_module_mem_server_awready, + debug_module_mem_server_wvalid, debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, debug_module_mem_server_wuser, - debug_module_mem_server_wvalid, debug_module_mem_server_wready, @@ -518,6 +461,7 @@ module mkProc(CLK, debug_module_mem_server_bready, + debug_module_mem_server_arvalid, debug_module_mem_server_arid, debug_module_mem_server_araddr, debug_module_mem_server_arlen, @@ -528,7 +472,6 @@ module mkProc(CLK, debug_module_mem_server_arprot, debug_module_mem_server_arqos, debug_module_mem_server_arregion, - debug_module_mem_server_arvalid, debug_module_mem_server_arready, @@ -649,9 +592,9 @@ module mkProc(CLK, input master0_wready; // action method master0_b_bflit + input master0_bvalid; input [4 : 0] master0_bid; input [1 : 0] master0_bresp; - input master0_bvalid; // value method master0_b_bready output master0_bready; @@ -695,128 +638,64 @@ module mkProc(CLK, input master0_arready; // action method master0_r_rflit + input master0_rvalid; input [4 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; input master0_ruser; - input master0_rvalid; // value method master0_r_rready output master0_rready; - // value method master1_aw_awid - output [3 : 0] master1_awid; + // value method master1_aw_canPeek + output master1_aw_canPeek; - // value method master1_aw_awaddr - output [63 : 0] master1_awaddr; + // value method master1_aw_peek + output [96 : 0] master1_aw_peek; + output RDY_master1_aw_peek; - // value method master1_aw_awlen - output [7 : 0] master1_awlen; + // action method master1_aw_drop + input EN_master1_aw_drop; + output RDY_master1_aw_drop; - // value method master1_aw_awsize - output [2 : 0] master1_awsize; + // value method master1_w_canPeek + output master1_w_canPeek; - // value method master1_aw_awburst - output [1 : 0] master1_awburst; + // value method master1_w_peek + output [73 : 0] master1_w_peek; + output RDY_master1_w_peek; - // value method master1_aw_awlock - output master1_awlock; + // action method master1_w_drop + input EN_master1_w_drop; + output RDY_master1_w_drop; - // value method master1_aw_awcache - output [3 : 0] master1_awcache; + // value method master1_b_canPut + output master1_b_canPut; - // value method master1_aw_awprot - output [2 : 0] master1_awprot; + // action method master1_b_put + input [5 : 0] master1_b_put_val; + input EN_master1_b_put; + output RDY_master1_b_put; - // value method master1_aw_awqos - output [3 : 0] master1_awqos; + // value method master1_ar_canPeek + output master1_ar_canPeek; - // value method master1_aw_awregion - output [3 : 0] master1_awregion; + // value method master1_ar_peek + output [96 : 0] master1_ar_peek; + output RDY_master1_ar_peek; - // value method master1_aw_awuser + // action method master1_ar_drop + input EN_master1_ar_drop; + output RDY_master1_ar_drop; - // value method master1_aw_awvalid - output master1_awvalid; + // value method master1_r_canPut + output master1_r_canPut; - // action method master1_aw_awready - input master1_awready; - - // value method master1_w_wdata - output [63 : 0] master1_wdata; - - // value method master1_w_wstrb - output [7 : 0] master1_wstrb; - - // value method master1_w_wlast - output master1_wlast; - - // value method master1_w_wuser - output master1_wuser; - - // value method master1_w_wvalid - output master1_wvalid; - - // action method master1_w_wready - input master1_wready; - - // action method master1_b_bflit - input [3 : 0] master1_bid; - input [1 : 0] master1_bresp; - input master1_bvalid; - - // value method master1_b_bready - output master1_bready; - - // value method master1_ar_arid - output [3 : 0] master1_arid; - - // value method master1_ar_araddr - output [63 : 0] master1_araddr; - - // value method master1_ar_arlen - output [7 : 0] master1_arlen; - - // value method master1_ar_arsize - output [2 : 0] master1_arsize; - - // value method master1_ar_arburst - output [1 : 0] master1_arburst; - - // value method master1_ar_arlock - output master1_arlock; - - // value method master1_ar_arcache - output [3 : 0] master1_arcache; - - // value method master1_ar_arprot - output [2 : 0] master1_arprot; - - // value method master1_ar_arqos - output [3 : 0] master1_arqos; - - // value method master1_ar_arregion - output [3 : 0] master1_arregion; - - // value method master1_ar_aruser - - // value method master1_ar_arvalid - output master1_arvalid; - - // action method master1_ar_arready - input master1_arready; - - // action method master1_r_rflit - input [3 : 0] master1_rid; - input [63 : 0] master1_rdata; - input [1 : 0] master1_rresp; - input master1_rlast; - input master1_ruser; - input master1_rvalid; - - // value method master1_r_rready - output master1_rready; + // action method master1_r_put + input [71 : 0] master1_r_put_val; + input EN_master1_r_put; + output RDY_master1_r_put; // action method m_external_interrupt_req input m_external_interrupt_req_set_not_clear; @@ -833,6 +712,7 @@ module mkProc(CLK, output RDY_set_verbosity; // action method debug_module_mem_server_aw_awflit + input debug_module_mem_server_awvalid; input [4 : 0] debug_module_mem_server_awid; input [63 : 0] debug_module_mem_server_awaddr; input [7 : 0] debug_module_mem_server_awlen; @@ -843,17 +723,16 @@ module mkProc(CLK, input [2 : 0] debug_module_mem_server_awprot; input [3 : 0] debug_module_mem_server_awqos; input [3 : 0] debug_module_mem_server_awregion; - input debug_module_mem_server_awvalid; // value method debug_module_mem_server_aw_awready output debug_module_mem_server_awready; // action method debug_module_mem_server_w_wflit + input debug_module_mem_server_wvalid; input [63 : 0] debug_module_mem_server_wdata; input [7 : 0] debug_module_mem_server_wstrb; input debug_module_mem_server_wlast; input debug_module_mem_server_wuser; - input debug_module_mem_server_wvalid; // value method debug_module_mem_server_w_wready output debug_module_mem_server_wready; @@ -873,6 +752,7 @@ module mkProc(CLK, input debug_module_mem_server_bready; // action method debug_module_mem_server_ar_arflit + input debug_module_mem_server_arvalid; input [4 : 0] debug_module_mem_server_arid; input [63 : 0] debug_module_mem_server_araddr; input [7 : 0] debug_module_mem_server_arlen; @@ -883,7 +763,6 @@ module mkProc(CLK, input [2 : 0] debug_module_mem_server_arprot; input [3 : 0] debug_module_mem_server_arqos; input [3 : 0] debug_module_mem_server_arregion; - input debug_module_mem_server_arvalid; // value method debug_module_mem_server_ar_arready output debug_module_mem_server_arready; @@ -955,22 +834,16 @@ module mkProc(CLK, output RDY_hart0_put_other_req_put; // signals for module outputs + wire [96 : 0] master1_ar_peek, master1_aw_peek; + wire [73 : 0] master1_w_peek; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; wire [63 : 0] debug_module_mem_server_rdata, master0_araddr, master0_awaddr, - master0_wdata, - master1_araddr, - master1_awaddr, - master1_wdata; - wire [7 : 0] master0_arlen, - master0_awlen, - master0_wstrb, - master1_arlen, - master1_awlen, - master1_wstrb; + master0_wdata; + wire [7 : 0] master0_arlen, master0_awlen, master0_wstrb; wire [4 : 0] debug_module_mem_server_bid, debug_module_mem_server_rid, master0_arid, @@ -980,29 +853,12 @@ module mkProc(CLK, master0_arregion, master0_awcache, master0_awqos, - master0_awregion, - master1_arcache, - master1_arid, - master1_arqos, - master1_arregion, - master1_awcache, - master1_awid, - master1_awqos, - master1_awregion; - wire [2 : 0] master0_arprot, - master0_arsize, - master0_awprot, - master0_awsize, - master1_arprot, - master1_arsize, - master1_awprot, - master1_awsize; + master0_awregion; + wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, master0_awsize; wire [1 : 0] debug_module_mem_server_bresp, debug_module_mem_server_rresp, master0_arburst, - master0_awburst, - master1_arburst, - master1_awburst; + master0_awburst; wire RDY_hart0_csr_mem_server_request_put, RDY_hart0_csr_mem_server_response_get, RDY_hart0_fpr_mem_server_request_put, @@ -1012,6 +868,14 @@ module mkProc(CLK, RDY_hart0_put_other_req_put, RDY_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_response_get, + RDY_master1_ar_drop, + RDY_master1_ar_peek, + RDY_master1_aw_drop, + RDY_master1_aw_peek, + RDY_master1_b_put, + RDY_master1_r_put, + RDY_master1_w_drop, + RDY_master1_w_peek, RDY_set_verbosity, RDY_start, debug_module_mem_server_arready, @@ -1031,15 +895,11 @@ module mkProc(CLK, master0_wlast, master0_wuser, master0_wvalid, - master1_arlock, - master1_arvalid, - master1_awlock, - master1_awvalid, - master1_bready, - master1_rready, - master1_wlast, - master1_wuser, - master1_wvalid; + master1_ar_canPeek, + master1_aw_canPeek, + master1_b_canPut, + master1_r_canPut, + master1_w_canPeek; // inlined wires wire [584 : 0] enqDst_1_0_lat_0$wget; @@ -1060,16 +920,8 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read; - wire [97 : 0] llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read; + wire [97 : 0] llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget, + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget; wire [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read, llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read, @@ -1077,11 +929,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read, - llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read; + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read; wire [73 : 0] enqDst_0_lat_0$wget, llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read, @@ -1091,30 +939,21 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget; - wire [72 : 0] llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget; + wire [72 : 0] llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget, propDstData_0_lat_0$wget, propDstData_1_lat_0$wget; - wire [71 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget; wire [65 : 0] llc_mem_server_enqDst_0_lat_0$wget; wire [64 : 0] mmioPlatform_toHostQ_enqReq_lat_0$wget; wire [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read, llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read, llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read; - wire [6 : 0] llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read; - wire [5 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget; + wire [6 : 0] llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget; wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, @@ -1124,29 +963,21 @@ module mkProc(CLK, wire enqDst_0_lat_0$whas, enqDst_1_0_lat_0$whas, llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas, + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas, + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas, + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas, + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas, llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas, llc_mem_server_propDstIdx_0_lat_1$whas, mmioPlatform_fromHostQ_deqReq_lat_0$whas, mmioPlatform_toHostQ_enqReq_lat_0$whas, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, propDstIdx_1_1_lat_1$whas, propDstIdx_1_lat_1$whas; @@ -1210,11 +1041,6 @@ module mkProc(CLK, wire [515 : 0] llc_axi4_adapter_rg_cline$D_IN; wire llc_axi4_adapter_rg_cline$EN; - // register llc_axi4_adapter_rg_rd_req_beat - reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat; - wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN; - wire llc_axi4_adapter_rg_rd_req_beat$EN; - // register llc_axi4_adapter_rg_rd_rsp_beat reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat; wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN; @@ -1453,41 +1279,26 @@ module mkProc(CLK, wire [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; wire mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN; - // register mmio_axi4_adapter_master_xactor_clearing - reg mmio_axi4_adapter_master_xactor_clearing; - wire mmio_axi4_adapter_master_xactor_clearing$D_IN, - mmio_axi4_adapter_master_xactor_clearing$EN; - - // register mmio_axi4_adapter_master_xactor_shim_arff_rv - reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv; - wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_arff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_awff_rv - reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv; - wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_awff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_bff_rv - reg [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv; - wire [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_bff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_rff_rv - reg [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv; - wire [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_rff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_wff_rv - reg [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv; - wire [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_wff_rv$EN; - // register mmio_axi4_adapter_read_req_addr reg [63 : 0] mmio_axi4_adapter_read_req_addr; wire [63 : 0] mmio_axi4_adapter_read_req_addr$D_IN; wire mmio_axi4_adapter_read_req_addr$EN; + // register mmio_axi4_adapter_rg_rd_rsp_beat + reg mmio_axi4_adapter_rg_rd_rsp_beat; + wire mmio_axi4_adapter_rg_rd_rsp_beat$D_IN, + mmio_axi4_adapter_rg_rd_rsp_beat$EN; + + // register mmio_axi4_adapter_rg_wr_req_beat + reg mmio_axi4_adapter_rg_wr_req_beat; + wire mmio_axi4_adapter_rg_wr_req_beat$D_IN, + mmio_axi4_adapter_rg_wr_req_beat$EN; + + // register mmio_axi4_adapter_rspData + reg [128 : 0] mmio_axi4_adapter_rspData; + wire [128 : 0] mmio_axi4_adapter_rspData$D_IN; + wire mmio_axi4_adapter_rspData$EN; + // register propDstData_0_rl reg [72 : 0] propDstData_0_rl; wire [72 : 0] propDstData_0_rl$D_IN; @@ -1721,6 +1532,51 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$ENQ, mmio_axi4_adapter_f_rsps_to_core$FULL_N; + // ports of submodule mmio_axi4_adapter_master_shim_arff + wire [96 : 0] mmio_axi4_adapter_master_shim_arff$D_IN, + mmio_axi4_adapter_master_shim_arff$D_OUT; + wire mmio_axi4_adapter_master_shim_arff$CLR, + mmio_axi4_adapter_master_shim_arff$DEQ, + mmio_axi4_adapter_master_shim_arff$EMPTY_N, + mmio_axi4_adapter_master_shim_arff$ENQ, + mmio_axi4_adapter_master_shim_arff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_awff + wire [96 : 0] mmio_axi4_adapter_master_shim_awff$D_IN, + mmio_axi4_adapter_master_shim_awff$D_OUT; + wire mmio_axi4_adapter_master_shim_awff$CLR, + mmio_axi4_adapter_master_shim_awff$DEQ, + mmio_axi4_adapter_master_shim_awff$EMPTY_N, + mmio_axi4_adapter_master_shim_awff$ENQ, + mmio_axi4_adapter_master_shim_awff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_bff + wire [5 : 0] mmio_axi4_adapter_master_shim_bff$D_IN, + mmio_axi4_adapter_master_shim_bff$D_OUT; + wire mmio_axi4_adapter_master_shim_bff$CLR, + mmio_axi4_adapter_master_shim_bff$DEQ, + mmio_axi4_adapter_master_shim_bff$EMPTY_N, + mmio_axi4_adapter_master_shim_bff$ENQ, + mmio_axi4_adapter_master_shim_bff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_rff + wire [71 : 0] mmio_axi4_adapter_master_shim_rff$D_IN, + mmio_axi4_adapter_master_shim_rff$D_OUT; + wire mmio_axi4_adapter_master_shim_rff$CLR, + mmio_axi4_adapter_master_shim_rff$DEQ, + mmio_axi4_adapter_master_shim_rff$EMPTY_N, + mmio_axi4_adapter_master_shim_rff$ENQ, + mmio_axi4_adapter_master_shim_rff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_wff + wire [73 : 0] mmio_axi4_adapter_master_shim_wff$D_IN, + mmio_axi4_adapter_master_shim_wff$D_OUT; + wire mmio_axi4_adapter_master_shim_wff$CLR, + mmio_axi4_adapter_master_shim_wff$DEQ, + mmio_axi4_adapter_master_shim_wff$EMPTY_N, + mmio_axi4_adapter_master_shim_wff$ENQ, + mmio_axi4_adapter_master_shim_wff$FULL_N; + // ports of submodule mmio_axi4_adapter_soc_map wire [63 : 0] mmio_axi4_adapter_soc_map$m_is_IO_addr_addr, mmio_axi4_adapter_soc_map$m_is_mem_addr_addr, @@ -1736,36 +1592,36 @@ module mkProc(CLK, CAN_FIRE_RL_enqDst_0_canon, CAN_FIRE_RL_enqDst_1_0_canon, CAN_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut, CAN_FIRE_RL_llc_mem_server_doEnq, CAN_FIRE_RL_llc_mem_server_dstSelectSrc, CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, @@ -1812,20 +1668,6 @@ module mkProc(CLK, CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone, CAN_FIRE_RL_mmioPlatform_waitMTimeDone, CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, @@ -1879,11 +1721,11 @@ module mkProc(CLK, CAN_FIRE_master0_b_bflit, CAN_FIRE_master0_r_rflit, CAN_FIRE_master0_w_wready, - CAN_FIRE_master1_ar_arready, - CAN_FIRE_master1_aw_awready, - CAN_FIRE_master1_b_bflit, - CAN_FIRE_master1_r_rflit, - CAN_FIRE_master1_w_wready, + CAN_FIRE_master1_ar_drop, + CAN_FIRE_master1_aw_drop, + CAN_FIRE_master1_b_put, + CAN_FIRE_master1_r_put, + CAN_FIRE_master1_w_drop, CAN_FIRE_non_maskable_interrupt_req, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_set_verbosity, @@ -1896,36 +1738,36 @@ module mkProc(CLK, WILL_FIRE_RL_enqDst_0_canon, WILL_FIRE_RL_enqDst_1_0_canon, WILL_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut, WILL_FIRE_RL_llc_mem_server_doEnq, WILL_FIRE_RL_llc_mem_server_dstSelectSrc, WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, @@ -1972,20 +1814,6 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone, WILL_FIRE_RL_mmioPlatform_waitMTimeDone, WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, @@ -2039,11 +1867,11 @@ module mkProc(CLK, WILL_FIRE_master0_b_bflit, WILL_FIRE_master0_r_rflit, WILL_FIRE_master0_w_wready, - WILL_FIRE_master1_ar_arready, - WILL_FIRE_master1_aw_awready, - WILL_FIRE_master1_b_bflit, - WILL_FIRE_master1_r_rflit, - WILL_FIRE_master1_w_wready, + WILL_FIRE_master1_ar_drop, + WILL_FIRE_master1_aw_drop, + WILL_FIRE_master1_b_put, + WILL_FIRE_master1_r_put, + WILL_FIRE_master1_w_drop, WILL_FIRE_non_maskable_interrupt_req, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_set_verbosity, @@ -2074,7 +1902,7 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9; wire [129 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1, - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2; wire [128 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1, MUX_mmioPlatform_amoResp$write_1__VAL_2; wire [66 : 0] MUX_mmioPlatform_curReq$write_1__VAL_1, @@ -2115,46 +1943,51 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1, - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2, + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h222673; - reg [31 : 0] v__h222210; - reg [31 : 0] v__h11342; - reg [31 : 0] v__h15880; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h4363; - reg [31 : 0] v__h7984; - reg [31 : 0] v__h19409; - reg [31 : 0] v__h18412; - reg [31 : 0] v__h18942; - reg [31 : 0] v__h10403; - reg [31 : 0] v__h10598; - reg [31 : 0] v__h199861; - reg [31 : 0] v__h213570; - reg [31 : 0] v__h191840; - reg [31 : 0] v__h221196; - reg [31 : 0] v__h192429; - reg [31 : 0] v__h192615; - reg [31 : 0] v__h4357; - reg [31 : 0] v__h7978; - reg [31 : 0] v__h10397; - reg [31 : 0] v__h10592; - reg [31 : 0] v__h11336; - reg [31 : 0] v__h15874; - reg [31 : 0] v__h16017; - reg [31 : 0] v__h18406; - reg [31 : 0] v__h18936; - reg [31 : 0] v__h19403; - reg [31 : 0] v__h191834; - reg [31 : 0] v__h192423; - reg [31 : 0] v__h192609; - reg [31 : 0] v__h199855; - reg [31 : 0] v__h213564; - reg [31 : 0] v__h221190; - reg [31 : 0] v__h222204; - reg [31 : 0] v__h222667; + reg [31 : 0] v__h224843; + reg [31 : 0] v__h224395; + reg [31 : 0] v__h9702; + reg [31 : 0] v__h9897; + reg [31 : 0] v__h11307; + reg [31 : 0] v__h17239; + reg [31 : 0] v__h17410; + reg [31 : 0] v__h18103; + reg [31 : 0] v__h18189; + reg [31 : 0] v__h2280; + reg [31 : 0] v__h7388; + reg [31 : 0] v__h20501; + reg [31 : 0] v__h21031; + reg [31 : 0] v__h21496; + reg [31 : 0] v__h202046; + reg [31 : 0] v__h215755; + reg [31 : 0] v__h194023; + reg [31 : 0] v__h223381; + reg [31 : 0] v__h194612; + reg [31 : 0] v__h194798; + reg [31 : 0] v__h2274; + reg [31 : 0] v__h7382; + reg [31 : 0] v__h9696; + reg [31 : 0] v__h9891; + reg [31 : 0] v__h11301; + reg [31 : 0] v__h17233; + reg [31 : 0] v__h17404; + reg [31 : 0] v__h18097; + reg [31 : 0] v__h18183; + reg [31 : 0] v__h20495; + reg [31 : 0] v__h21025; + reg [31 : 0] v__h21490; + reg [31 : 0] v__h194017; + reg [31 : 0] v__h194606; + reg [31 : 0] v__h194792; + reg [31 : 0] v__h202040; + reg [31 : 0] v__h215749; + reg [31 : 0] v__h223375; + reg [31 : 0] v__h224389; + reg [31 : 0] v__h224837; // synopsys translate_on // remaining internal signals @@ -2162,212 +1995,250 @@ module mkProc(CLK, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32, - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952, - dword__h148773, - ld_data__h186687, - v_wdata__h213878; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358; - reg [7 : 0] v_wstrb__h213879; - reg [5 : 0] IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811; - reg [2 : 0] x__h99064; - reg [1 : 0] CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30, - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15, - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16; + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, + CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981, + dword__h150925, + ld_data__h188839, + v_wdata__h216063, + wflit_wdata__h18041; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386; + reg [7 : 0] v_wstrb__h216064, wflit_wstrb__h18042; + reg [5 : 0] IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839; + reg [2 : 0] x__h101154; + reg [1 : 0] CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31, - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1451, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1688, - v_wuser__h213881, - x__h125885, - x__h99065; - wire [583 : 0] IF_enqDst_1_0_lat_1_whas__612_THEN_enqDst_1_0__ETC___d1659; - wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1808; - wire [517 : 0] IF_enqDst_1_0_lat_1_whas__612_THEN_enqDst_1_0__ETC___d1658; - wire [515 : 0] IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1650, - IF_llc_axi4_adapter_rg_rd_rsp_beat_229_BIT_0_2_ETC___d2271, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1803; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2000, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1785; - wire [129 : 0] IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1134; - wire [128 : 0] amoExec___d1043, - amoExec___d1099, - amoExec___d1328, - amoExec___d887, - amoExec___d973; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1751, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1768, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1802, - _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213; - wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37, - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35; - wire [96 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13, - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11; - wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36, - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12; - wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34; - wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513, - IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511; - wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__265_BI_ETC___d1366; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__08_ETC___d2086; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1630, - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1129, - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1127, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885, - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021, - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949, - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073, - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1544, - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1582, - addr1__h88641, - data__h139049, - failed_testnum__h222253, - line_addr__h138482, - line_addr__h148590, - line_addr__h191976, - mmioPlatform_mtime__h57710, - newData__h43098, - newData__h51199, - v_awaddr__h213467, - value__h59417, - x__h46411, - x__h54489, - x__h62414, - x__h66415, - x__h69089, - x__h71630, - x__h77269; - wire [47 : 0] IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1115, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989; - wire [31 : 0] IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1110, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984, - IF_mmioPlatform_fetchingWay_337_THEN_mmioPlatf_ETC___d1363, - amo_req_data__h36993, - lower_data__h42399, + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1716, + v_wuser__h216066, + x__h101155, + x__h127975; + wire [583 : 0] IF_enqDst_1_0_lat_1_whas__640_THEN_enqDst_1_0__ETC___d1687; + wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1836; + wire [517 : 0] IF_enqDst_1_0_lat_1_whas__640_THEN_enqDst_1_0__ETC___d1686; + wire [515 : 0] IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1678, + IF_llc_axi4_adapter_rg_rd_rsp_beat_258_BIT_0_2_ETC___d2300, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1831; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2029, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1813; + wire [129 : 0] IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1162; + wire [128 : 0] amoExec___d1001, + amoExec___d1071, + amoExec___d1127, + amoExec___d1356, + amoExec___d915, + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1779, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1796, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1830; + wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34, + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32; + wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33; + wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31; + wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541, + IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539; + wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2118; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1658, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1157, + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1155, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101, + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1572, + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1610, + addr1__h90731, + data__h141198, + failed_testnum__h224438, + line_addr__h140631, + line_addr__h150742, + line_addr__h194159, + mmioPlatform_mtime__h59797, + newData__h45185, + newData__h53286, + v_awaddr__h215652, + value__h61504, + x__h48498, + x__h56576, + x__h64504, + x__h68505, + x__h71179, + x__h73720, + x__h79359; + wire [47 : 0] IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1143, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942; + wire [31 : 0] IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1138, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933, + IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391, + amo_req_data__h39080, + lower_data__h44486, mmioPlatform_mtime_BITS_31_TO_0__q8, mmioPlatform_mtime_BITS_63_TO_32__q7, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, - upper_data__h42400, - v__h42255, - v__h42292, - x_data__h39934; - wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__401_THEN__ETC___d1507; - wire [7 : 0] IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872, - mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877; - wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33; - wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__401_THEN__ETC___d1506; - wire [3 : 0] b__h191767, b__h4263, mmioPlatform_reqAmofunc__h86411; - wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1726, - v_awsize_val__h15192; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1635, - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1549, - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1587; - wire IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929, - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785, - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924, - IF_enqDst_0_lat_0_whas__416_THEN_enqDst_0_lat__ETC___d1421, - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1620, - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1640, - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1656, - IF_llc_mem_server_enqDst_0_lat_0_whas__091_THE_ETC___d2096, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__076_ETC___d2079, - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1124, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1145, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334, - IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850, - IF_mmio_axi4_adapter_f_rsps_to_core_first__265_ETC___d1341, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53, - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1570, - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1608, - IF_propDstIdx_0_lat_0_whas__387_THEN_NOT_propD_ETC___d1453, - IF_propDstIdx_0_lat_0_whas__387_THEN_propDstId_ETC___d1390, - IF_propDstIdx_1_0_lat_0_whas__524_THEN_NOT_pro_ETC___d1690, - IF_propDstIdx_1_0_lat_0_whas__524_THEN_propDst_ETC___d1527, - IF_propDstIdx_1_1_lat_0_whas__531_THEN_propDst_ETC___d1534, - IF_propDstIdx_1_lat_0_whas__394_THEN_propDstId_ETC___d1397, - NOT_enqDst_0_rl_419_BIT_73_420_425_AND_SEL_ARR_ETC___d1513, - NOT_enqDst_0_rl_419_BIT_73_420_425_AND_SEL_ARR_ETC___d1518, - NOT_enqDst_1_0_rl_618_BIT_584_619_624_AND_SEL__ETC___d1814, - NOT_enqDst_1_0_rl_618_BIT_584_619_624_AND_SEL__ETC___d1819, - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225, - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2304, - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2307, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1168, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1263, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1274, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1284, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1332, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1344, - NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1455, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1692, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755, - core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2236, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2016, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1917, - mmioPlatform_amoWaitWriteResp_278_OR_core_0_RD_ETC___d1281, - mmioPlatform_cycle_57_ULT_99___d458, - mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346, - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996, - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941, - x__h114586, - x__h121150, - x__h98864; + upper_data__h44487, + v__h44342, + v__h44379, + x_data__h42021; + wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535; + wire [7 : 0] IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900, + mem_req_rd_addr_arlen__h5411, + mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905; + wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30; + wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534, + x__h15205, + x__h15217, + x__h15229, + x__h15241, + x__h15253, + x__h15265, + x__h15277, + x__h15289, + x__h15301, + x__h15313, + x__h15325, + x__h15337, + x__h15349, + x__h15361, + x__h15373, + y__h15206, + y__h15218, + y__h15230, + y__h15242, + y__h15254, + y__h15266, + y__h15278, + y__h15290, + y__h15302, + y__h15314, + y__h15326, + y__h15338, + y__h15350, + y__h15362, + y__h15374; + wire [3 : 0] b__h193959, b__h2174, mmioPlatform_reqAmofunc__h88501; + wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1754, + _theResult_____1_awsize_val__h17178; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1663, + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1577, + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1615; + wire IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957, + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813, + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952, + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1648, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1668, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1684, + IF_llc_mem_server_enqDst_0_lat_0_whas__123_THE_ETC___d2128, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__108_ETC___d2111, + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1152, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1173, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362, + IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878, + IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201, + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1598, + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1636, + IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481, + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418, + IF_propDstIdx_1_0_lat_0_whas__552_THEN_NOT_pro_ETC___d1718, + IF_propDstIdx_1_0_lat_0_whas__552_THEN_propDst_ETC___d1555, + IF_propDstIdx_1_1_lat_0_whas__559_THEN_propDst_ETC___d1562, + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425, + NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541, + NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1546, + NOT_enqDst_1_0_rl_646_BIT_584_647_652_AND_SEL__ETC___d1842, + NOT_enqDst_1_0_rl_646_BIT_584_647_652_AND_SEL__ETC___d1847, + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254, + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2333, + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2336, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1196, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1291, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1302, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1312, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1360, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1372, + NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1720, + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, + _theResult____h13554, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783, + core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2265, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2047, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1946, + mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309, + mmioPlatform_cycle_85_ULT_99___d486, + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374, + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024, + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252, + mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, + mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210, + whichHalf___1__h15117, + x__h100954, + x__h10759, + x__h116676, + x__h123240, + x__h17973; // action method start assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; @@ -2377,47 +2248,47 @@ module mkProc(CLK, // value method master0_aw_awid assign master0_awid = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[97:93] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[97:93] ; // value method master0_aw_awaddr assign master0_awaddr = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[92:29] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[92:29] ; // value method master0_aw_awlen assign master0_awlen = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[28:21] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[28:21] ; // value method master0_aw_awsize assign master0_awsize = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[20:18] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[20:18] ; // value method master0_aw_awburst assign master0_awburst = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[17:16] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[17:16] ; // value method master0_aw_awlock assign master0_awlock = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[15] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[15] ; // value method master0_aw_awcache assign master0_awcache = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[14:11] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[14:11] ; // value method master0_aw_awprot assign master0_awprot = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[10:8] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[10:8] ; // value method master0_aw_awqos assign master0_awqos = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[7:4] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[7:4] ; // value method master0_aw_awregion assign master0_awregion = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[3:0] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[3:0] ; // value method master0_aw_awvalid assign master0_awvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek ; // action method master0_aw_awready assign CAN_FIRE_master0_aw_awready = 1'd1 ; @@ -2425,23 +2296,23 @@ module mkProc(CLK, // value method master0_w_wdata assign master0_wdata = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[73:10] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[73:10] ; // value method master0_w_wstrb assign master0_wstrb = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[9:2] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[9:2] ; // value method master0_w_wlast assign master0_wlast = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[1] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[1] ; // value method master0_w_wuser assign master0_wuser = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[0] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[0] ; // value method master0_w_wvalid assign master0_wvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek ; // action method master0_w_wready assign CAN_FIRE_master0_w_wready = 1'd1 ; @@ -2449,54 +2320,54 @@ module mkProc(CLK, // action method master0_b_bflit assign CAN_FIRE_master0_b_bflit = 1'd1 ; - assign WILL_FIRE_master0_b_bflit = master0_bvalid ; + assign WILL_FIRE_master0_b_bflit = 1'd1 ; // value method master0_b_bready assign master0_bready = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; // value method master0_ar_arid assign master0_arid = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[97:93] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[97:93] ; // value method master0_ar_araddr assign master0_araddr = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[92:29] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[92:29] ; // value method master0_ar_arlen assign master0_arlen = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[28:21] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[28:21] ; // value method master0_ar_arsize assign master0_arsize = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[20:18] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[20:18] ; // value method master0_ar_arburst assign master0_arburst = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[17:16] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[17:16] ; // value method master0_ar_arlock assign master0_arlock = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[15] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[15] ; // value method master0_ar_arcache assign master0_arcache = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[14:11] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[14:11] ; // value method master0_ar_arprot assign master0_arprot = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[10:8] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[10:8] ; // value method master0_ar_arqos assign master0_arqos = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[7:4] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[7:4] ; // value method master0_ar_arregion assign master0_arregion = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[3:0] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[3:0] ; // value method master0_ar_arvalid assign master0_arvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek ; // action method master0_ar_arready assign CAN_FIRE_master0_ar_arready = 1'd1 ; @@ -2504,144 +2375,64 @@ module mkProc(CLK, // action method master0_r_rflit assign CAN_FIRE_master0_r_rflit = 1'd1 ; - assign WILL_FIRE_master0_r_rflit = master0_rvalid ; + assign WILL_FIRE_master0_r_rflit = 1'd1 ; // value method master0_r_rready assign master0_rready = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - // value method master1_aw_awid - assign master1_awid = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[96:93] ; + // value method master1_aw_canPeek + assign master1_aw_canPeek = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; - // value method master1_aw_awaddr - assign master1_awaddr = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[92:29] ; + // value method master1_aw_peek + assign master1_aw_peek = mmio_axi4_adapter_master_shim_awff$D_OUT ; + assign RDY_master1_aw_peek = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; - // value method master1_aw_awlen - assign master1_awlen = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[28:21] ; + // action method master1_aw_drop + assign RDY_master1_aw_drop = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; + assign CAN_FIRE_master1_aw_drop = + mmio_axi4_adapter_master_shim_awff$EMPTY_N ; + assign WILL_FIRE_master1_aw_drop = EN_master1_aw_drop ; - // value method master1_aw_awsize - assign master1_awsize = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[20:18] ; + // value method master1_w_canPeek + assign master1_w_canPeek = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; - // value method master1_aw_awburst - assign master1_awburst = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[17:16] ; + // value method master1_w_peek + assign master1_w_peek = mmio_axi4_adapter_master_shim_wff$D_OUT ; + assign RDY_master1_w_peek = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; - // value method master1_aw_awlock - assign master1_awlock = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[15] ; + // action method master1_w_drop + assign RDY_master1_w_drop = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; + assign CAN_FIRE_master1_w_drop = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; + assign WILL_FIRE_master1_w_drop = EN_master1_w_drop ; - // value method master1_aw_awcache - assign master1_awcache = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[14:11] ; + // value method master1_b_canPut + assign master1_b_canPut = mmio_axi4_adapter_master_shim_bff$FULL_N ; - // value method master1_aw_awprot - assign master1_awprot = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[10:8] ; + // action method master1_b_put + assign RDY_master1_b_put = mmio_axi4_adapter_master_shim_bff$FULL_N ; + assign CAN_FIRE_master1_b_put = mmio_axi4_adapter_master_shim_bff$FULL_N ; + assign WILL_FIRE_master1_b_put = EN_master1_b_put ; - // value method master1_aw_awqos - assign master1_awqos = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[7:4] ; + // value method master1_ar_canPeek + assign master1_ar_canPeek = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; - // value method master1_aw_awregion - assign master1_awregion = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[3:0] ; + // value method master1_ar_peek + assign master1_ar_peek = mmio_axi4_adapter_master_shim_arff$D_OUT ; + assign RDY_master1_ar_peek = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; - // value method master1_aw_awvalid - assign master1_awvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + // action method master1_ar_drop + assign RDY_master1_ar_drop = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; + assign CAN_FIRE_master1_ar_drop = + mmio_axi4_adapter_master_shim_arff$EMPTY_N ; + assign WILL_FIRE_master1_ar_drop = EN_master1_ar_drop ; - // action method master1_aw_awready - assign CAN_FIRE_master1_aw_awready = 1'd1 ; - assign WILL_FIRE_master1_aw_awready = 1'd1 ; + // value method master1_r_canPut + assign master1_r_canPut = mmio_axi4_adapter_master_shim_rff$FULL_N ; - // value method master1_w_wdata - assign master1_wdata = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[73:10] ; - - // value method master1_w_wstrb - assign master1_wstrb = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[9:2] ; - - // value method master1_w_wlast - assign master1_wlast = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[1] ; - - // value method master1_w_wuser - assign master1_wuser = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[0] ; - - // value method master1_w_wvalid - assign master1_wvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - - // action method master1_w_wready - assign CAN_FIRE_master1_w_wready = 1'd1 ; - assign WILL_FIRE_master1_w_wready = 1'd1 ; - - // action method master1_b_bflit - assign CAN_FIRE_master1_b_bflit = 1'd1 ; - assign WILL_FIRE_master1_b_bflit = master1_bvalid ; - - // value method master1_b_bready - assign master1_bready = !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - - // value method master1_ar_arid - assign master1_arid = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[96:93] ; - - // value method master1_ar_araddr - assign master1_araddr = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[92:29] ; - - // value method master1_ar_arlen - assign master1_arlen = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[28:21] ; - - // value method master1_ar_arsize - assign master1_arsize = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[20:18] ; - - // value method master1_ar_arburst - assign master1_arburst = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[17:16] ; - - // value method master1_ar_arlock - assign master1_arlock = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[15] ; - - // value method master1_ar_arcache - assign master1_arcache = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[14:11] ; - - // value method master1_ar_arprot - assign master1_arprot = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[10:8] ; - - // value method master1_ar_arqos - assign master1_arqos = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[7:4] ; - - // value method master1_ar_arregion - assign master1_arregion = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[3:0] ; - - // value method master1_ar_arvalid - assign master1_arvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - - // action method master1_ar_arready - assign CAN_FIRE_master1_ar_arready = 1'd1 ; - assign WILL_FIRE_master1_ar_arready = 1'd1 ; - - // action method master1_r_rflit - assign CAN_FIRE_master1_r_rflit = 1'd1 ; - assign WILL_FIRE_master1_r_rflit = master1_rvalid ; - - // value method master1_r_rready - assign master1_rready = !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; + // action method master1_r_put + assign RDY_master1_r_put = mmio_axi4_adapter_master_shim_rff$FULL_N ; + assign CAN_FIRE_master1_r_put = mmio_axi4_adapter_master_shim_rff$FULL_N ; + assign WILL_FIRE_master1_r_put = EN_master1_r_put ; // action method m_external_interrupt_req assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; @@ -2662,8 +2453,7 @@ module mkProc(CLK, // action method debug_module_mem_server_aw_awflit assign CAN_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_aw_awflit = - debug_module_mem_server_awvalid ; + assign WILL_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ; // value method debug_module_mem_server_aw_awready assign debug_module_mem_server_awready = @@ -2671,8 +2461,7 @@ module mkProc(CLK, // action method debug_module_mem_server_w_wflit assign CAN_FIRE_debug_module_mem_server_w_wflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_w_wflit = - debug_module_mem_server_wvalid ; + assign WILL_FIRE_debug_module_mem_server_w_wflit = 1'd1 ; // value method debug_module_mem_server_w_wready assign debug_module_mem_server_wready = @@ -2680,15 +2469,15 @@ module mkProc(CLK, // value method debug_module_mem_server_b_bid assign debug_module_mem_server_bid = - llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33[6:2] ; + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30[6:2] ; // value method debug_module_mem_server_b_bresp assign debug_module_mem_server_bresp = - llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33[1:0] ; + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30[1:0] ; // value method debug_module_mem_server_b_bvalid assign debug_module_mem_server_bvalid = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek ; // action method debug_module_mem_server_b_bready assign CAN_FIRE_debug_module_mem_server_b_bready = 1'd1 ; @@ -2696,8 +2485,7 @@ module mkProc(CLK, // action method debug_module_mem_server_ar_arflit assign CAN_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_ar_arflit = - debug_module_mem_server_arvalid ; + assign WILL_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ; // value method debug_module_mem_server_ar_arready assign debug_module_mem_server_arready = @@ -2705,27 +2493,27 @@ module mkProc(CLK, // value method debug_module_mem_server_r_rid assign debug_module_mem_server_rid = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[72:68] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[72:68] ; // value method debug_module_mem_server_r_rdata assign debug_module_mem_server_rdata = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[67:4] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[67:4] ; // value method debug_module_mem_server_r_rresp assign debug_module_mem_server_rresp = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[3:2] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[3:2] ; // value method debug_module_mem_server_r_rlast assign debug_module_mem_server_rlast = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[1] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[1] ; // value method debug_module_mem_server_r_ruser assign debug_module_mem_server_ruser = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[0] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[0] ; // value method debug_module_mem_server_r_rvalid assign debug_module_mem_server_rvalid = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek ; // action method debug_module_mem_server_r_rready assign CAN_FIRE_debug_module_mem_server_r_rready = 1'd1 ; @@ -3083,6 +2871,66 @@ module mkProc(CLK, .FULL_N(mmio_axi4_adapter_f_rsps_to_core$FULL_N), .EMPTY_N(mmio_axi4_adapter_f_rsps_to_core$EMPTY_N)); + // submodule mmio_axi4_adapter_master_shim_arff + FIFO2 #(.width(32'd97), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_arff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_arff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_arff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_arff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_arff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_arff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_arff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_arff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_awff + FIFO2 #(.width(32'd97), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_awff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_awff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_awff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_awff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_awff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_awff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_awff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_bff + FIFO2 #(.width(32'd6), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_bff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_bff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_bff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_bff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_bff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_bff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_bff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_bff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_rff + FIFO2 #(.width(32'd72), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_rff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_rff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_rff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_rff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_rff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_rff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_rff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_rff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_wff + FIFO2 #(.width(32'd74), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_wff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_wff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_wff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_wff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_wff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_wff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_wff$EMPTY_N)); + // submodule mmio_axi4_adapter_soc_map mkSoC_Map mmio_axi4_adapter_soc_map(.CLK(CLK), .RST_N(RST_N), @@ -3128,7 +2976,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && - IF_enqDst_0_lat_0_whas__416_THEN_enqDst_0_lat__ETC___d1421 ; + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3152,7 +3000,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1620 ; + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1648 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3242,22 +3090,41 @@ module mkProc(CLK, assign CAN_FIRE_RL_rl_tohost = !mmioPlatform_toHostQ_empty ; assign WILL_FIRE_RL_rl_tohost = CAN_FIRE_RL_rl_tohost ; + // rule RL_mmio_axi4_adapter_rl_handle_read_rsps + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + mmio_axi4_adapter_master_shim_rff$EMPTY_N && + (!mmio_axi4_adapter_master_shim_rff$D_OUT[1] || + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + // rule RL_mmio_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 && + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = - mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 && + mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd1 && - b__h4263 == 4'd0 ; + b__h2174 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + + // rule RL_mmio_axi4_adapter_rl_discard_write_rsp + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + b__h2174 != 4'd0 && mmio_axi4_adapter_master_shim_bff$EMPTY_N && + (mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 || + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_handle_non_Ld_St assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = @@ -3267,123 +3134,6 @@ module mkProc(CLK, assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ; - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && - mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = - !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] && - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ; - - // rule RL_mmio_axi4_adapter_rl_discard_write_rsp - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - !mmio_axi4_adapter_master_xactor_clearing && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[6] && - b__h4263 != 4'd0 && - (mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 || - mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && - mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = - !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] && - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ; - - // rule RL_mmio_axi4_adapter_rl_handle_read_rsps - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - !mmio_axi4_adapter_master_xactor_clearing && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72] && - mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // rule RL_mmio_axi4_adapter_master_xactor_do_clear - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = - mmio_axi4_adapter_master_xactor_clearing ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = - mmio_axi4_adapter_master_xactor_clearing ; - // rule RL_mmioPlatform_propagateTime assign CAN_FIRE_RL_mmioPlatform_propagateTime = mmioPlatform_state != 2'd0 ; assign WILL_FIRE_RL_mmioPlatform_propagateTime = @@ -3392,23 +3142,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_57_ULT_99___d458 ; + mmioPlatform_cycle_85_ULT_99___d486 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_57_ULT_99___d458 ; + !mmioPlatform_cycle_85_ULT_99___d486 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 && + NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3425,7 +3175,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786 && + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3434,7 +3184,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850 && + IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3480,7 +3230,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h71630 == 64'd0 || + x__h73720 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3498,7 +3248,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1168 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1196 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3506,37 +3256,37 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1263 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1291 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1274 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1302 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - mmioPlatform_amoWaitWriteResp_278_OR_core_0_RD_ETC___d1281 && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1284 ; + mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309 && + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1312 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1332 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1360 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__265_ETC___d1341 && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1344 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369 && + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1372 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3650,7 +3400,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__091_THE_ETC___d2096 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__123_THE_ETC___d2128 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3669,47 +3419,47 @@ module mkProc(CLK, assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut ; // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = @@ -3718,7 +3468,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2016 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2047 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3730,7 +3480,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1917 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1946 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3749,7 +3499,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1917 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1946 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3760,7 +3510,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2016 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2047 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3773,7 +3523,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1917 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1946 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3783,7 +3533,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2016 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2047 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3800,45 +3550,45 @@ module mkProc(CLK, !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas && !llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ; + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas && !llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ; + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop ; // rule RL_llc_mem_server_axi4_slave_xactor_do_clear assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear = @@ -3879,110 +3629,110 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && - b__h191767 == 4'd0 ; + b__h193959 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut = + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas && llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = + // rule RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] && - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ; + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = !llc_axi4_adapter_master_xactor_clearing && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] && - b__h191767 != 4'd0 ; + b__h193959 != 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut = + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas && llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = + // rule RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] && - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ; + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut ; // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2236 ; + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2265 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3995,7 +3745,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ; + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4003,25 +3753,25 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 || + (!mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4051,12 +3801,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && @@ -4082,31 +3832,33 @@ module mkProc(CLK, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 && !mmio_axi4_adapter_soc_map$m_is_IO_addr ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_master_shim_rff$D_OUT[1] ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3 = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0 ; + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0 ; assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = - { 1'd0, llc$to_child_toC_first[586:1] } ; - assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd1, llc$to_child_toC_first[586:521], llc$to_child_toC_first[519:0] } ; + assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = + { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amo_req_data__h36993 : - x_data__h39934 } ; + amo_req_data__h39080 : + x_data__h42021 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4122,16 +3874,16 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 67'h60000000000000000, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 3'd6, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 65'h0AAAAAAAAAAAAAAAA, - mmio_axi4_adapter_f_rsps_to_core_first__265_BI_ETC___d1366 } ; + mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = @@ -4140,24 +3892,24 @@ module mkProc(CLK, { 3'd6, mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h42255, 32'd0 }, + { v__h44342, 32'd0 }, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1134 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1162 } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = { llc_mem_server_rg_cacheline_cache_addr, 64'hFFFFFFFFFFFFFFFF, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h138482, + { line_addr__h140631, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h148590, + { line_addr__h150742, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4177,14 +3929,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2000, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2029, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd0) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4192,21 +3944,21 @@ module mkProc(CLK, { 65'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 } ; + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 } ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = { 1'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049, 64'd0 } ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) ? 67'h1AAAAAAAAAAAAAAAA : - ((!core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) ? + ((!core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) ? 67'h2AAAAAAAAAAAAAAAA : - IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513) ; + IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, (mmioPlatform_instSel == 2'd3) ? @@ -4219,11 +3971,11 @@ module mkProc(CLK, mmioPlatform_instSel + 2'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_3 = @@ -4234,32 +3986,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 or + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 or + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_5 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_5 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_5 = - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4267,95 +4019,79 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_6 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - (mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 ? + (mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - amoExec___d1328 } ; + amoExec___d1356 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { addr1__h88641, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + { addr1__h90731, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ; - assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = - { mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0, - 1'd0, - _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 } ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = + { mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0, + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 } ; // inlined wires - assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = - { master1_bid, master1_bresp } ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = - master1_bvalid && - !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = - { master1_rid, - master1_rdata, - master1_rresp, - master1_rlast, - master1_ruser } ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = - master1_rvalid && - !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h71630 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73720 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h71630 != 64'd0 ; + x__h73720 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h66415 == 64'd0 ; + x__h68505 == 64'd0 ; assign propDstIdx_1_lat_1$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1455 && - x__h98864 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 && + x__h100954 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17, - SEL_ARR_IF_propDstData_0_lat_0_whas__401_THEN__ETC___d1507 } ; + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535 } ; assign enqDst_0_lat_0$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1455 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 ; assign propDstIdx_1_1_lat_1$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1692 && - x__h121150 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1720 && + x__h123240 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1808 } ; + CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1836 } ; assign enqDst_1_0_lat_0$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1692 ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1720 ; + assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { debug_module_mem_server_awid, debug_module_mem_server_awaddr, debug_module_mem_server_awlen, @@ -4366,18 +4102,18 @@ module mkProc(CLK, debug_module_mem_server_awprot, debug_module_mem_server_awqos, debug_module_mem_server_awregion } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas = debug_module_mem_server_awvalid && !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget = + assign llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget = { debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, debug_module_mem_server_wuser } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas = debug_module_mem_server_wvalid && !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget = + assign llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget = { debug_module_mem_server_arid, debug_module_mem_server_araddr, debug_module_mem_server_arlen, @@ -4388,159 +4124,60 @@ module mkProc(CLK, debug_module_mem_server_arprot, debug_module_mem_server_arqos, debug_module_mem_server_arregion } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas = debug_module_mem_server_arvalid && !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__076_ETC___d2079 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__108_ETC___d2111 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__08_ETC___d2086 } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = + IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2118 } ; + assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = + assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = master0_bvalid && !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; - assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = + assign llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget = { master0_rid, master0_rdata, master0_rresp, master0_rlast, master0_ruser } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = + assign llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas = master0_rvalid && !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && - master1_awready ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - master1_wready ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && - master1_arready ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && debug_module_mem_server_bready ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && debug_module_mem_server_rready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && master0_awready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && master0_wready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && master0_arready ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 5'd16, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], - 8'd0, - v_awsize_val__h15192, - 18'd65536 } ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_awff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129], - 2'd2 } ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_wff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? - 75'h2AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 75'h2AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ? - mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_bff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read = - WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? - 7'd42 : - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 7'd42 : - mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 5'd16, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], - 29'd851968 } ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_arff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ? - mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_rff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ? - 73'h0AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 73'h0AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h4263 - 4'd1 ; + b__h2174 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h4263 ; + b__h2174 ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_awff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read = @@ -4553,9 +4190,9 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_wff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read = @@ -4566,12 +4203,16 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_clearing ? 75'h2AAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[97:93], + 2'd0 } ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read = WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? - 8'd128 : + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_bff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop ? 8'd42 : llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read = @@ -4580,9 +4221,9 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_arff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read = @@ -4594,13 +4235,16 @@ module mkProc(CLK, 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 = - { 6'd32, dword__h148773, 4'd2 } ; + { 1'd1, + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[97:93], + dword__h150925, + 4'd2 } ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_rff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop ? 74'h0AAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read = @@ -4611,13 +4255,13 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 6'd32, v_awaddr__h213467, 29'd15532032 } ; + { 6'd32, v_awaddr__h215652, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read = llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_awff_rv ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop ? 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read = @@ -4626,16 +4270,16 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - v_wdata__h213878, - v_wstrb__h213879, + v_wdata__h216063, + v_wstrb__h216064, llc_axi4_adapter_rg_wr_req_beat == 3'd7, - v_wuser__h213881 } ; + v_wuser__h216066 } ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_wff_rv ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop ? 75'h2AAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read = @@ -4644,9 +4288,9 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = { 1'd1, - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget } ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut ? llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_bff_rv ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read = @@ -4658,13 +4302,13 @@ module mkProc(CLK, 8'd42 : llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 6'd32, line_addr__h191976, 29'd15532032 } ; + { 6'd32, line_addr__h194159, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ? llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_arff_rv ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop ? 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read = @@ -4673,9 +4317,9 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = { 1'd1, - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget } ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut ? llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_rff_rv ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read = @@ -4692,11 +4336,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h191767 - 4'd1 ; + b__h193959 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h191767 ; + b__h193959 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4708,7 +4352,7 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__416_THEN_enqDst_0_lat__ETC___d1421, + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : (enqDst_0_lat_0$whas ? @@ -4719,8 +4363,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1620, - IF_enqDst_1_0_lat_1_whas__612_THEN_enqDst_1_0__ETC___d1659 } ; + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1648, + IF_enqDst_1_0_lat_1_whas__640_THEN_enqDst_1_0__ETC___d1687 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4764,14 +4408,10 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_229_BIT_0_2_ETC___d2271 ; + IF_llc_axi4_adapter_rg_rd_rsp_beat_258_BIT_0_2_ETC___d2300 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; - // register llc_axi4_adapter_rg_rd_req_beat - assign llc_axi4_adapter_rg_rd_req_beat$D_IN = 3'h0 ; - assign llc_axi4_adapter_rg_rd_req_beat$EN = 1'b0 ; - // register llc_axi4_adapter_rg_rd_rsp_beat assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN = llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; @@ -4817,7 +4457,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__091_THE_ETC___d2096, + IF_llc_mem_server_enqDst_0_lat_0_whas__123_THE_ETC___d2128, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4827,20 +4467,20 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__08_ETC___d2086 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2118 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__076_ETC___d2079 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__108_ETC___d2111 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h138482 : - line_addr__h148590 ; + line_addr__h140631 : + line_addr__h150742 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4923,7 +4563,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4936,11 +4576,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 && + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4950,11 +4590,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -5005,16 +4645,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h51199 : + newData__h53286 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -5023,7 +4663,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h43098 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h45185 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5033,9 +4673,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -5144,7 +4784,7 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = !mmioPlatform_toHostQ_clearReq_rl && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -5165,7 +4805,7 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = !mmioPlatform_toHostQ_clearReq_rl && - (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 || + (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl && mmioPlatform_toHostQ_full) ; @@ -5178,7 +4818,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5186,15 +4826,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5205,36 +4845,6 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_clearing - assign mmio_axi4_adapter_master_xactor_clearing$D_IN = 1'd0 ; - assign mmio_axi4_adapter_master_xactor_clearing$EN = - mmio_axi4_adapter_master_xactor_clearing ; - - // register mmio_axi4_adapter_master_xactor_shim_arff_rv - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_awff_rv - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_bff_rv - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_rff_rv - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_wff_rv - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_read_req_addr assign mmio_axi4_adapter_read_req_addr$D_IN = mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; @@ -5242,6 +4852,30 @@ module mkProc(CLK, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr ; + // register mmio_axi4_adapter_rg_rd_rsp_beat + assign mmio_axi4_adapter_rg_rd_rsp_beat$D_IN = + !mmio_axi4_adapter_master_shim_rff$D_OUT[1] && x__h10759 ; + assign mmio_axi4_adapter_rg_rd_rsp_beat$EN = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + + // register mmio_axi4_adapter_rg_wr_req_beat + assign mmio_axi4_adapter_rg_wr_req_beat$D_IN = + !whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + !mmio_axi4_adapter_rg_wr_req_beat && + x__h17973 ; + assign mmio_axi4_adapter_rg_wr_req_beat$EN = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + + // register mmio_axi4_adapter_rspData + assign mmio_axi4_adapter_rspData$D_IN = + mmio_axi4_adapter_master_shim_rff$D_OUT[1] ? + 129'd0 : + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 ; + assign mmio_axi4_adapter_rspData$EN = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + // register propDstData_0_rl assign propDstData_0_rl$D_IN = CAN_FIRE_RL_srcPropose ? @@ -5251,28 +4885,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1544, - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1549, + { IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1572, + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1577, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[517] : propDstData_1_0_rl[517], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516:1] : propDstData_1_0_rl[516:1], - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1570 } ; + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1598 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1582, - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1587, + { IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1610, + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1615, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[517] : propDstData_1_1_rl[517], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516:1] : propDstData_1_1_rl[516:1], - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1608 } ; + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1636 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5284,26 +4918,26 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = - !NOT_enqDst_0_rl_419_BIT_73_420_425_AND_SEL_ARR_ETC___d1513 && - IF_propDstIdx_0_lat_0_whas__387_THEN_propDstId_ETC___d1390 ; + !NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541 && + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = - !NOT_enqDst_1_0_rl_618_BIT_584_619_624_AND_SEL__ETC___d1814 && - IF_propDstIdx_1_0_lat_0_whas__524_THEN_propDst_ETC___d1527 ; + !NOT_enqDst_1_0_rl_646_BIT_584_647_652_AND_SEL__ETC___d1842 && + IF_propDstIdx_1_0_lat_0_whas__552_THEN_propDst_ETC___d1555 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__531_THEN_propDst_ETC___d1534 ; + IF_propDstIdx_1_1_lat_0_whas__559_THEN_propDst_ETC___d1562 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__394_THEN_propDstId_ETC___d1397 ; + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 @@ -5322,7 +4956,7 @@ module mkProc(CLK, assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq ? + WILL_FIRE_RL_sendPRs ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; assign core_0$hart0_csr_mem_server_request_put = @@ -5334,7 +4968,7 @@ module mkProc(CLK, assign core_0$hart0_run_halt_server_request_put = hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq_1 ? + WILL_FIRE_RL_sendPRs_1 ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or @@ -5422,7 +5056,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h186687, llc$dma_respLd_first[3] } ; + { ld_data__h188839, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5430,11 +5064,11 @@ module mkProc(CLK, assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ; assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ; assign core_0$EN_dCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ; + WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ; assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; + WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ; assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_llc_mem_server_srcPropose ; assign core_0$EN_tlbToMem_respLd_enq = @@ -5445,13 +5079,13 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp || WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 || + (!mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -5461,15 +5095,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_processFromHost ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 || + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5551,13 +5185,13 @@ module mkProc(CLK, enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1630, - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1635, - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1640, - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1650, - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1656 } ; + { IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1658, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1663, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1668, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1678, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1684 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_229_BIT_0_2_ETC___d2271, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_258_BIT_0_2_ETC___d2300, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5650,8 +5284,8 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; assign mmio_axi4_adapter_f_reqs_from_core$DEQ = + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St || - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ; @@ -5659,8 +5293,8 @@ module mkProc(CLK, always@(MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 or MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 or MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 or - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps or - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3) + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 or + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1: @@ -5668,10 +5302,10 @@ module mkProc(CLK, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1; MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2: mmio_axi4_adapter_f_rsps_to_core$D_IN = - 130'h200000000000000000000000000000000; - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps: + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3: mmio_axi4_adapter_f_rsps_to_core$D_IN = - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + 130'h200000000000000000000000000000000; default: mmio_axi4_adapter_f_rsps_to_core$D_IN = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -5680,16 +5314,69 @@ module mkProc(CLK, (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req) && !mmio_axi4_adapter_soc_map$m_is_IO_addr || + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_master_shim_rff$D_OUT[1] || WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0 || - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0 ; assign mmio_axi4_adapter_f_rsps_to_core$DEQ = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; assign mmio_axi4_adapter_f_rsps_to_core$CLR = 1'b0 ; + // submodule mmio_axi4_adapter_master_shim_arff + assign mmio_axi4_adapter_master_shim_arff$D_IN = + { 4'd0, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + mem_req_rd_addr_arlen__h5411, + 21'd851968 } ; + assign mmio_axi4_adapter_master_shim_arff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_shim_arff$DEQ = EN_master1_ar_drop ; + assign mmio_axi4_adapter_master_shim_arff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_awff + assign mmio_axi4_adapter_master_shim_awff$D_IN = + { 4'd0, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + mem_req_rd_addr_arlen__h5411, + _theResult_____1_awsize_val__h17178, + 18'd65536 } ; + assign mmio_axi4_adapter_master_shim_awff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 ; + assign mmio_axi4_adapter_master_shim_awff$DEQ = EN_master1_aw_drop ; + assign mmio_axi4_adapter_master_shim_awff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_bff + assign mmio_axi4_adapter_master_shim_bff$D_IN = master1_b_put_val ; + assign mmio_axi4_adapter_master_shim_bff$ENQ = EN_master1_b_put ; + assign mmio_axi4_adapter_master_shim_bff$DEQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ; + assign mmio_axi4_adapter_master_shim_bff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_rff + assign mmio_axi4_adapter_master_shim_rff$D_IN = master1_r_put_val ; + assign mmio_axi4_adapter_master_shim_rff$ENQ = EN_master1_r_put ; + assign mmio_axi4_adapter_master_shim_rff$DEQ = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + assign mmio_axi4_adapter_master_shim_rff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_wff + assign mmio_axi4_adapter_master_shim_wff$D_IN = + { wflit_wdata__h18041, + wflit_wstrb__h18042, + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat, + 1'd0 } ; + assign mmio_axi4_adapter_master_shim_wff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_shim_wff$DEQ = EN_master1_w_drop ; + assign mmio_axi4_adapter_master_shim_wff$CLR = 1'b0 ; + // submodule mmio_axi4_adapter_soc_map assign mmio_axi4_adapter_soc_map$m_is_IO_addr_addr = mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; @@ -5697,41 +5384,41 @@ module mkProc(CLK, assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current({ 65'd0, - value__h59417 }), + value__h61504 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d887)); - module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d915)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current({ 65'd0, - mmioPlatform_mtime__h57710 }), + mmioPlatform_mtime__h59797 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d973)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1001)); + module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current(129'd0), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d1043)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1071)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), - .amoExec_current({ 65'd0, x__h77269 }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), + .amoExec_current({ 65'd0, x__h79359 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d1099)); - module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h86411, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1127)); + module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88501, ((mmioPlatform_reqBE[0] ? 5'd1 : 5'd0) + @@ -5787,294 +5474,294 @@ module mkProc(CLK, .amoExec_wordIdx(mmioPlatform_curReq[3:2]), .amoExec_current(mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0]), .amoExec_inpt(mmioPlatform_reqData), - .amoExec(amoExec___d1328)); - assign IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929 = - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + .amoExec(amoExec___d1356)); + assign IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957 = + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1110 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - mmioPlatform_fromHostQ_data_0[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - mmioPlatform_fromHostQ_data_0[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - mmioPlatform_fromHostQ_data_0[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1115 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1110, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - mmioPlatform_fromHostQ_data_0[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - mmioPlatform_mtimecmp_0[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - mmioPlatform_mtimecmp_0[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - mmioPlatform_mtimecmp_0[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - mmioPlatform_mtimecmp_0[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : mmioPlatform_mtime[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : mmioPlatform_mtime[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : mmioPlatform_mtime[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : mmioPlatform_mtime[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513 = - (!core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) ? + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1138 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + mmioPlatform_fromHostQ_data_0[63:56], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + mmioPlatform_fromHostQ_data_0[55:48], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + mmioPlatform_fromHostQ_data_0[47:40], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + mmioPlatform_fromHostQ_data_0[39:32] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1143 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1138, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + mmioPlatform_fromHostQ_data_0[31:24], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + mmioPlatform_fromHostQ_data_0[23:16] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + mmioPlatform_mtimecmp_0[63:56], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + mmioPlatform_mtimecmp_0[55:48], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + mmioPlatform_mtimecmp_0[47:40], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + mmioPlatform_mtimecmp_0[39:32] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + mmioPlatform_mtimecmp_0[31:24], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + mmioPlatform_mtimecmp_0[23:16] } ; + assign IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541 = + (!core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) ? 67'h3AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511) ; - assign IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785 = + IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539) ; + assign IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 = - newData__h43098 <= mmioPlatform_mtime ; - assign IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511 = - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 ? + assign IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 = + newData__h45185 <= mmioPlatform_mtime ; + assign IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539 = + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 ? 67'h5AAAAAAAAAAAAAAAA : - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ? + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ; - assign IF_enqDst_0_lat_0_whas__416_THEN_enqDst_0_lat__ETC___d1421 = + assign IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449 = enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1620 = + assign IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1648 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[584] : enqDst_1_0_rl[584] ; - assign IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1630 = + assign IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1658 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[583:520] : enqDst_1_0_rl[583:520] ; - assign IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1635 = + assign IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1663 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[519:518] : enqDst_1_0_rl[519:518] ; - assign IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1640 = + assign IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1668 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[517] : enqDst_1_0_rl[517] ; - assign IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1650 = + assign IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1678 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[516:1] : enqDst_1_0_rl[516:1] ; - assign IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1656 = + assign IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1684 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__612_THEN_enqDst_1_0__ETC___d1658 = + assign IF_enqDst_1_0_lat_1_whas__640_THEN_enqDst_1_0__ETC___d1686 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1640, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1668, CAN_FIRE_RL_doEnq_1 ? 516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1650, - x__h114586 } ; - assign IF_enqDst_1_0_lat_1_whas__612_THEN_enqDst_1_0__ETC___d1659 = + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1678, + x__h116676 } ; + assign IF_enqDst_1_0_lat_1_whas__640_THEN_enqDst_1_0__ETC___d1687 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1630, + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1658, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1635, - IF_enqDst_1_0_lat_1_whas__612_THEN_enqDst_1_0__ETC___d1658 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_229_BIT_0_2_ETC___d2271 = + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1663, + IF_enqDst_1_0_lat_1_whas__640_THEN_enqDst_1_0__ETC___d1686 } ; + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_258_BIT_0_2_ETC___d2300 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2000 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2029 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd6) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd5) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd4) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[319:256], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd3) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd2) ? - data__h139049 : + data__h141198 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__091_THE_ETC___d2096 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__123_THE_ETC___d2128 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__08_ETC___d2086 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2118 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__076_ETC___d2079 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__108_ETC___d2111 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_fetchingWay_337_THEN_mmioPlatf_ETC___d1363 = + assign IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391 = mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358 ; - assign IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1129 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 ; + assign IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1157 = (mmioPlatform_fromHostQ_empty || mmioPlatform_fromHostAddr[0]) ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1127 = + assign IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1155 = mmioPlatform_fromHostQ_empty ? 64'd0 : (mmioPlatform_fromHostAddr[0] ? mmioPlatform_fromHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005 = - ((mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + assign IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033 = + ((mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872 = + assign IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 8'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqBE[15:8] : mmioPlatform_reqBE[7:0]) ; - assign IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 = + assign IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 64'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqData[127:64] : mmioPlatform_reqData[63:0]) ; - assign IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021 = + assign IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q7 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q8 } ; - assign IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 = + assign IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067, + { IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095, 1'd0, - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1134 = + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101 } ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1162 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1124, + { IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1152, 1'd0, - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1127, - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1129 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786 = + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1155, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1157 } ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022 = + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949 = + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067 = + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? mmioPlatform_toHostQ_empty : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1124 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1152 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h71630 == 64'd0 : - x__h66415 == 64'd0) : + x__h73720 == 64'd0 : + x__h68505 == 64'd0) : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1145 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1173 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h71630 != 64'd0 : - x__h66415 != 64'd0) : + x__h73720 != 64'd0 : + x__h68505 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; - assign IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073 = + assign IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101 = (mmioPlatform_toHostQ_empty || mmioPlatform_toHostAddr[0]) ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071 = + assign IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099 = mmioPlatform_toHostQ_empty ? 64'd0 : (mmioPlatform_toHostAddr[0] ? mmioPlatform_toHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 = + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850 = + assign IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6082,97 +5769,94 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__265_ETC___d1341 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 = + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? - !mmio_axi4_adapter_master_xactor_clearing && - !mmio_axi4_adapter_master_xactor_shim_awff_rv[97] && - !mmio_axi4_adapter_master_xactor_shim_wff_rv[74] : + mmio_axi4_adapter_master_shim_wff$FULL_N && + (!whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + mmio_axi4_adapter_rg_wr_req_beat || + mmio_axi4_adapter_master_shim_awff$FULL_N) : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 = - mmio_axi4_adapter_soc_map$m_is_IO_addr ? - !mmio_axi4_adapter_master_xactor_clearing && - !mmio_axi4_adapter_master_xactor_shim_arff_rv[97] : - mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1544 = + assign IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1572 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[583:520] : propDstData_1_0_rl[583:520] ; - assign IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1549 = + assign IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1577 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[519:518] : propDstData_1_0_rl[519:518] ; - assign IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1570 = + assign IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1598 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1582 = + assign IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1610 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[583:520] : propDstData_1_1_rl[583:520] ; - assign IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1587 = + assign IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1615 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[519:518] : propDstData_1_1_rl[519:518] ; - assign IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1608 = + assign IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1636 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstIdx_0_lat_0_whas__387_THEN_NOT_propD_ETC___d1453 = + assign IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 = !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign IF_propDstIdx_0_lat_0_whas__387_THEN_propDstId_ETC___d1390 = + assign IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__524_THEN_NOT_pro_ETC___d1690 = + assign IF_propDstIdx_1_0_lat_0_whas__552_THEN_NOT_pro_ETC___d1718 = !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__524_THEN_propDst_ETC___d1527 = + assign IF_propDstIdx_1_0_lat_0_whas__552_THEN_propDst_ETC___d1555 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__531_THEN_propDst_ETC___d1534 = + assign IF_propDstIdx_1_1_lat_0_whas__559_THEN_propDst_ETC___d1562 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__394_THEN_propDstId_ETC___d1397 = + assign IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_rl_419_BIT_73_420_425_AND_SEL_ARR_ETC___d1513 = + assign NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1455 && - (SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1451 ? + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 && + (SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 ? !srcRR_0 : - IF_propDstIdx_0_lat_0_whas__387_THEN_propDstId_ETC___d1390) ; - assign NOT_enqDst_0_rl_419_BIT_73_420_425_AND_SEL_ARR_ETC___d1518 = + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418) ; + assign NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1546 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1455 && - x__h98864 && + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 && + x__h100954 && !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; - assign NOT_enqDst_1_0_rl_618_BIT_584_619_624_AND_SEL__ETC___d1814 = + assign NOT_enqDst_1_0_rl_646_BIT_584_647_652_AND_SEL__ETC___d1842 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1692 && - (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1688 ? + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1720 && + (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1716 ? !srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__524_THEN_propDst_ETC___d1527) ; - assign NOT_enqDst_1_0_rl_618_BIT_584_619_624_AND_SEL__ETC___d1819 = + IF_propDstIdx_1_0_lat_0_whas__552_THEN_propDst_ETC___d1555) ; + assign NOT_enqDst_1_0_rl_646_BIT_584_647_652_AND_SEL__ETC___d1847 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1692 && - x__h121150 && + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1720 && + x__h123240 && !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2304 = - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2333 = + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2307 = - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2336 = + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1168 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1196 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6183,7 +5867,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1263 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1291 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6194,7 +5878,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1274 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1302 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6206,7 +5890,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1284 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1312 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6218,7 +5902,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1332 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1360 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6228,7 +5912,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1344 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1372 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6238,96 +5922,105 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 = + assign NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (!mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (!IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || !mmioPlatform_mtip_0) ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__401_THEN__ETC___d1506 = - { CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14, - x__h99064, - x__h99065 } ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__401_THEN__ETC___d1507 = - { CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15, - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16, - SEL_ARR_IF_propDstData_0_lat_0_whas__401_THEN__ETC___d1506 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1726 = - { CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1751 = - { CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1768 = - { CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1785 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1751, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1768, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1802 = - { CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1803 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1726, - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1785, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1802 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1808 = - { CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30, - !CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__539_THE_ETC___d1803, - x__h125885 } ; - assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1455 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1451 || - (IF_propDstIdx_0_lat_0_whas__387_THEN_NOT_propD_ETC___d1453 ? - IF_propDstIdx_1_lat_0_whas__394_THEN_propDstId_ETC___d1397 : - IF_propDstIdx_0_lat_0_whas__387_THEN_propDstId_ETC___d1390) ; - assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1692 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1688 || - (IF_propDstIdx_1_0_lat_0_whas__524_THEN_NOT_pro_ETC___d1690 ? - IF_propDstIdx_1_1_lat_0_whas__531_THEN_propDst_ETC___d1534 : - IF_propDstIdx_1_0_lat_0_whas__524_THEN_propDst_ETC___d1527) ; - assign _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 = - { 64'd0, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4] } << - (mmio_axi4_adapter_read_req_addr[3] ? 32'd64 : 32'd0) ; - assign addr1__h88641 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign amo_req_data__h36993 = + assign SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534 = + { CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + x__h101154, + x__h101155 } ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535 = + { CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1754 = + { CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1779 = + { CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1796 = + { CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1813 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1779, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1796, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1830 = + { CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1831 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1754, + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1813, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1830 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1836 = + { CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, + !CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__567_THE_ETC___d1831, + x__h127975 } ; + assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 || + (IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 ? + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 : + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418) ; + assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1720 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1716 || + (IF_propDstIdx_1_0_lat_0_whas__552_THEN_NOT_pro_ETC___d1718 ? + IF_propDstIdx_1_1_lat_0_whas__559_THEN_propDst_ETC___d1562 : + IF_propDstIdx_1_0_lat_0_whas__552_THEN_propDst_ETC___d1555) ; + assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat) ; + assign _theResult_____1_awsize_val__h17178 = + (x__h15205 + y__h15206 <= 5'd4) ? 3'b010 : 3'b011 ; + assign _theResult____h13554 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? + whichHalf___1__h15117 : + mmio_axi4_adapter_rg_wr_req_beat ; + assign addr1__h90731 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign amo_req_data__h39080 = (mmioPlatform_reqBE[3:0] == 4'd0 && mmioPlatform_reqBE[7:4] == 4'd0 && mmioPlatform_reqBE[11:8] == 4'd0 && @@ -6343,208 +6036,213 @@ module mkProc(CLK, ((mmioPlatform_reqBE[3:0] == 4'd0) ? mmioPlatform_reqData[63:32] : mmioPlatform_reqData[31:0]))) ; - assign b__h191767 = + assign b__h193959 = llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h4263 = + assign b__h2174 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554432 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556480 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_toHostAddr ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_fromHostAddr ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 ; + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ; + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ; - assign core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731 = + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ; + assign core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759 = core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497 ; - assign data__h139049 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525 ; + assign data__h141198 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952[7:0] } ; - assign failed_testnum__h222253 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981[7:0] } ; + assign failed_testnum__h224438 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h138482 = + assign line_addr__h140631 = { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h148590 = + assign line_addr__h150742 = { llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h191976 = { llc$to_mem_toM_first[68:11], 6'h0 } ; - assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37 = + assign line_addr__h194159 = { llc$to_mem_toM_first[68:11], 6'h0 } ; + assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34 = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35 = + assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2236 = + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2265 = llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || llc$RDY_to_mem_rsFromM_enq && llc_axi4_adapter_f_pending_reads$EMPTY_N) ; - assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36 = + assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2016 = - line_addr__h148590 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1917 = - line_addr__h138482 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33 = + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2047 = + line_addr__h150742 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1946 = + line_addr__h140631 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34 = + assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31 = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ; - assign lower_data__h42399 = - mmioPlatform_waitLowerMSIPCRs ? v__h42292 : 32'd0 ; - assign mmioPlatform_amoWaitWriteResp_278_OR_core_0_RD_ETC___d1281 = + assign lower_data__h44486 = + mmioPlatform_waitLowerMSIPCRs ? v__h44379 : 32'd0 ; + assign mem_req_rd_addr_arlen__h5411 = + (!whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? + 8'd1 : + 8'd0 ; + assign mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309 = mmioPlatform_amoWaitWriteResp || core_0$RDY_mmioToPlatform_pRs_enq && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) ; - assign mmioPlatform_cycle_57_ULT_99___d458 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346 = + assign mmioPlatform_cycle_85_ULT_99___d486 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h57710 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 = - mmioPlatform_mtimecmp_0 <= newData__h51199 ; - assign mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 = + assign mmioPlatform_mtime__h59797 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 = + mmioPlatform_mtimecmp_0 <= newData__h53286 ; + assign mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd0 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd1 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd2 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd3 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd4 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd5 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd6 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd7 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd8 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -6558,162 +6256,215 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_first[148:145] != 4'd6 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd7 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd8 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492 ; - assign mmioPlatform_reqAmofunc__h86411 = mmioPlatform_reqAmofunc ; - assign mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877 = + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520 ; + assign mmioPlatform_reqAmofunc__h88501 = mmioPlatform_reqAmofunc ; + assign mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905 = { mmioPlatform_reqFunc[3:0], - (IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0]) ? + (IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0]) ? 2'd1 : 2'd2, 2'd0 } ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (!mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (!IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || !mmioPlatform_mtip_0) ; - assign mmio_axi4_adapter_f_rsps_to_core_first__265_BI_ETC___d1366 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) && + mmio_axi4_adapter_cfg_verbosity != 4'd0 ; + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) && + mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15 ; + assign mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8 = + mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && + (mmio_axi4_adapter_soc_map$m_is_IO_addr ? + mmio_axi4_adapter_master_shim_arff$FULL_N : + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394 = { mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmioPlatform_fetchingWay, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - IF_mmioPlatform_fetchingWay_337_THEN_mmioPlatf_ETC___d1363 : + IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391 : mmioPlatform_fetchedInsts_0 } ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13 = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[96:0] ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11 = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[96:0] ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12 = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign newData__h43098 = + assign mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 = + mmio_axi4_adapter_read_req_addr[3] + + mmio_axi4_adapter_rg_rd_rsp_beat ; + assign mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 = + { mmio_axi4_adapter_rspData[128], + mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 ? + { mmio_axi4_adapter_master_shim_rff$D_OUT[67:4], + mmio_axi4_adapter_rspData[63:0] } : + { mmio_axi4_adapter_rspData[127:64], + mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; + assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 = + mmio_axi4_adapter_soc_map$m_is_IO_addr && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) ; + assign newData__h45185 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d887[63:0] : - x__h46411 ; - assign newData__h51199 = + amoExec___d915[63:0] : + x__h48498 ; + assign newData__h53286 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d973[63:0] : - x__h54489 ; - assign upper_data__h42400 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h42255 ; - assign v__h42255 = mmioPlatform_waitUpperMSIPCRs ? v__h42292 : 32'd0 ; - assign v__h42292 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign v_awaddr__h213467 = { llc$to_mem_toM_first[643:586], 6'h0 } ; - assign v_awsize_val__h15192 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:133] == 4'd0 || - mmio_axi4_adapter_f_reqs_from_core$D_OUT[132:129] == 4'd0) ? - 3'b010 : - 3'b011 ; - assign value__h59417 = mmioPlatform_mtimecmp_0 ; - assign x__h114586 = - !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__615_THEN_enqDst_1_0__ETC___d1656 ; - assign x__h121150 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1688 ? - srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__524_THEN_NOT_pro_ETC___d1690 ; - assign x__h46411 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_mtimecmp_0[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_mtimecmp_0[7:0] } ; - assign x__h54489 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_mtime[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_mtime[7:0] } ; - assign x__h62414 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - 8'd0 } ; - assign x__h66415 = - (mmioPlatform_reqFunc[5:4] != 2'd0 && - mmioPlatform_reqFunc[5:4] != 2'd1 && - mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1099[63:0] : - x__h69089 ; - assign x__h69089 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1115, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_fromHostQ_data_0[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_fromHostQ_data_0[7:0] } ; - assign x__h71630 = - (mmioPlatform_reqFunc[5:4] != 2'd0 && - mmioPlatform_reqFunc[5:4] != 2'd1 && - mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1043[63:0] : - x__h62414 ; - assign x__h77269 = mmioPlatform_fromHostQ_data_0 ; - assign x__h98864 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1451 ? + amoExec___d1001[63:0] : + x__h56576 ; + assign upper_data__h44487 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44342 ; + assign v__h44342 = mmioPlatform_waitUpperMSIPCRs ? v__h44379 : 32'd0 ; + assign v__h44379 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign v_awaddr__h215652 = { llc$to_mem_toM_first[643:586], 6'h0 } ; + assign value__h61504 = mmioPlatform_mtimecmp_0 ; + assign whichHalf___1__h15117 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; + assign x__h100954 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 ? srcRR_0 : - IF_propDstIdx_0_lat_0_whas__387_THEN_NOT_propD_ETC___d1453 ; - assign x_data__h39934 = { 31'd0, mmioPlatform_reqData[0] } ; + IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 ; + assign x__h10759 = mmio_axi4_adapter_rg_rd_rsp_beat + 1'd1 ; + assign x__h116676 = + !CAN_FIRE_RL_doEnq_1 && + IF_enqDst_1_0_lat_0_whas__643_THEN_enqDst_1_0__ETC___d1684 ; + assign x__h123240 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1716 ? + srcRR_1_0 : + IF_propDstIdx_1_0_lat_0_whas__552_THEN_NOT_pro_ETC___d1718 ; + assign x__h15205 = x__h15217 + y__h15218 ; + assign x__h15217 = x__h15229 + y__h15230 ; + assign x__h15229 = x__h15241 + y__h15242 ; + assign x__h15241 = x__h15253 + y__h15254 ; + assign x__h15253 = x__h15265 + y__h15266 ; + assign x__h15265 = x__h15277 + y__h15278 ; + assign x__h15277 = x__h15289 + y__h15290 ; + assign x__h15289 = x__h15301 + y__h15302 ; + assign x__h15301 = x__h15313 + y__h15314 ; + assign x__h15313 = x__h15325 + y__h15326 ; + assign x__h15325 = x__h15337 + y__h15338 ; + assign x__h15337 = x__h15349 + y__h15350 ; + assign x__h15349 = x__h15361 + y__h15362 ; + assign x__h15361 = x__h15373 + y__h15374 ; + assign x__h15373 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144] } ; + assign x__h17973 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; + assign x__h48498 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_mtimecmp_0[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_mtimecmp_0[7:0] } ; + assign x__h56576 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_mtime[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_mtime[7:0] } ; + assign x__h64504 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + 8'd0 } ; + assign x__h68505 = + (mmioPlatform_reqFunc[5:4] != 2'd0 && + mmioPlatform_reqFunc[5:4] != 2'd1 && + mmioPlatform_reqFunc[5:4] != 2'd2) ? + amoExec___d1127[63:0] : + x__h71179 ; + assign x__h71179 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1143, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_fromHostQ_data_0[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_fromHostQ_data_0[7:0] } ; + assign x__h73720 = + (mmioPlatform_reqFunc[5:4] != 2'd0 && + mmioPlatform_reqFunc[5:4] != 2'd1 && + mmioPlatform_reqFunc[5:4] != 2'd2) ? + amoExec___d1071[63:0] : + x__h64504 ; + assign x__h79359 = mmioPlatform_fromHostQ_data_0 ; + assign x_data__h42021 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h15206 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[129] } ; + assign y__h15218 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[130] } ; + assign y__h15230 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[131] } ; + assign y__h15242 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[132] } ; + assign y__h15254 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[133] } ; + assign y__h15266 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[134] } ; + assign y__h15278 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[135] } ; + assign y__h15290 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[136] } ; + assign y__h15302 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[137] } ; + assign y__h15314 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[138] } ; + assign y__h15326 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[139] } ; + assign y__h15338 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[140] } ; + assign y__h15350 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141] } ; + assign y__h15362 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[142] } ; + assign y__h15374 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[143] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h186687 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h186687 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h186687 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h186687 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h186687 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h186687 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h186687 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h186687 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h188839 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h188839 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h188839 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h188839 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h188839 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h188839 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h188839 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h188839 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) @@ -6768,49 +6519,71 @@ module mkProc(CLK, begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) 2'd0: - v_wdata__h213878 = + v_wdata__h216063 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1; 2'd1: - v_wdata__h213878 = + v_wdata__h216063 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2; 2'd2: - v_wdata__h213878 = + v_wdata__h216063 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3; 2'd3: - v_wdata__h213878 = + v_wdata__h216063 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: v_wstrb__h213879 = llc$to_mem_toM_first[523:516]; - 3'd1: v_wstrb__h213879 = llc$to_mem_toM_first[531:524]; - 3'd2: v_wstrb__h213879 = llc$to_mem_toM_first[539:532]; - 3'd3: v_wstrb__h213879 = llc$to_mem_toM_first[547:540]; - 3'd4: v_wstrb__h213879 = llc$to_mem_toM_first[555:548]; - 3'd5: v_wstrb__h213879 = llc$to_mem_toM_first[563:556]; - 3'd6: v_wstrb__h213879 = llc$to_mem_toM_first[571:564]; - 3'd7: v_wstrb__h213879 = llc$to_mem_toM_first[579:572]; + 3'd0: v_wstrb__h216064 = llc$to_mem_toM_first[523:516]; + 3'd1: v_wstrb__h216064 = llc$to_mem_toM_first[531:524]; + 3'd2: v_wstrb__h216064 = llc$to_mem_toM_first[539:532]; + 3'd3: v_wstrb__h216064 = llc$to_mem_toM_first[547:540]; + 3'd4: v_wstrb__h216064 = llc$to_mem_toM_first[555:548]; + 3'd5: v_wstrb__h216064 = llc$to_mem_toM_first[563:556]; + 3'd6: v_wstrb__h216064 = llc$to_mem_toM_first[571:564]; + 3'd7: v_wstrb__h216064 = llc$to_mem_toM_first[579:572]; + endcase + end + always@(_theResult____h13554 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) + begin + case (_theResult____h13554) + 1'd0: + wflit_wdata__h18041 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]; + 1'd1: + wflit_wdata__h18041 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64]; + endcase + end + always@(_theResult____h13554 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) + begin + case (_theResult____h13554) + 1'd0: + wflit_wstrb__h18042 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129]; + 1'd1: + wflit_wstrb__h18042 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) - 2'd0: v_wuser__h213881 = llc$to_mem_toM_first[512]; - 2'd1: v_wuser__h213881 = llc$to_mem_toM_first[513]; - 2'd2: v_wuser__h213881 = llc$to_mem_toM_first[514]; - 2'd3: v_wuser__h213881 = llc$to_mem_toM_first[515]; + 2'd0: v_wuser__h216066 = llc$to_mem_toM_first[512]; + 2'd1: v_wuser__h216066 = llc$to_mem_toM_first[513]; + 2'd2: v_wuser__h216066 = llc$to_mem_toM_first[514]; + 2'd3: v_wuser__h216066 = llc$to_mem_toM_first[515]; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811 = + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811 = + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6818,21 +6591,21 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 2'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 2'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; 2'd2: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64]; 2'd3: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929 or + IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6840,11 +6613,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = - IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929; + IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005 or + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6852,452 +6625,452 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005; + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033; endcase end always@(srcRR_0 or - IF_propDstIdx_0_lat_0_whas__387_THEN_propDstId_ETC___d1390 or - IF_propDstIdx_1_lat_0_whas__394_THEN_propDstId_ETC___d1397) + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 or + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425) begin case (srcRR_0) 1'd0: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1451 = - IF_propDstIdx_0_lat_0_whas__387_THEN_propDstId_ETC___d1390; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 = + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418; 1'd1: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__387_THEN_p_ETC___d1451 = - IF_propDstIdx_1_lat_0_whas__394_THEN_propDstId_ETC___d1397; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 = + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425; endcase end always@(srcRR_1_0 or - IF_propDstIdx_1_0_lat_0_whas__524_THEN_propDst_ETC___d1527 or - IF_propDstIdx_1_1_lat_0_whas__531_THEN_propDst_ETC___d1534) + IF_propDstIdx_1_0_lat_0_whas__552_THEN_propDst_ETC___d1555 or + IF_propDstIdx_1_1_lat_0_whas__559_THEN_propDst_ETC___d1562) begin case (srcRR_1_0) 1'd0: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1688 = - IF_propDstIdx_1_0_lat_0_whas__524_THEN_propDst_ETC___d1527; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1716 = + IF_propDstIdx_1_0_lat_0_whas__552_THEN_propDst_ETC___d1555; 1'd1: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__524_THEN_ETC___d1688 = - IF_propDstIdx_1_1_lat_0_whas__531_THEN_propDst_ETC___d1534; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__552_THEN_ETC___d1716 = + IF_propDstIdx_1_1_lat_0_whas__559_THEN_propDst_ETC___d1562; endcase end - always@(x__h98864 or + always@(x__h100954 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98864) + case (x__h100954) 1'd0: - x__h99064 = + x__h101154 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]; 1'd1: - x__h99064 = + x__h101154 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]; endcase end - always@(x__h98864 or + always@(x__h100954 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98864) + case (x__h100954) 1'd0: - x__h99065 = + x__h101155 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]; 1'd1: - x__h99065 = + x__h101155 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]; endcase end - always@(x__h98864 or + always@(x__h100954 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98864) + case (x__h100954) 1'd0: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]; 1'd1: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]; endcase end - always@(x__h98864 or + always@(x__h100954 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98864) + case (x__h100954) 1'd0: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]; 1'd1: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]; endcase end - always@(x__h98864 or + always@(x__h100954 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98864) + case (x__h100954) 1'd0: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]; 1'd1: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]; endcase end - always@(x__h98864 or + always@(x__h100954 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98864) + case (x__h100954) 1'd0: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]; 1'd1: - CASE_x8864_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17 = + CASE_x00954_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]; endcase end - always@(x__h121150 or - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1570 or - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1608) + always@(x__h123240 or + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1598 or + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1636) begin - case (x__h121150) + case (x__h123240) 1'd0: - x__h125885 = - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1570; + x__h127975 = + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1598; 1'd1: - x__h125885 = - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1608; + x__h127975 = + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1636; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516] : propDstData_1_0_rl[516]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516] : propDstData_1_1_rl[516]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515] : propDstData_1_0_rl[515]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515] : propDstData_1_1_rl[515]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[514] : propDstData_1_0_rl[514]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[514] : propDstData_1_1_rl[514]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513]; endcase end - always@(x__h121150 or - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1549 or - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1587) + always@(x__h123240 or + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1577 or + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1615) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30 = - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1549; + CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1577; 1'd1: - CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30 = - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1587; + CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1615; endcase end - always@(x__h121150 or + always@(x__h123240 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[517] : !propDstData_1_0_rl[517]; 1'd1: - CASE_x21150_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31 = + CASE_x23240_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[517] : !propDstData_1_1_rl[517]; endcase end - always@(x__h121150 or - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1544 or - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1582) + always@(x__h123240 or + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1572 or + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1610) begin - case (x__h121150) + case (x__h123240) 1'd0: - CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32 = - IF_propDstData_1_0_lat_0_whas__539_THEN_propDs_ETC___d1544; + CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_0_lat_0_whas__567_THEN_propDs_ETC___d1572; 1'd1: - CASE_x21150_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32 = - IF_propDstData_1_1_lat_0_whas__577_THEN_propDs_ETC___d1582; + CASE_x23240_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_1_lat_0_whas__605_THEN_propDs_ETC___d1610; endcase end always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or @@ -7305,28 +7078,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1952 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1981 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7334,14 +7107,14 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32]) - 3'd0: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h148773 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h150925 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7369,7 +7142,6 @@ module mkProc(CLK, 74'h0AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY 75'h2AAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_mem_server_axi4_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY @@ -7414,21 +7186,12 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY - 1'd0; - mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY - 7'd42; - mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY - 73'h0AAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY - 75'h2AAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmio_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmio_axi4_adapter_rspData <= `BSV_ASSIGNMENT_DELAY 129'd0; propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7474,9 +7237,6 @@ module mkProc(CLK, if (llc_axi4_adapter_master_xactor_shim_wff_rv$EN) llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN; - if (llc_axi4_adapter_rg_rd_req_beat$EN) - llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_rg_rd_req_beat$D_IN; if (llc_axi4_adapter_rg_rd_rsp_beat$EN) llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_rd_rsp_beat$D_IN; @@ -7579,24 +7339,15 @@ module mkProc(CLK, if (mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN) mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; - if (mmio_axi4_adapter_master_xactor_clearing$EN) - mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_clearing$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_arff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_awff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_bff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_rff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_wff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; + if (mmio_axi4_adapter_rg_rd_rsp_beat$EN) + mmio_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rg_rd_rsp_beat$D_IN; + if (mmio_axi4_adapter_rg_wr_req_beat$EN) + mmio_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rg_wr_req_beat$D_IN; + if (mmio_axi4_adapter_rspData$EN) + mmio_axi4_adapter_rspData <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rspData$D_IN; if (propDstData_0_rl$EN) propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN; if (propDstData_1_0_rl$EN) @@ -7683,7 +7434,6 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_rg_cline = 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_rg_rd_req_beat = 3'h2; llc_axi4_adapter_rg_rd_rsp_beat = 3'h2; llc_axi4_adapter_rg_wr_req_beat = 3'h2; llc_mem_server_axi4_slave_xactor_clearing = 1'h0; @@ -7737,15 +7487,10 @@ module mkProc(CLK, mmioPlatform_waitUpperMSIPCRs = 1'h0; mmio_axi4_adapter_cfg_verbosity = 4'hA; mmio_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA; - mmio_axi4_adapter_master_xactor_clearing = 1'h0; - mmio_axi4_adapter_master_xactor_shim_arff_rv = - 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_awff_rv = - 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_bff_rv = 7'h2A; - mmio_axi4_adapter_master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; mmio_axi4_adapter_read_req_addr = 64'hAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_rg_rd_rsp_beat = 1'h0; + mmio_axi4_adapter_rg_wr_req_beat = 1'h0; + mmio_axi4_adapter_rspData = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl = 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7771,30 +7516,30 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h222673 = $stime; + v__h224843 = $stime; #0; end - v__h222667 = v__h222673 / 32'd10; + v__h224837 = v__h224843 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h222667, + v__h224837, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_rl_419_BIT_73_420_425_AND_SEL_ARR_ETC___d1513 && - IF_propDstIdx_0_lat_0_whas__387_THEN_NOT_propD_ETC___d1453) + if (NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541 && + IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_rl_419_BIT_73_420_425_AND_SEL_ARR_ETC___d1518) + if (NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1546) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_rl_618_BIT_584_619_624_AND_SEL__ETC___d1814 && - IF_propDstIdx_1_0_lat_0_whas__524_THEN_NOT_pro_ETC___d1690) + if (NOT_enqDst_1_0_rl_646_BIT_584_647_652_AND_SEL__ETC___d1842 && + IF_propDstIdx_1_0_lat_0_whas__552_THEN_NOT_pro_ETC___d1718) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_rl_618_BIT_584_619_624_AND_SEL__ETC___d1819) + if (NOT_enqDst_1_0_rl_646_BIT_584_647_652_AND_SEL__ETC___d1847) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (core_0$RDY_coreIndInv_terminate) @@ -7802,14 +7547,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h222210 = $stime; + v__h224395 = $stime; #0; end - v__h222204 = v__h222210 / 32'd10; + v__h224389 = v__h224395 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h222204, + v__h224389, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7819,22 +7564,280 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h222253); + $display("FAIL %0d", failed_testnum__h224438); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h11342 = $stime; + v__h9702 = $stime; #0; end - v__h11336 = v__h11342 / 32'd10; + v__h9696 = v__h9702 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_handle_read_rsps ", v__h9696); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[71:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd1 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + begin + v__h9897 = $stime; + #0; + end + v__h9891 = v__h9897 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $display("%0d: %m.rl_handle_read_rsp: fabric response error", + v__h9891); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[71:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd1 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + !mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" Response MMIO to core: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("MMIODataPRs { ", "valid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_rspData[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_rspData[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h11336); + begin + v__h11307 = $stime; + #0; + end + v__h11301 = v__h11307 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%d: %m.rl_handle_write_req: St request:", v__h11301); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8156,37 +8159,259 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) begin - v__h15880 = $stime; + v__h17239 = $stime; #0; end - v__h15874 = v__h15880 / 32'd10; + v__h17233 = v__h17239 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h15874); + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $display("%d: %m.rl_handle_write_req: sent aw flit:", v__h17233); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", mem_req_rd_addr_arlen__h5411); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", _theResult_____1_awsize_val__h17178, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) + begin + v__h17410 = $stime; + #0; + end + v__h17404 = v__h17410 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) + $display("%0d: ERROR: CreditCounter: overflow", v__h17404); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + begin + v__h18103 = $stime; + #0; + end + v__h18097 = v__h18103 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%d: %m.rl_handle_write_req: sent w flit:", v__h18097); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", wflit_wdata__h18041); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", wflit_wstrb__h18042); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + !mmio_axi4_adapter_rg_wr_req_beat) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat)) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("first: %d, last: %d, whichHalf: %d", + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat, + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat, + _theResult____h13554, + "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h16023 = $stime; + v__h18189 = $stime; #0; end - v__h16017 = v__h16023 / 32'd10; + v__h18183 = v__h18189 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h16017); + v__h18183); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8580,14 +8805,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4363 = $stime; + v__h2280 = $stime; #0; end - v__h4357 = v__h4363 / 32'd10; + v__h2274 = v__h2280 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h4357); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2274); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8940,7 +9165,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 8'd0); + $write("'h%h", mem_req_rd_addr_arlen__h5411); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9036,16 +9261,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h7984 = $stime; + v__h7388 = $stime; #0; end - v__h7978 = v__h7984 / 32'd10; + v__h7382 = v__h7388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h7978); + v__h7382); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9436,16 +9661,137 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h19409 = $stime; + v__h20501 = $stime; #0; end - v__h19403 = v__h19409 / 32'd10; + v__h20495 = v__h20501 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_discard_write_rsp", v__h20495); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_bff$D_OUT[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd1 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + begin + v__h21031 = $stime; + #0; + end + v__h21025 = v__h21031 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", + v__h21025); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_bff$D_OUT[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd1 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) + begin + v__h21496 = $stime; + #0; + end + v__h21490 = v__h21496 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h19403); + v__h21490); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9735,572 +10081,130 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - begin - v__h18412 = $stime; - #0; - end - v__h18406 = v__h18412 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h18406); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_BFlit { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0) - $write("OKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - begin - v__h18942 = $stime; - #0; - end - v__h18936 = v__h18942 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h18936); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("AXI4_BFlit { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - begin - v__h10403 = $stime; - #0; - end - v__h10397 = v__h10403 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h10397); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_RFlit { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0) - $write("OKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - begin - v__h10598 = $stime; - #0; - end - v__h10592 = v__h10598 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h10592); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("AXI4_RFlit { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" Response MMIO to core: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("MMIODataPRs { ", "valid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("TaggedData { ", "tag: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write("[Platform - SelectReq] timer interrupt", ", mtime %x", mmioPlatform_mtime, ", mtimcmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(", old mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(", new interrupts "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("[Platform - SelectReq] core %d, req ", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write("tagged Inst ", "'h%h", core_0$mmioToPlatform_cRq_first[145]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write("tagged Ld ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write("tagged St ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -10309,542 +10213,542 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579) $write("Swap"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585) $write("Add"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591) $write("Xor"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597) $write("And"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603) $write("Or"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609) $write("Min"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615) $write("Max"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621) $write("Minu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627) $write("Maxu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649) $write("None"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("TaggedData { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[128]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && !core_0$mmioToPlatform_cRq_first[128]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" req type "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755) $write("tagged MSIP ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && - core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731) + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && + core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759) $write("tagged MTimeCmp ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736) + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764) $write("tagged MTime ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742) + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770) $write("tagged ToHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748) + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776) $write("tagged FromHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755) + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783) $write("tagged MMIO_Fabric_Adapter ", "'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) @@ -10907,8 +10811,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h42399, - upper_data__h42400); + lower_data__h44486, + upper_data__h44487); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -10920,62 +10824,62 @@ module mkProc(CLK, mmioPlatform_mtimecmp_0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write("[Platform - process mtimecmp] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(", mtime %x", mmioPlatform_mtime, ", old mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h43098, "\n"); + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) + $write(", new mtimecmp[%d] %x", 1'd0, newData__h45185, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -11020,61 +10924,61 @@ module mkProc(CLK, mmioPlatform_mtime); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write("[Platform - process mtime] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) - $write(", new mtime %x", newData__h51199, ", mtimecmp "); + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) + $write(", new mtime %x", newData__h53286, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeDone) @@ -11142,7 +11046,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11168,13 +11072,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11204,13 +11108,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h71630 != 64'd0) + x__h73720 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h66415 != 64'd0) + x__h68505 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11229,12 +11133,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1145) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1173) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1124) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1152) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11260,13 +11164,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1129, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1157, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1127, + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1155, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11761,7 +11665,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", addr1__h88641); + $write("'h%h", addr1__h90731); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -11846,76 +11750,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346) + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346) + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display(" fetchingWay %0d instSel %0d inst 0x%0h", mmioPlatform_fetchingWay, mmioPlatform_instSel, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1358); + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp: final resp to core:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_337_ULT_mmioPlatform__ETC___d1346) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && @@ -11965,7 +11869,7 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (!llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__076_ETC___d2079 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__108_ETC___d2111 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -11973,35 +11877,35 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h199861 = $stime; + v__h202046 = $stime; #0; end - v__h199855 = v__h199861 / 32'd10; + v__h202040 = v__h202046 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h199855); + v__h202040); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -13458,15 +13362,15 @@ module mkProc(CLK, llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h213570 = $stime; + v__h215755 = $stime; #0; end - v__h213564 = v__h213570 / 32'd10; + v__h215749 = v__h215755 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h213564); + $display("%0d: ERROR: CreditCounter: overflow", v__h215749); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && @@ -13474,209 +13378,193 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h191840 = $stime; + v__h194023 = $stime; #0; end - v__h191834 = v__h191840 / 32'd10; + v__h194017 = v__h194023 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) - $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h191834, - llc_axi4_adapter_rg_rd_req_beat); + llc_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory", + v__h194017); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("LdMemRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", llc$to_mem_toM_first[68:5]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0 && llc$to_mem_toM_first[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0 && !llc$to_mem_toM_first[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", llc$to_mem_toM_first[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) - $write("'h%h", line_addr__h191976); + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) + $write("'h%h", line_addr__h194159); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) begin - v__h221196 = $stime; + v__h223381 = $stime; #0; end - v__h221190 = v__h221196 / 32'd10; + v__h223375 = v__h223381 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h221190); + v__h223375); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) @@ -13727,69 +13615,69 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) begin - v__h192429 = $stime; + v__h194612 = $stime; #0; end - v__h192423 = v__h192429 / 32'd10; + v__h194606 = v__h194612 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h192423, + v__h194606, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13798,45 +13686,45 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) begin - v__h192615 = $stime; + v__h194798 = $stime; #0; end - v__h192609 = v__h192615 / 32'd10; + v__h194792 = v__h194798 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h192609); + v__h194792); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) @@ -13916,27 +13804,27 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225 && + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__207_U_ETC___d2225) + NOT_llc_axi4_adapter_cfg_verbosity_read__239_U_ETC___d2254) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v index caec9c9..38bc258 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:24:51 BST 2020 +// On Wed Jun 24 20:14:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRas.v b/src_SSITH_P3/Verilog_RTL_sim/mkRas.v index 54b69a8..976bcfb 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:26:00 BST 2020 +// On Wed Jun 24 20:15:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v index 51eccf4..eccb803 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:22:17 BST 2020 +// On Wed Jun 24 20:11:32 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v index f32ea45..203e2cd 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:25:35 BST 2020 +// On Wed Jun 24 20:14:51 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v index ed9ba95..d5f3950 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:51 BST 2020 +// On Wed Jun 24 20:20:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v index 0a7478d..2bca4a7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:25:49 BST 2020 +// On Wed Jun 24 20:15:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v index dc41f07..aad18ed 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:25:45 BST 2020 +// On Wed Jun 24 20:15:01 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v index e81daa7..f87e37d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:25:02 BST 2020 +// On Wed Jun 24 20:14:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v index 45dd97b..5f97ebe 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:27:31 BST 2020 +// On Wed Jun 24 20:16:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v index 79b4eb7..07ad4b4 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:27:24 BST 2020 +// On Wed Jun 24 20:16:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v index b522ac5..e603d3c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:08 BST 2020 +// On Wed Jun 24 20:19:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v b/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v index 9b7d879..56b0381 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:44 BST 2020 +// On Wed Jun 24 20:09:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v index 945aae7..58af34b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:24:42 BST 2020 +// On Wed Jun 24 20:13:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v index 1a0d7ef..28c4f12 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:26:50 BST 2020 +// On Wed Jun 24 20:16:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v index ee72bd1..ee673de 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:19 BST 2020 +// On Wed Jun 24 20:10:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v index cad23d3..5b0a4bf 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:48 BST 2020 +// On Wed Jun 24 20:11:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v index 3f7b944..b615a98 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:57 BST 2020 +// On Wed Jun 24 20:18:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v b/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v index 38cda59..3de176f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:28:57 BST 2020 +// On Wed Jun 24 20:18:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v b/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v index 51c74da..5dd6ffa 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:13 BST 2020 +// On Wed Jun 24 20:20:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v index 641db57..c153d64 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:20 BST 2020 +// On Wed Jun 24 20:20:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v index d263d7f..4e4ff0e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:20 BST 2020 +// On Wed Jun 24 20:20:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v index f21442c..706ed1c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:31:21 BST 2020 +// On Wed Jun 24 20:20:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v index ab48192..8da4f6b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v index 17e0bb3..3a56d47 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v index 51e25ff..2f09d8d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v index 55923a7..cffbd64 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v index cc5f4ab..9e50327 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v index bd7e10b..4070a0a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v index 4939ce5..d0b3f73 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v index 7b36523..eb7438d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v index 6930424..386fe8b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:29:55 BST 2020 +// On Wed Jun 24 20:19:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_alu.v b/src_SSITH_P3/Verilog_RTL_sim/module_alu.v index f08f243..846d2d6 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:04 BST 2020 +// On Wed Jun 24 20:10:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v b/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v index 578c677..5dacda3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:06 BST 2020 +// On Wed Jun 24 20:10:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v b/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v index d4fe42a..0ebd002 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:20:42 BST 2020 +// On Wed Jun 24 20:09:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v b/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v index 818f009..38451cb 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:07 BST 2020 +// On Wed Jun 24 20:10:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v index f81474e..dffd84b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:06 BST 2020 +// On Wed Jun 24 20:10:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v b/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v index 4e0100e..9ea893d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:03 BST 2020 +// On Wed Jun 24 20:10:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v b/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v index c40fbeb..7c757b0 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:06 BST 2020 +// On Wed Jun 24 20:10:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v b/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v index 036f996..ee975cf 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:06 BST 2020 +// On Wed Jun 24 20:10:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v b/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v index 3729451..374f28a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:08 BST 2020 +// On Wed Jun 24 20:10:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_decode.v b/src_SSITH_P3/Verilog_RTL_sim/module_decode.v index 72cb737..149c600 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:25:56 BST 2020 +// On Wed Jun 24 20:15:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v index 8dcb925..d83de1d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:25:52 BST 2020 +// On Wed Jun 24 20:15:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v index b167915..0227e0b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:30:14 BST 2020 +// On Wed Jun 24 20:19:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v b/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v index 9610034..c782b0a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:04 BST 2020 +// On Wed Jun 24 20:10:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v b/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v index 78e6e43..f883627 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:04 BST 2020 +// On Wed Jun 24 20:10:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v b/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v index 1fd3d4b..b0287ba 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:21:06 BST 2020 +// On Wed Jun 24 20:10:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v index 6a2c0a8..3284345 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:37 BST 2020 +// On Wed Jun 24 20:34:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v index 1b9f972..1e0fd92 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:38 BST 2020 +// On Wed Jun 24 20:34:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v index 1399351..65d65b0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:38 BST 2020 +// On Wed Jun 24 20:34:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v index a4c9ef0..2e6dc57 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 64579cd..546290c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:46:40 BST 2020 +// On Wed Jun 24 20:35:56 BST 2020 // // // Ports: @@ -3543,7 +3543,7 @@ module mkCore(CLK, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, MUX_regRenamingTable$rename_0_getRename_1__VAL_3; - wire [13 : 0] MUX_rob$setExecuted_deqLSQ_2__VAL_3, + wire [13 : 0] MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6; wire [10 : 0] MUX_csrf_mccsr_reg$write_1__VAL_1, MUX_csrf_mccsr_reg$write_1__VAL_2; @@ -3691,7 +3691,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, MUX_rg_core_run_state$write_1__SEL_4, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, @@ -3701,17 +3701,17 @@ module mkCore(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h213381; - reg [63 : 0] v__h215650; - reg [63 : 0] v__h271867; - reg [63 : 0] v__h347385; - reg [63 : 0] v__h423711; + reg [63 : 0] v__h213380; + reg [63 : 0] v__h215649; + reg [63 : 0] v__h271864; + reg [63 : 0] v__h347382; + reg [63 : 0] v__h423708; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5470; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873; - reg [65 : 0] thin_address__h857274, thin_address__h896908; + reg [65 : 0] thin_address__h857271, thin_address__h896904; reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q363, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q364, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q290, @@ -3750,33 +3750,33 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151, - addr__h505543, - addr__h843840, - addr__h886249, - data_out__h1014871, - trap_val__h994359, - x__h264659; + addr__h505540, + addr__h843837, + addr__h886245, + data_out__h1014865, + trap_val__h994354, + x__h264656; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232, - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233, - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234, - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235, - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236, - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237, - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226, - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227, - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228, - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229, - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230, - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231, - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216, - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217, - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218, - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219, - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220, - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221, + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232, + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233, + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234, + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235, + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236, + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237, + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226, + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227, + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228, + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229, + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230, + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231, + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216, + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217, + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218, + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219, + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220, + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298, @@ -3790,7 +3790,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17090; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040, - x__h264814; + x__h264811; reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q346, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_816_ETC__q285, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q340, @@ -3801,56 +3801,56 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q362, IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d20175, IF_fetchStage_pipelines_1_first__0058_BITS_267_ETC___d21125; - reg [22 : 0] CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64, - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65, - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95, - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96, - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93, - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94, - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97, - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98, - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100, - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99, - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130, - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131, - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60, - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61, - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128, - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129, - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58, - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59, - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132, - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133, - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62, - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63, - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134, - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135, - _theResult___fst_sfd__h576364, - _theResult___fst_sfd__h585087, - _theResult___fst_sfd__h593669, - _theResult___fst_sfd__h602853, - _theResult___fst_sfd__h611489, - _theResult___fst_sfd__h622115, - _theResult___fst_sfd__h630836, - _theResult___fst_sfd__h639418, - _theResult___fst_sfd__h648602, - _theResult___fst_sfd__h657238, - _theResult___fst_sfd__h667862, - _theResult___fst_sfd__h676583, - _theResult___fst_sfd__h685165, - _theResult___fst_sfd__h694349, - _theResult___fst_sfd__h702985; - reg [17 : 0] thin_otype__h857279, thin_otype__h896913; + reg [22 : 0] CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64, + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65, + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95, + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96, + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93, + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94, + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97, + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98, + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100, + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99, + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130, + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131, + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60, + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61, + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128, + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129, + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58, + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59, + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132, + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133, + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62, + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63, + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134, + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135, + _theResult___fst_sfd__h576361, + _theResult___fst_sfd__h585084, + _theResult___fst_sfd__h593666, + _theResult___fst_sfd__h602850, + _theResult___fst_sfd__h611486, + _theResult___fst_sfd__h622112, + _theResult___fst_sfd__h630833, + _theResult___fst_sfd__h639415, + _theResult___fst_sfd__h648599, + _theResult___fst_sfd__h657235, + _theResult___fst_sfd__h667859, + _theResult___fst_sfd__h676580, + _theResult___fst_sfd__h685162, + _theResult___fst_sfd__h694346, + _theResult___fst_sfd__h702982; + reg [17 : 0] thin_otype__h857276, thin_otype__h896909; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052; - reg [13 : 0] thin_addrBits__h857275, - thin_addrBits__h896909, - thin_bounds_baseBits__h859273, - thin_bounds_baseBits__h898315, - thin_bounds_topBits__h859272, - thin_bounds_topBits__h898314; - reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337, + reg [13 : 0] thin_addrBits__h857272, + thin_addrBits__h896905, + thin_bounds_baseBits__h859270, + thin_bounds_baseBits__h898311, + thin_bounds_topBits__h859269, + thin_bounds_topBits__h898310; + reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337, + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323; reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q348, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q287, @@ -3871,24 +3871,24 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_fetchStagepipelines_0_first_BITS_237_TO__ETC__q255, CASE_fetchStagepipelines_1_first_BITS_237_TO__ETC__q263, - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171, - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172, - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198, - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199, - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202, - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203, - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154, - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155, - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222, - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223, - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224, - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225, - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194, - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195, - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196, - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197, - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200, - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201, + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171, + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172, + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198, + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199, + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202, + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203, + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154, + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155, + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222, + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223, + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224, + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225, + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194, + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195, + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196, + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197, + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200, + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226, @@ -3898,47 +3898,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706; - reg [7 : 0] CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56, - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57, - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80, - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81, - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78, - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79, - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86, - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87, - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91, - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92, - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115, - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116, - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45, - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46, - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113, - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114, - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43, - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44, - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121, - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122, - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51, - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52, - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126, - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127, + reg [7 : 0] CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56, + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57, + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80, + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81, + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78, + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79, + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86, + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87, + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91, + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92, + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115, + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116, + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45, + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46, + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113, + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114, + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43, + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44, + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121, + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122, + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51, + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52, + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126, + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073, - _theResult___fst_exp__h576363, - _theResult___fst_exp__h585086, - _theResult___fst_exp__h593668, - _theResult___fst_exp__h602852, - _theResult___fst_exp__h611488, - _theResult___fst_exp__h622114, - _theResult___fst_exp__h630835, - _theResult___fst_exp__h639417, - _theResult___fst_exp__h648601, - _theResult___fst_exp__h657237, - _theResult___fst_exp__h667861, - _theResult___fst_exp__h676582, - _theResult___fst_exp__h685164, - _theResult___fst_exp__h694348, - _theResult___fst_exp__h702984; + _theResult___fst_exp__h576360, + _theResult___fst_exp__h585083, + _theResult___fst_exp__h593665, + _theResult___fst_exp__h602849, + _theResult___fst_exp__h611485, + _theResult___fst_exp__h622111, + _theResult___fst_exp__h630832, + _theResult___fst_exp__h639414, + _theResult___fst_exp__h648598, + _theResult___fst_exp__h657234, + _theResult___fst_exp__h667858, + _theResult___fst_exp__h676579, + _theResult___fst_exp__h685161, + _theResult___fst_exp__h694345, + _theResult___fst_exp__h702981; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q338, CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q329, @@ -3954,10 +3954,10 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q360, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q283, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332, CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23, CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q327, CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q252, @@ -3967,10 +3967,10 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_95_TO_3226_BIT_ETC__q328, IF_fetchStage_pipelines_0_first__0049_BITS_264_ETC___d21816, IF_fetchStage_pipelines_1_first__0058_BITS_264_ETC___d21961, - cause_code__h992792, - i__h992808, - t__h212809, - t__h215095; + cause_code__h992787, + i__h992803, + t__h212808, + t__h215094; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__820_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9261_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q245, @@ -3980,8 +3980,8 @@ module mkCore(CLK, CASE_IF_fetchStage_pipelines_0_first__0049_BIT_ETC__q251, CASE_IF_fetchStage_pipelines_1_first__0058_BIT_ETC__q260, CASE_checkForException_0436_BITS_4_TO_0_0_0_1__ETC__q257, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330, CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q320, IF_checkForException_0436_BITS_3_TO_0_0689_EQ__ETC___d20709, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18344, @@ -3996,9 +3996,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0058_BITS_235_ETC___d21151, IF_fetchStage_pipelines_1_first__0058_BITS_264_ETC___d21962, IF_rob_deqPort_0_deq_data__2032_BIT_294_3037_T_ETC___d23059, - i__h992982, - thin_perms_soft__h857526, - thin_perms_soft__h897088; + i__h992977, + thin_perms_soft__h857523, + thin_perms_soft__h897084; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__820_ETC__q246, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9261_ETC__q248, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__7_ETC__q244, @@ -4028,15 +4028,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850, IF_fetchStage_pipelines_0_first__0049_BITS_231_ETC___d20230, IF_fetchStage_pipelines_1_first__0058_BITS_231_ETC___d21180, - x__h501025, - x__h508693; + x__h501022, + x__h508690; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q367, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - thin_reserved__h857278, - thin_reserved__h896912; + thin_reserved__h857275, + thin_reserved__h896908; reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161, @@ -4077,46 +4077,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q266, CASE_fetchStagepipelines_1_first_BITS_264_TO__ETC__q270, CASE_fetchStagepipelines_1_first_BITS_267_TO__ETC__q272, - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73, - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72, - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181, - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175, - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179, - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173, - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102, - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101, - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183, - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177, - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104, - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103, - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106, - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105, - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160, - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108, - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107, - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214, - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204, - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136, - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210, - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206, - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67, - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66, - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212, - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208, - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69, - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68, - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140, - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71, - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70, - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143, - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267, + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73, + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72, + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181, + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175, + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179, + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173, + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102, + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101, + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183, + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177, + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104, + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103, + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106, + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105, + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160, + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108, + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107, + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214, + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204, + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136, + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210, + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206, + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67, + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66, + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212, + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208, + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69, + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68, + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140, + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71, + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70, + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143, + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19008, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19044, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19053, @@ -4247,20 +4247,20 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5542; wire [128 : 0] amoExec___d4904, amoExec___d773, - new_pc__h871752, - new_pc__h909836, - next_pc__h1007609, - pc__h960829, - v__h1007648, - v__h1008101, - x__h878730, - x__h912383; + new_pc__h871748, + new_pc__h909831, + next_pc__h1007604, + pc__h960824, + v__h1007643, + v__h1008096, + x__h878726, + x__h912378; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5147, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871, coreFix_memExe_regToExeQ_first__633_BITS_139_T_ETC___d4052, - x__h183367, - x__h199219; + x__h183366, + x__h199218; wire [108 : 0] IF_fetchStage_pipelines_0_first__0049_BITS_237_ETC___d20404, IF_fetchStage_pipelines_1_first__0058_BITS_237_ETC___d21354; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3568; @@ -4284,70 +4284,70 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16238, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3036, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3405, - addTop__h239914, - addTop__h241071, - addTop__h254680, - address__h996966, - address__h997310, - address__h997623, - address__h997967, + addTop__h239913, + addTop__h241070, + addTop__h254678, + address__h996961, + address__h997305, + address__h997618, + address__h997962, coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389, coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692, - cr_address__h865497, - cr_address__h866045, - cr_address__h904119, - cr_address__h904667, - data_address__h1013598, - data_address__h1014452, - in__h239745, - in__h240902, - in__h254511, - in__h995128, - pc_address__h992211, - pointer__h1005920, - pointer__h1025233, - pointer__h242569, - res_address__h126791, - res_address__h139703, - res_address__h178866, - res_address__h197631, - res_address__h216390, - res_address__h235267, - res_address__h567273, - res_address__h568125, - res_address__h613882, - res_address__h659629, - res_address__h705438, - res_address__h706298, - res_address__h848497, - res_address__h890898, - result__h240541, - result__h241698, - result__h255307, - result_d_address__h242780, - ret__h239918, - ret__h241075, - ret__h254684, - x__h1005944, - x__h1025256, - x__h235690, - x__h239763, - x__h239911, - x__h240920, - x__h241068, - x__h248052, - x__h254529, - x__h254677, - x__h995146, - x__h997160, - x__h997464, - x__h997817, - x__h998121, - y__h239762, - y__h240919, - y__h254528, - y__h995145; + cr_address__h865494, + cr_address__h866042, + cr_address__h904115, + cr_address__h904663, + data_address__h1013592, + data_address__h1014446, + in__h239744, + in__h240901, + in__h254509, + in__h995123, + pc_address__h992206, + pointer__h1005915, + pointer__h1025227, + pointer__h242568, + res_address__h126790, + res_address__h139702, + res_address__h178865, + res_address__h197630, + res_address__h216389, + res_address__h235266, + res_address__h567269, + res_address__h568122, + res_address__h613879, + res_address__h659626, + res_address__h705435, + res_address__h706295, + res_address__h848494, + res_address__h890894, + result__h240540, + result__h241697, + result__h255305, + result_d_address__h242779, + ret__h239917, + ret__h241074, + ret__h254682, + x__h1005939, + x__h1025250, + x__h235689, + x__h239762, + x__h239910, + x__h240919, + x__h241067, + x__h248050, + x__h254527, + x__h254675, + x__h995141, + x__h997155, + x__h997459, + x__h997812, + x__h998116, + y__h239761, + y__h240918, + y__h254526, + y__h995140; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13306, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12467, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12468, @@ -4373,173 +4373,173 @@ module mkCore(CLK, SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448, _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602, _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527, - _theResult___fst__h836055, - _theResult___snd__h836056, - a___1__h835774, - a___1__h836060, - a__h835633, - addBase__h239805, - addBase__h240962, - addBase__h254571, - addr__h148408, - addr__h151984, - addr__h235261, - addr__h987208, - address__h1008563, - address__h996900, - address__h996950, - b___1__h835775, - b___1__h836105, - b__h835634, - base__h996861, - base__h996915, + _theResult___fst__h836052, + _theResult___snd__h836053, + a___1__h835771, + a___1__h836057, + a__h835630, + addBase__h239804, + addBase__h240961, + addBase__h254569, + addr__h148407, + addr__h151983, + addr__h235260, + addr__h987203, + address__h1008558, + address__h996895, + address__h996945, + b___1__h835772, + b___1__h836102, + b__h835631, + base__h996856, + base__h996910, csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592, csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515, - data___1__h705460, - data___1__h706320, - data__h567607, - data__h613367, - data__h659114, - data__h704928, - data__h705760, - data__h705791, - fcsr_csr__read__h849072, - fflags_csr__read__h849047, - frm_csr__read__h849058, - mask__h996972, - mask__h997629, - mcause_csr__read__h850488, - mcounteren_csr__read__h850309, - medeleg_csr__read__h849989, - mideleg_csr__read__h850087, - mie_csr__read__h850214, - mip_csr__read__h850727, - mstatus_csr__read__h849835, - n__read__h1008993, + data___1__h705457, + data___1__h706317, + data__h567604, + data__h613364, + data__h659111, + data__h704925, + data__h705757, + data__h705788, + fcsr_csr__read__h849069, + fflags_csr__read__h849044, + frm_csr__read__h849055, + mask__h996967, + mask__h997624, + mcause_csr__read__h850485, + mcounteren_csr__read__h850306, + medeleg_csr__read__h849986, + mideleg_csr__read__h850084, + mie_csr__read__h850211, + mip_csr__read__h850724, + mstatus_csr__read__h849832, + n__read__h1008988, n__read__h7877, - newAddrDiff__h996973, - newAddrDiff__h997317, - newAddrDiff__h997630, - newAddrDiff__h997974, - offset__h242559, - q___1__h706385, - rVal1__h714446, - rVal2__h714447, - r___1__h706411, - res_data__h568165, - res_data__h568170, - res_data__h613919, - res_data__h613924, - res_data__h659666, - res_data__h659671, - resp_addr__h509039, - rg_tdata1__read__h851828, + newAddrDiff__h996968, + newAddrDiff__h997312, + newAddrDiff__h997625, + newAddrDiff__h997969, + offset__h242558, + q___1__h706382, + rVal1__h714443, + rVal2__h714444, + r___1__h706408, + res_data__h568162, + res_data__h568167, + res_data__h613916, + res_data__h613921, + res_data__h659663, + res_data__h659668, + resp_addr__h509036, + rg_tdata1__read__h851825, robdeqPort_0_deq_data_BITS_95_TO_32__q326, - satp_csr__read__h849689, - scause_csr__read__h849486, - scounteren_csr__read__h849391, - sie_csr__read__h849338, - sip_csr__read__h849626, - sstatus_csr__read__h849268, - thin_address__h996854, - tmpAddr__h242768, - trap_val__h994512, - upd__h1009069, + satp_csr__read__h849686, + scause_csr__read__h849483, + scounteren_csr__read__h849388, + sie_csr__read__h849335, + sip_csr__read__h849623, + sstatus_csr__read__h849265, + thin_address__h996849, + tmpAddr__h242767, + trap_val__h994507, + upd__h1009064, upd__h3035, upd__h3645, upd__h7946, - value__h239635, - value__h239799, - value__h240792, - value__h240956, - value__h254401, - value__h254565, - x__h127272, - x__h140188, - x__h183449, - x__h202200, - x__h216766, - x__h239653, - x__h239655, - x__h240810, - x__h240812, - x__h242708, + value__h239634, + value__h239798, + value__h240791, + value__h240955, + value__h254399, + value__h254563, + x__h127271, + x__h140187, + x__h183448, + x__h202199, + x__h216765, + x__h239652, + x__h239654, + x__h240809, + x__h240811, + x__h242707, + x__h254417, x__h254419, - x__h254421, - x__h714355, - x__h714356, - x__h714357, - x__h865674, - x__h866222, - x__h904296, - x__h904844, - x__h992383, - x__h995059, - x__h995061, + x__h714352, + x__h714353, + x__h714354, + x__h865671, + x__h866219, + x__h904292, + x__h904840, + x__h992378, + x__h995054, + x__h995056, x_addr__h19852, x_addr__h44221, - x_addr__h535302, - x_quotient__h705674, - x_reg_ifc__read__h849177, - x_remainder__h705675, - y__h1011220, - y__h997089, - y__h997746, - y_avValue__h710401, - y_avValue__h711034, - y_avValue__h711661, - y_avValue_snd_snd_snd_snd_snd__h1010691, - y_avValue_snd_snd_snd_snd_snd__h1011273, - y_avValue_snd_snd_snd_snd_snd__h1011302; + x_addr__h535298, + x_quotient__h705671, + x_reg_ifc__read__h849174, + x_remainder__h705672, + y__h1011215, + y__h997084, + y__h997741, + y_avValue__h710398, + y_avValue__h711031, + y_avValue__h711658, + y_avValue_snd_snd_snd_snd_snd__h1010686, + y_avValue_snd_snd_snd_snd_snd__h1011268, + y_avValue_snd_snd_snd_snd_snd__h1011297; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785, - r1__read__h852705, - r1__read__h853109, - r1__read__h853619, - r1__read__h853638, - r1__read__h853871, - r1__read__h854037, - r1__read__h854130, - r1__read__h854149; - wire [61 : 0] r1__read__h852707, - r1__read__h853111, - r1__read__h853621, - r1__read__h853640, - r1__read__h853873, - r1__read__h854013, - r1__read__h854039, - r1__read__h854132, - r1__read__h854151; - wire [60 : 0] r1__read__h853875, - r1__read__h854015, - r1__read__h854041, - r1__read__h854153; - wire [59 : 0] r1__read__h852709, - r1__read__h853113, - r1__read__h853642, - r1__read__h853877, - r1__read__h854043, - r1__read__h854155; + r1__read__h852702, + r1__read__h853106, + r1__read__h853616, + r1__read__h853635, + r1__read__h853868, + r1__read__h854034, + r1__read__h854127, + r1__read__h854146; + wire [61 : 0] r1__read__h852704, + r1__read__h853108, + r1__read__h853618, + r1__read__h853637, + r1__read__h853870, + r1__read__h854010, + r1__read__h854036, + r1__read__h854129, + r1__read__h854148; + wire [60 : 0] r1__read__h853872, + r1__read__h854012, + r1__read__h854038, + r1__read__h854150; + wire [59 : 0] r1__read__h852706, + r1__read__h853110, + r1__read__h853639, + r1__read__h853874, + r1__read__h854040, + r1__read__h854152; wire [58 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5478, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5520, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6956, - r1__read__h852711, - r1__read__h853115, - r1__read__h853631, - r1__read__h853644, - r1__read__h853879, - r1__read__h854045, - r1__read__h854142, - r1__read__h854157; + r1__read__h852708, + r1__read__h853112, + r1__read__h853628, + r1__read__h853641, + r1__read__h853876, + r1__read__h854042, + r1__read__h854139, + r1__read__h854154; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7193, - r1__read__h852713, - r1__read__h853117, - r1__read__h853646, - r1__read__h853881, - r1__read__h854017, - r1__read__h854047, - r1__read__h854159, - y__h422493; + r1__read__h852710, + r1__read__h853114, + r1__read__h853643, + r1__read__h853878, + r1__read__h854014, + r1__read__h854044, + r1__read__h854156, + y__h422490; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74, @@ -4567,195 +4567,195 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663, - _theResult____h576381, - _theResult____h594020, - _theResult____h622132, - _theResult____h639769, - _theResult____h667879, - _theResult____h685516, - _theResult____h735554, - _theResult____h774407, - _theResult____h813711, - _theResult___snd__h584503, - _theResult___snd__h584514, - _theResult___snd__h584516, - _theResult___snd__h584526, - _theResult___snd__h584532, - _theResult___snd__h584555, - _theResult___snd__h593099, - _theResult___snd__h593101, - _theResult___snd__h593108, - _theResult___snd__h593114, - _theResult___snd__h593137, - _theResult___snd__h602269, - _theResult___snd__h602280, - _theResult___snd__h602282, - _theResult___snd__h602292, - _theResult___snd__h602298, - _theResult___snd__h602321, - _theResult___snd__h610889, - _theResult___snd__h610903, - _theResult___snd__h610909, - _theResult___snd__h610927, - _theResult___snd__h630252, - _theResult___snd__h630263, - _theResult___snd__h630265, - _theResult___snd__h630275, - _theResult___snd__h630281, - _theResult___snd__h630304, - _theResult___snd__h638848, - _theResult___snd__h638850, - _theResult___snd__h638857, - _theResult___snd__h638863, - _theResult___snd__h638886, - _theResult___snd__h648018, - _theResult___snd__h648029, - _theResult___snd__h648031, - _theResult___snd__h648041, - _theResult___snd__h648047, - _theResult___snd__h648070, - _theResult___snd__h656638, - _theResult___snd__h656652, - _theResult___snd__h656658, - _theResult___snd__h656676, - _theResult___snd__h675999, - _theResult___snd__h676010, - _theResult___snd__h676012, - _theResult___snd__h676022, - _theResult___snd__h676028, - _theResult___snd__h676051, - _theResult___snd__h684595, - _theResult___snd__h684597, - _theResult___snd__h684604, - _theResult___snd__h684610, - _theResult___snd__h684633, - _theResult___snd__h693765, - _theResult___snd__h693776, - _theResult___snd__h693778, - _theResult___snd__h693788, - _theResult___snd__h693794, - _theResult___snd__h693817, - _theResult___snd__h702385, - _theResult___snd__h702399, - _theResult___snd__h702405, - _theResult___snd__h702423, - _theResult___snd__h734164, - _theResult___snd__h734166, - _theResult___snd__h734173, - _theResult___snd__h734179, - _theResult___snd__h734202, - _theResult___snd__h743801, - _theResult___snd__h743812, - _theResult___snd__h743814, - _theResult___snd__h743824, - _theResult___snd__h743830, - _theResult___snd__h743853, - _theResult___snd__h752569, - _theResult___snd__h752583, - _theResult___snd__h752589, - _theResult___snd__h752607, - _theResult___snd__h773017, - _theResult___snd__h773019, - _theResult___snd__h773026, - _theResult___snd__h773032, - _theResult___snd__h773055, - _theResult___snd__h782654, - _theResult___snd__h782665, - _theResult___snd__h782667, - _theResult___snd__h782677, - _theResult___snd__h782683, - _theResult___snd__h782706, - _theResult___snd__h791422, - _theResult___snd__h791436, - _theResult___snd__h791442, - _theResult___snd__h791460, - _theResult___snd__h812321, - _theResult___snd__h812323, - _theResult___snd__h812330, - _theResult___snd__h812336, - _theResult___snd__h812359, - _theResult___snd__h821958, - _theResult___snd__h821969, - _theResult___snd__h821971, - _theResult___snd__h821981, - _theResult___snd__h821987, - _theResult___snd__h822010, - _theResult___snd__h830726, - _theResult___snd__h830740, - _theResult___snd__h830746, - _theResult___snd__h830764, - r1__read__h853883, - r1__read__h854019, - r1__read__h854049, - r1__read__h854161, - result__h594633, - result__h640382, - result__h686129, - result__h736167, - result__h775020, - result__h814324, - sfd__h568776, - sfd__h614530, - sfd__h660277, - sfd__h715187, - sfd__h754181, - sfd__h793485, - sfdin__h584486, - sfdin__h602252, - sfdin__h630235, - sfdin__h648001, - sfdin__h675982, - sfdin__h693748, - sfdin__h743784, - sfdin__h782637, - sfdin__h821941, - x__h594730, - x__h640479, - x__h686226, - x__h736262, - x__h775115, - x__h814419; + _theResult____h576378, + _theResult____h594017, + _theResult____h622129, + _theResult____h639766, + _theResult____h667876, + _theResult____h685513, + _theResult____h735551, + _theResult____h774404, + _theResult____h813708, + _theResult___snd__h584500, + _theResult___snd__h584511, + _theResult___snd__h584513, + _theResult___snd__h584523, + _theResult___snd__h584529, + _theResult___snd__h584552, + _theResult___snd__h593096, + _theResult___snd__h593098, + _theResult___snd__h593105, + _theResult___snd__h593111, + _theResult___snd__h593134, + _theResult___snd__h602266, + _theResult___snd__h602277, + _theResult___snd__h602279, + _theResult___snd__h602289, + _theResult___snd__h602295, + _theResult___snd__h602318, + _theResult___snd__h610886, + _theResult___snd__h610900, + _theResult___snd__h610906, + _theResult___snd__h610924, + _theResult___snd__h630249, + _theResult___snd__h630260, + _theResult___snd__h630262, + _theResult___snd__h630272, + _theResult___snd__h630278, + _theResult___snd__h630301, + _theResult___snd__h638845, + _theResult___snd__h638847, + _theResult___snd__h638854, + _theResult___snd__h638860, + _theResult___snd__h638883, + _theResult___snd__h648015, + _theResult___snd__h648026, + _theResult___snd__h648028, + _theResult___snd__h648038, + _theResult___snd__h648044, + _theResult___snd__h648067, + _theResult___snd__h656635, + _theResult___snd__h656649, + _theResult___snd__h656655, + _theResult___snd__h656673, + _theResult___snd__h675996, + _theResult___snd__h676007, + _theResult___snd__h676009, + _theResult___snd__h676019, + _theResult___snd__h676025, + _theResult___snd__h676048, + _theResult___snd__h684592, + _theResult___snd__h684594, + _theResult___snd__h684601, + _theResult___snd__h684607, + _theResult___snd__h684630, + _theResult___snd__h693762, + _theResult___snd__h693773, + _theResult___snd__h693775, + _theResult___snd__h693785, + _theResult___snd__h693791, + _theResult___snd__h693814, + _theResult___snd__h702382, + _theResult___snd__h702396, + _theResult___snd__h702402, + _theResult___snd__h702420, + _theResult___snd__h734161, + _theResult___snd__h734163, + _theResult___snd__h734170, + _theResult___snd__h734176, + _theResult___snd__h734199, + _theResult___snd__h743798, + _theResult___snd__h743809, + _theResult___snd__h743811, + _theResult___snd__h743821, + _theResult___snd__h743827, + _theResult___snd__h743850, + _theResult___snd__h752566, + _theResult___snd__h752580, + _theResult___snd__h752586, + _theResult___snd__h752604, + _theResult___snd__h773014, + _theResult___snd__h773016, + _theResult___snd__h773023, + _theResult___snd__h773029, + _theResult___snd__h773052, + _theResult___snd__h782651, + _theResult___snd__h782662, + _theResult___snd__h782664, + _theResult___snd__h782674, + _theResult___snd__h782680, + _theResult___snd__h782703, + _theResult___snd__h791419, + _theResult___snd__h791433, + _theResult___snd__h791439, + _theResult___snd__h791457, + _theResult___snd__h812318, + _theResult___snd__h812320, + _theResult___snd__h812327, + _theResult___snd__h812333, + _theResult___snd__h812356, + _theResult___snd__h821955, + _theResult___snd__h821966, + _theResult___snd__h821968, + _theResult___snd__h821978, + _theResult___snd__h821984, + _theResult___snd__h822007, + _theResult___snd__h830723, + _theResult___snd__h830737, + _theResult___snd__h830743, + _theResult___snd__h830761, + r1__read__h853880, + r1__read__h854016, + r1__read__h854046, + r1__read__h854158, + result__h594630, + result__h640379, + result__h686126, + result__h736164, + result__h775017, + result__h814321, + sfd__h568773, + sfd__h614527, + sfd__h660274, + sfd__h715184, + sfd__h754178, + sfd__h793482, + sfdin__h584483, + sfdin__h602249, + sfdin__h630232, + sfdin__h647998, + sfdin__h675979, + sfdin__h693745, + sfdin__h743781, + sfdin__h782634, + sfdin__h821938, + x__h594727, + x__h640476, + x__h686223, + x__h736259, + x__h775112, + x__h814416; wire [55 : 0] coreFix_memExe_dispToRegQ_first__680_BIT_101_6_ETC___d3567, - r1__read__h852715, - r1__read__h853119, - r1__read__h853648, - r1__read__h853885, - r1__read__h854051, - r1__read__h854163; + r1__read__h852712, + r1__read__h853116, + r1__read__h853645, + r1__read__h853882, + r1__read__h854048, + r1__read__h854160; wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19198, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17093, - r1__read__h852717, - r1__read__h853121, - r1__read__h853650, - r1__read__h853887, - r1__read__h854053, - r1__read__h854165; - wire [53 : 0] r1__read__h853996, - r1__read__h854021, - r1__read__h854055, - r1__read__h854167, - sfd__h734231, - sfd__h743882, - sfd__h752642, - sfd__h773084, - sfd__h782735, - sfd__h791495, - sfd__h812388, - sfd__h822039, - sfd__h830799, - value__h577003, - value__h622752, - value__h668499; + r1__read__h852714, + r1__read__h853118, + r1__read__h853647, + r1__read__h853884, + r1__read__h854050, + r1__read__h854162; + wire [53 : 0] r1__read__h853993, + r1__read__h854018, + r1__read__h854052, + r1__read__h854164, + sfd__h734228, + sfd__h743879, + sfd__h752639, + sfd__h773081, + sfd__h782732, + sfd__h791492, + sfd__h812385, + sfd__h822036, + sfd__h830796, + value__h577000, + value__h622749, + value__h668496; wire [52 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3566, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19564, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19628, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17485, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17549, - r1__read__h853889, - r1__read__h853998, - r1__read__h854023, - r1__read__h854057, - r1__read__h854169; + r1__read__h853886, + r1__read__h853995, + r1__read__h854020, + r1__read__h854054, + r1__read__h854166; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982, @@ -4777,85 +4777,85 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784, - _theResult___fst_sfd__h719141, + _theResult___fst_sfd__h719138, + _theResult___fst_sfd__h734966, _theResult___fst_sfd__h734969, - _theResult___fst_sfd__h734972, + _theResult___fst_sfd__h744617, _theResult___fst_sfd__h744620, - _theResult___fst_sfd__h744623, + _theResult___fst_sfd__h753401, _theResult___fst_sfd__h753404, - _theResult___fst_sfd__h753407, - _theResult___fst_sfd__h753416, - _theResult___fst_sfd__h753422, - _theResult___fst_sfd__h757994, + _theResult___fst_sfd__h753413, + _theResult___fst_sfd__h753419, + _theResult___fst_sfd__h757991, + _theResult___fst_sfd__h773819, _theResult___fst_sfd__h773822, - _theResult___fst_sfd__h773825, + _theResult___fst_sfd__h783470, _theResult___fst_sfd__h783473, - _theResult___fst_sfd__h783476, + _theResult___fst_sfd__h792254, _theResult___fst_sfd__h792257, - _theResult___fst_sfd__h792260, - _theResult___fst_sfd__h792269, - _theResult___fst_sfd__h792275, - _theResult___fst_sfd__h797298, + _theResult___fst_sfd__h792266, + _theResult___fst_sfd__h792272, + _theResult___fst_sfd__h797295, + _theResult___fst_sfd__h813123, _theResult___fst_sfd__h813126, - _theResult___fst_sfd__h813129, + _theResult___fst_sfd__h822774, _theResult___fst_sfd__h822777, - _theResult___fst_sfd__h822780, + _theResult___fst_sfd__h831558, _theResult___fst_sfd__h831561, - _theResult___fst_sfd__h831564, - _theResult___fst_sfd__h831573, - _theResult___fst_sfd__h831579, - _theResult___sfd__h734869, - _theResult___sfd__h744520, - _theResult___sfd__h753304, - _theResult___sfd__h773722, - _theResult___sfd__h783373, - _theResult___sfd__h792157, - _theResult___sfd__h813026, - _theResult___sfd__h822677, - _theResult___sfd__h831461, - _theResult___snd_fst_sfd__h715141, - _theResult___snd_fst_sfd__h734975, - _theResult___snd_fst_sfd__h753410, - _theResult___snd_fst_sfd__h754135, - _theResult___snd_fst_sfd__h773828, - _theResult___snd_fst_sfd__h792263, - _theResult___snd_fst_sfd__h793439, - _theResult___snd_fst_sfd__h813132, - _theResult___snd_fst_sfd__h831567, - mask__h239915, - mask__h241072, - mask__h254681, - out___1_sfd__h714889, - out___1_sfd__h753883, - out___1_sfd__h793187, - out_sfd__h734872, - out_sfd__h744523, - out_sfd__h753307, - out_sfd__h773725, - out_sfd__h783376, - out_sfd__h792160, - out_sfd__h813029, - out_sfd__h822680, - out_sfd__h831464; - wire [50 : 0] r1__read__h852719, r1__read__h853891; + _theResult___fst_sfd__h831570, + _theResult___fst_sfd__h831576, + _theResult___sfd__h734866, + _theResult___sfd__h744517, + _theResult___sfd__h753301, + _theResult___sfd__h773719, + _theResult___sfd__h783370, + _theResult___sfd__h792154, + _theResult___sfd__h813023, + _theResult___sfd__h822674, + _theResult___sfd__h831458, + _theResult___snd_fst_sfd__h715138, + _theResult___snd_fst_sfd__h734972, + _theResult___snd_fst_sfd__h753407, + _theResult___snd_fst_sfd__h754132, + _theResult___snd_fst_sfd__h773825, + _theResult___snd_fst_sfd__h792260, + _theResult___snd_fst_sfd__h793436, + _theResult___snd_fst_sfd__h813129, + _theResult___snd_fst_sfd__h831564, + mask__h239914, + mask__h241071, + mask__h254679, + out___1_sfd__h714886, + out___1_sfd__h753880, + out___1_sfd__h793184, + out_sfd__h734869, + out_sfd__h744520, + out_sfd__h753304, + out_sfd__h773722, + out_sfd__h783373, + out_sfd__h792157, + out_sfd__h813026, + out_sfd__h822677, + out_sfd__h831461; + wire [50 : 0] r1__read__h852716, r1__read__h853888; wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q5, coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3, - highOffsetBits__h242578, - mask__h239806, - mask__h240963, - mask__h254572, - r1__read__h854000, - signBits__h242575, - x__h242605; - wire [48 : 0] r1__read__h852721, r1__read__h853893, r1__read__h854002; - wire [46 : 0] r1__read__h852723, r1__read__h853895; - wire [45 : 0] r1__read__h852725, r1__read__h853897; - wire [44 : 0] r1__read__h852727, r1__read__h853899; - wire [43 : 0] r1__read__h852729, r1__read__h853901; - wire [42 : 0] r1__read__h853903; - wire [41 : 0] r1__read__h853905; - wire [40 : 0] r1__read__h853907; + highOffsetBits__h242577, + mask__h239805, + mask__h240962, + mask__h254570, + r1__read__h853997, + signBits__h242574, + x__h242604; + wire [48 : 0] r1__read__h852718, r1__read__h853890, r1__read__h853999; + wire [46 : 0] r1__read__h852720, r1__read__h853892; + wire [45 : 0] r1__read__h852722, r1__read__h853894; + wire [44 : 0] r1__read__h852724, r1__read__h853896; + wire [43 : 0] r1__read__h852726, r1__read__h853898; + wire [42 : 0] r1__read__h853900; + wire [41 : 0] r1__read__h853902; + wire [40 : 0] r1__read__h853904; wire [38 : 0] IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_c_ETC___d22659; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954, IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120, @@ -4880,16 +4880,16 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21, coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16, - data05760_BITS_31_TO_0__q25, - r1__read__h852731, - r1__read__h853909, - x__h568180, - x__h613934, + data05757_BITS_31_TO_0__q25, + r1__read__h852728, + r1__read__h853906, + x__h568177, + x__h613931, x__h65608, - x__h659681, + x__h659678, x_data__h60109; - wire [29 : 0] r1__read__h852733, r1__read__h853911; - wire [27 : 0] r1__read__h853913; + wire [29 : 0] r1__read__h852730, r1__read__h853908; + wire [27 : 0] r1__read__h853910; wire [25 : 0] IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677, IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19904, IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19935, @@ -4899,21 +4899,21 @@ module mkCore(CLK, IF_csrf_mepcc_reg_read_wget__3118_BIT_34_3127__ETC___d23135, IF_csrf_rg_dpc_read__6185_BIT_34_3810_THEN_csr_ETC___d23818, IF_csrf_sepcc_reg_read_wget__3089_BIT_34_3098__ETC___d23106; - wire [24 : 0] sfd__h584584, - sfd__h593166, - sfd__h602350, - sfd__h610962, - sfd__h630333, - sfd__h638915, - sfd__h648099, - sfd__h656711, - sfd__h676080, - sfd__h684662, - sfd__h693846, - sfd__h702458, - value__h719770, - value__h758623, - value__h797927; + wire [24 : 0] sfd__h584581, + sfd__h593163, + sfd__h602347, + sfd__h610959, + sfd__h630330, + sfd__h638912, + sfd__h648096, + sfd__h656708, + sfd__h676077, + sfd__h684659, + sfd__h693843, + sfd__h702455, + value__h719767, + value__h758620, + value__h797924; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856, @@ -4938,67 +4938,67 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129, - _theResult___fst_sfd__h585090, - _theResult___fst_sfd__h593672, - _theResult___fst_sfd__h602856, - _theResult___fst_sfd__h611492, - _theResult___fst_sfd__h611501, - _theResult___fst_sfd__h611507, - _theResult___fst_sfd__h630839, - _theResult___fst_sfd__h639421, - _theResult___fst_sfd__h648605, - _theResult___fst_sfd__h657241, - _theResult___fst_sfd__h657250, - _theResult___fst_sfd__h657256, - _theResult___fst_sfd__h676586, - _theResult___fst_sfd__h685168, - _theResult___fst_sfd__h694352, - _theResult___fst_sfd__h702988, - _theResult___fst_sfd__h702997, - _theResult___fst_sfd__h703003, - _theResult___sfd__h585009, - _theResult___sfd__h593591, - _theResult___sfd__h602775, - _theResult___sfd__h611411, - _theResult___sfd__h611513, - _theResult___sfd__h630758, - _theResult___sfd__h639340, - _theResult___sfd__h648524, - _theResult___sfd__h657160, - _theResult___sfd__h657262, - _theResult___sfd__h676505, - _theResult___sfd__h685087, - _theResult___sfd__h694271, - _theResult___sfd__h702907, - _theResult___sfd__h703009, - _theResult___snd_fst_sfd__h568726, - _theResult___snd_fst_sfd__h593675, - _theResult___snd_fst_sfd__h611495, - _theResult___snd_fst_sfd__h614480, - _theResult___snd_fst_sfd__h639424, - _theResult___snd_fst_sfd__h657244, - _theResult___snd_fst_sfd__h660227, - _theResult___snd_fst_sfd__h685171, - _theResult___snd_fst_sfd__h702991, - f1_sfd__h714826, - f2_sfd__h753820, - f3_sfd__h793124, - out_f_sfd__h611790, - out_f_sfd__h657539, - out_f_sfd__h703286, - out_sfd__h585012, - out_sfd__h593594, - out_sfd__h602778, - out_sfd__h611414, - out_sfd__h630761, - out_sfd__h639343, - out_sfd__h648527, - out_sfd__h657163, - out_sfd__h676508, - out_sfd__h685090, - out_sfd__h694274, - out_sfd__h702910; - wire [19 : 0] r1__read__h853848; + _theResult___fst_sfd__h585087, + _theResult___fst_sfd__h593669, + _theResult___fst_sfd__h602853, + _theResult___fst_sfd__h611489, + _theResult___fst_sfd__h611498, + _theResult___fst_sfd__h611504, + _theResult___fst_sfd__h630836, + _theResult___fst_sfd__h639418, + _theResult___fst_sfd__h648602, + _theResult___fst_sfd__h657238, + _theResult___fst_sfd__h657247, + _theResult___fst_sfd__h657253, + _theResult___fst_sfd__h676583, + _theResult___fst_sfd__h685165, + _theResult___fst_sfd__h694349, + _theResult___fst_sfd__h702985, + _theResult___fst_sfd__h702994, + _theResult___fst_sfd__h703000, + _theResult___sfd__h585006, + _theResult___sfd__h593588, + _theResult___sfd__h602772, + _theResult___sfd__h611408, + _theResult___sfd__h611510, + _theResult___sfd__h630755, + _theResult___sfd__h639337, + _theResult___sfd__h648521, + _theResult___sfd__h657157, + _theResult___sfd__h657259, + _theResult___sfd__h676502, + _theResult___sfd__h685084, + _theResult___sfd__h694268, + _theResult___sfd__h702904, + _theResult___sfd__h703006, + _theResult___snd_fst_sfd__h568723, + _theResult___snd_fst_sfd__h593672, + _theResult___snd_fst_sfd__h611492, + _theResult___snd_fst_sfd__h614477, + _theResult___snd_fst_sfd__h639421, + _theResult___snd_fst_sfd__h657241, + _theResult___snd_fst_sfd__h660224, + _theResult___snd_fst_sfd__h685168, + _theResult___snd_fst_sfd__h702988, + f1_sfd__h714823, + f2_sfd__h753817, + f3_sfd__h793121, + out_f_sfd__h611787, + out_f_sfd__h657536, + out_f_sfd__h703283, + out_sfd__h585009, + out_sfd__h593591, + out_sfd__h602775, + out_sfd__h611411, + out_sfd__h630758, + out_sfd__h639340, + out_sfd__h648524, + out_sfd__h657160, + out_sfd__h676505, + out_sfd__h685087, + out_sfd__h694271, + out_sfd__h702907; + wire [19 : 0] r1__read__h853845; wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, @@ -5007,8 +5007,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10, - INV_x83367_BITS_108_TO_90__q33, - INV_x99219_BITS_108_TO_90__q35; + INV_x83366_BITS_108_TO_90__q33, + INV_x99218_BITS_108_TO_90__q35; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18846, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18847, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16462, @@ -5025,23 +5025,23 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3547; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116, IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3524, - _theResult____h917995, - base__h239640, - base__h240797, - base__h254406, - base__h995046, - enabled_ints___1__h918520, - enabled_ints__h918566, - offset__h239641, - offset__h240798, - offset__h254407, - offset__h995047, - pend_ints__h917993, - x__h240013, - x__h241170, - x__h254779, - x__h894478, - y__h918532; + _theResult____h917990, + base__h239639, + base__h240796, + base__h254404, + base__h995041, + enabled_ints___1__h918515, + enabled_ints__h918561, + offset__h239640, + offset__h240797, + offset__h254405, + offset__h995042, + pend_ints__h917988, + x__h240012, + x__h241169, + x__h254777, + x__h894474, + y__h918527; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18632, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18633, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16248, @@ -5063,65 +5063,65 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16253, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3056, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3413, - b_base__h127497, - b_base__h140413, - b_base__h183674, - b_base__h202425, - b_base__h216991, - b_base__h865912, - b_base__h866460, - b_base__h904534, - b_base__h905082, - b_base__h992608, + b_base__h127496, + b_base__h140412, + b_base__h183673, + b_base__h202424, + b_base__h216990, + b_base__h865909, + b_base__h866457, + b_base__h904530, + b_base__h905078, + b_base__h992603, checkForException___d20436, checkForException___d21375, - cr_addrBits__h865498, - cr_addrBits__h866046, - cr_addrBits__h904120, - cr_addrBits__h904668, - data_addrBits__h1013599, - data_addrBits__h1014453, - pc_addrBits__h992212, - r1__read_BITS_13_TO_0___h918542, - repBoundBits__h242584, - res_addrBits__h126792, - res_addrBits__h139704, - res_addrBits__h178867, - res_addrBits__h197632, - res_addrBits__h216391, - res_addrBits__h235268, - res_addrBits__h567274, - res_addrBits__h568126, - res_addrBits__h613883, - res_addrBits__h659630, - res_addrBits__h705439, - res_addrBits__h706299, - res_addrBits__h848498, - res_addrBits__h890899, - toBoundsM1__h242588, - toBounds__h242587, - x1_avValue_new_pcc_capFat_bounds_baseBits__h998359, - x__h127470, - x__h127490, - x__h140386, - x__h140406, - x__h183647, - x__h183667, - x__h202398, - x__h202418, - x__h216964, - x__h216984, - x__h865885, - x__h865905, - x__h866433, - x__h866453, - x__h904507, - x__h904527, - x__h905055, - x__h905075, - x__h992581, - x__h992601, - x__h998356; + cr_addrBits__h865495, + cr_addrBits__h866043, + cr_addrBits__h904116, + cr_addrBits__h904664, + data_addrBits__h1013593, + data_addrBits__h1014447, + pc_addrBits__h992207, + r1__read_BITS_13_TO_0___h918537, + repBoundBits__h242583, + res_addrBits__h126791, + res_addrBits__h139703, + res_addrBits__h178866, + res_addrBits__h197631, + res_addrBits__h216390, + res_addrBits__h235267, + res_addrBits__h567270, + res_addrBits__h568123, + res_addrBits__h613880, + res_addrBits__h659627, + res_addrBits__h705436, + res_addrBits__h706296, + res_addrBits__h848495, + res_addrBits__h890895, + toBoundsM1__h242587, + toBounds__h242586, + x1_avValue_new_pcc_capFat_bounds_baseBits__h998354, + x__h127469, + x__h127489, + x__h140385, + x__h140405, + x__h183646, + x__h183666, + x__h202397, + x__h202417, + x__h216963, + x__h216983, + x__h865882, + x__h865902, + x__h866430, + x__h866450, + x__h904503, + x__h904523, + x__h905051, + x__h905071, + x__h992576, + x__h992596, + x__h998351; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__239_BIT_27_ETC___d4739, IF_NOT_renameStage_rg_m_halt_req_0076_BIT_4_00_ETC___d20769, IF_NOT_renameStage_rg_m_halt_req_0076_BIT_4_00_ETC___d20770, @@ -5157,45 +5157,45 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659, - b_top__h127496, - b_top__h140412, - b_top__h183673, - b_top__h202424, - b_top__h216990, - b_top__h865911, - b_top__h866459, - b_top__h904533, - b_top__h905081, - b_top__h992607, + b_top__h127495, + b_top__h140411, + b_top__h183672, + b_top__h202423, + b_top__h216989, + b_top__h865908, + b_top__h866456, + b_top__h904529, + b_top__h905077, + b_top__h992602, capChecks___d4142, - renaming_spec_bits__h966287, - result__h913573, - result__h913624, - spec_bits__h971306, - topBits__h127399, - topBits__h140315, - topBits__h183576, - topBits__h202327, - topBits__h216893, - topBits__h865813, - topBits__h866361, - topBits__h904435, - topBits__h904983, - topBits__h992510, - w__h913568, - x__h594763, - x__h640512, - x__h686259, - x__h736295, - x__h775148, - x__h814452, - x__h913572, - x__h913623, - y__h913602, - y__h971319, - y_avValue_snd_fst__h960972, - y_avValue_snd_fst__h961014, - y_avValue_snd_fst__h961056; + renaming_spec_bits__h966282, + result__h913568, + result__h913619, + spec_bits__h971301, + topBits__h127398, + topBits__h140314, + topBits__h183575, + topBits__h202326, + topBits__h216892, + topBits__h865810, + topBits__h866358, + topBits__h904431, + topBits__h904979, + topBits__h992505, + w__h913563, + x__h594760, + x__h640509, + x__h686256, + x__h736292, + x__h775145, + x__h814449, + x__h913567, + x__h913618, + y__h913597, + y__h971314, + y_avValue_snd_fst__h960967, + y_avValue_snd_fst__h961009, + y_avValue_snd_fst__h961051; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899, @@ -5219,103 +5219,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q151, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q168, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q191, - _theResult___exp__h734868, - _theResult___exp__h744519, - _theResult___exp__h753303, - _theResult___exp__h773721, - _theResult___exp__h783372, - _theResult___exp__h792156, - _theResult___exp__h813025, - _theResult___exp__h822676, - _theResult___exp__h831460, - _theResult___fst_exp__h719140, - _theResult___fst_exp__h734204, + _theResult___exp__h734865, + _theResult___exp__h744516, + _theResult___exp__h753300, + _theResult___exp__h773718, + _theResult___exp__h783369, + _theResult___exp__h792153, + _theResult___exp__h813022, + _theResult___exp__h822673, + _theResult___exp__h831457, + _theResult___fst_exp__h719137, + _theResult___fst_exp__h734201, + _theResult___fst_exp__h734207, _theResult___fst_exp__h734210, - _theResult___fst_exp__h734213, + _theResult___fst_exp__h734965, _theResult___fst_exp__h734968, - _theResult___fst_exp__h734971, - _theResult___fst_exp__h743790, - _theResult___fst_exp__h743855, + _theResult___fst_exp__h743787, + _theResult___fst_exp__h743852, + _theResult___fst_exp__h743858, _theResult___fst_exp__h743861, - _theResult___fst_exp__h743864, + _theResult___fst_exp__h744616, _theResult___fst_exp__h744619, - _theResult___fst_exp__h744622, - _theResult___fst_exp__h752575, - _theResult___fst_exp__h752614, + _theResult___fst_exp__h752572, + _theResult___fst_exp__h752611, + _theResult___fst_exp__h752617, _theResult___fst_exp__h752620, - _theResult___fst_exp__h752623, + _theResult___fst_exp__h753400, _theResult___fst_exp__h753403, - _theResult___fst_exp__h753406, + _theResult___fst_exp__h753412, _theResult___fst_exp__h753415, - _theResult___fst_exp__h753418, - _theResult___fst_exp__h757993, - _theResult___fst_exp__h773057, + _theResult___fst_exp__h757990, + _theResult___fst_exp__h773054, + _theResult___fst_exp__h773060, _theResult___fst_exp__h773063, - _theResult___fst_exp__h773066, + _theResult___fst_exp__h773818, _theResult___fst_exp__h773821, - _theResult___fst_exp__h773824, - _theResult___fst_exp__h782643, - _theResult___fst_exp__h782708, + _theResult___fst_exp__h782640, + _theResult___fst_exp__h782705, + _theResult___fst_exp__h782711, _theResult___fst_exp__h782714, - _theResult___fst_exp__h782717, + _theResult___fst_exp__h783469, _theResult___fst_exp__h783472, - _theResult___fst_exp__h783475, - _theResult___fst_exp__h791428, - _theResult___fst_exp__h791467, + _theResult___fst_exp__h791425, + _theResult___fst_exp__h791464, + _theResult___fst_exp__h791470, _theResult___fst_exp__h791473, - _theResult___fst_exp__h791476, + _theResult___fst_exp__h792253, _theResult___fst_exp__h792256, - _theResult___fst_exp__h792259, + _theResult___fst_exp__h792265, _theResult___fst_exp__h792268, - _theResult___fst_exp__h792271, - _theResult___fst_exp__h797297, - _theResult___fst_exp__h812361, + _theResult___fst_exp__h797294, + _theResult___fst_exp__h812358, + _theResult___fst_exp__h812364, _theResult___fst_exp__h812367, - _theResult___fst_exp__h812370, + _theResult___fst_exp__h813122, _theResult___fst_exp__h813125, - _theResult___fst_exp__h813128, - _theResult___fst_exp__h821947, - _theResult___fst_exp__h822012, + _theResult___fst_exp__h821944, + _theResult___fst_exp__h822009, + _theResult___fst_exp__h822015, _theResult___fst_exp__h822018, - _theResult___fst_exp__h822021, + _theResult___fst_exp__h822773, _theResult___fst_exp__h822776, - _theResult___fst_exp__h822779, - _theResult___fst_exp__h830732, - _theResult___fst_exp__h830771, + _theResult___fst_exp__h830729, + _theResult___fst_exp__h830768, + _theResult___fst_exp__h830774, _theResult___fst_exp__h830777, - _theResult___fst_exp__h830780, + _theResult___fst_exp__h831557, _theResult___fst_exp__h831560, - _theResult___fst_exp__h831563, + _theResult___fst_exp__h831569, _theResult___fst_exp__h831572, - _theResult___fst_exp__h831575, - _theResult___snd_fst_exp__h734974, - _theResult___snd_fst_exp__h753409, - _theResult___snd_fst_exp__h773827, - _theResult___snd_fst_exp__h792262, - _theResult___snd_fst_exp__h813131, - _theResult___snd_fst_exp__h831566, + _theResult___snd_fst_exp__h734971, + _theResult___snd_fst_exp__h753406, + _theResult___snd_fst_exp__h773824, + _theResult___snd_fst_exp__h792259, + _theResult___snd_fst_exp__h813128, + _theResult___snd_fst_exp__h831563, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q47, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q117, - din_inc___2_exp__h753463, - din_inc___2_exp__h753498, - din_inc___2_exp__h753524, - din_inc___2_exp__h792316, - din_inc___2_exp__h792351, - din_inc___2_exp__h792377, - din_inc___2_exp__h831620, - din_inc___2_exp__h831655, - din_inc___2_exp__h831681, - out_exp__h734871, - out_exp__h744522, - out_exp__h753306, - out_exp__h773724, - out_exp__h783375, - out_exp__h792159, - out_exp__h813028, - out_exp__h822679, - out_exp__h831463, - x__h996333; + din_inc___2_exp__h753460, + din_inc___2_exp__h753495, + din_inc___2_exp__h753521, + din_inc___2_exp__h792313, + din_inc___2_exp__h792348, + din_inc___2_exp__h792374, + din_inc___2_exp__h831617, + din_inc___2_exp__h831652, + din_inc___2_exp__h831678, + out_exp__h734868, + out_exp__h744519, + out_exp__h753303, + out_exp__h773721, + out_exp__h783372, + out_exp__h792156, + out_exp__h813025, + out_exp__h822676, + out_exp__h831460, + x__h996328; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3623; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771, @@ -5371,128 +5371,128 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q88, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q53, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q123, - _theResult___exp__h585008, - _theResult___exp__h593590, - _theResult___exp__h602774, - _theResult___exp__h611410, - _theResult___exp__h611512, - _theResult___exp__h630757, - _theResult___exp__h639339, - _theResult___exp__h648523, - _theResult___exp__h657159, - _theResult___exp__h657261, - _theResult___exp__h676504, - _theResult___exp__h685086, - _theResult___exp__h694270, - _theResult___exp__h702906, - _theResult___exp__h703008, - _theResult___fst_exp__h584492, - _theResult___fst_exp__h584557, + _theResult___exp__h585005, + _theResult___exp__h593587, + _theResult___exp__h602771, + _theResult___exp__h611407, + _theResult___exp__h611509, + _theResult___exp__h630754, + _theResult___exp__h639336, + _theResult___exp__h648520, + _theResult___exp__h657156, + _theResult___exp__h657258, + _theResult___exp__h676501, + _theResult___exp__h685083, + _theResult___exp__h694267, + _theResult___exp__h702903, + _theResult___exp__h703005, + _theResult___fst_exp__h584489, + _theResult___fst_exp__h584554, + _theResult___fst_exp__h584560, _theResult___fst_exp__h584563, - _theResult___fst_exp__h584566, - _theResult___fst_exp__h585089, - _theResult___fst_exp__h593139, + _theResult___fst_exp__h585086, + _theResult___fst_exp__h593136, + _theResult___fst_exp__h593142, _theResult___fst_exp__h593145, - _theResult___fst_exp__h593148, - _theResult___fst_exp__h593671, - _theResult___fst_exp__h602258, - _theResult___fst_exp__h602323, + _theResult___fst_exp__h593668, + _theResult___fst_exp__h602255, + _theResult___fst_exp__h602320, + _theResult___fst_exp__h602326, _theResult___fst_exp__h602329, - _theResult___fst_exp__h602332, - _theResult___fst_exp__h602855, - _theResult___fst_exp__h610895, - _theResult___fst_exp__h610934, + _theResult___fst_exp__h602852, + _theResult___fst_exp__h610892, + _theResult___fst_exp__h610931, + _theResult___fst_exp__h610937, _theResult___fst_exp__h610940, - _theResult___fst_exp__h610943, - _theResult___fst_exp__h611491, + _theResult___fst_exp__h611488, + _theResult___fst_exp__h611497, _theResult___fst_exp__h611500, - _theResult___fst_exp__h611503, - _theResult___fst_exp__h630241, - _theResult___fst_exp__h630306, + _theResult___fst_exp__h630238, + _theResult___fst_exp__h630303, + _theResult___fst_exp__h630309, _theResult___fst_exp__h630312, - _theResult___fst_exp__h630315, - _theResult___fst_exp__h630838, - _theResult___fst_exp__h638888, + _theResult___fst_exp__h630835, + _theResult___fst_exp__h638885, + _theResult___fst_exp__h638891, _theResult___fst_exp__h638894, - _theResult___fst_exp__h638897, - _theResult___fst_exp__h639420, - _theResult___fst_exp__h648007, - _theResult___fst_exp__h648072, + _theResult___fst_exp__h639417, + _theResult___fst_exp__h648004, + _theResult___fst_exp__h648069, + _theResult___fst_exp__h648075, _theResult___fst_exp__h648078, - _theResult___fst_exp__h648081, - _theResult___fst_exp__h648604, - _theResult___fst_exp__h656644, - _theResult___fst_exp__h656683, + _theResult___fst_exp__h648601, + _theResult___fst_exp__h656641, + _theResult___fst_exp__h656680, + _theResult___fst_exp__h656686, _theResult___fst_exp__h656689, - _theResult___fst_exp__h656692, - _theResult___fst_exp__h657240, + _theResult___fst_exp__h657237, + _theResult___fst_exp__h657246, _theResult___fst_exp__h657249, - _theResult___fst_exp__h657252, - _theResult___fst_exp__h675988, - _theResult___fst_exp__h676053, + _theResult___fst_exp__h675985, + _theResult___fst_exp__h676050, + _theResult___fst_exp__h676056, _theResult___fst_exp__h676059, - _theResult___fst_exp__h676062, - _theResult___fst_exp__h676585, - _theResult___fst_exp__h684635, + _theResult___fst_exp__h676582, + _theResult___fst_exp__h684632, + _theResult___fst_exp__h684638, _theResult___fst_exp__h684641, - _theResult___fst_exp__h684644, - _theResult___fst_exp__h685167, - _theResult___fst_exp__h693754, - _theResult___fst_exp__h693819, + _theResult___fst_exp__h685164, + _theResult___fst_exp__h693751, + _theResult___fst_exp__h693816, + _theResult___fst_exp__h693822, _theResult___fst_exp__h693825, - _theResult___fst_exp__h693828, - _theResult___fst_exp__h694351, - _theResult___fst_exp__h702391, - _theResult___fst_exp__h702430, + _theResult___fst_exp__h694348, + _theResult___fst_exp__h702388, + _theResult___fst_exp__h702427, + _theResult___fst_exp__h702433, _theResult___fst_exp__h702436, - _theResult___fst_exp__h702439, - _theResult___fst_exp__h702987, + _theResult___fst_exp__h702984, + _theResult___fst_exp__h702993, _theResult___fst_exp__h702996, - _theResult___fst_exp__h702999, - _theResult___snd_fst_exp__h593674, - _theResult___snd_fst_exp__h611494, - _theResult___snd_fst_exp__h639423, - _theResult___snd_fst_exp__h657243, - _theResult___snd_fst_exp__h685170, - _theResult___snd_fst_exp__h702990, - din_inc___2_exp__h611525, - din_inc___2_exp__h611549, - din_inc___2_exp__h611579, - din_inc___2_exp__h611603, - din_inc___2_exp__h657274, - din_inc___2_exp__h657298, - din_inc___2_exp__h657328, - din_inc___2_exp__h657352, - din_inc___2_exp__h703021, - din_inc___2_exp__h703045, - din_inc___2_exp__h703075, - din_inc___2_exp__h703099, - f1_exp14825_MINUS_127__q147, - f1_exp__h714825, - f2_exp53819_MINUS_127__q187, - f2_exp__h753819, - f3_exp93123_MINUS_127__q164, - f3_exp__h793123, - out_exp__h585011, - out_exp__h593593, - out_exp__h602777, - out_exp__h611413, - out_exp__h630760, - out_exp__h639342, - out_exp__h648526, - out_exp__h657162, - out_exp__h676507, - out_exp__h685089, - out_exp__h694273, - out_exp__h702909, - out_f_exp__h611789, - out_f_exp__h657538, - out_f_exp__h703285, - x__h852690; + _theResult___snd_fst_exp__h593671, + _theResult___snd_fst_exp__h611491, + _theResult___snd_fst_exp__h639420, + _theResult___snd_fst_exp__h657240, + _theResult___snd_fst_exp__h685167, + _theResult___snd_fst_exp__h702987, + din_inc___2_exp__h611522, + din_inc___2_exp__h611546, + din_inc___2_exp__h611576, + din_inc___2_exp__h611600, + din_inc___2_exp__h657271, + din_inc___2_exp__h657295, + din_inc___2_exp__h657325, + din_inc___2_exp__h657349, + din_inc___2_exp__h703018, + din_inc___2_exp__h703042, + din_inc___2_exp__h703072, + din_inc___2_exp__h703096, + f1_exp14822_MINUS_127__q147, + f1_exp__h714822, + f2_exp53816_MINUS_127__q187, + f2_exp__h753816, + f3_exp93120_MINUS_127__q164, + f3_exp__h793120, + out_exp__h585008, + out_exp__h593590, + out_exp__h602774, + out_exp__h611410, + out_exp__h630757, + out_exp__h639339, + out_exp__h648523, + out_exp__h657159, + out_exp__h676504, + out_exp__h685086, + out_exp__h694270, + out_exp__h702906, + out_f_exp__h611786, + out_f_exp__h657535, + out_f_exp__h703282, + x__h852687; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8202_BI_ETC___d19240, NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17161, - x__h244610, - x__h997059; + x__h244608, + x__h997054; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749, @@ -5519,19 +5519,19 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d23934, fetchStage_pipelines_0_first__0049_BIT_167_037_ETC___d20398, fetchStage_pipelines_1_first__0058_BIT_167_132_ETC___d21348, - x__h127310, - x__h140226, - x__h183487, - x__h202238, - x__h216804, - x__h865712, - x__h866260, - x__h904334, - x__h904882, - x__h992421, - x__h997033, - x__h997690, - x__h998377; + x__h127309, + x__h140225, + x__h183486, + x__h202237, + x__h216803, + x__h865709, + x__h866257, + x__h904330, + x__h904878, + x__h992416, + x__h997028, + x__h997685, + x__h998372; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__9739_B_ETC___d19883, IF_IF_coreFix_aluExe_0_exeToFinQ_first__9739_B_ETC___d19884, IF_IF_coreFix_aluExe_1_exeToFinQ_first__7660_B_ETC___d17805, @@ -5574,51 +5574,51 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291, - cause_code__h994330, + cause_code__h994325, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138, - fflags__h1011197, - r1__read__h854478, - res_fflags__h568166, - res_fflags__h613920, - res_fflags__h659667, + fflags__h1011192, + r1__read__h854475, + res_fflags__h568163, + res_fflags__h613917, + res_fflags__h659664, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18985, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16601, - x__h148960, - x__h152094, - x__h249407, - x__h249419, - x__h249431, - x__h249443, - x__h249455, - x__h249467, - x__h249479, - x__h249491, - x__h249503, - x__h249515, - x__h249527, - x__h249539, - x__h249551, - x__h249563, - x__h249575, - y__h249408, - y__h249420, - y__h249432, - y__h249444, - y__h249456, - y__h249468, - y__h249480, - y__h249492, - y__h249504, - y__h249516, - y__h249528, - y__h249540, - y__h249552, - y__h249564, - y__h249576, - y_avValue_snd_fst__h1010675, - y_avValue_snd_fst__h1011257, - y_avValue_snd_fst__h1011286; + x__h148959, + x__h152093, + x__h249405, + x__h249417, + x__h249429, + x__h249441, + x__h249453, + x__h249465, + x__h249477, + x__h249489, + x__h249501, + x__h249513, + x__h249525, + x__h249537, + x__h249549, + x__h249561, + x__h249573, + y__h249406, + y__h249418, + y__h249430, + y__h249442, + y__h249454, + y__h249466, + y__h249478, + y__h249490, + y__h249502, + y__h249514, + y__h249526, + y__h249538, + y__h249550, + y__h249562, + y__h249574, + y_avValue_snd_fst__h1010670, + y_avValue_snd_fst__h1011252, + y_avValue_snd_fst__h1011281; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8202__ETC___d19237, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5590__ETC___d17158, IF_IF_renameStage_rg_m_halt_req_0076_BIT_4_007_ETC___d20759, @@ -5663,7 +5663,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3378, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3421, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3620, - vm_mode_reg__read__h853854; + vm_mode_reg__read__h853851; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18892, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18893, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16508, @@ -5680,54 +5680,54 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3577, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7078, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d23867, - _theResult_____2__h515296, - dcsr_cause__h991836, - next_deqP___1__h515541, - repBound__h237262, - repBound__h238947, - repBound__h248150, - repBound__h248675, - repBound__h856058, - repBound__h859402, - repBound__h859420, - repBound__h865966, - repBound__h866514, - repBound__h896085, - repBound__h898412, - repBound__h898430, - repBound__h904588, - repBound__h905136, - repBound__h995071, - repBound__h997124, - repBound__h997781, - tb__h865963, - tb__h866511, - tb__h904585, - tb__h905133, - tmp_expBotHalf__h127265, - tmp_expBotHalf__h140181, - tmp_expBotHalf__h183442, - tmp_expBotHalf__h202193, - tmp_expBotHalf__h216759, - tmp_expBotHalf__h865666, - tmp_expBotHalf__h866214, - tmp_expBotHalf__h904288, - tmp_expBotHalf__h904836, - tmp_expBotHalf__h992376, - tmp_expTopHalf__h127263, - tmp_expTopHalf__h140179, - tmp_expTopHalf__h183440, - tmp_expTopHalf__h202191, - tmp_expTopHalf__h216757, - tmp_expTopHalf__h865664, - tmp_expTopHalf__h866212, - tmp_expTopHalf__h904286, - tmp_expTopHalf__h904834, - tmp_expTopHalf__h992374, - v__h514752, - v__h514947, - x__h521603, - x_decodeInfo_frm__h923974; + _theResult_____2__h515292, + dcsr_cause__h991831, + next_deqP___1__h515537, + repBound__h237261, + repBound__h238946, + repBound__h248148, + repBound__h248673, + repBound__h856055, + repBound__h859399, + repBound__h859417, + repBound__h865963, + repBound__h866511, + repBound__h896081, + repBound__h898408, + repBound__h898426, + repBound__h904584, + repBound__h905132, + repBound__h995066, + repBound__h997119, + repBound__h997776, + tb__h865960, + tb__h866508, + tb__h904581, + tb__h905129, + tmp_expBotHalf__h127264, + tmp_expBotHalf__h140180, + tmp_expBotHalf__h183441, + tmp_expBotHalf__h202192, + tmp_expBotHalf__h216758, + tmp_expBotHalf__h865663, + tmp_expBotHalf__h866211, + tmp_expBotHalf__h904284, + tmp_expBotHalf__h904832, + tmp_expBotHalf__h992371, + tmp_expTopHalf__h127262, + tmp_expTopHalf__h140178, + tmp_expTopHalf__h183439, + tmp_expTopHalf__h202190, + tmp_expTopHalf__h216756, + tmp_expTopHalf__h865661, + tmp_expTopHalf__h866209, + tmp_expTopHalf__h904282, + tmp_expTopHalf__h904830, + tmp_expTopHalf__h992369, + v__h514748, + v__h514943, + x__h521599, + x_decodeInfo_frm__h923969; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18833, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18834, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16449, @@ -5743,108 +5743,108 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16454, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3257, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3539, - IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50, - IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167, - IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75, - IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150, - IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85, - IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110, - IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190, - IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40, - IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120, - IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125, - IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55, - IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163, - IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170, - IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146, - IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77, - IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153, - IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90, - IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186, - IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112, - IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193, - IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42, - carry_out__h127401, - carry_out__h140317, - carry_out__h183578, - carry_out__h202329, - carry_out__h216895, - carry_out__h865815, - carry_out__h866363, - carry_out__h904437, - carry_out__h904985, - carry_out__h992512, + IF_sfdin02249_BIT_33_THEN_2_ELSE_0__q50, + IF_sfdin21938_BIT_4_THEN_2_ELSE_0__q167, + IF_sfdin30232_BIT_33_THEN_2_ELSE_0__q75, + IF_sfdin43781_BIT_4_THEN_2_ELSE_0__q150, + IF_sfdin47998_BIT_33_THEN_2_ELSE_0__q85, + IF_sfdin75979_BIT_33_THEN_2_ELSE_0__q110, + IF_sfdin82634_BIT_4_THEN_2_ELSE_0__q190, + IF_sfdin84483_BIT_33_THEN_2_ELSE_0__q40, + IF_sfdin93745_BIT_33_THEN_2_ELSE_0__q120, + IF_theResult___snd02382_BIT_33_THEN_2_ELSE_0__q125, + IF_theResult___snd10886_BIT_33_THEN_2_ELSE_0__q55, + IF_theResult___snd12318_BIT_4_THEN_2_ELSE_0__q163, + IF_theResult___snd30723_BIT_4_THEN_2_ELSE_0__q170, + IF_theResult___snd34161_BIT_4_THEN_2_ELSE_0__q146, + IF_theResult___snd38845_BIT_33_THEN_2_ELSE_0__q77, + IF_theResult___snd52566_BIT_4_THEN_2_ELSE_0__q153, + IF_theResult___snd56635_BIT_33_THEN_2_ELSE_0__q90, + IF_theResult___snd73014_BIT_4_THEN_2_ELSE_0__q186, + IF_theResult___snd84592_BIT_33_THEN_2_ELSE_0__q112, + IF_theResult___snd91419_BIT_4_THEN_2_ELSE_0__q193, + IF_theResult___snd93096_BIT_33_THEN_2_ELSE_0__q42, + carry_out__h127400, + carry_out__h140316, + carry_out__h183577, + carry_out__h202328, + carry_out__h216894, + carry_out__h865812, + carry_out__h866360, + carry_out__h904433, + carry_out__h904981, + carry_out__h992507, coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, coreFix_memExe_regToExeQfirst_BITS_222_TO_221__q2, coreFix_memExe_regToExeQfirst_BITS_59_TO_58__q4, - cr_reserved__h865501, - cr_reserved__h866049, - cr_reserved__h904123, - cr_reserved__h904671, - guard__h576391, - guard__h585100, - guard__h594030, - guard__h602866, - guard__h622142, - guard__h630849, - guard__h639779, - guard__h648615, - guard__h667889, - guard__h676596, - guard__h685526, - guard__h694362, - guard__h726252, - guard__h735564, - guard__h744633, - guard__h765105, - guard__h774417, - guard__h783486, - guard__h804409, - guard__h813721, - guard__h822790, - impliedTopBits__h127403, - impliedTopBits__h140319, - impliedTopBits__h183580, - impliedTopBits__h202331, - impliedTopBits__h216897, - impliedTopBits__h865817, - impliedTopBits__h866365, - impliedTopBits__h904439, - impliedTopBits__h904987, - impliedTopBits__h992514, - len_correction__h127402, - len_correction__h140318, - len_correction__h183579, - len_correction__h202330, - len_correction__h216896, - len_correction__h865816, - len_correction__h866364, - len_correction__h904438, - len_correction__h904986, - len_correction__h992513, - prv__h1012290, - prv__h1012334, - r1__read_BITS_13_TO_12___h924176, - sbIdx__h151985, - v__h836568, - v__h836578, - v__h837213, - wordIdx__h263159, - x__h1007669, - x__h1011445, - x__h127487, - x__h140403, - x__h183664, - x__h202415, - x__h216981, - x__h865902, - x__h866450, - x__h904524, - x__h905072, - x__h992598, - y_avValue_snd_snd_snd_fst__h1010685, - y_avValue_snd_snd_snd_fst__h1011267, - y_avValue_snd_snd_snd_fst__h1011296; + cr_reserved__h865498, + cr_reserved__h866046, + cr_reserved__h904119, + cr_reserved__h904667, + guard__h576388, + guard__h585097, + guard__h594027, + guard__h602863, + guard__h622139, + guard__h630846, + guard__h639776, + guard__h648612, + guard__h667886, + guard__h676593, + guard__h685523, + guard__h694359, + guard__h726249, + guard__h735561, + guard__h744630, + guard__h765102, + guard__h774414, + guard__h783483, + guard__h804406, + guard__h813718, + guard__h822787, + impliedTopBits__h127402, + impliedTopBits__h140318, + impliedTopBits__h183579, + impliedTopBits__h202330, + impliedTopBits__h216896, + impliedTopBits__h865814, + impliedTopBits__h866362, + impliedTopBits__h904435, + impliedTopBits__h904983, + impliedTopBits__h992509, + len_correction__h127401, + len_correction__h140317, + len_correction__h183578, + len_correction__h202329, + len_correction__h216895, + len_correction__h865813, + len_correction__h866361, + len_correction__h904434, + len_correction__h904982, + len_correction__h992508, + prv__h1012285, + prv__h1012329, + r1__read_BITS_13_TO_12___h924171, + sbIdx__h151984, + v__h836565, + v__h836575, + v__h837210, + wordIdx__h263157, + x__h1007664, + x__h1011440, + x__h127486, + x__h140402, + x__h183663, + x__h202414, + x__h216980, + x__h865899, + x__h866447, + x__h904520, + x__h905068, + x__h992593, + y_avValue_snd_snd_snd_fst__h1010680, + y_avValue_snd_snd_snd_fst__h1011262, + y_avValue_snd_snd_snd_fst__h1011291; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10571, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10621, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11968, @@ -6561,12 +6561,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h526073, - _theResult_____2__h533166, - _theResult_____2__h543801, - _theResult_____2__h557634, - _theResult_____2__h561413, - cause_interrupt__h992790, + _theResult_____2__h526069, + _theResult_____2__h533162, + _theResult_____2__h543797, + _theResult_____2__h557630, + _theResult_____2__h561409, + cause_interrupt__h992785, commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22272, commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22279, commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22384, @@ -6950,10 +6950,10 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095, coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d22810, - cr_flags__h865500, - cr_flags__h866048, - cr_flags__h904122, - cr_flags__h904670, + cr_flags__h865497, + cr_flags__h866045, + cr_flags__h904118, + cr_flags__h904666, csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128, @@ -6996,27 +6996,27 @@ module mkCore(CLK, fetchStage_pipelines_1_first__0058_BITS_267_TO_ETC___d21659, fetchStage_pipelines_1_first__0058_BITS_267_TO_ETC___d21945, fetchStage_pipelines_1_first__0058_BITS_272_TO_ETC___d21670, - guard__h594628, - guard__h640377, - guard__h686124, - guard__h736162, - guard__h775015, - guard__h814319, - idx__h966426, - k__h942684, + guard__h594625, + guard__h640374, + guard__h686121, + guard__h736159, + guard__h775012, + guard__h814316, + idx__h966421, + k__h942679, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20461, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20853, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20873, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21779, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21781, - next_deqP___1__h526318, - next_deqP___1__h533596, - next_deqP___1__h544231, - next_deqP___1__h557879, - next_deqP___1__h561658, - r1__read_BIT_20___h924682, - r__h852737, - r__h854224, + next_deqP___1__h526314, + next_deqP___1__h533592, + next_deqP___1__h544227, + next_deqP___1__h557875, + next_deqP___1__h561654, + r1__read_BIT_20___h924677, + r__h852734, + r__h854221, regRenamingTable_RDY_rename_0_getRename__0810__ETC___d20821, regRenamingTable_RDY_rename_0_getRename__0810__ETC___d21625, regRenamingTable_rename_0_canRename__0933_AND__ETC___d20962, @@ -7060,20 +7060,20 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12424, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12425, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2762, - v__h516772, - v__h517152, - v__h532491, - v__h532686, - v__h534940, - v__h535135, - v__h555960, - v__h556155, - v__h559739, - v__h559934, - x__h240082, - x__h241239, - x__h254848, - x__h836069; + v__h516768, + v__h517148, + v__h532487, + v__h532682, + v__h534936, + v__h535131, + v__h555956, + v__h556151, + v__h559735, + v__h559930, + x__h240081, + x__h241238, + x__h254846, + x__h836066; // action method coreReq_start assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; @@ -11105,7 +11105,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; assign MUX_rg_core_run_state$write_1__SEL_4 = WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -11133,15 +11133,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h987208, + addr__h987203, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q323, rob$deqPort_0_deq_data[501:470] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1011220 ; + commitStage_rg_serial_num + y__h1011215 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h942684 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h942679 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786) ? { fetchStage$pipelines_0_first[272:268], IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d20175, @@ -11159,7 +11159,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11267,7 +11267,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h501025 } ; + x__h501022 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7018 } ; @@ -11277,7 +11277,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h505543, + addr__h505540, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7126 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11294,12 +11294,12 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : coreFix_memExe_reqLrScAmoQ_data_0_rl ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h148960, - addr__h148408, + { x__h148959, + addr__h148407, 158'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h152094, - addr__h151984, + { x__h152093, + addr__h151983, 158'h32AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 = { 1'd1, @@ -11309,7 +11309,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h509039, + resp_addr__h509036, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11317,8 +11317,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1012334, - prv__h1012334 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1012329, + prv__h1012329 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11387,39 +11387,39 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4873 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h912383, - new_pc__h909836, + { x__h912378, + new_pc__h909831, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h912383, - new_pc__h909836, + { x__h912378, + new_pc__h909831, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h878730, - new_pc__h871752, + { x__h878726, + new_pc__h871748, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h878730, - new_pc__h871752, + { x__h878726, + new_pc__h871748, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1011197 ; + csrf_fflags_reg | fflags__h1011192 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__2032_BIT_288_2701_T_ETC___d22795 == 6'd1) ? @@ -11468,9 +11468,9 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1008993 + 64'd1 ; + n__read__h1008988 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1008993 + { 62'd0, x__h1011445 } ; + n__read__h1008988 + { 62'd0, x__h1011440 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2032_BIT_288_2701_T_ETC___d22795 == @@ -11478,11 +11478,11 @@ module mkCore(CLK, MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h994512 or trap_val__h994359) + always@(commitStage_commitTrap or trap_val__h994507 or trap_val__h994354) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994512; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994359; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994507; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_2 = trap_val__h994354; default: MUX_csrf_mtval_csr$write_1__VAL_2 = 64'd0; endcase end @@ -11504,7 +11504,7 @@ module mkCore(CLK, 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1007669 : + x__h1007664 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? @@ -11513,29 +11513,29 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h991836, + dcsr_cause__h991831, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = { csrf_rg_dpc[152], - pointer__h1005920, - x__h1005944[13:0], + pointer__h1005915, + x__h1005939[13:0], csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = { commitStage_commitTrap[237], - pc_address__h992211, - pc_addrBits__h992212, + pc_address__h992206, + pc_addrBits__h992207, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351, - x__h992581, - x__h992601 } ; + x__h992576, + x__h992596 } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { csrf_rg_dpc[152], - pointer__h1025233, - x__h1025256[13:0], + pointer__h1025227, + x__h1025250[13:0], csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = @@ -11546,7 +11546,7 @@ module mkCore(CLK, 6'd19) && MUX_csrf_rg_tselect$write_1__VAL_2[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1014871 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1014865 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11562,14 +11562,14 @@ module mkCore(CLK, IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677[14:3], ~IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677[2], IF_IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_I_ETC___d22677[1:0], - thin_address__h996854 } ; + thin_address__h996849 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1007609 or v__h1007648 or v__h1008101) + next_pc__h1007604 or v__h1007643 or v__h1008096) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1007648; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1008101; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1007609; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1007643; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1008096; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1007604; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11616,38 +11616,38 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h567273, - res_addrBits__h567274, + res_address__h567269, + res_addrBits__h567270, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, - res_address__h568125, - res_addrBits__h568126, + res_address__h568122, + res_addrBits__h568123, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_3 = { 1'd0, - res_address__h613882, - res_addrBits__h613883, + res_address__h613879, + res_addrBits__h613880, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_4 = { 1'd0, - res_address__h659629, - res_addrBits__h659630, + res_address__h659626, + res_addrBits__h659627, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_5 = { 1'd0, - res_address__h705438, - res_addrBits__h705439, + res_address__h705435, + res_addrBits__h705436, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_6 = { 1'd0, - res_address__h706298, - res_addrBits__h706299, + res_address__h706295, + res_addrBits__h706296, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_3_wr_2__VAL_1 = { coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h126791, - res_addrBits__h126792, + res_address__h126790, + res_addrBits__h126791, coreFix_memExe_respLrScAmoQ_data_0[127:112], coreFix_memExe_respLrScAmoQ_data_0[109], coreFix_memExe_respLrScAmoQ_data_0[111:110], @@ -11655,8 +11655,8 @@ module mkCore(CLK, IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 } ; assign MUX_rf$write_3_wr_2__VAL_2 = { mmio_dataRespQ_data_0[128], - res_address__h139703, - res_addrBits__h139704, + res_address__h139702, + res_addrBits__h139703, mmio_dataRespQ_data_0[127:112], mmio_dataRespQ_data_0[109], mmio_dataRespQ_data_0[111:110], @@ -11665,27 +11665,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h178866, - res_addrBits__h178867, - x__h183367[127:112], - x__h183367[109], - x__h183367[111:110], - ~x__h183367[108:90], + res_address__h178865, + res_addrBits__h178866, + x__h183366[127:112], + x__h183366[109], + x__h183366[111:110], + ~x__h183366[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h197631, - res_addrBits__h197632, - x__h199219[127:112], - x__h199219[109], - x__h199219[111:110], - ~x__h199219[108:90], + res_address__h197630, + res_addrBits__h197631, + x__h199218[127:112], + x__h199218[109], + x__h199218[111:110], + ~x__h199218[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h216390, - res_addrBits__h216391, + res_address__h216389, + res_addrBits__h216390, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -11693,13 +11693,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1013598, - data_addrBits__h1013599, + data_address__h1013592, + data_addrBits__h1013593, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1014452, - data_addrBits__h1014453, + data_address__h1014446, + data_addrBits__h1014447, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[590:462], @@ -11752,24 +11752,24 @@ module mkCore(CLK, fetchStage$pipelines_0_first[76:70], 163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, fetchStage_pipelines_0_first__0049_BIT_167_037_ETC___d20927 } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h568166 ; + res_fflags__h568163 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h613920 ; + res_fflags__h613917 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h659667 ; + res_fflags__h659664 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12177,8 +12177,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h837213 : - v__h836568 ; + v__h837210 : + v__h836565 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -12276,7 +12276,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h515296 ; + _theResult_____2__h515292 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12295,7 +12295,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h514752 ; + v__h514748 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12337,7 +12337,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h526073 ; + _theResult_____2__h526069 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12356,7 +12356,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h516772 ; + v__h516768 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12453,7 +12453,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h533166 ; + _theResult_____2__h533162 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12469,7 +12469,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h532491 ; + v__h532487 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12489,7 +12489,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h535302, + { x_addr__h535298, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12516,7 +12516,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h543801 ; + _theResult_____2__h543797 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12535,7 +12535,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h534940 ; + v__h534936 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12611,7 +12611,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h561413 ; + _theResult_____2__h561409 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12626,7 +12626,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h559739 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h559735 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12667,7 +12667,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h557634 ; + _theResult_____2__h557630 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12682,7 +12682,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h555960 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h555956 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13042,13 +13042,13 @@ module mkCore(CLK, always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h992792 or + cause_code__h992787 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h992792; + csrf_mcause_code_reg$D_IN = cause_code__h992787; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; @@ -13068,14 +13068,14 @@ module mkCore(CLK, always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_interrupt__h992790 or + cause_interrupt__h992785 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[63]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h992790; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h992785; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; @@ -13251,7 +13251,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3035 : - n__read__h1008993 ; + n__read__h1008988 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13602,13 +13602,13 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h992792 or + cause_code__h992787 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h992792; + csrf_scause_code_reg$D_IN = cause_code__h992787; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; @@ -13628,14 +13628,14 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_interrupt__h992790 or + cause_interrupt__h992785 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[63]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h992790; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h992785; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; @@ -14802,7 +14802,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h942684 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h942679 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786) ? { fetchStage$pipelines_0_first[272:268], IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d20175, @@ -14820,7 +14820,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[328:305], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15299,19 +15299,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h836055 : - a__h835633 ; + _theResult___fst__h836052 : + a__h835630 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h835634 == 64'd0, - a__h835633, + { b__h835631 == 64'd0, + a__h835630, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h836069, - a__h835633[63], + x__h836066, + a__h835630[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h836056 : - b__h835634 ; + _theResult___snd__h836053 : + b__h835631 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && @@ -15372,20 +15372,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835633 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835634 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835630 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835631 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h835633 ; + a__h835630 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h835634 ; + b__h835631 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h835633 ; + a__h835630 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h835634 ; + b__h835631 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -15414,9 +15414,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q366, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h714355, - x__h714356, - x__h714357, + x__h714352, + x__h714353, + x__h714354, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19990 ; @@ -15468,7 +15468,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0058_BITS_267_ETC___d21125, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15622,7 +15622,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h501025 ; + x__h501022 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0) ? @@ -16054,7 +16054,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__0933_AND__ETC___d21830) ? specTagManager$currentSpecBits : - renaming_spec_bits__h966287 ; + renaming_spec_bits__h966282 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__0933_AND__ETC___d21839) ? @@ -16074,7 +16074,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__0933_AND__ETC___d21839) ? specTagManager$currentSpecBits : - renaming_spec_bits__h966287 ; + renaming_spec_bits__h966282 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16103,8 +16103,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h212809 : - t__h215095 ; + t__h212808 : + t__h215094 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16157,7 +16157,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[2], IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[1:0], coreFix_memExe_regToExeQ$first[217:154] } : - { pointer__h242569[3:0] == 4'd0 && + { pointer__h242568[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16327,7 +16327,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[238], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h966287, + renaming_spec_bits__h966282, fetchStage$pipelines_1_first[267:265] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16740,9 +16740,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h871752 or + new_pc__h871748 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h909836 or + new_pc__h909831 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -16753,9 +16753,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h871752; + fetchStage$redirect_pc = new_pc__h871748; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h909836; + fetchStage$redirect_pc = new_pc__h909831; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -16945,7 +16945,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h966287 ; + renaming_spec_bits__h966282 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17222,7 +17222,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0058_BITS_264_ETC___d21959, IF_NOT_fetchStage_pipelines_1_first__0058_BITS_ETC___d22013, 7'd32, - renaming_spec_bits__h966287 } ; + renaming_spec_bits__h966282 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17232,24 +17232,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 14'd2730; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 14'd11589; @@ -17306,29 +17306,29 @@ module mkCore(CLK, always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or - data__h567607 or + data__h567604 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or - data__h613367 or + data__h613364 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or - data__h659114 or + data__h659111 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or - data__h704928 or - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705791) + data__h704925 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705788) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567607; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567604; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613367; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613364; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659114; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659111; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h704928; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h704925; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705791; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705788; default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -17497,16 +17497,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -17785,11 +17785,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h854224 }), + .amoExec_current({ 128'd0, r__h854221 }), .amoExec_inpt({ 97'd0, x__h65608 }), .amoExec(amoExec___d773)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h263159), + .amoExec_wordIdx(wordIdx__h263157), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4836, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849 } }), @@ -17806,12 +17806,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h923974, - r1__read_BITS_13_TO_12___h924176 != + .checkForException_csrState({ x_decodeInfo_frm__h923969, + r1__read_BITS_13_TO_12___h924171 != 2'd0, - { prv__h1012290, + { prv__h1012285, csrf_tvm_reg, - { r1__read_BIT_20___h924682, + { r1__read_BIT_20___h924677, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17837,12 +17837,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h923974, - r1__read_BITS_13_TO_12___h924176 != + .checkForException_csrState({ x_decodeInfo_frm__h923969, + r1__read_BITS_13_TO_12___h924171 != 2'd0, - { prv__h1012290, + { prv__h1012285, csrf_tvm_reg, - { r1__read_BIT_20___h924682, + { r1__read_BIT_20___h924677, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17853,14 +17853,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h960829), + .checkForException_pcc(pc__h960824), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21375)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[383:221]), .capChecks_b(coreFix_memExe_regToExeQ$first[220:58]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h248675, + repBound__h248673, { csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 } }), @@ -17871,20 +17871,20 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[220:58]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h248675, + repBound__h248673, { csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125, csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126, csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h242768), - .prepareBoundsCheck_size(x__h249407 + - y__h249408), + .prepareBoundsCheck_vaddr(tmpAddr__h242767), + .prepareBoundsCheck_size(x__h249405 + + y__h249406), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[57:12]), .prepareBoundsCheck(prepareBoundsCheck___d4226)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q278, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h714446), - .execFpuSimple_rVal2(rVal2__h714447), + .execFpuSimple_rVal1(rVal1__h714443), + .execFpuSimple_rVal2(rVal2__h714444), .execFpuSimple(execFpuSimple___d15189)); module_basicExec instance_basicExec_8(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[821:817], CASE_coreFix_aluExe_1_regToExeQfirst_BITS_816_ETC__q280, @@ -17897,24 +17897,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h865497, - cr_addrBits__h865498, + { cr_address__h865494, + cr_addrBits__h865495, { coreFix_aluExe_1_regToExeQ$first[305:290], - { cr_flags__h865500, - cr_reserved__h865501 }, + { cr_flags__h865497, + cr_reserved__h865498 }, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17485 } }, - repBound__h865966, + repBound__h865963, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17492, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17493, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17505 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h866045, - cr_addrBits__h866046, + { cr_address__h866042, + cr_addrBits__h866043, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h866048, - cr_reserved__h866049 }, + { cr_flags__h866045, + cr_reserved__h866046 }, INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17549 } }, - repBound__h866514, + repBound__h866511, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17556, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17557, IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17569 } }), @@ -17931,24 +17931,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h904119, - cr_addrBits__h904120, + { cr_address__h904115, + cr_addrBits__h904116, { coreFix_aluExe_0_regToExeQ$first[305:290], - { cr_flags__h904122, - cr_reserved__h904123 }, + { cr_flags__h904118, + cr_reserved__h904119 }, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19564 } }, - repBound__h904588, + repBound__h904584, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19571, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19572, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19584 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h904667, - cr_addrBits__h904668, + { cr_address__h904663, + cr_addrBits__h904664, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h904670, - cr_reserved__h904671 }, + { cr_flags__h904666, + cr_reserved__h904667 }, INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19628 } }, - repBound__h905136, + repBound__h905132, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19635, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19636, IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19648 } }), @@ -17956,1191 +17956,1191 @@ module mkCore(CLK, .basicExec(basicExec___d19652)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148 ? - _theResult___snd__h676051 : - _theResult____h667879 ; + _theResult___snd__h676048 : + _theResult____h667876 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354 ? - _theResult___snd__h584555 : - _theResult____h576381 ; + _theResult___snd__h584552 : + _theResult____h576378 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751 ? - _theResult___snd__h630304 : - _theResult____h622132 ; + _theResult___snd__h630301 : + _theResult____h622129 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030 ? - _theResult___snd__h743853 : - _theResult____h735554 ; + _theResult___snd__h743850 : + _theResult____h735551 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745 ? - _theResult___snd__h822010 : - _theResult____h813711 ; + _theResult___snd__h822007 : + _theResult____h813708 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515 ? - _theResult___snd__h782706 : - _theResult____h774407 ; + _theResult___snd__h782703 : + _theResult____h774404 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q119 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699 ? - _theResult___snd__h693817 : - _theResult____h685516 ; + _theResult___snd__h693814 : + _theResult____h685513 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q49 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905 ? - _theResult___snd__h602321 : - _theResult____h594020 ; + _theResult___snd__h602318 : + _theResult____h594017 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q84 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302 ? - _theResult___snd__h648070 : - _theResult____h639769 ; + _theResult___snd__h648067 : + _theResult____h639766 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718 ? - _theResult___snd__h734202 : + _theResult___snd__h734199 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080 ? - _theResult___snd__h734202 : - _theResult___snd__h752607 ; + _theResult___snd__h734199 : + _theResult___snd__h752604 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448 ? - _theResult___snd__h812359 : + _theResult___snd__h812356 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795 ? - _theResult___snd__h812359 : - _theResult___snd__h830764 ; + _theResult___snd__h812356 : + _theResult___snd__h830761 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218 ? - _theResult___snd__h773055 : + _theResult___snd__h773052 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565 ? - _theResult___snd__h773055 : - _theResult___snd__h791460 ; + _theResult___snd__h773052 : + _theResult___snd__h791457 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q111 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379 ? - _theResult___snd__h684633 : + _theResult___snd__h684630 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q124 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772 ? - _theResult___snd__h684633 : - _theResult___snd__h702423 ; + _theResult___snd__h684630 : + _theResult___snd__h702420 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q41 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585 ? - _theResult___snd__h593137 : + _theResult___snd__h593134 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q54 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978 ? - _theResult___snd__h593137 : - _theResult___snd__h610927 ; + _theResult___snd__h593134 : + _theResult___snd__h610924 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q76 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982 ? - _theResult___snd__h638886 : + _theResult___snd__h638883 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q89 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375 ? - _theResult___snd__h638886 : - _theResult___snd__h656676 ; + _theResult___snd__h638883 : + _theResult___snd__h656673 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10571 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - ((_theResult___fst_exp__h630241 == 8'd255) ? + ((_theResult___fst_exp__h630238 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556) : - ((_theResult___fst_exp__h638897 == 8'd255) ? + ((_theResult___fst_exp__h638894 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10621 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - ((_theResult___fst_exp__h630241 == 8'd255) ? + ((_theResult___fst_exp__h630238 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612) : - ((_theResult___fst_exp__h638897 == 8'd255) ? + ((_theResult___fst_exp__h638894 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11968 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - ((_theResult___fst_exp__h675988 == 8'd255) ? + ((_theResult___fst_exp__h675985 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953) : - ((_theResult___fst_exp__h684644 == 8'd255) ? + ((_theResult___fst_exp__h684641 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12018 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - ((_theResult___fst_exp__h675988 == 8'd255) ? + ((_theResult___fst_exp__h675985 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009) : - ((_theResult___fst_exp__h684644 == 8'd255) ? + ((_theResult___fst_exp__h684641 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9174 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - ((_theResult___fst_exp__h584492 == 8'd255) ? + ((_theResult___fst_exp__h584489 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159) : - ((_theResult___fst_exp__h593148 == 8'd255) ? + ((_theResult___fst_exp__h593145 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9224 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - ((_theResult___fst_exp__h584492 == 8'd255) ? + ((_theResult___fst_exp__h584489 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215) : - ((_theResult___fst_exp__h593148 == 8'd255) ? + ((_theResult___fst_exp__h593145 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 = - (_theResult____h667879[56] ? + (_theResult____h667876[56] ? 6'd0 : - (_theResult____h667879[55] ? + (_theResult____h667876[55] ? 6'd1 : - (_theResult____h667879[54] ? + (_theResult____h667876[54] ? 6'd2 : - (_theResult____h667879[53] ? + (_theResult____h667876[53] ? 6'd3 : - (_theResult____h667879[52] ? + (_theResult____h667876[52] ? 6'd4 : - (_theResult____h667879[51] ? + (_theResult____h667876[51] ? 6'd5 : - (_theResult____h667879[50] ? + (_theResult____h667876[50] ? 6'd6 : - (_theResult____h667879[49] ? + (_theResult____h667876[49] ? 6'd7 : - (_theResult____h667879[48] ? + (_theResult____h667876[48] ? 6'd8 : - (_theResult____h667879[47] ? + (_theResult____h667876[47] ? 6'd9 : - (_theResult____h667879[46] ? + (_theResult____h667876[46] ? 6'd10 : - (_theResult____h667879[45] ? + (_theResult____h667876[45] ? 6'd11 : - (_theResult____h667879[44] ? + (_theResult____h667876[44] ? 6'd12 : - (_theResult____h667879[43] ? + (_theResult____h667876[43] ? 6'd13 : - (_theResult____h667879[42] ? + (_theResult____h667876[42] ? 6'd14 : - (_theResult____h667879[41] ? + (_theResult____h667876[41] ? 6'd15 : - (_theResult____h667879[40] ? + (_theResult____h667876[40] ? 6'd16 : - (_theResult____h667879[39] ? + (_theResult____h667876[39] ? 6'd17 : - (_theResult____h667879[38] ? + (_theResult____h667876[38] ? 6'd18 : - (_theResult____h667879[37] ? + (_theResult____h667876[37] ? 6'd19 : - (_theResult____h667879[36] ? + (_theResult____h667876[36] ? 6'd20 : - (_theResult____h667879[35] ? + (_theResult____h667876[35] ? 6'd21 : - (_theResult____h667879[34] ? + (_theResult____h667876[34] ? 6'd22 : - (_theResult____h667879[33] ? + (_theResult____h667876[33] ? 6'd23 : - (_theResult____h667879[32] ? + (_theResult____h667876[32] ? 6'd24 : - (_theResult____h667879[31] ? + (_theResult____h667876[31] ? 6'd25 : - (_theResult____h667879[30] ? + (_theResult____h667876[30] ? 6'd26 : - (_theResult____h667879[29] ? + (_theResult____h667876[29] ? 6'd27 : - (_theResult____h667879[28] ? + (_theResult____h667876[28] ? 6'd28 : - (_theResult____h667879[27] ? + (_theResult____h667876[27] ? 6'd29 : - (_theResult____h667879[26] ? + (_theResult____h667876[26] ? 6'd30 : - (_theResult____h667879[25] ? + (_theResult____h667876[25] ? 6'd31 : - (_theResult____h667879[24] ? + (_theResult____h667876[24] ? 6'd32 : - (_theResult____h667879[23] ? + (_theResult____h667876[23] ? 6'd33 : - (_theResult____h667879[22] ? + (_theResult____h667876[22] ? 6'd34 : - (_theResult____h667879[21] ? + (_theResult____h667876[21] ? 6'd35 : - (_theResult____h667879[20] ? + (_theResult____h667876[20] ? 6'd36 : - (_theResult____h667879[19] ? + (_theResult____h667876[19] ? 6'd37 : - (_theResult____h667879[18] ? + (_theResult____h667876[18] ? 6'd38 : - (_theResult____h667879[17] ? + (_theResult____h667876[17] ? 6'd39 : - (_theResult____h667879[16] ? + (_theResult____h667876[16] ? 6'd40 : - (_theResult____h667879[15] ? + (_theResult____h667876[15] ? 6'd41 : - (_theResult____h667879[14] ? + (_theResult____h667876[14] ? 6'd42 : - (_theResult____h667879[13] ? + (_theResult____h667876[13] ? 6'd43 : - (_theResult____h667879[12] ? + (_theResult____h667876[12] ? 6'd44 : - (_theResult____h667879[11] ? + (_theResult____h667876[11] ? 6'd45 : - (_theResult____h667879[10] ? + (_theResult____h667876[10] ? 6'd46 : - (_theResult____h667879[9] ? + (_theResult____h667876[9] ? 6'd47 : - (_theResult____h667879[8] ? + (_theResult____h667876[8] ? 6'd48 : - (_theResult____h667879[7] ? + (_theResult____h667876[7] ? 6'd49 : - (_theResult____h667879[6] ? + (_theResult____h667876[6] ? 6'd50 : - (_theResult____h667879[5] ? + (_theResult____h667876[5] ? 6'd51 : - (_theResult____h667879[4] ? + (_theResult____h667876[4] ? 6'd52 : - (_theResult____h667879[3] ? + (_theResult____h667876[3] ? 6'd53 : - (_theResult____h667879[2] ? + (_theResult____h667876[2] ? 6'd54 : - (_theResult____h667879[1] ? + (_theResult____h667876[1] ? 6'd55 : - (_theResult____h667879[0] ? + (_theResult____h667876[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 = - (_theResult____h576381[56] ? + (_theResult____h576378[56] ? 6'd0 : - (_theResult____h576381[55] ? + (_theResult____h576378[55] ? 6'd1 : - (_theResult____h576381[54] ? + (_theResult____h576378[54] ? 6'd2 : - (_theResult____h576381[53] ? + (_theResult____h576378[53] ? 6'd3 : - (_theResult____h576381[52] ? + (_theResult____h576378[52] ? 6'd4 : - (_theResult____h576381[51] ? + (_theResult____h576378[51] ? 6'd5 : - (_theResult____h576381[50] ? + (_theResult____h576378[50] ? 6'd6 : - (_theResult____h576381[49] ? + (_theResult____h576378[49] ? 6'd7 : - (_theResult____h576381[48] ? + (_theResult____h576378[48] ? 6'd8 : - (_theResult____h576381[47] ? + (_theResult____h576378[47] ? 6'd9 : - (_theResult____h576381[46] ? + (_theResult____h576378[46] ? 6'd10 : - (_theResult____h576381[45] ? + (_theResult____h576378[45] ? 6'd11 : - (_theResult____h576381[44] ? + (_theResult____h576378[44] ? 6'd12 : - (_theResult____h576381[43] ? + (_theResult____h576378[43] ? 6'd13 : - (_theResult____h576381[42] ? + (_theResult____h576378[42] ? 6'd14 : - (_theResult____h576381[41] ? + (_theResult____h576378[41] ? 6'd15 : - (_theResult____h576381[40] ? + (_theResult____h576378[40] ? 6'd16 : - (_theResult____h576381[39] ? + (_theResult____h576378[39] ? 6'd17 : - (_theResult____h576381[38] ? + (_theResult____h576378[38] ? 6'd18 : - (_theResult____h576381[37] ? + (_theResult____h576378[37] ? 6'd19 : - (_theResult____h576381[36] ? + (_theResult____h576378[36] ? 6'd20 : - (_theResult____h576381[35] ? + (_theResult____h576378[35] ? 6'd21 : - (_theResult____h576381[34] ? + (_theResult____h576378[34] ? 6'd22 : - (_theResult____h576381[33] ? + (_theResult____h576378[33] ? 6'd23 : - (_theResult____h576381[32] ? + (_theResult____h576378[32] ? 6'd24 : - (_theResult____h576381[31] ? + (_theResult____h576378[31] ? 6'd25 : - (_theResult____h576381[30] ? + (_theResult____h576378[30] ? 6'd26 : - (_theResult____h576381[29] ? + (_theResult____h576378[29] ? 6'd27 : - (_theResult____h576381[28] ? + (_theResult____h576378[28] ? 6'd28 : - (_theResult____h576381[27] ? + (_theResult____h576378[27] ? 6'd29 : - (_theResult____h576381[26] ? + (_theResult____h576378[26] ? 6'd30 : - (_theResult____h576381[25] ? + (_theResult____h576378[25] ? 6'd31 : - (_theResult____h576381[24] ? + (_theResult____h576378[24] ? 6'd32 : - (_theResult____h576381[23] ? + (_theResult____h576378[23] ? 6'd33 : - (_theResult____h576381[22] ? + (_theResult____h576378[22] ? 6'd34 : - (_theResult____h576381[21] ? + (_theResult____h576378[21] ? 6'd35 : - (_theResult____h576381[20] ? + (_theResult____h576378[20] ? 6'd36 : - (_theResult____h576381[19] ? + (_theResult____h576378[19] ? 6'd37 : - (_theResult____h576381[18] ? + (_theResult____h576378[18] ? 6'd38 : - (_theResult____h576381[17] ? + (_theResult____h576378[17] ? 6'd39 : - (_theResult____h576381[16] ? + (_theResult____h576378[16] ? 6'd40 : - (_theResult____h576381[15] ? + (_theResult____h576378[15] ? 6'd41 : - (_theResult____h576381[14] ? + (_theResult____h576378[14] ? 6'd42 : - (_theResult____h576381[13] ? + (_theResult____h576378[13] ? 6'd43 : - (_theResult____h576381[12] ? + (_theResult____h576378[12] ? 6'd44 : - (_theResult____h576381[11] ? + (_theResult____h576378[11] ? 6'd45 : - (_theResult____h576381[10] ? + (_theResult____h576378[10] ? 6'd46 : - (_theResult____h576381[9] ? + (_theResult____h576378[9] ? 6'd47 : - (_theResult____h576381[8] ? + (_theResult____h576378[8] ? 6'd48 : - (_theResult____h576381[7] ? + (_theResult____h576378[7] ? 6'd49 : - (_theResult____h576381[6] ? + (_theResult____h576378[6] ? 6'd50 : - (_theResult____h576381[5] ? + (_theResult____h576378[5] ? 6'd51 : - (_theResult____h576381[4] ? + (_theResult____h576378[4] ? 6'd52 : - (_theResult____h576381[3] ? + (_theResult____h576378[3] ? 6'd53 : - (_theResult____h576381[2] ? + (_theResult____h576378[2] ? 6'd54 : - (_theResult____h576381[1] ? + (_theResult____h576378[1] ? 6'd55 : - (_theResult____h576381[0] ? + (_theResult____h576378[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 = - (_theResult____h622132[56] ? + (_theResult____h622129[56] ? 6'd0 : - (_theResult____h622132[55] ? + (_theResult____h622129[55] ? 6'd1 : - (_theResult____h622132[54] ? + (_theResult____h622129[54] ? 6'd2 : - (_theResult____h622132[53] ? + (_theResult____h622129[53] ? 6'd3 : - (_theResult____h622132[52] ? + (_theResult____h622129[52] ? 6'd4 : - (_theResult____h622132[51] ? + (_theResult____h622129[51] ? 6'd5 : - (_theResult____h622132[50] ? + (_theResult____h622129[50] ? 6'd6 : - (_theResult____h622132[49] ? + (_theResult____h622129[49] ? 6'd7 : - (_theResult____h622132[48] ? + (_theResult____h622129[48] ? 6'd8 : - (_theResult____h622132[47] ? + (_theResult____h622129[47] ? 6'd9 : - (_theResult____h622132[46] ? + (_theResult____h622129[46] ? 6'd10 : - (_theResult____h622132[45] ? + (_theResult____h622129[45] ? 6'd11 : - (_theResult____h622132[44] ? + (_theResult____h622129[44] ? 6'd12 : - (_theResult____h622132[43] ? + (_theResult____h622129[43] ? 6'd13 : - (_theResult____h622132[42] ? + (_theResult____h622129[42] ? 6'd14 : - (_theResult____h622132[41] ? + (_theResult____h622129[41] ? 6'd15 : - (_theResult____h622132[40] ? + (_theResult____h622129[40] ? 6'd16 : - (_theResult____h622132[39] ? + (_theResult____h622129[39] ? 6'd17 : - (_theResult____h622132[38] ? + (_theResult____h622129[38] ? 6'd18 : - (_theResult____h622132[37] ? + (_theResult____h622129[37] ? 6'd19 : - (_theResult____h622132[36] ? + (_theResult____h622129[36] ? 6'd20 : - (_theResult____h622132[35] ? + (_theResult____h622129[35] ? 6'd21 : - (_theResult____h622132[34] ? + (_theResult____h622129[34] ? 6'd22 : - (_theResult____h622132[33] ? + (_theResult____h622129[33] ? 6'd23 : - (_theResult____h622132[32] ? + (_theResult____h622129[32] ? 6'd24 : - (_theResult____h622132[31] ? + (_theResult____h622129[31] ? 6'd25 : - (_theResult____h622132[30] ? + (_theResult____h622129[30] ? 6'd26 : - (_theResult____h622132[29] ? + (_theResult____h622129[29] ? 6'd27 : - (_theResult____h622132[28] ? + (_theResult____h622129[28] ? 6'd28 : - (_theResult____h622132[27] ? + (_theResult____h622129[27] ? 6'd29 : - (_theResult____h622132[26] ? + (_theResult____h622129[26] ? 6'd30 : - (_theResult____h622132[25] ? + (_theResult____h622129[25] ? 6'd31 : - (_theResult____h622132[24] ? + (_theResult____h622129[24] ? 6'd32 : - (_theResult____h622132[23] ? + (_theResult____h622129[23] ? 6'd33 : - (_theResult____h622132[22] ? + (_theResult____h622129[22] ? 6'd34 : - (_theResult____h622132[21] ? + (_theResult____h622129[21] ? 6'd35 : - (_theResult____h622132[20] ? + (_theResult____h622129[20] ? 6'd36 : - (_theResult____h622132[19] ? + (_theResult____h622129[19] ? 6'd37 : - (_theResult____h622132[18] ? + (_theResult____h622129[18] ? 6'd38 : - (_theResult____h622132[17] ? + (_theResult____h622129[17] ? 6'd39 : - (_theResult____h622132[16] ? + (_theResult____h622129[16] ? 6'd40 : - (_theResult____h622132[15] ? + (_theResult____h622129[15] ? 6'd41 : - (_theResult____h622132[14] ? + (_theResult____h622129[14] ? 6'd42 : - (_theResult____h622132[13] ? + (_theResult____h622129[13] ? 6'd43 : - (_theResult____h622132[12] ? + (_theResult____h622129[12] ? 6'd44 : - (_theResult____h622132[11] ? + (_theResult____h622129[11] ? 6'd45 : - (_theResult____h622132[10] ? + (_theResult____h622129[10] ? 6'd46 : - (_theResult____h622132[9] ? + (_theResult____h622129[9] ? 6'd47 : - (_theResult____h622132[8] ? + (_theResult____h622129[8] ? 6'd48 : - (_theResult____h622132[7] ? + (_theResult____h622129[7] ? 6'd49 : - (_theResult____h622132[6] ? + (_theResult____h622129[6] ? 6'd50 : - (_theResult____h622132[5] ? + (_theResult____h622129[5] ? 6'd51 : - (_theResult____h622132[4] ? + (_theResult____h622129[4] ? 6'd52 : - (_theResult____h622132[3] ? + (_theResult____h622129[3] ? 6'd53 : - (_theResult____h622132[2] ? + (_theResult____h622129[2] ? 6'd54 : - (_theResult____h622132[1] ? + (_theResult____h622129[1] ? 6'd55 : - (_theResult____h622132[0] ? + (_theResult____h622129[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 = - (_theResult____h735554[56] ? + (_theResult____h735551[56] ? 6'd0 : - (_theResult____h735554[55] ? + (_theResult____h735551[55] ? 6'd1 : - (_theResult____h735554[54] ? + (_theResult____h735551[54] ? 6'd2 : - (_theResult____h735554[53] ? + (_theResult____h735551[53] ? 6'd3 : - (_theResult____h735554[52] ? + (_theResult____h735551[52] ? 6'd4 : - (_theResult____h735554[51] ? + (_theResult____h735551[51] ? 6'd5 : - (_theResult____h735554[50] ? + (_theResult____h735551[50] ? 6'd6 : - (_theResult____h735554[49] ? + (_theResult____h735551[49] ? 6'd7 : - (_theResult____h735554[48] ? + (_theResult____h735551[48] ? 6'd8 : - (_theResult____h735554[47] ? + (_theResult____h735551[47] ? 6'd9 : - (_theResult____h735554[46] ? + (_theResult____h735551[46] ? 6'd10 : - (_theResult____h735554[45] ? + (_theResult____h735551[45] ? 6'd11 : - (_theResult____h735554[44] ? + (_theResult____h735551[44] ? 6'd12 : - (_theResult____h735554[43] ? + (_theResult____h735551[43] ? 6'd13 : - (_theResult____h735554[42] ? + (_theResult____h735551[42] ? 6'd14 : - (_theResult____h735554[41] ? + (_theResult____h735551[41] ? 6'd15 : - (_theResult____h735554[40] ? + (_theResult____h735551[40] ? 6'd16 : - (_theResult____h735554[39] ? + (_theResult____h735551[39] ? 6'd17 : - (_theResult____h735554[38] ? + (_theResult____h735551[38] ? 6'd18 : - (_theResult____h735554[37] ? + (_theResult____h735551[37] ? 6'd19 : - (_theResult____h735554[36] ? + (_theResult____h735551[36] ? 6'd20 : - (_theResult____h735554[35] ? + (_theResult____h735551[35] ? 6'd21 : - (_theResult____h735554[34] ? + (_theResult____h735551[34] ? 6'd22 : - (_theResult____h735554[33] ? + (_theResult____h735551[33] ? 6'd23 : - (_theResult____h735554[32] ? + (_theResult____h735551[32] ? 6'd24 : - (_theResult____h735554[31] ? + (_theResult____h735551[31] ? 6'd25 : - (_theResult____h735554[30] ? + (_theResult____h735551[30] ? 6'd26 : - (_theResult____h735554[29] ? + (_theResult____h735551[29] ? 6'd27 : - (_theResult____h735554[28] ? + (_theResult____h735551[28] ? 6'd28 : - (_theResult____h735554[27] ? + (_theResult____h735551[27] ? 6'd29 : - (_theResult____h735554[26] ? + (_theResult____h735551[26] ? 6'd30 : - (_theResult____h735554[25] ? + (_theResult____h735551[25] ? 6'd31 : - (_theResult____h735554[24] ? + (_theResult____h735551[24] ? 6'd32 : - (_theResult____h735554[23] ? + (_theResult____h735551[23] ? 6'd33 : - (_theResult____h735554[22] ? + (_theResult____h735551[22] ? 6'd34 : - (_theResult____h735554[21] ? + (_theResult____h735551[21] ? 6'd35 : - (_theResult____h735554[20] ? + (_theResult____h735551[20] ? 6'd36 : - (_theResult____h735554[19] ? + (_theResult____h735551[19] ? 6'd37 : - (_theResult____h735554[18] ? + (_theResult____h735551[18] ? 6'd38 : - (_theResult____h735554[17] ? + (_theResult____h735551[17] ? 6'd39 : - (_theResult____h735554[16] ? + (_theResult____h735551[16] ? 6'd40 : - (_theResult____h735554[15] ? + (_theResult____h735551[15] ? 6'd41 : - (_theResult____h735554[14] ? + (_theResult____h735551[14] ? 6'd42 : - (_theResult____h735554[13] ? + (_theResult____h735551[13] ? 6'd43 : - (_theResult____h735554[12] ? + (_theResult____h735551[12] ? 6'd44 : - (_theResult____h735554[11] ? + (_theResult____h735551[11] ? 6'd45 : - (_theResult____h735554[10] ? + (_theResult____h735551[10] ? 6'd46 : - (_theResult____h735554[9] ? + (_theResult____h735551[9] ? 6'd47 : - (_theResult____h735554[8] ? + (_theResult____h735551[8] ? 6'd48 : - (_theResult____h735554[7] ? + (_theResult____h735551[7] ? 6'd49 : - (_theResult____h735554[6] ? + (_theResult____h735551[6] ? 6'd50 : - (_theResult____h735554[5] ? + (_theResult____h735551[5] ? 6'd51 : - (_theResult____h735554[4] ? + (_theResult____h735551[4] ? 6'd52 : - (_theResult____h735554[3] ? + (_theResult____h735551[3] ? 6'd53 : - (_theResult____h735554[2] ? + (_theResult____h735551[2] ? 6'd54 : - (_theResult____h735554[1] ? + (_theResult____h735551[1] ? 6'd55 : - (_theResult____h735554[0] ? + (_theResult____h735551[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 = - (_theResult____h813711[56] ? + (_theResult____h813708[56] ? 6'd0 : - (_theResult____h813711[55] ? + (_theResult____h813708[55] ? 6'd1 : - (_theResult____h813711[54] ? + (_theResult____h813708[54] ? 6'd2 : - (_theResult____h813711[53] ? + (_theResult____h813708[53] ? 6'd3 : - (_theResult____h813711[52] ? + (_theResult____h813708[52] ? 6'd4 : - (_theResult____h813711[51] ? + (_theResult____h813708[51] ? 6'd5 : - (_theResult____h813711[50] ? + (_theResult____h813708[50] ? 6'd6 : - (_theResult____h813711[49] ? + (_theResult____h813708[49] ? 6'd7 : - (_theResult____h813711[48] ? + (_theResult____h813708[48] ? 6'd8 : - (_theResult____h813711[47] ? + (_theResult____h813708[47] ? 6'd9 : - (_theResult____h813711[46] ? + (_theResult____h813708[46] ? 6'd10 : - (_theResult____h813711[45] ? + (_theResult____h813708[45] ? 6'd11 : - (_theResult____h813711[44] ? + (_theResult____h813708[44] ? 6'd12 : - (_theResult____h813711[43] ? + (_theResult____h813708[43] ? 6'd13 : - (_theResult____h813711[42] ? + (_theResult____h813708[42] ? 6'd14 : - (_theResult____h813711[41] ? + (_theResult____h813708[41] ? 6'd15 : - (_theResult____h813711[40] ? + (_theResult____h813708[40] ? 6'd16 : - (_theResult____h813711[39] ? + (_theResult____h813708[39] ? 6'd17 : - (_theResult____h813711[38] ? + (_theResult____h813708[38] ? 6'd18 : - (_theResult____h813711[37] ? + (_theResult____h813708[37] ? 6'd19 : - (_theResult____h813711[36] ? + (_theResult____h813708[36] ? 6'd20 : - (_theResult____h813711[35] ? + (_theResult____h813708[35] ? 6'd21 : - (_theResult____h813711[34] ? + (_theResult____h813708[34] ? 6'd22 : - (_theResult____h813711[33] ? + (_theResult____h813708[33] ? 6'd23 : - (_theResult____h813711[32] ? + (_theResult____h813708[32] ? 6'd24 : - (_theResult____h813711[31] ? + (_theResult____h813708[31] ? 6'd25 : - (_theResult____h813711[30] ? + (_theResult____h813708[30] ? 6'd26 : - (_theResult____h813711[29] ? + (_theResult____h813708[29] ? 6'd27 : - (_theResult____h813711[28] ? + (_theResult____h813708[28] ? 6'd28 : - (_theResult____h813711[27] ? + (_theResult____h813708[27] ? 6'd29 : - (_theResult____h813711[26] ? + (_theResult____h813708[26] ? 6'd30 : - (_theResult____h813711[25] ? + (_theResult____h813708[25] ? 6'd31 : - (_theResult____h813711[24] ? + (_theResult____h813708[24] ? 6'd32 : - (_theResult____h813711[23] ? + (_theResult____h813708[23] ? 6'd33 : - (_theResult____h813711[22] ? + (_theResult____h813708[22] ? 6'd34 : - (_theResult____h813711[21] ? + (_theResult____h813708[21] ? 6'd35 : - (_theResult____h813711[20] ? + (_theResult____h813708[20] ? 6'd36 : - (_theResult____h813711[19] ? + (_theResult____h813708[19] ? 6'd37 : - (_theResult____h813711[18] ? + (_theResult____h813708[18] ? 6'd38 : - (_theResult____h813711[17] ? + (_theResult____h813708[17] ? 6'd39 : - (_theResult____h813711[16] ? + (_theResult____h813708[16] ? 6'd40 : - (_theResult____h813711[15] ? + (_theResult____h813708[15] ? 6'd41 : - (_theResult____h813711[14] ? + (_theResult____h813708[14] ? 6'd42 : - (_theResult____h813711[13] ? + (_theResult____h813708[13] ? 6'd43 : - (_theResult____h813711[12] ? + (_theResult____h813708[12] ? 6'd44 : - (_theResult____h813711[11] ? + (_theResult____h813708[11] ? 6'd45 : - (_theResult____h813711[10] ? + (_theResult____h813708[10] ? 6'd46 : - (_theResult____h813711[9] ? + (_theResult____h813708[9] ? 6'd47 : - (_theResult____h813711[8] ? + (_theResult____h813708[8] ? 6'd48 : - (_theResult____h813711[7] ? + (_theResult____h813708[7] ? 6'd49 : - (_theResult____h813711[6] ? + (_theResult____h813708[6] ? 6'd50 : - (_theResult____h813711[5] ? + (_theResult____h813708[5] ? 6'd51 : - (_theResult____h813711[4] ? + (_theResult____h813708[4] ? 6'd52 : - (_theResult____h813711[3] ? + (_theResult____h813708[3] ? 6'd53 : - (_theResult____h813711[2] ? + (_theResult____h813708[2] ? 6'd54 : - (_theResult____h813711[1] ? + (_theResult____h813708[1] ? 6'd55 : - (_theResult____h813711[0] ? + (_theResult____h813708[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 = - (_theResult____h774407[56] ? + (_theResult____h774404[56] ? 6'd0 : - (_theResult____h774407[55] ? + (_theResult____h774404[55] ? 6'd1 : - (_theResult____h774407[54] ? + (_theResult____h774404[54] ? 6'd2 : - (_theResult____h774407[53] ? + (_theResult____h774404[53] ? 6'd3 : - (_theResult____h774407[52] ? + (_theResult____h774404[52] ? 6'd4 : - (_theResult____h774407[51] ? + (_theResult____h774404[51] ? 6'd5 : - (_theResult____h774407[50] ? + (_theResult____h774404[50] ? 6'd6 : - (_theResult____h774407[49] ? + (_theResult____h774404[49] ? 6'd7 : - (_theResult____h774407[48] ? + (_theResult____h774404[48] ? 6'd8 : - (_theResult____h774407[47] ? + (_theResult____h774404[47] ? 6'd9 : - (_theResult____h774407[46] ? + (_theResult____h774404[46] ? 6'd10 : - (_theResult____h774407[45] ? + (_theResult____h774404[45] ? 6'd11 : - (_theResult____h774407[44] ? + (_theResult____h774404[44] ? 6'd12 : - (_theResult____h774407[43] ? + (_theResult____h774404[43] ? 6'd13 : - (_theResult____h774407[42] ? + (_theResult____h774404[42] ? 6'd14 : - (_theResult____h774407[41] ? + (_theResult____h774404[41] ? 6'd15 : - (_theResult____h774407[40] ? + (_theResult____h774404[40] ? 6'd16 : - (_theResult____h774407[39] ? + (_theResult____h774404[39] ? 6'd17 : - (_theResult____h774407[38] ? + (_theResult____h774404[38] ? 6'd18 : - (_theResult____h774407[37] ? + (_theResult____h774404[37] ? 6'd19 : - (_theResult____h774407[36] ? + (_theResult____h774404[36] ? 6'd20 : - (_theResult____h774407[35] ? + (_theResult____h774404[35] ? 6'd21 : - (_theResult____h774407[34] ? + (_theResult____h774404[34] ? 6'd22 : - (_theResult____h774407[33] ? + (_theResult____h774404[33] ? 6'd23 : - (_theResult____h774407[32] ? + (_theResult____h774404[32] ? 6'd24 : - (_theResult____h774407[31] ? + (_theResult____h774404[31] ? 6'd25 : - (_theResult____h774407[30] ? + (_theResult____h774404[30] ? 6'd26 : - (_theResult____h774407[29] ? + (_theResult____h774404[29] ? 6'd27 : - (_theResult____h774407[28] ? + (_theResult____h774404[28] ? 6'd28 : - (_theResult____h774407[27] ? + (_theResult____h774404[27] ? 6'd29 : - (_theResult____h774407[26] ? + (_theResult____h774404[26] ? 6'd30 : - (_theResult____h774407[25] ? + (_theResult____h774404[25] ? 6'd31 : - (_theResult____h774407[24] ? + (_theResult____h774404[24] ? 6'd32 : - (_theResult____h774407[23] ? + (_theResult____h774404[23] ? 6'd33 : - (_theResult____h774407[22] ? + (_theResult____h774404[22] ? 6'd34 : - (_theResult____h774407[21] ? + (_theResult____h774404[21] ? 6'd35 : - (_theResult____h774407[20] ? + (_theResult____h774404[20] ? 6'd36 : - (_theResult____h774407[19] ? + (_theResult____h774404[19] ? 6'd37 : - (_theResult____h774407[18] ? + (_theResult____h774404[18] ? 6'd38 : - (_theResult____h774407[17] ? + (_theResult____h774404[17] ? 6'd39 : - (_theResult____h774407[16] ? + (_theResult____h774404[16] ? 6'd40 : - (_theResult____h774407[15] ? + (_theResult____h774404[15] ? 6'd41 : - (_theResult____h774407[14] ? + (_theResult____h774404[14] ? 6'd42 : - (_theResult____h774407[13] ? + (_theResult____h774404[13] ? 6'd43 : - (_theResult____h774407[12] ? + (_theResult____h774404[12] ? 6'd44 : - (_theResult____h774407[11] ? + (_theResult____h774404[11] ? 6'd45 : - (_theResult____h774407[10] ? + (_theResult____h774404[10] ? 6'd46 : - (_theResult____h774407[9] ? + (_theResult____h774404[9] ? 6'd47 : - (_theResult____h774407[8] ? + (_theResult____h774404[8] ? 6'd48 : - (_theResult____h774407[7] ? + (_theResult____h774404[7] ? 6'd49 : - (_theResult____h774407[6] ? + (_theResult____h774404[6] ? 6'd50 : - (_theResult____h774407[5] ? + (_theResult____h774404[5] ? 6'd51 : - (_theResult____h774407[4] ? + (_theResult____h774404[4] ? 6'd52 : - (_theResult____h774407[3] ? + (_theResult____h774404[3] ? 6'd53 : - (_theResult____h774407[2] ? + (_theResult____h774404[2] ? 6'd54 : - (_theResult____h774407[1] ? + (_theResult____h774404[1] ? 6'd55 : - (_theResult____h774407[0] ? + (_theResult____h774404[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 = - (_theResult____h639769[56] ? + (_theResult____h639766[56] ? 6'd0 : - (_theResult____h639769[55] ? + (_theResult____h639766[55] ? 6'd1 : - (_theResult____h639769[54] ? + (_theResult____h639766[54] ? 6'd2 : - (_theResult____h639769[53] ? + (_theResult____h639766[53] ? 6'd3 : - (_theResult____h639769[52] ? + (_theResult____h639766[52] ? 6'd4 : - (_theResult____h639769[51] ? + (_theResult____h639766[51] ? 6'd5 : - (_theResult____h639769[50] ? + (_theResult____h639766[50] ? 6'd6 : - (_theResult____h639769[49] ? + (_theResult____h639766[49] ? 6'd7 : - (_theResult____h639769[48] ? + (_theResult____h639766[48] ? 6'd8 : - (_theResult____h639769[47] ? + (_theResult____h639766[47] ? 6'd9 : - (_theResult____h639769[46] ? + (_theResult____h639766[46] ? 6'd10 : - (_theResult____h639769[45] ? + (_theResult____h639766[45] ? 6'd11 : - (_theResult____h639769[44] ? + (_theResult____h639766[44] ? 6'd12 : - (_theResult____h639769[43] ? + (_theResult____h639766[43] ? 6'd13 : - (_theResult____h639769[42] ? + (_theResult____h639766[42] ? 6'd14 : - (_theResult____h639769[41] ? + (_theResult____h639766[41] ? 6'd15 : - (_theResult____h639769[40] ? + (_theResult____h639766[40] ? 6'd16 : - (_theResult____h639769[39] ? + (_theResult____h639766[39] ? 6'd17 : - (_theResult____h639769[38] ? + (_theResult____h639766[38] ? 6'd18 : - (_theResult____h639769[37] ? + (_theResult____h639766[37] ? 6'd19 : - (_theResult____h639769[36] ? + (_theResult____h639766[36] ? 6'd20 : - (_theResult____h639769[35] ? + (_theResult____h639766[35] ? 6'd21 : - (_theResult____h639769[34] ? + (_theResult____h639766[34] ? 6'd22 : - (_theResult____h639769[33] ? + (_theResult____h639766[33] ? 6'd23 : - (_theResult____h639769[32] ? + (_theResult____h639766[32] ? 6'd24 : - (_theResult____h639769[31] ? + (_theResult____h639766[31] ? 6'd25 : - (_theResult____h639769[30] ? + (_theResult____h639766[30] ? 6'd26 : - (_theResult____h639769[29] ? + (_theResult____h639766[29] ? 6'd27 : - (_theResult____h639769[28] ? + (_theResult____h639766[28] ? 6'd28 : - (_theResult____h639769[27] ? + (_theResult____h639766[27] ? 6'd29 : - (_theResult____h639769[26] ? + (_theResult____h639766[26] ? 6'd30 : - (_theResult____h639769[25] ? + (_theResult____h639766[25] ? 6'd31 : - (_theResult____h639769[24] ? + (_theResult____h639766[24] ? 6'd32 : - (_theResult____h639769[23] ? + (_theResult____h639766[23] ? 6'd33 : - (_theResult____h639769[22] ? + (_theResult____h639766[22] ? 6'd34 : - (_theResult____h639769[21] ? + (_theResult____h639766[21] ? 6'd35 : - (_theResult____h639769[20] ? + (_theResult____h639766[20] ? 6'd36 : - (_theResult____h639769[19] ? + (_theResult____h639766[19] ? 6'd37 : - (_theResult____h639769[18] ? + (_theResult____h639766[18] ? 6'd38 : - (_theResult____h639769[17] ? + (_theResult____h639766[17] ? 6'd39 : - (_theResult____h639769[16] ? + (_theResult____h639766[16] ? 6'd40 : - (_theResult____h639769[15] ? + (_theResult____h639766[15] ? 6'd41 : - (_theResult____h639769[14] ? + (_theResult____h639766[14] ? 6'd42 : - (_theResult____h639769[13] ? + (_theResult____h639766[13] ? 6'd43 : - (_theResult____h639769[12] ? + (_theResult____h639766[12] ? 6'd44 : - (_theResult____h639769[11] ? + (_theResult____h639766[11] ? 6'd45 : - (_theResult____h639769[10] ? + (_theResult____h639766[10] ? 6'd46 : - (_theResult____h639769[9] ? + (_theResult____h639766[9] ? 6'd47 : - (_theResult____h639769[8] ? + (_theResult____h639766[8] ? 6'd48 : - (_theResult____h639769[7] ? + (_theResult____h639766[7] ? 6'd49 : - (_theResult____h639769[6] ? + (_theResult____h639766[6] ? 6'd50 : - (_theResult____h639769[5] ? + (_theResult____h639766[5] ? 6'd51 : - (_theResult____h639769[4] ? + (_theResult____h639766[4] ? 6'd52 : - (_theResult____h639769[3] ? + (_theResult____h639766[3] ? 6'd53 : - (_theResult____h639769[2] ? + (_theResult____h639766[2] ? 6'd54 : - (_theResult____h639769[1] ? + (_theResult____h639766[1] ? 6'd55 : - (_theResult____h639769[0] ? + (_theResult____h639766[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 = - (_theResult____h685516[56] ? + (_theResult____h685513[56] ? 6'd0 : - (_theResult____h685516[55] ? + (_theResult____h685513[55] ? 6'd1 : - (_theResult____h685516[54] ? + (_theResult____h685513[54] ? 6'd2 : - (_theResult____h685516[53] ? + (_theResult____h685513[53] ? 6'd3 : - (_theResult____h685516[52] ? + (_theResult____h685513[52] ? 6'd4 : - (_theResult____h685516[51] ? + (_theResult____h685513[51] ? 6'd5 : - (_theResult____h685516[50] ? + (_theResult____h685513[50] ? 6'd6 : - (_theResult____h685516[49] ? + (_theResult____h685513[49] ? 6'd7 : - (_theResult____h685516[48] ? + (_theResult____h685513[48] ? 6'd8 : - (_theResult____h685516[47] ? + (_theResult____h685513[47] ? 6'd9 : - (_theResult____h685516[46] ? + (_theResult____h685513[46] ? 6'd10 : - (_theResult____h685516[45] ? + (_theResult____h685513[45] ? 6'd11 : - (_theResult____h685516[44] ? + (_theResult____h685513[44] ? 6'd12 : - (_theResult____h685516[43] ? + (_theResult____h685513[43] ? 6'd13 : - (_theResult____h685516[42] ? + (_theResult____h685513[42] ? 6'd14 : - (_theResult____h685516[41] ? + (_theResult____h685513[41] ? 6'd15 : - (_theResult____h685516[40] ? + (_theResult____h685513[40] ? 6'd16 : - (_theResult____h685516[39] ? + (_theResult____h685513[39] ? 6'd17 : - (_theResult____h685516[38] ? + (_theResult____h685513[38] ? 6'd18 : - (_theResult____h685516[37] ? + (_theResult____h685513[37] ? 6'd19 : - (_theResult____h685516[36] ? + (_theResult____h685513[36] ? 6'd20 : - (_theResult____h685516[35] ? + (_theResult____h685513[35] ? 6'd21 : - (_theResult____h685516[34] ? + (_theResult____h685513[34] ? 6'd22 : - (_theResult____h685516[33] ? + (_theResult____h685513[33] ? 6'd23 : - (_theResult____h685516[32] ? + (_theResult____h685513[32] ? 6'd24 : - (_theResult____h685516[31] ? + (_theResult____h685513[31] ? 6'd25 : - (_theResult____h685516[30] ? + (_theResult____h685513[30] ? 6'd26 : - (_theResult____h685516[29] ? + (_theResult____h685513[29] ? 6'd27 : - (_theResult____h685516[28] ? + (_theResult____h685513[28] ? 6'd28 : - (_theResult____h685516[27] ? + (_theResult____h685513[27] ? 6'd29 : - (_theResult____h685516[26] ? + (_theResult____h685513[26] ? 6'd30 : - (_theResult____h685516[25] ? + (_theResult____h685513[25] ? 6'd31 : - (_theResult____h685516[24] ? + (_theResult____h685513[24] ? 6'd32 : - (_theResult____h685516[23] ? + (_theResult____h685513[23] ? 6'd33 : - (_theResult____h685516[22] ? + (_theResult____h685513[22] ? 6'd34 : - (_theResult____h685516[21] ? + (_theResult____h685513[21] ? 6'd35 : - (_theResult____h685516[20] ? + (_theResult____h685513[20] ? 6'd36 : - (_theResult____h685516[19] ? + (_theResult____h685513[19] ? 6'd37 : - (_theResult____h685516[18] ? + (_theResult____h685513[18] ? 6'd38 : - (_theResult____h685516[17] ? + (_theResult____h685513[17] ? 6'd39 : - (_theResult____h685516[16] ? + (_theResult____h685513[16] ? 6'd40 : - (_theResult____h685516[15] ? + (_theResult____h685513[15] ? 6'd41 : - (_theResult____h685516[14] ? + (_theResult____h685513[14] ? 6'd42 : - (_theResult____h685516[13] ? + (_theResult____h685513[13] ? 6'd43 : - (_theResult____h685516[12] ? + (_theResult____h685513[12] ? 6'd44 : - (_theResult____h685516[11] ? + (_theResult____h685513[11] ? 6'd45 : - (_theResult____h685516[10] ? + (_theResult____h685513[10] ? 6'd46 : - (_theResult____h685516[9] ? + (_theResult____h685513[9] ? 6'd47 : - (_theResult____h685516[8] ? + (_theResult____h685513[8] ? 6'd48 : - (_theResult____h685516[7] ? + (_theResult____h685513[7] ? 6'd49 : - (_theResult____h685516[6] ? + (_theResult____h685513[6] ? 6'd50 : - (_theResult____h685516[5] ? + (_theResult____h685513[5] ? 6'd51 : - (_theResult____h685516[4] ? + (_theResult____h685513[4] ? 6'd52 : - (_theResult____h685516[3] ? + (_theResult____h685513[3] ? 6'd53 : - (_theResult____h685516[2] ? + (_theResult____h685513[2] ? 6'd54 : - (_theResult____h685516[1] ? + (_theResult____h685513[1] ? 6'd55 : - (_theResult____h685516[0] ? + (_theResult____h685513[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 = - (_theResult____h594020[56] ? + (_theResult____h594017[56] ? 6'd0 : - (_theResult____h594020[55] ? + (_theResult____h594017[55] ? 6'd1 : - (_theResult____h594020[54] ? + (_theResult____h594017[54] ? 6'd2 : - (_theResult____h594020[53] ? + (_theResult____h594017[53] ? 6'd3 : - (_theResult____h594020[52] ? + (_theResult____h594017[52] ? 6'd4 : - (_theResult____h594020[51] ? + (_theResult____h594017[51] ? 6'd5 : - (_theResult____h594020[50] ? + (_theResult____h594017[50] ? 6'd6 : - (_theResult____h594020[49] ? + (_theResult____h594017[49] ? 6'd7 : - (_theResult____h594020[48] ? + (_theResult____h594017[48] ? 6'd8 : - (_theResult____h594020[47] ? + (_theResult____h594017[47] ? 6'd9 : - (_theResult____h594020[46] ? + (_theResult____h594017[46] ? 6'd10 : - (_theResult____h594020[45] ? + (_theResult____h594017[45] ? 6'd11 : - (_theResult____h594020[44] ? + (_theResult____h594017[44] ? 6'd12 : - (_theResult____h594020[43] ? + (_theResult____h594017[43] ? 6'd13 : - (_theResult____h594020[42] ? + (_theResult____h594017[42] ? 6'd14 : - (_theResult____h594020[41] ? + (_theResult____h594017[41] ? 6'd15 : - (_theResult____h594020[40] ? + (_theResult____h594017[40] ? 6'd16 : - (_theResult____h594020[39] ? + (_theResult____h594017[39] ? 6'd17 : - (_theResult____h594020[38] ? + (_theResult____h594017[38] ? 6'd18 : - (_theResult____h594020[37] ? + (_theResult____h594017[37] ? 6'd19 : - (_theResult____h594020[36] ? + (_theResult____h594017[36] ? 6'd20 : - (_theResult____h594020[35] ? + (_theResult____h594017[35] ? 6'd21 : - (_theResult____h594020[34] ? + (_theResult____h594017[34] ? 6'd22 : - (_theResult____h594020[33] ? + (_theResult____h594017[33] ? 6'd23 : - (_theResult____h594020[32] ? + (_theResult____h594017[32] ? 6'd24 : - (_theResult____h594020[31] ? + (_theResult____h594017[31] ? 6'd25 : - (_theResult____h594020[30] ? + (_theResult____h594017[30] ? 6'd26 : - (_theResult____h594020[29] ? + (_theResult____h594017[29] ? 6'd27 : - (_theResult____h594020[28] ? + (_theResult____h594017[28] ? 6'd28 : - (_theResult____h594020[27] ? + (_theResult____h594017[27] ? 6'd29 : - (_theResult____h594020[26] ? + (_theResult____h594017[26] ? 6'd30 : - (_theResult____h594020[25] ? + (_theResult____h594017[25] ? 6'd31 : - (_theResult____h594020[24] ? + (_theResult____h594017[24] ? 6'd32 : - (_theResult____h594020[23] ? + (_theResult____h594017[23] ? 6'd33 : - (_theResult____h594020[22] ? + (_theResult____h594017[22] ? 6'd34 : - (_theResult____h594020[21] ? + (_theResult____h594017[21] ? 6'd35 : - (_theResult____h594020[20] ? + (_theResult____h594017[20] ? 6'd36 : - (_theResult____h594020[19] ? + (_theResult____h594017[19] ? 6'd37 : - (_theResult____h594020[18] ? + (_theResult____h594017[18] ? 6'd38 : - (_theResult____h594020[17] ? + (_theResult____h594017[17] ? 6'd39 : - (_theResult____h594020[16] ? + (_theResult____h594017[16] ? 6'd40 : - (_theResult____h594020[15] ? + (_theResult____h594017[15] ? 6'd41 : - (_theResult____h594020[14] ? + (_theResult____h594017[14] ? 6'd42 : - (_theResult____h594020[13] ? + (_theResult____h594017[13] ? 6'd43 : - (_theResult____h594020[12] ? + (_theResult____h594017[12] ? 6'd44 : - (_theResult____h594020[11] ? + (_theResult____h594017[11] ? 6'd45 : - (_theResult____h594020[10] ? + (_theResult____h594017[10] ? 6'd46 : - (_theResult____h594020[9] ? + (_theResult____h594017[9] ? 6'd47 : - (_theResult____h594020[8] ? + (_theResult____h594017[8] ? 6'd48 : - (_theResult____h594020[7] ? + (_theResult____h594017[7] ? 6'd49 : - (_theResult____h594020[6] ? + (_theResult____h594017[6] ? 6'd50 : - (_theResult____h594020[5] ? + (_theResult____h594017[5] ? 6'd51 : - (_theResult____h594020[4] ? + (_theResult____h594017[4] ? 6'd52 : - (_theResult____h594020[3] ? + (_theResult____h594017[3] ? 6'd53 : - (_theResult____h594020[2] ? + (_theResult____h594017[2] ? 6'd54 : - (_theResult____h594020[1] ? + (_theResult____h594017[1] ? 6'd55 : - (_theResult____h594020[0] ? + (_theResult____h594017[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13072 = - (_theResult___fst_exp__h743790 == 11'd2047) ? + (_theResult___fst_exp__h743787 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19148,10 +19148,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13787 = - (_theResult___fst_exp__h821947 == 11'd2047) ? + (_theResult___fst_exp__h821944 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19159,10 +19159,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 : + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14055 = - (_theResult___fst_exp__h821947 == 11'd2047) ? + (_theResult___fst_exp__h821944 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19170,10 +19170,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 : + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14557 = - (_theResult___fst_exp__h782643 == 11'd2047) ? + (_theResult___fst_exp__h782640 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19181,10 +19181,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 : + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14824 = - (_theResult___fst_exp__h782643 == 11'd2047) ? + (_theResult___fst_exp__h782640 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19192,404 +19192,404 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 : + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459 = - (guard__h622142 == 2'b0 || + (guard__h622139 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h630235[56:34] : - _theResult___sfd__h630758 ; + sfdin__h630232[56:34] : + _theResult___sfd__h630755 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461 = - (guard__h622142 == 2'b0) ? - sfdin__h630235[56:34] : + (guard__h622139 == 2'b0) ? + sfdin__h630232[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h630758 : - sfdin__h630235[56:34]) ; + _theResult___sfd__h630755 : + sfdin__h630232[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209 = - (guard__h667889 == 2'b0 || + (guard__h667886 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h675988 : - _theResult___exp__h676504 ; + _theResult___fst_exp__h675985 : + _theResult___exp__h676501 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212 = - (guard__h667889 == 2'b0) ? - _theResult___fst_exp__h675988 : + (guard__h667886 == 2'b0) ? + _theResult___fst_exp__h675985 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h676504 : - _theResult___fst_exp__h675988) ; + _theResult___exp__h676501 : + _theResult___fst_exp__h675985) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856 = - (guard__h667889 == 2'b0 || + (guard__h667886 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h675982[56:34] : - _theResult___sfd__h676505 ; + sfdin__h675979[56:34] : + _theResult___sfd__h676502 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858 = - (guard__h667889 == 2'b0) ? - sfdin__h675982[56:34] : + (guard__h667886 == 2'b0) ? + sfdin__h675979[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h676505 : - sfdin__h675982[56:34]) ; + _theResult___sfd__h676502 : + sfdin__h675979[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415 = - (guard__h576391 == 2'b0 || + (guard__h576388 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h584492 : - _theResult___exp__h585008 ; + _theResult___fst_exp__h584489 : + _theResult___exp__h585005 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418 = - (guard__h576391 == 2'b0) ? - _theResult___fst_exp__h584492 : + (guard__h576388 == 2'b0) ? + _theResult___fst_exp__h584489 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h585008 : - _theResult___fst_exp__h584492) ; + _theResult___exp__h585005 : + _theResult___fst_exp__h584489) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062 = - (guard__h576391 == 2'b0 || + (guard__h576388 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h584486[56:34] : - _theResult___sfd__h585009 ; + sfdin__h584483[56:34] : + _theResult___sfd__h585006 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064 = - (guard__h576391 == 2'b0) ? - sfdin__h584486[56:34] : + (guard__h576388 == 2'b0) ? + sfdin__h584483[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h585009 : - sfdin__h584486[56:34]) ; + _theResult___sfd__h585006 : + sfdin__h584483[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812 = - (guard__h622142 == 2'b0 || + (guard__h622139 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h630241 : - _theResult___exp__h630757 ; + _theResult___fst_exp__h630238 : + _theResult___exp__h630754 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815 = - (guard__h622142 == 2'b0) ? - _theResult___fst_exp__h630241 : + (guard__h622139 == 2'b0) ? + _theResult___fst_exp__h630238 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h630757 : - _theResult___fst_exp__h630241) ; + _theResult___exp__h630754 : + _theResult___fst_exp__h630238) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189 = - (guard__h735564 == 2'b0 || + (guard__h735561 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h743790 : - _theResult___exp__h744519 ; + _theResult___fst_exp__h743787 : + _theResult___exp__h744516 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191 = - (guard__h735564 == 2'b0) ? - _theResult___fst_exp__h743790 : + (guard__h735561 == 2'b0) ? + _theResult___fst_exp__h743787 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h744519 : - _theResult___fst_exp__h743790) ; + _theResult___exp__h744516 : + _theResult___fst_exp__h743787) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273 = - (guard__h735564 == 2'b0 || + (guard__h735561 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h743784[56:5] : - _theResult___sfd__h744520 ; + sfdin__h743781[56:5] : + _theResult___sfd__h744517 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275 = - (guard__h735564 == 2'b0) ? - sfdin__h743784[56:5] : + (guard__h735561 == 2'b0) ? + sfdin__h743781[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h744520 : - sfdin__h743784[56:5]) ; + _theResult___sfd__h744517 : + sfdin__h743781[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899 = - (guard__h813721 == 2'b0 || + (guard__h813718 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h821947 : - _theResult___exp__h822676 ; + _theResult___fst_exp__h821944 : + _theResult___exp__h822673 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901 = - (guard__h813721 == 2'b0) ? - _theResult___fst_exp__h821947 : + (guard__h813718 == 2'b0) ? + _theResult___fst_exp__h821944 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h822676 : - _theResult___fst_exp__h821947) ; + _theResult___exp__h822673 : + _theResult___fst_exp__h821944) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982 = - (guard__h813721 == 2'b0 || + (guard__h813718 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h821941[56:5] : - _theResult___sfd__h822677 ; + sfdin__h821938[56:5] : + _theResult___sfd__h822674 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984 = - (guard__h813721 == 2'b0) ? - sfdin__h821941[56:5] : + (guard__h813718 == 2'b0) ? + sfdin__h821938[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h822677 : - sfdin__h821941[56:5]) ; + _theResult___sfd__h822674 : + sfdin__h821938[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669 = - (guard__h774417 == 2'b0 || + (guard__h774414 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h782643 : - _theResult___exp__h783372 ; + _theResult___fst_exp__h782640 : + _theResult___exp__h783369 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671 = - (guard__h774417 == 2'b0) ? - _theResult___fst_exp__h782643 : + (guard__h774414 == 2'b0) ? + _theResult___fst_exp__h782640 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h783372 : - _theResult___fst_exp__h782643) ; + _theResult___exp__h783369 : + _theResult___fst_exp__h782640) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752 = - (guard__h774417 == 2'b0 || + (guard__h774414 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h782637[56:5] : - _theResult___sfd__h783373 ; + sfdin__h782634[56:5] : + _theResult___sfd__h783370 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754 = - (guard__h774417 == 2'b0) ? - sfdin__h782637[56:5] : + (guard__h774414 == 2'b0) ? + sfdin__h782634[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h783373 : - sfdin__h782637[56:5]) ; + _theResult___sfd__h783370 : + sfdin__h782634[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359 = - (guard__h639779 == 2'b0 || + (guard__h639776 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h648007 : - _theResult___exp__h648523 ; + _theResult___fst_exp__h648004 : + _theResult___exp__h648520 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361 = - (guard__h639779 == 2'b0) ? - _theResult___fst_exp__h648007 : + (guard__h639776 == 2'b0) ? + _theResult___fst_exp__h648004 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h648523 : - _theResult___fst_exp__h648007) ; + _theResult___exp__h648520 : + _theResult___fst_exp__h648004) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 = - (guard__h639779 == 2'b0 || + (guard__h639776 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h648001[56:34] : - _theResult___sfd__h648524 ; + sfdin__h647998[56:34] : + _theResult___sfd__h648521 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 = - (guard__h639779 == 2'b0) ? - sfdin__h648001[56:34] : + (guard__h639776 == 2'b0) ? + sfdin__h647998[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h648524 : - sfdin__h648001[56:34]) ; + _theResult___sfd__h648521 : + sfdin__h647998[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756 = - (guard__h685526 == 2'b0 || + (guard__h685523 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h693754 : - _theResult___exp__h694270 ; + _theResult___fst_exp__h693751 : + _theResult___exp__h694267 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758 = - (guard__h685526 == 2'b0) ? - _theResult___fst_exp__h693754 : + (guard__h685523 == 2'b0) ? + _theResult___fst_exp__h693751 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h694270 : - _theResult___fst_exp__h693754) ; + _theResult___exp__h694267 : + _theResult___fst_exp__h693751) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902 = - (guard__h685526 == 2'b0 || + (guard__h685523 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h693748[56:34] : - _theResult___sfd__h694271 ; + sfdin__h693745[56:34] : + _theResult___sfd__h694268 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904 = - (guard__h685526 == 2'b0) ? - sfdin__h693748[56:34] : + (guard__h685523 == 2'b0) ? + sfdin__h693745[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h694271 : - sfdin__h693748[56:34]) ; + _theResult___sfd__h694268 : + sfdin__h693745[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962 = - (guard__h594030 == 2'b0 || + (guard__h594027 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h602258 : - _theResult___exp__h602774 ; + _theResult___fst_exp__h602255 : + _theResult___exp__h602771 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964 = - (guard__h594030 == 2'b0) ? - _theResult___fst_exp__h602258 : + (guard__h594027 == 2'b0) ? + _theResult___fst_exp__h602255 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h602774 : - _theResult___fst_exp__h602258) ; + _theResult___exp__h602771 : + _theResult___fst_exp__h602255) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108 = - (guard__h594030 == 2'b0 || + (guard__h594027 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h602252[56:34] : - _theResult___sfd__h602775 ; + sfdin__h602249[56:34] : + _theResult___sfd__h602772 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110 = - (guard__h594030 == 2'b0) ? - sfdin__h602252[56:34] : + (guard__h594027 == 2'b0) ? + sfdin__h602249[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h602775 : - sfdin__h602252[56:34]) ; + _theResult___sfd__h602772 : + sfdin__h602249[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146 = - (guard__h726252 == 2'b0 || + (guard__h726249 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h734213 : - _theResult___exp__h734868 ; + _theResult___fst_exp__h734210 : + _theResult___exp__h734865 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148 = - (guard__h726252 == 2'b0) ? - _theResult___fst_exp__h734213 : + (guard__h726249 == 2'b0) ? + _theResult___fst_exp__h734210 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h734868 : - _theResult___fst_exp__h734213) ; + _theResult___exp__h734865 : + _theResult___fst_exp__h734210) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220 = - (guard__h744633 == 2'b0 || + (guard__h744630 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h752623 : - _theResult___exp__h753303 ; + _theResult___fst_exp__h752620 : + _theResult___exp__h753300 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222 = - (guard__h744633 == 2'b0) ? - _theResult___fst_exp__h752623 : + (guard__h744630 == 2'b0) ? + _theResult___fst_exp__h752620 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h753303 : - _theResult___fst_exp__h752623) ; + _theResult___exp__h753300 : + _theResult___fst_exp__h752620) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246 = - (guard__h726252 == 2'b0 || + (guard__h726249 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h734164[56:5] : - _theResult___sfd__h734869 ; + _theResult___snd__h734161[56:5] : + _theResult___sfd__h734866 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248 = - (guard__h726252 == 2'b0) ? - _theResult___snd__h734164[56:5] : + (guard__h726249 == 2'b0) ? + _theResult___snd__h734161[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h734869 : - _theResult___snd__h734164[56:5]) ; + _theResult___sfd__h734866 : + _theResult___snd__h734161[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292 = - (guard__h744633 == 2'b0 || + (guard__h744630 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h752569[56:5] : - _theResult___sfd__h753304 ; + _theResult___snd__h752566[56:5] : + _theResult___sfd__h753301 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294 = - (guard__h744633 == 2'b0) ? - _theResult___snd__h752569[56:5] : + (guard__h744630 == 2'b0) ? + _theResult___snd__h752566[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h753304 : - _theResult___snd__h752569[56:5]) ; + _theResult___sfd__h753301 : + _theResult___snd__h752566[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861 = - (guard__h804409 == 2'b0 || + (guard__h804406 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h812370 : - _theResult___exp__h813025 ; + _theResult___fst_exp__h812367 : + _theResult___exp__h813022 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863 = - (guard__h804409 == 2'b0) ? - _theResult___fst_exp__h812370 : + (guard__h804406 == 2'b0) ? + _theResult___fst_exp__h812367 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h813025 : - _theResult___fst_exp__h812370) ; + _theResult___exp__h813022 : + _theResult___fst_exp__h812367) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930 = - (guard__h822790 == 2'b0 || + (guard__h822787 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h830780 : - _theResult___exp__h831460 ; + _theResult___fst_exp__h830777 : + _theResult___exp__h831457 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932 = - (guard__h822790 == 2'b0) ? - _theResult___fst_exp__h830780 : + (guard__h822787 == 2'b0) ? + _theResult___fst_exp__h830777 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h831460 : - _theResult___fst_exp__h830780) ; + _theResult___exp__h831457 : + _theResult___fst_exp__h830777) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956 = - (guard__h804409 == 2'b0 || + (guard__h804406 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h812321[56:5] : - _theResult___sfd__h813026 ; + _theResult___snd__h812318[56:5] : + _theResult___sfd__h813023 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958 = - (guard__h804409 == 2'b0) ? - _theResult___snd__h812321[56:5] : + (guard__h804406 == 2'b0) ? + _theResult___snd__h812318[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h813026 : - _theResult___snd__h812321[56:5]) ; + _theResult___sfd__h813023 : + _theResult___snd__h812318[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001 = - (guard__h822790 == 2'b0 || + (guard__h822787 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h830726[56:5] : - _theResult___sfd__h831461 ; + _theResult___snd__h830723[56:5] : + _theResult___sfd__h831458 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003 = - (guard__h822790 == 2'b0) ? - _theResult___snd__h830726[56:5] : + (guard__h822787 == 2'b0) ? + _theResult___snd__h830723[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h831461 : - _theResult___snd__h830726[56:5]) ; + _theResult___sfd__h831458 : + _theResult___snd__h830723[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631 = - (guard__h765105 == 2'b0 || + (guard__h765102 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h773066 : - _theResult___exp__h773721 ; + _theResult___fst_exp__h773063 : + _theResult___exp__h773718 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633 = - (guard__h765105 == 2'b0) ? - _theResult___fst_exp__h773066 : + (guard__h765102 == 2'b0) ? + _theResult___fst_exp__h773063 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h773721 : - _theResult___fst_exp__h773066) ; + _theResult___exp__h773718 : + _theResult___fst_exp__h773063) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700 = - (guard__h783486 == 2'b0 || + (guard__h783483 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h791476 : - _theResult___exp__h792156 ; + _theResult___fst_exp__h791473 : + _theResult___exp__h792153 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702 = - (guard__h783486 == 2'b0) ? - _theResult___fst_exp__h791476 : + (guard__h783483 == 2'b0) ? + _theResult___fst_exp__h791473 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h792156 : - _theResult___fst_exp__h791476) ; + _theResult___exp__h792153 : + _theResult___fst_exp__h791473) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726 = - (guard__h765105 == 2'b0 || + (guard__h765102 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h773017[56:5] : - _theResult___sfd__h773722 ; + _theResult___snd__h773014[56:5] : + _theResult___sfd__h773719 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728 = - (guard__h765105 == 2'b0) ? - _theResult___snd__h773017[56:5] : + (guard__h765102 == 2'b0) ? + _theResult___snd__h773014[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h773722 : - _theResult___snd__h773017[56:5]) ; + _theResult___sfd__h773719 : + _theResult___snd__h773014[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771 = - (guard__h783486 == 2'b0 || + (guard__h783483 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h791422[56:5] : - _theResult___sfd__h792157 ; + _theResult___snd__h791419[56:5] : + _theResult___sfd__h792154 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773 = - (guard__h783486 == 2'b0) ? - _theResult___snd__h791422[56:5] : + (guard__h783483 == 2'b0) ? + _theResult___snd__h791419[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h792157 : - _theResult___snd__h791422[56:5]) ; + _theResult___sfd__h792154 : + _theResult___snd__h791419[56:5]) ; assign IF_IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_ETC___d20711 = (IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[0] || IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[1] || @@ -19801,139 +19801,139 @@ module mkCore(CLK, IF_checkForException_0436_BITS_3_TO_0_0689_EQ__ETC___d20709 == 4'd9 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034 = - (guard__h630849 == 2'b0 || + (guard__h630846 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h638897 : - _theResult___exp__h639339 ; + _theResult___fst_exp__h638894 : + _theResult___exp__h639336 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036 = - (guard__h630849 == 2'b0) ? - _theResult___fst_exp__h638897 : + (guard__h630846 == 2'b0) ? + _theResult___fst_exp__h638894 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h639339 : - _theResult___fst_exp__h638897) ; + _theResult___exp__h639336 : + _theResult___fst_exp__h638894) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428 = - (guard__h648615 == 2'b0 || + (guard__h648612 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h656692 : - _theResult___exp__h657159 ; + _theResult___fst_exp__h656689 : + _theResult___exp__h657156 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430 = - (guard__h648615 == 2'b0) ? - _theResult___fst_exp__h656692 : + (guard__h648612 == 2'b0) ? + _theResult___fst_exp__h656689 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h657159 : - _theResult___fst_exp__h656692) ; + _theResult___exp__h657156 : + _theResult___fst_exp__h656689) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478 = - (guard__h630849 == 2'b0 || + (guard__h630846 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h638848[56:34] : - _theResult___sfd__h639340 ; + _theResult___snd__h638845[56:34] : + _theResult___sfd__h639337 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480 = - (guard__h630849 == 2'b0) ? - _theResult___snd__h638848[56:34] : + (guard__h630846 == 2'b0) ? + _theResult___snd__h638845[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h639340 : - _theResult___snd__h638848[56:34]) ; + _theResult___sfd__h639337 : + _theResult___snd__h638845[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524 = - (guard__h648615 == 2'b0 || + (guard__h648612 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h656638[56:34] : - _theResult___sfd__h657160 ; + _theResult___snd__h656635[56:34] : + _theResult___sfd__h657157 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526 = - (guard__h648615 == 2'b0) ? - _theResult___snd__h656638[56:34] : + (guard__h648612 == 2'b0) ? + _theResult___snd__h656635[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h657160 : - _theResult___snd__h656638[56:34]) ; + _theResult___sfd__h657157 : + _theResult___snd__h656635[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431 = - (guard__h676596 == 2'b0 || + (guard__h676593 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h684644 : - _theResult___exp__h685086 ; + _theResult___fst_exp__h684641 : + _theResult___exp__h685083 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433 = - (guard__h676596 == 2'b0) ? - _theResult___fst_exp__h684644 : + (guard__h676593 == 2'b0) ? + _theResult___fst_exp__h684641 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h685086 : - _theResult___fst_exp__h684644) ; + _theResult___exp__h685083 : + _theResult___fst_exp__h684641) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825 = - (guard__h694362 == 2'b0 || + (guard__h694359 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h702439 : - _theResult___exp__h702906 ; + _theResult___fst_exp__h702436 : + _theResult___exp__h702903 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827 = - (guard__h694362 == 2'b0) ? - _theResult___fst_exp__h702439 : + (guard__h694359 == 2'b0) ? + _theResult___fst_exp__h702436 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h702906 : - _theResult___fst_exp__h702439) ; + _theResult___exp__h702903 : + _theResult___fst_exp__h702436) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875 = - (guard__h676596 == 2'b0 || + (guard__h676593 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h684595[56:34] : - _theResult___sfd__h685087 ; + _theResult___snd__h684592[56:34] : + _theResult___sfd__h685084 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877 = - (guard__h676596 == 2'b0) ? - _theResult___snd__h684595[56:34] : + (guard__h676593 == 2'b0) ? + _theResult___snd__h684592[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h685087 : - _theResult___snd__h684595[56:34]) ; + _theResult___sfd__h685084 : + _theResult___snd__h684592[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921 = - (guard__h694362 == 2'b0 || + (guard__h694359 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h702385[56:34] : - _theResult___sfd__h702907 ; + _theResult___snd__h702382[56:34] : + _theResult___sfd__h702904 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923 = - (guard__h694362 == 2'b0) ? - _theResult___snd__h702385[56:34] : + (guard__h694359 == 2'b0) ? + _theResult___snd__h702382[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h702907 : - _theResult___snd__h702385[56:34]) ; + _theResult___sfd__h702904 : + _theResult___snd__h702382[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637 = - (guard__h585100 == 2'b0 || + (guard__h585097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h593148 : - _theResult___exp__h593590 ; + _theResult___fst_exp__h593145 : + _theResult___exp__h593587 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639 = - (guard__h585100 == 2'b0) ? - _theResult___fst_exp__h593148 : + (guard__h585097 == 2'b0) ? + _theResult___fst_exp__h593145 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h593590 : - _theResult___fst_exp__h593148) ; + _theResult___exp__h593587 : + _theResult___fst_exp__h593145) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031 = - (guard__h602866 == 2'b0 || + (guard__h602863 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h610943 : - _theResult___exp__h611410 ; + _theResult___fst_exp__h610940 : + _theResult___exp__h611407 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033 = - (guard__h602866 == 2'b0) ? - _theResult___fst_exp__h610943 : + (guard__h602863 == 2'b0) ? + _theResult___fst_exp__h610940 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h611410 : - _theResult___fst_exp__h610943) ; + _theResult___exp__h611407 : + _theResult___fst_exp__h610940) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081 = - (guard__h585100 == 2'b0 || + (guard__h585097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h593099[56:34] : - _theResult___sfd__h593591 ; + _theResult___snd__h593096[56:34] : + _theResult___sfd__h593588 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083 = - (guard__h585100 == 2'b0) ? - _theResult___snd__h593099[56:34] : + (guard__h585097 == 2'b0) ? + _theResult___snd__h593096[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h593591 : - _theResult___snd__h593099[56:34]) ; + _theResult___sfd__h593588 : + _theResult___snd__h593096[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127 = - (guard__h602866 == 2'b0 || + (guard__h602863 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h610889[56:34] : - _theResult___sfd__h611411 ; + _theResult___snd__h610886[56:34] : + _theResult___sfd__h611408 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129 = - (guard__h602866 == 2'b0) ? - _theResult___snd__h610889[56:34] : + (guard__h602863 == 2'b0) ? + _theResult___snd__h610886[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h611411 : - _theResult___snd__h610889[56:34]) ; + _theResult___sfd__h611408 : + _theResult___snd__h610886[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13118 = - (_theResult___fst_exp__h752623 == 11'd2047) ? + (_theResult___fst_exp__h752620 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19941,10 +19941,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 : + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13833 = - (_theResult___fst_exp__h830780 == 11'd2047) ? + (_theResult___fst_exp__h830777 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19952,10 +19952,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 : + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14040 = - (_theResult___fst_exp__h812370 == 11'd2047) ? + (_theResult___fst_exp__h812367 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19963,10 +19963,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 : + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14067 = - (_theResult___fst_exp__h830780 == 11'd2047) ? + (_theResult___fst_exp__h830777 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19974,10 +19974,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 : + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14603 = - (_theResult___fst_exp__h791476 == 11'd2047) ? + (_theResult___fst_exp__h791473 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19985,10 +19985,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 : + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14809 = - (_theResult___fst_exp__h773066 == 11'd2047) ? + (_theResult___fst_exp__h773063 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19996,10 +19996,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 : + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14836 = - (_theResult___fst_exp__h791476 == 11'd2047) ? + (_theResult___fst_exp__h791473 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20007,14 +20007,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 : + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213) ; assign IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116 = - (_theResult____h917995 == 16'd0 && + (_theResult____h917990 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h918566 : - _theResult____h917995 ; + enabled_ints__h918561 : + _theResult____h917990 ; assign IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20458 = IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[0] || IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[1] || @@ -20459,148 +20459,148 @@ module mkCore(CLK, 5'd0 : IF_IF_coreFix_aluExe_1_exeToFinQ_first__7660_B_ETC___d17805 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 = - ((f1_exp__h714825 == 8'd0) ? - (f1_sfd__h714826[22] ? + ((f1_exp__h714822 == 8'd0) ? + (f1_sfd__h714823[22] ? 6'd2 : - (f1_sfd__h714826[21] ? + (f1_sfd__h714823[21] ? 6'd3 : - (f1_sfd__h714826[20] ? + (f1_sfd__h714823[20] ? 6'd4 : - (f1_sfd__h714826[19] ? + (f1_sfd__h714823[19] ? 6'd5 : - (f1_sfd__h714826[18] ? + (f1_sfd__h714823[18] ? 6'd6 : - (f1_sfd__h714826[17] ? + (f1_sfd__h714823[17] ? 6'd7 : - (f1_sfd__h714826[16] ? + (f1_sfd__h714823[16] ? 6'd8 : - (f1_sfd__h714826[15] ? + (f1_sfd__h714823[15] ? 6'd9 : - (f1_sfd__h714826[14] ? + (f1_sfd__h714823[14] ? 6'd10 : - (f1_sfd__h714826[13] ? + (f1_sfd__h714823[13] ? 6'd11 : - (f1_sfd__h714826[12] ? + (f1_sfd__h714823[12] ? 6'd12 : - (f1_sfd__h714826[11] ? + (f1_sfd__h714823[11] ? 6'd13 : - (f1_sfd__h714826[10] ? + (f1_sfd__h714823[10] ? 6'd14 : - (f1_sfd__h714826[9] ? + (f1_sfd__h714823[9] ? 6'd15 : - (f1_sfd__h714826[8] ? + (f1_sfd__h714823[8] ? 6'd16 : - (f1_sfd__h714826[7] ? + (f1_sfd__h714823[7] ? 6'd17 : - (f1_sfd__h714826[6] ? + (f1_sfd__h714823[6] ? 6'd18 : - (f1_sfd__h714826[5] ? + (f1_sfd__h714823[5] ? 6'd19 : - (f1_sfd__h714826[4] ? + (f1_sfd__h714823[4] ? 6'd20 : - (f1_sfd__h714826[3] ? + (f1_sfd__h714823[3] ? 6'd21 : - (f1_sfd__h714826[2] ? + (f1_sfd__h714823[2] ? 6'd22 : - (f1_sfd__h714826[1] ? + (f1_sfd__h714823[1] ? 6'd23 : - (f1_sfd__h714826[0] ? + (f1_sfd__h714823[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13122 = - (f1_exp__h714825 == 8'd255 && f1_sfd__h714826 != 23'd0 || - (f1_exp__h714825 == 8'd255 || f1_exp__h714825 == 8'd0) && - f1_sfd__h714826 == 23'd0) ? + (f1_exp__h714822 == 8'd255 && f1_sfd__h714823 != 23'd0 || + (f1_exp__h714822 == 8'd255 || f1_exp__h714822 == 8'd0) && + f1_sfd__h714823 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h714825 == 8'd0) ? + ((f1_exp__h714822 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12777 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13120) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305 = - (f1_exp__h714825 == 8'd255 && f1_sfd__h714826 != 23'd0) ? - _theResult___snd_fst_sfd__h715141 : - _theResult___fst_sfd__h753422 ; + (f1_exp__h714822 == 8'd255 && f1_sfd__h714823 != 23'd0) ? + _theResult___snd_fst_sfd__h715138 : + _theResult___fst_sfd__h753419 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13306 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13122, - (f1_exp__h714825 == 8'd255) ? + (f1_exp__h714822 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h753418, + _theResult___fst_exp__h753415, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13305 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 = - ((f3_exp__h793123 == 8'd0) ? - (f3_sfd__h793124[22] ? + ((f3_exp__h793120 == 8'd0) ? + (f3_sfd__h793121[22] ? 6'd2 : - (f3_sfd__h793124[21] ? + (f3_sfd__h793121[21] ? 6'd3 : - (f3_sfd__h793124[20] ? + (f3_sfd__h793121[20] ? 6'd4 : - (f3_sfd__h793124[19] ? + (f3_sfd__h793121[19] ? 6'd5 : - (f3_sfd__h793124[18] ? + (f3_sfd__h793121[18] ? 6'd6 : - (f3_sfd__h793124[17] ? + (f3_sfd__h793121[17] ? 6'd7 : - (f3_sfd__h793124[16] ? + (f3_sfd__h793121[16] ? 6'd8 : - (f3_sfd__h793124[15] ? + (f3_sfd__h793121[15] ? 6'd9 : - (f3_sfd__h793124[14] ? + (f3_sfd__h793121[14] ? 6'd10 : - (f3_sfd__h793124[13] ? + (f3_sfd__h793121[13] ? 6'd11 : - (f3_sfd__h793124[12] ? + (f3_sfd__h793121[12] ? 6'd12 : - (f3_sfd__h793124[11] ? + (f3_sfd__h793121[11] ? 6'd13 : - (f3_sfd__h793124[10] ? + (f3_sfd__h793121[10] ? 6'd14 : - (f3_sfd__h793124[9] ? + (f3_sfd__h793121[9] ? 6'd15 : - (f3_sfd__h793124[8] ? + (f3_sfd__h793121[8] ? 6'd16 : - (f3_sfd__h793124[7] ? + (f3_sfd__h793121[7] ? 6'd17 : - (f3_sfd__h793124[6] ? + (f3_sfd__h793121[6] ? 6'd18 : - (f3_sfd__h793124[5] ? + (f3_sfd__h793121[5] ? 6'd19 : - (f3_sfd__h793124[4] ? + (f3_sfd__h793121[4] ? 6'd20 : - (f3_sfd__h793124[3] ? + (f3_sfd__h793121[3] ? 6'd21 : - (f3_sfd__h793124[2] ? + (f3_sfd__h793121[2] ? 6'd22 : - (f3_sfd__h793124[1] ? + (f3_sfd__h793121[1] ? 6'd23 : - (f3_sfd__h793124[0] ? + (f3_sfd__h793121[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13837 = - (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0 || - (f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && - f3_sfd__h793124 == 23'd0) ? + (f3_exp__h793120 == 8'd255 && f3_sfd__h793121 != 23'd0 || + (f3_exp__h793120 == 8'd255 || f3_exp__h793120 == 8'd0) && + f3_sfd__h793121 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h793123 == 8'd0) ? + ((f3_exp__h793120 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13492 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13835) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014 = - (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0) ? - _theResult___snd_fst_sfd__h793439 : - _theResult___fst_sfd__h831579 ; + (f3_exp__h793120 == 8'd255 && f3_sfd__h793121 != 23'd0) ? + _theResult___snd_fst_sfd__h793436 : + _theResult___fst_sfd__h831576 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14015 = - { (f3_exp__h793123 == 8'd255) ? + { (f3_exp__h793120 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h831575, + _theResult___fst_exp__h831572, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14014 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14070 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -20610,85 +20610,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14042) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14069 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14071 = - (f3_exp__h793123 == 8'd255 && f3_sfd__h793124 != 23'd0 || - (f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && - f3_sfd__h793124 == 23'd0) ? + (f3_exp__h793120 == 8'd255 && f3_sfd__h793121 != 23'd0 || + (f3_exp__h793120 == 8'd255 || f3_exp__h793120 == 8'd0) && + f3_sfd__h793121 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14070 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 = - ((f2_exp__h753819 == 8'd0) ? - (f2_sfd__h753820[22] ? + ((f2_exp__h753816 == 8'd0) ? + (f2_sfd__h753817[22] ? 6'd2 : - (f2_sfd__h753820[21] ? + (f2_sfd__h753817[21] ? 6'd3 : - (f2_sfd__h753820[20] ? + (f2_sfd__h753817[20] ? 6'd4 : - (f2_sfd__h753820[19] ? + (f2_sfd__h753817[19] ? 6'd5 : - (f2_sfd__h753820[18] ? + (f2_sfd__h753817[18] ? 6'd6 : - (f2_sfd__h753820[17] ? + (f2_sfd__h753817[17] ? 6'd7 : - (f2_sfd__h753820[16] ? + (f2_sfd__h753817[16] ? 6'd8 : - (f2_sfd__h753820[15] ? + (f2_sfd__h753817[15] ? 6'd9 : - (f2_sfd__h753820[14] ? + (f2_sfd__h753817[14] ? 6'd10 : - (f2_sfd__h753820[13] ? + (f2_sfd__h753817[13] ? 6'd11 : - (f2_sfd__h753820[12] ? + (f2_sfd__h753817[12] ? 6'd12 : - (f2_sfd__h753820[11] ? + (f2_sfd__h753817[11] ? 6'd13 : - (f2_sfd__h753820[10] ? + (f2_sfd__h753817[10] ? 6'd14 : - (f2_sfd__h753820[9] ? + (f2_sfd__h753817[9] ? 6'd15 : - (f2_sfd__h753820[8] ? + (f2_sfd__h753817[8] ? 6'd16 : - (f2_sfd__h753820[7] ? + (f2_sfd__h753817[7] ? 6'd17 : - (f2_sfd__h753820[6] ? + (f2_sfd__h753817[6] ? 6'd18 : - (f2_sfd__h753820[5] ? + (f2_sfd__h753817[5] ? 6'd19 : - (f2_sfd__h753820[4] ? + (f2_sfd__h753817[4] ? 6'd20 : - (f2_sfd__h753820[3] ? + (f2_sfd__h753817[3] ? 6'd21 : - (f2_sfd__h753820[2] ? + (f2_sfd__h753817[2] ? 6'd22 : - (f2_sfd__h753820[1] ? + (f2_sfd__h753817[1] ? 6'd23 : - (f2_sfd__h753820[0] ? + (f2_sfd__h753817[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14607 = - (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0 || - (f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && - f2_sfd__h753820 == 23'd0) ? + (f2_exp__h753816 == 8'd255 && f2_sfd__h753817 != 23'd0 || + (f2_exp__h753816 == 8'd255 || f2_exp__h753816 == 8'd0) && + f2_sfd__h753817 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h753819 == 8'd0) ? + ((f2_exp__h753816 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14262 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14605) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784 = - (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0) ? - _theResult___snd_fst_sfd__h754135 : - _theResult___fst_sfd__h792275 ; + (f2_exp__h753816 == 8'd255 && f2_sfd__h753817 != 23'd0) ? + _theResult___snd_fst_sfd__h754132 : + _theResult___fst_sfd__h792272 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14785 = - { (f2_exp__h753819 == 8'd255) ? + { (f2_exp__h753816 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h792271, + _theResult___fst_exp__h792268, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14784 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14839 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20698,15 +20698,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14811) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14838 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14840 = - (f2_exp__h753819 == 8'd255 && f2_sfd__h753820 != 23'd0 || - (f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && - f2_sfd__h753820 == 23'd0) ? + (f2_exp__h753816 == 8'd255 && f2_sfd__h753817 != 23'd0 || + (f2_exp__h753816 == 8'd255 || f2_exp__h753816 == 8'd0) && + f2_sfd__h753817 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14839 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14895 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[4] : @@ -20714,7 +20714,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14936 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[4] : @@ -20722,7 +20722,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14980 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[4] : @@ -20730,7 +20730,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14995 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[3] : @@ -20738,7 +20738,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15005 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[3] : @@ -20746,7 +20746,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15016 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[3] : @@ -20754,70 +20754,70 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15035 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15033 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15049 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15047 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15064 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15062 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15081 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15079 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15093 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15091 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15106 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15104 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15123 = - (f1_exp__h714825 == 8'd0) ? + (f1_exp__h714822 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15121 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15135 = - (f2_exp__h753819 == 8'd0) ? + (f2_exp__h753816 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15133 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15148 = - (f3_exp__h793123 == 8'd0) ? + (f3_exp__h793120 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15146 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231 = - _theResult_____2__h515296 == v__h514752 ; + _theResult_____2__h515292 == v__h514748 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7239 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7231 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 || @@ -20832,7 +20832,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7222 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322 = - _theResult_____2__h526073 == v__h516772 ; + _theResult_____2__h526069 == v__h516768 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7331 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7322 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 || @@ -20861,9 +20861,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h521603 } ; + x__h521599 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482 = - _theResult_____2__h533166 == v__h532491 ; + _theResult_____2__h533162 == v__h532487 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7490 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7482 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 || @@ -20878,7 +20878,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7475 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566 = - _theResult_____2__h543801 == v__h534940 ; + _theResult_____2__h543797 == v__h534936 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7574 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7566 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 || @@ -21275,7 +21275,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852 = - _theResult_____2__h561413 == v__h559739 ; + _theResult_____2__h561409 == v__h559735 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7860 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7852 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 || @@ -21290,7 +21290,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7846 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770 = - _theResult_____2__h557634 == v__h555960 ; + _theResult_____2__h557630 == v__h555956 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7778 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7770 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 || @@ -21308,12 +21308,12 @@ module mkCore(CLK, (csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h998356[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h998359 } : - { x__h998356[11:3], - x__h998377[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h998359[13:3], - x__h998377[2:0] } ; + { x__h998351[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h998354 } : + { x__h998351[11:3], + x__h998372[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h998354[13:3], + x__h998372[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0049_BITS__ETC___d21013 = IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d21004 ? !csrf_rg_dcsr[2] && @@ -21554,27 +21554,27 @@ module mkCore(CLK, 4'd0 : IF_IF_renameStage_rg_m_halt_req_0076_BIT_4_007_ETC___d20766 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 = - { INV_x83367_BITS_108_TO_90__q33[0] ? x__h183487 : 6'd0, - x__h183647, - x__h183667 } ; + { INV_x83366_BITS_108_TO_90__q33[0] ? x__h183486 : 6'd0, + x__h183646, + x__h183666 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 = - { INV_x99219_BITS_108_TO_90__q35[0] ? x__h202238 : 6'd0, - x__h202398, - x__h202418 } ; + { INV_x99218_BITS_108_TO_90__q35[0] ? x__h202237 : 6'd0, + x__h202397, + x__h202417 } ; assign IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h992421 : + x__h992416 : 6'd0 ; assign IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22432 = - x__h992601[13:11] < repBound__h995071 ; + x__h992596[13:11] < repBound__h995066 ; assign IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22434 = - pc_addrBits__h992212[13:11] < repBound__h995071 ; + pc_addrBits__h992207[13:11] < repBound__h995066 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19571 = - tb__h904585 < repBound__h904588 ; + tb__h904581 < repBound__h904584 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19572 = - x__h904527[13:11] < repBound__h904588 ; + x__h904523[13:11] < repBound__h904584 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19574 = - cr_addrBits__h904120[13:11] < repBound__h904588 ; + cr_addrBits__h904116[13:11] < repBound__h904584 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19584 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19574, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19571 == @@ -21592,11 +21592,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19635 = - tb__h905133 < repBound__h905136 ; + tb__h905129 < repBound__h905132 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19636 = - x__h905075[13:11] < repBound__h905136 ; + x__h905071[13:11] < repBound__h905132 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19638 = - cr_addrBits__h904668[13:11] < repBound__h905136 ; + cr_addrBits__h904664[13:11] < repBound__h905132 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19648 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19638, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9261__ETC___d19635 == @@ -21614,11 +21614,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17492 = - tb__h865963 < repBound__h865966 ; + tb__h865960 < repBound__h865963 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17493 = - x__h865905[13:11] < repBound__h865966 ; + x__h865902[13:11] < repBound__h865963 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17495 = - cr_addrBits__h865498[13:11] < repBound__h865966 ; + cr_addrBits__h865495[13:11] < repBound__h865963 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17505 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17495, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17492 == @@ -21636,11 +21636,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17556 = - tb__h866511 < repBound__h866514 ; + tb__h866508 < repBound__h866511 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17557 = - x__h866453[13:11] < repBound__h866514 ; + x__h866450[13:11] < repBound__h866511 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17559 = - cr_addrBits__h866046[13:11] < repBound__h866514 ; + cr_addrBits__h866043[13:11] < repBound__h866511 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17569 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17559, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7182__ETC___d17556 == @@ -21659,26 +21659,26 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? - x__h216804 : + x__h216803 : 6'd0, - x__h216964, - x__h216984 } ; + x__h216963, + x__h216983 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127310 : + x__h127309 : 6'd0, - x__h127470, - x__h127490 } ; + x__h127469, + x__h127489 } ; assign IF_INV_mmio_dataRespQ_data_0_389_BITS_108_TO_9_ETC___d1433 = { INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? - x__h140226 : + x__h140225 : 6'd0, - x__h140386, - x__h140406 } ; + x__h140385, + x__h140405 } ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12777 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 || - _theResult___fst_exp__h734213 == 11'd2047) ? + _theResult___fst_exp__h734210 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21686,12 +21686,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13492 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 || - _theResult___fst_exp__h812370 == 11'd2047) ? + _theResult___fst_exp__h812367 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21699,12 +21699,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 : + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14262 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 || - _theResult___fst_exp__h773066 == 11'd2047) ? + _theResult___fst_exp__h773063 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21712,7 +21712,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 : + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3__ETC___d20687 = IF_IF_NOT_csrf_prv_reg_read__0079_EQ_3_0080_00_ETC___d20116[0] ? @@ -23436,48 +23436,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15033 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[2] : - _theResult___fst_exp__h753406 == 11'd2047 && - _theResult___fst_sfd__h753407 == 52'd0 ; + _theResult___fst_exp__h753403 == 11'd2047 && + _theResult___fst_sfd__h753404 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15047 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[2] : - _theResult___fst_exp__h792259 == 11'd2047 && - _theResult___fst_sfd__h792260 == 52'd0 ; + _theResult___fst_exp__h792256 == 11'd2047 && + _theResult___fst_sfd__h792257 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15062 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[2] : - _theResult___fst_exp__h831563 == 11'd2047 && - _theResult___fst_sfd__h831564 == 52'd0 ; + _theResult___fst_exp__h831560 == 11'd2047 && + _theResult___fst_sfd__h831561 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15079 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[1] : - _theResult___fst_exp__h752623 == 11'd0 && - guard__h744633 != 2'b0 ; + _theResult___fst_exp__h752620 == 11'd0 && + guard__h744630 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15091 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[1] : - _theResult___fst_exp__h791476 == 11'd0 && - guard__h783486 != 2'b0 ; + _theResult___fst_exp__h791473 == 11'd0 && + guard__h783483 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15104 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[1] : - _theResult___fst_exp__h830780 == 11'd0 && - guard__h822790 != 2'b0 ; + _theResult___fst_exp__h830777 == 11'd0 && + guard__h822787 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15121 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891[0] : - _theResult___fst_exp__h752623 != 11'd2047 && - guard__h744633 != 2'b0 ; + _theResult___fst_exp__h752620 != 11'd2047 && + guard__h744630 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15133 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932[0] : - _theResult___fst_exp__h791476 != 11'd2047 && - guard__h783486 != 2'b0 ; + _theResult___fst_exp__h791473 != 11'd2047 && + guard__h783483 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15146 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976[0] : - _theResult___fst_exp__h830780 != 11'd2047 && - guard__h822790 != 2'b0 ; + _theResult___fst_exp__h830777 != 11'd2047 && + guard__h822787 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] == 8'd0) ? @@ -23487,35 +23487,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10601 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - ((_theResult___fst_exp__h648007 == 8'd255) ? + ((_theResult___fst_exp__h648004 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586) : - ((_theResult___fst_exp__h656692 == 8'd255) ? + ((_theResult___fst_exp__h656689 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10638 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - ((_theResult___fst_exp__h648007 == 8'd255) ? + ((_theResult___fst_exp__h648004 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629) : - ((_theResult___fst_exp__h656692 == 8'd255) ? + ((_theResult___fst_exp__h656689 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10734 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[2] : - _theResult___fst_exp__h657240 == 8'd255 && - _theResult___fst_sfd__h657241 == 23'd0 ; + _theResult___fst_exp__h657237 == 8'd255 && + _theResult___fst_sfd__h657238 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10747 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[1] : - _theResult___fst_exp__h656692 == 8'd0 && - guard__h648615 != 2'b0 ; + _theResult___fst_exp__h656689 == 8'd0 && + guard__h648612 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10760 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705[0] : - _theResult___fst_exp__h656692 != 8'd255 && - guard__h648615 != 2'b0 ; + _theResult___fst_exp__h656689 != 8'd255 && + guard__h648612 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] == 8'd0) ? @@ -23525,35 +23525,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11998 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - ((_theResult___fst_exp__h693754 == 8'd255) ? + ((_theResult___fst_exp__h693751 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983) : - ((_theResult___fst_exp__h702439 == 8'd255) ? + ((_theResult___fst_exp__h702436 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12035 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - ((_theResult___fst_exp__h693754 == 8'd255) ? + ((_theResult___fst_exp__h693751 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026) : - ((_theResult___fst_exp__h702439 == 8'd255) ? + ((_theResult___fst_exp__h702436 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12131 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[2] : - _theResult___fst_exp__h702987 == 8'd255 && - _theResult___fst_sfd__h702988 == 23'd0 ; + _theResult___fst_exp__h702984 == 8'd255 && + _theResult___fst_sfd__h702985 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12144 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[1] : - _theResult___fst_exp__h702439 == 8'd0 && - guard__h694362 != 2'b0 ; + _theResult___fst_exp__h702436 == 8'd0 && + guard__h694359 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12157 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102[0] : - _theResult___fst_exp__h702439 != 8'd255 && - guard__h694362 != 2'b0 ; + _theResult___fst_exp__h702436 != 8'd255 && + guard__h694359 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] == 8'd0) ? @@ -23563,41 +23563,41 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9204 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - ((_theResult___fst_exp__h602258 == 8'd255) ? + ((_theResult___fst_exp__h602255 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189) : - ((_theResult___fst_exp__h610943 == 8'd255) ? + ((_theResult___fst_exp__h610940 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9241 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - ((_theResult___fst_exp__h602258 == 8'd255) ? + ((_theResult___fst_exp__h602255 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232) : - ((_theResult___fst_exp__h610943 == 8'd255) ? + ((_theResult___fst_exp__h610940 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9337 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[2] : - _theResult___fst_exp__h611491 == 8'd255 && - _theResult___fst_sfd__h611492 == 23'd0 ; + _theResult___fst_exp__h611488 == 8'd255 && + _theResult___fst_sfd__h611489 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9350 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[1] : - _theResult___fst_exp__h610943 == 8'd0 && - guard__h602866 != 2'b0 ; + _theResult___fst_exp__h610940 == 8'd0 && + guard__h602863 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9363 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308[0] : - _theResult___fst_exp__h610943 != 8'd255 && - guard__h602866 != 2'b0 ; + _theResult___fst_exp__h610940 != 8'd255 && + guard__h602863 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__633_BI_ETC___d4077 = - offset__h242559[63] ? - x__h242708[13:0] >= toBounds__h242587 && - repBoundBits__h242584 != + offset__h242558[63] ? + x__h242707[13:0] >= toBounds__h242586 && + repBoundBits__h242583 != coreFix_memExe_regToExeQ$first[316:303] : - x__h242708[13:0] < toBoundsM1__h242588 ; + x__h242707[13:0] < toBoundsM1__h242587 ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8201_ETC___d18233 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && @@ -23673,24 +23673,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18416 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18624 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h890898 : + res_address__h890894 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18622 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d18639 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h890899 : + res_addrBits__h890895 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18637 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19198 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h896912 : + thin_reserved__h896908 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h896913 : + thin_otype__h896909 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19186, @@ -23699,7 +23699,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19199 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h897088 : + thin_perms_soft__h897084 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19044, @@ -23730,18 +23730,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19198 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19200 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h896908 : + thin_address__h896904 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h896909 : + thin_addrBits__h896905 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19199 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19221 = - thin_bounds_topBits__h898314[13:11] < repBound__h898430 ; + thin_bounds_topBits__h898310[13:11] < repBound__h898426 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19223 = - thin_bounds_baseBits__h898315[13:11] < repBound__h898430 ; + thin_bounds_baseBits__h898311[13:11] < repBound__h898426 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19226 = - thin_addrBits__h896909[13:11] < repBound__h898430 ; + thin_addrBits__h896905[13:11] < repBound__h898426 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19885 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -23954,24 +23954,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d15804 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16240 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h848497 : + res_address__h848494 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16238 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16255 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h848498 : + res_addrBits__h848495 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16253 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17093 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h857278 : + thin_reserved__h857275 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h857279 : + thin_otype__h857276 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17068, @@ -23980,7 +23980,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17094 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h857526 : + thin_perms_soft__h857523 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16731, @@ -24011,18 +24011,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17093 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17095 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h857274 : + thin_address__h857271 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h857275 : + thin_addrBits__h857272 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17094 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17142 = - thin_bounds_topBits__h859272[13:11] < repBound__h859420 ; + thin_bounds_topBits__h859269[13:11] < repBound__h859417 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17144 = - thin_bounds_baseBits__h859273[13:11] < repBound__h859420 ; + thin_bounds_baseBits__h859270[13:11] < repBound__h859417 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17147 = - thin_addrBits__h857275[13:11] < repBound__h859420 ; + thin_addrBits__h857272[13:11] < repBound__h859417 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17807 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -24784,8 +24784,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d19990 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h913573 : - w__h913568 ; + result__h913568 : + w__h913563 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d4993 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25259,15 +25259,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__680_BIT_1_ETC___d3622 } ; assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3058 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h235268 : + res_addrBits__h235267 : ((coreFix_memExe_dispToRegQ$first[109] && coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3056 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3303 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h235267 : - x__h235690, + res_address__h235266 : + x__h235689, IF_coreFix_memExe_dispToRegQ_first__680_BIT_12_ETC___d3058, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25406,13 +25406,13 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4231 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h242569[3:0] != 4'd0 : + pointer__h242568[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h242569[2:0] != 3'd0 : + pointer__h242568[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h242569[1:0] != 2'd0 : + pointer__h242568[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h242569[0])), + pointer__h242568[0])), capChecks___d4142[11:5], CASE_capChecks_142_BITS_4_TO_0_0_capChecks_142_ETC__q289, prepareBoundsCheck___d4226 } ; @@ -25534,7 +25534,7 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22623 = - ((newAddrDiff__h997630 == 64'd0) ? + ((newAddrDiff__h997625 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22599 ? 2'd3 : @@ -25551,12 +25551,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22626 = IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22623 && - (newAddrDiff__h997630 == 64'd0 || + (newAddrDiff__h997625 == 64'd0 || csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22599 || - newAddrDiff__h997630 == + newAddrDiff__h997625 == _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602) ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22648 = - ((newAddrDiff__h997974 == 64'd0) ? + ((newAddrDiff__h997969 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22632 ? 2'd3 : @@ -25573,12 +25573,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22651 = IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22648 && - (newAddrDiff__h997974 == 64'd0 || + (newAddrDiff__h997969 == 64'd0 || csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22632 || - newAddrDiff__h997974 == + newAddrDiff__h997969 == _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602) ; assign IF_csrf_mtcc_reg_read__6627_BIT_86_2584_AND_NO_ETC___d22654 = - (csrf_mtcc_reg[86] && cause_interrupt__h992790) ? + (csrf_mtcc_reg[86] && cause_interrupt__h992785) ? (NOT_csrf_mtcc_reg_read__6627_BITS_33_TO_28_258_ETC___d22588 || IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22626) && csrf_mtcc_reg[152] : @@ -25586,9 +25586,9 @@ module mkCore(CLK, IF_csrf_mtcc_reg_read__6627_BITS_149_TO_86_258_ETC___d22651) && csrf_mtcc_reg[152] ; assign IF_csrf_mtcc_reg_read__6627_BIT_86_2584_AND_NO_ETC___d22688 = - (csrf_mtcc_reg[86] && cause_interrupt__h992790) ? - address__h996950 : - base__h996915 ; + (csrf_mtcc_reg[86] && cause_interrupt__h992785) ? + address__h996945 : + base__h996910 ; assign IF_csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_c_ETC___d22659 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? { IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22579, @@ -25708,7 +25708,7 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22548 = - ((newAddrDiff__h996973 == 64'd0) ? + ((newAddrDiff__h996968 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22524 ? 2'd3 : @@ -25725,12 +25725,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22551 = IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22548 && - (newAddrDiff__h996973 == 64'd0 || + (newAddrDiff__h996968 == 64'd0 || csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22524 || - newAddrDiff__h996973 == + newAddrDiff__h996968 == _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527) ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22573 = - ((newAddrDiff__h997317 == 64'd0) ? + ((newAddrDiff__h997312 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22557 ? 2'd3 : @@ -25747,12 +25747,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22576 = IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22573 && - (newAddrDiff__h997317 == 64'd0 || + (newAddrDiff__h997312 == 64'd0 || csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22557 || - newAddrDiff__h997317 == + newAddrDiff__h997312 == _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527) ; assign IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22579 = - (csrf_stcc_reg[86] && cause_interrupt__h992790) ? + (csrf_stcc_reg[86] && cause_interrupt__h992785) ? (NOT_csrf_stcc_reg_read__6618_BITS_33_TO_28_250_ETC___d22511 || IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22551) && csrf_stcc_reg[152] : @@ -25760,9 +25760,9 @@ module mkCore(CLK, IF_csrf_stcc_reg_read__6618_BITS_149_TO_86_251_ETC___d22576) && csrf_stcc_reg[152] ; assign IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22687 = - (csrf_stcc_reg[86] && cause_interrupt__h992790) ? - address__h996900 : - base__h996861 ; + (csrf_stcc_reg[86] && cause_interrupt__h992785) ? + address__h996895 : + base__h996856 ; assign IF_fetchStage_RDY_pipelines_0_first__0046_AND__ETC___d20968 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[267:265] != 3'd1 || @@ -26168,13 +26168,13 @@ module mkCore(CLK, 2'd3) } ; assign IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1010691 : + y_avValue_snd_snd_snd_snd_snd__h1010686 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1010675 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1010670 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1010685 : + y_avValue_snd_snd_snd_fst__h1010680 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__3175_THEN_IF_NOT_rob__ETC___d23412 = rob$deqPort_1_canDeq ? @@ -26308,7 +26308,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18875) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18897 = sbCons$lazyLookup_0_get[3] ? - repBound__h896085 : + repBound__h896081 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8222_8_ETC___d18249 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__822_ETC___d18893) ; @@ -26339,7 +26339,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19000 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h898412, + repBound__h898408, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18972, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18973, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18985 } : @@ -26474,7 +26474,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16491) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16513 = sbCons$lazyLookup_1_get[3] ? - repBound__h856058 : + repBound__h856055 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5610_5_ETC___d15637 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__561_ETC___d16509) ; @@ -26505,7 +26505,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16616 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h859402, + repBound__h859399, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16589, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16601 } : @@ -26640,7 +26640,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3293) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3315 = sbCons$lazyLookup_3_get[3] ? - repBound__h237262 : + repBound__h237261 : (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2725 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3311) ; @@ -26796,7 +26796,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3560) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3577 = sbCons$lazyLookup_3_get[2] ? - repBound__h238947 : + repBound__h238946 : (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3573) ; @@ -26824,64 +26824,64 @@ module mkCore(CLK, (NOT_coreFix_memExe_bypassWire_0_whas__698_704__ETC___d2752 ? coreFix_aluExe_0_bypassWire_3$wget[3:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d3616) ; - assign IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50 = - sfdin__h602252[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167 = - sfdin__h821941[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75 = - sfdin__h630235[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150 = - sfdin__h743784[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85 = - sfdin__h648001[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110 = - sfdin__h675982[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190 = - sfdin__h782637[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40 = - sfdin__h584486[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120 = - sfdin__h693748[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125 = - _theResult___snd__h702385[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55 = - _theResult___snd__h610889[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163 = - _theResult___snd__h812321[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170 = - _theResult___snd__h830726[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146 = - _theResult___snd__h734164[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77 = - _theResult___snd__h638848[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153 = - _theResult___snd__h752569[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90 = - _theResult___snd__h656638[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186 = - _theResult___snd__h773017[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112 = - _theResult___snd__h684595[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193 = - _theResult___snd__h791422[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42 = - _theResult___snd__h593099[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin02249_BIT_33_THEN_2_ELSE_0__q50 = + sfdin__h602249[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin21938_BIT_4_THEN_2_ELSE_0__q167 = + sfdin__h821938[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin30232_BIT_33_THEN_2_ELSE_0__q75 = + sfdin__h630232[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin43781_BIT_4_THEN_2_ELSE_0__q150 = + sfdin__h743781[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin47998_BIT_33_THEN_2_ELSE_0__q85 = + sfdin__h647998[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin75979_BIT_33_THEN_2_ELSE_0__q110 = + sfdin__h675979[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin82634_BIT_4_THEN_2_ELSE_0__q190 = + sfdin__h782634[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin84483_BIT_33_THEN_2_ELSE_0__q40 = + sfdin__h584483[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin93745_BIT_33_THEN_2_ELSE_0__q120 = + sfdin__h693745[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02382_BIT_33_THEN_2_ELSE_0__q125 = + _theResult___snd__h702382[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd10886_BIT_33_THEN_2_ELSE_0__q55 = + _theResult___snd__h610886[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12318_BIT_4_THEN_2_ELSE_0__q163 = + _theResult___snd__h812318[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30723_BIT_4_THEN_2_ELSE_0__q170 = + _theResult___snd__h830723[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd34161_BIT_4_THEN_2_ELSE_0__q146 = + _theResult___snd__h734161[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd38845_BIT_33_THEN_2_ELSE_0__q77 = + _theResult___snd__h638845[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd52566_BIT_4_THEN_2_ELSE_0__q153 = + _theResult___snd__h752566[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56635_BIT_33_THEN_2_ELSE_0__q90 = + _theResult___snd__h656635[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd73014_BIT_4_THEN_2_ELSE_0__q186 = + _theResult___snd__h773014[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84592_BIT_33_THEN_2_ELSE_0__q112 = + _theResult___snd__h684592[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd91419_BIT_4_THEN_2_ELSE_0__q193 = + _theResult___snd__h791419[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd93096_BIT_33_THEN_2_ELSE_0__q42 = + _theResult___snd__h593096[33] ? 2'd2 : 2'd0 ; assign INV_commitStage_commitTrap_BITS_217_TO_199__q15 = ~commitStage_commitTrap[217:199] ; assign INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19564 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h904334 : + x__h904330 : 6'd0, - x__h904507, - x__h904527 } ; + x__h904503, + x__h904523 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9261_BIT_ETC___d19628 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h904882 : + x__h904878 : 6'd0, - x__h905055, - x__h905075 } ; + x__h905051, + x__h905071 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -26889,17 +26889,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17485 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h865712 : + x__h865709 : 6'd0, - x__h865885, - x__h865905 } ; + x__h865882, + x__h865902 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7182_BIT_ETC___d17549 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h866260 : + x__h866257 : 6'd0, - x__h866433, - x__h866453 } ; + x__h866430, + x__h866450 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -26910,8 +26910,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x83367_BITS_108_TO_90__q33 = ~x__h183367[108:90] ; - assign INV_x99219_BITS_108_TO_90__q35 = ~x__h199219[108:90] ; + assign INV_x83366_BITS_108_TO_90__q33 = ~x__h183366[108:90] ; + assign INV_x99218_BITS_108_TO_90__q35 = ~x__h199218[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10728 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? @@ -27000,130 +27000,130 @@ module mkCore(CLK, !checkForException___d21375[13] && NOT_csrf_fs_reg_read__5969_EQ_0_0422_0423_OR_N_ETC___d21400 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__3171_3172_OR__ETC___d23417 = - (fflags__h1011197 & csrf_fflags_reg) != fflags__h1011197 || - !r__h852737 && + (fflags__h1011192 & csrf_fflags_reg) != fflags__h1011192 || + !r__h852734 && (IF_rob_deqPort_1_canDeq__3175_THEN_IF_NOT_rob__ETC___d23412 || - fflags__h1011197 != 5'd0) ; + fflags__h1011192 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 = - !f1_sfd__h714826[21] && !f1_sfd__h714826[20] && - !f1_sfd__h714826[19] && - !f1_sfd__h714826[18] && - !f1_sfd__h714826[17] && - !f1_sfd__h714826[16] && - !f1_sfd__h714826[15] && - !f1_sfd__h714826[14] && - !f1_sfd__h714826[13] && - !f1_sfd__h714826[12] && - !f1_sfd__h714826[11] && - !f1_sfd__h714826[10] && - !f1_sfd__h714826[9] && - !f1_sfd__h714826[8] && - !f1_sfd__h714826[7] && - !f1_sfd__h714826[6] && - !f1_sfd__h714826[5] && - !f1_sfd__h714826[4] && - !f1_sfd__h714826[3] && - !f1_sfd__h714826[2] && - !f1_sfd__h714826[1] && - !f1_sfd__h714826[0] ; + !f1_sfd__h714823[21] && !f1_sfd__h714823[20] && + !f1_sfd__h714823[19] && + !f1_sfd__h714823[18] && + !f1_sfd__h714823[17] && + !f1_sfd__h714823[16] && + !f1_sfd__h714823[15] && + !f1_sfd__h714823[14] && + !f1_sfd__h714823[13] && + !f1_sfd__h714823[12] && + !f1_sfd__h714823[11] && + !f1_sfd__h714823[10] && + !f1_sfd__h714823[9] && + !f1_sfd__h714823[8] && + !f1_sfd__h714823[7] && + !f1_sfd__h714823[6] && + !f1_sfd__h714823[5] && + !f1_sfd__h714823[4] && + !f1_sfd__h714823[3] && + !f1_sfd__h714823[2] && + !f1_sfd__h714823[1] && + !f1_sfd__h714823[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 = - !f3_sfd__h793124[21] && !f3_sfd__h793124[20] && - !f3_sfd__h793124[19] && - !f3_sfd__h793124[18] && - !f3_sfd__h793124[17] && - !f3_sfd__h793124[16] && - !f3_sfd__h793124[15] && - !f3_sfd__h793124[14] && - !f3_sfd__h793124[13] && - !f3_sfd__h793124[12] && - !f3_sfd__h793124[11] && - !f3_sfd__h793124[10] && - !f3_sfd__h793124[9] && - !f3_sfd__h793124[8] && - !f3_sfd__h793124[7] && - !f3_sfd__h793124[6] && - !f3_sfd__h793124[5] && - !f3_sfd__h793124[4] && - !f3_sfd__h793124[3] && - !f3_sfd__h793124[2] && - !f3_sfd__h793124[1] && - !f3_sfd__h793124[0] ; + !f3_sfd__h793121[21] && !f3_sfd__h793121[20] && + !f3_sfd__h793121[19] && + !f3_sfd__h793121[18] && + !f3_sfd__h793121[17] && + !f3_sfd__h793121[16] && + !f3_sfd__h793121[15] && + !f3_sfd__h793121[14] && + !f3_sfd__h793121[13] && + !f3_sfd__h793121[12] && + !f3_sfd__h793121[11] && + !f3_sfd__h793121[10] && + !f3_sfd__h793121[9] && + !f3_sfd__h793121[8] && + !f3_sfd__h793121[7] && + !f3_sfd__h793121[6] && + !f3_sfd__h793121[5] && + !f3_sfd__h793121[4] && + !f3_sfd__h793121[3] && + !f3_sfd__h793121[2] && + !f3_sfd__h793121[1] && + !f3_sfd__h793121[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 = - !f2_sfd__h753820[21] && !f2_sfd__h753820[20] && - !f2_sfd__h753820[19] && - !f2_sfd__h753820[18] && - !f2_sfd__h753820[17] && - !f2_sfd__h753820[16] && - !f2_sfd__h753820[15] && - !f2_sfd__h753820[14] && - !f2_sfd__h753820[13] && - !f2_sfd__h753820[12] && - !f2_sfd__h753820[11] && - !f2_sfd__h753820[10] && - !f2_sfd__h753820[9] && - !f2_sfd__h753820[8] && - !f2_sfd__h753820[7] && - !f2_sfd__h753820[6] && - !f2_sfd__h753820[5] && - !f2_sfd__h753820[4] && - !f2_sfd__h753820[3] && - !f2_sfd__h753820[2] && - !f2_sfd__h753820[1] && - !f2_sfd__h753820[0] ; + !f2_sfd__h753817[21] && !f2_sfd__h753817[20] && + !f2_sfd__h753817[19] && + !f2_sfd__h753817[18] && + !f2_sfd__h753817[17] && + !f2_sfd__h753817[16] && + !f2_sfd__h753817[15] && + !f2_sfd__h753817[14] && + !f2_sfd__h753817[13] && + !f2_sfd__h753817[12] && + !f2_sfd__h753817[11] && + !f2_sfd__h753817[10] && + !f2_sfd__h753817[9] && + !f2_sfd__h753817[8] && + !f2_sfd__h753817[7] && + !f2_sfd__h753817[6] && + !f2_sfd__h753817[5] && + !f2_sfd__h753817[4] && + !f2_sfd__h753817[3] && + !f2_sfd__h753817[2] && + !f2_sfd__h753817[1] && + !f2_sfd__h753817[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14895 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14898 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14936) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14995 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14998 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15005) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15035 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15038 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15049) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15081 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15084 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15093) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126 = - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 == 23'd0) && - (f1_exp__h714825 != 8'd255 || f1_sfd__h714826 != 23'd0) && - (f1_exp__h714825 != 8'd0 || f1_sfd__h714826 != 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 == 23'd0) && + (f1_exp__h714822 != 8'd255 || f1_sfd__h714823 != 23'd0) && + (f1_exp__h714822 != 8'd0 || f1_sfd__h714823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15123 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15126 | - ((f2_exp__h753819 != 8'd255 || f2_sfd__h753820 == 23'd0) && - (f2_exp__h753819 != 8'd255 || f2_sfd__h753820 != 23'd0) && - (f2_exp__h753819 != 8'd0 || f2_sfd__h753820 != 23'd0) && + ((f2_exp__h753816 != 8'd255 || f2_sfd__h753817 == 23'd0) && + (f2_exp__h753816 != 8'd255 || f2_sfd__h753817 != 23'd0) && + (f2_exp__h753816 != 8'd0 || f2_sfd__h753817 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15135) ; assign NOT_commitStage_commitTrap_2039_BITS_44_TO_43__ETC___d22305 = commitStage_commitTrap[44:43] != 2'd0 && @@ -28280,7 +28280,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q311, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q312, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7119, - x__h508693 } ; + x__h508690 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d23934 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q313, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q314, @@ -28303,8 +28303,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q307 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 = - { {4{f1_exp14825_MINUS_127__q147[7]}}, - f1_exp14825_MINUS_127__q147 } ; + { {4{f1_exp14822_MINUS_127__q147[7]}}, + f1_exp14822_MINUS_127__q147 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12779 ^ 12'h800) <= @@ -28314,8 +28314,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 = - { {4{f3_exp93123_MINUS_127__q164[7]}}, - f3_exp93123_MINUS_127__q164 } ; + { {4{f3_exp93120_MINUS_127__q164[7]}}, + f3_exp93120_MINUS_127__q164 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13494 ^ 12'h800) <= @@ -28325,8 +28325,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 = - { {4{f2_exp53819_MINUS_127__q187[7]}}, - f2_exp53819_MINUS_127__q187 } ; + { {4{f2_exp53816_MINUS_127__q187[7]}}, + f2_exp53816_MINUS_127__q187 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14264 ^ 12'h800) <= @@ -28354,11 +28354,11 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4863 = - { {64{x__h264659[63]}}, x__h264659 } ; + { {64{x__h264656[63]}}, x__h264656 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4871 = - { {96{x__h264814[31]}}, x__h264814 } ; + { {96{x__h264811[31]}}, x__h264811 } ; assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448 = - x__h995059 | in__h995128[63:0] ; + x__h995054 | in__h995123[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10053 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q82 } ; @@ -28412,15 +28412,15 @@ module mkCore(CLK, 8'd127 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10676 = { 3'd0, - _theResult___fst_exp__h630241 == 8'd0 && - (sfdin__h630235[56:34] == 23'd0 || guard__h622142 != 2'b0), + _theResult___fst_exp__h630238 == 8'd0 && + (sfdin__h630232[56:34] == 23'd0 || guard__h622139 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h630838 == 8'd255 && - _theResult___fst_sfd__h630839 == 23'd0, + _theResult___fst_exp__h630835 == 8'd255 && + _theResult___fst_sfd__h630836 == 23'd0, 1'd0, - _theResult___fst_exp__h630241 != 8'd255 && - guard__h622142 != 2'b0 } ; + _theResult___fst_exp__h630238 != 8'd255 && + guard__h622139 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 } ^ @@ -28428,15 +28428,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12073 = { 3'd0, - _theResult___fst_exp__h675988 == 8'd0 && - (sfdin__h675982[56:34] == 23'd0 || guard__h667889 != 2'b0), + _theResult___fst_exp__h675985 == 8'd0 && + (sfdin__h675979[56:34] == 23'd0 || guard__h667886 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h676585 == 8'd255 && - _theResult___fst_sfd__h676586 == 23'd0, + _theResult___fst_exp__h676582 == 8'd255 && + _theResult___fst_sfd__h676583 == 23'd0, 1'd0, - _theResult___fst_exp__h675988 != 8'd255 && - guard__h667889 != 2'b0 } ; + _theResult___fst_exp__h675985 != 8'd255 && + guard__h667886 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 } ^ @@ -28444,15 +28444,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9279 = { 3'd0, - _theResult___fst_exp__h584492 == 8'd0 && - (sfdin__h584486[56:34] == 23'd0 || guard__h576391 != 2'b0), + _theResult___fst_exp__h584489 == 8'd0 && + (sfdin__h584483[56:34] == 23'd0 || guard__h576388 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h585089 == 8'd255 && - _theResult___fst_sfd__h585090 == 23'd0, + _theResult___fst_exp__h585086 == 8'd255 && + _theResult___fst_sfd__h585087 == 23'd0, 1'd0, - _theResult___fst_exp__h584492 != 8'd255 && - guard__h576391 != 2'b0 } ; + _theResult___fst_exp__h584489 != 8'd255 && + guard__h576388 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 } ^ @@ -28475,37 +28475,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14891 = { 3'd0, - _theResult___fst_exp__h743790 == 11'd0 && - (sfdin__h743784[56:5] == 52'd0 || guard__h735564 != 2'b0), + _theResult___fst_exp__h743787 == 11'd0 && + (sfdin__h743781[56:5] == 52'd0 || guard__h735561 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h744622 == 11'd2047 && - _theResult___fst_sfd__h744623 == 52'd0, + _theResult___fst_exp__h744619 == 11'd2047 && + _theResult___fst_sfd__h744620 == 52'd0, 1'd0, - _theResult___fst_exp__h743790 != 11'd2047 && - guard__h735564 != 2'b0 } ; + _theResult___fst_exp__h743787 != 11'd2047 && + guard__h735561 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14932 = { 3'd0, - _theResult___fst_exp__h782643 == 11'd0 && - (sfdin__h782637[56:5] == 52'd0 || guard__h774417 != 2'b0), + _theResult___fst_exp__h782640 == 11'd0 && + (sfdin__h782634[56:5] == 52'd0 || guard__h774414 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h783475 == 11'd2047 && - _theResult___fst_sfd__h783476 == 52'd0, + _theResult___fst_exp__h783472 == 11'd2047 && + _theResult___fst_sfd__h783473 == 52'd0, 1'd0, - _theResult___fst_exp__h782643 != 11'd2047 && - guard__h774417 != 2'b0 } ; + _theResult___fst_exp__h782640 != 11'd2047 && + guard__h774414 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14976 = { 3'd0, - _theResult___fst_exp__h821947 == 11'd0 && - (sfdin__h821941[56:5] == 52'd0 || guard__h813721 != 2'b0), + _theResult___fst_exp__h821944 == 11'd0 && + (sfdin__h821938[56:5] == 52'd0 || guard__h813718 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h822779 == 11'd2047 && - _theResult___fst_sfd__h822780 == 52'd0, + _theResult___fst_exp__h822776 == 11'd2047 && + _theResult___fst_sfd__h822777 == 52'd0, 1'd0, - _theResult___fst_exp__h821947 != 11'd2047 && - guard__h813721 != 2'b0 } ; + _theResult___fst_exp__h821944 != 11'd2047 && + guard__h813718 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 } ^ @@ -28513,15 +28513,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10705 = { 3'd0, - _theResult___fst_exp__h648007 == 8'd0 && - (sfdin__h648001[56:34] == 23'd0 || guard__h639779 != 2'b0), + _theResult___fst_exp__h648004 == 8'd0 && + (sfdin__h647998[56:34] == 23'd0 || guard__h639776 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h648604 == 8'd255 && - _theResult___fst_sfd__h648605 == 23'd0, + _theResult___fst_exp__h648601 == 8'd255 && + _theResult___fst_sfd__h648602 == 23'd0, 1'd0, - _theResult___fst_exp__h648007 != 8'd255 && - guard__h639779 != 2'b0 } ; + _theResult___fst_exp__h648004 != 8'd255 && + guard__h639776 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 } ^ @@ -28529,15 +28529,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12102 = { 3'd0, - _theResult___fst_exp__h693754 == 8'd0 && - (sfdin__h693748[56:34] == 23'd0 || guard__h685526 != 2'b0), + _theResult___fst_exp__h693751 == 8'd0 && + (sfdin__h693745[56:34] == 23'd0 || guard__h685523 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h694351 == 8'd255 && - _theResult___fst_sfd__h694352 == 23'd0, + _theResult___fst_exp__h694348 == 8'd255 && + _theResult___fst_sfd__h694349 == 23'd0, 1'd0, - _theResult___fst_exp__h693754 != 8'd255 && - guard__h685526 != 2'b0 } ; + _theResult___fst_exp__h693751 != 8'd255 && + guard__h685523 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 } ^ @@ -28545,15 +28545,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9308 = { 3'd0, - _theResult___fst_exp__h602258 == 8'd0 && - (sfdin__h602252[56:34] == 23'd0 || guard__h594030 != 2'b0), + _theResult___fst_exp__h602255 == 8'd0 && + (sfdin__h602249[56:34] == 23'd0 || guard__h594027 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h602855 == 8'd255 && - _theResult___fst_sfd__h602856 == 23'd0, + _theResult___fst_exp__h602852 == 8'd255 && + _theResult___fst_sfd__h602853 == 23'd0, 1'd0, - _theResult___fst_exp__h602258 != 8'd255 && - guard__h594030 != 2'b0 } ; + _theResult___fst_exp__h602255 != 8'd255 && + guard__h594027 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ^ @@ -28589,37 +28589,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14874 = { 3'd0, - _theResult___fst_exp__h734213 == 11'd0 && - guard__h726252 != 2'b0, + _theResult___fst_exp__h734210 == 11'd0 && + guard__h726249 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h734971 == 11'd2047 && - _theResult___fst_sfd__h734972 == 52'd0, + _theResult___fst_exp__h734968 == 11'd2047 && + _theResult___fst_sfd__h734969 == 52'd0, 1'd0, - _theResult___fst_exp__h734213 != 11'd2047 && - guard__h726252 != 2'b0 } ; + _theResult___fst_exp__h734210 != 11'd2047 && + guard__h726249 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14915 = { 3'd0, - _theResult___fst_exp__h773066 == 11'd0 && - guard__h765105 != 2'b0, + _theResult___fst_exp__h773063 == 11'd0 && + guard__h765102 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h773824 == 11'd2047 && - _theResult___fst_sfd__h773825 == 52'd0, + _theResult___fst_exp__h773821 == 11'd2047 && + _theResult___fst_sfd__h773822 == 52'd0, 1'd0, - _theResult___fst_exp__h773066 != 11'd2047 && - guard__h765105 != 2'b0 } ; + _theResult___fst_exp__h773063 != 11'd2047 && + guard__h765102 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14959 = { 3'd0, - _theResult___fst_exp__h812370 == 11'd0 && - guard__h804409 != 2'b0, + _theResult___fst_exp__h812367 == 11'd0 && + guard__h804406 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h813128 == 11'd2047 && - _theResult___fst_sfd__h813129 == 52'd0, + _theResult___fst_exp__h813125 == 11'd2047 && + _theResult___fst_sfd__h813126 == 52'd0, 1'd0, - _theResult___fst_exp__h812370 != 11'd2047 && - guard__h804409 != 2'b0 } ; + _theResult___fst_exp__h812367 != 11'd2047 && + guard__h804406 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ^ @@ -28628,15 +28628,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10688 = { 3'd0, - _theResult___fst_exp__h638897 == 8'd0 && - guard__h630849 != 2'b0, + _theResult___fst_exp__h638894 == 8'd0 && + guard__h630846 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h639420 == 8'd255 && - _theResult___fst_sfd__h639421 == 23'd0, + _theResult___fst_exp__h639417 == 8'd255 && + _theResult___fst_sfd__h639418 == 23'd0, 1'd0, - _theResult___fst_exp__h638897 != 8'd255 && - guard__h630849 != 2'b0 } ; + _theResult___fst_exp__h638894 != 8'd255 && + guard__h630846 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ^ @@ -28650,15 +28650,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12085 = { 3'd0, - _theResult___fst_exp__h684644 == 8'd0 && - guard__h676596 != 2'b0, + _theResult___fst_exp__h684641 == 8'd0 && + guard__h676593 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h685167 == 8'd255 && - _theResult___fst_sfd__h685168 == 23'd0, + _theResult___fst_exp__h685164 == 8'd255 && + _theResult___fst_sfd__h685165 == 23'd0, 1'd0, - _theResult___fst_exp__h684644 != 8'd255 && - guard__h676596 != 2'b0 } ; + _theResult___fst_exp__h684641 != 8'd255 && + guard__h676593 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ^ @@ -28672,15 +28672,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9291 = { 3'd0, - _theResult___fst_exp__h593148 == 8'd0 && - guard__h585100 != 2'b0, + _theResult___fst_exp__h593145 == 8'd0 && + guard__h585097 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h593671 == 8'd255 && - _theResult___fst_sfd__h593672 == 23'd0, + _theResult___fst_exp__h593668 == 8'd255 && + _theResult___fst_sfd__h593669 == 23'd0, 1'd0, - _theResult___fst_exp__h593148 != 8'd255 && - guard__h585100 != 2'b0 } ; + _theResult___fst_exp__h593145 != 8'd255 && + guard__h585097 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ^ @@ -28706,17 +28706,17 @@ module mkCore(CLK, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; assign _0_CONCAT_csrf_mtcc_reg_read__6627_BITS_149_TO__ETC___d22614 = - x__h997817[13:11] < repBound__h997781 ; + x__h997812[13:11] < repBound__h997776 ; assign _0_CONCAT_csrf_mtcc_reg_read__6627_BITS_149_TO__ETC___d22640 = - x__h998121[13:11] < repBound__h997781 ; + x__h998116[13:11] < repBound__h997776 ; assign _0_CONCAT_csrf_stcc_reg_read__6618_BITS_149_TO__ETC___d22539 = - x__h997160[13:11] < repBound__h997124 ; + x__h997155[13:11] < repBound__h997119 ; assign _0_CONCAT_csrf_stcc_reg_read__6618_BITS_149_TO__ETC___d22565 = - x__h997464[13:11] < repBound__h997124 ; + x__h997459[13:11] < repBound__h997119 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0049_BI_ETC___d21612 = (fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 ; + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0058_BI_ETC___d21510 = (fetchStage$pipelines_1_first[267:265] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -28730,37 +28730,37 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__0047_AND_N_ETC__q269 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786 = - sfd__h715187 >> + sfd__h715184 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501 = - sfd__h793485 >> + sfd__h793482 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271 = - sfd__h754181 >> + sfd__h754178 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060 = - sfd__h614530 >> + sfd__h614527 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457 = - sfd__h660277 >> + sfd__h660274 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663 = - sfd__h568776 >> + sfd__h568773 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659) ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__6063_6064_ETC___d22413 = - medeleg_csr__read__h849989[i__h992808] ; + medeleg_csr__read__h849986[i__h992803] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22415 = - mideleg_csr__read__h850087[i__h992982] ; + mideleg_csr__read__h850084[i__h992977] ; assign _18446744073709551615_SL_csrf_mtcc_reg_read__66_ETC___d22602 = - mask__h997629 ^ y__h997746 ; + mask__h997624 ^ y__h997741 ; assign _18446744073709551615_SL_csrf_stcc_reg_read__66_ETC___d22527 = - mask__h996972 ^ y__h997089 ; + mask__h996967 ^ y__h997084 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10691 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? @@ -29166,51 +29166,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12642 = 12'd3970 - { 7'd0, - f1_sfd__h714826[22] ? + f1_sfd__h714823[22] ? 5'd0 : - (f1_sfd__h714826[21] ? + (f1_sfd__h714823[21] ? 5'd1 : - (f1_sfd__h714826[20] ? + (f1_sfd__h714823[20] ? 5'd2 : - (f1_sfd__h714826[19] ? + (f1_sfd__h714823[19] ? 5'd3 : - (f1_sfd__h714826[18] ? + (f1_sfd__h714823[18] ? 5'd4 : - (f1_sfd__h714826[17] ? + (f1_sfd__h714823[17] ? 5'd5 : - (f1_sfd__h714826[16] ? + (f1_sfd__h714823[16] ? 5'd6 : - (f1_sfd__h714826[15] ? + (f1_sfd__h714823[15] ? 5'd7 : - (f1_sfd__h714826[14] ? + (f1_sfd__h714823[14] ? 5'd8 : - (f1_sfd__h714826[13] ? + (f1_sfd__h714823[13] ? 5'd9 : - (f1_sfd__h714826[12] ? + (f1_sfd__h714823[12] ? 5'd10 : - (f1_sfd__h714826[11] ? + (f1_sfd__h714823[11] ? 5'd11 : - (f1_sfd__h714826[10] ? + (f1_sfd__h714823[10] ? 5'd12 : - (f1_sfd__h714826[9] ? + (f1_sfd__h714823[9] ? 5'd13 : - (f1_sfd__h714826[8] ? + (f1_sfd__h714823[8] ? 5'd14 : - (f1_sfd__h714826[7] ? + (f1_sfd__h714823[7] ? 5'd15 : - (f1_sfd__h714826[6] ? + (f1_sfd__h714823[6] ? 5'd16 : - (f1_sfd__h714826[5] ? + (f1_sfd__h714823[5] ? 5'd17 : - (f1_sfd__h714826[4] ? + (f1_sfd__h714823[4] ? 5'd18 : - (f1_sfd__h714826[3] ? + (f1_sfd__h714823[3] ? 5'd19 : - (f1_sfd__h714826[2] ? + (f1_sfd__h714823[2] ? 5'd20 : - (f1_sfd__h714826[1] ? + (f1_sfd__h714823[1] ? 5'd21 : - (f1_sfd__h714826[0] ? + (f1_sfd__h714823[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 = @@ -29224,51 +29224,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13372 = 12'd3970 - { 7'd0, - f3_sfd__h793124[22] ? + f3_sfd__h793121[22] ? 5'd0 : - (f3_sfd__h793124[21] ? + (f3_sfd__h793121[21] ? 5'd1 : - (f3_sfd__h793124[20] ? + (f3_sfd__h793121[20] ? 5'd2 : - (f3_sfd__h793124[19] ? + (f3_sfd__h793121[19] ? 5'd3 : - (f3_sfd__h793124[18] ? + (f3_sfd__h793121[18] ? 5'd4 : - (f3_sfd__h793124[17] ? + (f3_sfd__h793121[17] ? 5'd5 : - (f3_sfd__h793124[16] ? + (f3_sfd__h793121[16] ? 5'd6 : - (f3_sfd__h793124[15] ? + (f3_sfd__h793121[15] ? 5'd7 : - (f3_sfd__h793124[14] ? + (f3_sfd__h793121[14] ? 5'd8 : - (f3_sfd__h793124[13] ? + (f3_sfd__h793121[13] ? 5'd9 : - (f3_sfd__h793124[12] ? + (f3_sfd__h793121[12] ? 5'd10 : - (f3_sfd__h793124[11] ? + (f3_sfd__h793121[11] ? 5'd11 : - (f3_sfd__h793124[10] ? + (f3_sfd__h793121[10] ? 5'd12 : - (f3_sfd__h793124[9] ? + (f3_sfd__h793121[9] ? 5'd13 : - (f3_sfd__h793124[8] ? + (f3_sfd__h793121[8] ? 5'd14 : - (f3_sfd__h793124[7] ? + (f3_sfd__h793121[7] ? 5'd15 : - (f3_sfd__h793124[6] ? + (f3_sfd__h793121[6] ? 5'd16 : - (f3_sfd__h793124[5] ? + (f3_sfd__h793121[5] ? 5'd17 : - (f3_sfd__h793124[4] ? + (f3_sfd__h793121[4] ? 5'd18 : - (f3_sfd__h793124[3] ? + (f3_sfd__h793121[3] ? 5'd19 : - (f3_sfd__h793124[2] ? + (f3_sfd__h793121[2] ? 5'd20 : - (f3_sfd__h793124[1] ? + (f3_sfd__h793121[1] ? 5'd21 : - (f3_sfd__h793124[0] ? + (f3_sfd__h793121[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 = @@ -29282,51 +29282,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14142 = 12'd3970 - { 7'd0, - f2_sfd__h753820[22] ? + f2_sfd__h753817[22] ? 5'd0 : - (f2_sfd__h753820[21] ? + (f2_sfd__h753817[21] ? 5'd1 : - (f2_sfd__h753820[20] ? + (f2_sfd__h753817[20] ? 5'd2 : - (f2_sfd__h753820[19] ? + (f2_sfd__h753817[19] ? 5'd3 : - (f2_sfd__h753820[18] ? + (f2_sfd__h753817[18] ? 5'd4 : - (f2_sfd__h753820[17] ? + (f2_sfd__h753817[17] ? 5'd5 : - (f2_sfd__h753820[16] ? + (f2_sfd__h753817[16] ? 5'd6 : - (f2_sfd__h753820[15] ? + (f2_sfd__h753817[15] ? 5'd7 : - (f2_sfd__h753820[14] ? + (f2_sfd__h753817[14] ? 5'd8 : - (f2_sfd__h753820[13] ? + (f2_sfd__h753817[13] ? 5'd9 : - (f2_sfd__h753820[12] ? + (f2_sfd__h753817[12] ? 5'd10 : - (f2_sfd__h753820[11] ? + (f2_sfd__h753817[11] ? 5'd11 : - (f2_sfd__h753820[10] ? + (f2_sfd__h753817[10] ? 5'd12 : - (f2_sfd__h753820[9] ? + (f2_sfd__h753817[9] ? 5'd13 : - (f2_sfd__h753820[8] ? + (f2_sfd__h753817[8] ? 5'd14 : - (f2_sfd__h753820[7] ? + (f2_sfd__h753817[7] ? 5'd15 : - (f2_sfd__h753820[6] ? + (f2_sfd__h753817[6] ? 5'd16 : - (f2_sfd__h753820[5] ? + (f2_sfd__h753817[5] ? 5'd17 : - (f2_sfd__h753820[4] ? + (f2_sfd__h753817[4] ? 5'd18 : - (f2_sfd__h753820[3] ? + (f2_sfd__h753817[3] ? 5'd19 : - (f2_sfd__h753820[2] ? + (f2_sfd__h753817[2] ? 5'd20 : - (f2_sfd__h753820[1] ? + (f2_sfd__h753817[1] ? 5'd21 : - (f2_sfd__h753820[0] ? + (f2_sfd__h753817[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 = @@ -29367,7 +29367,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[237:236] != 2'd1 && fetchStage_pipelines_1_first__0058_BITS_267_TO_ETC___d21945 ; assign _dfoo16 = - k__h942684 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h942679 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786 || (fetchStage_pipelines_0_canDeq__0047_AND_NOT_fe_ETC___d21871 || NOT_fetchStage_pipelines_0_canDeq__0047_0048_O_ETC___d21884) == @@ -29375,7 +29375,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0047_0048_O_ETC___d21889 && NOT_fetchStage_pipelines_1_first__0058_BITS_26_ETC___d21901 ; assign _dfoo18 = - k__h942684 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h942679 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21786 || (fetchStage_pipelines_0_canDeq__0047_AND_NOT_fe_ETC___d21871 || NOT_fetchStage_pipelines_0_canDeq__0047_0048_O_ETC___d21884) == @@ -29482,1415 +29482,1415 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h515296 = + assign _theResult_____2__h515292 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7222 ? - next_deqP___1__h515541 : + next_deqP___1__h515537 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h526073 = + assign _theResult_____2__h526069 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7316 ? - next_deqP___1__h526318 : + next_deqP___1__h526314 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h533166 = + assign _theResult_____2__h533162 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7475 ? - next_deqP___1__h533596 : + next_deqP___1__h533592 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h543801 = + assign _theResult_____2__h543797 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7559 ? - next_deqP___1__h544231 : + next_deqP___1__h544227 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h557634 = + assign _theResult_____2__h557630 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7764 ? - next_deqP___1__h557879 : + next_deqP___1__h557875 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h561413 = + assign _theResult_____2__h561409 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7846 ? - next_deqP___1__h561658 : + next_deqP___1__h561654 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h576381 = - (value__h577003 == 54'd0) ? sfd__h568776 : 57'd1 ; - assign _theResult____h594020 = + assign _theResult____h576378 = + (value__h577000 == 54'd0) ? sfd__h568773 : 57'd1 ; + assign _theResult____h594017 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659 ^ 12'h800) < 12'd2105) ? - result__h594633 : - _theResult____h576381 ; - assign _theResult____h622132 = - (value__h622752 == 54'd0) ? sfd__h614530 : 57'd1 ; - assign _theResult____h639769 = + result__h594630 : + _theResult____h576378 ; + assign _theResult____h622129 = + (value__h622749 == 54'd0) ? sfd__h614527 : 57'd1 ; + assign _theResult____h639766 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056 ^ 12'h800) < 12'd2105) ? - result__h640382 : - _theResult____h622132 ; - assign _theResult____h667879 = - (value__h668499 == 54'd0) ? sfd__h660277 : 57'd1 ; - assign _theResult____h685516 = + result__h640379 : + _theResult____h622129 ; + assign _theResult____h667876 = + (value__h668496 == 54'd0) ? sfd__h660274 : 57'd1 ; + assign _theResult____h685513 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453 ^ 12'h800) < 12'd2105) ? - result__h686129 : - _theResult____h667879 ; - assign _theResult____h735554 = + result__h686126 : + _theResult____h667876 ; + assign _theResult____h735551 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ^ 12'h800) < 12'd2105) ? - result__h736167 : - ((value__h719770 == 25'd0) ? sfd__h715187 : 57'd1) ; - assign _theResult____h774407 = + result__h736164 : + ((value__h719767 == 25'd0) ? sfd__h715184 : 57'd1) ; + assign _theResult____h774404 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ^ 12'h800) < 12'd2105) ? - result__h775020 : - ((value__h758623 == 25'd0) ? sfd__h754181 : 57'd1) ; - assign _theResult____h813711 = + result__h775017 : + ((value__h758620 == 25'd0) ? sfd__h754178 : 57'd1) ; + assign _theResult____h813708 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ^ 12'h800) < 12'd2105) ? - result__h814324 : - ((value__h797927 == 25'd0) ? sfd__h793485 : 57'd1) ; - assign _theResult____h917995 = + result__h814321 : + ((value__h797924 == 25'd0) ? sfd__h793482 : 57'd1) ; + assign _theResult____h917990 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h918520 : + enabled_ints___1__h918515 : 16'd0 ; - assign _theResult___exp__h585008 = - sfd__h584584[24] ? - ((_theResult___fst_exp__h584492 == 8'd254) ? + assign _theResult___exp__h585005 = + sfd__h584581[24] ? + ((_theResult___fst_exp__h584489 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611525) : - ((_theResult___fst_exp__h584492 == 8'd0 && - sfd__h584584[24:23] == 2'b01) ? + din_inc___2_exp__h611522) : + ((_theResult___fst_exp__h584489 == 8'd0 && + sfd__h584581[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h584492) ; - assign _theResult___exp__h593590 = - sfd__h593166[24] ? - ((_theResult___fst_exp__h593148 == 8'd254) ? + _theResult___fst_exp__h584489) ; + assign _theResult___exp__h593587 = + sfd__h593163[24] ? + ((_theResult___fst_exp__h593145 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611549) : - ((_theResult___fst_exp__h593148 == 8'd0 && - sfd__h593166[24:23] == 2'b01) ? + din_inc___2_exp__h611546) : + ((_theResult___fst_exp__h593145 == 8'd0 && + sfd__h593163[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h593148) ; - assign _theResult___exp__h602774 = - sfd__h602350[24] ? - ((_theResult___fst_exp__h602258 == 8'd254) ? + _theResult___fst_exp__h593145) ; + assign _theResult___exp__h602771 = + sfd__h602347[24] ? + ((_theResult___fst_exp__h602255 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611579) : - ((_theResult___fst_exp__h602258 == 8'd0 && - sfd__h602350[24:23] == 2'b01) ? + din_inc___2_exp__h611576) : + ((_theResult___fst_exp__h602255 == 8'd0 && + sfd__h602347[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h602258) ; - assign _theResult___exp__h611410 = - sfd__h610962[24] ? - ((_theResult___fst_exp__h610943 == 8'd254) ? + _theResult___fst_exp__h602255) ; + assign _theResult___exp__h611407 = + sfd__h610959[24] ? + ((_theResult___fst_exp__h610940 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611603) : - ((_theResult___fst_exp__h610943 == 8'd0 && - sfd__h610962[24:23] == 2'b01) ? + din_inc___2_exp__h611600) : + ((_theResult___fst_exp__h610940 == 8'd0 && + sfd__h610959[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h610943) ; - assign _theResult___exp__h611512 = + _theResult___fst_exp__h610940) ; + assign _theResult___exp__h611509 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611503 ; - assign _theResult___exp__h630757 = - sfd__h630333[24] ? - ((_theResult___fst_exp__h630241 == 8'd254) ? + _theResult___fst_exp__h611500 ; + assign _theResult___exp__h630754 = + sfd__h630330[24] ? + ((_theResult___fst_exp__h630238 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657274) : - ((_theResult___fst_exp__h630241 == 8'd0 && - sfd__h630333[24:23] == 2'b01) ? + din_inc___2_exp__h657271) : + ((_theResult___fst_exp__h630238 == 8'd0 && + sfd__h630330[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h630241) ; - assign _theResult___exp__h639339 = - sfd__h638915[24] ? - ((_theResult___fst_exp__h638897 == 8'd254) ? + _theResult___fst_exp__h630238) ; + assign _theResult___exp__h639336 = + sfd__h638912[24] ? + ((_theResult___fst_exp__h638894 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657298) : - ((_theResult___fst_exp__h638897 == 8'd0 && - sfd__h638915[24:23] == 2'b01) ? + din_inc___2_exp__h657295) : + ((_theResult___fst_exp__h638894 == 8'd0 && + sfd__h638912[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h638897) ; - assign _theResult___exp__h648523 = - sfd__h648099[24] ? - ((_theResult___fst_exp__h648007 == 8'd254) ? + _theResult___fst_exp__h638894) ; + assign _theResult___exp__h648520 = + sfd__h648096[24] ? + ((_theResult___fst_exp__h648004 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657328) : - ((_theResult___fst_exp__h648007 == 8'd0 && - sfd__h648099[24:23] == 2'b01) ? + din_inc___2_exp__h657325) : + ((_theResult___fst_exp__h648004 == 8'd0 && + sfd__h648096[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h648007) ; - assign _theResult___exp__h657159 = - sfd__h656711[24] ? - ((_theResult___fst_exp__h656692 == 8'd254) ? + _theResult___fst_exp__h648004) ; + assign _theResult___exp__h657156 = + sfd__h656708[24] ? + ((_theResult___fst_exp__h656689 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657352) : - ((_theResult___fst_exp__h656692 == 8'd0 && - sfd__h656711[24:23] == 2'b01) ? + din_inc___2_exp__h657349) : + ((_theResult___fst_exp__h656689 == 8'd0 && + sfd__h656708[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h656692) ; - assign _theResult___exp__h657261 = + _theResult___fst_exp__h656689) ; + assign _theResult___exp__h657258 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657252 ; - assign _theResult___exp__h676504 = - sfd__h676080[24] ? - ((_theResult___fst_exp__h675988 == 8'd254) ? + _theResult___fst_exp__h657249 ; + assign _theResult___exp__h676501 = + sfd__h676077[24] ? + ((_theResult___fst_exp__h675985 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703021) : - ((_theResult___fst_exp__h675988 == 8'd0 && - sfd__h676080[24:23] == 2'b01) ? + din_inc___2_exp__h703018) : + ((_theResult___fst_exp__h675985 == 8'd0 && + sfd__h676077[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h675988) ; - assign _theResult___exp__h685086 = - sfd__h684662[24] ? - ((_theResult___fst_exp__h684644 == 8'd254) ? + _theResult___fst_exp__h675985) ; + assign _theResult___exp__h685083 = + sfd__h684659[24] ? + ((_theResult___fst_exp__h684641 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703045) : - ((_theResult___fst_exp__h684644 == 8'd0 && - sfd__h684662[24:23] == 2'b01) ? + din_inc___2_exp__h703042) : + ((_theResult___fst_exp__h684641 == 8'd0 && + sfd__h684659[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h684644) ; - assign _theResult___exp__h694270 = - sfd__h693846[24] ? - ((_theResult___fst_exp__h693754 == 8'd254) ? + _theResult___fst_exp__h684641) ; + assign _theResult___exp__h694267 = + sfd__h693843[24] ? + ((_theResult___fst_exp__h693751 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703075) : - ((_theResult___fst_exp__h693754 == 8'd0 && - sfd__h693846[24:23] == 2'b01) ? + din_inc___2_exp__h703072) : + ((_theResult___fst_exp__h693751 == 8'd0 && + sfd__h693843[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h693754) ; - assign _theResult___exp__h702906 = - sfd__h702458[24] ? - ((_theResult___fst_exp__h702439 == 8'd254) ? + _theResult___fst_exp__h693751) ; + assign _theResult___exp__h702903 = + sfd__h702455[24] ? + ((_theResult___fst_exp__h702436 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703099) : - ((_theResult___fst_exp__h702439 == 8'd0 && - sfd__h702458[24:23] == 2'b01) ? + din_inc___2_exp__h703096) : + ((_theResult___fst_exp__h702436 == 8'd0 && + sfd__h702455[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h702439) ; - assign _theResult___exp__h703008 = + _theResult___fst_exp__h702436) ; + assign _theResult___exp__h703005 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h702999 ; - assign _theResult___exp__h734868 = - sfd__h734231[53] ? - ((_theResult___fst_exp__h734213 == 11'd2046) ? + _theResult___fst_exp__h702996 ; + assign _theResult___exp__h734865 = + sfd__h734228[53] ? + ((_theResult___fst_exp__h734210 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753463) : - ((_theResult___fst_exp__h734213 == 11'd0 && - sfd__h734231[53:52] == 2'b01) ? + din_inc___2_exp__h753460) : + ((_theResult___fst_exp__h734210 == 11'd0 && + sfd__h734228[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h734213) ; - assign _theResult___exp__h744519 = - sfd__h743882[53] ? - ((_theResult___fst_exp__h743790 == 11'd2046) ? + _theResult___fst_exp__h734210) ; + assign _theResult___exp__h744516 = + sfd__h743879[53] ? + ((_theResult___fst_exp__h743787 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753498) : - ((_theResult___fst_exp__h743790 == 11'd0 && - sfd__h743882[53:52] == 2'b01) ? + din_inc___2_exp__h753495) : + ((_theResult___fst_exp__h743787 == 11'd0 && + sfd__h743879[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h743790) ; - assign _theResult___exp__h753303 = - sfd__h752642[53] ? - ((_theResult___fst_exp__h752623 == 11'd2046) ? + _theResult___fst_exp__h743787) ; + assign _theResult___exp__h753300 = + sfd__h752639[53] ? + ((_theResult___fst_exp__h752620 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753524) : - ((_theResult___fst_exp__h752623 == 11'd0 && - sfd__h752642[53:52] == 2'b01) ? + din_inc___2_exp__h753521) : + ((_theResult___fst_exp__h752620 == 11'd0 && + sfd__h752639[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h752623) ; - assign _theResult___exp__h773721 = - sfd__h773084[53] ? - ((_theResult___fst_exp__h773066 == 11'd2046) ? + _theResult___fst_exp__h752620) ; + assign _theResult___exp__h773718 = + sfd__h773081[53] ? + ((_theResult___fst_exp__h773063 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792316) : - ((_theResult___fst_exp__h773066 == 11'd0 && - sfd__h773084[53:52] == 2'b01) ? + din_inc___2_exp__h792313) : + ((_theResult___fst_exp__h773063 == 11'd0 && + sfd__h773081[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h773066) ; - assign _theResult___exp__h783372 = - sfd__h782735[53] ? - ((_theResult___fst_exp__h782643 == 11'd2046) ? + _theResult___fst_exp__h773063) ; + assign _theResult___exp__h783369 = + sfd__h782732[53] ? + ((_theResult___fst_exp__h782640 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792351) : - ((_theResult___fst_exp__h782643 == 11'd0 && - sfd__h782735[53:52] == 2'b01) ? + din_inc___2_exp__h792348) : + ((_theResult___fst_exp__h782640 == 11'd0 && + sfd__h782732[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h782643) ; - assign _theResult___exp__h792156 = - sfd__h791495[53] ? - ((_theResult___fst_exp__h791476 == 11'd2046) ? + _theResult___fst_exp__h782640) ; + assign _theResult___exp__h792153 = + sfd__h791492[53] ? + ((_theResult___fst_exp__h791473 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792377) : - ((_theResult___fst_exp__h791476 == 11'd0 && - sfd__h791495[53:52] == 2'b01) ? + din_inc___2_exp__h792374) : + ((_theResult___fst_exp__h791473 == 11'd0 && + sfd__h791492[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h791476) ; - assign _theResult___exp__h813025 = - sfd__h812388[53] ? - ((_theResult___fst_exp__h812370 == 11'd2046) ? + _theResult___fst_exp__h791473) ; + assign _theResult___exp__h813022 = + sfd__h812385[53] ? + ((_theResult___fst_exp__h812367 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831620) : - ((_theResult___fst_exp__h812370 == 11'd0 && - sfd__h812388[53:52] == 2'b01) ? + din_inc___2_exp__h831617) : + ((_theResult___fst_exp__h812367 == 11'd0 && + sfd__h812385[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h812370) ; - assign _theResult___exp__h822676 = - sfd__h822039[53] ? - ((_theResult___fst_exp__h821947 == 11'd2046) ? + _theResult___fst_exp__h812367) ; + assign _theResult___exp__h822673 = + sfd__h822036[53] ? + ((_theResult___fst_exp__h821944 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831655) : - ((_theResult___fst_exp__h821947 == 11'd0 && - sfd__h822039[53:52] == 2'b01) ? + din_inc___2_exp__h831652) : + ((_theResult___fst_exp__h821944 == 11'd0 && + sfd__h822036[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h821947) ; - assign _theResult___exp__h831460 = - sfd__h830799[53] ? - ((_theResult___fst_exp__h830780 == 11'd2046) ? + _theResult___fst_exp__h821944) ; + assign _theResult___exp__h831457 = + sfd__h830796[53] ? + ((_theResult___fst_exp__h830777 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831681) : - ((_theResult___fst_exp__h830780 == 11'd0 && - sfd__h830799[53:52] == 2'b01) ? + din_inc___2_exp__h831678) : + ((_theResult___fst_exp__h830777 == 11'd0 && + sfd__h830796[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h830780) ; - assign _theResult___fst__h836055 = - a__h835633[63] ? a___1__h836060 : a__h835633 ; - assign _theResult___fst_exp__h584492 = - _theResult____h576381[56] ? + _theResult___fst_exp__h830777) ; + assign _theResult___fst__h836052 = + a__h835630[63] ? a___1__h836057 : a__h835630 ; + assign _theResult___fst_exp__h584489 = + _theResult____h576378[56] ? 8'd2 : - _theResult___fst_exp__h584566 ; - assign _theResult___fst_exp__h584557 = + _theResult___fst_exp__h584563 ; + assign _theResult___fst_exp__h584554 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 } ; - assign _theResult___fst_exp__h584563 = - (!_theResult____h576381[56] && !_theResult____h576381[55] && - !_theResult____h576381[54] && - !_theResult____h576381[53] && - !_theResult____h576381[52] && - !_theResult____h576381[51] && - !_theResult____h576381[50] && - !_theResult____h576381[49] && - !_theResult____h576381[48] && - !_theResult____h576381[47] && - !_theResult____h576381[46] && - !_theResult____h576381[45] && - !_theResult____h576381[44] && - !_theResult____h576381[43] && - !_theResult____h576381[42] && - !_theResult____h576381[41] && - !_theResult____h576381[40] && - !_theResult____h576381[39] && - !_theResult____h576381[38] && - !_theResult____h576381[37] && - !_theResult____h576381[36] && - !_theResult____h576381[35] && - !_theResult____h576381[34] && - !_theResult____h576381[33] && - !_theResult____h576381[32] && - !_theResult____h576381[31] && - !_theResult____h576381[30] && - !_theResult____h576381[29] && - !_theResult____h576381[28] && - !_theResult____h576381[27] && - !_theResult____h576381[26] && - !_theResult____h576381[25] && - !_theResult____h576381[24] && - !_theResult____h576381[23] && - !_theResult____h576381[22] && - !_theResult____h576381[21] && - !_theResult____h576381[20] && - !_theResult____h576381[19] && - !_theResult____h576381[18] && - !_theResult____h576381[17] && - !_theResult____h576381[16] && - !_theResult____h576381[15] && - !_theResult____h576381[14] && - !_theResult____h576381[13] && - !_theResult____h576381[12] && - !_theResult____h576381[11] && - !_theResult____h576381[10] && - !_theResult____h576381[9] && - !_theResult____h576381[8] && - !_theResult____h576381[7] && - !_theResult____h576381[6] && - !_theResult____h576381[5] && - !_theResult____h576381[4] && - !_theResult____h576381[3] && - !_theResult____h576381[2] && - !_theResult____h576381[1] && - !_theResult____h576381[0] || + assign _theResult___fst_exp__h584560 = + (!_theResult____h576378[56] && !_theResult____h576378[55] && + !_theResult____h576378[54] && + !_theResult____h576378[53] && + !_theResult____h576378[52] && + !_theResult____h576378[51] && + !_theResult____h576378[50] && + !_theResult____h576378[49] && + !_theResult____h576378[48] && + !_theResult____h576378[47] && + !_theResult____h576378[46] && + !_theResult____h576378[45] && + !_theResult____h576378[44] && + !_theResult____h576378[43] && + !_theResult____h576378[42] && + !_theResult____h576378[41] && + !_theResult____h576378[40] && + !_theResult____h576378[39] && + !_theResult____h576378[38] && + !_theResult____h576378[37] && + !_theResult____h576378[36] && + !_theResult____h576378[35] && + !_theResult____h576378[34] && + !_theResult____h576378[33] && + !_theResult____h576378[32] && + !_theResult____h576378[31] && + !_theResult____h576378[30] && + !_theResult____h576378[29] && + !_theResult____h576378[28] && + !_theResult____h576378[27] && + !_theResult____h576378[26] && + !_theResult____h576378[25] && + !_theResult____h576378[24] && + !_theResult____h576378[23] && + !_theResult____h576378[22] && + !_theResult____h576378[21] && + !_theResult____h576378[20] && + !_theResult____h576378[19] && + !_theResult____h576378[18] && + !_theResult____h576378[17] && + !_theResult____h576378[16] && + !_theResult____h576378[15] && + !_theResult____h576378[14] && + !_theResult____h576378[13] && + !_theResult____h576378[12] && + !_theResult____h576378[11] && + !_theResult____h576378[10] && + !_theResult____h576378[9] && + !_theResult____h576378[8] && + !_theResult____h576378[7] && + !_theResult____h576378[6] && + !_theResult____h576378[5] && + !_theResult____h576378[4] && + !_theResult____h576378[3] && + !_theResult____h576378[2] && + !_theResult____h576378[1] && + !_theResult____h576378[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8354) ? 8'd0 : - _theResult___fst_exp__h584557 ; - assign _theResult___fst_exp__h584566 = - (!_theResult____h576381[56] && _theResult____h576381[55]) ? + _theResult___fst_exp__h584554 ; + assign _theResult___fst_exp__h584563 = + (!_theResult____h576378[56] && _theResult____h576378[55]) ? 8'd1 : - _theResult___fst_exp__h584563 ; - assign _theResult___fst_exp__h585089 = - (_theResult___fst_exp__h584492 == 8'd255) ? - _theResult___fst_exp__h584492 : - _theResult___fst_exp__h585086 ; - assign _theResult___fst_exp__h593139 = + _theResult___fst_exp__h584560 ; + assign _theResult___fst_exp__h585086 = + (_theResult___fst_exp__h584489 == 8'd255) ? + _theResult___fst_exp__h584489 : + _theResult___fst_exp__h585083 ; + assign _theResult___fst_exp__h593136 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ; - assign _theResult___fst_exp__h593145 = + assign _theResult___fst_exp__h593142 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8585) ? 8'd0 : - _theResult___fst_exp__h593139 ; - assign _theResult___fst_exp__h593148 = + _theResult___fst_exp__h593136 ; + assign _theResult___fst_exp__h593145 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h593145 : + _theResult___fst_exp__h593142 : 8'd129 ; - assign _theResult___fst_exp__h593671 = - (_theResult___fst_exp__h593148 == 8'd255) ? - _theResult___fst_exp__h593148 : - _theResult___fst_exp__h593668 ; - assign _theResult___fst_exp__h602258 = - _theResult____h594020[56] ? + assign _theResult___fst_exp__h593668 = + (_theResult___fst_exp__h593145 == 8'd255) ? + _theResult___fst_exp__h593145 : + _theResult___fst_exp__h593665 ; + assign _theResult___fst_exp__h602255 = + _theResult____h594017[56] ? 8'd2 : - _theResult___fst_exp__h602332 ; - assign _theResult___fst_exp__h602323 = + _theResult___fst_exp__h602329 ; + assign _theResult___fst_exp__h602320 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 } ; - assign _theResult___fst_exp__h602329 = - (!_theResult____h594020[56] && !_theResult____h594020[55] && - !_theResult____h594020[54] && - !_theResult____h594020[53] && - !_theResult____h594020[52] && - !_theResult____h594020[51] && - !_theResult____h594020[50] && - !_theResult____h594020[49] && - !_theResult____h594020[48] && - !_theResult____h594020[47] && - !_theResult____h594020[46] && - !_theResult____h594020[45] && - !_theResult____h594020[44] && - !_theResult____h594020[43] && - !_theResult____h594020[42] && - !_theResult____h594020[41] && - !_theResult____h594020[40] && - !_theResult____h594020[39] && - !_theResult____h594020[38] && - !_theResult____h594020[37] && - !_theResult____h594020[36] && - !_theResult____h594020[35] && - !_theResult____h594020[34] && - !_theResult____h594020[33] && - !_theResult____h594020[32] && - !_theResult____h594020[31] && - !_theResult____h594020[30] && - !_theResult____h594020[29] && - !_theResult____h594020[28] && - !_theResult____h594020[27] && - !_theResult____h594020[26] && - !_theResult____h594020[25] && - !_theResult____h594020[24] && - !_theResult____h594020[23] && - !_theResult____h594020[22] && - !_theResult____h594020[21] && - !_theResult____h594020[20] && - !_theResult____h594020[19] && - !_theResult____h594020[18] && - !_theResult____h594020[17] && - !_theResult____h594020[16] && - !_theResult____h594020[15] && - !_theResult____h594020[14] && - !_theResult____h594020[13] && - !_theResult____h594020[12] && - !_theResult____h594020[11] && - !_theResult____h594020[10] && - !_theResult____h594020[9] && - !_theResult____h594020[8] && - !_theResult____h594020[7] && - !_theResult____h594020[6] && - !_theResult____h594020[5] && - !_theResult____h594020[4] && - !_theResult____h594020[3] && - !_theResult____h594020[2] && - !_theResult____h594020[1] && - !_theResult____h594020[0] || + assign _theResult___fst_exp__h602326 = + (!_theResult____h594017[56] && !_theResult____h594017[55] && + !_theResult____h594017[54] && + !_theResult____h594017[53] && + !_theResult____h594017[52] && + !_theResult____h594017[51] && + !_theResult____h594017[50] && + !_theResult____h594017[49] && + !_theResult____h594017[48] && + !_theResult____h594017[47] && + !_theResult____h594017[46] && + !_theResult____h594017[45] && + !_theResult____h594017[44] && + !_theResult____h594017[43] && + !_theResult____h594017[42] && + !_theResult____h594017[41] && + !_theResult____h594017[40] && + !_theResult____h594017[39] && + !_theResult____h594017[38] && + !_theResult____h594017[37] && + !_theResult____h594017[36] && + !_theResult____h594017[35] && + !_theResult____h594017[34] && + !_theResult____h594017[33] && + !_theResult____h594017[32] && + !_theResult____h594017[31] && + !_theResult____h594017[30] && + !_theResult____h594017[29] && + !_theResult____h594017[28] && + !_theResult____h594017[27] && + !_theResult____h594017[26] && + !_theResult____h594017[25] && + !_theResult____h594017[24] && + !_theResult____h594017[23] && + !_theResult____h594017[22] && + !_theResult____h594017[21] && + !_theResult____h594017[20] && + !_theResult____h594017[19] && + !_theResult____h594017[18] && + !_theResult____h594017[17] && + !_theResult____h594017[16] && + !_theResult____h594017[15] && + !_theResult____h594017[14] && + !_theResult____h594017[13] && + !_theResult____h594017[12] && + !_theResult____h594017[11] && + !_theResult____h594017[10] && + !_theResult____h594017[9] && + !_theResult____h594017[8] && + !_theResult____h594017[7] && + !_theResult____h594017[6] && + !_theResult____h594017[5] && + !_theResult____h594017[4] && + !_theResult____h594017[3] && + !_theResult____h594017[2] && + !_theResult____h594017[1] && + !_theResult____h594017[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8905) ? 8'd0 : - _theResult___fst_exp__h602323 ; - assign _theResult___fst_exp__h602332 = - (!_theResult____h594020[56] && _theResult____h594020[55]) ? + _theResult___fst_exp__h602320 ; + assign _theResult___fst_exp__h602329 = + (!_theResult____h594017[56] && _theResult____h594017[55]) ? 8'd1 : - _theResult___fst_exp__h602329 ; - assign _theResult___fst_exp__h602855 = - (_theResult___fst_exp__h602258 == 8'd255) ? - _theResult___fst_exp__h602258 : - _theResult___fst_exp__h602852 ; - assign _theResult___fst_exp__h610895 = + _theResult___fst_exp__h602326 ; + assign _theResult___fst_exp__h602852 = + (_theResult___fst_exp__h602255 == 8'd255) ? + _theResult___fst_exp__h602255 : + _theResult___fst_exp__h602849 ; + assign _theResult___fst_exp__h610892 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] ; - assign _theResult___fst_exp__h610934 = + assign _theResult___fst_exp__h610931 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q48[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 } ; - assign _theResult___fst_exp__h610940 = + assign _theResult___fst_exp__h610937 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8978) ? 8'd0 : - _theResult___fst_exp__h610934 ; - assign _theResult___fst_exp__h610943 = + _theResult___fst_exp__h610931 ; + assign _theResult___fst_exp__h610940 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h610937 : + _theResult___fst_exp__h610892 ; + assign _theResult___fst_exp__h611488 = + (_theResult___fst_exp__h610940 == 8'd255) ? _theResult___fst_exp__h610940 : - _theResult___fst_exp__h610895 ; - assign _theResult___fst_exp__h611491 = - (_theResult___fst_exp__h610943 == 8'd255) ? - _theResult___fst_exp__h610943 : - _theResult___fst_exp__h611488 ; - assign _theResult___fst_exp__h611500 = + _theResult___fst_exp__h611485 ; + assign _theResult___fst_exp__h611497 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? - _theResult___snd_fst_exp__h593674 : - _theResult___fst_exp__h576363) : + _theResult___snd_fst_exp__h593671 : + _theResult___fst_exp__h576360) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? - _theResult___snd_fst_exp__h611494 : - _theResult___fst_exp__h576363) ; - assign _theResult___fst_exp__h611503 = + _theResult___snd_fst_exp__h611491 : + _theResult___fst_exp__h576360) ; + assign _theResult___fst_exp__h611500 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h611500 ; - assign _theResult___fst_exp__h630241 = - _theResult____h622132[56] ? + _theResult___fst_exp__h611497 ; + assign _theResult___fst_exp__h630238 = + _theResult____h622129[56] ? 8'd2 : - _theResult___fst_exp__h630315 ; - assign _theResult___fst_exp__h630306 = + _theResult___fst_exp__h630312 ; + assign _theResult___fst_exp__h630303 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 } ; - assign _theResult___fst_exp__h630312 = - (!_theResult____h622132[56] && !_theResult____h622132[55] && - !_theResult____h622132[54] && - !_theResult____h622132[53] && - !_theResult____h622132[52] && - !_theResult____h622132[51] && - !_theResult____h622132[50] && - !_theResult____h622132[49] && - !_theResult____h622132[48] && - !_theResult____h622132[47] && - !_theResult____h622132[46] && - !_theResult____h622132[45] && - !_theResult____h622132[44] && - !_theResult____h622132[43] && - !_theResult____h622132[42] && - !_theResult____h622132[41] && - !_theResult____h622132[40] && - !_theResult____h622132[39] && - !_theResult____h622132[38] && - !_theResult____h622132[37] && - !_theResult____h622132[36] && - !_theResult____h622132[35] && - !_theResult____h622132[34] && - !_theResult____h622132[33] && - !_theResult____h622132[32] && - !_theResult____h622132[31] && - !_theResult____h622132[30] && - !_theResult____h622132[29] && - !_theResult____h622132[28] && - !_theResult____h622132[27] && - !_theResult____h622132[26] && - !_theResult____h622132[25] && - !_theResult____h622132[24] && - !_theResult____h622132[23] && - !_theResult____h622132[22] && - !_theResult____h622132[21] && - !_theResult____h622132[20] && - !_theResult____h622132[19] && - !_theResult____h622132[18] && - !_theResult____h622132[17] && - !_theResult____h622132[16] && - !_theResult____h622132[15] && - !_theResult____h622132[14] && - !_theResult____h622132[13] && - !_theResult____h622132[12] && - !_theResult____h622132[11] && - !_theResult____h622132[10] && - !_theResult____h622132[9] && - !_theResult____h622132[8] && - !_theResult____h622132[7] && - !_theResult____h622132[6] && - !_theResult____h622132[5] && - !_theResult____h622132[4] && - !_theResult____h622132[3] && - !_theResult____h622132[2] && - !_theResult____h622132[1] && - !_theResult____h622132[0] || + assign _theResult___fst_exp__h630309 = + (!_theResult____h622129[56] && !_theResult____h622129[55] && + !_theResult____h622129[54] && + !_theResult____h622129[53] && + !_theResult____h622129[52] && + !_theResult____h622129[51] && + !_theResult____h622129[50] && + !_theResult____h622129[49] && + !_theResult____h622129[48] && + !_theResult____h622129[47] && + !_theResult____h622129[46] && + !_theResult____h622129[45] && + !_theResult____h622129[44] && + !_theResult____h622129[43] && + !_theResult____h622129[42] && + !_theResult____h622129[41] && + !_theResult____h622129[40] && + !_theResult____h622129[39] && + !_theResult____h622129[38] && + !_theResult____h622129[37] && + !_theResult____h622129[36] && + !_theResult____h622129[35] && + !_theResult____h622129[34] && + !_theResult____h622129[33] && + !_theResult____h622129[32] && + !_theResult____h622129[31] && + !_theResult____h622129[30] && + !_theResult____h622129[29] && + !_theResult____h622129[28] && + !_theResult____h622129[27] && + !_theResult____h622129[26] && + !_theResult____h622129[25] && + !_theResult____h622129[24] && + !_theResult____h622129[23] && + !_theResult____h622129[22] && + !_theResult____h622129[21] && + !_theResult____h622129[20] && + !_theResult____h622129[19] && + !_theResult____h622129[18] && + !_theResult____h622129[17] && + !_theResult____h622129[16] && + !_theResult____h622129[15] && + !_theResult____h622129[14] && + !_theResult____h622129[13] && + !_theResult____h622129[12] && + !_theResult____h622129[11] && + !_theResult____h622129[10] && + !_theResult____h622129[9] && + !_theResult____h622129[8] && + !_theResult____h622129[7] && + !_theResult____h622129[6] && + !_theResult____h622129[5] && + !_theResult____h622129[4] && + !_theResult____h622129[3] && + !_theResult____h622129[2] && + !_theResult____h622129[1] && + !_theResult____h622129[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9751) ? 8'd0 : - _theResult___fst_exp__h630306 ; - assign _theResult___fst_exp__h630315 = - (!_theResult____h622132[56] && _theResult____h622132[55]) ? + _theResult___fst_exp__h630303 ; + assign _theResult___fst_exp__h630312 = + (!_theResult____h622129[56] && _theResult____h622129[55]) ? 8'd1 : - _theResult___fst_exp__h630312 ; - assign _theResult___fst_exp__h630838 = - (_theResult___fst_exp__h630241 == 8'd255) ? - _theResult___fst_exp__h630241 : - _theResult___fst_exp__h630835 ; - assign _theResult___fst_exp__h638888 = + _theResult___fst_exp__h630309 ; + assign _theResult___fst_exp__h630835 = + (_theResult___fst_exp__h630238 == 8'd255) ? + _theResult___fst_exp__h630238 : + _theResult___fst_exp__h630832 ; + assign _theResult___fst_exp__h638885 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ; - assign _theResult___fst_exp__h638894 = + assign _theResult___fst_exp__h638891 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9982) ? 8'd0 : - _theResult___fst_exp__h638888 ; - assign _theResult___fst_exp__h638897 = + _theResult___fst_exp__h638885 ; + assign _theResult___fst_exp__h638894 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h638894 : + _theResult___fst_exp__h638891 : 8'd129 ; - assign _theResult___fst_exp__h639420 = - (_theResult___fst_exp__h638897 == 8'd255) ? - _theResult___fst_exp__h638897 : - _theResult___fst_exp__h639417 ; - assign _theResult___fst_exp__h648007 = - _theResult____h639769[56] ? + assign _theResult___fst_exp__h639417 = + (_theResult___fst_exp__h638894 == 8'd255) ? + _theResult___fst_exp__h638894 : + _theResult___fst_exp__h639414 ; + assign _theResult___fst_exp__h648004 = + _theResult____h639766[56] ? 8'd2 : - _theResult___fst_exp__h648081 ; - assign _theResult___fst_exp__h648072 = + _theResult___fst_exp__h648078 ; + assign _theResult___fst_exp__h648069 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 } ; - assign _theResult___fst_exp__h648078 = - (!_theResult____h639769[56] && !_theResult____h639769[55] && - !_theResult____h639769[54] && - !_theResult____h639769[53] && - !_theResult____h639769[52] && - !_theResult____h639769[51] && - !_theResult____h639769[50] && - !_theResult____h639769[49] && - !_theResult____h639769[48] && - !_theResult____h639769[47] && - !_theResult____h639769[46] && - !_theResult____h639769[45] && - !_theResult____h639769[44] && - !_theResult____h639769[43] && - !_theResult____h639769[42] && - !_theResult____h639769[41] && - !_theResult____h639769[40] && - !_theResult____h639769[39] && - !_theResult____h639769[38] && - !_theResult____h639769[37] && - !_theResult____h639769[36] && - !_theResult____h639769[35] && - !_theResult____h639769[34] && - !_theResult____h639769[33] && - !_theResult____h639769[32] && - !_theResult____h639769[31] && - !_theResult____h639769[30] && - !_theResult____h639769[29] && - !_theResult____h639769[28] && - !_theResult____h639769[27] && - !_theResult____h639769[26] && - !_theResult____h639769[25] && - !_theResult____h639769[24] && - !_theResult____h639769[23] && - !_theResult____h639769[22] && - !_theResult____h639769[21] && - !_theResult____h639769[20] && - !_theResult____h639769[19] && - !_theResult____h639769[18] && - !_theResult____h639769[17] && - !_theResult____h639769[16] && - !_theResult____h639769[15] && - !_theResult____h639769[14] && - !_theResult____h639769[13] && - !_theResult____h639769[12] && - !_theResult____h639769[11] && - !_theResult____h639769[10] && - !_theResult____h639769[9] && - !_theResult____h639769[8] && - !_theResult____h639769[7] && - !_theResult____h639769[6] && - !_theResult____h639769[5] && - !_theResult____h639769[4] && - !_theResult____h639769[3] && - !_theResult____h639769[2] && - !_theResult____h639769[1] && - !_theResult____h639769[0] || + assign _theResult___fst_exp__h648075 = + (!_theResult____h639766[56] && !_theResult____h639766[55] && + !_theResult____h639766[54] && + !_theResult____h639766[53] && + !_theResult____h639766[52] && + !_theResult____h639766[51] && + !_theResult____h639766[50] && + !_theResult____h639766[49] && + !_theResult____h639766[48] && + !_theResult____h639766[47] && + !_theResult____h639766[46] && + !_theResult____h639766[45] && + !_theResult____h639766[44] && + !_theResult____h639766[43] && + !_theResult____h639766[42] && + !_theResult____h639766[41] && + !_theResult____h639766[40] && + !_theResult____h639766[39] && + !_theResult____h639766[38] && + !_theResult____h639766[37] && + !_theResult____h639766[36] && + !_theResult____h639766[35] && + !_theResult____h639766[34] && + !_theResult____h639766[33] && + !_theResult____h639766[32] && + !_theResult____h639766[31] && + !_theResult____h639766[30] && + !_theResult____h639766[29] && + !_theResult____h639766[28] && + !_theResult____h639766[27] && + !_theResult____h639766[26] && + !_theResult____h639766[25] && + !_theResult____h639766[24] && + !_theResult____h639766[23] && + !_theResult____h639766[22] && + !_theResult____h639766[21] && + !_theResult____h639766[20] && + !_theResult____h639766[19] && + !_theResult____h639766[18] && + !_theResult____h639766[17] && + !_theResult____h639766[16] && + !_theResult____h639766[15] && + !_theResult____h639766[14] && + !_theResult____h639766[13] && + !_theResult____h639766[12] && + !_theResult____h639766[11] && + !_theResult____h639766[10] && + !_theResult____h639766[9] && + !_theResult____h639766[8] && + !_theResult____h639766[7] && + !_theResult____h639766[6] && + !_theResult____h639766[5] && + !_theResult____h639766[4] && + !_theResult____h639766[3] && + !_theResult____h639766[2] && + !_theResult____h639766[1] && + !_theResult____h639766[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10302) ? 8'd0 : - _theResult___fst_exp__h648072 ; - assign _theResult___fst_exp__h648081 = - (!_theResult____h639769[56] && _theResult____h639769[55]) ? + _theResult___fst_exp__h648069 ; + assign _theResult___fst_exp__h648078 = + (!_theResult____h639766[56] && _theResult____h639766[55]) ? 8'd1 : - _theResult___fst_exp__h648078 ; - assign _theResult___fst_exp__h648604 = - (_theResult___fst_exp__h648007 == 8'd255) ? - _theResult___fst_exp__h648007 : - _theResult___fst_exp__h648601 ; - assign _theResult___fst_exp__h656644 = + _theResult___fst_exp__h648075 ; + assign _theResult___fst_exp__h648601 = + (_theResult___fst_exp__h648004 == 8'd255) ? + _theResult___fst_exp__h648004 : + _theResult___fst_exp__h648598 ; + assign _theResult___fst_exp__h656641 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] ; - assign _theResult___fst_exp__h656683 = + assign _theResult___fst_exp__h656680 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q83[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 } ; - assign _theResult___fst_exp__h656689 = + assign _theResult___fst_exp__h656686 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10375) ? 8'd0 : - _theResult___fst_exp__h656683 ; - assign _theResult___fst_exp__h656692 = + _theResult___fst_exp__h656680 ; + assign _theResult___fst_exp__h656689 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h656686 : + _theResult___fst_exp__h656641 ; + assign _theResult___fst_exp__h657237 = + (_theResult___fst_exp__h656689 == 8'd255) ? _theResult___fst_exp__h656689 : - _theResult___fst_exp__h656644 ; - assign _theResult___fst_exp__h657240 = - (_theResult___fst_exp__h656692 == 8'd255) ? - _theResult___fst_exp__h656692 : - _theResult___fst_exp__h657237 ; - assign _theResult___fst_exp__h657249 = + _theResult___fst_exp__h657234 ; + assign _theResult___fst_exp__h657246 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? - _theResult___snd_fst_exp__h639423 : - _theResult___fst_exp__h622114) : + _theResult___snd_fst_exp__h639420 : + _theResult___fst_exp__h622111) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? - _theResult___snd_fst_exp__h657243 : - _theResult___fst_exp__h622114) ; - assign _theResult___fst_exp__h657252 = + _theResult___snd_fst_exp__h657240 : + _theResult___fst_exp__h622111) ; + assign _theResult___fst_exp__h657249 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h657249 ; - assign _theResult___fst_exp__h675988 = - _theResult____h667879[56] ? + _theResult___fst_exp__h657246 ; + assign _theResult___fst_exp__h675985 = + _theResult____h667876[56] ? 8'd2 : - _theResult___fst_exp__h676062 ; - assign _theResult___fst_exp__h676053 = + _theResult___fst_exp__h676059 ; + assign _theResult___fst_exp__h676050 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 } ; - assign _theResult___fst_exp__h676059 = - (!_theResult____h667879[56] && !_theResult____h667879[55] && - !_theResult____h667879[54] && - !_theResult____h667879[53] && - !_theResult____h667879[52] && - !_theResult____h667879[51] && - !_theResult____h667879[50] && - !_theResult____h667879[49] && - !_theResult____h667879[48] && - !_theResult____h667879[47] && - !_theResult____h667879[46] && - !_theResult____h667879[45] && - !_theResult____h667879[44] && - !_theResult____h667879[43] && - !_theResult____h667879[42] && - !_theResult____h667879[41] && - !_theResult____h667879[40] && - !_theResult____h667879[39] && - !_theResult____h667879[38] && - !_theResult____h667879[37] && - !_theResult____h667879[36] && - !_theResult____h667879[35] && - !_theResult____h667879[34] && - !_theResult____h667879[33] && - !_theResult____h667879[32] && - !_theResult____h667879[31] && - !_theResult____h667879[30] && - !_theResult____h667879[29] && - !_theResult____h667879[28] && - !_theResult____h667879[27] && - !_theResult____h667879[26] && - !_theResult____h667879[25] && - !_theResult____h667879[24] && - !_theResult____h667879[23] && - !_theResult____h667879[22] && - !_theResult____h667879[21] && - !_theResult____h667879[20] && - !_theResult____h667879[19] && - !_theResult____h667879[18] && - !_theResult____h667879[17] && - !_theResult____h667879[16] && - !_theResult____h667879[15] && - !_theResult____h667879[14] && - !_theResult____h667879[13] && - !_theResult____h667879[12] && - !_theResult____h667879[11] && - !_theResult____h667879[10] && - !_theResult____h667879[9] && - !_theResult____h667879[8] && - !_theResult____h667879[7] && - !_theResult____h667879[6] && - !_theResult____h667879[5] && - !_theResult____h667879[4] && - !_theResult____h667879[3] && - !_theResult____h667879[2] && - !_theResult____h667879[1] && - !_theResult____h667879[0] || + assign _theResult___fst_exp__h676056 = + (!_theResult____h667876[56] && !_theResult____h667876[55] && + !_theResult____h667876[54] && + !_theResult____h667876[53] && + !_theResult____h667876[52] && + !_theResult____h667876[51] && + !_theResult____h667876[50] && + !_theResult____h667876[49] && + !_theResult____h667876[48] && + !_theResult____h667876[47] && + !_theResult____h667876[46] && + !_theResult____h667876[45] && + !_theResult____h667876[44] && + !_theResult____h667876[43] && + !_theResult____h667876[42] && + !_theResult____h667876[41] && + !_theResult____h667876[40] && + !_theResult____h667876[39] && + !_theResult____h667876[38] && + !_theResult____h667876[37] && + !_theResult____h667876[36] && + !_theResult____h667876[35] && + !_theResult____h667876[34] && + !_theResult____h667876[33] && + !_theResult____h667876[32] && + !_theResult____h667876[31] && + !_theResult____h667876[30] && + !_theResult____h667876[29] && + !_theResult____h667876[28] && + !_theResult____h667876[27] && + !_theResult____h667876[26] && + !_theResult____h667876[25] && + !_theResult____h667876[24] && + !_theResult____h667876[23] && + !_theResult____h667876[22] && + !_theResult____h667876[21] && + !_theResult____h667876[20] && + !_theResult____h667876[19] && + !_theResult____h667876[18] && + !_theResult____h667876[17] && + !_theResult____h667876[16] && + !_theResult____h667876[15] && + !_theResult____h667876[14] && + !_theResult____h667876[13] && + !_theResult____h667876[12] && + !_theResult____h667876[11] && + !_theResult____h667876[10] && + !_theResult____h667876[9] && + !_theResult____h667876[8] && + !_theResult____h667876[7] && + !_theResult____h667876[6] && + !_theResult____h667876[5] && + !_theResult____h667876[4] && + !_theResult____h667876[3] && + !_theResult____h667876[2] && + !_theResult____h667876[1] && + !_theResult____h667876[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11148) ? 8'd0 : - _theResult___fst_exp__h676053 ; - assign _theResult___fst_exp__h676062 = - (!_theResult____h667879[56] && _theResult____h667879[55]) ? + _theResult___fst_exp__h676050 ; + assign _theResult___fst_exp__h676059 = + (!_theResult____h667876[56] && _theResult____h667876[55]) ? 8'd1 : - _theResult___fst_exp__h676059 ; - assign _theResult___fst_exp__h676585 = - (_theResult___fst_exp__h675988 == 8'd255) ? - _theResult___fst_exp__h675988 : - _theResult___fst_exp__h676582 ; - assign _theResult___fst_exp__h684635 = + _theResult___fst_exp__h676056 ; + assign _theResult___fst_exp__h676582 = + (_theResult___fst_exp__h675985 == 8'd255) ? + _theResult___fst_exp__h675985 : + _theResult___fst_exp__h676579 ; + assign _theResult___fst_exp__h684632 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ; - assign _theResult___fst_exp__h684641 = + assign _theResult___fst_exp__h684638 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11379) ? 8'd0 : - _theResult___fst_exp__h684635 ; - assign _theResult___fst_exp__h684644 = + _theResult___fst_exp__h684632 ; + assign _theResult___fst_exp__h684641 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h684641 : + _theResult___fst_exp__h684638 : 8'd129 ; - assign _theResult___fst_exp__h685167 = - (_theResult___fst_exp__h684644 == 8'd255) ? - _theResult___fst_exp__h684644 : - _theResult___fst_exp__h685164 ; - assign _theResult___fst_exp__h693754 = - _theResult____h685516[56] ? + assign _theResult___fst_exp__h685164 = + (_theResult___fst_exp__h684641 == 8'd255) ? + _theResult___fst_exp__h684641 : + _theResult___fst_exp__h685161 ; + assign _theResult___fst_exp__h693751 = + _theResult____h685513[56] ? 8'd2 : - _theResult___fst_exp__h693828 ; - assign _theResult___fst_exp__h693819 = + _theResult___fst_exp__h693825 ; + assign _theResult___fst_exp__h693816 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 } ; - assign _theResult___fst_exp__h693825 = - (!_theResult____h685516[56] && !_theResult____h685516[55] && - !_theResult____h685516[54] && - !_theResult____h685516[53] && - !_theResult____h685516[52] && - !_theResult____h685516[51] && - !_theResult____h685516[50] && - !_theResult____h685516[49] && - !_theResult____h685516[48] && - !_theResult____h685516[47] && - !_theResult____h685516[46] && - !_theResult____h685516[45] && - !_theResult____h685516[44] && - !_theResult____h685516[43] && - !_theResult____h685516[42] && - !_theResult____h685516[41] && - !_theResult____h685516[40] && - !_theResult____h685516[39] && - !_theResult____h685516[38] && - !_theResult____h685516[37] && - !_theResult____h685516[36] && - !_theResult____h685516[35] && - !_theResult____h685516[34] && - !_theResult____h685516[33] && - !_theResult____h685516[32] && - !_theResult____h685516[31] && - !_theResult____h685516[30] && - !_theResult____h685516[29] && - !_theResult____h685516[28] && - !_theResult____h685516[27] && - !_theResult____h685516[26] && - !_theResult____h685516[25] && - !_theResult____h685516[24] && - !_theResult____h685516[23] && - !_theResult____h685516[22] && - !_theResult____h685516[21] && - !_theResult____h685516[20] && - !_theResult____h685516[19] && - !_theResult____h685516[18] && - !_theResult____h685516[17] && - !_theResult____h685516[16] && - !_theResult____h685516[15] && - !_theResult____h685516[14] && - !_theResult____h685516[13] && - !_theResult____h685516[12] && - !_theResult____h685516[11] && - !_theResult____h685516[10] && - !_theResult____h685516[9] && - !_theResult____h685516[8] && - !_theResult____h685516[7] && - !_theResult____h685516[6] && - !_theResult____h685516[5] && - !_theResult____h685516[4] && - !_theResult____h685516[3] && - !_theResult____h685516[2] && - !_theResult____h685516[1] && - !_theResult____h685516[0] || + assign _theResult___fst_exp__h693822 = + (!_theResult____h685513[56] && !_theResult____h685513[55] && + !_theResult____h685513[54] && + !_theResult____h685513[53] && + !_theResult____h685513[52] && + !_theResult____h685513[51] && + !_theResult____h685513[50] && + !_theResult____h685513[49] && + !_theResult____h685513[48] && + !_theResult____h685513[47] && + !_theResult____h685513[46] && + !_theResult____h685513[45] && + !_theResult____h685513[44] && + !_theResult____h685513[43] && + !_theResult____h685513[42] && + !_theResult____h685513[41] && + !_theResult____h685513[40] && + !_theResult____h685513[39] && + !_theResult____h685513[38] && + !_theResult____h685513[37] && + !_theResult____h685513[36] && + !_theResult____h685513[35] && + !_theResult____h685513[34] && + !_theResult____h685513[33] && + !_theResult____h685513[32] && + !_theResult____h685513[31] && + !_theResult____h685513[30] && + !_theResult____h685513[29] && + !_theResult____h685513[28] && + !_theResult____h685513[27] && + !_theResult____h685513[26] && + !_theResult____h685513[25] && + !_theResult____h685513[24] && + !_theResult____h685513[23] && + !_theResult____h685513[22] && + !_theResult____h685513[21] && + !_theResult____h685513[20] && + !_theResult____h685513[19] && + !_theResult____h685513[18] && + !_theResult____h685513[17] && + !_theResult____h685513[16] && + !_theResult____h685513[15] && + !_theResult____h685513[14] && + !_theResult____h685513[13] && + !_theResult____h685513[12] && + !_theResult____h685513[11] && + !_theResult____h685513[10] && + !_theResult____h685513[9] && + !_theResult____h685513[8] && + !_theResult____h685513[7] && + !_theResult____h685513[6] && + !_theResult____h685513[5] && + !_theResult____h685513[4] && + !_theResult____h685513[3] && + !_theResult____h685513[2] && + !_theResult____h685513[1] && + !_theResult____h685513[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11699) ? 8'd0 : - _theResult___fst_exp__h693819 ; - assign _theResult___fst_exp__h693828 = - (!_theResult____h685516[56] && _theResult____h685516[55]) ? + _theResult___fst_exp__h693816 ; + assign _theResult___fst_exp__h693825 = + (!_theResult____h685513[56] && _theResult____h685513[55]) ? 8'd1 : - _theResult___fst_exp__h693825 ; - assign _theResult___fst_exp__h694351 = - (_theResult___fst_exp__h693754 == 8'd255) ? - _theResult___fst_exp__h693754 : - _theResult___fst_exp__h694348 ; - assign _theResult___fst_exp__h702391 = + _theResult___fst_exp__h693822 ; + assign _theResult___fst_exp__h694348 = + (_theResult___fst_exp__h693751 == 8'd255) ? + _theResult___fst_exp__h693751 : + _theResult___fst_exp__h694345 ; + assign _theResult___fst_exp__h702388 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] ; - assign _theResult___fst_exp__h702430 = + assign _theResult___fst_exp__h702427 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q118[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 } ; - assign _theResult___fst_exp__h702436 = + assign _theResult___fst_exp__h702433 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11772) ? 8'd0 : - _theResult___fst_exp__h702430 ; - assign _theResult___fst_exp__h702439 = + _theResult___fst_exp__h702427 ; + assign _theResult___fst_exp__h702436 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h702433 : + _theResult___fst_exp__h702388 ; + assign _theResult___fst_exp__h702984 = + (_theResult___fst_exp__h702436 == 8'd255) ? _theResult___fst_exp__h702436 : - _theResult___fst_exp__h702391 ; - assign _theResult___fst_exp__h702987 = - (_theResult___fst_exp__h702439 == 8'd255) ? - _theResult___fst_exp__h702439 : - _theResult___fst_exp__h702984 ; - assign _theResult___fst_exp__h702996 = + _theResult___fst_exp__h702981 ; + assign _theResult___fst_exp__h702993 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? - _theResult___snd_fst_exp__h685170 : - _theResult___fst_exp__h667861) : + _theResult___snd_fst_exp__h685167 : + _theResult___fst_exp__h667858) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? - _theResult___snd_fst_exp__h702990 : - _theResult___fst_exp__h667861) ; - assign _theResult___fst_exp__h702999 = + _theResult___snd_fst_exp__h702987 : + _theResult___fst_exp__h667858) ; + assign _theResult___fst_exp__h702996 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h702996 ; - assign _theResult___fst_exp__h719140 = + _theResult___fst_exp__h702993 ; + assign _theResult___fst_exp__h719137 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q26 ; - assign _theResult___fst_exp__h734204 = + assign _theResult___fst_exp__h734201 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ; - assign _theResult___fst_exp__h734210 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___fst_exp__h734207 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12718) ? 11'd0 : - _theResult___fst_exp__h734204 ; - assign _theResult___fst_exp__h734213 = - (f1_exp__h714825 == 8'd0) ? - _theResult___fst_exp__h734210 : + _theResult___fst_exp__h734201 ; + assign _theResult___fst_exp__h734210 = + (f1_exp__h714822 == 8'd0) ? + _theResult___fst_exp__h734207 : 11'd897 ; - assign _theResult___fst_exp__h734968 = + assign _theResult___fst_exp__h734965 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 : + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 ; - assign _theResult___fst_exp__h734971 = - (_theResult___fst_exp__h734213 == 11'd2047) ? - _theResult___fst_exp__h734213 : - _theResult___fst_exp__h734968 ; - assign _theResult___fst_exp__h743790 = - _theResult____h735554[56] ? + assign _theResult___fst_exp__h734968 = + (_theResult___fst_exp__h734210 == 11'd2047) ? + _theResult___fst_exp__h734210 : + _theResult___fst_exp__h734965 ; + assign _theResult___fst_exp__h743787 = + _theResult____h735551[56] ? 11'd2 : - _theResult___fst_exp__h743864 ; - assign _theResult___fst_exp__h743855 = + _theResult___fst_exp__h743861 ; + assign _theResult___fst_exp__h743852 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 } ; - assign _theResult___fst_exp__h743861 = - (!_theResult____h735554[56] && !_theResult____h735554[55] && - !_theResult____h735554[54] && - !_theResult____h735554[53] && - !_theResult____h735554[52] && - !_theResult____h735554[51] && - !_theResult____h735554[50] && - !_theResult____h735554[49] && - !_theResult____h735554[48] && - !_theResult____h735554[47] && - !_theResult____h735554[46] && - !_theResult____h735554[45] && - !_theResult____h735554[44] && - !_theResult____h735554[43] && - !_theResult____h735554[42] && - !_theResult____h735554[41] && - !_theResult____h735554[40] && - !_theResult____h735554[39] && - !_theResult____h735554[38] && - !_theResult____h735554[37] && - !_theResult____h735554[36] && - !_theResult____h735554[35] && - !_theResult____h735554[34] && - !_theResult____h735554[33] && - !_theResult____h735554[32] && - !_theResult____h735554[31] && - !_theResult____h735554[30] && - !_theResult____h735554[29] && - !_theResult____h735554[28] && - !_theResult____h735554[27] && - !_theResult____h735554[26] && - !_theResult____h735554[25] && - !_theResult____h735554[24] && - !_theResult____h735554[23] && - !_theResult____h735554[22] && - !_theResult____h735554[21] && - !_theResult____h735554[20] && - !_theResult____h735554[19] && - !_theResult____h735554[18] && - !_theResult____h735554[17] && - !_theResult____h735554[16] && - !_theResult____h735554[15] && - !_theResult____h735554[14] && - !_theResult____h735554[13] && - !_theResult____h735554[12] && - !_theResult____h735554[11] && - !_theResult____h735554[10] && - !_theResult____h735554[9] && - !_theResult____h735554[8] && - !_theResult____h735554[7] && - !_theResult____h735554[6] && - !_theResult____h735554[5] && - !_theResult____h735554[4] && - !_theResult____h735554[3] && - !_theResult____h735554[2] && - !_theResult____h735554[1] && - !_theResult____h735554[0] || + assign _theResult___fst_exp__h743858 = + (!_theResult____h735551[56] && !_theResult____h735551[55] && + !_theResult____h735551[54] && + !_theResult____h735551[53] && + !_theResult____h735551[52] && + !_theResult____h735551[51] && + !_theResult____h735551[50] && + !_theResult____h735551[49] && + !_theResult____h735551[48] && + !_theResult____h735551[47] && + !_theResult____h735551[46] && + !_theResult____h735551[45] && + !_theResult____h735551[44] && + !_theResult____h735551[43] && + !_theResult____h735551[42] && + !_theResult____h735551[41] && + !_theResult____h735551[40] && + !_theResult____h735551[39] && + !_theResult____h735551[38] && + !_theResult____h735551[37] && + !_theResult____h735551[36] && + !_theResult____h735551[35] && + !_theResult____h735551[34] && + !_theResult____h735551[33] && + !_theResult____h735551[32] && + !_theResult____h735551[31] && + !_theResult____h735551[30] && + !_theResult____h735551[29] && + !_theResult____h735551[28] && + !_theResult____h735551[27] && + !_theResult____h735551[26] && + !_theResult____h735551[25] && + !_theResult____h735551[24] && + !_theResult____h735551[23] && + !_theResult____h735551[22] && + !_theResult____h735551[21] && + !_theResult____h735551[20] && + !_theResult____h735551[19] && + !_theResult____h735551[18] && + !_theResult____h735551[17] && + !_theResult____h735551[16] && + !_theResult____h735551[15] && + !_theResult____h735551[14] && + !_theResult____h735551[13] && + !_theResult____h735551[12] && + !_theResult____h735551[11] && + !_theResult____h735551[10] && + !_theResult____h735551[9] && + !_theResult____h735551[8] && + !_theResult____h735551[7] && + !_theResult____h735551[6] && + !_theResult____h735551[5] && + !_theResult____h735551[4] && + !_theResult____h735551[3] && + !_theResult____h735551[2] && + !_theResult____h735551[1] && + !_theResult____h735551[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13030) ? 11'd0 : - _theResult___fst_exp__h743855 ; - assign _theResult___fst_exp__h743864 = - (!_theResult____h735554[56] && _theResult____h735554[55]) ? + _theResult___fst_exp__h743852 ; + assign _theResult___fst_exp__h743861 = + (!_theResult____h735551[56] && _theResult____h735551[55]) ? 11'd1 : - _theResult___fst_exp__h743861 ; - assign _theResult___fst_exp__h744619 = + _theResult___fst_exp__h743858 ; + assign _theResult___fst_exp__h744616 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 : + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 ; - assign _theResult___fst_exp__h744622 = - (_theResult___fst_exp__h743790 == 11'd2047) ? - _theResult___fst_exp__h743790 : - _theResult___fst_exp__h744619 ; - assign _theResult___fst_exp__h752575 = + assign _theResult___fst_exp__h744619 = + (_theResult___fst_exp__h743787 == 11'd2047) ? + _theResult___fst_exp__h743787 : + _theResult___fst_exp__h744616 ; + assign _theResult___fst_exp__h752572 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] ; - assign _theResult___fst_exp__h752614 = + assign _theResult___fst_exp__h752611 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q148[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 } ; - assign _theResult___fst_exp__h752620 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___fst_exp__h752617 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13080) ? 11'd0 : - _theResult___fst_exp__h752614 ; - assign _theResult___fst_exp__h752623 = - (f1_exp__h714825 == 8'd0) ? - _theResult___fst_exp__h752620 : - _theResult___fst_exp__h752575 ; - assign _theResult___fst_exp__h753403 = + _theResult___fst_exp__h752611 ; + assign _theResult___fst_exp__h752620 = + (f1_exp__h714822 == 8'd0) ? + _theResult___fst_exp__h752617 : + _theResult___fst_exp__h752572 ; + assign _theResult___fst_exp__h753400 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 : + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 ; - assign _theResult___fst_exp__h753406 = - (_theResult___fst_exp__h752623 == 11'd2047) ? - _theResult___fst_exp__h752623 : - _theResult___fst_exp__h753403 ; - assign _theResult___fst_exp__h753415 = - (f1_exp__h714825 == 8'd0) ? + assign _theResult___fst_exp__h753403 = + (_theResult___fst_exp__h752620 == 11'd2047) ? + _theResult___fst_exp__h752620 : + _theResult___fst_exp__h753400 ; + assign _theResult___fst_exp__h753412 = + (f1_exp__h714822 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 ? - _theResult___snd_fst_exp__h734974 : - _theResult___fst_exp__h719140) : + _theResult___snd_fst_exp__h734971 : + _theResult___fst_exp__h719137) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 ? - _theResult___snd_fst_exp__h753409 : - _theResult___fst_exp__h719140) ; - assign _theResult___fst_exp__h753418 = - (f1_exp__h714825 == 8'd0 && f1_sfd__h714826 == 23'd0) ? + _theResult___snd_fst_exp__h753406 : + _theResult___fst_exp__h719137) ; + assign _theResult___fst_exp__h753415 = + (f1_exp__h714822 == 8'd0 && f1_sfd__h714823 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h753415 ; - assign _theResult___fst_exp__h757993 = + _theResult___fst_exp__h753412 ; + assign _theResult___fst_exp__h757990 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 ; - assign _theResult___fst_exp__h773057 = + assign _theResult___fst_exp__h773054 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ; - assign _theResult___fst_exp__h773063 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___fst_exp__h773060 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14218) ? 11'd0 : - _theResult___fst_exp__h773057 ; - assign _theResult___fst_exp__h773066 = - (f2_exp__h753819 == 8'd0) ? - _theResult___fst_exp__h773063 : + _theResult___fst_exp__h773054 ; + assign _theResult___fst_exp__h773063 = + (f2_exp__h753816 == 8'd0) ? + _theResult___fst_exp__h773060 : 11'd897 ; - assign _theResult___fst_exp__h773821 = + assign _theResult___fst_exp__h773818 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 : + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 ; - assign _theResult___fst_exp__h773824 = - (_theResult___fst_exp__h773066 == 11'd2047) ? - _theResult___fst_exp__h773066 : - _theResult___fst_exp__h773821 ; - assign _theResult___fst_exp__h782643 = - _theResult____h774407[56] ? + assign _theResult___fst_exp__h773821 = + (_theResult___fst_exp__h773063 == 11'd2047) ? + _theResult___fst_exp__h773063 : + _theResult___fst_exp__h773818 ; + assign _theResult___fst_exp__h782640 = + _theResult____h774404[56] ? 11'd2 : - _theResult___fst_exp__h782717 ; - assign _theResult___fst_exp__h782708 = + _theResult___fst_exp__h782714 ; + assign _theResult___fst_exp__h782705 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 } ; - assign _theResult___fst_exp__h782714 = - (!_theResult____h774407[56] && !_theResult____h774407[55] && - !_theResult____h774407[54] && - !_theResult____h774407[53] && - !_theResult____h774407[52] && - !_theResult____h774407[51] && - !_theResult____h774407[50] && - !_theResult____h774407[49] && - !_theResult____h774407[48] && - !_theResult____h774407[47] && - !_theResult____h774407[46] && - !_theResult____h774407[45] && - !_theResult____h774407[44] && - !_theResult____h774407[43] && - !_theResult____h774407[42] && - !_theResult____h774407[41] && - !_theResult____h774407[40] && - !_theResult____h774407[39] && - !_theResult____h774407[38] && - !_theResult____h774407[37] && - !_theResult____h774407[36] && - !_theResult____h774407[35] && - !_theResult____h774407[34] && - !_theResult____h774407[33] && - !_theResult____h774407[32] && - !_theResult____h774407[31] && - !_theResult____h774407[30] && - !_theResult____h774407[29] && - !_theResult____h774407[28] && - !_theResult____h774407[27] && - !_theResult____h774407[26] && - !_theResult____h774407[25] && - !_theResult____h774407[24] && - !_theResult____h774407[23] && - !_theResult____h774407[22] && - !_theResult____h774407[21] && - !_theResult____h774407[20] && - !_theResult____h774407[19] && - !_theResult____h774407[18] && - !_theResult____h774407[17] && - !_theResult____h774407[16] && - !_theResult____h774407[15] && - !_theResult____h774407[14] && - !_theResult____h774407[13] && - !_theResult____h774407[12] && - !_theResult____h774407[11] && - !_theResult____h774407[10] && - !_theResult____h774407[9] && - !_theResult____h774407[8] && - !_theResult____h774407[7] && - !_theResult____h774407[6] && - !_theResult____h774407[5] && - !_theResult____h774407[4] && - !_theResult____h774407[3] && - !_theResult____h774407[2] && - !_theResult____h774407[1] && - !_theResult____h774407[0] || + assign _theResult___fst_exp__h782711 = + (!_theResult____h774404[56] && !_theResult____h774404[55] && + !_theResult____h774404[54] && + !_theResult____h774404[53] && + !_theResult____h774404[52] && + !_theResult____h774404[51] && + !_theResult____h774404[50] && + !_theResult____h774404[49] && + !_theResult____h774404[48] && + !_theResult____h774404[47] && + !_theResult____h774404[46] && + !_theResult____h774404[45] && + !_theResult____h774404[44] && + !_theResult____h774404[43] && + !_theResult____h774404[42] && + !_theResult____h774404[41] && + !_theResult____h774404[40] && + !_theResult____h774404[39] && + !_theResult____h774404[38] && + !_theResult____h774404[37] && + !_theResult____h774404[36] && + !_theResult____h774404[35] && + !_theResult____h774404[34] && + !_theResult____h774404[33] && + !_theResult____h774404[32] && + !_theResult____h774404[31] && + !_theResult____h774404[30] && + !_theResult____h774404[29] && + !_theResult____h774404[28] && + !_theResult____h774404[27] && + !_theResult____h774404[26] && + !_theResult____h774404[25] && + !_theResult____h774404[24] && + !_theResult____h774404[23] && + !_theResult____h774404[22] && + !_theResult____h774404[21] && + !_theResult____h774404[20] && + !_theResult____h774404[19] && + !_theResult____h774404[18] && + !_theResult____h774404[17] && + !_theResult____h774404[16] && + !_theResult____h774404[15] && + !_theResult____h774404[14] && + !_theResult____h774404[13] && + !_theResult____h774404[12] && + !_theResult____h774404[11] && + !_theResult____h774404[10] && + !_theResult____h774404[9] && + !_theResult____h774404[8] && + !_theResult____h774404[7] && + !_theResult____h774404[6] && + !_theResult____h774404[5] && + !_theResult____h774404[4] && + !_theResult____h774404[3] && + !_theResult____h774404[2] && + !_theResult____h774404[1] && + !_theResult____h774404[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14515) ? 11'd0 : - _theResult___fst_exp__h782708 ; - assign _theResult___fst_exp__h782717 = - (!_theResult____h774407[56] && _theResult____h774407[55]) ? + _theResult___fst_exp__h782705 ; + assign _theResult___fst_exp__h782714 = + (!_theResult____h774404[56] && _theResult____h774404[55]) ? 11'd1 : - _theResult___fst_exp__h782714 ; - assign _theResult___fst_exp__h783472 = + _theResult___fst_exp__h782711 ; + assign _theResult___fst_exp__h783469 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 : + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 ; - assign _theResult___fst_exp__h783475 = - (_theResult___fst_exp__h782643 == 11'd2047) ? - _theResult___fst_exp__h782643 : - _theResult___fst_exp__h783472 ; - assign _theResult___fst_exp__h791428 = + assign _theResult___fst_exp__h783472 = + (_theResult___fst_exp__h782640 == 11'd2047) ? + _theResult___fst_exp__h782640 : + _theResult___fst_exp__h783469 ; + assign _theResult___fst_exp__h791425 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] ; - assign _theResult___fst_exp__h791467 = + assign _theResult___fst_exp__h791464 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q188[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 } ; - assign _theResult___fst_exp__h791473 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___fst_exp__h791470 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14565) ? 11'd0 : - _theResult___fst_exp__h791467 ; - assign _theResult___fst_exp__h791476 = - (f2_exp__h753819 == 8'd0) ? - _theResult___fst_exp__h791473 : - _theResult___fst_exp__h791428 ; - assign _theResult___fst_exp__h792256 = + _theResult___fst_exp__h791464 ; + assign _theResult___fst_exp__h791473 = + (f2_exp__h753816 == 8'd0) ? + _theResult___fst_exp__h791470 : + _theResult___fst_exp__h791425 ; + assign _theResult___fst_exp__h792253 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 : + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 ; - assign _theResult___fst_exp__h792259 = - (_theResult___fst_exp__h791476 == 11'd2047) ? - _theResult___fst_exp__h791476 : - _theResult___fst_exp__h792256 ; - assign _theResult___fst_exp__h792268 = - (f2_exp__h753819 == 8'd0) ? + assign _theResult___fst_exp__h792256 = + (_theResult___fst_exp__h791473 == 11'd2047) ? + _theResult___fst_exp__h791473 : + _theResult___fst_exp__h792253 ; + assign _theResult___fst_exp__h792265 = + (f2_exp__h753816 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? - _theResult___snd_fst_exp__h773827 : - _theResult___fst_exp__h757993) : + _theResult___snd_fst_exp__h773824 : + _theResult___fst_exp__h757990) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? - _theResult___snd_fst_exp__h792262 : - _theResult___fst_exp__h757993) ; - assign _theResult___fst_exp__h792271 = - (f2_exp__h753819 == 8'd0 && f2_sfd__h753820 == 23'd0) ? + _theResult___snd_fst_exp__h792259 : + _theResult___fst_exp__h757990) ; + assign _theResult___fst_exp__h792268 = + (f2_exp__h753816 == 8'd0 && f2_sfd__h753817 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h792268 ; - assign _theResult___fst_exp__h797297 = + _theResult___fst_exp__h792265 ; + assign _theResult___fst_exp__h797294 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 ; - assign _theResult___fst_exp__h812361 = + assign _theResult___fst_exp__h812358 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ; - assign _theResult___fst_exp__h812367 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___fst_exp__h812364 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13448) ? 11'd0 : - _theResult___fst_exp__h812361 ; - assign _theResult___fst_exp__h812370 = - (f3_exp__h793123 == 8'd0) ? - _theResult___fst_exp__h812367 : + _theResult___fst_exp__h812358 ; + assign _theResult___fst_exp__h812367 = + (f3_exp__h793120 == 8'd0) ? + _theResult___fst_exp__h812364 : 11'd897 ; - assign _theResult___fst_exp__h813125 = + assign _theResult___fst_exp__h813122 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 : + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 ; - assign _theResult___fst_exp__h813128 = - (_theResult___fst_exp__h812370 == 11'd2047) ? - _theResult___fst_exp__h812370 : - _theResult___fst_exp__h813125 ; - assign _theResult___fst_exp__h821947 = - _theResult____h813711[56] ? + assign _theResult___fst_exp__h813125 = + (_theResult___fst_exp__h812367 == 11'd2047) ? + _theResult___fst_exp__h812367 : + _theResult___fst_exp__h813122 ; + assign _theResult___fst_exp__h821944 = + _theResult____h813708[56] ? 11'd2 : - _theResult___fst_exp__h822021 ; - assign _theResult___fst_exp__h822012 = + _theResult___fst_exp__h822018 ; + assign _theResult___fst_exp__h822009 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 } ; - assign _theResult___fst_exp__h822018 = - (!_theResult____h813711[56] && !_theResult____h813711[55] && - !_theResult____h813711[54] && - !_theResult____h813711[53] && - !_theResult____h813711[52] && - !_theResult____h813711[51] && - !_theResult____h813711[50] && - !_theResult____h813711[49] && - !_theResult____h813711[48] && - !_theResult____h813711[47] && - !_theResult____h813711[46] && - !_theResult____h813711[45] && - !_theResult____h813711[44] && - !_theResult____h813711[43] && - !_theResult____h813711[42] && - !_theResult____h813711[41] && - !_theResult____h813711[40] && - !_theResult____h813711[39] && - !_theResult____h813711[38] && - !_theResult____h813711[37] && - !_theResult____h813711[36] && - !_theResult____h813711[35] && - !_theResult____h813711[34] && - !_theResult____h813711[33] && - !_theResult____h813711[32] && - !_theResult____h813711[31] && - !_theResult____h813711[30] && - !_theResult____h813711[29] && - !_theResult____h813711[28] && - !_theResult____h813711[27] && - !_theResult____h813711[26] && - !_theResult____h813711[25] && - !_theResult____h813711[24] && - !_theResult____h813711[23] && - !_theResult____h813711[22] && - !_theResult____h813711[21] && - !_theResult____h813711[20] && - !_theResult____h813711[19] && - !_theResult____h813711[18] && - !_theResult____h813711[17] && - !_theResult____h813711[16] && - !_theResult____h813711[15] && - !_theResult____h813711[14] && - !_theResult____h813711[13] && - !_theResult____h813711[12] && - !_theResult____h813711[11] && - !_theResult____h813711[10] && - !_theResult____h813711[9] && - !_theResult____h813711[8] && - !_theResult____h813711[7] && - !_theResult____h813711[6] && - !_theResult____h813711[5] && - !_theResult____h813711[4] && - !_theResult____h813711[3] && - !_theResult____h813711[2] && - !_theResult____h813711[1] && - !_theResult____h813711[0] || + assign _theResult___fst_exp__h822015 = + (!_theResult____h813708[56] && !_theResult____h813708[55] && + !_theResult____h813708[54] && + !_theResult____h813708[53] && + !_theResult____h813708[52] && + !_theResult____h813708[51] && + !_theResult____h813708[50] && + !_theResult____h813708[49] && + !_theResult____h813708[48] && + !_theResult____h813708[47] && + !_theResult____h813708[46] && + !_theResult____h813708[45] && + !_theResult____h813708[44] && + !_theResult____h813708[43] && + !_theResult____h813708[42] && + !_theResult____h813708[41] && + !_theResult____h813708[40] && + !_theResult____h813708[39] && + !_theResult____h813708[38] && + !_theResult____h813708[37] && + !_theResult____h813708[36] && + !_theResult____h813708[35] && + !_theResult____h813708[34] && + !_theResult____h813708[33] && + !_theResult____h813708[32] && + !_theResult____h813708[31] && + !_theResult____h813708[30] && + !_theResult____h813708[29] && + !_theResult____h813708[28] && + !_theResult____h813708[27] && + !_theResult____h813708[26] && + !_theResult____h813708[25] && + !_theResult____h813708[24] && + !_theResult____h813708[23] && + !_theResult____h813708[22] && + !_theResult____h813708[21] && + !_theResult____h813708[20] && + !_theResult____h813708[19] && + !_theResult____h813708[18] && + !_theResult____h813708[17] && + !_theResult____h813708[16] && + !_theResult____h813708[15] && + !_theResult____h813708[14] && + !_theResult____h813708[13] && + !_theResult____h813708[12] && + !_theResult____h813708[11] && + !_theResult____h813708[10] && + !_theResult____h813708[9] && + !_theResult____h813708[8] && + !_theResult____h813708[7] && + !_theResult____h813708[6] && + !_theResult____h813708[5] && + !_theResult____h813708[4] && + !_theResult____h813708[3] && + !_theResult____h813708[2] && + !_theResult____h813708[1] && + !_theResult____h813708[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13745) ? 11'd0 : - _theResult___fst_exp__h822012 ; - assign _theResult___fst_exp__h822021 = - (!_theResult____h813711[56] && _theResult____h813711[55]) ? + _theResult___fst_exp__h822009 ; + assign _theResult___fst_exp__h822018 = + (!_theResult____h813708[56] && _theResult____h813708[55]) ? 11'd1 : - _theResult___fst_exp__h822018 ; - assign _theResult___fst_exp__h822776 = + _theResult___fst_exp__h822015 ; + assign _theResult___fst_exp__h822773 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 : + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 ; - assign _theResult___fst_exp__h822779 = - (_theResult___fst_exp__h821947 == 11'd2047) ? - _theResult___fst_exp__h821947 : - _theResult___fst_exp__h822776 ; - assign _theResult___fst_exp__h830732 = + assign _theResult___fst_exp__h822776 = + (_theResult___fst_exp__h821944 == 11'd2047) ? + _theResult___fst_exp__h821944 : + _theResult___fst_exp__h822773 ; + assign _theResult___fst_exp__h830729 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] ; - assign _theResult___fst_exp__h830771 = + assign _theResult___fst_exp__h830768 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q165[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 } ; - assign _theResult___fst_exp__h830777 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___fst_exp__h830774 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13795) ? 11'd0 : - _theResult___fst_exp__h830771 ; - assign _theResult___fst_exp__h830780 = - (f3_exp__h793123 == 8'd0) ? - _theResult___fst_exp__h830777 : - _theResult___fst_exp__h830732 ; - assign _theResult___fst_exp__h831560 = + _theResult___fst_exp__h830768 ; + assign _theResult___fst_exp__h830777 = + (f3_exp__h793120 == 8'd0) ? + _theResult___fst_exp__h830774 : + _theResult___fst_exp__h830729 ; + assign _theResult___fst_exp__h831557 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 : + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 ; - assign _theResult___fst_exp__h831563 = - (_theResult___fst_exp__h830780 == 11'd2047) ? - _theResult___fst_exp__h830780 : - _theResult___fst_exp__h831560 ; - assign _theResult___fst_exp__h831572 = - (f3_exp__h793123 == 8'd0) ? + assign _theResult___fst_exp__h831560 = + (_theResult___fst_exp__h830777 == 11'd2047) ? + _theResult___fst_exp__h830777 : + _theResult___fst_exp__h831557 ; + assign _theResult___fst_exp__h831569 = + (f3_exp__h793120 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? - _theResult___snd_fst_exp__h813131 : - _theResult___fst_exp__h797297) : + _theResult___snd_fst_exp__h813128 : + _theResult___fst_exp__h797294) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? - _theResult___snd_fst_exp__h831566 : - _theResult___fst_exp__h797297) ; - assign _theResult___fst_exp__h831575 = - (f3_exp__h793123 == 8'd0 && f3_sfd__h793124 == 23'd0) ? + _theResult___snd_fst_exp__h831563 : + _theResult___fst_exp__h797294) ; + assign _theResult___fst_exp__h831572 = + (f3_exp__h793120 == 8'd0 && f3_sfd__h793121 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h831572 ; - assign _theResult___fst_sfd__h585090 = - (_theResult___fst_exp__h584492 == 8'd255) ? - sfdin__h584486[56:34] : - _theResult___fst_sfd__h585087 ; - assign _theResult___fst_sfd__h593672 = - (_theResult___fst_exp__h593148 == 8'd255) ? - _theResult___snd__h593099[56:34] : - _theResult___fst_sfd__h593669 ; - assign _theResult___fst_sfd__h602856 = - (_theResult___fst_exp__h602258 == 8'd255) ? - sfdin__h602252[56:34] : - _theResult___fst_sfd__h602853 ; - assign _theResult___fst_sfd__h611492 = - (_theResult___fst_exp__h610943 == 8'd255) ? - _theResult___snd__h610889[56:34] : - _theResult___fst_sfd__h611489 ; - assign _theResult___fst_sfd__h611501 = + _theResult___fst_exp__h831569 ; + assign _theResult___fst_sfd__h585087 = + (_theResult___fst_exp__h584489 == 8'd255) ? + sfdin__h584483[56:34] : + _theResult___fst_sfd__h585084 ; + assign _theResult___fst_sfd__h593669 = + (_theResult___fst_exp__h593145 == 8'd255) ? + _theResult___snd__h593096[56:34] : + _theResult___fst_sfd__h593666 ; + assign _theResult___fst_sfd__h602853 = + (_theResult___fst_exp__h602255 == 8'd255) ? + sfdin__h602249[56:34] : + _theResult___fst_sfd__h602850 ; + assign _theResult___fst_sfd__h611489 = + (_theResult___fst_exp__h610940 == 8'd255) ? + _theResult___snd__h610886[56:34] : + _theResult___fst_sfd__h611486 ; + assign _theResult___fst_sfd__h611498 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8117 ? - _theResult___snd_fst_sfd__h593675 : - _theResult___fst_sfd__h576364) : + _theResult___snd_fst_sfd__h593672 : + _theResult___fst_sfd__h576361) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8657 ? - _theResult___snd_fst_sfd__h611495 : - _theResult___fst_sfd__h576364) ; - assign _theResult___fst_sfd__h611507 = + _theResult___snd_fst_sfd__h611492 : + _theResult___fst_sfd__h576361) ; + assign _theResult___fst_sfd__h611504 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -30898,33 +30898,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h611501 ; - assign _theResult___fst_sfd__h630839 = - (_theResult___fst_exp__h630241 == 8'd255) ? - sfdin__h630235[56:34] : - _theResult___fst_sfd__h630836 ; - assign _theResult___fst_sfd__h639421 = - (_theResult___fst_exp__h638897 == 8'd255) ? - _theResult___snd__h638848[56:34] : - _theResult___fst_sfd__h639418 ; - assign _theResult___fst_sfd__h648605 = - (_theResult___fst_exp__h648007 == 8'd255) ? - sfdin__h648001[56:34] : - _theResult___fst_sfd__h648602 ; - assign _theResult___fst_sfd__h657241 = - (_theResult___fst_exp__h656692 == 8'd255) ? - _theResult___snd__h656638[56:34] : - _theResult___fst_sfd__h657238 ; - assign _theResult___fst_sfd__h657250 = + _theResult___fst_sfd__h611498 ; + assign _theResult___fst_sfd__h630836 = + (_theResult___fst_exp__h630238 == 8'd255) ? + sfdin__h630232[56:34] : + _theResult___fst_sfd__h630833 ; + assign _theResult___fst_sfd__h639418 = + (_theResult___fst_exp__h638894 == 8'd255) ? + _theResult___snd__h638845[56:34] : + _theResult___fst_sfd__h639415 ; + assign _theResult___fst_sfd__h648602 = + (_theResult___fst_exp__h648004 == 8'd255) ? + sfdin__h647998[56:34] : + _theResult___fst_sfd__h648599 ; + assign _theResult___fst_sfd__h657238 = + (_theResult___fst_exp__h656689 == 8'd255) ? + _theResult___snd__h656635[56:34] : + _theResult___fst_sfd__h657235 ; + assign _theResult___fst_sfd__h657247 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9514 ? - _theResult___snd_fst_sfd__h639424 : - _theResult___fst_sfd__h622115) : + _theResult___snd_fst_sfd__h639421 : + _theResult___fst_sfd__h622112) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10054 ? - _theResult___snd_fst_sfd__h657244 : - _theResult___fst_sfd__h622115) ; - assign _theResult___fst_sfd__h657256 = + _theResult___snd_fst_sfd__h657241 : + _theResult___fst_sfd__h622112) ; + assign _theResult___fst_sfd__h657253 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -30932,33 +30932,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h657250 ; - assign _theResult___fst_sfd__h676586 = - (_theResult___fst_exp__h675988 == 8'd255) ? - sfdin__h675982[56:34] : - _theResult___fst_sfd__h676583 ; - assign _theResult___fst_sfd__h685168 = - (_theResult___fst_exp__h684644 == 8'd255) ? - _theResult___snd__h684595[56:34] : - _theResult___fst_sfd__h685165 ; - assign _theResult___fst_sfd__h694352 = - (_theResult___fst_exp__h693754 == 8'd255) ? - sfdin__h693748[56:34] : - _theResult___fst_sfd__h694349 ; - assign _theResult___fst_sfd__h702988 = - (_theResult___fst_exp__h702439 == 8'd255) ? - _theResult___snd__h702385[56:34] : - _theResult___fst_sfd__h702985 ; - assign _theResult___fst_sfd__h702997 = + _theResult___fst_sfd__h657247 ; + assign _theResult___fst_sfd__h676583 = + (_theResult___fst_exp__h675985 == 8'd255) ? + sfdin__h675979[56:34] : + _theResult___fst_sfd__h676580 ; + assign _theResult___fst_sfd__h685165 = + (_theResult___fst_exp__h684641 == 8'd255) ? + _theResult___snd__h684592[56:34] : + _theResult___fst_sfd__h685162 ; + assign _theResult___fst_sfd__h694349 = + (_theResult___fst_exp__h693751 == 8'd255) ? + sfdin__h693745[56:34] : + _theResult___fst_sfd__h694346 ; + assign _theResult___fst_sfd__h702985 = + (_theResult___fst_exp__h702436 == 8'd255) ? + _theResult___snd__h702382[56:34] : + _theResult___fst_sfd__h702982 ; + assign _theResult___fst_sfd__h702994 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10911 ? - _theResult___snd_fst_sfd__h685171 : - _theResult___fst_sfd__h667862) : + _theResult___snd_fst_sfd__h685168 : + _theResult___fst_sfd__h667859) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11451 ? - _theResult___snd_fst_sfd__h702991 : - _theResult___fst_sfd__h667862) ; - assign _theResult___fst_sfd__h703003 = + _theResult___snd_fst_sfd__h702988 : + _theResult___fst_sfd__h667859) ; + assign _theResult___fst_sfd__h703000 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -30966,1426 +30966,1426 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h702997 ; - assign _theResult___fst_sfd__h719141 = + _theResult___fst_sfd__h702994 ; + assign _theResult___fst_sfd__h719138 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 ; - assign _theResult___fst_sfd__h734969 = + assign _theResult___fst_sfd__h734966 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 : + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 ; - assign _theResult___fst_sfd__h734972 = - (_theResult___fst_exp__h734213 == 11'd2047) ? - _theResult___snd__h734164[56:5] : - _theResult___fst_sfd__h734969 ; - assign _theResult___fst_sfd__h744620 = + assign _theResult___fst_sfd__h734969 = + (_theResult___fst_exp__h734210 == 11'd2047) ? + _theResult___snd__h734161[56:5] : + _theResult___fst_sfd__h734966 ; + assign _theResult___fst_sfd__h744617 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 : + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 ; - assign _theResult___fst_sfd__h744623 = - (_theResult___fst_exp__h743790 == 11'd2047) ? - sfdin__h743784[56:5] : - _theResult___fst_sfd__h744620 ; - assign _theResult___fst_sfd__h753404 = + assign _theResult___fst_sfd__h744620 = + (_theResult___fst_exp__h743787 == 11'd2047) ? + sfdin__h743781[56:5] : + _theResult___fst_sfd__h744617 ; + assign _theResult___fst_sfd__h753401 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 : + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 ; - assign _theResult___fst_sfd__h753407 = - (_theResult___fst_exp__h752623 == 11'd2047) ? - _theResult___snd__h752569[56:5] : - _theResult___fst_sfd__h753404 ; - assign _theResult___fst_sfd__h753416 = - (f1_exp__h714825 == 8'd0) ? + assign _theResult___fst_sfd__h753404 = + (_theResult___fst_exp__h752620 == 11'd2047) ? + _theResult___snd__h752566[56:5] : + _theResult___fst_sfd__h753401 ; + assign _theResult___fst_sfd__h753413 = + (f1_exp__h714822 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12643 ? - _theResult___snd_fst_sfd__h734975 : - _theResult___fst_sfd__h719141) : + _theResult___snd_fst_sfd__h734972 : + _theResult___fst_sfd__h719138) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12780 ? - _theResult___snd_fst_sfd__h753410 : - _theResult___fst_sfd__h719141) ; - assign _theResult___fst_sfd__h753422 = - ((f1_exp__h714825 == 8'd255 || f1_exp__h714825 == 8'd0) && - f1_sfd__h714826 == 23'd0) ? + _theResult___snd_fst_sfd__h753407 : + _theResult___fst_sfd__h719138) ; + assign _theResult___fst_sfd__h753419 = + ((f1_exp__h714822 == 8'd255 || f1_exp__h714822 == 8'd0) && + f1_sfd__h714823 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h753416 ; - assign _theResult___fst_sfd__h757994 = + _theResult___fst_sfd__h753413 ; + assign _theResult___fst_sfd__h757991 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 ; - assign _theResult___fst_sfd__h773822 = + assign _theResult___fst_sfd__h773819 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 : + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 ; - assign _theResult___fst_sfd__h773825 = - (_theResult___fst_exp__h773066 == 11'd2047) ? - _theResult___snd__h773017[56:5] : - _theResult___fst_sfd__h773822 ; - assign _theResult___fst_sfd__h783473 = + assign _theResult___fst_sfd__h773822 = + (_theResult___fst_exp__h773063 == 11'd2047) ? + _theResult___snd__h773014[56:5] : + _theResult___fst_sfd__h773819 ; + assign _theResult___fst_sfd__h783470 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 : + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 ; - assign _theResult___fst_sfd__h783476 = - (_theResult___fst_exp__h782643 == 11'd2047) ? - sfdin__h782637[56:5] : - _theResult___fst_sfd__h783473 ; - assign _theResult___fst_sfd__h792257 = + assign _theResult___fst_sfd__h783473 = + (_theResult___fst_exp__h782640 == 11'd2047) ? + sfdin__h782634[56:5] : + _theResult___fst_sfd__h783470 ; + assign _theResult___fst_sfd__h792254 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 : + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 ; - assign _theResult___fst_sfd__h792260 = - (_theResult___fst_exp__h791476 == 11'd2047) ? - _theResult___snd__h791422[56:5] : - _theResult___fst_sfd__h792257 ; - assign _theResult___fst_sfd__h792269 = - (f2_exp__h753819 == 8'd0) ? + assign _theResult___fst_sfd__h792257 = + (_theResult___fst_exp__h791473 == 11'd2047) ? + _theResult___snd__h791419[56:5] : + _theResult___fst_sfd__h792254 ; + assign _theResult___fst_sfd__h792266 = + (f2_exp__h753816 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14143 ? - _theResult___snd_fst_sfd__h773828 : - _theResult___fst_sfd__h757994) : + _theResult___snd_fst_sfd__h773825 : + _theResult___fst_sfd__h757991) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14265 ? - _theResult___snd_fst_sfd__h792263 : - _theResult___fst_sfd__h757994) ; - assign _theResult___fst_sfd__h792275 = - ((f2_exp__h753819 == 8'd255 || f2_exp__h753819 == 8'd0) && - f2_sfd__h753820 == 23'd0) ? + _theResult___snd_fst_sfd__h792260 : + _theResult___fst_sfd__h757991) ; + assign _theResult___fst_sfd__h792272 = + ((f2_exp__h753816 == 8'd255 || f2_exp__h753816 == 8'd0) && + f2_sfd__h753817 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h792269 ; - assign _theResult___fst_sfd__h797298 = + _theResult___fst_sfd__h792266 ; + assign _theResult___fst_sfd__h797295 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 ; - assign _theResult___fst_sfd__h813126 = + assign _theResult___fst_sfd__h813123 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 : + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 ; - assign _theResult___fst_sfd__h813129 = - (_theResult___fst_exp__h812370 == 11'd2047) ? - _theResult___snd__h812321[56:5] : - _theResult___fst_sfd__h813126 ; - assign _theResult___fst_sfd__h822777 = + assign _theResult___fst_sfd__h813126 = + (_theResult___fst_exp__h812367 == 11'd2047) ? + _theResult___snd__h812318[56:5] : + _theResult___fst_sfd__h813123 ; + assign _theResult___fst_sfd__h822774 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 : + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 ; - assign _theResult___fst_sfd__h822780 = - (_theResult___fst_exp__h821947 == 11'd2047) ? - sfdin__h821941[56:5] : - _theResult___fst_sfd__h822777 ; - assign _theResult___fst_sfd__h831561 = + assign _theResult___fst_sfd__h822777 = + (_theResult___fst_exp__h821944 == 11'd2047) ? + sfdin__h821938[56:5] : + _theResult___fst_sfd__h822774 ; + assign _theResult___fst_sfd__h831558 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 : + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 ; - assign _theResult___fst_sfd__h831564 = - (_theResult___fst_exp__h830780 == 11'd2047) ? - _theResult___snd__h830726[56:5] : - _theResult___fst_sfd__h831561 ; - assign _theResult___fst_sfd__h831573 = - (f3_exp__h793123 == 8'd0) ? + assign _theResult___fst_sfd__h831561 = + (_theResult___fst_exp__h830777 == 11'd2047) ? + _theResult___snd__h830723[56:5] : + _theResult___fst_sfd__h831558 ; + assign _theResult___fst_sfd__h831570 = + (f3_exp__h793120 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13373 ? - _theResult___snd_fst_sfd__h813132 : - _theResult___fst_sfd__h797298) : + _theResult___snd_fst_sfd__h813129 : + _theResult___fst_sfd__h797295) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13495 ? - _theResult___snd_fst_sfd__h831567 : - _theResult___fst_sfd__h797298) ; - assign _theResult___fst_sfd__h831579 = - ((f3_exp__h793123 == 8'd255 || f3_exp__h793123 == 8'd0) && - f3_sfd__h793124 == 23'd0) ? + _theResult___snd_fst_sfd__h831564 : + _theResult___fst_sfd__h797295) ; + assign _theResult___fst_sfd__h831576 = + ((f3_exp__h793120 == 8'd255 || f3_exp__h793120 == 8'd0) && + f3_sfd__h793121 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h831573 ; - assign _theResult___sfd__h585009 = - sfd__h584584[24] ? - ((_theResult___fst_exp__h584492 == 8'd254) ? + _theResult___fst_sfd__h831570 ; + assign _theResult___sfd__h585006 = + sfd__h584581[24] ? + ((_theResult___fst_exp__h584489 == 8'd254) ? 23'd0 : - sfd__h584584[23:1]) : - sfd__h584584[22:0] ; - assign _theResult___sfd__h593591 = - sfd__h593166[24] ? - ((_theResult___fst_exp__h593148 == 8'd254) ? + sfd__h584581[23:1]) : + sfd__h584581[22:0] ; + assign _theResult___sfd__h593588 = + sfd__h593163[24] ? + ((_theResult___fst_exp__h593145 == 8'd254) ? 23'd0 : - sfd__h593166[23:1]) : - sfd__h593166[22:0] ; - assign _theResult___sfd__h602775 = - sfd__h602350[24] ? - ((_theResult___fst_exp__h602258 == 8'd254) ? + sfd__h593163[23:1]) : + sfd__h593163[22:0] ; + assign _theResult___sfd__h602772 = + sfd__h602347[24] ? + ((_theResult___fst_exp__h602255 == 8'd254) ? 23'd0 : - sfd__h602350[23:1]) : - sfd__h602350[22:0] ; - assign _theResult___sfd__h611411 = - sfd__h610962[24] ? - ((_theResult___fst_exp__h610943 == 8'd254) ? + sfd__h602347[23:1]) : + sfd__h602347[22:0] ; + assign _theResult___sfd__h611408 = + sfd__h610959[24] ? + ((_theResult___fst_exp__h610940 == 8'd254) ? 23'd0 : - sfd__h610962[23:1]) : - sfd__h610962[22:0] ; - assign _theResult___sfd__h611513 = + sfd__h610959[23:1]) : + sfd__h610959[22:0] ; + assign _theResult___sfd__h611510 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h568726 : - _theResult___fst_sfd__h611507 ; - assign _theResult___sfd__h630758 = - sfd__h630333[24] ? - ((_theResult___fst_exp__h630241 == 8'd254) ? + _theResult___snd_fst_sfd__h568723 : + _theResult___fst_sfd__h611504 ; + assign _theResult___sfd__h630755 = + sfd__h630330[24] ? + ((_theResult___fst_exp__h630238 == 8'd254) ? 23'd0 : - sfd__h630333[23:1]) : - sfd__h630333[22:0] ; - assign _theResult___sfd__h639340 = - sfd__h638915[24] ? - ((_theResult___fst_exp__h638897 == 8'd254) ? + sfd__h630330[23:1]) : + sfd__h630330[22:0] ; + assign _theResult___sfd__h639337 = + sfd__h638912[24] ? + ((_theResult___fst_exp__h638894 == 8'd254) ? 23'd0 : - sfd__h638915[23:1]) : - sfd__h638915[22:0] ; - assign _theResult___sfd__h648524 = - sfd__h648099[24] ? - ((_theResult___fst_exp__h648007 == 8'd254) ? + sfd__h638912[23:1]) : + sfd__h638912[22:0] ; + assign _theResult___sfd__h648521 = + sfd__h648096[24] ? + ((_theResult___fst_exp__h648004 == 8'd254) ? 23'd0 : - sfd__h648099[23:1]) : - sfd__h648099[22:0] ; - assign _theResult___sfd__h657160 = - sfd__h656711[24] ? - ((_theResult___fst_exp__h656692 == 8'd254) ? + sfd__h648096[23:1]) : + sfd__h648096[22:0] ; + assign _theResult___sfd__h657157 = + sfd__h656708[24] ? + ((_theResult___fst_exp__h656689 == 8'd254) ? 23'd0 : - sfd__h656711[23:1]) : - sfd__h656711[22:0] ; - assign _theResult___sfd__h657262 = + sfd__h656708[23:1]) : + sfd__h656708[22:0] ; + assign _theResult___sfd__h657259 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h614480 : - _theResult___fst_sfd__h657256 ; - assign _theResult___sfd__h676505 = - sfd__h676080[24] ? - ((_theResult___fst_exp__h675988 == 8'd254) ? + _theResult___snd_fst_sfd__h614477 : + _theResult___fst_sfd__h657253 ; + assign _theResult___sfd__h676502 = + sfd__h676077[24] ? + ((_theResult___fst_exp__h675985 == 8'd254) ? 23'd0 : - sfd__h676080[23:1]) : - sfd__h676080[22:0] ; - assign _theResult___sfd__h685087 = - sfd__h684662[24] ? - ((_theResult___fst_exp__h684644 == 8'd254) ? + sfd__h676077[23:1]) : + sfd__h676077[22:0] ; + assign _theResult___sfd__h685084 = + sfd__h684659[24] ? + ((_theResult___fst_exp__h684641 == 8'd254) ? 23'd0 : - sfd__h684662[23:1]) : - sfd__h684662[22:0] ; - assign _theResult___sfd__h694271 = - sfd__h693846[24] ? - ((_theResult___fst_exp__h693754 == 8'd254) ? + sfd__h684659[23:1]) : + sfd__h684659[22:0] ; + assign _theResult___sfd__h694268 = + sfd__h693843[24] ? + ((_theResult___fst_exp__h693751 == 8'd254) ? 23'd0 : - sfd__h693846[23:1]) : - sfd__h693846[22:0] ; - assign _theResult___sfd__h702907 = - sfd__h702458[24] ? - ((_theResult___fst_exp__h702439 == 8'd254) ? + sfd__h693843[23:1]) : + sfd__h693843[22:0] ; + assign _theResult___sfd__h702904 = + sfd__h702455[24] ? + ((_theResult___fst_exp__h702436 == 8'd254) ? 23'd0 : - sfd__h702458[23:1]) : - sfd__h702458[22:0] ; - assign _theResult___sfd__h703009 = + sfd__h702455[23:1]) : + sfd__h702455[22:0] ; + assign _theResult___sfd__h703006 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h660227 : - _theResult___fst_sfd__h703003 ; - assign _theResult___sfd__h734869 = - sfd__h734231[53] ? - ((_theResult___fst_exp__h734213 == 11'd2046) ? + _theResult___snd_fst_sfd__h660224 : + _theResult___fst_sfd__h703000 ; + assign _theResult___sfd__h734866 = + sfd__h734228[53] ? + ((_theResult___fst_exp__h734210 == 11'd2046) ? 52'd0 : - sfd__h734231[52:1]) : - sfd__h734231[51:0] ; - assign _theResult___sfd__h744520 = - sfd__h743882[53] ? - ((_theResult___fst_exp__h743790 == 11'd2046) ? + sfd__h734228[52:1]) : + sfd__h734228[51:0] ; + assign _theResult___sfd__h744517 = + sfd__h743879[53] ? + ((_theResult___fst_exp__h743787 == 11'd2046) ? 52'd0 : - sfd__h743882[52:1]) : - sfd__h743882[51:0] ; - assign _theResult___sfd__h753304 = - sfd__h752642[53] ? - ((_theResult___fst_exp__h752623 == 11'd2046) ? + sfd__h743879[52:1]) : + sfd__h743879[51:0] ; + assign _theResult___sfd__h753301 = + sfd__h752639[53] ? + ((_theResult___fst_exp__h752620 == 11'd2046) ? 52'd0 : - sfd__h752642[52:1]) : - sfd__h752642[51:0] ; - assign _theResult___sfd__h773722 = - sfd__h773084[53] ? - ((_theResult___fst_exp__h773066 == 11'd2046) ? + sfd__h752639[52:1]) : + sfd__h752639[51:0] ; + assign _theResult___sfd__h773719 = + sfd__h773081[53] ? + ((_theResult___fst_exp__h773063 == 11'd2046) ? 52'd0 : - sfd__h773084[52:1]) : - sfd__h773084[51:0] ; - assign _theResult___sfd__h783373 = - sfd__h782735[53] ? - ((_theResult___fst_exp__h782643 == 11'd2046) ? + sfd__h773081[52:1]) : + sfd__h773081[51:0] ; + assign _theResult___sfd__h783370 = + sfd__h782732[53] ? + ((_theResult___fst_exp__h782640 == 11'd2046) ? 52'd0 : - sfd__h782735[52:1]) : - sfd__h782735[51:0] ; - assign _theResult___sfd__h792157 = - sfd__h791495[53] ? - ((_theResult___fst_exp__h791476 == 11'd2046) ? + sfd__h782732[52:1]) : + sfd__h782732[51:0] ; + assign _theResult___sfd__h792154 = + sfd__h791492[53] ? + ((_theResult___fst_exp__h791473 == 11'd2046) ? 52'd0 : - sfd__h791495[52:1]) : - sfd__h791495[51:0] ; - assign _theResult___sfd__h813026 = - sfd__h812388[53] ? - ((_theResult___fst_exp__h812370 == 11'd2046) ? + sfd__h791492[52:1]) : + sfd__h791492[51:0] ; + assign _theResult___sfd__h813023 = + sfd__h812385[53] ? + ((_theResult___fst_exp__h812367 == 11'd2046) ? 52'd0 : - sfd__h812388[52:1]) : - sfd__h812388[51:0] ; - assign _theResult___sfd__h822677 = - sfd__h822039[53] ? - ((_theResult___fst_exp__h821947 == 11'd2046) ? + sfd__h812385[52:1]) : + sfd__h812385[51:0] ; + assign _theResult___sfd__h822674 = + sfd__h822036[53] ? + ((_theResult___fst_exp__h821944 == 11'd2046) ? 52'd0 : - sfd__h822039[52:1]) : - sfd__h822039[51:0] ; - assign _theResult___sfd__h831461 = - sfd__h830799[53] ? - ((_theResult___fst_exp__h830780 == 11'd2046) ? + sfd__h822036[52:1]) : + sfd__h822036[51:0] ; + assign _theResult___sfd__h831458 = + sfd__h830796[53] ? + ((_theResult___fst_exp__h830777 == 11'd2046) ? 52'd0 : - sfd__h830799[52:1]) : - sfd__h830799[51:0] ; - assign _theResult___snd__h584503 = { _theResult____h576381[55:0], 1'd0 } ; - assign _theResult___snd__h584514 = - (!_theResult____h576381[56] && _theResult____h576381[55]) ? - _theResult___snd__h584516 : - _theResult___snd__h584526 ; - assign _theResult___snd__h584516 = { _theResult____h576381[54:0], 2'd0 } ; - assign _theResult___snd__h584526 = - (!_theResult____h576381[56] && !_theResult____h576381[55] && - !_theResult____h576381[54] && - !_theResult____h576381[53] && - !_theResult____h576381[52] && - !_theResult____h576381[51] && - !_theResult____h576381[50] && - !_theResult____h576381[49] && - !_theResult____h576381[48] && - !_theResult____h576381[47] && - !_theResult____h576381[46] && - !_theResult____h576381[45] && - !_theResult____h576381[44] && - !_theResult____h576381[43] && - !_theResult____h576381[42] && - !_theResult____h576381[41] && - !_theResult____h576381[40] && - !_theResult____h576381[39] && - !_theResult____h576381[38] && - !_theResult____h576381[37] && - !_theResult____h576381[36] && - !_theResult____h576381[35] && - !_theResult____h576381[34] && - !_theResult____h576381[33] && - !_theResult____h576381[32] && - !_theResult____h576381[31] && - !_theResult____h576381[30] && - !_theResult____h576381[29] && - !_theResult____h576381[28] && - !_theResult____h576381[27] && - !_theResult____h576381[26] && - !_theResult____h576381[25] && - !_theResult____h576381[24] && - !_theResult____h576381[23] && - !_theResult____h576381[22] && - !_theResult____h576381[21] && - !_theResult____h576381[20] && - !_theResult____h576381[19] && - !_theResult____h576381[18] && - !_theResult____h576381[17] && - !_theResult____h576381[16] && - !_theResult____h576381[15] && - !_theResult____h576381[14] && - !_theResult____h576381[13] && - !_theResult____h576381[12] && - !_theResult____h576381[11] && - !_theResult____h576381[10] && - !_theResult____h576381[9] && - !_theResult____h576381[8] && - !_theResult____h576381[7] && - !_theResult____h576381[6] && - !_theResult____h576381[5] && - !_theResult____h576381[4] && - !_theResult____h576381[3] && - !_theResult____h576381[2] && - !_theResult____h576381[1] && - !_theResult____h576381[0]) ? - _theResult____h576381 : - _theResult___snd__h584532 ; - assign _theResult___snd__h584532 = + sfd__h830796[52:1]) : + sfd__h830796[51:0] ; + assign _theResult___snd__h584500 = { _theResult____h576378[55:0], 1'd0 } ; + assign _theResult___snd__h584511 = + (!_theResult____h576378[56] && _theResult____h576378[55]) ? + _theResult___snd__h584513 : + _theResult___snd__h584523 ; + assign _theResult___snd__h584513 = { _theResult____h576378[54:0], 2'd0 } ; + assign _theResult___snd__h584523 = + (!_theResult____h576378[56] && !_theResult____h576378[55] && + !_theResult____h576378[54] && + !_theResult____h576378[53] && + !_theResult____h576378[52] && + !_theResult____h576378[51] && + !_theResult____h576378[50] && + !_theResult____h576378[49] && + !_theResult____h576378[48] && + !_theResult____h576378[47] && + !_theResult____h576378[46] && + !_theResult____h576378[45] && + !_theResult____h576378[44] && + !_theResult____h576378[43] && + !_theResult____h576378[42] && + !_theResult____h576378[41] && + !_theResult____h576378[40] && + !_theResult____h576378[39] && + !_theResult____h576378[38] && + !_theResult____h576378[37] && + !_theResult____h576378[36] && + !_theResult____h576378[35] && + !_theResult____h576378[34] && + !_theResult____h576378[33] && + !_theResult____h576378[32] && + !_theResult____h576378[31] && + !_theResult____h576378[30] && + !_theResult____h576378[29] && + !_theResult____h576378[28] && + !_theResult____h576378[27] && + !_theResult____h576378[26] && + !_theResult____h576378[25] && + !_theResult____h576378[24] && + !_theResult____h576378[23] && + !_theResult____h576378[22] && + !_theResult____h576378[21] && + !_theResult____h576378[20] && + !_theResult____h576378[19] && + !_theResult____h576378[18] && + !_theResult____h576378[17] && + !_theResult____h576378[16] && + !_theResult____h576378[15] && + !_theResult____h576378[14] && + !_theResult____h576378[13] && + !_theResult____h576378[12] && + !_theResult____h576378[11] && + !_theResult____h576378[10] && + !_theResult____h576378[9] && + !_theResult____h576378[8] && + !_theResult____h576378[7] && + !_theResult____h576378[6] && + !_theResult____h576378[5] && + !_theResult____h576378[4] && + !_theResult____h576378[3] && + !_theResult____h576378[2] && + !_theResult____h576378[1] && + !_theResult____h576378[0]) ? + _theResult____h576378 : + _theResult___snd__h584529 ; + assign _theResult___snd__h584529 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q39[54:0], 2'd0 } ; - assign _theResult___snd__h584555 = - _theResult____h576381 << + assign _theResult___snd__h584552 = + _theResult____h576378 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8352 ; - assign _theResult___snd__h593099 = + assign _theResult___snd__h593096 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h593108 : - _theResult___snd__h593101 ; - assign _theResult___snd__h593101 = + _theResult___snd__h593105 : + _theResult___snd__h593098 ; + assign _theResult___snd__h593098 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h593108 = + assign _theResult___snd__h593105 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528) ? - sfd__h568776 : - _theResult___snd__h593114 ; - assign _theResult___snd__h593114 = + sfd__h568773 : + _theResult___snd__h593111 ; + assign _theResult___snd__h593111 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q41[54:0], 2'd0 } ; - assign _theResult___snd__h593137 = - sfd__h568776 << + assign _theResult___snd__h593134 = + sfd__h568773 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8583 ; - assign _theResult___snd__h602269 = { _theResult____h594020[55:0], 1'd0 } ; - assign _theResult___snd__h602280 = - (!_theResult____h594020[56] && _theResult____h594020[55]) ? - _theResult___snd__h602282 : - _theResult___snd__h602292 ; - assign _theResult___snd__h602282 = { _theResult____h594020[54:0], 2'd0 } ; - assign _theResult___snd__h602292 = - (!_theResult____h594020[56] && !_theResult____h594020[55] && - !_theResult____h594020[54] && - !_theResult____h594020[53] && - !_theResult____h594020[52] && - !_theResult____h594020[51] && - !_theResult____h594020[50] && - !_theResult____h594020[49] && - !_theResult____h594020[48] && - !_theResult____h594020[47] && - !_theResult____h594020[46] && - !_theResult____h594020[45] && - !_theResult____h594020[44] && - !_theResult____h594020[43] && - !_theResult____h594020[42] && - !_theResult____h594020[41] && - !_theResult____h594020[40] && - !_theResult____h594020[39] && - !_theResult____h594020[38] && - !_theResult____h594020[37] && - !_theResult____h594020[36] && - !_theResult____h594020[35] && - !_theResult____h594020[34] && - !_theResult____h594020[33] && - !_theResult____h594020[32] && - !_theResult____h594020[31] && - !_theResult____h594020[30] && - !_theResult____h594020[29] && - !_theResult____h594020[28] && - !_theResult____h594020[27] && - !_theResult____h594020[26] && - !_theResult____h594020[25] && - !_theResult____h594020[24] && - !_theResult____h594020[23] && - !_theResult____h594020[22] && - !_theResult____h594020[21] && - !_theResult____h594020[20] && - !_theResult____h594020[19] && - !_theResult____h594020[18] && - !_theResult____h594020[17] && - !_theResult____h594020[16] && - !_theResult____h594020[15] && - !_theResult____h594020[14] && - !_theResult____h594020[13] && - !_theResult____h594020[12] && - !_theResult____h594020[11] && - !_theResult____h594020[10] && - !_theResult____h594020[9] && - !_theResult____h594020[8] && - !_theResult____h594020[7] && - !_theResult____h594020[6] && - !_theResult____h594020[5] && - !_theResult____h594020[4] && - !_theResult____h594020[3] && - !_theResult____h594020[2] && - !_theResult____h594020[1] && - !_theResult____h594020[0]) ? - _theResult____h594020 : - _theResult___snd__h602298 ; - assign _theResult___snd__h602298 = + assign _theResult___snd__h602266 = { _theResult____h594017[55:0], 1'd0 } ; + assign _theResult___snd__h602277 = + (!_theResult____h594017[56] && _theResult____h594017[55]) ? + _theResult___snd__h602279 : + _theResult___snd__h602289 ; + assign _theResult___snd__h602279 = { _theResult____h594017[54:0], 2'd0 } ; + assign _theResult___snd__h602289 = + (!_theResult____h594017[56] && !_theResult____h594017[55] && + !_theResult____h594017[54] && + !_theResult____h594017[53] && + !_theResult____h594017[52] && + !_theResult____h594017[51] && + !_theResult____h594017[50] && + !_theResult____h594017[49] && + !_theResult____h594017[48] && + !_theResult____h594017[47] && + !_theResult____h594017[46] && + !_theResult____h594017[45] && + !_theResult____h594017[44] && + !_theResult____h594017[43] && + !_theResult____h594017[42] && + !_theResult____h594017[41] && + !_theResult____h594017[40] && + !_theResult____h594017[39] && + !_theResult____h594017[38] && + !_theResult____h594017[37] && + !_theResult____h594017[36] && + !_theResult____h594017[35] && + !_theResult____h594017[34] && + !_theResult____h594017[33] && + !_theResult____h594017[32] && + !_theResult____h594017[31] && + !_theResult____h594017[30] && + !_theResult____h594017[29] && + !_theResult____h594017[28] && + !_theResult____h594017[27] && + !_theResult____h594017[26] && + !_theResult____h594017[25] && + !_theResult____h594017[24] && + !_theResult____h594017[23] && + !_theResult____h594017[22] && + !_theResult____h594017[21] && + !_theResult____h594017[20] && + !_theResult____h594017[19] && + !_theResult____h594017[18] && + !_theResult____h594017[17] && + !_theResult____h594017[16] && + !_theResult____h594017[15] && + !_theResult____h594017[14] && + !_theResult____h594017[13] && + !_theResult____h594017[12] && + !_theResult____h594017[11] && + !_theResult____h594017[10] && + !_theResult____h594017[9] && + !_theResult____h594017[8] && + !_theResult____h594017[7] && + !_theResult____h594017[6] && + !_theResult____h594017[5] && + !_theResult____h594017[4] && + !_theResult____h594017[3] && + !_theResult____h594017[2] && + !_theResult____h594017[1] && + !_theResult____h594017[0]) ? + _theResult____h594017 : + _theResult___snd__h602295 ; + assign _theResult___snd__h602295 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q49[54:0], 2'd0 } ; - assign _theResult___snd__h602321 = - _theResult____h594020 << + assign _theResult___snd__h602318 = + _theResult____h594017 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8903 ; - assign _theResult___snd__h610889 = + assign _theResult___snd__h610886 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h610903 : - _theResult___snd__h593101 ; - assign _theResult___snd__h610903 = + _theResult___snd__h610900 : + _theResult___snd__h593098 ; + assign _theResult___snd__h610900 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8528) ? - sfd__h568776 : - _theResult___snd__h610909 ; - assign _theResult___snd__h610909 = + sfd__h568773 : + _theResult___snd__h610906 ; + assign _theResult___snd__h610906 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q54[54:0], 2'd0 } ; - assign _theResult___snd__h610927 = - sfd__h568776 << + assign _theResult___snd__h610924 = + sfd__h568773 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8977) ; - assign _theResult___snd__h630252 = { _theResult____h622132[55:0], 1'd0 } ; - assign _theResult___snd__h630263 = - (!_theResult____h622132[56] && _theResult____h622132[55]) ? - _theResult___snd__h630265 : - _theResult___snd__h630275 ; - assign _theResult___snd__h630265 = { _theResult____h622132[54:0], 2'd0 } ; - assign _theResult___snd__h630275 = - (!_theResult____h622132[56] && !_theResult____h622132[55] && - !_theResult____h622132[54] && - !_theResult____h622132[53] && - !_theResult____h622132[52] && - !_theResult____h622132[51] && - !_theResult____h622132[50] && - !_theResult____h622132[49] && - !_theResult____h622132[48] && - !_theResult____h622132[47] && - !_theResult____h622132[46] && - !_theResult____h622132[45] && - !_theResult____h622132[44] && - !_theResult____h622132[43] && - !_theResult____h622132[42] && - !_theResult____h622132[41] && - !_theResult____h622132[40] && - !_theResult____h622132[39] && - !_theResult____h622132[38] && - !_theResult____h622132[37] && - !_theResult____h622132[36] && - !_theResult____h622132[35] && - !_theResult____h622132[34] && - !_theResult____h622132[33] && - !_theResult____h622132[32] && - !_theResult____h622132[31] && - !_theResult____h622132[30] && - !_theResult____h622132[29] && - !_theResult____h622132[28] && - !_theResult____h622132[27] && - !_theResult____h622132[26] && - !_theResult____h622132[25] && - !_theResult____h622132[24] && - !_theResult____h622132[23] && - !_theResult____h622132[22] && - !_theResult____h622132[21] && - !_theResult____h622132[20] && - !_theResult____h622132[19] && - !_theResult____h622132[18] && - !_theResult____h622132[17] && - !_theResult____h622132[16] && - !_theResult____h622132[15] && - !_theResult____h622132[14] && - !_theResult____h622132[13] && - !_theResult____h622132[12] && - !_theResult____h622132[11] && - !_theResult____h622132[10] && - !_theResult____h622132[9] && - !_theResult____h622132[8] && - !_theResult____h622132[7] && - !_theResult____h622132[6] && - !_theResult____h622132[5] && - !_theResult____h622132[4] && - !_theResult____h622132[3] && - !_theResult____h622132[2] && - !_theResult____h622132[1] && - !_theResult____h622132[0]) ? - _theResult____h622132 : - _theResult___snd__h630281 ; - assign _theResult___snd__h630281 = + assign _theResult___snd__h630249 = { _theResult____h622129[55:0], 1'd0 } ; + assign _theResult___snd__h630260 = + (!_theResult____h622129[56] && _theResult____h622129[55]) ? + _theResult___snd__h630262 : + _theResult___snd__h630272 ; + assign _theResult___snd__h630262 = { _theResult____h622129[54:0], 2'd0 } ; + assign _theResult___snd__h630272 = + (!_theResult____h622129[56] && !_theResult____h622129[55] && + !_theResult____h622129[54] && + !_theResult____h622129[53] && + !_theResult____h622129[52] && + !_theResult____h622129[51] && + !_theResult____h622129[50] && + !_theResult____h622129[49] && + !_theResult____h622129[48] && + !_theResult____h622129[47] && + !_theResult____h622129[46] && + !_theResult____h622129[45] && + !_theResult____h622129[44] && + !_theResult____h622129[43] && + !_theResult____h622129[42] && + !_theResult____h622129[41] && + !_theResult____h622129[40] && + !_theResult____h622129[39] && + !_theResult____h622129[38] && + !_theResult____h622129[37] && + !_theResult____h622129[36] && + !_theResult____h622129[35] && + !_theResult____h622129[34] && + !_theResult____h622129[33] && + !_theResult____h622129[32] && + !_theResult____h622129[31] && + !_theResult____h622129[30] && + !_theResult____h622129[29] && + !_theResult____h622129[28] && + !_theResult____h622129[27] && + !_theResult____h622129[26] && + !_theResult____h622129[25] && + !_theResult____h622129[24] && + !_theResult____h622129[23] && + !_theResult____h622129[22] && + !_theResult____h622129[21] && + !_theResult____h622129[20] && + !_theResult____h622129[19] && + !_theResult____h622129[18] && + !_theResult____h622129[17] && + !_theResult____h622129[16] && + !_theResult____h622129[15] && + !_theResult____h622129[14] && + !_theResult____h622129[13] && + !_theResult____h622129[12] && + !_theResult____h622129[11] && + !_theResult____h622129[10] && + !_theResult____h622129[9] && + !_theResult____h622129[8] && + !_theResult____h622129[7] && + !_theResult____h622129[6] && + !_theResult____h622129[5] && + !_theResult____h622129[4] && + !_theResult____h622129[3] && + !_theResult____h622129[2] && + !_theResult____h622129[1] && + !_theResult____h622129[0]) ? + _theResult____h622129 : + _theResult___snd__h630278 ; + assign _theResult___snd__h630278 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q74[54:0], 2'd0 } ; - assign _theResult___snd__h630304 = - _theResult____h622132 << + assign _theResult___snd__h630301 = + _theResult____h622129 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9749 ; - assign _theResult___snd__h638848 = + assign _theResult___snd__h638845 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h638857 : - _theResult___snd__h638850 ; - assign _theResult___snd__h638850 = + _theResult___snd__h638854 : + _theResult___snd__h638847 ; + assign _theResult___snd__h638847 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h638857 = + assign _theResult___snd__h638854 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925) ? - sfd__h614530 : - _theResult___snd__h638863 ; - assign _theResult___snd__h638863 = + sfd__h614527 : + _theResult___snd__h638860 ; + assign _theResult___snd__h638860 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q76[54:0], 2'd0 } ; - assign _theResult___snd__h638886 = - sfd__h614530 << + assign _theResult___snd__h638883 = + sfd__h614527 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9980 ; - assign _theResult___snd__h648018 = { _theResult____h639769[55:0], 1'd0 } ; - assign _theResult___snd__h648029 = - (!_theResult____h639769[56] && _theResult____h639769[55]) ? - _theResult___snd__h648031 : - _theResult___snd__h648041 ; - assign _theResult___snd__h648031 = { _theResult____h639769[54:0], 2'd0 } ; - assign _theResult___snd__h648041 = - (!_theResult____h639769[56] && !_theResult____h639769[55] && - !_theResult____h639769[54] && - !_theResult____h639769[53] && - !_theResult____h639769[52] && - !_theResult____h639769[51] && - !_theResult____h639769[50] && - !_theResult____h639769[49] && - !_theResult____h639769[48] && - !_theResult____h639769[47] && - !_theResult____h639769[46] && - !_theResult____h639769[45] && - !_theResult____h639769[44] && - !_theResult____h639769[43] && - !_theResult____h639769[42] && - !_theResult____h639769[41] && - !_theResult____h639769[40] && - !_theResult____h639769[39] && - !_theResult____h639769[38] && - !_theResult____h639769[37] && - !_theResult____h639769[36] && - !_theResult____h639769[35] && - !_theResult____h639769[34] && - !_theResult____h639769[33] && - !_theResult____h639769[32] && - !_theResult____h639769[31] && - !_theResult____h639769[30] && - !_theResult____h639769[29] && - !_theResult____h639769[28] && - !_theResult____h639769[27] && - !_theResult____h639769[26] && - !_theResult____h639769[25] && - !_theResult____h639769[24] && - !_theResult____h639769[23] && - !_theResult____h639769[22] && - !_theResult____h639769[21] && - !_theResult____h639769[20] && - !_theResult____h639769[19] && - !_theResult____h639769[18] && - !_theResult____h639769[17] && - !_theResult____h639769[16] && - !_theResult____h639769[15] && - !_theResult____h639769[14] && - !_theResult____h639769[13] && - !_theResult____h639769[12] && - !_theResult____h639769[11] && - !_theResult____h639769[10] && - !_theResult____h639769[9] && - !_theResult____h639769[8] && - !_theResult____h639769[7] && - !_theResult____h639769[6] && - !_theResult____h639769[5] && - !_theResult____h639769[4] && - !_theResult____h639769[3] && - !_theResult____h639769[2] && - !_theResult____h639769[1] && - !_theResult____h639769[0]) ? - _theResult____h639769 : - _theResult___snd__h648047 ; - assign _theResult___snd__h648047 = + assign _theResult___snd__h648015 = { _theResult____h639766[55:0], 1'd0 } ; + assign _theResult___snd__h648026 = + (!_theResult____h639766[56] && _theResult____h639766[55]) ? + _theResult___snd__h648028 : + _theResult___snd__h648038 ; + assign _theResult___snd__h648028 = { _theResult____h639766[54:0], 2'd0 } ; + assign _theResult___snd__h648038 = + (!_theResult____h639766[56] && !_theResult____h639766[55] && + !_theResult____h639766[54] && + !_theResult____h639766[53] && + !_theResult____h639766[52] && + !_theResult____h639766[51] && + !_theResult____h639766[50] && + !_theResult____h639766[49] && + !_theResult____h639766[48] && + !_theResult____h639766[47] && + !_theResult____h639766[46] && + !_theResult____h639766[45] && + !_theResult____h639766[44] && + !_theResult____h639766[43] && + !_theResult____h639766[42] && + !_theResult____h639766[41] && + !_theResult____h639766[40] && + !_theResult____h639766[39] && + !_theResult____h639766[38] && + !_theResult____h639766[37] && + !_theResult____h639766[36] && + !_theResult____h639766[35] && + !_theResult____h639766[34] && + !_theResult____h639766[33] && + !_theResult____h639766[32] && + !_theResult____h639766[31] && + !_theResult____h639766[30] && + !_theResult____h639766[29] && + !_theResult____h639766[28] && + !_theResult____h639766[27] && + !_theResult____h639766[26] && + !_theResult____h639766[25] && + !_theResult____h639766[24] && + !_theResult____h639766[23] && + !_theResult____h639766[22] && + !_theResult____h639766[21] && + !_theResult____h639766[20] && + !_theResult____h639766[19] && + !_theResult____h639766[18] && + !_theResult____h639766[17] && + !_theResult____h639766[16] && + !_theResult____h639766[15] && + !_theResult____h639766[14] && + !_theResult____h639766[13] && + !_theResult____h639766[12] && + !_theResult____h639766[11] && + !_theResult____h639766[10] && + !_theResult____h639766[9] && + !_theResult____h639766[8] && + !_theResult____h639766[7] && + !_theResult____h639766[6] && + !_theResult____h639766[5] && + !_theResult____h639766[4] && + !_theResult____h639766[3] && + !_theResult____h639766[2] && + !_theResult____h639766[1] && + !_theResult____h639766[0]) ? + _theResult____h639766 : + _theResult___snd__h648044 ; + assign _theResult___snd__h648044 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q84[54:0], 2'd0 } ; - assign _theResult___snd__h648070 = - _theResult____h639769 << + assign _theResult___snd__h648067 = + _theResult____h639766 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10300 ; - assign _theResult___snd__h656638 = + assign _theResult___snd__h656635 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h656652 : - _theResult___snd__h638850 ; - assign _theResult___snd__h656652 = + _theResult___snd__h656649 : + _theResult___snd__h638847 ; + assign _theResult___snd__h656649 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9925) ? - sfd__h614530 : - _theResult___snd__h656658 ; - assign _theResult___snd__h656658 = + sfd__h614527 : + _theResult___snd__h656655 ; + assign _theResult___snd__h656655 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q89[54:0], 2'd0 } ; - assign _theResult___snd__h656676 = - sfd__h614530 << + assign _theResult___snd__h656673 = + sfd__h614527 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10374) ; - assign _theResult___snd__h675999 = { _theResult____h667879[55:0], 1'd0 } ; - assign _theResult___snd__h676010 = - (!_theResult____h667879[56] && _theResult____h667879[55]) ? - _theResult___snd__h676012 : - _theResult___snd__h676022 ; - assign _theResult___snd__h676012 = { _theResult____h667879[54:0], 2'd0 } ; - assign _theResult___snd__h676022 = - (!_theResult____h667879[56] && !_theResult____h667879[55] && - !_theResult____h667879[54] && - !_theResult____h667879[53] && - !_theResult____h667879[52] && - !_theResult____h667879[51] && - !_theResult____h667879[50] && - !_theResult____h667879[49] && - !_theResult____h667879[48] && - !_theResult____h667879[47] && - !_theResult____h667879[46] && - !_theResult____h667879[45] && - !_theResult____h667879[44] && - !_theResult____h667879[43] && - !_theResult____h667879[42] && - !_theResult____h667879[41] && - !_theResult____h667879[40] && - !_theResult____h667879[39] && - !_theResult____h667879[38] && - !_theResult____h667879[37] && - !_theResult____h667879[36] && - !_theResult____h667879[35] && - !_theResult____h667879[34] && - !_theResult____h667879[33] && - !_theResult____h667879[32] && - !_theResult____h667879[31] && - !_theResult____h667879[30] && - !_theResult____h667879[29] && - !_theResult____h667879[28] && - !_theResult____h667879[27] && - !_theResult____h667879[26] && - !_theResult____h667879[25] && - !_theResult____h667879[24] && - !_theResult____h667879[23] && - !_theResult____h667879[22] && - !_theResult____h667879[21] && - !_theResult____h667879[20] && - !_theResult____h667879[19] && - !_theResult____h667879[18] && - !_theResult____h667879[17] && - !_theResult____h667879[16] && - !_theResult____h667879[15] && - !_theResult____h667879[14] && - !_theResult____h667879[13] && - !_theResult____h667879[12] && - !_theResult____h667879[11] && - !_theResult____h667879[10] && - !_theResult____h667879[9] && - !_theResult____h667879[8] && - !_theResult____h667879[7] && - !_theResult____h667879[6] && - !_theResult____h667879[5] && - !_theResult____h667879[4] && - !_theResult____h667879[3] && - !_theResult____h667879[2] && - !_theResult____h667879[1] && - !_theResult____h667879[0]) ? - _theResult____h667879 : - _theResult___snd__h676028 ; - assign _theResult___snd__h676028 = + assign _theResult___snd__h675996 = { _theResult____h667876[55:0], 1'd0 } ; + assign _theResult___snd__h676007 = + (!_theResult____h667876[56] && _theResult____h667876[55]) ? + _theResult___snd__h676009 : + _theResult___snd__h676019 ; + assign _theResult___snd__h676009 = { _theResult____h667876[54:0], 2'd0 } ; + assign _theResult___snd__h676019 = + (!_theResult____h667876[56] && !_theResult____h667876[55] && + !_theResult____h667876[54] && + !_theResult____h667876[53] && + !_theResult____h667876[52] && + !_theResult____h667876[51] && + !_theResult____h667876[50] && + !_theResult____h667876[49] && + !_theResult____h667876[48] && + !_theResult____h667876[47] && + !_theResult____h667876[46] && + !_theResult____h667876[45] && + !_theResult____h667876[44] && + !_theResult____h667876[43] && + !_theResult____h667876[42] && + !_theResult____h667876[41] && + !_theResult____h667876[40] && + !_theResult____h667876[39] && + !_theResult____h667876[38] && + !_theResult____h667876[37] && + !_theResult____h667876[36] && + !_theResult____h667876[35] && + !_theResult____h667876[34] && + !_theResult____h667876[33] && + !_theResult____h667876[32] && + !_theResult____h667876[31] && + !_theResult____h667876[30] && + !_theResult____h667876[29] && + !_theResult____h667876[28] && + !_theResult____h667876[27] && + !_theResult____h667876[26] && + !_theResult____h667876[25] && + !_theResult____h667876[24] && + !_theResult____h667876[23] && + !_theResult____h667876[22] && + !_theResult____h667876[21] && + !_theResult____h667876[20] && + !_theResult____h667876[19] && + !_theResult____h667876[18] && + !_theResult____h667876[17] && + !_theResult____h667876[16] && + !_theResult____h667876[15] && + !_theResult____h667876[14] && + !_theResult____h667876[13] && + !_theResult____h667876[12] && + !_theResult____h667876[11] && + !_theResult____h667876[10] && + !_theResult____h667876[9] && + !_theResult____h667876[8] && + !_theResult____h667876[7] && + !_theResult____h667876[6] && + !_theResult____h667876[5] && + !_theResult____h667876[4] && + !_theResult____h667876[3] && + !_theResult____h667876[2] && + !_theResult____h667876[1] && + !_theResult____h667876[0]) ? + _theResult____h667876 : + _theResult___snd__h676025 ; + assign _theResult___snd__h676025 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q109[54:0], 2'd0 } ; - assign _theResult___snd__h676051 = - _theResult____h667879 << + assign _theResult___snd__h676048 = + _theResult____h667876 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11146 ; - assign _theResult___snd__h684595 = + assign _theResult___snd__h684592 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h684604 : - _theResult___snd__h684597 ; - assign _theResult___snd__h684597 = + _theResult___snd__h684601 : + _theResult___snd__h684594 ; + assign _theResult___snd__h684594 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h684604 = + assign _theResult___snd__h684601 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322) ? - sfd__h660277 : - _theResult___snd__h684610 ; - assign _theResult___snd__h684610 = + sfd__h660274 : + _theResult___snd__h684607 ; + assign _theResult___snd__h684607 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q111[54:0], 2'd0 } ; - assign _theResult___snd__h684633 = - sfd__h660277 << + assign _theResult___snd__h684630 = + sfd__h660274 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11377 ; - assign _theResult___snd__h693765 = { _theResult____h685516[55:0], 1'd0 } ; - assign _theResult___snd__h693776 = - (!_theResult____h685516[56] && _theResult____h685516[55]) ? - _theResult___snd__h693778 : - _theResult___snd__h693788 ; - assign _theResult___snd__h693778 = { _theResult____h685516[54:0], 2'd0 } ; - assign _theResult___snd__h693788 = - (!_theResult____h685516[56] && !_theResult____h685516[55] && - !_theResult____h685516[54] && - !_theResult____h685516[53] && - !_theResult____h685516[52] && - !_theResult____h685516[51] && - !_theResult____h685516[50] && - !_theResult____h685516[49] && - !_theResult____h685516[48] && - !_theResult____h685516[47] && - !_theResult____h685516[46] && - !_theResult____h685516[45] && - !_theResult____h685516[44] && - !_theResult____h685516[43] && - !_theResult____h685516[42] && - !_theResult____h685516[41] && - !_theResult____h685516[40] && - !_theResult____h685516[39] && - !_theResult____h685516[38] && - !_theResult____h685516[37] && - !_theResult____h685516[36] && - !_theResult____h685516[35] && - !_theResult____h685516[34] && - !_theResult____h685516[33] && - !_theResult____h685516[32] && - !_theResult____h685516[31] && - !_theResult____h685516[30] && - !_theResult____h685516[29] && - !_theResult____h685516[28] && - !_theResult____h685516[27] && - !_theResult____h685516[26] && - !_theResult____h685516[25] && - !_theResult____h685516[24] && - !_theResult____h685516[23] && - !_theResult____h685516[22] && - !_theResult____h685516[21] && - !_theResult____h685516[20] && - !_theResult____h685516[19] && - !_theResult____h685516[18] && - !_theResult____h685516[17] && - !_theResult____h685516[16] && - !_theResult____h685516[15] && - !_theResult____h685516[14] && - !_theResult____h685516[13] && - !_theResult____h685516[12] && - !_theResult____h685516[11] && - !_theResult____h685516[10] && - !_theResult____h685516[9] && - !_theResult____h685516[8] && - !_theResult____h685516[7] && - !_theResult____h685516[6] && - !_theResult____h685516[5] && - !_theResult____h685516[4] && - !_theResult____h685516[3] && - !_theResult____h685516[2] && - !_theResult____h685516[1] && - !_theResult____h685516[0]) ? - _theResult____h685516 : - _theResult___snd__h693794 ; - assign _theResult___snd__h693794 = + assign _theResult___snd__h693762 = { _theResult____h685513[55:0], 1'd0 } ; + assign _theResult___snd__h693773 = + (!_theResult____h685513[56] && _theResult____h685513[55]) ? + _theResult___snd__h693775 : + _theResult___snd__h693785 ; + assign _theResult___snd__h693775 = { _theResult____h685513[54:0], 2'd0 } ; + assign _theResult___snd__h693785 = + (!_theResult____h685513[56] && !_theResult____h685513[55] && + !_theResult____h685513[54] && + !_theResult____h685513[53] && + !_theResult____h685513[52] && + !_theResult____h685513[51] && + !_theResult____h685513[50] && + !_theResult____h685513[49] && + !_theResult____h685513[48] && + !_theResult____h685513[47] && + !_theResult____h685513[46] && + !_theResult____h685513[45] && + !_theResult____h685513[44] && + !_theResult____h685513[43] && + !_theResult____h685513[42] && + !_theResult____h685513[41] && + !_theResult____h685513[40] && + !_theResult____h685513[39] && + !_theResult____h685513[38] && + !_theResult____h685513[37] && + !_theResult____h685513[36] && + !_theResult____h685513[35] && + !_theResult____h685513[34] && + !_theResult____h685513[33] && + !_theResult____h685513[32] && + !_theResult____h685513[31] && + !_theResult____h685513[30] && + !_theResult____h685513[29] && + !_theResult____h685513[28] && + !_theResult____h685513[27] && + !_theResult____h685513[26] && + !_theResult____h685513[25] && + !_theResult____h685513[24] && + !_theResult____h685513[23] && + !_theResult____h685513[22] && + !_theResult____h685513[21] && + !_theResult____h685513[20] && + !_theResult____h685513[19] && + !_theResult____h685513[18] && + !_theResult____h685513[17] && + !_theResult____h685513[16] && + !_theResult____h685513[15] && + !_theResult____h685513[14] && + !_theResult____h685513[13] && + !_theResult____h685513[12] && + !_theResult____h685513[11] && + !_theResult____h685513[10] && + !_theResult____h685513[9] && + !_theResult____h685513[8] && + !_theResult____h685513[7] && + !_theResult____h685513[6] && + !_theResult____h685513[5] && + !_theResult____h685513[4] && + !_theResult____h685513[3] && + !_theResult____h685513[2] && + !_theResult____h685513[1] && + !_theResult____h685513[0]) ? + _theResult____h685513 : + _theResult___snd__h693791 ; + assign _theResult___snd__h693791 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q119[54:0], 2'd0 } ; - assign _theResult___snd__h693817 = - _theResult____h685516 << + assign _theResult___snd__h693814 = + _theResult____h685513 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11697 ; - assign _theResult___snd__h702385 = + assign _theResult___snd__h702382 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h702399 : - _theResult___snd__h684597 ; - assign _theResult___snd__h702399 = + _theResult___snd__h702396 : + _theResult___snd__h684594 ; + assign _theResult___snd__h702396 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11322) ? - sfd__h660277 : - _theResult___snd__h702405 ; - assign _theResult___snd__h702405 = + sfd__h660274 : + _theResult___snd__h702402 ; + assign _theResult___snd__h702402 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q124[54:0], 2'd0 } ; - assign _theResult___snd__h702423 = - sfd__h660277 << + assign _theResult___snd__h702420 = + sfd__h660274 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11771) ; - assign _theResult___snd__h734164 = - (f1_exp__h714825 == 8'd0) ? - _theResult___snd__h734173 : - _theResult___snd__h734166 ; - assign _theResult___snd__h734166 = { f1_sfd__h714826, 34'd0 } ; - assign _theResult___snd__h734173 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___snd__h734161 = + (f1_exp__h714822 == 8'd0) ? + _theResult___snd__h734170 : + _theResult___snd__h734163 ; + assign _theResult___snd__h734163 = { f1_sfd__h714823, 34'd0 } ; + assign _theResult___snd__h734170 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689) ? - sfd__h715187 : - _theResult___snd__h734179 ; - assign _theResult___snd__h734179 = + sfd__h715184 : + _theResult___snd__h734176 ; + assign _theResult___snd__h734176 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q145[54:0], 2'd0 } ; - assign _theResult___snd__h734202 = - sfd__h715187 << + assign _theResult___snd__h734199 = + sfd__h715184 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12716 ; - assign _theResult___snd__h743801 = { _theResult____h735554[55:0], 1'd0 } ; - assign _theResult___snd__h743812 = - (!_theResult____h735554[56] && _theResult____h735554[55]) ? - _theResult___snd__h743814 : - _theResult___snd__h743824 ; - assign _theResult___snd__h743814 = { _theResult____h735554[54:0], 2'd0 } ; - assign _theResult___snd__h743824 = - (!_theResult____h735554[56] && !_theResult____h735554[55] && - !_theResult____h735554[54] && - !_theResult____h735554[53] && - !_theResult____h735554[52] && - !_theResult____h735554[51] && - !_theResult____h735554[50] && - !_theResult____h735554[49] && - !_theResult____h735554[48] && - !_theResult____h735554[47] && - !_theResult____h735554[46] && - !_theResult____h735554[45] && - !_theResult____h735554[44] && - !_theResult____h735554[43] && - !_theResult____h735554[42] && - !_theResult____h735554[41] && - !_theResult____h735554[40] && - !_theResult____h735554[39] && - !_theResult____h735554[38] && - !_theResult____h735554[37] && - !_theResult____h735554[36] && - !_theResult____h735554[35] && - !_theResult____h735554[34] && - !_theResult____h735554[33] && - !_theResult____h735554[32] && - !_theResult____h735554[31] && - !_theResult____h735554[30] && - !_theResult____h735554[29] && - !_theResult____h735554[28] && - !_theResult____h735554[27] && - !_theResult____h735554[26] && - !_theResult____h735554[25] && - !_theResult____h735554[24] && - !_theResult____h735554[23] && - !_theResult____h735554[22] && - !_theResult____h735554[21] && - !_theResult____h735554[20] && - !_theResult____h735554[19] && - !_theResult____h735554[18] && - !_theResult____h735554[17] && - !_theResult____h735554[16] && - !_theResult____h735554[15] && - !_theResult____h735554[14] && - !_theResult____h735554[13] && - !_theResult____h735554[12] && - !_theResult____h735554[11] && - !_theResult____h735554[10] && - !_theResult____h735554[9] && - !_theResult____h735554[8] && - !_theResult____h735554[7] && - !_theResult____h735554[6] && - !_theResult____h735554[5] && - !_theResult____h735554[4] && - !_theResult____h735554[3] && - !_theResult____h735554[2] && - !_theResult____h735554[1] && - !_theResult____h735554[0]) ? - _theResult____h735554 : - _theResult___snd__h743830 ; - assign _theResult___snd__h743830 = + assign _theResult___snd__h743798 = { _theResult____h735551[55:0], 1'd0 } ; + assign _theResult___snd__h743809 = + (!_theResult____h735551[56] && _theResult____h735551[55]) ? + _theResult___snd__h743811 : + _theResult___snd__h743821 ; + assign _theResult___snd__h743811 = { _theResult____h735551[54:0], 2'd0 } ; + assign _theResult___snd__h743821 = + (!_theResult____h735551[56] && !_theResult____h735551[55] && + !_theResult____h735551[54] && + !_theResult____h735551[53] && + !_theResult____h735551[52] && + !_theResult____h735551[51] && + !_theResult____h735551[50] && + !_theResult____h735551[49] && + !_theResult____h735551[48] && + !_theResult____h735551[47] && + !_theResult____h735551[46] && + !_theResult____h735551[45] && + !_theResult____h735551[44] && + !_theResult____h735551[43] && + !_theResult____h735551[42] && + !_theResult____h735551[41] && + !_theResult____h735551[40] && + !_theResult____h735551[39] && + !_theResult____h735551[38] && + !_theResult____h735551[37] && + !_theResult____h735551[36] && + !_theResult____h735551[35] && + !_theResult____h735551[34] && + !_theResult____h735551[33] && + !_theResult____h735551[32] && + !_theResult____h735551[31] && + !_theResult____h735551[30] && + !_theResult____h735551[29] && + !_theResult____h735551[28] && + !_theResult____h735551[27] && + !_theResult____h735551[26] && + !_theResult____h735551[25] && + !_theResult____h735551[24] && + !_theResult____h735551[23] && + !_theResult____h735551[22] && + !_theResult____h735551[21] && + !_theResult____h735551[20] && + !_theResult____h735551[19] && + !_theResult____h735551[18] && + !_theResult____h735551[17] && + !_theResult____h735551[16] && + !_theResult____h735551[15] && + !_theResult____h735551[14] && + !_theResult____h735551[13] && + !_theResult____h735551[12] && + !_theResult____h735551[11] && + !_theResult____h735551[10] && + !_theResult____h735551[9] && + !_theResult____h735551[8] && + !_theResult____h735551[7] && + !_theResult____h735551[6] && + !_theResult____h735551[5] && + !_theResult____h735551[4] && + !_theResult____h735551[3] && + !_theResult____h735551[2] && + !_theResult____h735551[1] && + !_theResult____h735551[0]) ? + _theResult____h735551 : + _theResult___snd__h743827 ; + assign _theResult___snd__h743827 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q149[54:0], 2'd0 } ; - assign _theResult___snd__h743853 = - _theResult____h735554 << + assign _theResult___snd__h743850 = + _theResult____h735551 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13028 ; - assign _theResult___snd__h752569 = - (f1_exp__h714825 == 8'd0) ? - _theResult___snd__h752583 : - _theResult___snd__h734166 ; - assign _theResult___snd__h752583 = - (f1_exp__h714825 == 8'd0 && !f1_sfd__h714826[22] && + assign _theResult___snd__h752566 = + (f1_exp__h714822 == 8'd0) ? + _theResult___snd__h752580 : + _theResult___snd__h734163 ; + assign _theResult___snd__h752580 = + (f1_exp__h714822 == 8'd0 && !f1_sfd__h714823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12689) ? - sfd__h715187 : - _theResult___snd__h752589 ; - assign _theResult___snd__h752589 = + sfd__h715184 : + _theResult___snd__h752586 ; + assign _theResult___snd__h752586 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q152[54:0], 2'd0 } ; - assign _theResult___snd__h752607 = - sfd__h715187 << + assign _theResult___snd__h752604 = + sfd__h715184 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13079 ; - assign _theResult___snd__h773017 = - (f2_exp__h753819 == 8'd0) ? - _theResult___snd__h773026 : - _theResult___snd__h773019 ; - assign _theResult___snd__h773019 = { f2_sfd__h753820, 34'd0 } ; - assign _theResult___snd__h773026 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___snd__h773014 = + (f2_exp__h753816 == 8'd0) ? + _theResult___snd__h773023 : + _theResult___snd__h773016 ; + assign _theResult___snd__h773016 = { f2_sfd__h753817, 34'd0 } ; + assign _theResult___snd__h773023 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189) ? - sfd__h754181 : - _theResult___snd__h773032 ; - assign _theResult___snd__h773032 = + sfd__h754178 : + _theResult___snd__h773029 ; + assign _theResult___snd__h773029 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q185[54:0], 2'd0 } ; - assign _theResult___snd__h773055 = - sfd__h754181 << + assign _theResult___snd__h773052 = + sfd__h754178 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14216 ; - assign _theResult___snd__h782654 = { _theResult____h774407[55:0], 1'd0 } ; - assign _theResult___snd__h782665 = - (!_theResult____h774407[56] && _theResult____h774407[55]) ? - _theResult___snd__h782667 : - _theResult___snd__h782677 ; - assign _theResult___snd__h782667 = { _theResult____h774407[54:0], 2'd0 } ; - assign _theResult___snd__h782677 = - (!_theResult____h774407[56] && !_theResult____h774407[55] && - !_theResult____h774407[54] && - !_theResult____h774407[53] && - !_theResult____h774407[52] && - !_theResult____h774407[51] && - !_theResult____h774407[50] && - !_theResult____h774407[49] && - !_theResult____h774407[48] && - !_theResult____h774407[47] && - !_theResult____h774407[46] && - !_theResult____h774407[45] && - !_theResult____h774407[44] && - !_theResult____h774407[43] && - !_theResult____h774407[42] && - !_theResult____h774407[41] && - !_theResult____h774407[40] && - !_theResult____h774407[39] && - !_theResult____h774407[38] && - !_theResult____h774407[37] && - !_theResult____h774407[36] && - !_theResult____h774407[35] && - !_theResult____h774407[34] && - !_theResult____h774407[33] && - !_theResult____h774407[32] && - !_theResult____h774407[31] && - !_theResult____h774407[30] && - !_theResult____h774407[29] && - !_theResult____h774407[28] && - !_theResult____h774407[27] && - !_theResult____h774407[26] && - !_theResult____h774407[25] && - !_theResult____h774407[24] && - !_theResult____h774407[23] && - !_theResult____h774407[22] && - !_theResult____h774407[21] && - !_theResult____h774407[20] && - !_theResult____h774407[19] && - !_theResult____h774407[18] && - !_theResult____h774407[17] && - !_theResult____h774407[16] && - !_theResult____h774407[15] && - !_theResult____h774407[14] && - !_theResult____h774407[13] && - !_theResult____h774407[12] && - !_theResult____h774407[11] && - !_theResult____h774407[10] && - !_theResult____h774407[9] && - !_theResult____h774407[8] && - !_theResult____h774407[7] && - !_theResult____h774407[6] && - !_theResult____h774407[5] && - !_theResult____h774407[4] && - !_theResult____h774407[3] && - !_theResult____h774407[2] && - !_theResult____h774407[1] && - !_theResult____h774407[0]) ? - _theResult____h774407 : - _theResult___snd__h782683 ; - assign _theResult___snd__h782683 = + assign _theResult___snd__h782651 = { _theResult____h774404[55:0], 1'd0 } ; + assign _theResult___snd__h782662 = + (!_theResult____h774404[56] && _theResult____h774404[55]) ? + _theResult___snd__h782664 : + _theResult___snd__h782674 ; + assign _theResult___snd__h782664 = { _theResult____h774404[54:0], 2'd0 } ; + assign _theResult___snd__h782674 = + (!_theResult____h774404[56] && !_theResult____h774404[55] && + !_theResult____h774404[54] && + !_theResult____h774404[53] && + !_theResult____h774404[52] && + !_theResult____h774404[51] && + !_theResult____h774404[50] && + !_theResult____h774404[49] && + !_theResult____h774404[48] && + !_theResult____h774404[47] && + !_theResult____h774404[46] && + !_theResult____h774404[45] && + !_theResult____h774404[44] && + !_theResult____h774404[43] && + !_theResult____h774404[42] && + !_theResult____h774404[41] && + !_theResult____h774404[40] && + !_theResult____h774404[39] && + !_theResult____h774404[38] && + !_theResult____h774404[37] && + !_theResult____h774404[36] && + !_theResult____h774404[35] && + !_theResult____h774404[34] && + !_theResult____h774404[33] && + !_theResult____h774404[32] && + !_theResult____h774404[31] && + !_theResult____h774404[30] && + !_theResult____h774404[29] && + !_theResult____h774404[28] && + !_theResult____h774404[27] && + !_theResult____h774404[26] && + !_theResult____h774404[25] && + !_theResult____h774404[24] && + !_theResult____h774404[23] && + !_theResult____h774404[22] && + !_theResult____h774404[21] && + !_theResult____h774404[20] && + !_theResult____h774404[19] && + !_theResult____h774404[18] && + !_theResult____h774404[17] && + !_theResult____h774404[16] && + !_theResult____h774404[15] && + !_theResult____h774404[14] && + !_theResult____h774404[13] && + !_theResult____h774404[12] && + !_theResult____h774404[11] && + !_theResult____h774404[10] && + !_theResult____h774404[9] && + !_theResult____h774404[8] && + !_theResult____h774404[7] && + !_theResult____h774404[6] && + !_theResult____h774404[5] && + !_theResult____h774404[4] && + !_theResult____h774404[3] && + !_theResult____h774404[2] && + !_theResult____h774404[1] && + !_theResult____h774404[0]) ? + _theResult____h774404 : + _theResult___snd__h782680 ; + assign _theResult___snd__h782680 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q189[54:0], 2'd0 } ; - assign _theResult___snd__h782706 = - _theResult____h774407 << + assign _theResult___snd__h782703 = + _theResult____h774404 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14513 ; - assign _theResult___snd__h791422 = - (f2_exp__h753819 == 8'd0) ? - _theResult___snd__h791436 : - _theResult___snd__h773019 ; - assign _theResult___snd__h791436 = - (f2_exp__h753819 == 8'd0 && !f2_sfd__h753820[22] && + assign _theResult___snd__h791419 = + (f2_exp__h753816 == 8'd0) ? + _theResult___snd__h791433 : + _theResult___snd__h773016 ; + assign _theResult___snd__h791433 = + (f2_exp__h753816 == 8'd0 && !f2_sfd__h753817[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14189) ? - sfd__h754181 : - _theResult___snd__h791442 ; - assign _theResult___snd__h791442 = + sfd__h754178 : + _theResult___snd__h791439 ; + assign _theResult___snd__h791439 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q192[54:0], 2'd0 } ; - assign _theResult___snd__h791460 = - sfd__h754181 << + assign _theResult___snd__h791457 = + sfd__h754178 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14564 ; - assign _theResult___snd__h812321 = - (f3_exp__h793123 == 8'd0) ? - _theResult___snd__h812330 : - _theResult___snd__h812323 ; - assign _theResult___snd__h812323 = { f3_sfd__h793124, 34'd0 } ; - assign _theResult___snd__h812330 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___snd__h812318 = + (f3_exp__h793120 == 8'd0) ? + _theResult___snd__h812327 : + _theResult___snd__h812320 ; + assign _theResult___snd__h812320 = { f3_sfd__h793121, 34'd0 } ; + assign _theResult___snd__h812327 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419) ? - sfd__h793485 : - _theResult___snd__h812336 ; - assign _theResult___snd__h812336 = + sfd__h793482 : + _theResult___snd__h812333 ; + assign _theResult___snd__h812333 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q162[54:0], 2'd0 } ; - assign _theResult___snd__h812359 = - sfd__h793485 << + assign _theResult___snd__h812356 = + sfd__h793482 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13446 ; - assign _theResult___snd__h821958 = { _theResult____h813711[55:0], 1'd0 } ; - assign _theResult___snd__h821969 = - (!_theResult____h813711[56] && _theResult____h813711[55]) ? - _theResult___snd__h821971 : - _theResult___snd__h821981 ; - assign _theResult___snd__h821971 = { _theResult____h813711[54:0], 2'd0 } ; - assign _theResult___snd__h821981 = - (!_theResult____h813711[56] && !_theResult____h813711[55] && - !_theResult____h813711[54] && - !_theResult____h813711[53] && - !_theResult____h813711[52] && - !_theResult____h813711[51] && - !_theResult____h813711[50] && - !_theResult____h813711[49] && - !_theResult____h813711[48] && - !_theResult____h813711[47] && - !_theResult____h813711[46] && - !_theResult____h813711[45] && - !_theResult____h813711[44] && - !_theResult____h813711[43] && - !_theResult____h813711[42] && - !_theResult____h813711[41] && - !_theResult____h813711[40] && - !_theResult____h813711[39] && - !_theResult____h813711[38] && - !_theResult____h813711[37] && - !_theResult____h813711[36] && - !_theResult____h813711[35] && - !_theResult____h813711[34] && - !_theResult____h813711[33] && - !_theResult____h813711[32] && - !_theResult____h813711[31] && - !_theResult____h813711[30] && - !_theResult____h813711[29] && - !_theResult____h813711[28] && - !_theResult____h813711[27] && - !_theResult____h813711[26] && - !_theResult____h813711[25] && - !_theResult____h813711[24] && - !_theResult____h813711[23] && - !_theResult____h813711[22] && - !_theResult____h813711[21] && - !_theResult____h813711[20] && - !_theResult____h813711[19] && - !_theResult____h813711[18] && - !_theResult____h813711[17] && - !_theResult____h813711[16] && - !_theResult____h813711[15] && - !_theResult____h813711[14] && - !_theResult____h813711[13] && - !_theResult____h813711[12] && - !_theResult____h813711[11] && - !_theResult____h813711[10] && - !_theResult____h813711[9] && - !_theResult____h813711[8] && - !_theResult____h813711[7] && - !_theResult____h813711[6] && - !_theResult____h813711[5] && - !_theResult____h813711[4] && - !_theResult____h813711[3] && - !_theResult____h813711[2] && - !_theResult____h813711[1] && - !_theResult____h813711[0]) ? - _theResult____h813711 : - _theResult___snd__h821987 ; - assign _theResult___snd__h821987 = + assign _theResult___snd__h821955 = { _theResult____h813708[55:0], 1'd0 } ; + assign _theResult___snd__h821966 = + (!_theResult____h813708[56] && _theResult____h813708[55]) ? + _theResult___snd__h821968 : + _theResult___snd__h821978 ; + assign _theResult___snd__h821968 = { _theResult____h813708[54:0], 2'd0 } ; + assign _theResult___snd__h821978 = + (!_theResult____h813708[56] && !_theResult____h813708[55] && + !_theResult____h813708[54] && + !_theResult____h813708[53] && + !_theResult____h813708[52] && + !_theResult____h813708[51] && + !_theResult____h813708[50] && + !_theResult____h813708[49] && + !_theResult____h813708[48] && + !_theResult____h813708[47] && + !_theResult____h813708[46] && + !_theResult____h813708[45] && + !_theResult____h813708[44] && + !_theResult____h813708[43] && + !_theResult____h813708[42] && + !_theResult____h813708[41] && + !_theResult____h813708[40] && + !_theResult____h813708[39] && + !_theResult____h813708[38] && + !_theResult____h813708[37] && + !_theResult____h813708[36] && + !_theResult____h813708[35] && + !_theResult____h813708[34] && + !_theResult____h813708[33] && + !_theResult____h813708[32] && + !_theResult____h813708[31] && + !_theResult____h813708[30] && + !_theResult____h813708[29] && + !_theResult____h813708[28] && + !_theResult____h813708[27] && + !_theResult____h813708[26] && + !_theResult____h813708[25] && + !_theResult____h813708[24] && + !_theResult____h813708[23] && + !_theResult____h813708[22] && + !_theResult____h813708[21] && + !_theResult____h813708[20] && + !_theResult____h813708[19] && + !_theResult____h813708[18] && + !_theResult____h813708[17] && + !_theResult____h813708[16] && + !_theResult____h813708[15] && + !_theResult____h813708[14] && + !_theResult____h813708[13] && + !_theResult____h813708[12] && + !_theResult____h813708[11] && + !_theResult____h813708[10] && + !_theResult____h813708[9] && + !_theResult____h813708[8] && + !_theResult____h813708[7] && + !_theResult____h813708[6] && + !_theResult____h813708[5] && + !_theResult____h813708[4] && + !_theResult____h813708[3] && + !_theResult____h813708[2] && + !_theResult____h813708[1] && + !_theResult____h813708[0]) ? + _theResult____h813708 : + _theResult___snd__h821984 ; + assign _theResult___snd__h821984 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h822010 = - _theResult____h813711 << + assign _theResult___snd__h822007 = + _theResult____h813708 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13743 ; - assign _theResult___snd__h830726 = - (f3_exp__h793123 == 8'd0) ? - _theResult___snd__h830740 : - _theResult___snd__h812323 ; - assign _theResult___snd__h830740 = - (f3_exp__h793123 == 8'd0 && !f3_sfd__h793124[22] && + assign _theResult___snd__h830723 = + (f3_exp__h793120 == 8'd0) ? + _theResult___snd__h830737 : + _theResult___snd__h812320 ; + assign _theResult___snd__h830737 = + (f3_exp__h793120 == 8'd0 && !f3_sfd__h793121[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13419) ? - sfd__h793485 : - _theResult___snd__h830746 ; - assign _theResult___snd__h830746 = + sfd__h793482 : + _theResult___snd__h830743 ; + assign _theResult___snd__h830743 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q169[54:0], 2'd0 } ; - assign _theResult___snd__h830764 = - sfd__h793485 << + assign _theResult___snd__h830761 = + sfd__h793482 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13794 ; - assign _theResult___snd__h836056 = - b__h835634[63] ? b___1__h836105 : b__h835634 ; - assign _theResult___snd_fst_exp__h593674 = + assign _theResult___snd__h836053 = + b__h835631[63] ? b___1__h836102 : b__h835631 ; + assign _theResult___snd_fst_exp__h593671 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - _theResult___fst_exp__h585089 : - _theResult___fst_exp__h593671 ; - assign _theResult___snd_fst_exp__h611494 = + _theResult___fst_exp__h585086 : + _theResult___fst_exp__h593668 ; + assign _theResult___snd_fst_exp__h611491 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - _theResult___fst_exp__h602855 : - _theResult___fst_exp__h611491 ; - assign _theResult___snd_fst_exp__h639423 = + _theResult___fst_exp__h602852 : + _theResult___fst_exp__h611488 ; + assign _theResult___snd_fst_exp__h639420 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - _theResult___fst_exp__h630838 : - _theResult___fst_exp__h639420 ; - assign _theResult___snd_fst_exp__h657243 = + _theResult___fst_exp__h630835 : + _theResult___fst_exp__h639417 ; + assign _theResult___snd_fst_exp__h657240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - _theResult___fst_exp__h648604 : - _theResult___fst_exp__h657240 ; - assign _theResult___snd_fst_exp__h685170 = + _theResult___fst_exp__h648601 : + _theResult___fst_exp__h657237 ; + assign _theResult___snd_fst_exp__h685167 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - _theResult___fst_exp__h676585 : - _theResult___fst_exp__h685167 ; - assign _theResult___snd_fst_exp__h702990 = + _theResult___fst_exp__h676582 : + _theResult___fst_exp__h685164 ; + assign _theResult___snd_fst_exp__h702987 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - _theResult___fst_exp__h694351 : - _theResult___fst_exp__h702987 ; - assign _theResult___snd_fst_exp__h734974 = + _theResult___fst_exp__h694348 : + _theResult___fst_exp__h702984 ; + assign _theResult___snd_fst_exp__h734971 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 ? 11'd0 : - _theResult___fst_exp__h734971 ; - assign _theResult___snd_fst_exp__h753409 = + _theResult___fst_exp__h734968 ; + assign _theResult___snd_fst_exp__h753406 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? - _theResult___fst_exp__h744622 : - _theResult___fst_exp__h753406 ; - assign _theResult___snd_fst_exp__h773827 = + _theResult___fst_exp__h744619 : + _theResult___fst_exp__h753403 ; + assign _theResult___snd_fst_exp__h773824 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? 11'd0 : - _theResult___fst_exp__h773824 ; - assign _theResult___snd_fst_exp__h792262 = + _theResult___fst_exp__h773821 ; + assign _theResult___snd_fst_exp__h792259 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? - _theResult___fst_exp__h783475 : - _theResult___fst_exp__h792259 ; - assign _theResult___snd_fst_exp__h813131 = + _theResult___fst_exp__h783472 : + _theResult___fst_exp__h792256 ; + assign _theResult___snd_fst_exp__h813128 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? 11'd0 : - _theResult___fst_exp__h813128 ; - assign _theResult___snd_fst_exp__h831566 = + _theResult___fst_exp__h813125 ; + assign _theResult___snd_fst_exp__h831563 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? - _theResult___fst_exp__h822779 : - _theResult___fst_exp__h831563 ; - assign _theResult___snd_fst_sfd__h568726 = + _theResult___fst_exp__h822776 : + _theResult___fst_exp__h831560 ; + assign _theResult___snd_fst_sfd__h568723 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h593675 = + assign _theResult___snd_fst_sfd__h593672 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8118 ? - _theResult___fst_sfd__h585090 : - _theResult___fst_sfd__h593672 ; - assign _theResult___snd_fst_sfd__h611495 = + _theResult___fst_sfd__h585087 : + _theResult___fst_sfd__h593669 ; + assign _theResult___snd_fst_sfd__h611492 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8658 ? - _theResult___fst_sfd__h602856 : - _theResult___fst_sfd__h611492 ; - assign _theResult___snd_fst_sfd__h614480 = + _theResult___fst_sfd__h602853 : + _theResult___fst_sfd__h611489 ; + assign _theResult___snd_fst_sfd__h614477 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h639424 = + assign _theResult___snd_fst_sfd__h639421 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9515 ? - _theResult___fst_sfd__h630839 : - _theResult___fst_sfd__h639421 ; - assign _theResult___snd_fst_sfd__h657244 = + _theResult___fst_sfd__h630836 : + _theResult___fst_sfd__h639418 ; + assign _theResult___snd_fst_sfd__h657241 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10055 ? - _theResult___fst_sfd__h648605 : - _theResult___fst_sfd__h657241 ; - assign _theResult___snd_fst_sfd__h660227 = + _theResult___fst_sfd__h648602 : + _theResult___fst_sfd__h657238 ; + assign _theResult___snd_fst_sfd__h660224 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h685171 = + assign _theResult___snd_fst_sfd__h685168 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10912 ? - _theResult___fst_sfd__h676586 : - _theResult___fst_sfd__h685168 ; - assign _theResult___snd_fst_sfd__h702991 = + _theResult___fst_sfd__h676583 : + _theResult___fst_sfd__h685165 ; + assign _theResult___snd_fst_sfd__h702988 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11452 ? - _theResult___fst_sfd__h694352 : - _theResult___fst_sfd__h702988 ; - assign _theResult___snd_fst_sfd__h715141 = - (f1_sfd__h714826 == 23'd0) ? + _theResult___fst_sfd__h694349 : + _theResult___fst_sfd__h702985 ; + assign _theResult___snd_fst_sfd__h715138 = + (f1_sfd__h714823 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h714889 ; - assign _theResult___snd_fst_sfd__h734975 = + out___1_sfd__h714886 ; + assign _theResult___snd_fst_sfd__h734972 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12645 ? 52'd0 : - _theResult___fst_sfd__h734972 ; - assign _theResult___snd_fst_sfd__h753410 = + _theResult___fst_sfd__h734969 ; + assign _theResult___snd_fst_sfd__h753407 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12781 ? - _theResult___fst_sfd__h744623 : - _theResult___fst_sfd__h753407 ; - assign _theResult___snd_fst_sfd__h754135 = - (f2_sfd__h753820 == 23'd0) ? + _theResult___fst_sfd__h744620 : + _theResult___fst_sfd__h753404 ; + assign _theResult___snd_fst_sfd__h754132 = + (f2_sfd__h753817 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h753883 ; - assign _theResult___snd_fst_sfd__h773828 = + out___1_sfd__h753880 ; + assign _theResult___snd_fst_sfd__h773825 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14145 ? 52'd0 : - _theResult___fst_sfd__h773825 ; - assign _theResult___snd_fst_sfd__h792263 = + _theResult___fst_sfd__h773822 ; + assign _theResult___snd_fst_sfd__h792260 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14266 ? - _theResult___fst_sfd__h783476 : - _theResult___fst_sfd__h792260 ; - assign _theResult___snd_fst_sfd__h793439 = - (f3_sfd__h793124 == 23'd0) ? + _theResult___fst_sfd__h783473 : + _theResult___fst_sfd__h792257 ; + assign _theResult___snd_fst_sfd__h793436 = + (f3_sfd__h793121 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h793187 ; - assign _theResult___snd_fst_sfd__h813132 = + out___1_sfd__h793184 ; + assign _theResult___snd_fst_sfd__h813129 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13375 ? 52'd0 : - _theResult___fst_sfd__h813129 ; - assign _theResult___snd_fst_sfd__h831567 = + _theResult___fst_sfd__h813126 ; + assign _theResult___snd_fst_sfd__h831564 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13496 ? - _theResult___fst_sfd__h822780 : - _theResult___fst_sfd__h831564 ; - assign a___1__h835774 = + _theResult___fst_sfd__h822777 : + _theResult___fst_sfd__h831561 ; + assign a___1__h835771 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q21 } ; - assign a___1__h836060 = 64'd0 - a__h835633 ; - assign a__h835633 = + assign a___1__h836057 = 64'd0 - a__h835630 ; + assign a__h835630 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h835774 : + a___1__h835771 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h239805 = - { {48{base__h239640[15]}}, base__h239640 } << + assign addBase__h239804 = + { {48{base__h239639[15]}}, base__h239639 } << coreFix_memExe_regToExeQ$first[264:259] ; - assign addBase__h240962 = - { {48{base__h240797[15]}}, base__h240797 } << + assign addBase__h240961 = + { {48{base__h240796[15]}}, base__h240796 } << coreFix_memExe_regToExeQ$first[101:96] ; - assign addBase__h254571 = - { {48{base__h254406[15]}}, base__h254406 } << + assign addBase__h254569 = + { {48{base__h254404[15]}}, base__h254404 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h239914 = - { {50{x__h240013[15]}}, x__h240013 } << + assign addTop__h239913 = + { {50{x__h240012[15]}}, x__h240012 } << coreFix_memExe_regToExeQ$first[264:259] ; - assign addTop__h241071 = - { {50{x__h241170[15]}}, x__h241170 } << + assign addTop__h241070 = + { {50{x__h241169[15]}}, x__h241169 } << coreFix_memExe_regToExeQ$first[101:96] ; - assign addTop__h254680 = - { {50{x__h254779[15]}}, x__h254779 } << + assign addTop__h254678 = + { {50{x__h254777[15]}}, x__h254777 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addr__h148408 = + assign addr__h148407 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0] ; - assign addr__h151984 = + assign addr__h151983 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h235261 = x__h235690[63:0] + csrf_ddc_reg[149:86] ; - assign addr__h987208 = + assign addr__h235260 = x__h235689[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h987203 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign address__h1008563 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h996900 = base__h996861 + { 57'd0, x__h997059 } ; - assign address__h996950 = base__h996915 + { 57'd0, x__h997059 } ; - assign address__h996966 = { 2'd0, address__h996900 } ; - assign address__h997310 = { 2'd0, base__h996861 } ; - assign address__h997623 = { 2'd0, address__h996950 } ; - assign address__h997967 = { 2'd0, base__h996915 } ; - assign b___1__h835775 = + assign address__h1008558 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h996895 = base__h996856 + { 57'd0, x__h997054 } ; + assign address__h996945 = base__h996910 + { 57'd0, x__h997054 } ; + assign address__h996961 = { 2'd0, address__h996895 } ; + assign address__h997305 = { 2'd0, base__h996856 } ; + assign address__h997618 = { 2'd0, address__h996945 } ; + assign address__h997962 = { 2'd0, base__h996910 } ; + assign b___1__h835772 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h836105 = 64'd0 - b__h835634 ; - assign b__h835634 = + assign b___1__h836102 = 64'd0 - b__h835631 ; + assign b__h835631 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h835775 : + b___1__h835772 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b_base__h127497 = + assign b_base__h127496 = { coreFix_memExe_respLrScAmoQ_data_0[77:67], ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign b_base__h140413 = + assign b_base__h140412 = { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h183674 = - { x__h183367[77:67], ~x__h183367[66], x__h183367[65:64] } ; - assign b_base__h202425 = - { x__h199219[77:67], ~x__h199219[66], x__h199219[65:64] } ; - assign b_base__h216991 = + assign b_base__h183673 = + { x__h183366[77:67], ~x__h183366[66], x__h183366[65:64] } ; + assign b_base__h202424 = + { x__h199218[77:67], ~x__h199218[66], x__h199218[65:64] } ; + assign b_base__h216990 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h865912 = + assign b_base__h865909 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h866460 = + assign b_base__h866457 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h904534 = + assign b_base__h904530 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h905082 = + assign b_base__h905078 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_base__h992608 = + assign b_base__h992603 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign b_top__h127496 = + assign b_top__h127495 = { coreFix_memExe_respLrScAmoQ_data_0[89:81], ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign b_top__h140412 = + assign b_top__h140411 = { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h183673 = - { x__h183367[89:81], ~x__h183367[80:79], x__h183367[78] } ; - assign b_top__h202424 = - { x__h199219[89:81], ~x__h199219[80:79], x__h199219[78] } ; - assign b_top__h216990 = + assign b_top__h183672 = + { x__h183366[89:81], ~x__h183366[80:79], x__h183366[78] } ; + assign b_top__h202423 = + { x__h199218[89:81], ~x__h199218[80:79], x__h199218[78] } ; + assign b_top__h216989 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h865911 = + assign b_top__h865908 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h866459 = + assign b_top__h866456 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h904533 = + assign b_top__h904529 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h905081 = + assign b_top__h905077 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign b_top__h992607 = + assign b_top__h992602 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign base__h239640 = + assign base__h239639 = { coreFix_memExe_regToExeQ$first[222:221], coreFix_memExe_regToExeQ$first[244:231] } ; - assign base__h240797 = + assign base__h240796 = { coreFix_memExe_regToExeQ$first[59:58], coreFix_memExe_regToExeQ$first[81:68] } ; - assign base__h254406 = + assign base__h254404 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h995046 = + assign base__h995041 = { (IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22432 == IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22434) ? 2'd0 : @@ -32393,31 +32393,31 @@ module mkCore(CLK, !IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22434) ? 2'd1 : 2'd3), - x__h992601 } ; - assign base__h996861 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h996915 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign carry_out__h127401 = - (topBits__h127399 < x__h127490[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h140317 = - (topBits__h140315 < x__h140406[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h183578 = - (topBits__h183576 < x__h183667[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h202329 = - (topBits__h202327 < x__h202418[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h216895 = - (topBits__h216893 < x__h216984[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h865815 = - (topBits__h865813 < x__h865905[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h866363 = - (topBits__h866361 < x__h866453[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h904437 = - (topBits__h904435 < x__h904527[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h904985 = - (topBits__h904983 < x__h905075[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h992512 = - (topBits__h992510 < x__h992601[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h994330 = { 1'd0, i__h992982 } ; - assign cause_interrupt__h992790 = + x__h992596 } ; + assign base__h996856 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h996910 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign carry_out__h127400 = + (topBits__h127398 < x__h127489[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h140316 = + (topBits__h140314 < x__h140405[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h183577 = + (topBits__h183575 < x__h183666[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h202328 = + (topBits__h202326 < x__h202417[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h216894 = + (topBits__h216892 < x__h216983[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h865812 = + (topBits__h865810 < x__h865902[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h866360 = + (topBits__h866358 < x__h866450[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h904433 = + (topBits__h904431 < x__h904523[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h904981 = + (topBits__h904979 < x__h905071[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h992507 = + (topBits__h992505 < x__h992596[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h994325 = { 1'd0, i__h992977 } ; + assign cause_interrupt__h992785 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2039_BITS_44_TO_43_2232_ETC___d22272 = @@ -32482,7 +32482,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19008, IF_coreFix_aluExe_0_dispToRegQ_first__8202_BIT_ETC___d19200, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h898430 : + repBound__h898426 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8202_BI_ETC___d19240 } ; assign coreFix_aluExe_0_dispToRegQ_first__8202_BIT_13_ETC___d18287 = @@ -32533,7 +32533,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d16643, IF_coreFix_aluExe_1_dispToRegQ_first__5590_BIT_ETC___d17095, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h859420 : + repBound__h859417 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5590_BI_ETC___d17161 } ; assign coreFix_aluExe_1_dispToRegQ_first__5590_BIT_13_ETC___d15675 = @@ -32638,9 +32638,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14940 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14980) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15021 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32648,9 +32648,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15009 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15016) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15069 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32658,9 +32658,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15053 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15064) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15111 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32668,9 +32668,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15097 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15106) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d15153 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -32678,9 +32678,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15139 | - ((f3_exp__h793123 != 8'd255 || f3_sfd__h793124 == 23'd0) && - (f3_exp__h793123 != 8'd255 || f3_sfd__h793124 != 23'd0) && - (f3_exp__h793123 != 8'd0 || f3_sfd__h793124 != 23'd0) && + ((f3_exp__h793120 != 8'd255 || f3_sfd__h793121 == 23'd0) && + (f3_exp__h793120 != 8'd255 || f3_sfd__h793121 != 23'd0) && + (f3_exp__h793120 != 8'd0 || f3_sfd__h793121 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15148) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q22 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -32719,7 +32719,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5005 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h422493 ; + y__h422490 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5614 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -34899,12 +34899,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__239_BITS_334_TO__ETC___d4402 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64:63] - - { 1'd0, x__h254848 } > + { 1'd0, x__h254846 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h254681, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h254679, 14'd0 } + - addTop__h254680 ; + addTop__h254678 ; assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4539 = coreFix_memExe_dTlb$procResp[560:500] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__239_BITS_560_TO__ETC___d4540 = @@ -34950,15 +34950,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__680_BIT_10_ETC___d3568 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4232 = - { coreFix_memExe_lsq$getOrigBE << pointer__h242569[3:0], - (highOffsetBits__h242578 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h242568[3:0], + (highOffsetBits__h242577 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__633_BI_ETC___d4077 || coreFix_memExe_regToExeQ$first[264:259] >= 6'd50) && coreFix_memExe_regToExeQ$first[383], - result_d_address__h242780, - x__h248052[13:0], + result_d_address__h242779, + x__h248050[13:0], coreFix_memExe_regToExeQ$first[302:231], - repBound__h248150, + repBound__h248148, coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092, coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105, @@ -34966,7 +34966,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__633_BITS_101_T_ETC___d3767 = coreFix_memExe_regToExeQ$first[101:96] < 6'd51 && coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64:63] - - { 1'd0, x__h241239 } > + { 1'd0, x__h241238 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__633_BITS_139_T_ETC___d4052 = { coreFix_memExe_regToExeQ$first[139:124], @@ -34979,26 +34979,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[2], IF_coreFix_memExe_regToExeQ_first__633_BIT_102_ETC___d3999[1:0], coreFix_memExe_regToExeQ$first[217:154] } << - x__h244610 ; + x__h244608 ; assign coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754 = - { coreFix_memExe_regToExeQ$first[219:168] & mask__h241072, + { coreFix_memExe_regToExeQ$first[219:168] & mask__h241071, 14'd0 } + - addTop__h241071 ; + addTop__h241070 ; assign coreFix_memExe_regToExeQ_first__633_BITS_244_T_ETC___d4093 = - coreFix_memExe_regToExeQ$first[244:242] < repBound__h248150 ; + coreFix_memExe_regToExeQ$first[244:242] < repBound__h248148 ; assign coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092 = - coreFix_memExe_regToExeQ$first[258:256] < repBound__h248150 ; + coreFix_memExe_regToExeQ$first[258:256] < repBound__h248148 ; assign coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705 = coreFix_memExe_regToExeQ$first[264:259] < 6'd51 && coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64:63] - - { 1'd0, x__h240082 } > + { 1'd0, x__h240081 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692 = - { coreFix_memExe_regToExeQ$first[382:331] & mask__h239915, + { coreFix_memExe_regToExeQ$first[382:331] & mask__h239914, 14'd0 } + - addTop__h239914 ; + addTop__h239913 ; assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095 = - x__h248052[13:11] < repBound__h248150 ; + x__h248050[13:11] < repBound__h248148 ; assign coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4105 = { coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d4095, (coreFix_memExe_regToExeQ_first__633_BITS_258_T_ETC___d4092 == @@ -35039,44 +35039,44 @@ module mkCore(CLK, fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__2032_BITS_469_TO_4_ETC___d22805 ; - assign cr_addrBits__h865498 = + assign cr_addrBits__h865495 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h865674[13:0] : + x__h865671[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h866046 = + assign cr_addrBits__h866043 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h866222[13:0] : + x__h866219[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h904120 = + assign cr_addrBits__h904116 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h904296[13:0] : + x__h904292[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h904668 = + assign cr_addrBits__h904664 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h904844[13:0] : + x__h904840[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h865497 = + assign cr_address__h865494 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h866045 = + assign cr_address__h866042 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h904119 = + assign cr_address__h904115 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h904667 = + assign cr_address__h904663 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h865500 = coreFix_aluExe_1_regToExeQ$first[287] ; - assign cr_flags__h866048 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h904122 = coreFix_aluExe_0_regToExeQ$first[287] ; - assign cr_flags__h904670 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h865501 = coreFix_aluExe_1_regToExeQ$first[289:288] ; - assign cr_reserved__h866049 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h904123 = coreFix_aluExe_0_regToExeQ$first[289:288] ; - assign cr_reserved__h904671 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h865497 = coreFix_aluExe_1_regToExeQ$first[287] ; + assign cr_flags__h866045 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h904118 = coreFix_aluExe_0_regToExeQ$first[287] ; + assign cr_flags__h904666 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h865498 = coreFix_aluExe_1_regToExeQ$first[289:288] ; + assign cr_reserved__h866046 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h904119 = coreFix_aluExe_0_regToExeQ$first[289:288] ; + assign cr_reserved__h904667 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__039_BITS_13_TO_11_122_ULT_c_ETC___d4126 = - csrf_ddc_reg[13:11] < repBound__h248675 ; + csrf_ddc_reg[13:11] < repBound__h248673 ; assign csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125 = - csrf_ddc_reg[27:25] < repBound__h248675 ; + csrf_ddc_reg[27:25] < repBound__h248673 ; assign csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128 = - csrf_ddc_reg[85:83] < repBound__h248675 ; + csrf_ddc_reg[85:83] < repBound__h248673 ; assign csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4138 = { csrf_ddc_reg_read__039_BITS_85_TO_83_127_ULT_c_ETC___d4128, (csrf_ddc_reg_read__039_BITS_27_TO_25_124_ULT_c_ETC___d4125 == @@ -35133,13 +35133,13 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592 = - csrf_mtcc_reg[149:86] & mask__h997629 ; + csrf_mtcc_reg[149:86] & mask__h997624 ; assign csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22599 = - newAddrDiff__h997630 == mask__h997629 ; + newAddrDiff__h997625 == mask__h997624 ; assign csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22632 = - newAddrDiff__h997974 == mask__h997629 ; + newAddrDiff__h997969 == mask__h997624 ; assign csrf_mtcc_reg_read__6627_BITS_85_TO_83_2607_UL_ETC___d22610 = - csrf_mtcc_reg[85:83] < repBound__h997781 ; + csrf_mtcc_reg[85:83] < repBound__h997776 ; assign csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 = csrf_prv_reg_read__0079_ULE_1___d22385 && ((commitStage_commitTrap[44:43] == 2'd1) ? @@ -35148,50 +35148,50 @@ module mkCore(CLK, _0b0_CONCAT_csrf_mideleg_11_reg_read__6071_6072_ETC___d22415) ; assign csrf_prv_reg_read__0079_ULE_1___d22385 = csrf_prv_reg <= 2'd1 ; assign csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515 = - csrf_stcc_reg[149:86] & mask__h996972 ; + csrf_stcc_reg[149:86] & mask__h996967 ; assign csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22524 = - newAddrDiff__h996973 == mask__h996972 ; + newAddrDiff__h996968 == mask__h996967 ; assign csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22557 = - newAddrDiff__h997317 == mask__h996972 ; + newAddrDiff__h997312 == mask__h996967 ; assign csrf_stcc_reg_read__6618_BITS_85_TO_83_2532_UL_ETC___d22535 = - csrf_stcc_reg[85:83] < repBound__h997124 ; - assign data05760_BITS_31_TO_0__q25 = data__h705760[31:0] ; - assign data___1__h705460 = + csrf_stcc_reg[85:83] < repBound__h997119 ; + assign data05757_BITS_31_TO_0__q25 = data__h705757[31:0] ; + assign data___1__h705457 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q144 } ; - assign data___1__h706320 = - { {32{data05760_BITS_31_TO_0__q25[31]}}, - data05760_BITS_31_TO_0__q25 } ; - assign data__h567607 = + assign data___1__h706317 = + { {32{data05757_BITS_31_TO_0__q25[31]}}, + data05757_BITS_31_TO_0__q25 } ; + assign data__h567604 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h568170 : - res_data__h568165 ; - assign data__h613367 = + res_data__h568167 : + res_data__h568162 ; + assign data__h613364 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h613924 : - res_data__h613919 ; - assign data__h659114 = + res_data__h613921 : + res_data__h613916 ; + assign data__h659111 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h659671 : - res_data__h659666 ; - assign data__h704928 = + res_data__h659668 : + res_data__h659663 ; + assign data__h704925 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h705460 : + data___1__h705457 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12190 ; - assign data__h705760 = + assign data__h705757 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h705674 : - x_remainder__h705675 ; - assign data__h705791 = + x_quotient__h705671 : + x_remainder__h705672 ; + assign data__h705788 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h706320 : - data__h705760 ; - assign data_addrBits__h1013599 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1014453 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1013598 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1014452 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h991836 = + data___1__h706317 : + data__h705757 ; + assign data_addrBits__h1013593 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1014447 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1013592 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1014446 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h991831 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -35210,59 +35210,59 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h611525 = _theResult___fst_exp__h584492 + 8'd1 ; - assign din_inc___2_exp__h611549 = _theResult___fst_exp__h593148 + 8'd1 ; - assign din_inc___2_exp__h611579 = _theResult___fst_exp__h602258 + 8'd1 ; - assign din_inc___2_exp__h611603 = _theResult___fst_exp__h610943 + 8'd1 ; - assign din_inc___2_exp__h657274 = _theResult___fst_exp__h630241 + 8'd1 ; - assign din_inc___2_exp__h657298 = _theResult___fst_exp__h638897 + 8'd1 ; - assign din_inc___2_exp__h657328 = _theResult___fst_exp__h648007 + 8'd1 ; - assign din_inc___2_exp__h657352 = _theResult___fst_exp__h656692 + 8'd1 ; - assign din_inc___2_exp__h703021 = _theResult___fst_exp__h675988 + 8'd1 ; - assign din_inc___2_exp__h703045 = _theResult___fst_exp__h684644 + 8'd1 ; - assign din_inc___2_exp__h703075 = _theResult___fst_exp__h693754 + 8'd1 ; - assign din_inc___2_exp__h703099 = _theResult___fst_exp__h702439 + 8'd1 ; - assign din_inc___2_exp__h753463 = _theResult___fst_exp__h734213 + 11'd1 ; - assign din_inc___2_exp__h753498 = _theResult___fst_exp__h743790 + 11'd1 ; - assign din_inc___2_exp__h753524 = _theResult___fst_exp__h752623 + 11'd1 ; - assign din_inc___2_exp__h792316 = _theResult___fst_exp__h773066 + 11'd1 ; - assign din_inc___2_exp__h792351 = _theResult___fst_exp__h782643 + 11'd1 ; - assign din_inc___2_exp__h792377 = _theResult___fst_exp__h791476 + 11'd1 ; - assign din_inc___2_exp__h831620 = _theResult___fst_exp__h812370 + 11'd1 ; - assign din_inc___2_exp__h831655 = _theResult___fst_exp__h821947 + 11'd1 ; - assign din_inc___2_exp__h831681 = _theResult___fst_exp__h830780 + 11'd1 ; - assign enabled_ints___1__h918520 = pend_ints__h917993 & y__h918532 ; - assign enabled_ints__h918566 = - pend_ints__h917993 & - { r1__read_BITS_13_TO_0___h918542, csrf_mideleg_1_0_reg } ; - assign f1_exp14825_MINUS_127__q147 = f1_exp__h714825 - 8'd127 ; - assign f1_exp__h714825 = + assign din_inc___2_exp__h611522 = _theResult___fst_exp__h584489 + 8'd1 ; + assign din_inc___2_exp__h611546 = _theResult___fst_exp__h593145 + 8'd1 ; + assign din_inc___2_exp__h611576 = _theResult___fst_exp__h602255 + 8'd1 ; + assign din_inc___2_exp__h611600 = _theResult___fst_exp__h610940 + 8'd1 ; + assign din_inc___2_exp__h657271 = _theResult___fst_exp__h630238 + 8'd1 ; + assign din_inc___2_exp__h657295 = _theResult___fst_exp__h638894 + 8'd1 ; + assign din_inc___2_exp__h657325 = _theResult___fst_exp__h648004 + 8'd1 ; + assign din_inc___2_exp__h657349 = _theResult___fst_exp__h656689 + 8'd1 ; + assign din_inc___2_exp__h703018 = _theResult___fst_exp__h675985 + 8'd1 ; + assign din_inc___2_exp__h703042 = _theResult___fst_exp__h684641 + 8'd1 ; + assign din_inc___2_exp__h703072 = _theResult___fst_exp__h693751 + 8'd1 ; + assign din_inc___2_exp__h703096 = _theResult___fst_exp__h702436 + 8'd1 ; + assign din_inc___2_exp__h753460 = _theResult___fst_exp__h734210 + 11'd1 ; + assign din_inc___2_exp__h753495 = _theResult___fst_exp__h743787 + 11'd1 ; + assign din_inc___2_exp__h753521 = _theResult___fst_exp__h752620 + 11'd1 ; + assign din_inc___2_exp__h792313 = _theResult___fst_exp__h773063 + 11'd1 ; + assign din_inc___2_exp__h792348 = _theResult___fst_exp__h782640 + 11'd1 ; + assign din_inc___2_exp__h792374 = _theResult___fst_exp__h791473 + 11'd1 ; + assign din_inc___2_exp__h831617 = _theResult___fst_exp__h812367 + 11'd1 ; + assign din_inc___2_exp__h831652 = _theResult___fst_exp__h821944 + 11'd1 ; + assign din_inc___2_exp__h831678 = _theResult___fst_exp__h830777 + 11'd1 ; + assign enabled_ints___1__h918515 = pend_ints__h917988 & y__h918527 ; + assign enabled_ints__h918561 = + pend_ints__h917988 & + { r1__read_BITS_13_TO_0___h918537, csrf_mideleg_1_0_reg } ; + assign f1_exp14822_MINUS_127__q147 = f1_exp__h714822 - 8'd127 ; + assign f1_exp__h714822 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h714826 = + assign f1_sfd__h714823 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp53819_MINUS_127__q187 = f2_exp__h753819 - 8'd127 ; - assign f2_exp__h753819 = + assign f2_exp53816_MINUS_127__q187 = f2_exp__h753816 - 8'd127 ; + assign f2_exp__h753816 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h753820 = + assign f2_sfd__h753817 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp93123_MINUS_127__q164 = f3_exp__h793123 - 8'd127 ; - assign f3_exp__h793123 = + assign f3_exp93120_MINUS_127__q164 = f3_exp__h793120 - 8'd127 ; + assign f3_exp__h793120 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h793124 = + assign f3_sfd__h793121 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; @@ -35272,7 +35272,7 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h849072 = { 56'd0, x__h852690 } ; + assign fcsr_csr__read__h849069 = { 56'd0, x__h852687 } ; assign fetchStage_RDY_pipelines_0_first__0046_AND_fet_ETC___d21036 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[267:265] == 3'd1 && @@ -35546,83 +35546,83 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0058_BIT_180_122_ETC___d21324 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q258 } ; - assign fflags__h1011197 = + assign fflags__h1011192 = NOT_rob_deqPort_0_canDeq__3171_3172_OR_rob_deq_ETC___d23391 ? - y_avValue_snd_fst__h1011257 : + y_avValue_snd_fst__h1011252 : IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 ; - assign fflags_csr__read__h849047 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h849058 = { 61'd0, csrf_frm_reg } ; - assign guard__h576391 = - { IF_sfdin84486_BIT_33_THEN_2_ELSE_0__q40[1], - { sfdin__h584486[32:0], 23'd0 } != 56'd0 } ; - assign guard__h585100 = - { IF_theResult___snd93099_BIT_33_THEN_2_ELSE_0__q42[1], - { _theResult___snd__h593099[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594030 = - { IF_sfdin02252_BIT_33_THEN_2_ELSE_0__q50[1], - { sfdin__h602252[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594628 = x__h594730 != 57'd0 ; - assign guard__h602866 = - { IF_theResult___snd10889_BIT_33_THEN_2_ELSE_0__q55[1], - { _theResult___snd__h610889[32:0], 23'd0 } != 56'd0 } ; - assign guard__h622142 = - { IF_sfdin30235_BIT_33_THEN_2_ELSE_0__q75[1], - { sfdin__h630235[32:0], 23'd0 } != 56'd0 } ; - assign guard__h630849 = - { IF_theResult___snd38848_BIT_33_THEN_2_ELSE_0__q77[1], - { _theResult___snd__h638848[32:0], 23'd0 } != 56'd0 } ; - assign guard__h639779 = - { IF_sfdin48001_BIT_33_THEN_2_ELSE_0__q85[1], - { sfdin__h648001[32:0], 23'd0 } != 56'd0 } ; - assign guard__h640377 = x__h640479 != 57'd0 ; - assign guard__h648615 = - { IF_theResult___snd56638_BIT_33_THEN_2_ELSE_0__q90[1], - { _theResult___snd__h656638[32:0], 23'd0 } != 56'd0 } ; - assign guard__h667889 = - { IF_sfdin75982_BIT_33_THEN_2_ELSE_0__q110[1], - { sfdin__h675982[32:0], 23'd0 } != 56'd0 } ; - assign guard__h676596 = - { IF_theResult___snd84595_BIT_33_THEN_2_ELSE_0__q112[1], - { _theResult___snd__h684595[32:0], 23'd0 } != 56'd0 } ; - assign guard__h685526 = - { IF_sfdin93748_BIT_33_THEN_2_ELSE_0__q120[1], - { sfdin__h693748[32:0], 23'd0 } != 56'd0 } ; - assign guard__h686124 = x__h686226 != 57'd0 ; - assign guard__h694362 = - { IF_theResult___snd02385_BIT_33_THEN_2_ELSE_0__q125[1], - { _theResult___snd__h702385[32:0], 23'd0 } != 56'd0 } ; - assign guard__h726252 = - { IF_theResult___snd34164_BIT_4_THEN_2_ELSE_0__q146[1], - { _theResult___snd__h734164[3:0], 52'd0 } != 56'd0 } ; - assign guard__h735564 = - { IF_sfdin43784_BIT_4_THEN_2_ELSE_0__q150[1], - { sfdin__h743784[3:0], 52'd0 } != 56'd0 } ; - assign guard__h736162 = x__h736262 != 57'd0 ; - assign guard__h744633 = - { IF_theResult___snd52569_BIT_4_THEN_2_ELSE_0__q153[1], - { _theResult___snd__h752569[3:0], 52'd0 } != 56'd0 } ; - assign guard__h765105 = - { IF_theResult___snd73017_BIT_4_THEN_2_ELSE_0__q186[1], - { _theResult___snd__h773017[3:0], 52'd0 } != 56'd0 } ; - assign guard__h774417 = - { IF_sfdin82637_BIT_4_THEN_2_ELSE_0__q190[1], - { sfdin__h782637[3:0], 52'd0 } != 56'd0 } ; - assign guard__h775015 = x__h775115 != 57'd0 ; - assign guard__h783486 = - { IF_theResult___snd91422_BIT_4_THEN_2_ELSE_0__q193[1], - { _theResult___snd__h791422[3:0], 52'd0 } != 56'd0 } ; - assign guard__h804409 = - { IF_theResult___snd12321_BIT_4_THEN_2_ELSE_0__q163[1], - { _theResult___snd__h812321[3:0], 52'd0 } != 56'd0 } ; - assign guard__h813721 = - { IF_sfdin21941_BIT_4_THEN_2_ELSE_0__q167[1], - { sfdin__h821941[3:0], 52'd0 } != 56'd0 } ; - assign guard__h814319 = x__h814419 != 57'd0 ; - assign guard__h822790 = - { IF_theResult___snd30726_BIT_4_THEN_2_ELSE_0__q170[1], - { _theResult___snd__h830726[3:0], 52'd0 } != 56'd0 } ; - assign highOffsetBits__h242578 = x__h242605 & mask__h239806 ; - assign idx__h966426 = + assign fflags_csr__read__h849044 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h849055 = { 61'd0, csrf_frm_reg } ; + assign guard__h576388 = + { IF_sfdin84483_BIT_33_THEN_2_ELSE_0__q40[1], + { sfdin__h584483[32:0], 23'd0 } != 56'd0 } ; + assign guard__h585097 = + { IF_theResult___snd93096_BIT_33_THEN_2_ELSE_0__q42[1], + { _theResult___snd__h593096[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594027 = + { IF_sfdin02249_BIT_33_THEN_2_ELSE_0__q50[1], + { sfdin__h602249[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594625 = x__h594727 != 57'd0 ; + assign guard__h602863 = + { IF_theResult___snd10886_BIT_33_THEN_2_ELSE_0__q55[1], + { _theResult___snd__h610886[32:0], 23'd0 } != 56'd0 } ; + assign guard__h622139 = + { IF_sfdin30232_BIT_33_THEN_2_ELSE_0__q75[1], + { sfdin__h630232[32:0], 23'd0 } != 56'd0 } ; + assign guard__h630846 = + { IF_theResult___snd38845_BIT_33_THEN_2_ELSE_0__q77[1], + { _theResult___snd__h638845[32:0], 23'd0 } != 56'd0 } ; + assign guard__h639776 = + { IF_sfdin47998_BIT_33_THEN_2_ELSE_0__q85[1], + { sfdin__h647998[32:0], 23'd0 } != 56'd0 } ; + assign guard__h640374 = x__h640476 != 57'd0 ; + assign guard__h648612 = + { IF_theResult___snd56635_BIT_33_THEN_2_ELSE_0__q90[1], + { _theResult___snd__h656635[32:0], 23'd0 } != 56'd0 } ; + assign guard__h667886 = + { IF_sfdin75979_BIT_33_THEN_2_ELSE_0__q110[1], + { sfdin__h675979[32:0], 23'd0 } != 56'd0 } ; + assign guard__h676593 = + { IF_theResult___snd84592_BIT_33_THEN_2_ELSE_0__q112[1], + { _theResult___snd__h684592[32:0], 23'd0 } != 56'd0 } ; + assign guard__h685523 = + { IF_sfdin93745_BIT_33_THEN_2_ELSE_0__q120[1], + { sfdin__h693745[32:0], 23'd0 } != 56'd0 } ; + assign guard__h686121 = x__h686223 != 57'd0 ; + assign guard__h694359 = + { IF_theResult___snd02382_BIT_33_THEN_2_ELSE_0__q125[1], + { _theResult___snd__h702382[32:0], 23'd0 } != 56'd0 } ; + assign guard__h726249 = + { IF_theResult___snd34161_BIT_4_THEN_2_ELSE_0__q146[1], + { _theResult___snd__h734161[3:0], 52'd0 } != 56'd0 } ; + assign guard__h735561 = + { IF_sfdin43781_BIT_4_THEN_2_ELSE_0__q150[1], + { sfdin__h743781[3:0], 52'd0 } != 56'd0 } ; + assign guard__h736159 = x__h736259 != 57'd0 ; + assign guard__h744630 = + { IF_theResult___snd52566_BIT_4_THEN_2_ELSE_0__q153[1], + { _theResult___snd__h752566[3:0], 52'd0 } != 56'd0 } ; + assign guard__h765102 = + { IF_theResult___snd73014_BIT_4_THEN_2_ELSE_0__q186[1], + { _theResult___snd__h773014[3:0], 52'd0 } != 56'd0 } ; + assign guard__h774414 = + { IF_sfdin82634_BIT_4_THEN_2_ELSE_0__q190[1], + { sfdin__h782634[3:0], 52'd0 } != 56'd0 } ; + assign guard__h775012 = x__h775112 != 57'd0 ; + assign guard__h783483 = + { IF_theResult___snd91419_BIT_4_THEN_2_ELSE_0__q193[1], + { _theResult___snd__h791419[3:0], 52'd0 } != 56'd0 } ; + assign guard__h804406 = + { IF_theResult___snd12318_BIT_4_THEN_2_ELSE_0__q163[1], + { _theResult___snd__h812318[3:0], 52'd0 } != 56'd0 } ; + assign guard__h813718 = + { IF_sfdin21938_BIT_4_THEN_2_ELSE_0__q167[1], + { sfdin__h821938[3:0], 52'd0 } != 56'd0 } ; + assign guard__h814316 = x__h814416 != 57'd0 ; + assign guard__h822787 = + { IF_theResult___snd30723_BIT_4_THEN_2_ELSE_0__q170[1], + { _theResult___snd__h830723[3:0], 52'd0 } != 56'd0 } ; + assign highOffsetBits__h242577 = x__h242604 & mask__h239805 ; + assign idx__h966421 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21423 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -35630,82 +35630,82 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0049_BITS_267_TO_ETC___d21446) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__0978__ETC___d20980 ; - assign impliedTopBits__h127403 = x__h127487 + len_correction__h127402 ; - assign impliedTopBits__h140319 = x__h140403 + len_correction__h140318 ; - assign impliedTopBits__h183580 = x__h183664 + len_correction__h183579 ; - assign impliedTopBits__h202331 = x__h202415 + len_correction__h202330 ; - assign impliedTopBits__h216897 = x__h216981 + len_correction__h216896 ; - assign impliedTopBits__h865817 = x__h865902 + len_correction__h865816 ; - assign impliedTopBits__h866365 = x__h866450 + len_correction__h866364 ; - assign impliedTopBits__h904439 = x__h904524 + len_correction__h904438 ; - assign impliedTopBits__h904987 = x__h905072 + len_correction__h904986 ; - assign impliedTopBits__h992514 = x__h992598 + len_correction__h992513 ; - assign in__h239745 = coreFix_memExe_regToExeQ$first[382:317] & y__h239762 ; - assign in__h240902 = coreFix_memExe_regToExeQ$first[219:154] & y__h240919 ; - assign in__h254511 = coreFix_memExe_dTlb$procResp[452:387] & y__h254528 ; - assign in__h995128 = pc_address__h992211 & y__h995145 ; - assign k__h942684 = + assign impliedTopBits__h127402 = x__h127486 + len_correction__h127401 ; + assign impliedTopBits__h140318 = x__h140402 + len_correction__h140317 ; + assign impliedTopBits__h183579 = x__h183663 + len_correction__h183578 ; + assign impliedTopBits__h202330 = x__h202414 + len_correction__h202329 ; + assign impliedTopBits__h216896 = x__h216980 + len_correction__h216895 ; + assign impliedTopBits__h865814 = x__h865899 + len_correction__h865813 ; + assign impliedTopBits__h866362 = x__h866447 + len_correction__h866361 ; + assign impliedTopBits__h904435 = x__h904520 + len_correction__h904434 ; + assign impliedTopBits__h904983 = x__h905068 + len_correction__h904982 ; + assign impliedTopBits__h992509 = x__h992593 + len_correction__h992508 ; + assign in__h239744 = coreFix_memExe_regToExeQ$first[382:317] & y__h239761 ; + assign in__h240901 = coreFix_memExe_regToExeQ$first[219:154] & y__h240918 ; + assign in__h254509 = coreFix_memExe_dTlb$procResp[452:387] & y__h254526 ; + assign in__h995123 = pc_address__h992206 & y__h995140 ; + assign k__h942679 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__0978__ETC___d20980 ; - assign len_correction__h127402 = + assign len_correction__h127401 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? 2'b01 : 2'b0 ; - assign len_correction__h140318 = + assign len_correction__h140317 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h183579 = - INV_x83367_BITS_108_TO_90__q33[0] ? 2'b01 : 2'b0 ; - assign len_correction__h202330 = - INV_x99219_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; - assign len_correction__h216896 = + assign len_correction__h183578 = + INV_x83366_BITS_108_TO_90__q33[0] ? 2'b01 : 2'b0 ; + assign len_correction__h202329 = + INV_x99218_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; + assign len_correction__h216895 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h865816 = + assign len_correction__h865813 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h866364 = + assign len_correction__h866361 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h904438 = + assign len_correction__h904434 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h904986 = + assign len_correction__h904982 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign len_correction__h992513 = + assign len_correction__h992508 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? 2'b01 : 2'b0 ; - assign mask__h239806 = + assign mask__h239805 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign mask__h239915 = + assign mask__h239914 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign mask__h240963 = + assign mask__h240962 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign mask__h241072 = + assign mask__h241071 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign mask__h254572 = + assign mask__h254570 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h254681 = + assign mask__h254679 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h996972 = 64'hFFFFFFFFFFFFFFFF << x__h997033 ; - assign mask__h997629 = 64'hFFFFFFFFFFFFFFFF << x__h997690 ; - assign mcause_csr__read__h850488 = - { r1__read__h854142, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h850309 = - { r1__read__h854130, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h849989 = - { r1__read__h853996, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h850087 = - { r1__read__h854013, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h850214 = { r1__read__h854037, 1'b0 } ; - assign mip_csr__read__h850727 = { r1__read__h854149, 1'b0 } ; + assign mask__h996967 = 64'hFFFFFFFFFFFFFFFF << x__h997028 ; + assign mask__h997624 = 64'hFFFFFFFFFFFFFFFF << x__h997685 ; + assign mcause_csr__read__h850485 = + { r1__read__h854139, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h850306 = + { r1__read__h854127, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h849986 = + { r1__read__h853993, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h850084 = + { r1__read__h854010, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h850211 = { r1__read__h854034, 1'b0 } ; + assign mip_csr__read__h850724 = { r1__read__h854146, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20461 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -35747,28 +35747,28 @@ module mkCore(CLK, fetchStage$pipelines_0_first[272:268] != 5'd24 && fetchStage$pipelines_0_first[272:268] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h849835 = { r1__read__h853871, csrf_ie_vec_0 } ; - assign n__read__h1008993 = + assign mstatus_csr__read__h849832 = { r1__read__h853868, csrf_ie_vec_0 } ; + assign n__read__h1008988 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1009069 : + upd__h1009064 : csrf_minstret_ehr_data_rl ; assign n__read__h7877 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7946 : csrf_mcycle_ehr_data_rl ; - assign newAddrDiff__h996973 = + assign newAddrDiff__h996968 = csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515 - - (address__h996900 & mask__h996972) ; - assign newAddrDiff__h997317 = + (address__h996895 & mask__h996967) ; + assign newAddrDiff__h997312 = csrf_stcc_reg_read__6618_BITS_149_TO_86_2512_A_ETC___d22515 - - (base__h996861 & mask__h996972) ; - assign newAddrDiff__h997630 = + (base__h996856 & mask__h996967) ; + assign newAddrDiff__h997625 = csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592 - - (address__h996950 & mask__h997629) ; - assign newAddrDiff__h997974 = + (address__h996945 & mask__h997624) ; + assign newAddrDiff__h997969 = csrf_mtcc_reg_read__6627_BITS_149_TO_86_2589_A_ETC___d22592 - - (base__h996915 & mask__h997629) ; - assign new_pc__h871752 = + (base__h996910 & mask__h997624) ; + assign new_pc__h871748 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -35780,7 +35780,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17826[2], IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17826[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h909836 = + assign new_pc__h909831 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -35792,266 +35792,266 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19904[2], IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19904[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h515541 = + assign next_deqP___1__h515537 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h526318 = + assign next_deqP___1__h526314 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h533596 = + assign next_deqP___1__h533592 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h544231 = + assign next_deqP___1__h544227 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h557879 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h561658 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1007609 = + assign next_deqP___1__h557875 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h561654 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1007604 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1008563 } ; - assign offset__h239641 = + { rob$deqPort_0_deq_data[630:566], address__h1008558 } ; + assign offset__h239640 = { 2'd0, coreFix_memExe_regToExeQ$first[316:303] } - - base__h239640 ; - assign offset__h240798 = + base__h239639 ; + assign offset__h240797 = { 2'd0, coreFix_memExe_regToExeQ$first[153:140] } - - base__h240797 ; - assign offset__h242559 = + base__h240796 ; + assign offset__h242558 = { {32{coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16[31]}}, coreFix_memExe_regToExeQfirst_BITS_433_TO_402__q16 } ; - assign offset__h254407 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254406 ; - assign offset__h995047 = { 2'd0, pc_addrBits__h992212 } - base__h995046 ; - assign out___1_sfd__h714889 = { f1_sfd__h714826, 29'd0 } ; - assign out___1_sfd__h753883 = { f2_sfd__h753820, 29'd0 } ; - assign out___1_sfd__h793187 = { f3_sfd__h793124, 29'd0 } ; - assign out_exp__h585011 = - sfdin__h584486[34] ? - _theResult___exp__h585008 : - _theResult___fst_exp__h584492 ; - assign out_exp__h593593 = - _theResult___snd__h593099[34] ? - _theResult___exp__h593590 : - _theResult___fst_exp__h593148 ; - assign out_exp__h602777 = - sfdin__h602252[34] ? - _theResult___exp__h602774 : - _theResult___fst_exp__h602258 ; - assign out_exp__h611413 = - _theResult___snd__h610889[34] ? - _theResult___exp__h611410 : - _theResult___fst_exp__h610943 ; - assign out_exp__h630760 = - sfdin__h630235[34] ? - _theResult___exp__h630757 : - _theResult___fst_exp__h630241 ; - assign out_exp__h639342 = - _theResult___snd__h638848[34] ? - _theResult___exp__h639339 : - _theResult___fst_exp__h638897 ; - assign out_exp__h648526 = - sfdin__h648001[34] ? - _theResult___exp__h648523 : - _theResult___fst_exp__h648007 ; - assign out_exp__h657162 = - _theResult___snd__h656638[34] ? - _theResult___exp__h657159 : - _theResult___fst_exp__h656692 ; - assign out_exp__h676507 = - sfdin__h675982[34] ? - _theResult___exp__h676504 : - _theResult___fst_exp__h675988 ; - assign out_exp__h685089 = - _theResult___snd__h684595[34] ? - _theResult___exp__h685086 : - _theResult___fst_exp__h684644 ; - assign out_exp__h694273 = - sfdin__h693748[34] ? - _theResult___exp__h694270 : - _theResult___fst_exp__h693754 ; - assign out_exp__h702909 = - _theResult___snd__h702385[34] ? - _theResult___exp__h702906 : - _theResult___fst_exp__h702439 ; - assign out_exp__h734871 = - _theResult___snd__h734164[5] ? - _theResult___exp__h734868 : - _theResult___fst_exp__h734213 ; - assign out_exp__h744522 = - sfdin__h743784[5] ? - _theResult___exp__h744519 : - _theResult___fst_exp__h743790 ; - assign out_exp__h753306 = - _theResult___snd__h752569[5] ? - _theResult___exp__h753303 : - _theResult___fst_exp__h752623 ; - assign out_exp__h773724 = - _theResult___snd__h773017[5] ? - _theResult___exp__h773721 : - _theResult___fst_exp__h773066 ; - assign out_exp__h783375 = - sfdin__h782637[5] ? - _theResult___exp__h783372 : - _theResult___fst_exp__h782643 ; - assign out_exp__h792159 = - _theResult___snd__h791422[5] ? - _theResult___exp__h792156 : - _theResult___fst_exp__h791476 ; - assign out_exp__h813028 = - _theResult___snd__h812321[5] ? - _theResult___exp__h813025 : - _theResult___fst_exp__h812370 ; - assign out_exp__h822679 = - sfdin__h821941[5] ? - _theResult___exp__h822676 : - _theResult___fst_exp__h821947 ; - assign out_exp__h831463 = - _theResult___snd__h830726[5] ? - _theResult___exp__h831460 : - _theResult___fst_exp__h830780 ; - assign out_f_exp__h611789 = - (_theResult___exp__h611512 == 8'd255 && - _theResult___sfd__h611513 != 23'd0 || + assign offset__h254405 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254404 ; + assign offset__h995042 = { 2'd0, pc_addrBits__h992207 } - base__h995041 ; + assign out___1_sfd__h714886 = { f1_sfd__h714823, 29'd0 } ; + assign out___1_sfd__h753880 = { f2_sfd__h753817, 29'd0 } ; + assign out___1_sfd__h793184 = { f3_sfd__h793121, 29'd0 } ; + assign out_exp__h585008 = + sfdin__h584483[34] ? + _theResult___exp__h585005 : + _theResult___fst_exp__h584489 ; + assign out_exp__h593590 = + _theResult___snd__h593096[34] ? + _theResult___exp__h593587 : + _theResult___fst_exp__h593145 ; + assign out_exp__h602774 = + sfdin__h602249[34] ? + _theResult___exp__h602771 : + _theResult___fst_exp__h602255 ; + assign out_exp__h611410 = + _theResult___snd__h610886[34] ? + _theResult___exp__h611407 : + _theResult___fst_exp__h610940 ; + assign out_exp__h630757 = + sfdin__h630232[34] ? + _theResult___exp__h630754 : + _theResult___fst_exp__h630238 ; + assign out_exp__h639339 = + _theResult___snd__h638845[34] ? + _theResult___exp__h639336 : + _theResult___fst_exp__h638894 ; + assign out_exp__h648523 = + sfdin__h647998[34] ? + _theResult___exp__h648520 : + _theResult___fst_exp__h648004 ; + assign out_exp__h657159 = + _theResult___snd__h656635[34] ? + _theResult___exp__h657156 : + _theResult___fst_exp__h656689 ; + assign out_exp__h676504 = + sfdin__h675979[34] ? + _theResult___exp__h676501 : + _theResult___fst_exp__h675985 ; + assign out_exp__h685086 = + _theResult___snd__h684592[34] ? + _theResult___exp__h685083 : + _theResult___fst_exp__h684641 ; + assign out_exp__h694270 = + sfdin__h693745[34] ? + _theResult___exp__h694267 : + _theResult___fst_exp__h693751 ; + assign out_exp__h702906 = + _theResult___snd__h702382[34] ? + _theResult___exp__h702903 : + _theResult___fst_exp__h702436 ; + assign out_exp__h734868 = + _theResult___snd__h734161[5] ? + _theResult___exp__h734865 : + _theResult___fst_exp__h734210 ; + assign out_exp__h744519 = + sfdin__h743781[5] ? + _theResult___exp__h744516 : + _theResult___fst_exp__h743787 ; + assign out_exp__h753303 = + _theResult___snd__h752566[5] ? + _theResult___exp__h753300 : + _theResult___fst_exp__h752620 ; + assign out_exp__h773721 = + _theResult___snd__h773014[5] ? + _theResult___exp__h773718 : + _theResult___fst_exp__h773063 ; + assign out_exp__h783372 = + sfdin__h782634[5] ? + _theResult___exp__h783369 : + _theResult___fst_exp__h782640 ; + assign out_exp__h792156 = + _theResult___snd__h791419[5] ? + _theResult___exp__h792153 : + _theResult___fst_exp__h791473 ; + assign out_exp__h813025 = + _theResult___snd__h812318[5] ? + _theResult___exp__h813022 : + _theResult___fst_exp__h812367 ; + assign out_exp__h822676 = + sfdin__h821938[5] ? + _theResult___exp__h822673 : + _theResult___fst_exp__h821944 ; + assign out_exp__h831460 = + _theResult___snd__h830723[5] ? + _theResult___exp__h831457 : + _theResult___fst_exp__h830777 ; + assign out_f_exp__h611786 = + (_theResult___exp__h611509 == 8'd255 && + _theResult___sfd__h611510 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611503 ; - assign out_f_exp__h657538 = - (_theResult___exp__h657261 == 8'd255 && - _theResult___sfd__h657262 != 23'd0 || + _theResult___fst_exp__h611500 ; + assign out_f_exp__h657535 = + (_theResult___exp__h657258 == 8'd255 && + _theResult___sfd__h657259 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657252 ; - assign out_f_exp__h703285 = - (_theResult___exp__h703008 == 8'd255 && - _theResult___sfd__h703009 != 23'd0 || + _theResult___fst_exp__h657249 ; + assign out_f_exp__h703282 = + (_theResult___exp__h703005 == 8'd255 && + _theResult___sfd__h703006 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h702999 ; - assign out_f_sfd__h611790 = - (_theResult___exp__h611512 == 8'd255 && - _theResult___sfd__h611513 != 23'd0) ? + _theResult___fst_exp__h702996 ; + assign out_f_sfd__h611787 = + (_theResult___exp__h611509 == 8'd255 && + _theResult___sfd__h611510 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h611513 ; - assign out_f_sfd__h657539 = - (_theResult___exp__h657261 == 8'd255 && - _theResult___sfd__h657262 != 23'd0) ? + _theResult___sfd__h611510 ; + assign out_f_sfd__h657536 = + (_theResult___exp__h657258 == 8'd255 && + _theResult___sfd__h657259 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h657262 ; - assign out_f_sfd__h703286 = - (_theResult___exp__h703008 == 8'd255 && - _theResult___sfd__h703009 != 23'd0) ? + _theResult___sfd__h657259 ; + assign out_f_sfd__h703283 = + (_theResult___exp__h703005 == 8'd255 && + _theResult___sfd__h703006 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h703009 ; - assign out_sfd__h585012 = - sfdin__h584486[34] ? - _theResult___sfd__h585009 : - sfdin__h584486[56:34] ; - assign out_sfd__h593594 = - _theResult___snd__h593099[34] ? - _theResult___sfd__h593591 : - _theResult___snd__h593099[56:34] ; - assign out_sfd__h602778 = - sfdin__h602252[34] ? - _theResult___sfd__h602775 : - sfdin__h602252[56:34] ; - assign out_sfd__h611414 = - _theResult___snd__h610889[34] ? - _theResult___sfd__h611411 : - _theResult___snd__h610889[56:34] ; - assign out_sfd__h630761 = - sfdin__h630235[34] ? - _theResult___sfd__h630758 : - sfdin__h630235[56:34] ; - assign out_sfd__h639343 = - _theResult___snd__h638848[34] ? - _theResult___sfd__h639340 : - _theResult___snd__h638848[56:34] ; - assign out_sfd__h648527 = - sfdin__h648001[34] ? - _theResult___sfd__h648524 : - sfdin__h648001[56:34] ; - assign out_sfd__h657163 = - _theResult___snd__h656638[34] ? - _theResult___sfd__h657160 : - _theResult___snd__h656638[56:34] ; - assign out_sfd__h676508 = - sfdin__h675982[34] ? - _theResult___sfd__h676505 : - sfdin__h675982[56:34] ; - assign out_sfd__h685090 = - _theResult___snd__h684595[34] ? - _theResult___sfd__h685087 : - _theResult___snd__h684595[56:34] ; - assign out_sfd__h694274 = - sfdin__h693748[34] ? - _theResult___sfd__h694271 : - sfdin__h693748[56:34] ; - assign out_sfd__h702910 = - _theResult___snd__h702385[34] ? - _theResult___sfd__h702907 : - _theResult___snd__h702385[56:34] ; - assign out_sfd__h734872 = - _theResult___snd__h734164[5] ? - _theResult___sfd__h734869 : - _theResult___snd__h734164[56:5] ; - assign out_sfd__h744523 = - sfdin__h743784[5] ? - _theResult___sfd__h744520 : - sfdin__h743784[56:5] ; - assign out_sfd__h753307 = - _theResult___snd__h752569[5] ? - _theResult___sfd__h753304 : - _theResult___snd__h752569[56:5] ; - assign out_sfd__h773725 = - _theResult___snd__h773017[5] ? - _theResult___sfd__h773722 : - _theResult___snd__h773017[56:5] ; - assign out_sfd__h783376 = - sfdin__h782637[5] ? - _theResult___sfd__h783373 : - sfdin__h782637[56:5] ; - assign out_sfd__h792160 = - _theResult___snd__h791422[5] ? - _theResult___sfd__h792157 : - _theResult___snd__h791422[56:5] ; - assign out_sfd__h813029 = - _theResult___snd__h812321[5] ? - _theResult___sfd__h813026 : - _theResult___snd__h812321[56:5] ; - assign out_sfd__h822680 = - sfdin__h821941[5] ? - _theResult___sfd__h822677 : - sfdin__h821941[56:5] ; - assign out_sfd__h831464 = - _theResult___snd__h830726[5] ? - _theResult___sfd__h831461 : - _theResult___snd__h830726[56:5] ; - assign pc__h960829 = fetchStage$pipelines_1_first[590:462] ; - assign pc_addrBits__h992212 = + _theResult___sfd__h703006 ; + assign out_sfd__h585009 = + sfdin__h584483[34] ? + _theResult___sfd__h585006 : + sfdin__h584483[56:34] ; + assign out_sfd__h593591 = + _theResult___snd__h593096[34] ? + _theResult___sfd__h593588 : + _theResult___snd__h593096[56:34] ; + assign out_sfd__h602775 = + sfdin__h602249[34] ? + _theResult___sfd__h602772 : + sfdin__h602249[56:34] ; + assign out_sfd__h611411 = + _theResult___snd__h610886[34] ? + _theResult___sfd__h611408 : + _theResult___snd__h610886[56:34] ; + assign out_sfd__h630758 = + sfdin__h630232[34] ? + _theResult___sfd__h630755 : + sfdin__h630232[56:34] ; + assign out_sfd__h639340 = + _theResult___snd__h638845[34] ? + _theResult___sfd__h639337 : + _theResult___snd__h638845[56:34] ; + assign out_sfd__h648524 = + sfdin__h647998[34] ? + _theResult___sfd__h648521 : + sfdin__h647998[56:34] ; + assign out_sfd__h657160 = + _theResult___snd__h656635[34] ? + _theResult___sfd__h657157 : + _theResult___snd__h656635[56:34] ; + assign out_sfd__h676505 = + sfdin__h675979[34] ? + _theResult___sfd__h676502 : + sfdin__h675979[56:34] ; + assign out_sfd__h685087 = + _theResult___snd__h684592[34] ? + _theResult___sfd__h685084 : + _theResult___snd__h684592[56:34] ; + assign out_sfd__h694271 = + sfdin__h693745[34] ? + _theResult___sfd__h694268 : + sfdin__h693745[56:34] ; + assign out_sfd__h702907 = + _theResult___snd__h702382[34] ? + _theResult___sfd__h702904 : + _theResult___snd__h702382[56:34] ; + assign out_sfd__h734869 = + _theResult___snd__h734161[5] ? + _theResult___sfd__h734866 : + _theResult___snd__h734161[56:5] ; + assign out_sfd__h744520 = + sfdin__h743781[5] ? + _theResult___sfd__h744517 : + sfdin__h743781[56:5] ; + assign out_sfd__h753304 = + _theResult___snd__h752566[5] ? + _theResult___sfd__h753301 : + _theResult___snd__h752566[56:5] ; + assign out_sfd__h773722 = + _theResult___snd__h773014[5] ? + _theResult___sfd__h773719 : + _theResult___snd__h773014[56:5] ; + assign out_sfd__h783373 = + sfdin__h782634[5] ? + _theResult___sfd__h783370 : + sfdin__h782634[56:5] ; + assign out_sfd__h792157 = + _theResult___snd__h791419[5] ? + _theResult___sfd__h792154 : + _theResult___snd__h791419[56:5] ; + assign out_sfd__h813026 = + _theResult___snd__h812318[5] ? + _theResult___sfd__h813023 : + _theResult___snd__h812318[56:5] ; + assign out_sfd__h822677 = + sfdin__h821938[5] ? + _theResult___sfd__h822674 : + sfdin__h821938[56:5] ; + assign out_sfd__h831461 = + _theResult___snd__h830723[5] ? + _theResult___sfd__h831458 : + _theResult___snd__h830723[56:5] ; + assign pc__h960824 = fetchStage$pipelines_1_first[590:462] ; + assign pc_addrBits__h992207 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h992383[13:0] : + x__h992378[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h992211 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h917993 = + assign pc_address__h992206 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h917988 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6082_ETC___d20090, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h1005920 = { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign pointer__h1025233 = { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign pointer__h242569 = + assign pointer__h1005915 = { 2'd0, rob$deqPort_0_deq_data[95:32] } ; + assign pointer__h1025227 = { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign pointer__h242568 = coreFix_memExe_regToExeQ$first[382:317] + - { 2'd0, offset__h242559 } ; - assign prv__h1012290 = csrf_prv_reg ; - assign prv__h1012334 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h706385 = + { 2'd0, offset__h242558 } ; + assign prv__h1012285 = csrf_prv_reg ; + assign prv__h1012329 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h706382 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h918542 = + assign r1__read_BITS_13_TO_0___h918537 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -36059,117 +36059,117 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h924176 = csrf_fs_reg ; - assign r1__read_BIT_20___h924682 = csrf_tw_reg ; - assign r1__read__h852705 = { r1__read__h852707, csrf_ie_vec_1 } ; - assign r1__read__h852707 = { r1__read__h852709, 2'b0 } ; - assign r1__read__h852709 = { r1__read__h852711, csrf_prev_ie_vec_0 } ; - assign r1__read__h852711 = { r1__read__h852713, csrf_prev_ie_vec_1 } ; - assign r1__read__h852713 = { r1__read__h852715, 2'b0 } ; - assign r1__read__h852715 = { r1__read__h852717, csrf_spp_reg } ; - assign r1__read__h852717 = { r1__read__h852719, 4'b0 } ; - assign r1__read__h852719 = { r1__read__h852721, csrf_fs_reg } ; - assign r1__read__h852721 = { r1__read__h852723, 2'd0 } ; - assign r1__read__h852723 = { r1__read__h852725, 1'b0 } ; - assign r1__read__h852725 = { r1__read__h852727, csrf_sum_reg } ; - assign r1__read__h852727 = { r1__read__h852729, csrf_mxr_reg } ; - assign r1__read__h852729 = { r1__read__h852731, 12'b0 } ; - assign r1__read__h852731 = { r1__read__h852733, 2'b10 } ; - assign r1__read__h852733 = { r__h852737, 29'b0 } ; - assign r1__read__h853109 = - { r1__read__h853111, csrf_software_int_en_vec_1 } ; - assign r1__read__h853111 = { r1__read__h853113, 2'b0 } ; - assign r1__read__h853113 = { r1__read__h853115, 1'b0 } ; - assign r1__read__h853115 = { r1__read__h853117, csrf_timer_int_en_vec_1 } ; - assign r1__read__h853117 = { r1__read__h853119, 2'b0 } ; - assign r1__read__h853119 = { r1__read__h853121, 1'b0 } ; - assign r1__read__h853121 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h853619 = { r1__read__h853621, csrf_scounteren_tm_reg } ; - assign r1__read__h853621 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h853631 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h853638 = - { r1__read__h853640, csrf_software_int_pend_vec_1 } ; - assign r1__read__h853640 = { r1__read__h853642, 2'b0 } ; - assign r1__read__h853642 = { r1__read__h853644, 1'b0 } ; - assign r1__read__h853644 = - { r1__read__h853646, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h853646 = { r1__read__h853648, 2'b0 } ; - assign r1__read__h853648 = { r1__read__h853650, 1'b0 } ; - assign r1__read__h853650 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h853848 = { vm_mode_reg__read__h853854, 16'd0 } ; - assign r1__read__h853871 = { r1__read__h853873, csrf_ie_vec_1 } ; - assign r1__read__h853873 = { r1__read__h853875, 1'b0 } ; - assign r1__read__h853875 = { r1__read__h853877, csrf_ie_vec_3 } ; - assign r1__read__h853877 = { r1__read__h853879, csrf_prev_ie_vec_0 } ; - assign r1__read__h853879 = { r1__read__h853881, csrf_prev_ie_vec_1 } ; - assign r1__read__h853881 = { r1__read__h853883, 1'b0 } ; - assign r1__read__h853883 = { r1__read__h853885, csrf_prev_ie_vec_3 } ; - assign r1__read__h853885 = { r1__read__h853887, csrf_spp_reg } ; - assign r1__read__h853887 = { r1__read__h853889, 2'b0 } ; - assign r1__read__h853889 = { r1__read__h853891, csrf_mpp_reg } ; - assign r1__read__h853891 = { r1__read__h853893, csrf_fs_reg } ; - assign r1__read__h853893 = { r1__read__h853895, 2'd0 } ; - assign r1__read__h853895 = { r1__read__h853897, csrf_mprv_reg } ; - assign r1__read__h853897 = { r1__read__h853899, csrf_sum_reg } ; - assign r1__read__h853899 = { r1__read__h853901, csrf_mxr_reg } ; - assign r1__read__h853901 = { r1__read__h853903, csrf_tvm_reg } ; - assign r1__read__h853903 = { r1__read__h853905, csrf_tw_reg } ; - assign r1__read__h853905 = { r1__read__h853907, csrf_tsr_reg } ; - assign r1__read__h853907 = { r1__read__h853909, 9'b0 } ; - assign r1__read__h853909 = { r1__read__h853911, 2'b10 } ; - assign r1__read__h853911 = { r1__read__h853913, 2'b10 } ; - assign r1__read__h853913 = { r__h852737, 27'b0 } ; - assign r1__read__h853996 = { r1__read__h853998, 1'b0 } ; - assign r1__read__h853998 = { r1__read__h854000, csrf_medeleg_13_11_reg } ; - assign r1__read__h854000 = { r1__read__h854002, 1'b0 } ; - assign r1__read__h854002 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h854013 = { r1__read__h854015, 1'b0 } ; - assign r1__read__h854015 = { r1__read__h854017, csrf_mideleg_5_3_reg } ; - assign r1__read__h854017 = { r1__read__h854019, 1'b0 } ; - assign r1__read__h854019 = { r1__read__h854021, csrf_mideleg_9_7_reg } ; - assign r1__read__h854021 = { r1__read__h854023, 1'b0 } ; - assign r1__read__h854023 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h854037 = - { r1__read__h854039, csrf_software_int_en_vec_1 } ; - assign r1__read__h854039 = { r1__read__h854041, 1'b0 } ; - assign r1__read__h854041 = - { r1__read__h854043, csrf_software_int_en_vec_3 } ; - assign r1__read__h854043 = { r1__read__h854045, 1'b0 } ; - assign r1__read__h854045 = { r1__read__h854047, csrf_timer_int_en_vec_1 } ; - assign r1__read__h854047 = { r1__read__h854049, 1'b0 } ; - assign r1__read__h854049 = { r1__read__h854051, csrf_timer_int_en_vec_3 } ; - assign r1__read__h854051 = { r1__read__h854053, 1'b0 } ; - assign r1__read__h854053 = - { r1__read__h854055, csrf_external_int_en_vec_1 } ; - assign r1__read__h854055 = { r1__read__h854057, 1'b0 } ; - assign r1__read__h854057 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h854130 = { r1__read__h854132, csrf_mcounteren_tm_reg } ; - assign r1__read__h854132 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h854142 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h854149 = - { r1__read__h854151, csrf_software_int_pend_vec_1 } ; - assign r1__read__h854151 = { r1__read__h854153, 1'b0 } ; - assign r1__read__h854153 = - { r1__read__h854155, csrf_software_int_pend_vec_3 } ; - assign r1__read__h854155 = { r1__read__h854157, 1'b0 } ; - assign r1__read__h854157 = - { r1__read__h854159, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h854159 = { r1__read__h854161, 1'b0 } ; - assign r1__read__h854161 = - { r1__read__h854163, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h854163 = { r1__read__h854165, 1'b0 } ; - assign r1__read__h854165 = - { r1__read__h854167, csrf_external_int_pend_vec_1 } ; - assign r1__read__h854167 = { r1__read__h854169, 1'b0 } ; - assign r1__read__h854169 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h854478 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h714446 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h714447 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h706411 = + assign r1__read_BITS_13_TO_12___h924171 = csrf_fs_reg ; + assign r1__read_BIT_20___h924677 = csrf_tw_reg ; + assign r1__read__h852702 = { r1__read__h852704, csrf_ie_vec_1 } ; + assign r1__read__h852704 = { r1__read__h852706, 2'b0 } ; + assign r1__read__h852706 = { r1__read__h852708, csrf_prev_ie_vec_0 } ; + assign r1__read__h852708 = { r1__read__h852710, csrf_prev_ie_vec_1 } ; + assign r1__read__h852710 = { r1__read__h852712, 2'b0 } ; + assign r1__read__h852712 = { r1__read__h852714, csrf_spp_reg } ; + assign r1__read__h852714 = { r1__read__h852716, 4'b0 } ; + assign r1__read__h852716 = { r1__read__h852718, csrf_fs_reg } ; + assign r1__read__h852718 = { r1__read__h852720, 2'd0 } ; + assign r1__read__h852720 = { r1__read__h852722, 1'b0 } ; + assign r1__read__h852722 = { r1__read__h852724, csrf_sum_reg } ; + assign r1__read__h852724 = { r1__read__h852726, csrf_mxr_reg } ; + assign r1__read__h852726 = { r1__read__h852728, 12'b0 } ; + assign r1__read__h852728 = { r1__read__h852730, 2'b10 } ; + assign r1__read__h852730 = { r__h852734, 29'b0 } ; + assign r1__read__h853106 = + { r1__read__h853108, csrf_software_int_en_vec_1 } ; + assign r1__read__h853108 = { r1__read__h853110, 2'b0 } ; + assign r1__read__h853110 = { r1__read__h853112, 1'b0 } ; + assign r1__read__h853112 = { r1__read__h853114, csrf_timer_int_en_vec_1 } ; + assign r1__read__h853114 = { r1__read__h853116, 2'b0 } ; + assign r1__read__h853116 = { r1__read__h853118, 1'b0 } ; + assign r1__read__h853118 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h853616 = { r1__read__h853618, csrf_scounteren_tm_reg } ; + assign r1__read__h853618 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h853628 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h853635 = + { r1__read__h853637, csrf_software_int_pend_vec_1 } ; + assign r1__read__h853637 = { r1__read__h853639, 2'b0 } ; + assign r1__read__h853639 = { r1__read__h853641, 1'b0 } ; + assign r1__read__h853641 = + { r1__read__h853643, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h853643 = { r1__read__h853645, 2'b0 } ; + assign r1__read__h853645 = { r1__read__h853647, 1'b0 } ; + assign r1__read__h853647 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h853845 = { vm_mode_reg__read__h853851, 16'd0 } ; + assign r1__read__h853868 = { r1__read__h853870, csrf_ie_vec_1 } ; + assign r1__read__h853870 = { r1__read__h853872, 1'b0 } ; + assign r1__read__h853872 = { r1__read__h853874, csrf_ie_vec_3 } ; + assign r1__read__h853874 = { r1__read__h853876, csrf_prev_ie_vec_0 } ; + assign r1__read__h853876 = { r1__read__h853878, csrf_prev_ie_vec_1 } ; + assign r1__read__h853878 = { r1__read__h853880, 1'b0 } ; + assign r1__read__h853880 = { r1__read__h853882, csrf_prev_ie_vec_3 } ; + assign r1__read__h853882 = { r1__read__h853884, csrf_spp_reg } ; + assign r1__read__h853884 = { r1__read__h853886, 2'b0 } ; + assign r1__read__h853886 = { r1__read__h853888, csrf_mpp_reg } ; + assign r1__read__h853888 = { r1__read__h853890, csrf_fs_reg } ; + assign r1__read__h853890 = { r1__read__h853892, 2'd0 } ; + assign r1__read__h853892 = { r1__read__h853894, csrf_mprv_reg } ; + assign r1__read__h853894 = { r1__read__h853896, csrf_sum_reg } ; + assign r1__read__h853896 = { r1__read__h853898, csrf_mxr_reg } ; + assign r1__read__h853898 = { r1__read__h853900, csrf_tvm_reg } ; + assign r1__read__h853900 = { r1__read__h853902, csrf_tw_reg } ; + assign r1__read__h853902 = { r1__read__h853904, csrf_tsr_reg } ; + assign r1__read__h853904 = { r1__read__h853906, 9'b0 } ; + assign r1__read__h853906 = { r1__read__h853908, 2'b10 } ; + assign r1__read__h853908 = { r1__read__h853910, 2'b10 } ; + assign r1__read__h853910 = { r__h852734, 27'b0 } ; + assign r1__read__h853993 = { r1__read__h853995, 1'b0 } ; + assign r1__read__h853995 = { r1__read__h853997, csrf_medeleg_13_11_reg } ; + assign r1__read__h853997 = { r1__read__h853999, 1'b0 } ; + assign r1__read__h853999 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h854010 = { r1__read__h854012, 1'b0 } ; + assign r1__read__h854012 = { r1__read__h854014, csrf_mideleg_5_3_reg } ; + assign r1__read__h854014 = { r1__read__h854016, 1'b0 } ; + assign r1__read__h854016 = { r1__read__h854018, csrf_mideleg_9_7_reg } ; + assign r1__read__h854018 = { r1__read__h854020, 1'b0 } ; + assign r1__read__h854020 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h854034 = + { r1__read__h854036, csrf_software_int_en_vec_1 } ; + assign r1__read__h854036 = { r1__read__h854038, 1'b0 } ; + assign r1__read__h854038 = + { r1__read__h854040, csrf_software_int_en_vec_3 } ; + assign r1__read__h854040 = { r1__read__h854042, 1'b0 } ; + assign r1__read__h854042 = { r1__read__h854044, csrf_timer_int_en_vec_1 } ; + assign r1__read__h854044 = { r1__read__h854046, 1'b0 } ; + assign r1__read__h854046 = { r1__read__h854048, csrf_timer_int_en_vec_3 } ; + assign r1__read__h854048 = { r1__read__h854050, 1'b0 } ; + assign r1__read__h854050 = + { r1__read__h854052, csrf_external_int_en_vec_1 } ; + assign r1__read__h854052 = { r1__read__h854054, 1'b0 } ; + assign r1__read__h854054 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h854127 = { r1__read__h854129, csrf_mcounteren_tm_reg } ; + assign r1__read__h854129 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h854139 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h854146 = + { r1__read__h854148, csrf_software_int_pend_vec_1 } ; + assign r1__read__h854148 = { r1__read__h854150, 1'b0 } ; + assign r1__read__h854150 = + { r1__read__h854152, csrf_software_int_pend_vec_3 } ; + assign r1__read__h854152 = { r1__read__h854154, 1'b0 } ; + assign r1__read__h854154 = + { r1__read__h854156, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h854156 = { r1__read__h854158, 1'b0 } ; + assign r1__read__h854158 = + { r1__read__h854160, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h854160 = { r1__read__h854162, 1'b0 } ; + assign r1__read__h854162 = + { r1__read__h854164, csrf_external_int_pend_vec_1 } ; + assign r1__read__h854164 = { r1__read__h854166, 1'b0 } ; + assign r1__read__h854166 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h854475 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h714443 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h714444 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h706408 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h852737 = csrf_fs_reg == 2'b11 ; - assign r__h854224 = csrf_software_int_pend_vec_3 ; + assign r__h852734 = csrf_fs_reg == 2'b11 ; + assign r__h854221 = csrf_software_int_pend_vec_3 ; assign regRenamingTable_RDY_rename_0_getRename__0810__ETC___d20821 = regRenamingTable$RDY_rename_0_getRename && rob$RDY_enqPort_0_enq && @@ -36372,78 +36372,78 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20436[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h966287 = + assign renaming_spec_bits__h966282 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h960972 : + y_avValue_snd_fst__h960967 : specTagManager$currentSpecBits ; - assign repBoundBits__h242584 = + assign repBoundBits__h242583 = { coreFix_memExe_regToExeQ$first[230:228], 11'd0 } ; - assign repBound__h237262 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h238947 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h248150 = + assign repBound__h237261 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h238946 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h248148 = coreFix_memExe_regToExeQ$first[244:242] - 3'b001 ; - assign repBound__h248675 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h856058 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h859402 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h859420 = thin_bounds_baseBits__h859273[13:11] - 3'b001 ; - assign repBound__h865966 = x__h865905[13:11] - 3'b001 ; - assign repBound__h866514 = x__h866453[13:11] - 3'b001 ; - assign repBound__h896085 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h898412 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h898430 = thin_bounds_baseBits__h898315[13:11] - 3'b001 ; - assign repBound__h904588 = x__h904527[13:11] - 3'b001 ; - assign repBound__h905136 = x__h905075[13:11] - 3'b001 ; - assign repBound__h995071 = x__h992601[13:11] - 3'b001 ; - assign repBound__h997124 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h997781 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign res_addrBits__h126792 = + assign repBound__h248673 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h856055 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h859399 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h859417 = thin_bounds_baseBits__h859270[13:11] - 3'b001 ; + assign repBound__h865963 = x__h865902[13:11] - 3'b001 ; + assign repBound__h866511 = x__h866450[13:11] - 3'b001 ; + assign repBound__h896081 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h898408 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h898426 = thin_bounds_baseBits__h898311[13:11] - 3'b001 ; + assign repBound__h904584 = x__h904523[13:11] - 3'b001 ; + assign repBound__h905132 = x__h905071[13:11] - 3'b001 ; + assign repBound__h995066 = x__h992596[13:11] - 3'b001 ; + assign repBound__h997119 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h997776 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign res_addrBits__h126791 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127272[13:0] : + x__h127271[13:0] : coreFix_memExe_respLrScAmoQ_data_0[13:0] ; - assign res_addrBits__h139704 = + assign res_addrBits__h139703 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? - x__h140188[13:0] : + x__h140187[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h178867 = - INV_x83367_BITS_108_TO_90__q33[0] ? - x__h183449[13:0] : - x__h183367[13:0] ; - assign res_addrBits__h197632 = - INV_x99219_BITS_108_TO_90__q35[0] ? - x__h202200[13:0] : - x__h199219[13:0] ; - assign res_addrBits__h216391 = + assign res_addrBits__h178866 = + INV_x83366_BITS_108_TO_90__q33[0] ? + x__h183448[13:0] : + x__h183366[13:0] ; + assign res_addrBits__h197631 = + INV_x99218_BITS_108_TO_90__q35[0] ? + x__h202199[13:0] : + x__h199218[13:0] ; + assign res_addrBits__h216390 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? - x__h216766[13:0] : + x__h216765[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h235268 = { 2'b0, addr__h235261[63:52] } ; - assign res_addrBits__h567274 = + assign res_addrBits__h235267 = { 2'b0, addr__h235260[63:52] } ; + assign res_addrBits__h567270 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; - assign res_addrBits__h568126 = { 2'b0, data__h567607[63:52] } ; - assign res_addrBits__h613883 = { 2'b0, data__h613367[63:52] } ; - assign res_addrBits__h659630 = { 2'b0, data__h659114[63:52] } ; - assign res_addrBits__h705439 = { 2'b0, data__h704928[63:52] } ; - assign res_addrBits__h706299 = { 2'b0, data__h705791[63:52] } ; - assign res_addrBits__h848498 = { 2'b0, addr__h843840[63:52] } ; - assign res_addrBits__h890899 = { 2'b0, addr__h886249[63:52] } ; - assign res_address__h126791 = + assign res_addrBits__h568123 = { 2'b0, data__h567604[63:52] } ; + assign res_addrBits__h613880 = { 2'b0, data__h613364[63:52] } ; + assign res_addrBits__h659627 = { 2'b0, data__h659111[63:52] } ; + assign res_addrBits__h705436 = { 2'b0, data__h704925[63:52] } ; + assign res_addrBits__h706296 = { 2'b0, data__h705788[63:52] } ; + assign res_addrBits__h848495 = { 2'b0, addr__h843837[63:52] } ; + assign res_addrBits__h890895 = { 2'b0, addr__h886245[63:52] } ; + assign res_address__h126790 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; - assign res_address__h139703 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h178866 = { 2'd0, x__h183367[63:0] } ; - assign res_address__h197631 = { 2'd0, x__h199219[63:0] } ; - assign res_address__h216390 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h235267 = { 2'd0, addr__h235261 } ; - assign res_address__h567273 = + assign res_address__h139702 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; + assign res_address__h178865 = { 2'd0, x__h183366[63:0] } ; + assign res_address__h197630 = { 2'd0, x__h199218[63:0] } ; + assign res_address__h216389 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h235266 = { 2'd0, addr__h235260 } ; + assign res_address__h567269 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; - assign res_address__h568125 = { 2'd0, data__h567607 } ; - assign res_address__h613882 = { 2'd0, data__h613367 } ; - assign res_address__h659629 = { 2'd0, data__h659114 } ; - assign res_address__h705438 = { 2'd0, data__h704928 } ; - assign res_address__h706298 = { 2'd0, data__h705791 } ; - assign res_address__h848497 = { 2'd0, addr__h843840 } ; - assign res_address__h890898 = { 2'd0, addr__h886249 } ; - assign res_data__h568165 = { 32'hFFFFFFFF, x__h568180 } ; - assign res_data__h568170 = + assign res_address__h568122 = { 2'd0, data__h567604 } ; + assign res_address__h613879 = { 2'd0, data__h613364 } ; + assign res_address__h659626 = { 2'd0, data__h659111 } ; + assign res_address__h705435 = { 2'd0, data__h704925 } ; + assign res_address__h706295 = { 2'd0, data__h705788 } ; + assign res_address__h848494 = { 2'd0, addr__h843837 } ; + assign res_address__h890894 = { 2'd0, addr__h886245 } ; + assign res_data__h568162 = { 32'hFFFFFFFF, x__h568177 } ; + assign res_data__h568167 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -36456,8 +36456,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h613919 = { 32'hFFFFFFFF, x__h613934 } ; - assign res_data__h613924 = + assign res_data__h613916 = { 32'hFFFFFFFF, x__h613931 } ; + assign res_data__h613921 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -36470,8 +36470,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h659666 = { 32'hFFFFFFFF, x__h659681 } ; - assign res_data__h659671 = + assign res_data__h659663 = { 32'hFFFFFFFF, x__h659678 } ; + assign res_data__h659668 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -36484,7 +36484,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h568166 = + assign res_fflags__h568163 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -36552,7 +36552,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9365 } ; - assign res_fflags__h613920 = + assign res_fflags__h613917 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -36620,7 +36620,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10762 } ; - assign res_fflags__h659667 = + assign res_fflags__h659664 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -36688,69 +36688,69 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12159 } ; - assign resp_addr__h509039 = + assign resp_addr__h509036 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[53:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[168:158] } ; - assign result__h240541 = + assign result__h240540 = { 1'd0, ~coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64], coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[63:0] } ; - assign result__h241698 = + assign result__h241697 = { 1'd0, ~coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64], coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[63:0] } ; - assign result__h255307 = + assign result__h255305 = { 1'd0, ~coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64], coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[63:0] } ; - assign result__h594633 = + assign result__h594630 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8663[0] | - guard__h594628 } ; - assign result__h640382 = + guard__h594625 } ; + assign result__h640379 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10060[0] | - guard__h640377 } ; - assign result__h686129 = + guard__h640374 } ; + assign result__h686126 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11457[0] | - guard__h686124 } ; - assign result__h736167 = + guard__h686121 } ; + assign result__h736164 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12786[0] | - guard__h736162 } ; - assign result__h775020 = + guard__h736159 } ; + assign result__h775017 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14271[0] | - guard__h775015 } ; - assign result__h814324 = + guard__h775012 } ; + assign result__h814321 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13501[0] | - guard__h814319 } ; - assign result__h913573 = w__h913568 & y__h913602 ; - assign result__h913624 = ~x__h913623 ; - assign result_d_address__h242780 = { 2'd0, pointer__h242569[63:0] } ; - assign ret__h239918 = + guard__h814316 } ; + assign result__h913568 = w__h913563 & y__h913597 ; + assign result__h913619 = ~x__h913618 ; + assign result_d_address__h242779 = { 2'd0, pointer__h242568[63:0] } ; + assign ret__h239917 = { 1'd0, coreFix_memExe_regToExeQ_first__633_BITS_382_T_ETC___d3692[64:0] } ; - assign ret__h241075 = + assign ret__h241074 = { 1'd0, coreFix_memExe_regToExeQ_first__633_BITS_219_T_ETC___d3754[64:0] } ; - assign ret__h254684 = + assign ret__h254682 = { 1'd0, coreFix_memExe_dTlb_procResp__239_BITS_452_TO__ETC___d4389[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18901 = - rf$read_0_rd1[27:25] < repBound__h896085 ; + rf$read_0_rd1[27:25] < repBound__h896081 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18914 = - rf$read_0_rd1[13:11] < repBound__h896085 ; + rf$read_0_rd1[13:11] < repBound__h896081 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18928 = - rf$read_0_rd1[85:83] < repBound__h896085 ; + rf$read_0_rd1[85:83] < repBound__h896081 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18972 = - rf$read_0_rd2[27:25] < repBound__h898412 ; + rf$read_0_rd2[27:25] < repBound__h898408 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18973 = - rf$read_0_rd2[13:11] < repBound__h898412 ; + rf$read_0_rd2[13:11] < repBound__h898408 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18975 = - rf$read_0_rd2[85:83] < repBound__h898412 ; + rf$read_0_rd2[85:83] < repBound__h898408 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18985 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18975, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d18972 == @@ -36768,17 +36768,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16517 = - rf$read_1_rd1[27:25] < repBound__h856058 ; + rf$read_1_rd1[27:25] < repBound__h856055 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16530 = - rf$read_1_rd1[13:11] < repBound__h856058 ; + rf$read_1_rd1[13:11] < repBound__h856055 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16544 = - rf$read_1_rd1[85:83] < repBound__h856058 ; + rf$read_1_rd1[85:83] < repBound__h856055 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588 = - rf$read_1_rd2[27:25] < repBound__h859402 ; + rf$read_1_rd2[27:25] < repBound__h859399 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16589 = - rf$read_1_rd2[13:11] < repBound__h859402 ; + rf$read_1_rd2[13:11] < repBound__h859399 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16591 = - rf$read_1_rd2[85:83] < repBound__h859402 ; + rf$read_1_rd2[85:83] < repBound__h859399 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16601 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16591, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16588 == @@ -36796,25 +36796,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3319 = - rf$read_3_rd1[27:25] < repBound__h237262 ; + rf$read_3_rd1[27:25] < repBound__h237261 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3332 = - rf$read_3_rd1[13:11] < repBound__h237262 ; + rf$read_3_rd1[13:11] < repBound__h237261 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3346 = - rf$read_3_rd1[85:83] < repBound__h237262 ; + rf$read_3_rd1[85:83] < repBound__h237261 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3580 = - rf$read_3_rd2[27:25] < repBound__h238947 ; + rf$read_3_rd2[27:25] < repBound__h238946 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3588 = - rf$read_3_rd2[13:11] < repBound__h238947 ; + rf$read_3_rd2[13:11] < repBound__h238946 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3597 = - rf$read_3_rd2[85:83] < repBound__h238947 ; + rf$read_3_rd2[85:83] < repBound__h238946 ; assign rg_core_run_state_read__0464_EQ_2_0465_AND_NOT_ETC___d23466 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h851828 = - { r1__read__h854478, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h851825 = + { r1__read__h854475, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1405_AND_epochManager_ch_ETC___d21410 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -36824,7 +36824,7 @@ module mkCore(CLK, IF_IF_fetchStage_pipelines_0_first__0049_BITS__ETC___d21013) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q326 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h849689 = { r1__read__h853848, csrf_ppn_reg } ; + assign satp_csr__read__h849686 = { r1__read__h853845, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12424 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12380 && @@ -36844,272 +36844,272 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__679_AN_ETC___d2742 && IF_NOT_coreFix_memExe_bypassWire_0_whas__698_7_ETC___d2759) ; - assign sbIdx__h151985 = + assign sbIdx__h151984 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h849486 = - { r1__read__h853631, csrf_scause_code_reg } ; - assign scounteren_csr__read__h849391 = - { r1__read__h853619, csrf_scounteren_cy_reg } ; - assign sfd__h568776 = { value__h577003, 3'd0 } ; - assign sfd__h584584 = + assign scause_csr__read__h849483 = + { r1__read__h853628, csrf_scause_code_reg } ; + assign scounteren_csr__read__h849388 = + { r1__read__h853616, csrf_scounteren_cy_reg } ; + assign sfd__h568773 = { value__h577000, 3'd0 } ; + assign sfd__h584581 = { 1'b0, - _theResult___fst_exp__h584492 != 8'd0, - sfdin__h584486[56:34] } + + _theResult___fst_exp__h584489 != 8'd0, + sfdin__h584483[56:34] } + 25'd1 ; - assign sfd__h593166 = + assign sfd__h593163 = { 1'b0, - _theResult___fst_exp__h593148 != 8'd0, - _theResult___snd__h593099[56:34] } + + _theResult___fst_exp__h593145 != 8'd0, + _theResult___snd__h593096[56:34] } + 25'd1 ; - assign sfd__h602350 = + assign sfd__h602347 = { 1'b0, - _theResult___fst_exp__h602258 != 8'd0, - sfdin__h602252[56:34] } + + _theResult___fst_exp__h602255 != 8'd0, + sfdin__h602249[56:34] } + 25'd1 ; - assign sfd__h610962 = + assign sfd__h610959 = { 1'b0, - _theResult___fst_exp__h610943 != 8'd0, - _theResult___snd__h610889[56:34] } + + _theResult___fst_exp__h610940 != 8'd0, + _theResult___snd__h610886[56:34] } + 25'd1 ; - assign sfd__h614530 = { value__h622752, 3'd0 } ; - assign sfd__h630333 = + assign sfd__h614527 = { value__h622749, 3'd0 } ; + assign sfd__h630330 = { 1'b0, - _theResult___fst_exp__h630241 != 8'd0, - sfdin__h630235[56:34] } + + _theResult___fst_exp__h630238 != 8'd0, + sfdin__h630232[56:34] } + 25'd1 ; - assign sfd__h638915 = + assign sfd__h638912 = { 1'b0, - _theResult___fst_exp__h638897 != 8'd0, - _theResult___snd__h638848[56:34] } + + _theResult___fst_exp__h638894 != 8'd0, + _theResult___snd__h638845[56:34] } + 25'd1 ; - assign sfd__h648099 = + assign sfd__h648096 = { 1'b0, - _theResult___fst_exp__h648007 != 8'd0, - sfdin__h648001[56:34] } + + _theResult___fst_exp__h648004 != 8'd0, + sfdin__h647998[56:34] } + 25'd1 ; - assign sfd__h656711 = + assign sfd__h656708 = { 1'b0, - _theResult___fst_exp__h656692 != 8'd0, - _theResult___snd__h656638[56:34] } + + _theResult___fst_exp__h656689 != 8'd0, + _theResult___snd__h656635[56:34] } + 25'd1 ; - assign sfd__h660277 = { value__h668499, 3'd0 } ; - assign sfd__h676080 = + assign sfd__h660274 = { value__h668496, 3'd0 } ; + assign sfd__h676077 = { 1'b0, - _theResult___fst_exp__h675988 != 8'd0, - sfdin__h675982[56:34] } + + _theResult___fst_exp__h675985 != 8'd0, + sfdin__h675979[56:34] } + 25'd1 ; - assign sfd__h684662 = + assign sfd__h684659 = { 1'b0, - _theResult___fst_exp__h684644 != 8'd0, - _theResult___snd__h684595[56:34] } + + _theResult___fst_exp__h684641 != 8'd0, + _theResult___snd__h684592[56:34] } + 25'd1 ; - assign sfd__h693846 = + assign sfd__h693843 = { 1'b0, - _theResult___fst_exp__h693754 != 8'd0, - sfdin__h693748[56:34] } + + _theResult___fst_exp__h693751 != 8'd0, + sfdin__h693745[56:34] } + 25'd1 ; - assign sfd__h702458 = + assign sfd__h702455 = { 1'b0, - _theResult___fst_exp__h702439 != 8'd0, - _theResult___snd__h702385[56:34] } + + _theResult___fst_exp__h702436 != 8'd0, + _theResult___snd__h702382[56:34] } + 25'd1 ; - assign sfd__h715187 = { value__h719770, 32'd0 } ; - assign sfd__h734231 = + assign sfd__h715184 = { value__h719767, 32'd0 } ; + assign sfd__h734228 = { 1'b0, - _theResult___fst_exp__h734213 != 11'd0, - _theResult___snd__h734164[56:5] } + + _theResult___fst_exp__h734210 != 11'd0, + _theResult___snd__h734161[56:5] } + 54'd1 ; - assign sfd__h743882 = + assign sfd__h743879 = { 1'b0, - _theResult___fst_exp__h743790 != 11'd0, - sfdin__h743784[56:5] } + + _theResult___fst_exp__h743787 != 11'd0, + sfdin__h743781[56:5] } + 54'd1 ; - assign sfd__h752642 = + assign sfd__h752639 = { 1'b0, - _theResult___fst_exp__h752623 != 11'd0, - _theResult___snd__h752569[56:5] } + + _theResult___fst_exp__h752620 != 11'd0, + _theResult___snd__h752566[56:5] } + 54'd1 ; - assign sfd__h754181 = { value__h758623, 32'd0 } ; - assign sfd__h773084 = + assign sfd__h754178 = { value__h758620, 32'd0 } ; + assign sfd__h773081 = { 1'b0, - _theResult___fst_exp__h773066 != 11'd0, - _theResult___snd__h773017[56:5] } + + _theResult___fst_exp__h773063 != 11'd0, + _theResult___snd__h773014[56:5] } + 54'd1 ; - assign sfd__h782735 = + assign sfd__h782732 = { 1'b0, - _theResult___fst_exp__h782643 != 11'd0, - sfdin__h782637[56:5] } + + _theResult___fst_exp__h782640 != 11'd0, + sfdin__h782634[56:5] } + 54'd1 ; - assign sfd__h791495 = + assign sfd__h791492 = { 1'b0, - _theResult___fst_exp__h791476 != 11'd0, - _theResult___snd__h791422[56:5] } + + _theResult___fst_exp__h791473 != 11'd0, + _theResult___snd__h791419[56:5] } + 54'd1 ; - assign sfd__h793485 = { value__h797927, 32'd0 } ; - assign sfd__h812388 = + assign sfd__h793482 = { value__h797924, 32'd0 } ; + assign sfd__h812385 = { 1'b0, - _theResult___fst_exp__h812370 != 11'd0, - _theResult___snd__h812321[56:5] } + + _theResult___fst_exp__h812367 != 11'd0, + _theResult___snd__h812318[56:5] } + 54'd1 ; - assign sfd__h822039 = + assign sfd__h822036 = { 1'b0, - _theResult___fst_exp__h821947 != 11'd0, - sfdin__h821941[56:5] } + + _theResult___fst_exp__h821944 != 11'd0, + sfdin__h821938[56:5] } + 54'd1 ; - assign sfd__h830799 = + assign sfd__h830796 = { 1'b0, - _theResult___fst_exp__h830780 != 11'd0, - _theResult___snd__h830726[56:5] } + + _theResult___fst_exp__h830777 != 11'd0, + _theResult___snd__h830723[56:5] } + 54'd1 ; - assign sfdin__h584486 = - _theResult____h576381[56] ? - _theResult___snd__h584503 : - _theResult___snd__h584514 ; - assign sfdin__h602252 = - _theResult____h594020[56] ? - _theResult___snd__h602269 : - _theResult___snd__h602280 ; - assign sfdin__h630235 = - _theResult____h622132[56] ? - _theResult___snd__h630252 : - _theResult___snd__h630263 ; - assign sfdin__h648001 = - _theResult____h639769[56] ? - _theResult___snd__h648018 : - _theResult___snd__h648029 ; - assign sfdin__h675982 = - _theResult____h667879[56] ? - _theResult___snd__h675999 : - _theResult___snd__h676010 ; - assign sfdin__h693748 = - _theResult____h685516[56] ? - _theResult___snd__h693765 : - _theResult___snd__h693776 ; - assign sfdin__h743784 = - _theResult____h735554[56] ? - _theResult___snd__h743801 : - _theResult___snd__h743812 ; - assign sfdin__h782637 = - _theResult____h774407[56] ? - _theResult___snd__h782654 : - _theResult___snd__h782665 ; - assign sfdin__h821941 = - _theResult____h813711[56] ? - _theResult___snd__h821958 : - _theResult___snd__h821969 ; - assign sie_csr__read__h849338 = { r1__read__h853109, 1'b0 } ; - assign signBits__h242575 = {50{offset__h242559[63]}} ; - assign sip_csr__read__h849626 = { r1__read__h853638, 1'b0 } ; - assign spec_bits__h971306 = specTagManager$currentSpecBits | y__h971319 ; - assign sstatus_csr__read__h849268 = { r1__read__h852705, csrf_ie_vec_0 } ; - assign tb__h865963 = { impliedTopBits__h865817, topBits__h865813[11] } ; - assign tb__h866511 = { impliedTopBits__h866365, topBits__h866361[11] } ; - assign tb__h904585 = { impliedTopBits__h904439, topBits__h904435[11] } ; - assign tb__h905133 = { impliedTopBits__h904987, topBits__h904983[11] } ; - assign thin_address__h996854 = + assign sfdin__h584483 = + _theResult____h576378[56] ? + _theResult___snd__h584500 : + _theResult___snd__h584511 ; + assign sfdin__h602249 = + _theResult____h594017[56] ? + _theResult___snd__h602266 : + _theResult___snd__h602277 ; + assign sfdin__h630232 = + _theResult____h622129[56] ? + _theResult___snd__h630249 : + _theResult___snd__h630260 ; + assign sfdin__h647998 = + _theResult____h639766[56] ? + _theResult___snd__h648015 : + _theResult___snd__h648026 ; + assign sfdin__h675979 = + _theResult____h667876[56] ? + _theResult___snd__h675996 : + _theResult___snd__h676007 ; + assign sfdin__h693745 = + _theResult____h685513[56] ? + _theResult___snd__h693762 : + _theResult___snd__h693773 ; + assign sfdin__h743781 = + _theResult____h735551[56] ? + _theResult___snd__h743798 : + _theResult___snd__h743809 ; + assign sfdin__h782634 = + _theResult____h774404[56] ? + _theResult___snd__h782651 : + _theResult___snd__h782662 ; + assign sfdin__h821938 = + _theResult____h813708[56] ? + _theResult___snd__h821955 : + _theResult___snd__h821966 ; + assign sie_csr__read__h849335 = { r1__read__h853106, 1'b0 } ; + assign signBits__h242574 = {50{offset__h242558[63]}} ; + assign sip_csr__read__h849623 = { r1__read__h853635, 1'b0 } ; + assign spec_bits__h971301 = specTagManager$currentSpecBits | y__h971314 ; + assign sstatus_csr__read__h849265 = { r1__read__h852702, csrf_ie_vec_0 } ; + assign tb__h865960 = { impliedTopBits__h865814, topBits__h865810[11] } ; + assign tb__h866508 = { impliedTopBits__h866362, topBits__h866358[11] } ; + assign tb__h904581 = { impliedTopBits__h904435, topBits__h904431[11] } ; + assign tb__h905129 = { impliedTopBits__h904983, topBits__h904979[11] } ; + assign thin_address__h996849 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? IF_csrf_stcc_reg_read__6618_BIT_86_2507_AND_NO_ETC___d22687 : IF_csrf_mtcc_reg_read__6627_BIT_86_2584_AND_NO_ETC___d22688 ; - assign tmpAddr__h242768 = pointer__h242569[63:0] ; - assign tmp_expBotHalf__h127265 = + assign tmpAddr__h242767 = pointer__h242568[63:0] ; + assign tmp_expBotHalf__h127264 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign tmp_expBotHalf__h140181 = + assign tmp_expBotHalf__h140180 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h183442 = { ~x__h183367[66], x__h183367[65:64] } ; - assign tmp_expBotHalf__h202193 = { ~x__h199219[66], x__h199219[65:64] } ; - assign tmp_expBotHalf__h216759 = + assign tmp_expBotHalf__h183441 = { ~x__h183366[66], x__h183366[65:64] } ; + assign tmp_expBotHalf__h202192 = { ~x__h199218[66], x__h199218[65:64] } ; + assign tmp_expBotHalf__h216758 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h865666 = + assign tmp_expBotHalf__h865663 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h866214 = + assign tmp_expBotHalf__h866211 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h904288 = + assign tmp_expBotHalf__h904284 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h904836 = + assign tmp_expBotHalf__h904832 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h992376 = + assign tmp_expBotHalf__h992371 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign tmp_expTopHalf__h127263 = + assign tmp_expTopHalf__h127262 = { ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign tmp_expTopHalf__h140179 = + assign tmp_expTopHalf__h140178 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h183440 = { ~x__h183367[80:79], x__h183367[78] } ; - assign tmp_expTopHalf__h202191 = { ~x__h199219[80:79], x__h199219[78] } ; - assign tmp_expTopHalf__h216757 = + assign tmp_expTopHalf__h183439 = { ~x__h183366[80:79], x__h183366[78] } ; + assign tmp_expTopHalf__h202190 = { ~x__h199218[80:79], x__h199218[78] } ; + assign tmp_expTopHalf__h216756 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h865664 = + assign tmp_expTopHalf__h865661 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h866212 = + assign tmp_expTopHalf__h866209 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h904286 = + assign tmp_expTopHalf__h904282 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h904834 = + assign tmp_expTopHalf__h904830 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h992374 = + assign tmp_expTopHalf__h992369 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign toBoundsM1__h242588 = - repBoundBits__h242584 + + assign toBoundsM1__h242587 = + repBoundBits__h242583 + ~coreFix_memExe_regToExeQ$first[316:303] ; - assign toBounds__h242587 = - repBoundBits__h242584 - coreFix_memExe_regToExeQ$first[316:303] ; - assign topBits__h127399 = + assign toBounds__h242586 = + repBoundBits__h242583 - coreFix_memExe_regToExeQ$first[316:303] ; + assign topBits__h127398 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : - b_top__h127496 ; - assign topBits__h140315 = + b_top__h127495 ; + assign topBits__h140314 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : - b_top__h140412 ; - assign topBits__h183576 = - INV_x83367_BITS_108_TO_90__q33[0] ? - { x__h183367[89:81], 3'd0 } : - b_top__h183673 ; - assign topBits__h202327 = - INV_x99219_BITS_108_TO_90__q35[0] ? - { x__h199219[89:81], 3'd0 } : - b_top__h202424 ; - assign topBits__h216893 = + b_top__h140411 ; + assign topBits__h183575 = + INV_x83366_BITS_108_TO_90__q33[0] ? + { x__h183366[89:81], 3'd0 } : + b_top__h183672 ; + assign topBits__h202326 = + INV_x99218_BITS_108_TO_90__q35[0] ? + { x__h199218[89:81], 3'd0 } : + b_top__h202423 ; + assign topBits__h216892 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h216990 ; - assign topBits__h865813 = + b_top__h216989 ; + assign topBits__h865810 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h865911 ; - assign topBits__h866361 = + b_top__h865908 ; + assign topBits__h866358 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h866459 ; - assign topBits__h904435 = + b_top__h866456 ; + assign topBits__h904431 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h904533 ; - assign topBits__h904983 = + b_top__h904529 ; + assign topBits__h904979 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h905081 ; - assign topBits__h992510 = + b_top__h905077 ; + assign topBits__h992505 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h992607 ; - assign trap_val__h994512 = { 53'd0, x__h996333 } ; - assign upd__h1009069 = + b_top__h992602 ; + assign trap_val__h994507 = { 53'd0, x__h996328 } ; + assign upd__h1009064 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -37122,7 +37122,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1007648 = + assign v__h1007643 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], @@ -37134,7 +37134,7 @@ module mkCore(CLK, ~IF_csrf_sepcc_reg_read_wget__3089_BIT_34_3098__ETC___d23106[2], IF_csrf_sepcc_reg_read_wget__3089_BIT_34_3098__ETC___d23106[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1008101 = + assign v__h1008096 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], @@ -37146,308 +37146,308 @@ module mkCore(CLK, ~IF_csrf_mepcc_reg_read_wget__3118_BIT_34_3127__ETC___d23135[2], IF_csrf_mepcc_reg_read_wget__3118_BIT_34_3127__ETC___d23135[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h514752 = + assign v__h514748 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7209 ? - v__h514947 : + v__h514943 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h514947 = + assign v__h514943 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h516772 = + assign v__h516768 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7303 ? - v__h517152 : + v__h517148 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h517152 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h532491 = + assign v__h517148 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h532487 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7462 ? - v__h532686 : + v__h532682 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h532686 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h534940 = + assign v__h532682 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h534936 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7546 ? - v__h535135 : + v__h535131 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h535135 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h555960 = + assign v__h535131 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h555956 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7751 ? - v__h556155 : + v__h556151 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h556155 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h559739 = + assign v__h556151 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h559735 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7833 ? - v__h559934 : + v__h559930 : coreFix_memExe_forwardQ_enqP ; - assign v__h559934 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h836568 = + assign v__h559930 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h836565 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h836578 : + v__h836575 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h836578 = + assign v__h836575 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h837213 = v__h836568 - 2'd1 ; - assign value__h239635 = x__h239653 | in__h239745[63:0] ; - assign value__h239799 = - { coreFix_memExe_regToExeQ$first[380:331] & mask__h239806, + assign v__h837210 = v__h836565 - 2'd1 ; + assign value__h239634 = x__h239652 | in__h239744[63:0] ; + assign value__h239798 = + { coreFix_memExe_regToExeQ$first[380:331] & mask__h239805, 14'd0 } + - addBase__h239805 ; - assign value__h240792 = x__h240810 | in__h240902[63:0] ; - assign value__h240956 = - { coreFix_memExe_regToExeQ$first[217:168] & mask__h240963, + addBase__h239804 ; + assign value__h240791 = x__h240809 | in__h240901[63:0] ; + assign value__h240955 = + { coreFix_memExe_regToExeQ$first[217:168] & mask__h240962, 14'd0 } + - addBase__h240962 ; - assign value__h254401 = x__h254419 | in__h254511[63:0] ; - assign value__h254565 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h254572, + addBase__h240961 ; + assign value__h254399 = x__h254417 | in__h254509[63:0] ; + assign value__h254563 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h254570, 14'd0 } + - addBase__h254571 ; - assign value__h577003 = + addBase__h254569 ; + assign value__h577000 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h622752 = + assign value__h622749 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h668499 = + assign value__h668496 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h719770 = { 1'b0, f1_exp__h714825 != 8'd0, f1_sfd__h714826 } ; - assign value__h758623 = { 1'b0, f2_exp__h753819 != 8'd0, f2_sfd__h753820 } ; - assign value__h797927 = { 1'b0, f3_exp__h793123 != 8'd0, f3_sfd__h793124 } ; - assign vm_mode_reg__read__h853854 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h913568 = + assign value__h719767 = { 1'b0, f1_exp__h714822 != 8'd0, f1_sfd__h714823 } ; + assign value__h758620 = { 1'b0, f2_exp__h753816 != 8'd0, f2_sfd__h753817 } ; + assign value__h797924 = { 1'b0, f3_exp__h793120 != 8'd0, f3_sfd__h793121 } ; + assign vm_mode_reg__read__h853851 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h913563 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h913624 : + result__h913619 : 12'd4095 ; - assign wordIdx__h263159 = + assign wordIdx__h263157 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h998359 = + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h998354 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1005944 = pointer__h1005920 >> csrf_rg_dpc[33:28] ; - assign x__h1007669 = { 1'b0, csrf_spp_reg } ; - assign x__h1011445 = + assign x__h1005939 = pointer__h1005915 >> csrf_rg_dpc[33:28] ; + assign x__h1007664 = { 1'b0, csrf_spp_reg } ; + assign x__h1011440 = NOT_rob_deqPort_0_canDeq__3171_3172_OR_rob_deq_ETC___d23391 ? - y_avValue_snd_snd_snd_fst__h1011267 : + y_avValue_snd_snd_snd_fst__h1011262 : IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 ; - assign x__h1025256 = pointer__h1025233 >> csrf_rg_dpc[33:28] ; - assign x__h127272 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127310 ; - assign x__h127310 = { tmp_expTopHalf__h127263, tmp_expBotHalf__h127265 } ; - assign x__h127470 = { impliedTopBits__h127403, topBits__h127399 } ; - assign x__h127487 = x__h127490[13:12] + carry_out__h127401 ; - assign x__h127490 = + assign x__h1025250 = pointer__h1025227 >> csrf_rg_dpc[33:28] ; + assign x__h127271 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127309 ; + assign x__h127309 = { tmp_expTopHalf__h127262, tmp_expBotHalf__h127264 } ; + assign x__h127469 = { impliedTopBits__h127402, topBits__h127398 } ; + assign x__h127486 = x__h127489[13:12] + carry_out__h127400 ; + assign x__h127489 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[77:67], 3'd0 } : - b_base__h127497 ; - assign x__h140188 = mmio_dataRespQ_data_0[63:0] >> x__h140226 ; - assign x__h140226 = { tmp_expTopHalf__h140179, tmp_expBotHalf__h140181 } ; - assign x__h140386 = { impliedTopBits__h140319, topBits__h140315 } ; - assign x__h140403 = x__h140406[13:12] + carry_out__h140317 ; - assign x__h140406 = + b_base__h127496 ; + assign x__h140187 = mmio_dataRespQ_data_0[63:0] >> x__h140225 ; + assign x__h140225 = { tmp_expTopHalf__h140178, tmp_expBotHalf__h140180 } ; + assign x__h140385 = { impliedTopBits__h140318, topBits__h140314 } ; + assign x__h140402 = x__h140405[13:12] + carry_out__h140316 ; + assign x__h140405 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q10[0] ? { mmio_dataRespQ_data_0[77:67], 3'd0 } : - b_base__h140413 ; - assign x__h148960 = + b_base__h140412 ; + assign x__h148959 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; - assign x__h152094 = { 3'd0, sbIdx__h151985 } ; - assign x__h183367 = + assign x__h152093 = { 3'd0, sbIdx__h151984 } ; + assign x__h183366 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 } ; - assign x__h183449 = x__h183367[63:0] >> x__h183487 ; - assign x__h183487 = { tmp_expTopHalf__h183440, tmp_expBotHalf__h183442 } ; - assign x__h183647 = { impliedTopBits__h183580, topBits__h183576 } ; - assign x__h183664 = x__h183667[13:12] + carry_out__h183578 ; - assign x__h183667 = - INV_x83367_BITS_108_TO_90__q33[0] ? - { x__h183367[77:67], 3'd0 } : - b_base__h183674 ; - assign x__h199219 = + assign x__h183448 = x__h183366[63:0] >> x__h183486 ; + assign x__h183486 = { tmp_expTopHalf__h183439, tmp_expBotHalf__h183441 } ; + assign x__h183646 = { impliedTopBits__h183579, topBits__h183575 } ; + assign x__h183663 = x__h183666[13:12] + carry_out__h183577 ; + assign x__h183666 = + INV_x83366_BITS_108_TO_90__q33[0] ? + { x__h183366[77:67], 3'd0 } : + b_base__h183673 ; + assign x__h199218 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 } ; - assign x__h202200 = x__h199219[63:0] >> x__h202238 ; - assign x__h202238 = { tmp_expTopHalf__h202191, tmp_expBotHalf__h202193 } ; - assign x__h202398 = { impliedTopBits__h202331, topBits__h202327 } ; - assign x__h202415 = x__h202418[13:12] + carry_out__h202329 ; - assign x__h202418 = - INV_x99219_BITS_108_TO_90__q35[0] ? - { x__h199219[77:67], 3'd0 } : - b_base__h202425 ; - assign x__h216766 = coreFix_memExe_lsq$respLd[63:0] >> x__h216804 ; - assign x__h216804 = { tmp_expTopHalf__h216757, tmp_expBotHalf__h216759 } ; - assign x__h216964 = { impliedTopBits__h216897, topBits__h216893 } ; - assign x__h216981 = x__h216984[13:12] + carry_out__h216895 ; - assign x__h216984 = + assign x__h202199 = x__h199218[63:0] >> x__h202237 ; + assign x__h202237 = { tmp_expTopHalf__h202190, tmp_expBotHalf__h202192 } ; + assign x__h202397 = { impliedTopBits__h202330, topBits__h202326 } ; + assign x__h202414 = x__h202417[13:12] + carry_out__h202328 ; + assign x__h202417 = + INV_x99218_BITS_108_TO_90__q35[0] ? + { x__h199218[77:67], 3'd0 } : + b_base__h202424 ; + assign x__h216765 = coreFix_memExe_lsq$respLd[63:0] >> x__h216803 ; + assign x__h216803 = { tmp_expTopHalf__h216756, tmp_expBotHalf__h216758 } ; + assign x__h216963 = { impliedTopBits__h216896, topBits__h216892 } ; + assign x__h216980 = x__h216983[13:12] + carry_out__h216894 ; + assign x__h216983 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q9[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h216991 ; - assign x__h235690 = + b_base__h216990 ; + assign x__h235689 = (coreFix_memExe_dispToRegQ$first[109] && coreFix_memExe_dispToRegQ$first[108:102] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3036 : 66'd0 ; - assign x__h239653 = x__h239655 << coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h239655 = { {48{offset__h239641[15]}}, offset__h239641 } ; - assign x__h239763 = + assign x__h239652 = x__h239654 << coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h239654 = { {48{offset__h239640[15]}}, offset__h239640 } ; + assign x__h239762 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h239911 = + assign x__h239910 = coreFix_memExe_regToExeQ_first__633_BITS_264_T_ETC___d3705 ? - result__h240541 : - ret__h239918 ; - assign x__h240013 = + result__h240540 : + ret__h239917 ; + assign x__h240012 = { coreFix_memExe_regToExeQ$first[224:223], coreFix_memExe_regToExeQ$first[258:245] } ; - assign x__h240082 = + assign x__h240081 = (coreFix_memExe_regToExeQ$first[264:259] == 6'd50) ? coreFix_memExe_regToExeQ$first[244] : coreFix_memExe_regToExeQfirst_BITS_380_TO_331_ETC__q3[49] ; - assign x__h240810 = x__h240812 << coreFix_memExe_regToExeQ$first[101:96] ; - assign x__h240812 = { {48{offset__h240798[15]}}, offset__h240798 } ; - assign x__h240920 = + assign x__h240809 = x__h240811 << coreFix_memExe_regToExeQ$first[101:96] ; + assign x__h240811 = { {48{offset__h240797[15]}}, offset__h240797 } ; + assign x__h240919 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[101:96] ; - assign x__h241068 = + assign x__h241067 = coreFix_memExe_regToExeQ_first__633_BITS_101_T_ETC___d3767 ? - result__h241698 : - ret__h241075 ; - assign x__h241170 = + result__h241697 : + ret__h241074 ; + assign x__h241169 = { coreFix_memExe_regToExeQ$first[61:60], coreFix_memExe_regToExeQ$first[95:82] } ; - assign x__h241239 = + assign x__h241238 = (coreFix_memExe_regToExeQ$first[101:96] == 6'd50) ? coreFix_memExe_regToExeQ$first[81] : coreFix_memExe_regToExeQfirst_BITS_217_TO_168_ETC__q5[49] ; - assign x__h242605 = offset__h242559[63:14] ^ signBits__h242575 ; - assign x__h242708 = - offset__h242559 >> coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h244610 = { pointer__h242569[3:0], 3'b0 } ; - assign x__h248052 = - pointer__h242569 >> coreFix_memExe_regToExeQ$first[264:259] ; - assign x__h249407 = x__h249419 + y__h249420 ; - assign x__h249419 = x__h249431 + y__h249432 ; - assign x__h249431 = x__h249443 + y__h249444 ; - assign x__h249443 = x__h249455 + y__h249456 ; - assign x__h249455 = x__h249467 + y__h249468 ; - assign x__h249467 = x__h249479 + y__h249480 ; - assign x__h249479 = x__h249491 + y__h249492 ; - assign x__h249491 = x__h249503 + y__h249504 ; - assign x__h249503 = x__h249515 + y__h249516 ; - assign x__h249515 = x__h249527 + y__h249528 ; - assign x__h249527 = x__h249539 + y__h249540 ; - assign x__h249539 = x__h249551 + y__h249552 ; - assign x__h249551 = x__h249563 + y__h249564 ; - assign x__h249563 = x__h249575 + y__h249576 ; - assign x__h249575 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h254419 = x__h254421 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254421 = { {48{offset__h254407[15]}}, offset__h254407 } ; - assign x__h254529 = + assign x__h242604 = offset__h242558[63:14] ^ signBits__h242574 ; + assign x__h242707 = + offset__h242558 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h244608 = { pointer__h242568[3:0], 3'b0 } ; + assign x__h248050 = + pointer__h242568 >> coreFix_memExe_regToExeQ$first[264:259] ; + assign x__h249405 = x__h249417 + y__h249418 ; + assign x__h249417 = x__h249429 + y__h249430 ; + assign x__h249429 = x__h249441 + y__h249442 ; + assign x__h249441 = x__h249453 + y__h249454 ; + assign x__h249453 = x__h249465 + y__h249466 ; + assign x__h249465 = x__h249477 + y__h249478 ; + assign x__h249477 = x__h249489 + y__h249490 ; + assign x__h249489 = x__h249501 + y__h249502 ; + assign x__h249501 = x__h249513 + y__h249514 ; + assign x__h249513 = x__h249525 + y__h249526 ; + assign x__h249525 = x__h249537 + y__h249538 ; + assign x__h249537 = x__h249549 + y__h249550 ; + assign x__h249549 = x__h249561 + y__h249562 ; + assign x__h249561 = x__h249573 + y__h249574 ; + assign x__h249573 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h254417 = x__h254419 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254419 = { {48{offset__h254405[15]}}, offset__h254405 } ; + assign x__h254527 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254677 = + assign x__h254675 = coreFix_memExe_dTlb_procResp__239_BITS_334_TO__ETC___d4402 ? - result__h255307 : - ret__h254684 ; - assign x__h254779 = + result__h255305 : + ret__h254682 ; + assign x__h254777 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h254848 = + assign x__h254846 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h521603 = + assign x__h521599 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h568180 = - { (_theResult___exp__h611512 != 8'd255 || - _theResult___sfd__h611513 == 23'd0) && + assign x__h568177 = + { (_theResult___exp__h611509 != 8'd255 || + _theResult___sfd__h611510 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9245, - out_f_exp__h611789, - out_f_sfd__h611790 } ; - assign x__h594730 = - sfd__h568776 << (x__h594763[11] ? 12'hAAA : x__h594763) ; - assign x__h594763 = + out_f_exp__h611786, + out_f_sfd__h611787 } ; + assign x__h594727 = + sfd__h568773 << (x__h594760[11] ? 12'hAAA : x__h594760) ; + assign x__h594760 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8659 ; - assign x__h613934 = - { (_theResult___exp__h657261 != 8'd255 || - _theResult___sfd__h657262 == 23'd0) && + assign x__h613931 = + { (_theResult___exp__h657258 != 8'd255 || + _theResult___sfd__h657259 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10642, - out_f_exp__h657538, - out_f_sfd__h657539 } ; - assign x__h640479 = - sfd__h614530 << (x__h640512[11] ? 12'hAAA : x__h640512) ; - assign x__h640512 = + out_f_exp__h657535, + out_f_sfd__h657536 } ; + assign x__h640476 = + sfd__h614527 << (x__h640509[11] ? 12'hAAA : x__h640509) ; + assign x__h640509 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10056 ; assign x__h65608 = mmio_pRqQ_data_0[31:0] ; - assign x__h659681 = - { (_theResult___exp__h703008 != 8'd255 || - _theResult___sfd__h703009 == 23'd0) && + assign x__h659678 = + { (_theResult___exp__h703005 != 8'd255 || + _theResult___sfd__h703006 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12039, - out_f_exp__h703285, - out_f_sfd__h703286 } ; - assign x__h686226 = - sfd__h660277 << (x__h686259[11] ? 12'hAAA : x__h686259) ; - assign x__h686259 = + out_f_exp__h703282, + out_f_sfd__h703283 } ; + assign x__h686223 = + sfd__h660274 << (x__h686256[11] ? 12'hAAA : x__h686256) ; + assign x__h686256 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11453 ; - assign x__h714355 = + assign x__h714352 = sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1[149:86] : - y_avValue__h710401 ; - assign x__h714356 = + y_avValue__h710398 ; + assign x__h714353 = sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2[149:86] : - y_avValue__h711034 ; - assign x__h714357 = + y_avValue__h711031 ; + assign x__h714354 = sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3[149:86] : - y_avValue__h711661 ; - assign x__h736262 = sfd__h715187 << x__h736295 ; - assign x__h736295 = + y_avValue__h711658 ; + assign x__h736259 = sfd__h715184 << x__h736292 ; + assign x__h736292 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12782 ; - assign x__h775115 = sfd__h754181 << x__h775148 ; - assign x__h775148 = + assign x__h775112 = sfd__h754178 << x__h775145 ; + assign x__h775145 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14267 ; - assign x__h814419 = sfd__h793485 << x__h814452 ; - assign x__h814452 = + assign x__h814416 = sfd__h793482 << x__h814449 ; + assign x__h814449 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13497 ; - assign x__h836069 = a__h835633[63] ^ b__h835634[63] ; - assign x__h852690 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h865674 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h865712 ; - assign x__h865712 = { tmp_expTopHalf__h865664, tmp_expBotHalf__h865666 } ; - assign x__h865885 = { impliedTopBits__h865817, topBits__h865813 } ; - assign x__h865902 = x__h865905[13:12] + carry_out__h865815 ; - assign x__h865905 = + assign x__h836066 = a__h835630[63] ^ b__h835631[63] ; + assign x__h852687 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h865671 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h865709 ; + assign x__h865709 = { tmp_expTopHalf__h865661, tmp_expBotHalf__h865663 } ; + assign x__h865882 = { impliedTopBits__h865814, topBits__h865810 } ; + assign x__h865899 = x__h865902[13:12] + carry_out__h865812 ; + assign x__h865902 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h865912 ; - assign x__h866222 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h866260 ; - assign x__h866260 = { tmp_expTopHalf__h866212, tmp_expBotHalf__h866214 } ; - assign x__h866433 = { impliedTopBits__h866365, topBits__h866361 } ; - assign x__h866450 = x__h866453[13:12] + carry_out__h866363 ; - assign x__h866453 = + b_base__h865909 ; + assign x__h866219 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h866257 ; + assign x__h866257 = { tmp_expTopHalf__h866209, tmp_expBotHalf__h866211 } ; + assign x__h866430 = { impliedTopBits__h866362, topBits__h866358 } ; + assign x__h866447 = x__h866450[13:12] + carry_out__h866360 ; + assign x__h866450 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h866460 ; - assign x__h878730 = + b_base__h866457 ; + assign x__h878726 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -37459,28 +37459,28 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17857[2], IF_coreFix_aluExe_1_exeToFinQ_first__7660_BIT__ETC___d17857[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h894478 = + assign x__h894474 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q23, 5'd3 } ; - assign x__h904296 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h904334 ; - assign x__h904334 = { tmp_expTopHalf__h904286, tmp_expBotHalf__h904288 } ; - assign x__h904507 = { impliedTopBits__h904439, topBits__h904435 } ; - assign x__h904524 = x__h904527[13:12] + carry_out__h904437 ; - assign x__h904527 = + assign x__h904292 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h904330 ; + assign x__h904330 = { tmp_expTopHalf__h904282, tmp_expBotHalf__h904284 } ; + assign x__h904503 = { impliedTopBits__h904435, topBits__h904431 } ; + assign x__h904520 = x__h904523[13:12] + carry_out__h904433 ; + assign x__h904523 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h904534 ; - assign x__h904844 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h904882 ; - assign x__h904882 = { tmp_expTopHalf__h904834, tmp_expBotHalf__h904836 } ; - assign x__h905055 = { impliedTopBits__h904987, topBits__h904983 } ; - assign x__h905072 = x__h905075[13:12] + carry_out__h904985 ; - assign x__h905075 = + b_base__h904530 ; + assign x__h904840 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h904878 ; + assign x__h904878 = { tmp_expTopHalf__h904830, tmp_expBotHalf__h904832 } ; + assign x__h905051 = { impliedTopBits__h904983, topBits__h904979 } ; + assign x__h905068 = x__h905071[13:12] + carry_out__h904981 ; + assign x__h905071 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h905082 ; - assign x__h912383 = + b_base__h905078 ; + assign x__h912378 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -37492,38 +37492,38 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19935[2], IF_coreFix_aluExe_0_exeToFinQ_first__9739_BIT__ETC___d19935[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h913572 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h913623 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h992383 = commitStage_commitTrap[172:109] >> x__h992421 ; - assign x__h992421 = { tmp_expTopHalf__h992374, tmp_expBotHalf__h992376 } ; - assign x__h992581 = { impliedTopBits__h992514, topBits__h992510 } ; - assign x__h992598 = x__h992601[13:12] + carry_out__h992512 ; - assign x__h992601 = + assign x__h913567 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h913618 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h992378 = commitStage_commitTrap[172:109] >> x__h992416 ; + assign x__h992416 = { tmp_expTopHalf__h992369, tmp_expBotHalf__h992371 } ; + assign x__h992576 = { impliedTopBits__h992509, topBits__h992505 } ; + assign x__h992593 = x__h992596[13:12] + carry_out__h992507 ; + assign x__h992596 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h992608 ; - assign x__h995059 = - x__h995061 << + b_base__h992603 ; + assign x__h995054 = + x__h995056 << IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351 ; - assign x__h995061 = { {48{offset__h995047[15]}}, offset__h995047 } ; - assign x__h995146 = + assign x__h995056 = { {48{offset__h995042[15]}}, offset__h995042 } ; + assign x__h995141 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2039_BITS_217_TO_ETC___d22351 ; - assign x__h996333 = + assign x__h996328 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q24 } ; - assign x__h997033 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h997059 = { cause_code__h992792, 2'b0 } ; - assign x__h997160 = address__h996966 >> csrf_stcc_reg[33:28] ; - assign x__h997464 = address__h997310 >> csrf_stcc_reg[33:28] ; - assign x__h997690 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h997817 = address__h997623 >> csrf_mtcc_reg[33:28] ; - assign x__h998121 = address__h997967 >> csrf_mtcc_reg[33:28] ; - assign x__h998356 = + assign x__h997028 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h997054 = { cause_code__h992787, 2'b0 } ; + assign x__h997155 = address__h996961 >> csrf_stcc_reg[33:28] ; + assign x__h997459 = address__h997305 >> csrf_stcc_reg[33:28] ; + assign x__h997685 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h997812 = address__h997618 >> csrf_mtcc_reg[33:28] ; + assign x__h998116 = address__h997962 >> csrf_mtcc_reg[33:28] ; + assign x__h998351 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h998377 = + assign x__h998372 = csrf_prv_reg_read__0079_ULE_1_2385_AND_IF_comm_ETC___d22418 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; @@ -37535,7 +37535,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h535302 = + assign x_addr__h535298 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -37543,49 +37543,49 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h923974 = csrf_frm_reg ; - assign x_quotient__h705674 = + assign x_decodeInfo_frm__h923969 = csrf_frm_reg ; + assign x_quotient__h705671 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h706385 : + q___1__h706382 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h849177 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h705675 = + assign x_reg_ifc__read__h849174 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h705672 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h706411 : + r___1__h706408 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h1011220 = + assign y__h1011215 = NOT_rob_deqPort_0_canDeq__3171_3172_OR_rob_deq_ETC___d23391 ? - y_avValue_snd_snd_snd_snd_snd__h1011273 : + y_avValue_snd_snd_snd_snd_snd__h1011268 : IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 ; - assign y__h239762 = ~x__h239763 ; - assign y__h240919 = ~x__h240920 ; - assign y__h249408 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h249420 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h249432 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h249444 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h249456 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h249468 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h249480 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h249492 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h249504 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h249516 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h249528 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h249540 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h249552 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h249564 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h249576 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h254528 = ~x__h254529 ; - assign y__h422493 = + assign y__h239761 = ~x__h239762 ; + assign y__h240918 = ~x__h240919 ; + assign y__h249406 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h249418 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h249430 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h249442 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h249454 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h249466 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h249478 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h249490 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h249502 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h249514 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h249526 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h249538 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h249550 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h249562 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h249574 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h254526 = ~x__h254527 ; + assign y__h422490 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[168:164] } ; - assign y__h913602 = ~x__h913572 ; - assign y__h918532 = + assign y__h913597 = ~x__h913567 ; + assign y__h918527 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -37594,23 +37594,23 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h971319 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h995145 = ~x__h995146 ; - assign y__h997089 = { mask__h996972[62:0], 1'd0 } ; - assign y__h997746 = { mask__h997629[62:0], 1'd0 } ; - assign y_avValue__h710401 = + assign y__h971314 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h995140 = ~x__h995141 ; + assign y__h997084 = { mask__h996967[62:0], 1'd0 } ; + assign y__h997741 = { mask__h997624[62:0], 1'd0 } ; + assign y_avValue__h710398 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12363 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12468 ; - assign y_avValue__h711034 = + assign y_avValue__h711031 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12390 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12480 ; - assign y_avValue__h711661 = + assign y_avValue__h711658 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12414 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12492 ; - assign y_avValue_snd_fst__h1010675 = + assign y_avValue_snd_fst__h1010670 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -37625,7 +37625,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1011257 = + assign y_avValue_snd_fst__h1011252 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -37639,25 +37639,25 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 : - y_avValue_snd_fst__h1011286 ; - assign y_avValue_snd_fst__h1011286 = + y_avValue_snd_fst__h1011281 ; + assign y_avValue_snd_fst__h1011281 = IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23398 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h960972 = + assign y_avValue_snd_fst__h960967 = ((fetchStage$pipelines_0_first[267:265] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__0933_AND__ETC___d20962) ? - y_avValue_snd_fst__h961014 : + y_avValue_snd_fst__h961009 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h961014 = + assign y_avValue_snd_fst__h961009 = IF_fetchStage_pipelines_0_first__0049_BITS_267_ETC___d21004 ? - y_avValue_snd_fst__h961056 : + y_avValue_snd_fst__h961051 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h961056 = + assign y_avValue_snd_fst__h961051 = (fetchStage$pipelines_0_first[267:265] == 3'd1) ? - spec_bits__h971306 : + spec_bits__h971301 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1010685 = + assign y_avValue_snd_snd_snd_fst__h1010680 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -37672,7 +37672,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1011267 = + assign y_avValue_snd_snd_snd_fst__h1011262 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -37686,11 +37686,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 : - y_avValue_snd_snd_snd_fst__h1011296 ; - assign y_avValue_snd_snd_snd_fst__h1011296 = + y_avValue_snd_snd_snd_fst__h1011291 ; + assign y_avValue_snd_snd_snd_fst__h1011291 = IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23420 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1010691 = + assign y_avValue_snd_snd_snd_snd_snd__h1010686 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -37705,7 +37705,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1011273 = + assign y_avValue_snd_snd_snd_snd_snd__h1011268 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -37719,8 +37719,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 : - y_avValue_snd_snd_snd_snd_snd__h1011302 ; - assign y_avValue_snd_snd_snd_snd_snd__h1011302 = + y_avValue_snd_snd_snd_snd_snd__h1011297 ; + assign y_avValue_snd_snd_snd_snd_snd__h1011297 = IF_rob_deqPort_0_canDeq__3171_THEN_IF_NOT_rob__ETC___d23292 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -37746,28 +37746,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h501025 = + x__h501022 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -37777,10 +37777,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h505543 = + addr__h505540 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h505543 = + addr__h505540 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; endcase end @@ -37789,16 +37789,16 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h212809 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h212809 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h212808 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h212808 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h215095 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h215095 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h215094 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h215094 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -37857,16 +37857,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q17; 2'd1: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd2: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd3: - x__h264659 = + x__h264656 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; endcase end @@ -37874,8 +37874,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h992982 = commitStage_commitTrap[35:32]; - default: i__h992982 = 4'd15; + i__h992977 = commitStage_commitTrap[35:32]; + default: i__h992977 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -37948,340 +37948,340 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h508693 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h508690 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h508693 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h508690 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h849047 or - frm_csr__read__h849058 or - fcsr_csr__read__h849072 or - sstatus_csr__read__h849268 or - sie_csr__read__h849338 or - scounteren_csr__read__h849391 or + fflags_csr__read__h849044 or + frm_csr__read__h849055 or + fcsr_csr__read__h849069 or + sstatus_csr__read__h849265 or + sie_csr__read__h849335 or + scounteren_csr__read__h849388 or csrf_sscratch_csr or - scause_csr__read__h849486 or + scause_csr__read__h849483 or csrf_stval_csr or - sip_csr__read__h849626 or - satp_csr__read__h849689 or - mstatus_csr__read__h849835 or - medeleg_csr__read__h849989 or - mideleg_csr__read__h850087 or - mie_csr__read__h850214 or - mcounteren_csr__read__h850309 or + sip_csr__read__h849623 or + satp_csr__read__h849686 or + mstatus_csr__read__h849832 or + medeleg_csr__read__h849986 or + mideleg_csr__read__h850084 or + mie_csr__read__h850211 or + mcounteren_csr__read__h850306 or csrf_mscratch_csr or - mcause_csr__read__h850488 or + mcause_csr__read__h850485 or csrf_mtval_csr or - mip_csr__read__h850727 or + mip_csr__read__h850724 or csrf_rg_tselect or - rg_tdata1__read__h851828 or + rg_tdata1__read__h851825 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849177 or + x_reg_ifc__read__h849174 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h894478 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h894474 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1014871 = fflags_csr__read__h849047; - 12'd2: data_out__h1014871 = frm_csr__read__h849058; - 12'd3: data_out__h1014871 = fcsr_csr__read__h849072; - 12'd256: data_out__h1014871 = sstatus_csr__read__h849268; - 12'd260: data_out__h1014871 = sie_csr__read__h849338; - 12'd262: data_out__h1014871 = scounteren_csr__read__h849391; - 12'd320: data_out__h1014871 = csrf_sscratch_csr; - 12'd322: data_out__h1014871 = scause_csr__read__h849486; - 12'd323: data_out__h1014871 = csrf_stval_csr; - 12'd324: data_out__h1014871 = sip_csr__read__h849626; - 12'd384: data_out__h1014871 = satp_csr__read__h849689; - 12'd768: data_out__h1014871 = mstatus_csr__read__h849835; - 12'd769: data_out__h1014871 = 64'h800000000014112D; - 12'd770: data_out__h1014871 = medeleg_csr__read__h849989; - 12'd771: data_out__h1014871 = mideleg_csr__read__h850087; - 12'd772: data_out__h1014871 = mie_csr__read__h850214; - 12'd774: data_out__h1014871 = mcounteren_csr__read__h850309; - 12'd832: data_out__h1014871 = csrf_mscratch_csr; - 12'd834: data_out__h1014871 = mcause_csr__read__h850488; - 12'd835: data_out__h1014871 = csrf_mtval_csr; - 12'd836: data_out__h1014871 = mip_csr__read__h850727; - 12'd1952: data_out__h1014871 = csrf_rg_tselect; - 12'd1953: data_out__h1014871 = rg_tdata1__read__h851828; - 12'd1954: data_out__h1014871 = csrf_rg_tdata2; - 12'd1955: data_out__h1014871 = csrf_rg_tdata3; - 12'd1968: data_out__h1014871 = csrf_rg_dcsr; - 12'd1969: data_out__h1014871 = csrf_rg_dpc[149:86]; - 12'd1970: data_out__h1014871 = csrf_rg_dscratch0; - 12'd1971: data_out__h1014871 = csrf_rg_dscratch1; + 12'd1: data_out__h1014865 = fflags_csr__read__h849044; + 12'd2: data_out__h1014865 = frm_csr__read__h849055; + 12'd3: data_out__h1014865 = fcsr_csr__read__h849069; + 12'd256: data_out__h1014865 = sstatus_csr__read__h849265; + 12'd260: data_out__h1014865 = sie_csr__read__h849335; + 12'd262: data_out__h1014865 = scounteren_csr__read__h849388; + 12'd320: data_out__h1014865 = csrf_sscratch_csr; + 12'd322: data_out__h1014865 = scause_csr__read__h849483; + 12'd323: data_out__h1014865 = csrf_stval_csr; + 12'd324: data_out__h1014865 = sip_csr__read__h849623; + 12'd384: data_out__h1014865 = satp_csr__read__h849686; + 12'd768: data_out__h1014865 = mstatus_csr__read__h849832; + 12'd769: data_out__h1014865 = 64'h800000000014112D; + 12'd770: data_out__h1014865 = medeleg_csr__read__h849986; + 12'd771: data_out__h1014865 = mideleg_csr__read__h850084; + 12'd772: data_out__h1014865 = mie_csr__read__h850211; + 12'd774: data_out__h1014865 = mcounteren_csr__read__h850306; + 12'd832: data_out__h1014865 = csrf_mscratch_csr; + 12'd834: data_out__h1014865 = mcause_csr__read__h850485; + 12'd835: data_out__h1014865 = csrf_mtval_csr; + 12'd836: data_out__h1014865 = mip_csr__read__h850724; + 12'd1952: data_out__h1014865 = csrf_rg_tselect; + 12'd1953: data_out__h1014865 = rg_tdata1__read__h851825; + 12'd1954: data_out__h1014865 = csrf_rg_tdata2; + 12'd1955: data_out__h1014865 = csrf_rg_tdata3; + 12'd1968: data_out__h1014865 = csrf_rg_dcsr; + 12'd1969: data_out__h1014865 = csrf_rg_dpc[149:86]; + 12'd1970: data_out__h1014865 = csrf_rg_dscratch0; + 12'd1971: data_out__h1014865 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1014871 = 64'd0; - 12'd2049: data_out__h1014871 = x_reg_ifc__read__h849177; - 12'd2816, 12'd3072: data_out__h1014871 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1014871 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1014871 = { 48'd0, x__h894478 }; - 12'd3073: data_out__h1014871 = csrf_time_reg; - default: data_out__h1014871 = 64'b0; + data_out__h1014865 = 64'd0; + 12'd2049: data_out__h1014865 = x_reg_ifc__read__h849174; + 12'd2816, 12'd3072: data_out__h1014865 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1014865 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1014865 = { 48'd0, x__h894474 }; + 12'd3073: data_out__h1014865 = csrf_time_reg; + default: data_out__h1014865 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h849047 or - frm_csr__read__h849058 or - fcsr_csr__read__h849072 or - sstatus_csr__read__h849268 or - sie_csr__read__h849338 or - scounteren_csr__read__h849391 or + fflags_csr__read__h849044 or + frm_csr__read__h849055 or + fcsr_csr__read__h849069 or + sstatus_csr__read__h849265 or + sie_csr__read__h849335 or + scounteren_csr__read__h849388 or csrf_sscratch_csr or - scause_csr__read__h849486 or + scause_csr__read__h849483 or csrf_stval_csr or - sip_csr__read__h849626 or - satp_csr__read__h849689 or - mstatus_csr__read__h849835 or - medeleg_csr__read__h849989 or - mideleg_csr__read__h850087 or - mie_csr__read__h850214 or - mcounteren_csr__read__h850309 or + sip_csr__read__h849623 or + satp_csr__read__h849686 or + mstatus_csr__read__h849832 or + medeleg_csr__read__h849986 or + mideleg_csr__read__h850084 or + mie_csr__read__h850211 or + mcounteren_csr__read__h850306 or csrf_mscratch_csr or - mcause_csr__read__h850488 or + mcause_csr__read__h850485 or csrf_mtval_csr or - mip_csr__read__h850727 or + mip_csr__read__h850724 or csrf_rg_tselect or - rg_tdata1__read__h851828 or + rg_tdata1__read__h851825 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849177 or + x_reg_ifc__read__h849174 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h894478 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h894474 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h843840 = fflags_csr__read__h849047; - 12'd2: addr__h843840 = frm_csr__read__h849058; - 12'd3: addr__h843840 = fcsr_csr__read__h849072; - 12'd256: addr__h843840 = sstatus_csr__read__h849268; - 12'd260: addr__h843840 = sie_csr__read__h849338; - 12'd262: addr__h843840 = scounteren_csr__read__h849391; - 12'd320: addr__h843840 = csrf_sscratch_csr; - 12'd322: addr__h843840 = scause_csr__read__h849486; - 12'd323: addr__h843840 = csrf_stval_csr; - 12'd324: addr__h843840 = sip_csr__read__h849626; - 12'd384: addr__h843840 = satp_csr__read__h849689; - 12'd768: addr__h843840 = mstatus_csr__read__h849835; - 12'd769: addr__h843840 = 64'h800000000014112D; - 12'd770: addr__h843840 = medeleg_csr__read__h849989; - 12'd771: addr__h843840 = mideleg_csr__read__h850087; - 12'd772: addr__h843840 = mie_csr__read__h850214; - 12'd774: addr__h843840 = mcounteren_csr__read__h850309; - 12'd832: addr__h843840 = csrf_mscratch_csr; - 12'd834: addr__h843840 = mcause_csr__read__h850488; - 12'd835: addr__h843840 = csrf_mtval_csr; - 12'd836: addr__h843840 = mip_csr__read__h850727; - 12'd1952: addr__h843840 = csrf_rg_tselect; - 12'd1953: addr__h843840 = rg_tdata1__read__h851828; - 12'd1954: addr__h843840 = csrf_rg_tdata2; - 12'd1955: addr__h843840 = csrf_rg_tdata3; - 12'd1968: addr__h843840 = csrf_rg_dcsr; - 12'd1969: addr__h843840 = csrf_rg_dpc[149:86]; - 12'd1970: addr__h843840 = csrf_rg_dscratch0; - 12'd1971: addr__h843840 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843840 = 64'd0; - 12'd2049: addr__h843840 = x_reg_ifc__read__h849177; - 12'd2816, 12'd3072: addr__h843840 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h843840 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h843840 = { 48'd0, x__h894478 }; - 12'd3073: addr__h843840 = csrf_time_reg; - default: addr__h843840 = 64'b0; + 12'd1: addr__h843837 = fflags_csr__read__h849044; + 12'd2: addr__h843837 = frm_csr__read__h849055; + 12'd3: addr__h843837 = fcsr_csr__read__h849069; + 12'd256: addr__h843837 = sstatus_csr__read__h849265; + 12'd260: addr__h843837 = sie_csr__read__h849335; + 12'd262: addr__h843837 = scounteren_csr__read__h849388; + 12'd320: addr__h843837 = csrf_sscratch_csr; + 12'd322: addr__h843837 = scause_csr__read__h849483; + 12'd323: addr__h843837 = csrf_stval_csr; + 12'd324: addr__h843837 = sip_csr__read__h849623; + 12'd384: addr__h843837 = satp_csr__read__h849686; + 12'd768: addr__h843837 = mstatus_csr__read__h849832; + 12'd769: addr__h843837 = 64'h800000000014112D; + 12'd770: addr__h843837 = medeleg_csr__read__h849986; + 12'd771: addr__h843837 = mideleg_csr__read__h850084; + 12'd772: addr__h843837 = mie_csr__read__h850211; + 12'd774: addr__h843837 = mcounteren_csr__read__h850306; + 12'd832: addr__h843837 = csrf_mscratch_csr; + 12'd834: addr__h843837 = mcause_csr__read__h850485; + 12'd835: addr__h843837 = csrf_mtval_csr; + 12'd836: addr__h843837 = mip_csr__read__h850724; + 12'd1952: addr__h843837 = csrf_rg_tselect; + 12'd1953: addr__h843837 = rg_tdata1__read__h851825; + 12'd1954: addr__h843837 = csrf_rg_tdata2; + 12'd1955: addr__h843837 = csrf_rg_tdata3; + 12'd1968: addr__h843837 = csrf_rg_dcsr; + 12'd1969: addr__h843837 = csrf_rg_dpc[149:86]; + 12'd1970: addr__h843837 = csrf_rg_dscratch0; + 12'd1971: addr__h843837 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843837 = 64'd0; + 12'd2049: addr__h843837 = x_reg_ifc__read__h849174; + 12'd2816, 12'd3072: addr__h843837 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h843837 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h843837 = { 48'd0, x__h894474 }; + 12'd3073: addr__h843837 = csrf_time_reg; + default: addr__h843837 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h849047 or - frm_csr__read__h849058 or - fcsr_csr__read__h849072 or - sstatus_csr__read__h849268 or - sie_csr__read__h849338 or - scounteren_csr__read__h849391 or + fflags_csr__read__h849044 or + frm_csr__read__h849055 or + fcsr_csr__read__h849069 or + sstatus_csr__read__h849265 or + sie_csr__read__h849335 or + scounteren_csr__read__h849388 or csrf_sscratch_csr or - scause_csr__read__h849486 or + scause_csr__read__h849483 or csrf_stval_csr or - sip_csr__read__h849626 or - satp_csr__read__h849689 or - mstatus_csr__read__h849835 or - medeleg_csr__read__h849989 or - mideleg_csr__read__h850087 or - mie_csr__read__h850214 or - mcounteren_csr__read__h850309 or + sip_csr__read__h849623 or + satp_csr__read__h849686 or + mstatus_csr__read__h849832 or + medeleg_csr__read__h849986 or + mideleg_csr__read__h850084 or + mie_csr__read__h850211 or + mcounteren_csr__read__h850306 or csrf_mscratch_csr or - mcause_csr__read__h850488 or + mcause_csr__read__h850485 or csrf_mtval_csr or - mip_csr__read__h850727 or + mip_csr__read__h850724 or csrf_rg_tselect or - rg_tdata1__read__h851828 or + rg_tdata1__read__h851825 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849177 or + x_reg_ifc__read__h849174 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h894478 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h894474 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h886249 = fflags_csr__read__h849047; - 12'd2: addr__h886249 = frm_csr__read__h849058; - 12'd3: addr__h886249 = fcsr_csr__read__h849072; - 12'd256: addr__h886249 = sstatus_csr__read__h849268; - 12'd260: addr__h886249 = sie_csr__read__h849338; - 12'd262: addr__h886249 = scounteren_csr__read__h849391; - 12'd320: addr__h886249 = csrf_sscratch_csr; - 12'd322: addr__h886249 = scause_csr__read__h849486; - 12'd323: addr__h886249 = csrf_stval_csr; - 12'd324: addr__h886249 = sip_csr__read__h849626; - 12'd384: addr__h886249 = satp_csr__read__h849689; - 12'd768: addr__h886249 = mstatus_csr__read__h849835; - 12'd769: addr__h886249 = 64'h800000000014112D; - 12'd770: addr__h886249 = medeleg_csr__read__h849989; - 12'd771: addr__h886249 = mideleg_csr__read__h850087; - 12'd772: addr__h886249 = mie_csr__read__h850214; - 12'd774: addr__h886249 = mcounteren_csr__read__h850309; - 12'd832: addr__h886249 = csrf_mscratch_csr; - 12'd834: addr__h886249 = mcause_csr__read__h850488; - 12'd835: addr__h886249 = csrf_mtval_csr; - 12'd836: addr__h886249 = mip_csr__read__h850727; - 12'd1952: addr__h886249 = csrf_rg_tselect; - 12'd1953: addr__h886249 = rg_tdata1__read__h851828; - 12'd1954: addr__h886249 = csrf_rg_tdata2; - 12'd1955: addr__h886249 = csrf_rg_tdata3; - 12'd1968: addr__h886249 = csrf_rg_dcsr; - 12'd1969: addr__h886249 = csrf_rg_dpc[149:86]; - 12'd1970: addr__h886249 = csrf_rg_dscratch0; - 12'd1971: addr__h886249 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h886249 = 64'd0; - 12'd2049: addr__h886249 = x_reg_ifc__read__h849177; - 12'd2816, 12'd3072: addr__h886249 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h886249 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h886249 = { 48'd0, x__h894478 }; - 12'd3073: addr__h886249 = csrf_time_reg; - default: addr__h886249 = 64'b0; + 12'd1: addr__h886245 = fflags_csr__read__h849044; + 12'd2: addr__h886245 = frm_csr__read__h849055; + 12'd3: addr__h886245 = fcsr_csr__read__h849069; + 12'd256: addr__h886245 = sstatus_csr__read__h849265; + 12'd260: addr__h886245 = sie_csr__read__h849335; + 12'd262: addr__h886245 = scounteren_csr__read__h849388; + 12'd320: addr__h886245 = csrf_sscratch_csr; + 12'd322: addr__h886245 = scause_csr__read__h849483; + 12'd323: addr__h886245 = csrf_stval_csr; + 12'd324: addr__h886245 = sip_csr__read__h849623; + 12'd384: addr__h886245 = satp_csr__read__h849686; + 12'd768: addr__h886245 = mstatus_csr__read__h849832; + 12'd769: addr__h886245 = 64'h800000000014112D; + 12'd770: addr__h886245 = medeleg_csr__read__h849986; + 12'd771: addr__h886245 = mideleg_csr__read__h850084; + 12'd772: addr__h886245 = mie_csr__read__h850211; + 12'd774: addr__h886245 = mcounteren_csr__read__h850306; + 12'd832: addr__h886245 = csrf_mscratch_csr; + 12'd834: addr__h886245 = mcause_csr__read__h850485; + 12'd835: addr__h886245 = csrf_mtval_csr; + 12'd836: addr__h886245 = mip_csr__read__h850724; + 12'd1952: addr__h886245 = csrf_rg_tselect; + 12'd1953: addr__h886245 = rg_tdata1__read__h851825; + 12'd1954: addr__h886245 = csrf_rg_tdata2; + 12'd1955: addr__h886245 = csrf_rg_tdata3; + 12'd1968: addr__h886245 = csrf_rg_dcsr; + 12'd1969: addr__h886245 = csrf_rg_dpc[149:86]; + 12'd1970: addr__h886245 = csrf_rg_dscratch0; + 12'd1971: addr__h886245 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h886245 = 64'd0; + 12'd2049: addr__h886245 = x_reg_ifc__read__h849174; + 12'd2816, 12'd3072: addr__h886245 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h886245 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h886245 = { 48'd0, x__h894474 }; + 12'd3073: addr__h886245 = csrf_time_reg; + default: addr__h886245 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h576363 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h576360 = 8'd255; 3'd2: - _theResult___fst_exp__h576363 = + _theResult___fst_exp__h576360 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h576363 = + _theResult___fst_exp__h576360 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h576363 = 8'd254; - default: _theResult___fst_exp__h576363 = 8'd0; + 3'd4: _theResult___fst_exp__h576360 = 8'd254; + default: _theResult___fst_exp__h576360 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h576364 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h576361 = 23'd0; 3'd2: - _theResult___fst_sfd__h576364 = + _theResult___fst_sfd__h576361 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h576364 = + _theResult___fst_sfd__h576361 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h576364 = 23'd8388607; - default: _theResult___fst_sfd__h576364 = 23'd0; + 3'd4: _theResult___fst_sfd__h576361 = 23'd8388607; + default: _theResult___fst_sfd__h576361 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h622114 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h622111 = 8'd255; 3'd2: - _theResult___fst_exp__h622114 = + _theResult___fst_exp__h622111 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h622114 = + _theResult___fst_exp__h622111 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h622114 = 8'd254; - default: _theResult___fst_exp__h622114 = 8'd0; + 3'd4: _theResult___fst_exp__h622111 = 8'd254; + default: _theResult___fst_exp__h622111 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h622115 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h622112 = 23'd0; 3'd2: - _theResult___fst_sfd__h622115 = + _theResult___fst_sfd__h622112 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h622115 = + _theResult___fst_sfd__h622112 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h622115 = 23'd8388607; - default: _theResult___fst_sfd__h622115 = 23'd0; + 3'd4: _theResult___fst_sfd__h622112 = 23'd8388607; + default: _theResult___fst_sfd__h622112 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h667861 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h667858 = 8'd255; 3'd2: - _theResult___fst_exp__h667861 = + _theResult___fst_exp__h667858 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h667861 = + _theResult___fst_exp__h667858 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h667861 = 8'd254; - default: _theResult___fst_exp__h667861 = 8'd0; + 3'd4: _theResult___fst_exp__h667858 = 8'd254; + default: _theResult___fst_exp__h667858 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h667862 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h667859 = 23'd0; 3'd2: - _theResult___fst_sfd__h667862 = + _theResult___fst_sfd__h667859 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h667862 = + _theResult___fst_sfd__h667859 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h667862 = 23'd8388607; - default: _theResult___fst_sfd__h667862 = 23'd0; + 3'd4: _theResult___fst_sfd__h667859 = 23'd8388607; + default: _theResult___fst_sfd__h667859 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -38433,16 +38433,16 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h992808 = commitStage_commitTrap[36:32]; - default: i__h992808 = 5'd28; + i__h992803 = commitStage_commitTrap[36:32]; + default: i__h992803 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h994330 or i__h992808) + always@(commitStage_commitTrap or cause_code__h994325 or i__h992803) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h992792 = 5'd28; - 2'd1: cause_code__h992792 = i__h992808; - default: cause_code__h992792 = cause_code__h994330; + 2'd0: cause_code__h992787 = 5'd28; + 2'd1: cause_code__h992787 = i__h992803; + default: cause_code__h992787 = cause_code__h994325; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -38732,16 +38732,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849[31:0]; 2'd1: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4849[63:32]; 2'd2: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843[31:0]; 2'd3: - x__h264814 = + x__h264811 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4843[63:32]; endcase end @@ -38905,446 +38905,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[516]; endcase end - always@(guard__h585100 or - _theResult___fst_exp__h593148 or - out_exp__h593593 or _theResult___exp__h593590) + always@(guard__h585097 or + _theResult___fst_exp__h593145 or + out_exp__h593590 or _theResult___exp__h593587) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = - _theResult___fst_exp__h593148; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 = + _theResult___fst_exp__h593145; 2'b10: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = - out_exp__h593593; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 = + out_exp__h593590; 2'b11: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 = - _theResult___exp__h593590; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 = + _theResult___exp__h593587; endcase end - always@(guard__h585100 or - _theResult___fst_exp__h593148 or _theResult___exp__h593590) + always@(guard__h585097 or + _theResult___fst_exp__h593145 or _theResult___exp__h593587) begin - case (guard__h585100) + case (guard__h585097) 2'b0: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 = - _theResult___fst_exp__h593148; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44 = + _theResult___fst_exp__h593145; 2'b01, 2'b10, 2'b11: - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 = - _theResult___exp__h593590; + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44 = + _theResult___exp__h593587; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43 or - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44 or + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43 or + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639 or - _theResult___fst_exp__h593148) + _theResult___fst_exp__h593145) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h593668 = - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q43; + _theResult___fst_exp__h593665 = + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q43; 3'd1: - _theResult___fst_exp__h593668 = - CASE_guard85100_0b0_theResult___fst_exp93148_0_ETC__q44; + _theResult___fst_exp__h593665 = + CASE_guard85097_0b0_theResult___fst_exp93145_0_ETC__q44; 3'd2: - _theResult___fst_exp__h593668 = + _theResult___fst_exp__h593665 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8637; 3'd3: - _theResult___fst_exp__h593668 = + _theResult___fst_exp__h593665 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8639; - 3'd4: _theResult___fst_exp__h593668 = _theResult___fst_exp__h593148; - default: _theResult___fst_exp__h593668 = 8'd0; + 3'd4: _theResult___fst_exp__h593665 = _theResult___fst_exp__h593145; + default: _theResult___fst_exp__h593665 = 8'd0; endcase end - always@(guard__h576391 or - _theResult___fst_exp__h584492 or - out_exp__h585011 or _theResult___exp__h585008) + always@(guard__h576388 or + _theResult___fst_exp__h584489 or + out_exp__h585008 or _theResult___exp__h585005) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = - _theResult___fst_exp__h584492; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 = + _theResult___fst_exp__h584489; 2'b10: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = - out_exp__h585011; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 = + out_exp__h585008; 2'b11: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 = - _theResult___exp__h585008; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 = + _theResult___exp__h585005; endcase end - always@(guard__h576391 or - _theResult___fst_exp__h584492 or _theResult___exp__h585008) + always@(guard__h576388 or + _theResult___fst_exp__h584489 or _theResult___exp__h585005) begin - case (guard__h576391) + case (guard__h576388) 2'b0: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 = - _theResult___fst_exp__h584492; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46 = + _theResult___fst_exp__h584489; 2'b01, 2'b10, 2'b11: - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 = - _theResult___exp__h585008; + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46 = + _theResult___exp__h585005; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45 or - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46 or + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45 or + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418 or - _theResult___fst_exp__h584492) + _theResult___fst_exp__h584489) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h585086 = - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q45; + _theResult___fst_exp__h585083 = + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q45; 3'd1: - _theResult___fst_exp__h585086 = - CASE_guard76391_0b0_theResult___fst_exp84492_0_ETC__q46; + _theResult___fst_exp__h585083 = + CASE_guard76388_0b0_theResult___fst_exp84489_0_ETC__q46; 3'd2: - _theResult___fst_exp__h585086 = + _theResult___fst_exp__h585083 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8415; 3'd3: - _theResult___fst_exp__h585086 = + _theResult___fst_exp__h585083 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8418; - 3'd4: _theResult___fst_exp__h585086 = _theResult___fst_exp__h584492; - default: _theResult___fst_exp__h585086 = 8'd0; + 3'd4: _theResult___fst_exp__h585083 = _theResult___fst_exp__h584489; + default: _theResult___fst_exp__h585083 = 8'd0; endcase end - always@(guard__h594030 or - _theResult___fst_exp__h602258 or - out_exp__h602777 or _theResult___exp__h602774) + always@(guard__h594027 or + _theResult___fst_exp__h602255 or + out_exp__h602774 or _theResult___exp__h602771) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = - _theResult___fst_exp__h602258; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 = + _theResult___fst_exp__h602255; 2'b10: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = - out_exp__h602777; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 = + out_exp__h602774; 2'b11: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 = - _theResult___exp__h602774; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 = + _theResult___exp__h602771; endcase end - always@(guard__h594030 or - _theResult___fst_exp__h602258 or _theResult___exp__h602774) + always@(guard__h594027 or + _theResult___fst_exp__h602255 or _theResult___exp__h602771) begin - case (guard__h594030) + case (guard__h594027) 2'b0: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 = - _theResult___fst_exp__h602258; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52 = + _theResult___fst_exp__h602255; 2'b01, 2'b10, 2'b11: - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 = - _theResult___exp__h602774; + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52 = + _theResult___exp__h602771; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51 or - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52 or + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51 or + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964 or - _theResult___fst_exp__h602258) + _theResult___fst_exp__h602255) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h602852 = - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q51; + _theResult___fst_exp__h602849 = + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q51; 3'd1: - _theResult___fst_exp__h602852 = - CASE_guard94030_0b0_theResult___fst_exp02258_0_ETC__q52; + _theResult___fst_exp__h602849 = + CASE_guard94027_0b0_theResult___fst_exp02255_0_ETC__q52; 3'd2: - _theResult___fst_exp__h602852 = + _theResult___fst_exp__h602849 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8962; 3'd3: - _theResult___fst_exp__h602852 = + _theResult___fst_exp__h602849 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8964; - 3'd4: _theResult___fst_exp__h602852 = _theResult___fst_exp__h602258; - default: _theResult___fst_exp__h602852 = 8'd0; + 3'd4: _theResult___fst_exp__h602849 = _theResult___fst_exp__h602255; + default: _theResult___fst_exp__h602849 = 8'd0; endcase end - always@(guard__h602866 or - _theResult___fst_exp__h610943 or - out_exp__h611413 or _theResult___exp__h611410) + always@(guard__h602863 or + _theResult___fst_exp__h610940 or + out_exp__h611410 or _theResult___exp__h611407) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = - _theResult___fst_exp__h610943; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 = + _theResult___fst_exp__h610940; 2'b10: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = - out_exp__h611413; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 = + out_exp__h611410; 2'b11: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 = - _theResult___exp__h611410; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 = + _theResult___exp__h611407; endcase end - always@(guard__h602866 or - _theResult___fst_exp__h610943 or _theResult___exp__h611410) + always@(guard__h602863 or + _theResult___fst_exp__h610940 or _theResult___exp__h611407) begin - case (guard__h602866) + case (guard__h602863) 2'b0: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 = - _theResult___fst_exp__h610943; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57 = + _theResult___fst_exp__h610940; 2'b01, 2'b10, 2'b11: - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 = - _theResult___exp__h611410; + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57 = + _theResult___exp__h611407; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56 or - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57 or + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56 or + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033 or - _theResult___fst_exp__h610943) + _theResult___fst_exp__h610940) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h611488 = - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q56; + _theResult___fst_exp__h611485 = + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q56; 3'd1: - _theResult___fst_exp__h611488 = - CASE_guard02866_0b0_theResult___fst_exp10943_0_ETC__q57; + _theResult___fst_exp__h611485 = + CASE_guard02863_0b0_theResult___fst_exp10940_0_ETC__q57; 3'd2: - _theResult___fst_exp__h611488 = + _theResult___fst_exp__h611485 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9031; 3'd3: - _theResult___fst_exp__h611488 = + _theResult___fst_exp__h611485 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9033; - 3'd4: _theResult___fst_exp__h611488 = _theResult___fst_exp__h610943; - default: _theResult___fst_exp__h611488 = 8'd0; + 3'd4: _theResult___fst_exp__h611485 = _theResult___fst_exp__h610940; + default: _theResult___fst_exp__h611485 = 8'd0; endcase end - always@(guard__h585100 or - _theResult___snd__h593099 or - out_sfd__h593594 or _theResult___sfd__h593591) + always@(guard__h585097 or + _theResult___snd__h593096 or + out_sfd__h593591 or _theResult___sfd__h593588) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = - _theResult___snd__h593099[56:34]; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 = + _theResult___snd__h593096[56:34]; 2'b10: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = - out_sfd__h593594; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 = + out_sfd__h593591; 2'b11: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 = - _theResult___sfd__h593591; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 = + _theResult___sfd__h593588; endcase end - always@(guard__h585100 or - _theResult___snd__h593099 or _theResult___sfd__h593591) + always@(guard__h585097 or + _theResult___snd__h593096 or _theResult___sfd__h593588) begin - case (guard__h585100) + case (guard__h585097) 2'b0: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 = - _theResult___snd__h593099[56:34]; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59 = + _theResult___snd__h593096[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 = - _theResult___sfd__h593591; + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59 = + _theResult___sfd__h593588; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58 or - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59 or + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58 or + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083 or - _theResult___snd__h593099) + _theResult___snd__h593096) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h593669 = - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q58; + _theResult___fst_sfd__h593666 = + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q58; 3'd1: - _theResult___fst_sfd__h593669 = - CASE_guard85100_0b0_theResult___snd93099_BITS__ETC__q59; + _theResult___fst_sfd__h593666 = + CASE_guard85097_0b0_theResult___snd93096_BITS__ETC__q59; 3'd2: - _theResult___fst_sfd__h593669 = + _theResult___fst_sfd__h593666 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9081; 3'd3: - _theResult___fst_sfd__h593669 = + _theResult___fst_sfd__h593666 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9083; - 3'd4: _theResult___fst_sfd__h593669 = _theResult___snd__h593099[56:34]; - default: _theResult___fst_sfd__h593669 = 23'd0; + 3'd4: _theResult___fst_sfd__h593666 = _theResult___snd__h593096[56:34]; + default: _theResult___fst_sfd__h593666 = 23'd0; endcase end - always@(guard__h576391 or - sfdin__h584486 or out_sfd__h585012 or _theResult___sfd__h585009) + always@(guard__h576388 or + sfdin__h584483 or out_sfd__h585009 or _theResult___sfd__h585006) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = - sfdin__h584486[56:34]; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 = + sfdin__h584483[56:34]; 2'b10: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = - out_sfd__h585012; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 = + out_sfd__h585009; 2'b11: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 = - _theResult___sfd__h585009; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 = + _theResult___sfd__h585006; endcase end - always@(guard__h576391 or sfdin__h584486 or _theResult___sfd__h585009) + always@(guard__h576388 or sfdin__h584483 or _theResult___sfd__h585006) begin - case (guard__h576391) + case (guard__h576388) 2'b0: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 = - sfdin__h584486[56:34]; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61 = + sfdin__h584483[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 = - _theResult___sfd__h585009; + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61 = + _theResult___sfd__h585006; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60 or - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61 or + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60 or + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064 or - sfdin__h584486) + sfdin__h584483) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h585087 = - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q60; + _theResult___fst_sfd__h585084 = + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q60; 3'd1: - _theResult___fst_sfd__h585087 = - CASE_guard76391_0b0_sfdin84486_BITS_56_TO_34_0_ETC__q61; + _theResult___fst_sfd__h585084 = + CASE_guard76388_0b0_sfdin84483_BITS_56_TO_34_0_ETC__q61; 3'd2: - _theResult___fst_sfd__h585087 = + _theResult___fst_sfd__h585084 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9062; 3'd3: - _theResult___fst_sfd__h585087 = + _theResult___fst_sfd__h585084 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9064; - 3'd4: _theResult___fst_sfd__h585087 = sfdin__h584486[56:34]; - default: _theResult___fst_sfd__h585087 = 23'd0; + 3'd4: _theResult___fst_sfd__h585084 = sfdin__h584483[56:34]; + default: _theResult___fst_sfd__h585084 = 23'd0; endcase end - always@(guard__h594030 or - sfdin__h602252 or out_sfd__h602778 or _theResult___sfd__h602775) + always@(guard__h594027 or + sfdin__h602249 or out_sfd__h602775 or _theResult___sfd__h602772) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = - sfdin__h602252[56:34]; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 = + sfdin__h602249[56:34]; 2'b10: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = - out_sfd__h602778; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 = + out_sfd__h602775; 2'b11: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 = - _theResult___sfd__h602775; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 = + _theResult___sfd__h602772; endcase end - always@(guard__h594030 or sfdin__h602252 or _theResult___sfd__h602775) + always@(guard__h594027 or sfdin__h602249 or _theResult___sfd__h602772) begin - case (guard__h594030) + case (guard__h594027) 2'b0: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 = - sfdin__h602252[56:34]; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63 = + sfdin__h602249[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 = - _theResult___sfd__h602775; + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63 = + _theResult___sfd__h602772; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62 or - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63 or + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62 or + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110 or - sfdin__h602252) + sfdin__h602249) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h602853 = - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q62; + _theResult___fst_sfd__h602850 = + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q62; 3'd1: - _theResult___fst_sfd__h602853 = - CASE_guard94030_0b0_sfdin02252_BITS_56_TO_34_0_ETC__q63; + _theResult___fst_sfd__h602850 = + CASE_guard94027_0b0_sfdin02249_BITS_56_TO_34_0_ETC__q63; 3'd2: - _theResult___fst_sfd__h602853 = + _theResult___fst_sfd__h602850 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9108; 3'd3: - _theResult___fst_sfd__h602853 = + _theResult___fst_sfd__h602850 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9110; - 3'd4: _theResult___fst_sfd__h602853 = sfdin__h602252[56:34]; - default: _theResult___fst_sfd__h602853 = 23'd0; + 3'd4: _theResult___fst_sfd__h602850 = sfdin__h602249[56:34]; + default: _theResult___fst_sfd__h602850 = 23'd0; endcase end - always@(guard__h602866 or - _theResult___snd__h610889 or - out_sfd__h611414 or _theResult___sfd__h611411) + always@(guard__h602863 or + _theResult___snd__h610886 or + out_sfd__h611411 or _theResult___sfd__h611408) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = - _theResult___snd__h610889[56:34]; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 = + _theResult___snd__h610886[56:34]; 2'b10: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = - out_sfd__h611414; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 = + out_sfd__h611411; 2'b11: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 = - _theResult___sfd__h611411; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 = + _theResult___sfd__h611408; endcase end - always@(guard__h602866 or - _theResult___snd__h610889 or _theResult___sfd__h611411) + always@(guard__h602863 or + _theResult___snd__h610886 or _theResult___sfd__h611408) begin - case (guard__h602866) + case (guard__h602863) 2'b0: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 = - _theResult___snd__h610889[56:34]; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65 = + _theResult___snd__h610886[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 = - _theResult___sfd__h611411; + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65 = + _theResult___sfd__h611408; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64 or - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65 or + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64 or + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129 or - _theResult___snd__h610889) + _theResult___snd__h610886) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h611489 = - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q64; + _theResult___fst_sfd__h611486 = + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q64; 3'd1: - _theResult___fst_sfd__h611489 = - CASE_guard02866_0b0_theResult___snd10889_BITS__ETC__q65; + _theResult___fst_sfd__h611486 = + CASE_guard02863_0b0_theResult___snd10886_BITS__ETC__q65; 3'd2: - _theResult___fst_sfd__h611489 = + _theResult___fst_sfd__h611486 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9127; 3'd3: - _theResult___fst_sfd__h611489 = + _theResult___fst_sfd__h611486 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9129; - 3'd4: _theResult___fst_sfd__h611489 = _theResult___snd__h610889[56:34]; - default: _theResult___fst_sfd__h611489 = 23'd0; + 3'd4: _theResult___fst_sfd__h611486 = _theResult___snd__h610886[56:34]; + default: _theResult___fst_sfd__h611486 = 23'd0; endcase end - always@(guard__h576391 or + always@(guard__h576388 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01, 2'b10: - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = - guard__h576391 == 2'b11 && + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 = + guard__h576388 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 or - guard__h576391) + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66 or + guard__h576388) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = - CASE_guard76391_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66; + CASE_guard76388_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q66; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = - (guard__h576391 == 2'b0) ? + (guard__h576388 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h576391 == 2'b01 || guard__h576391 == 2'b10 || - guard__h576391 == 2'b11) && + (guard__h576388 == 2'b01 || guard__h576388 == 2'b10 || + guard__h576388 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9215 = @@ -39355,34 +39355,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h576391 or + always@(guard__h576388 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576391) + case (guard__h576388) 2'b0, 2'b01, 2'b10: - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = - guard__h576391 != 2'b11 || + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 = + guard__h576388 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 or - guard__h576391) + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67 or + guard__h576388) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = - CASE_guard76391_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67; + CASE_guard76388_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q67; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = - (guard__h576391 == 2'b0) ? + (guard__h576388 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h576391 != 2'b01 && guard__h576391 != 2'b10 && - guard__h576391 != 2'b11 || + guard__h576388 != 2'b01 && guard__h576388 != 2'b10 && + guard__h576388 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9159 = @@ -39393,34 +39393,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585100 or + always@(guard__h585097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01, 2'b10: - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = - guard__h585100 == 2'b11 && + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = + guard__h585097 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 or - guard__h585100) + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 or + guard__h585097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = - CASE_guard85100_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68; + CASE_guard85097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = - (guard__h585100 == 2'b0) ? + (guard__h585097 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h585100 == 2'b01 || guard__h585100 == 2'b10 || - guard__h585100 == 2'b11) && + (guard__h585097 == 2'b01 || guard__h585097 == 2'b10 || + guard__h585097 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9222 = @@ -39431,34 +39431,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585100 or + always@(guard__h585097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585100) + case (guard__h585097) 2'b0, 2'b01, 2'b10: - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = - guard__h585100 != 2'b11 || + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = + guard__h585097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 or - guard__h585100) + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 or + guard__h585097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = - CASE_guard85100_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69; + CASE_guard85097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = - (guard__h585100 == 2'b0) ? + (guard__h585097 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h585100 != 2'b01 && guard__h585100 != 2'b10 && - guard__h585100 != 2'b11 || + guard__h585097 != 2'b01 && guard__h585097 != 2'b10 && + guard__h585097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9172 = @@ -39469,34 +39469,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594030 or + always@(guard__h594027 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01, 2'b10: - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = - guard__h594030 == 2'b11 && + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + guard__h594027 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 or - guard__h594030) + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 or + guard__h594027) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = - CASE_guard94030_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70; + CASE_guard94027_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = - (guard__h594030 == 2'b0) ? + (guard__h594027 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h594030 == 2'b01 || guard__h594030 == 2'b10 || - guard__h594030 == 2'b11) && + (guard__h594027 == 2'b01 || guard__h594027 == 2'b10 || + guard__h594027 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9232 = @@ -39507,34 +39507,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594030 or + always@(guard__h594027 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594030) + case (guard__h594027) 2'b0, 2'b01, 2'b10: - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = - guard__h594030 != 2'b11 || + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = + guard__h594027 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 or - guard__h594030) + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 or + guard__h594027) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = - CASE_guard94030_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71; + CASE_guard94027_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = - (guard__h594030 == 2'b0) ? + (guard__h594027 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h594030 != 2'b01 && guard__h594030 != 2'b10 && - guard__h594030 != 2'b11 || + guard__h594027 != 2'b01 && guard__h594027 != 2'b10 && + guard__h594027 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9189 = @@ -39545,34 +39545,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602866 or + always@(guard__h602863 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01, 2'b10: - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = - guard__h602866 == 2'b11 && + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = + guard__h602863 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 or - guard__h602866) + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 or + guard__h602863) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = - CASE_guard02866_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72; + CASE_guard02863_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = - (guard__h602866 == 2'b0) ? + (guard__h602863 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h602866 == 2'b01 || guard__h602866 == 2'b10 || - guard__h602866 == 2'b11) && + (guard__h602863 == 2'b01 || guard__h602863 == 2'b10 || + guard__h602863 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9239 = @@ -39583,34 +39583,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602866 or + always@(guard__h602863 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602866) + case (guard__h602863) 2'b0, 2'b01, 2'b10: - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = - guard__h602866 != 2'b11 || + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + guard__h602863 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 or - guard__h602866) + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 or + guard__h602863) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = - CASE_guard02866_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73; + CASE_guard02863_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = - (guard__h602866 == 2'b0) ? + (guard__h602863 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h602866 != 2'b01 && guard__h602866 != 2'b10 && - guard__h602866 != 2'b11 || + guard__h602863 != 2'b01 && guard__h602863 != 2'b10 && + guard__h602863 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9202 = @@ -39647,446 +39647,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h630849 or - _theResult___fst_exp__h638897 or - out_exp__h639342 or _theResult___exp__h639339) + always@(guard__h630846 or + _theResult___fst_exp__h638894 or + out_exp__h639339 or _theResult___exp__h639336) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = - _theResult___fst_exp__h638897; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 = + _theResult___fst_exp__h638894; 2'b10: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = - out_exp__h639342; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 = + out_exp__h639339; 2'b11: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 = - _theResult___exp__h639339; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 = + _theResult___exp__h639336; endcase end - always@(guard__h630849 or - _theResult___fst_exp__h638897 or _theResult___exp__h639339) + always@(guard__h630846 or + _theResult___fst_exp__h638894 or _theResult___exp__h639336) begin - case (guard__h630849) + case (guard__h630846) 2'b0: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 = - _theResult___fst_exp__h638897; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79 = + _theResult___fst_exp__h638894; 2'b01, 2'b10, 2'b11: - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 = - _theResult___exp__h639339; + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79 = + _theResult___exp__h639336; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78 or - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79 or + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78 or + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036 or - _theResult___fst_exp__h638897) + _theResult___fst_exp__h638894) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h639417 = - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q78; + _theResult___fst_exp__h639414 = + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q78; 3'd1: - _theResult___fst_exp__h639417 = - CASE_guard30849_0b0_theResult___fst_exp38897_0_ETC__q79; + _theResult___fst_exp__h639414 = + CASE_guard30846_0b0_theResult___fst_exp38894_0_ETC__q79; 3'd2: - _theResult___fst_exp__h639417 = + _theResult___fst_exp__h639414 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10034; 3'd3: - _theResult___fst_exp__h639417 = + _theResult___fst_exp__h639414 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10036; - 3'd4: _theResult___fst_exp__h639417 = _theResult___fst_exp__h638897; - default: _theResult___fst_exp__h639417 = 8'd0; + 3'd4: _theResult___fst_exp__h639414 = _theResult___fst_exp__h638894; + default: _theResult___fst_exp__h639414 = 8'd0; endcase end - always@(guard__h622142 or - _theResult___fst_exp__h630241 or - out_exp__h630760 or _theResult___exp__h630757) + always@(guard__h622139 or + _theResult___fst_exp__h630238 or + out_exp__h630757 or _theResult___exp__h630754) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = - _theResult___fst_exp__h630241; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 = + _theResult___fst_exp__h630238; 2'b10: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = - out_exp__h630760; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 = + out_exp__h630757; 2'b11: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 = - _theResult___exp__h630757; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 = + _theResult___exp__h630754; endcase end - always@(guard__h622142 or - _theResult___fst_exp__h630241 or _theResult___exp__h630757) + always@(guard__h622139 or + _theResult___fst_exp__h630238 or _theResult___exp__h630754) begin - case (guard__h622142) + case (guard__h622139) 2'b0: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 = - _theResult___fst_exp__h630241; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81 = + _theResult___fst_exp__h630238; 2'b01, 2'b10, 2'b11: - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 = - _theResult___exp__h630757; + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81 = + _theResult___exp__h630754; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80 or - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81 or + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80 or + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815 or - _theResult___fst_exp__h630241) + _theResult___fst_exp__h630238) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h630835 = - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q80; + _theResult___fst_exp__h630832 = + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q80; 3'd1: - _theResult___fst_exp__h630835 = - CASE_guard22142_0b0_theResult___fst_exp30241_0_ETC__q81; + _theResult___fst_exp__h630832 = + CASE_guard22139_0b0_theResult___fst_exp30238_0_ETC__q81; 3'd2: - _theResult___fst_exp__h630835 = + _theResult___fst_exp__h630832 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9812; 3'd3: - _theResult___fst_exp__h630835 = + _theResult___fst_exp__h630832 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9815; - 3'd4: _theResult___fst_exp__h630835 = _theResult___fst_exp__h630241; - default: _theResult___fst_exp__h630835 = 8'd0; + 3'd4: _theResult___fst_exp__h630832 = _theResult___fst_exp__h630238; + default: _theResult___fst_exp__h630832 = 8'd0; endcase end - always@(guard__h639779 or - _theResult___fst_exp__h648007 or - out_exp__h648526 or _theResult___exp__h648523) + always@(guard__h639776 or + _theResult___fst_exp__h648004 or + out_exp__h648523 or _theResult___exp__h648520) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = - _theResult___fst_exp__h648007; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 = + _theResult___fst_exp__h648004; 2'b10: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = - out_exp__h648526; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 = + out_exp__h648523; 2'b11: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 = - _theResult___exp__h648523; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 = + _theResult___exp__h648520; endcase end - always@(guard__h639779 or - _theResult___fst_exp__h648007 or _theResult___exp__h648523) + always@(guard__h639776 or + _theResult___fst_exp__h648004 or _theResult___exp__h648520) begin - case (guard__h639779) + case (guard__h639776) 2'b0: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 = - _theResult___fst_exp__h648007; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87 = + _theResult___fst_exp__h648004; 2'b01, 2'b10, 2'b11: - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 = - _theResult___exp__h648523; + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87 = + _theResult___exp__h648520; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86 or - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87 or + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86 or + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361 or - _theResult___fst_exp__h648007) + _theResult___fst_exp__h648004) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h648601 = - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q86; + _theResult___fst_exp__h648598 = + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q86; 3'd1: - _theResult___fst_exp__h648601 = - CASE_guard39779_0b0_theResult___fst_exp48007_0_ETC__q87; + _theResult___fst_exp__h648598 = + CASE_guard39776_0b0_theResult___fst_exp48004_0_ETC__q87; 3'd2: - _theResult___fst_exp__h648601 = + _theResult___fst_exp__h648598 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10359; 3'd3: - _theResult___fst_exp__h648601 = + _theResult___fst_exp__h648598 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10361; - 3'd4: _theResult___fst_exp__h648601 = _theResult___fst_exp__h648007; - default: _theResult___fst_exp__h648601 = 8'd0; + 3'd4: _theResult___fst_exp__h648598 = _theResult___fst_exp__h648004; + default: _theResult___fst_exp__h648598 = 8'd0; endcase end - always@(guard__h648615 or - _theResult___fst_exp__h656692 or - out_exp__h657162 or _theResult___exp__h657159) + always@(guard__h648612 or + _theResult___fst_exp__h656689 or + out_exp__h657159 or _theResult___exp__h657156) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = - _theResult___fst_exp__h656692; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 = + _theResult___fst_exp__h656689; 2'b10: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = - out_exp__h657162; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 = + out_exp__h657159; 2'b11: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 = - _theResult___exp__h657159; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 = + _theResult___exp__h657156; endcase end - always@(guard__h648615 or - _theResult___fst_exp__h656692 or _theResult___exp__h657159) + always@(guard__h648612 or + _theResult___fst_exp__h656689 or _theResult___exp__h657156) begin - case (guard__h648615) + case (guard__h648612) 2'b0: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 = - _theResult___fst_exp__h656692; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92 = + _theResult___fst_exp__h656689; 2'b01, 2'b10, 2'b11: - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 = - _theResult___exp__h657159; + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92 = + _theResult___exp__h657156; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91 or - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92 or + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91 or + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430 or - _theResult___fst_exp__h656692) + _theResult___fst_exp__h656689) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h657237 = - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q91; + _theResult___fst_exp__h657234 = + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q91; 3'd1: - _theResult___fst_exp__h657237 = - CASE_guard48615_0b0_theResult___fst_exp56692_0_ETC__q92; + _theResult___fst_exp__h657234 = + CASE_guard48612_0b0_theResult___fst_exp56689_0_ETC__q92; 3'd2: - _theResult___fst_exp__h657237 = + _theResult___fst_exp__h657234 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10428; 3'd3: - _theResult___fst_exp__h657237 = + _theResult___fst_exp__h657234 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10430; - 3'd4: _theResult___fst_exp__h657237 = _theResult___fst_exp__h656692; - default: _theResult___fst_exp__h657237 = 8'd0; + 3'd4: _theResult___fst_exp__h657234 = _theResult___fst_exp__h656689; + default: _theResult___fst_exp__h657234 = 8'd0; endcase end - always@(guard__h630849 or - _theResult___snd__h638848 or - out_sfd__h639343 or _theResult___sfd__h639340) + always@(guard__h630846 or + _theResult___snd__h638845 or + out_sfd__h639340 or _theResult___sfd__h639337) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = - _theResult___snd__h638848[56:34]; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 = + _theResult___snd__h638845[56:34]; 2'b10: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = - out_sfd__h639343; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 = + out_sfd__h639340; 2'b11: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 = - _theResult___sfd__h639340; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 = + _theResult___sfd__h639337; endcase end - always@(guard__h630849 or - _theResult___snd__h638848 or _theResult___sfd__h639340) + always@(guard__h630846 or + _theResult___snd__h638845 or _theResult___sfd__h639337) begin - case (guard__h630849) + case (guard__h630846) 2'b0: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 = - _theResult___snd__h638848[56:34]; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94 = + _theResult___snd__h638845[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 = - _theResult___sfd__h639340; + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94 = + _theResult___sfd__h639337; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93 or - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94 or + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93 or + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480 or - _theResult___snd__h638848) + _theResult___snd__h638845) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h639418 = - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q93; + _theResult___fst_sfd__h639415 = + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q93; 3'd1: - _theResult___fst_sfd__h639418 = - CASE_guard30849_0b0_theResult___snd38848_BITS__ETC__q94; + _theResult___fst_sfd__h639415 = + CASE_guard30846_0b0_theResult___snd38845_BITS__ETC__q94; 3'd2: - _theResult___fst_sfd__h639418 = + _theResult___fst_sfd__h639415 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10478; 3'd3: - _theResult___fst_sfd__h639418 = + _theResult___fst_sfd__h639415 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10480; - 3'd4: _theResult___fst_sfd__h639418 = _theResult___snd__h638848[56:34]; - default: _theResult___fst_sfd__h639418 = 23'd0; + 3'd4: _theResult___fst_sfd__h639415 = _theResult___snd__h638845[56:34]; + default: _theResult___fst_sfd__h639415 = 23'd0; endcase end - always@(guard__h622142 or - sfdin__h630235 or out_sfd__h630761 or _theResult___sfd__h630758) + always@(guard__h622139 or + sfdin__h630232 or out_sfd__h630758 or _theResult___sfd__h630755) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = - sfdin__h630235[56:34]; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 = + sfdin__h630232[56:34]; 2'b10: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = - out_sfd__h630761; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 = + out_sfd__h630758; 2'b11: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 = - _theResult___sfd__h630758; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 = + _theResult___sfd__h630755; endcase end - always@(guard__h622142 or sfdin__h630235 or _theResult___sfd__h630758) + always@(guard__h622139 or sfdin__h630232 or _theResult___sfd__h630755) begin - case (guard__h622142) + case (guard__h622139) 2'b0: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 = - sfdin__h630235[56:34]; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96 = + sfdin__h630232[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 = - _theResult___sfd__h630758; + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96 = + _theResult___sfd__h630755; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95 or - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96 or + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95 or + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461 or - sfdin__h630235) + sfdin__h630232) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h630836 = - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q95; + _theResult___fst_sfd__h630833 = + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q95; 3'd1: - _theResult___fst_sfd__h630836 = - CASE_guard22142_0b0_sfdin30235_BITS_56_TO_34_0_ETC__q96; + _theResult___fst_sfd__h630833 = + CASE_guard22139_0b0_sfdin30232_BITS_56_TO_34_0_ETC__q96; 3'd2: - _theResult___fst_sfd__h630836 = + _theResult___fst_sfd__h630833 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10459; 3'd3: - _theResult___fst_sfd__h630836 = + _theResult___fst_sfd__h630833 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10461; - 3'd4: _theResult___fst_sfd__h630836 = sfdin__h630235[56:34]; - default: _theResult___fst_sfd__h630836 = 23'd0; + 3'd4: _theResult___fst_sfd__h630833 = sfdin__h630232[56:34]; + default: _theResult___fst_sfd__h630833 = 23'd0; endcase end - always@(guard__h639779 or - sfdin__h648001 or out_sfd__h648527 or _theResult___sfd__h648524) + always@(guard__h639776 or + sfdin__h647998 or out_sfd__h648524 or _theResult___sfd__h648521) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = - sfdin__h648001[56:34]; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 = + sfdin__h647998[56:34]; 2'b10: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = - out_sfd__h648527; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 = + out_sfd__h648524; 2'b11: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 = - _theResult___sfd__h648524; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 = + _theResult___sfd__h648521; endcase end - always@(guard__h639779 or sfdin__h648001 or _theResult___sfd__h648524) + always@(guard__h639776 or sfdin__h647998 or _theResult___sfd__h648521) begin - case (guard__h639779) + case (guard__h639776) 2'b0: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 = - sfdin__h648001[56:34]; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98 = + sfdin__h647998[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 = - _theResult___sfd__h648524; + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98 = + _theResult___sfd__h648521; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97 or - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98 or + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97 or + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 or - sfdin__h648001) + sfdin__h647998) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h648602 = - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q97; + _theResult___fst_sfd__h648599 = + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q97; 3'd1: - _theResult___fst_sfd__h648602 = - CASE_guard39779_0b0_sfdin48001_BITS_56_TO_34_0_ETC__q98; + _theResult___fst_sfd__h648599 = + CASE_guard39776_0b0_sfdin47998_BITS_56_TO_34_0_ETC__q98; 3'd2: - _theResult___fst_sfd__h648602 = + _theResult___fst_sfd__h648599 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505; 3'd3: - _theResult___fst_sfd__h648602 = + _theResult___fst_sfd__h648599 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507; - 3'd4: _theResult___fst_sfd__h648602 = sfdin__h648001[56:34]; - default: _theResult___fst_sfd__h648602 = 23'd0; + 3'd4: _theResult___fst_sfd__h648599 = sfdin__h647998[56:34]; + default: _theResult___fst_sfd__h648599 = 23'd0; endcase end - always@(guard__h648615 or - _theResult___snd__h656638 or - out_sfd__h657163 or _theResult___sfd__h657160) + always@(guard__h648612 or + _theResult___snd__h656635 or + out_sfd__h657160 or _theResult___sfd__h657157) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = - _theResult___snd__h656638[56:34]; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 = + _theResult___snd__h656635[56:34]; 2'b10: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = - out_sfd__h657163; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 = + out_sfd__h657160; 2'b11: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 = - _theResult___sfd__h657160; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 = + _theResult___sfd__h657157; endcase end - always@(guard__h648615 or - _theResult___snd__h656638 or _theResult___sfd__h657160) + always@(guard__h648612 or + _theResult___snd__h656635 or _theResult___sfd__h657157) begin - case (guard__h648615) + case (guard__h648612) 2'b0: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 = - _theResult___snd__h656638[56:34]; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100 = + _theResult___snd__h656635[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 = - _theResult___sfd__h657160; + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100 = + _theResult___sfd__h657157; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99 or - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100 or + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99 or + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526 or - _theResult___snd__h656638) + _theResult___snd__h656635) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h657238 = - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q99; + _theResult___fst_sfd__h657235 = + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q99; 3'd1: - _theResult___fst_sfd__h657238 = - CASE_guard48615_0b0_theResult___snd56638_BITS__ETC__q100; + _theResult___fst_sfd__h657235 = + CASE_guard48612_0b0_theResult___snd56635_BITS__ETC__q100; 3'd2: - _theResult___fst_sfd__h657238 = + _theResult___fst_sfd__h657235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10524; 3'd3: - _theResult___fst_sfd__h657238 = + _theResult___fst_sfd__h657235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10526; - 3'd4: _theResult___fst_sfd__h657238 = _theResult___snd__h656638[56:34]; - default: _theResult___fst_sfd__h657238 = 23'd0; + 3'd4: _theResult___fst_sfd__h657235 = _theResult___snd__h656635[56:34]; + default: _theResult___fst_sfd__h657235 = 23'd0; endcase end - always@(guard__h622142 or + always@(guard__h622139 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01, 2'b10: - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = - guard__h622142 == 2'b11 && + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 = + guard__h622139 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 or - guard__h622142) + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101 or + guard__h622139) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = - CASE_guard22142_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101; + CASE_guard22139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q101; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = - (guard__h622142 == 2'b0) ? + (guard__h622139 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h622142 == 2'b01 || guard__h622142 == 2'b10 || - guard__h622142 == 2'b11) && + (guard__h622139 == 2'b01 || guard__h622139 == 2'b10 || + guard__h622139 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10612 = @@ -40097,34 +40097,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h622142 or + always@(guard__h622139 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622142) + case (guard__h622139) 2'b0, 2'b01, 2'b10: - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = - guard__h622142 != 2'b11 || + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 = + guard__h622139 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 or - guard__h622142) + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102 or + guard__h622139) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = - CASE_guard22142_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102; + CASE_guard22139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q102; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = - (guard__h622142 == 2'b0) ? + (guard__h622139 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h622142 != 2'b01 && guard__h622142 != 2'b10 && - guard__h622142 != 2'b11 || + guard__h622139 != 2'b01 && guard__h622139 != 2'b10 && + guard__h622139 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10556 = @@ -40135,34 +40135,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630849 or + always@(guard__h630846 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01, 2'b10: - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = - guard__h630849 == 2'b11 && + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = + guard__h630846 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 or - guard__h630849) + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 or + guard__h630846) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = - CASE_guard30849_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103; + CASE_guard30846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = - (guard__h630849 == 2'b0) ? + (guard__h630846 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h630849 == 2'b01 || guard__h630849 == 2'b10 || - guard__h630849 == 2'b11) && + (guard__h630846 == 2'b01 || guard__h630846 == 2'b10 || + guard__h630846 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10619 = @@ -40173,34 +40173,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630849 or + always@(guard__h630846 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630849) + case (guard__h630846) 2'b0, 2'b01, 2'b10: - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = - guard__h630849 != 2'b11 || + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = + guard__h630846 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 or - guard__h630849) + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 or + guard__h630846) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = - CASE_guard30849_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104; + CASE_guard30846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = - (guard__h630849 == 2'b0) ? + (guard__h630846 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h630849 != 2'b01 && guard__h630849 != 2'b10 && - guard__h630849 != 2'b11 || + guard__h630846 != 2'b01 && guard__h630846 != 2'b10 && + guard__h630846 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10569 = @@ -40211,34 +40211,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639779 or + always@(guard__h639776 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01, 2'b10: - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = - guard__h639779 == 2'b11 && + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = + guard__h639776 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 or - guard__h639779) + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 or + guard__h639776) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = - CASE_guard39779_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105; + CASE_guard39776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = - (guard__h639779 == 2'b0) ? + (guard__h639776 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h639779 == 2'b01 || guard__h639779 == 2'b10 || - guard__h639779 == 2'b11) && + (guard__h639776 == 2'b01 || guard__h639776 == 2'b10 || + guard__h639776 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10629 = @@ -40249,34 +40249,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639779 or + always@(guard__h639776 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639779) + case (guard__h639776) 2'b0, 2'b01, 2'b10: - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = - guard__h639779 != 2'b11 || + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + guard__h639776 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 or - guard__h639779) + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 or + guard__h639776) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = - CASE_guard39779_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106; + CASE_guard39776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = - (guard__h639779 == 2'b0) ? + (guard__h639776 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h639779 != 2'b01 && guard__h639779 != 2'b10 && - guard__h639779 != 2'b11 || + guard__h639776 != 2'b01 && guard__h639776 != 2'b10 && + guard__h639776 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10586 = @@ -40287,34 +40287,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648615 or + always@(guard__h648612 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01, 2'b10: - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = - guard__h648615 == 2'b11 && + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = + guard__h648612 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 or - guard__h648615) + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 or + guard__h648612) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = - CASE_guard48615_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107; + CASE_guard48612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = - (guard__h648615 == 2'b0) ? + (guard__h648612 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h648615 == 2'b01 || guard__h648615 == 2'b10 || - guard__h648615 == 2'b11) && + (guard__h648612 == 2'b01 || guard__h648612 == 2'b10 || + guard__h648612 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10636 = @@ -40325,34 +40325,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648615 or + always@(guard__h648612 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648615) + case (guard__h648612) 2'b0, 2'b01, 2'b10: - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = - guard__h648615 != 2'b11 || + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = + guard__h648612 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 or - guard__h648615) + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 or + guard__h648612) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = - CASE_guard48615_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108; + CASE_guard48612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = - (guard__h648615 == 2'b0) ? + (guard__h648612 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h648615 != 2'b01 && guard__h648615 != 2'b10 && - guard__h648615 != 2'b11 || + guard__h648612 != 2'b01 && guard__h648612 != 2'b10 && + guard__h648612 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10599 = @@ -40389,446 +40389,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h676596 or - _theResult___fst_exp__h684644 or - out_exp__h685089 or _theResult___exp__h685086) + always@(guard__h676593 or + _theResult___fst_exp__h684641 or + out_exp__h685086 or _theResult___exp__h685083) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = - _theResult___fst_exp__h684644; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 = + _theResult___fst_exp__h684641; 2'b10: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = - out_exp__h685089; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 = + out_exp__h685086; 2'b11: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 = - _theResult___exp__h685086; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 = + _theResult___exp__h685083; endcase end - always@(guard__h676596 or - _theResult___fst_exp__h684644 or _theResult___exp__h685086) + always@(guard__h676593 or + _theResult___fst_exp__h684641 or _theResult___exp__h685083) begin - case (guard__h676596) + case (guard__h676593) 2'b0: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 = - _theResult___fst_exp__h684644; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114 = + _theResult___fst_exp__h684641; 2'b01, 2'b10, 2'b11: - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 = - _theResult___exp__h685086; + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114 = + _theResult___exp__h685083; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113 or - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114 or + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113 or + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433 or - _theResult___fst_exp__h684644) + _theResult___fst_exp__h684641) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h685164 = - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q113; + _theResult___fst_exp__h685161 = + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q113; 3'd1: - _theResult___fst_exp__h685164 = - CASE_guard76596_0b0_theResult___fst_exp84644_0_ETC__q114; + _theResult___fst_exp__h685161 = + CASE_guard76593_0b0_theResult___fst_exp84641_0_ETC__q114; 3'd2: - _theResult___fst_exp__h685164 = + _theResult___fst_exp__h685161 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11431; 3'd3: - _theResult___fst_exp__h685164 = + _theResult___fst_exp__h685161 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11433; - 3'd4: _theResult___fst_exp__h685164 = _theResult___fst_exp__h684644; - default: _theResult___fst_exp__h685164 = 8'd0; + 3'd4: _theResult___fst_exp__h685161 = _theResult___fst_exp__h684641; + default: _theResult___fst_exp__h685161 = 8'd0; endcase end - always@(guard__h667889 or - _theResult___fst_exp__h675988 or - out_exp__h676507 or _theResult___exp__h676504) + always@(guard__h667886 or + _theResult___fst_exp__h675985 or + out_exp__h676504 or _theResult___exp__h676501) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = - _theResult___fst_exp__h675988; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 = + _theResult___fst_exp__h675985; 2'b10: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = - out_exp__h676507; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 = + out_exp__h676504; 2'b11: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 = - _theResult___exp__h676504; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 = + _theResult___exp__h676501; endcase end - always@(guard__h667889 or - _theResult___fst_exp__h675988 or _theResult___exp__h676504) + always@(guard__h667886 or + _theResult___fst_exp__h675985 or _theResult___exp__h676501) begin - case (guard__h667889) + case (guard__h667886) 2'b0: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 = - _theResult___fst_exp__h675988; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116 = + _theResult___fst_exp__h675985; 2'b01, 2'b10, 2'b11: - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 = - _theResult___exp__h676504; + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116 = + _theResult___exp__h676501; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115 or - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116 or + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115 or + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212 or - _theResult___fst_exp__h675988) + _theResult___fst_exp__h675985) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h676582 = - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q115; + _theResult___fst_exp__h676579 = + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q115; 3'd1: - _theResult___fst_exp__h676582 = - CASE_guard67889_0b0_theResult___fst_exp75988_0_ETC__q116; + _theResult___fst_exp__h676579 = + CASE_guard67886_0b0_theResult___fst_exp75985_0_ETC__q116; 3'd2: - _theResult___fst_exp__h676582 = + _theResult___fst_exp__h676579 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11209; 3'd3: - _theResult___fst_exp__h676582 = + _theResult___fst_exp__h676579 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11212; - 3'd4: _theResult___fst_exp__h676582 = _theResult___fst_exp__h675988; - default: _theResult___fst_exp__h676582 = 8'd0; + 3'd4: _theResult___fst_exp__h676579 = _theResult___fst_exp__h675985; + default: _theResult___fst_exp__h676579 = 8'd0; endcase end - always@(guard__h685526 or - _theResult___fst_exp__h693754 or - out_exp__h694273 or _theResult___exp__h694270) + always@(guard__h685523 or + _theResult___fst_exp__h693751 or + out_exp__h694270 or _theResult___exp__h694267) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = - _theResult___fst_exp__h693754; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 = + _theResult___fst_exp__h693751; 2'b10: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = - out_exp__h694273; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 = + out_exp__h694270; 2'b11: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 = - _theResult___exp__h694270; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 = + _theResult___exp__h694267; endcase end - always@(guard__h685526 or - _theResult___fst_exp__h693754 or _theResult___exp__h694270) + always@(guard__h685523 or + _theResult___fst_exp__h693751 or _theResult___exp__h694267) begin - case (guard__h685526) + case (guard__h685523) 2'b0: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 = - _theResult___fst_exp__h693754; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122 = + _theResult___fst_exp__h693751; 2'b01, 2'b10, 2'b11: - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 = - _theResult___exp__h694270; + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122 = + _theResult___exp__h694267; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121 or - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122 or + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121 or + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758 or - _theResult___fst_exp__h693754) + _theResult___fst_exp__h693751) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h694348 = - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q121; + _theResult___fst_exp__h694345 = + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q121; 3'd1: - _theResult___fst_exp__h694348 = - CASE_guard85526_0b0_theResult___fst_exp93754_0_ETC__q122; + _theResult___fst_exp__h694345 = + CASE_guard85523_0b0_theResult___fst_exp93751_0_ETC__q122; 3'd2: - _theResult___fst_exp__h694348 = + _theResult___fst_exp__h694345 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11756; 3'd3: - _theResult___fst_exp__h694348 = + _theResult___fst_exp__h694345 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11758; - 3'd4: _theResult___fst_exp__h694348 = _theResult___fst_exp__h693754; - default: _theResult___fst_exp__h694348 = 8'd0; + 3'd4: _theResult___fst_exp__h694345 = _theResult___fst_exp__h693751; + default: _theResult___fst_exp__h694345 = 8'd0; endcase end - always@(guard__h694362 or - _theResult___fst_exp__h702439 or - out_exp__h702909 or _theResult___exp__h702906) + always@(guard__h694359 or + _theResult___fst_exp__h702436 or + out_exp__h702906 or _theResult___exp__h702903) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = - _theResult___fst_exp__h702439; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 = + _theResult___fst_exp__h702436; 2'b10: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = - out_exp__h702909; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 = + out_exp__h702906; 2'b11: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 = - _theResult___exp__h702906; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 = + _theResult___exp__h702903; endcase end - always@(guard__h694362 or - _theResult___fst_exp__h702439 or _theResult___exp__h702906) + always@(guard__h694359 or + _theResult___fst_exp__h702436 or _theResult___exp__h702903) begin - case (guard__h694362) + case (guard__h694359) 2'b0: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 = - _theResult___fst_exp__h702439; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127 = + _theResult___fst_exp__h702436; 2'b01, 2'b10, 2'b11: - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 = - _theResult___exp__h702906; + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127 = + _theResult___exp__h702903; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126 or - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127 or + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126 or + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827 or - _theResult___fst_exp__h702439) + _theResult___fst_exp__h702436) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h702984 = - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q126; + _theResult___fst_exp__h702981 = + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q126; 3'd1: - _theResult___fst_exp__h702984 = - CASE_guard94362_0b0_theResult___fst_exp02439_0_ETC__q127; + _theResult___fst_exp__h702981 = + CASE_guard94359_0b0_theResult___fst_exp02436_0_ETC__q127; 3'd2: - _theResult___fst_exp__h702984 = + _theResult___fst_exp__h702981 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11825; 3'd3: - _theResult___fst_exp__h702984 = + _theResult___fst_exp__h702981 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11827; - 3'd4: _theResult___fst_exp__h702984 = _theResult___fst_exp__h702439; - default: _theResult___fst_exp__h702984 = 8'd0; + 3'd4: _theResult___fst_exp__h702981 = _theResult___fst_exp__h702436; + default: _theResult___fst_exp__h702981 = 8'd0; endcase end - always@(guard__h676596 or - _theResult___snd__h684595 or - out_sfd__h685090 or _theResult___sfd__h685087) + always@(guard__h676593 or + _theResult___snd__h684592 or + out_sfd__h685087 or _theResult___sfd__h685084) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = - _theResult___snd__h684595[56:34]; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 = + _theResult___snd__h684592[56:34]; 2'b10: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = - out_sfd__h685090; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 = + out_sfd__h685087; 2'b11: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 = - _theResult___sfd__h685087; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 = + _theResult___sfd__h685084; endcase end - always@(guard__h676596 or - _theResult___snd__h684595 or _theResult___sfd__h685087) + always@(guard__h676593 or + _theResult___snd__h684592 or _theResult___sfd__h685084) begin - case (guard__h676596) + case (guard__h676593) 2'b0: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 = - _theResult___snd__h684595[56:34]; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129 = + _theResult___snd__h684592[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 = - _theResult___sfd__h685087; + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129 = + _theResult___sfd__h685084; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128 or - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129 or + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128 or + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877 or - _theResult___snd__h684595) + _theResult___snd__h684592) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h685165 = - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q128; + _theResult___fst_sfd__h685162 = + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q128; 3'd1: - _theResult___fst_sfd__h685165 = - CASE_guard76596_0b0_theResult___snd84595_BITS__ETC__q129; + _theResult___fst_sfd__h685162 = + CASE_guard76593_0b0_theResult___snd84592_BITS__ETC__q129; 3'd2: - _theResult___fst_sfd__h685165 = + _theResult___fst_sfd__h685162 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11875; 3'd3: - _theResult___fst_sfd__h685165 = + _theResult___fst_sfd__h685162 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11877; - 3'd4: _theResult___fst_sfd__h685165 = _theResult___snd__h684595[56:34]; - default: _theResult___fst_sfd__h685165 = 23'd0; + 3'd4: _theResult___fst_sfd__h685162 = _theResult___snd__h684592[56:34]; + default: _theResult___fst_sfd__h685162 = 23'd0; endcase end - always@(guard__h667889 or - sfdin__h675982 or out_sfd__h676508 or _theResult___sfd__h676505) + always@(guard__h667886 or + sfdin__h675979 or out_sfd__h676505 or _theResult___sfd__h676502) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = - sfdin__h675982[56:34]; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 = + sfdin__h675979[56:34]; 2'b10: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = - out_sfd__h676508; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 = + out_sfd__h676505; 2'b11: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 = - _theResult___sfd__h676505; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 = + _theResult___sfd__h676502; endcase end - always@(guard__h667889 or sfdin__h675982 or _theResult___sfd__h676505) + always@(guard__h667886 or sfdin__h675979 or _theResult___sfd__h676502) begin - case (guard__h667889) + case (guard__h667886) 2'b0: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 = - sfdin__h675982[56:34]; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131 = + sfdin__h675979[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 = - _theResult___sfd__h676505; + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131 = + _theResult___sfd__h676502; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130 or - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131 or + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130 or + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858 or - sfdin__h675982) + sfdin__h675979) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h676583 = - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q130; + _theResult___fst_sfd__h676580 = + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q130; 3'd1: - _theResult___fst_sfd__h676583 = - CASE_guard67889_0b0_sfdin75982_BITS_56_TO_34_0_ETC__q131; + _theResult___fst_sfd__h676580 = + CASE_guard67886_0b0_sfdin75979_BITS_56_TO_34_0_ETC__q131; 3'd2: - _theResult___fst_sfd__h676583 = + _theResult___fst_sfd__h676580 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11856; 3'd3: - _theResult___fst_sfd__h676583 = + _theResult___fst_sfd__h676580 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11858; - 3'd4: _theResult___fst_sfd__h676583 = sfdin__h675982[56:34]; - default: _theResult___fst_sfd__h676583 = 23'd0; + 3'd4: _theResult___fst_sfd__h676580 = sfdin__h675979[56:34]; + default: _theResult___fst_sfd__h676580 = 23'd0; endcase end - always@(guard__h685526 or - sfdin__h693748 or out_sfd__h694274 or _theResult___sfd__h694271) + always@(guard__h685523 or + sfdin__h693745 or out_sfd__h694271 or _theResult___sfd__h694268) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = - sfdin__h693748[56:34]; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 = + sfdin__h693745[56:34]; 2'b10: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = - out_sfd__h694274; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 = + out_sfd__h694271; 2'b11: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 = - _theResult___sfd__h694271; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 = + _theResult___sfd__h694268; endcase end - always@(guard__h685526 or sfdin__h693748 or _theResult___sfd__h694271) + always@(guard__h685523 or sfdin__h693745 or _theResult___sfd__h694268) begin - case (guard__h685526) + case (guard__h685523) 2'b0: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 = - sfdin__h693748[56:34]; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133 = + sfdin__h693745[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h694271; + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133 = + _theResult___sfd__h694268; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132 or - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133 or + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132 or + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904 or - sfdin__h693748) + sfdin__h693745) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h694349 = - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q132; + _theResult___fst_sfd__h694346 = + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q132; 3'd1: - _theResult___fst_sfd__h694349 = - CASE_guard85526_0b0_sfdin93748_BITS_56_TO_34_0_ETC__q133; + _theResult___fst_sfd__h694346 = + CASE_guard85523_0b0_sfdin93745_BITS_56_TO_34_0_ETC__q133; 3'd2: - _theResult___fst_sfd__h694349 = + _theResult___fst_sfd__h694346 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11902; 3'd3: - _theResult___fst_sfd__h694349 = + _theResult___fst_sfd__h694346 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11904; - 3'd4: _theResult___fst_sfd__h694349 = sfdin__h693748[56:34]; - default: _theResult___fst_sfd__h694349 = 23'd0; + 3'd4: _theResult___fst_sfd__h694346 = sfdin__h693745[56:34]; + default: _theResult___fst_sfd__h694346 = 23'd0; endcase end - always@(guard__h694362 or - _theResult___snd__h702385 or - out_sfd__h702910 or _theResult___sfd__h702907) + always@(guard__h694359 or + _theResult___snd__h702382 or + out_sfd__h702907 or _theResult___sfd__h702904) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = - _theResult___snd__h702385[56:34]; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 = + _theResult___snd__h702382[56:34]; 2'b10: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = - out_sfd__h702910; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 = + out_sfd__h702907; 2'b11: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 = - _theResult___sfd__h702907; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 = + _theResult___sfd__h702904; endcase end - always@(guard__h694362 or - _theResult___snd__h702385 or _theResult___sfd__h702907) + always@(guard__h694359 or + _theResult___snd__h702382 or _theResult___sfd__h702904) begin - case (guard__h694362) + case (guard__h694359) 2'b0: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 = - _theResult___snd__h702385[56:34]; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135 = + _theResult___snd__h702382[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 = - _theResult___sfd__h702907; + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135 = + _theResult___sfd__h702904; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134 or - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135 or + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134 or + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923 or - _theResult___snd__h702385) + _theResult___snd__h702382) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h702985 = - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q134; + _theResult___fst_sfd__h702982 = + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q134; 3'd1: - _theResult___fst_sfd__h702985 = - CASE_guard94362_0b0_theResult___snd02385_BITS__ETC__q135; + _theResult___fst_sfd__h702982 = + CASE_guard94359_0b0_theResult___snd02382_BITS__ETC__q135; 3'd2: - _theResult___fst_sfd__h702985 = + _theResult___fst_sfd__h702982 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11921; 3'd3: - _theResult___fst_sfd__h702985 = + _theResult___fst_sfd__h702982 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11923; - 3'd4: _theResult___fst_sfd__h702985 = _theResult___snd__h702385[56:34]; - default: _theResult___fst_sfd__h702985 = 23'd0; + 3'd4: _theResult___fst_sfd__h702982 = _theResult___snd__h702382[56:34]; + default: _theResult___fst_sfd__h702982 = 23'd0; endcase end - always@(guard__h667889 or + always@(guard__h667886 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01, 2'b10: - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = - guard__h667889 != 2'b11 || + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 = + guard__h667886 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 or - guard__h667889) + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136 or + guard__h667886) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = - CASE_guard67889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136; + CASE_guard67886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q136; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = - (guard__h667889 == 2'b0) ? + (guard__h667886 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h667889 != 2'b01 && guard__h667889 != 2'b10 && - guard__h667889 != 2'b11 || + guard__h667886 != 2'b01 && guard__h667886 != 2'b10 && + guard__h667886 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11953 = @@ -40839,34 +40839,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h667889 or + always@(guard__h667886 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h667889) + case (guard__h667886) 2'b0, 2'b01, 2'b10: - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = - guard__h667889 == 2'b11 && + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + guard__h667886 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or - guard__h667889) + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or + guard__h667886) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = - CASE_guard67889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; + CASE_guard67886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = - (guard__h667889 == 2'b0) ? + (guard__h667886 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h667889 == 2'b01 || guard__h667889 == 2'b10 || - guard__h667889 == 2'b11) && + (guard__h667886 == 2'b01 || guard__h667886 == 2'b10 || + guard__h667886 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12009 = @@ -40877,34 +40877,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676596 or + always@(guard__h676593 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01, 2'b10: - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = - guard__h676596 == 2'b11 && + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = + guard__h676593 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or - guard__h676596) + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or + guard__h676593) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = - CASE_guard76596_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; + CASE_guard76593_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = - (guard__h676596 == 2'b0) ? + (guard__h676593 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h676596 == 2'b01 || guard__h676596 == 2'b10 || - guard__h676596 == 2'b11) && + (guard__h676593 == 2'b01 || guard__h676593 == 2'b10 || + guard__h676593 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12016 = @@ -40915,34 +40915,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676596 or + always@(guard__h676593 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676596) + case (guard__h676593) 2'b0, 2'b01, 2'b10: - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = - guard__h676596 != 2'b11 || + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + guard__h676593 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or - guard__h676596) + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or + guard__h676593) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = - CASE_guard76596_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; + CASE_guard76593_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = - (guard__h676596 == 2'b0) ? + (guard__h676593 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h676596 != 2'b01 && guard__h676596 != 2'b10 && - guard__h676596 != 2'b11 || + guard__h676593 != 2'b01 && guard__h676593 != 2'b10 && + guard__h676593 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11966 = @@ -40953,34 +40953,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685526 or + always@(guard__h685523 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01, 2'b10: - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = - guard__h685526 == 2'b11 && + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = + guard__h685523 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 or - guard__h685526) + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 or + guard__h685523) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = - CASE_guard85526_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140; + CASE_guard85523_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = - (guard__h685526 == 2'b0) ? + (guard__h685523 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h685526 == 2'b01 || guard__h685526 == 2'b10 || - guard__h685526 == 2'b11) && + (guard__h685523 == 2'b01 || guard__h685523 == 2'b10 || + guard__h685523 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12026 = @@ -40991,34 +40991,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694362 or + always@(guard__h694359 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01, 2'b10: - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = - guard__h694362 == 2'b11 && + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + guard__h694359 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or - guard__h694362) + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or + guard__h694359) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = - CASE_guard94362_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; + CASE_guard94359_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = - (guard__h694362 == 2'b0) ? + (guard__h694359 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h694362 == 2'b01 || guard__h694362 == 2'b10 || - guard__h694362 == 2'b11) && + (guard__h694359 == 2'b01 || guard__h694359 == 2'b10 || + guard__h694359 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12033 = @@ -41029,34 +41029,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685526 or + always@(guard__h685523 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685526) + case (guard__h685523) 2'b0, 2'b01, 2'b10: - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = - guard__h685526 != 2'b11 || + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + guard__h685523 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or - guard__h685526) + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or + guard__h685523) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = - CASE_guard85526_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; + CASE_guard85523_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = - (guard__h685526 == 2'b0) ? + (guard__h685523 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h685526 != 2'b01 && guard__h685526 != 2'b10 && - guard__h685526 != 2'b11 || + guard__h685523 != 2'b01 && guard__h685523 != 2'b10 && + guard__h685523 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11983 = @@ -41067,34 +41067,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694362 or + always@(guard__h694359 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694362) + case (guard__h694359) 2'b0, 2'b01, 2'b10: - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = - guard__h694362 != 2'b11 || + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = + guard__h694359 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 or - guard__h694362) + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 or + guard__h694359) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = - CASE_guard94362_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143; + CASE_guard94359_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = - (guard__h694362 == 2'b0) ? + (guard__h694359 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h694362 != 2'b01 && guard__h694362 != 2'b10 && - guard__h694362 != 2'b11 || + guard__h694359 != 2'b01 && guard__h694359 != 2'b10 && + guard__h694359 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11996 = @@ -41151,28 +41151,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h726252 or - _theResult___fst_exp__h734213 or _theResult___exp__h734868) + always@(guard__h726249 or + _theResult___fst_exp__h734210 or _theResult___exp__h734865) begin - case (guard__h726252) + case (guard__h726249) 2'b0: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154 = - _theResult___fst_exp__h734213; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154 = + _theResult___fst_exp__h734210; 2'b01, 2'b10, 2'b11: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154 = - _theResult___exp__h734868; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154 = + _theResult___exp__h734865; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h734213 or + _theResult___fst_exp__h734210 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146 or - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154) + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = - _theResult___fst_exp__h734213; + _theResult___fst_exp__h734210; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13148; @@ -41181,44 +41181,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13146; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q154; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q154; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13152 = 11'd0; endcase end - always@(guard__h726252 or - _theResult___fst_exp__h734213 or - out_exp__h734871 or _theResult___exp__h734868) + always@(guard__h726249 or + _theResult___fst_exp__h734210 or + out_exp__h734868 or _theResult___exp__h734865) begin - case (guard__h726252) + case (guard__h726249) 2'b0, 2'b01: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = - _theResult___fst_exp__h734213; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 = + _theResult___fst_exp__h734210; 2'b10: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = - out_exp__h734871; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 = + out_exp__h734868; 2'b11: - CASE_guard26252_0b0_theResult___fst_exp34213_0_ETC__q155 = - _theResult___exp__h734868; + CASE_guard26249_0b0_theResult___fst_exp34210_0_ETC__q155 = + _theResult___exp__h734865; endcase end - always@(guard__h726252 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h726249 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h726252) + case (guard__h726249) 2'b0, 2'b01, 2'b10: - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard26252_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h726252 == 2'b11 && + CASE_guard26249_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h726249 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726252) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726249) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41228,12 +41228,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h726252 == 2'b0) ? + (guard__h726249 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h726252 == 2'b01 || guard__h726252 == 2'b10 || - guard__h726252 == 2'b11) && + (guard__h726249 == 2'b01 || guard__h726249 == 2'b10 || + guard__h726249 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41244,23 +41244,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h735564 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h735561 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h735564) + case (guard__h735561) 2'b0, 2'b01, 2'b10: - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard35564_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h735564 == 2'b11 && + CASE_guard35561_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h735561 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735564) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735561) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41270,12 +41270,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h735564 == 2'b0) ? + (guard__h735561 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h735564 == 2'b01 || guard__h735564 == 2'b10 || - guard__h735564 == 2'b11) && + (guard__h735561 == 2'b01 || guard__h735561 == 2'b10 || + guard__h735561 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41286,23 +41286,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h744633 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h744630 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h744633) + case (guard__h744630) 2'b0, 2'b01, 2'b10: - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard44633_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = - guard__h744633 == 2'b11 && + CASE_guard44630_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q160 = + guard__h744630 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744633) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744630) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41312,12 +41312,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h744633 == 2'b0) ? + (guard__h744630 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h744633 == 2'b01 || guard__h744633 == 2'b10 || - guard__h744633 == 2'b11) && + (guard__h744630 == 2'b01 || guard__h744630 == 2'b10 || + guard__h744630 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41328,28 +41328,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h804409 or - _theResult___fst_exp__h812370 or _theResult___exp__h813025) + always@(guard__h804406 or + _theResult___fst_exp__h812367 or _theResult___exp__h813022) begin - case (guard__h804409) + case (guard__h804406) 2'b0: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171 = - _theResult___fst_exp__h812370; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171 = + _theResult___fst_exp__h812367; 2'b01, 2'b10, 2'b11: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171 = - _theResult___exp__h813025; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171 = + _theResult___exp__h813022; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h812370 or + _theResult___fst_exp__h812367 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861 or - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171) + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = - _theResult___fst_exp__h812370; + _theResult___fst_exp__h812367; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13863; @@ -41358,42 +41358,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13861; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q171; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q171; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13867 = 11'd0; endcase end - always@(guard__h804409 or - _theResult___fst_exp__h812370 or - out_exp__h813028 or _theResult___exp__h813025) + always@(guard__h804406 or + _theResult___fst_exp__h812367 or + out_exp__h813025 or _theResult___exp__h813022) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = - _theResult___fst_exp__h812370; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 = + _theResult___fst_exp__h812367; 2'b10: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = - out_exp__h813028; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 = + out_exp__h813025; 2'b11: - CASE_guard04409_0b0_theResult___fst_exp12370_0_ETC__q172 = - _theResult___exp__h813025; + CASE_guard04406_0b0_theResult___fst_exp12367_0_ETC__q172 = + _theResult___exp__h813022; endcase end - always@(guard__h813721 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813718 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01, 2'b10: - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13721_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = - guard__h813721 == 2'b11 && + CASE_guard13718_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q173 = + guard__h813718 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813721) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813718) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41402,12 +41402,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q174 = - (guard__h813721 == 2'b0) ? + (guard__h813718 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h813721 == 2'b01 || guard__h813721 == 2'b10 || - guard__h813721 == 2'b11) && + (guard__h813718 == 2'b01 || guard__h813718 == 2'b10 || + guard__h813718 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41418,21 +41418,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h804409 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804406 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01, 2'b10: - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04409_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = - guard__h804409 == 2'b11 && + CASE_guard04406_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q175 = + guard__h804406 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804409) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804406) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41441,12 +41441,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q176 = - (guard__h804409 == 2'b0) ? + (guard__h804406 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h804409 == 2'b01 || guard__h804409 == 2'b10 || - guard__h804409 == 2'b11) && + (guard__h804406 == 2'b01 || guard__h804406 == 2'b10 || + guard__h804406 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41457,21 +41457,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822790 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822787 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01, 2'b10: - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22790_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = - guard__h822790 == 2'b11 && + CASE_guard22787_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q177 = + guard__h822787 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822790) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822787) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41480,12 +41480,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q178 = - (guard__h822790 == 2'b0) ? + (guard__h822787 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h822790 == 2'b01 || guard__h822790 == 2'b10 || - guard__h822790 == 2'b11) && + (guard__h822787 == 2'b01 || guard__h822787 == 2'b10 || + guard__h822787 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41496,21 +41496,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h813721 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813718 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01, 2'b10: - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13721_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = - guard__h813721 != 2'b11 || + CASE_guard13718_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q179 = + guard__h813718 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813721) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813718) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41519,12 +41519,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q180 = - (guard__h813721 == 2'b0) ? + (guard__h813718 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h813721 != 2'b01 && guard__h813721 != 2'b10 && - guard__h813721 != 2'b11 || + guard__h813718 != 2'b01 && guard__h813718 != 2'b10 && + guard__h813718 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41535,21 +41535,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h804409 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804406 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01, 2'b10: - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04409_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = - guard__h804409 != 2'b11 || + CASE_guard04406_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q181 = + guard__h804406 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804409) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804406) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41558,12 +41558,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q182 = - (guard__h804409 == 2'b0) ? + (guard__h804406 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h804409 != 2'b01 && guard__h804409 != 2'b10 && - guard__h804409 != 2'b11 || + guard__h804406 != 2'b01 && guard__h804406 != 2'b10 && + guard__h804406 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41574,21 +41574,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822790 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822787 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01, 2'b10: - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22790_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = - guard__h822790 != 2'b11 || + CASE_guard22787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q183 = + guard__h822787 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822790) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822787) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41597,12 +41597,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q184 = - (guard__h822790 == 2'b0) ? + (guard__h822787 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h822790 != 2'b01 && guard__h822790 != 2'b10 && - guard__h822790 != 2'b11 || + guard__h822787 != 2'b01 && guard__h822787 != 2'b10 && + guard__h822787 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -41613,28 +41613,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h765105 or - _theResult___fst_exp__h773066 or _theResult___exp__h773721) + always@(guard__h765102 or + _theResult___fst_exp__h773063 or _theResult___exp__h773718) begin - case (guard__h765105) + case (guard__h765102) 2'b0: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194 = - _theResult___fst_exp__h773066; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194 = + _theResult___fst_exp__h773063; 2'b01, 2'b10, 2'b11: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194 = - _theResult___exp__h773721; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194 = + _theResult___exp__h773718; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h773066 or + _theResult___fst_exp__h773063 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631 or - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194) + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = - _theResult___fst_exp__h773066; + _theResult___fst_exp__h773063; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14633; @@ -41643,49 +41643,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14631; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q194; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q194; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14637 = 11'd0; endcase end - always@(guard__h765105 or - _theResult___fst_exp__h773066 or - out_exp__h773724 or _theResult___exp__h773721) + always@(guard__h765102 or + _theResult___fst_exp__h773063 or + out_exp__h773721 or _theResult___exp__h773718) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = - _theResult___fst_exp__h773066; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 = + _theResult___fst_exp__h773063; 2'b10: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = - out_exp__h773724; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 = + out_exp__h773721; 2'b11: - CASE_guard65105_0b0_theResult___fst_exp73066_0_ETC__q195 = - _theResult___exp__h773721; + CASE_guard65102_0b0_theResult___fst_exp73063_0_ETC__q195 = + _theResult___exp__h773718; endcase end - always@(guard__h774417 or - _theResult___fst_exp__h782643 or _theResult___exp__h783372) + always@(guard__h774414 or + _theResult___fst_exp__h782640 or _theResult___exp__h783369) begin - case (guard__h774417) + case (guard__h774414) 2'b0: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196 = - _theResult___fst_exp__h782643; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196 = + _theResult___fst_exp__h782640; 2'b01, 2'b10, 2'b11: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196 = - _theResult___exp__h783372; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196 = + _theResult___exp__h783369; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h782643 or + _theResult___fst_exp__h782640 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669 or - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196) + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = - _theResult___fst_exp__h782643; + _theResult___fst_exp__h782640; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14671; @@ -41694,49 +41694,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14669; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q196; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q196; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14675 = 11'd0; endcase end - always@(guard__h774417 or - _theResult___fst_exp__h782643 or - out_exp__h783375 or _theResult___exp__h783372) + always@(guard__h774414 or + _theResult___fst_exp__h782640 or + out_exp__h783372 or _theResult___exp__h783369) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = - _theResult___fst_exp__h782643; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 = + _theResult___fst_exp__h782640; 2'b10: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = - out_exp__h783375; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 = + out_exp__h783372; 2'b11: - CASE_guard74417_0b0_theResult___fst_exp82643_0_ETC__q197 = - _theResult___exp__h783372; + CASE_guard74414_0b0_theResult___fst_exp82640_0_ETC__q197 = + _theResult___exp__h783369; endcase end - always@(guard__h813721 or - _theResult___fst_exp__h821947 or _theResult___exp__h822676) + always@(guard__h813718 or + _theResult___fst_exp__h821944 or _theResult___exp__h822673) begin - case (guard__h813721) + case (guard__h813718) 2'b0: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198 = - _theResult___fst_exp__h821947; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198 = + _theResult___fst_exp__h821944; 2'b01, 2'b10, 2'b11: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198 = - _theResult___exp__h822676; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198 = + _theResult___exp__h822673; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h821947 or + _theResult___fst_exp__h821944 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899 or - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198) + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = - _theResult___fst_exp__h821947; + _theResult___fst_exp__h821944; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13901; @@ -41745,49 +41745,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13899; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q198; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q198; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13905 = 11'd0; endcase end - always@(guard__h813721 or - _theResult___fst_exp__h821947 or - out_exp__h822679 or _theResult___exp__h822676) + always@(guard__h813718 or + _theResult___fst_exp__h821944 or + out_exp__h822676 or _theResult___exp__h822673) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 = - _theResult___fst_exp__h821947; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 = + _theResult___fst_exp__h821944; 2'b10: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 = - out_exp__h822679; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 = + out_exp__h822676; 2'b11: - CASE_guard13721_0b0_theResult___fst_exp21947_0_ETC__q199 = - _theResult___exp__h822676; + CASE_guard13718_0b0_theResult___fst_exp21944_0_ETC__q199 = + _theResult___exp__h822673; endcase end - always@(guard__h783486 or - _theResult___fst_exp__h791476 or _theResult___exp__h792156) + always@(guard__h783483 or + _theResult___fst_exp__h791473 or _theResult___exp__h792153) begin - case (guard__h783486) + case (guard__h783483) 2'b0: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200 = - _theResult___fst_exp__h791476; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200 = + _theResult___fst_exp__h791473; 2'b01, 2'b10, 2'b11: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200 = - _theResult___exp__h792156; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200 = + _theResult___exp__h792153; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h791476 or + _theResult___fst_exp__h791473 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700 or - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200) + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = - _theResult___fst_exp__h791476; + _theResult___fst_exp__h791473; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14702; @@ -41796,49 +41796,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14700; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q200; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q200; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14706 = 11'd0; endcase end - always@(guard__h783486 or - _theResult___fst_exp__h791476 or - out_exp__h792159 or _theResult___exp__h792156) + always@(guard__h783483 or + _theResult___fst_exp__h791473 or + out_exp__h792156 or _theResult___exp__h792153) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 = - _theResult___fst_exp__h791476; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 = + _theResult___fst_exp__h791473; 2'b10: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 = - out_exp__h792159; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 = + out_exp__h792156; 2'b11: - CASE_guard83486_0b0_theResult___fst_exp91476_0_ETC__q201 = - _theResult___exp__h792156; + CASE_guard83483_0b0_theResult___fst_exp91473_0_ETC__q201 = + _theResult___exp__h792153; endcase end - always@(guard__h822790 or - _theResult___fst_exp__h830780 or _theResult___exp__h831460) + always@(guard__h822787 or + _theResult___fst_exp__h830777 or _theResult___exp__h831457) begin - case (guard__h822790) + case (guard__h822787) 2'b0: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202 = - _theResult___fst_exp__h830780; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202 = + _theResult___fst_exp__h830777; 2'b01, 2'b10, 2'b11: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202 = - _theResult___exp__h831460; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202 = + _theResult___exp__h831457; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h830780 or + _theResult___fst_exp__h830777 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930 or - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202) + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = - _theResult___fst_exp__h830780; + _theResult___fst_exp__h830777; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13932; @@ -41847,44 +41847,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13930; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q202; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q202; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13936 = 11'd0; endcase end - always@(guard__h822790 or - _theResult___fst_exp__h830780 or - out_exp__h831463 or _theResult___exp__h831460) + always@(guard__h822787 or + _theResult___fst_exp__h830777 or + out_exp__h831460 or _theResult___exp__h831457) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = - _theResult___fst_exp__h830780; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 = + _theResult___fst_exp__h830777; 2'b10: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = - out_exp__h831463; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 = + out_exp__h831460; 2'b11: - CASE_guard22790_0b0_theResult___fst_exp30780_0_ETC__q203 = - _theResult___exp__h831460; + CASE_guard22787_0b0_theResult___fst_exp30777_0_ETC__q203 = + _theResult___exp__h831457; endcase end - always@(guard__h765105 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765102 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01, 2'b10: - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = - guard__h765105 == 2'b11 && + CASE_guard65102_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q204 = + guard__h765102 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765105) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765102) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41894,12 +41894,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q205 = - (guard__h765105 == 2'b0) ? + (guard__h765102 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h765105 == 2'b01 || guard__h765105 == 2'b10 || - guard__h765105 == 2'b11) && + (guard__h765102 == 2'b01 || guard__h765102 == 2'b10 || + guard__h765102 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -41910,23 +41910,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774417 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774414 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01, 2'b10: - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74417_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = - guard__h774417 == 2'b11 && + CASE_guard74414_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q206 = + guard__h774414 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774417) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774414) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41936,12 +41936,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q207 = - (guard__h774417 == 2'b0) ? + (guard__h774414 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h774417 == 2'b01 || guard__h774417 == 2'b10 || - guard__h774417 == 2'b11) && + (guard__h774414 == 2'b01 || guard__h774414 == 2'b10 || + guard__h774414 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -41952,23 +41952,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783486 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783483 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01, 2'b10: - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83486_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = - guard__h783486 == 2'b11 && + CASE_guard83483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q208 = + guard__h783483 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783486) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783483) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41978,12 +41978,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q209 = - (guard__h783486 == 2'b0) ? + (guard__h783483 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h783486 == 2'b01 || guard__h783486 == 2'b10 || - guard__h783486 == 2'b11) && + (guard__h783483 == 2'b01 || guard__h783483 == 2'b10 || + guard__h783483 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -41994,23 +41994,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774417 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774414 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01, 2'b10: - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74417_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = - guard__h774417 != 2'b11 || + CASE_guard74414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q210 = + guard__h774414 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774417) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774414) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42020,12 +42020,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q211 = - (guard__h774417 == 2'b0) ? + (guard__h774414 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h774417 != 2'b01 && guard__h774417 != 2'b10 && - guard__h774417 != 2'b11 || + guard__h774414 != 2'b01 && guard__h774414 != 2'b10 && + guard__h774414 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42036,23 +42036,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783486 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783483 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01, 2'b10: - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83486_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = - guard__h783486 != 2'b11 || + CASE_guard83483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q212 = + guard__h783483 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783486) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783483) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42062,12 +42062,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q213 = - (guard__h783486 == 2'b0) ? + (guard__h783483 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h783486 != 2'b01 && guard__h783486 != 2'b10 && - guard__h783486 != 2'b11 || + guard__h783483 != 2'b01 && guard__h783483 != 2'b10 && + guard__h783483 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42078,23 +42078,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765105 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765102 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01, 2'b10: - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = - guard__h765105 != 2'b11 || + CASE_guard65102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q214 = + guard__h765102 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765105) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765102) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42104,12 +42104,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q215 = - (guard__h765105 == 2'b0) ? + (guard__h765102 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h765105 != 2'b01 && guard__h765105 != 2'b10 && - guard__h765105 != 2'b11 || + guard__h765102 != 2'b01 && guard__h765102 != 2'b10 && + guard__h765102 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42120,28 +42120,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765105 or - _theResult___snd__h773017 or _theResult___sfd__h773722) + always@(guard__h765102 or + _theResult___snd__h773014 or _theResult___sfd__h773719) begin - case (guard__h765105) + case (guard__h765102) 2'b0: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216 = - _theResult___snd__h773017[56:5]; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216 = + _theResult___snd__h773014[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216 = - _theResult___sfd__h773722; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216 = + _theResult___sfd__h773719; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h773017 or + _theResult___snd__h773014 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726 or - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216) + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = - _theResult___snd__h773017[56:5]; + _theResult___snd__h773014[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14728; @@ -42150,48 +42150,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14726; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q216; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q216; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14732 = 52'd0; endcase end - always@(guard__h765105 or - _theResult___snd__h773017 or - out_sfd__h773725 or _theResult___sfd__h773722) + always@(guard__h765102 or + _theResult___snd__h773014 or + out_sfd__h773722 or _theResult___sfd__h773719) begin - case (guard__h765105) + case (guard__h765102) 2'b0, 2'b01: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = - _theResult___snd__h773017[56:5]; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 = + _theResult___snd__h773014[56:5]; 2'b10: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = - out_sfd__h773725; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 = + out_sfd__h773722; 2'b11: - CASE_guard65105_0b0_theResult___snd73017_BITS__ETC__q217 = - _theResult___sfd__h773722; + CASE_guard65102_0b0_theResult___snd73014_BITS__ETC__q217 = + _theResult___sfd__h773719; endcase end - always@(guard__h774417 or sfdin__h782637 or _theResult___sfd__h783373) + always@(guard__h774414 or sfdin__h782634 or _theResult___sfd__h783370) begin - case (guard__h774417) + case (guard__h774414) 2'b0: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h782637[56:5]; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h782634[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h783373; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h783370; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h782637 or + sfdin__h782634 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752 or - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218) + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = - sfdin__h782637[56:5]; + sfdin__h782634[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14754; @@ -42200,48 +42200,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14752; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q218; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q218; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14758 = 52'd0; endcase end - always@(guard__h774417 or - sfdin__h782637 or out_sfd__h783376 or _theResult___sfd__h783373) + always@(guard__h774414 or + sfdin__h782634 or out_sfd__h783373 or _theResult___sfd__h783370) begin - case (guard__h774417) + case (guard__h774414) 2'b0, 2'b01: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = - sfdin__h782637[56:5]; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h782634[56:5]; 2'b10: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = - out_sfd__h783376; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 = + out_sfd__h783373; 2'b11: - CASE_guard74417_0b0_sfdin82637_BITS_56_TO_5_0b_ETC__q219 = - _theResult___sfd__h783373; + CASE_guard74414_0b0_sfdin82634_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h783370; endcase end - always@(guard__h783486 or - _theResult___snd__h791422 or _theResult___sfd__h792157) + always@(guard__h783483 or + _theResult___snd__h791419 or _theResult___sfd__h792154) begin - case (guard__h783486) + case (guard__h783483) 2'b0: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220 = - _theResult___snd__h791422[56:5]; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220 = + _theResult___snd__h791419[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220 = - _theResult___sfd__h792157; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220 = + _theResult___sfd__h792154; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h791422 or + _theResult___snd__h791419 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771 or - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220) + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = - _theResult___snd__h791422[56:5]; + _theResult___snd__h791419[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14773; @@ -42250,49 +42250,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14771; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q220; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q220; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14777 = 52'd0; endcase end - always@(guard__h783486 or - _theResult___snd__h791422 or - out_sfd__h792160 or _theResult___sfd__h792157) + always@(guard__h783483 or + _theResult___snd__h791419 or + out_sfd__h792157 or _theResult___sfd__h792154) begin - case (guard__h783486) + case (guard__h783483) 2'b0, 2'b01: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = - _theResult___snd__h791422[56:5]; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 = + _theResult___snd__h791419[56:5]; 2'b10: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = - out_sfd__h792160; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 = + out_sfd__h792157; 2'b11: - CASE_guard83486_0b0_theResult___snd91422_BITS__ETC__q221 = - _theResult___sfd__h792157; + CASE_guard83483_0b0_theResult___snd91419_BITS__ETC__q221 = + _theResult___sfd__h792154; endcase end - always@(guard__h735564 or - _theResult___fst_exp__h743790 or _theResult___exp__h744519) + always@(guard__h735561 or + _theResult___fst_exp__h743787 or _theResult___exp__h744516) begin - case (guard__h735564) + case (guard__h735561) 2'b0: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222 = - _theResult___fst_exp__h743790; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222 = + _theResult___fst_exp__h743787; 2'b01, 2'b10, 2'b11: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222 = - _theResult___exp__h744519; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222 = + _theResult___exp__h744516; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h743790 or + _theResult___fst_exp__h743787 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189 or - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222) + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = - _theResult___fst_exp__h743790; + _theResult___fst_exp__h743787; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13191; @@ -42301,49 +42301,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13189; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q222; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q222; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13195 = 11'd0; endcase end - always@(guard__h735564 or - _theResult___fst_exp__h743790 or - out_exp__h744522 or _theResult___exp__h744519) + always@(guard__h735561 or + _theResult___fst_exp__h743787 or + out_exp__h744519 or _theResult___exp__h744516) begin - case (guard__h735564) + case (guard__h735561) 2'b0, 2'b01: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = - _theResult___fst_exp__h743790; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 = + _theResult___fst_exp__h743787; 2'b10: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = - out_exp__h744522; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 = + out_exp__h744519; 2'b11: - CASE_guard35564_0b0_theResult___fst_exp43790_0_ETC__q223 = - _theResult___exp__h744519; + CASE_guard35561_0b0_theResult___fst_exp43787_0_ETC__q223 = + _theResult___exp__h744516; endcase end - always@(guard__h744633 or - _theResult___fst_exp__h752623 or _theResult___exp__h753303) + always@(guard__h744630 or + _theResult___fst_exp__h752620 or _theResult___exp__h753300) begin - case (guard__h744633) + case (guard__h744630) 2'b0: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224 = - _theResult___fst_exp__h752623; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224 = + _theResult___fst_exp__h752620; 2'b01, 2'b10, 2'b11: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224 = - _theResult___exp__h753303; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224 = + _theResult___exp__h753300; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h752623 or + _theResult___fst_exp__h752620 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220 or - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224) + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = - _theResult___fst_exp__h752623; + _theResult___fst_exp__h752620; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13222; @@ -42352,49 +42352,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13220; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q224; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q224; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13226 = 11'd0; endcase end - always@(guard__h744633 or - _theResult___fst_exp__h752623 or - out_exp__h753306 or _theResult___exp__h753303) + always@(guard__h744630 or + _theResult___fst_exp__h752620 or + out_exp__h753303 or _theResult___exp__h753300) begin - case (guard__h744633) + case (guard__h744630) 2'b0, 2'b01: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = - _theResult___fst_exp__h752623; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 = + _theResult___fst_exp__h752620; 2'b10: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = - out_exp__h753306; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 = + out_exp__h753303; 2'b11: - CASE_guard44633_0b0_theResult___fst_exp52623_0_ETC__q225 = - _theResult___exp__h753303; + CASE_guard44630_0b0_theResult___fst_exp52620_0_ETC__q225 = + _theResult___exp__h753300; endcase end - always@(guard__h726252 or - _theResult___snd__h734164 or _theResult___sfd__h734869) + always@(guard__h726249 or + _theResult___snd__h734161 or _theResult___sfd__h734866) begin - case (guard__h726252) + case (guard__h726249) 2'b0: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226 = - _theResult___snd__h734164[56:5]; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226 = + _theResult___snd__h734161[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226 = - _theResult___sfd__h734869; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226 = + _theResult___sfd__h734866; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h734164 or + _theResult___snd__h734161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246 or - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226) + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = - _theResult___snd__h734164[56:5]; + _theResult___snd__h734161[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13248; @@ -42403,48 +42403,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13246; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q226; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q226; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13252 = 52'd0; endcase end - always@(guard__h726252 or - _theResult___snd__h734164 or - out_sfd__h734872 or _theResult___sfd__h734869) + always@(guard__h726249 or + _theResult___snd__h734161 or + out_sfd__h734869 or _theResult___sfd__h734866) begin - case (guard__h726252) + case (guard__h726249) 2'b0, 2'b01: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = - _theResult___snd__h734164[56:5]; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 = + _theResult___snd__h734161[56:5]; 2'b10: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = - out_sfd__h734872; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 = + out_sfd__h734869; 2'b11: - CASE_guard26252_0b0_theResult___snd34164_BITS__ETC__q227 = - _theResult___sfd__h734869; + CASE_guard26249_0b0_theResult___snd34161_BITS__ETC__q227 = + _theResult___sfd__h734866; endcase end - always@(guard__h735564 or sfdin__h743784 or _theResult___sfd__h744520) + always@(guard__h735561 or sfdin__h743781 or _theResult___sfd__h744517) begin - case (guard__h735564) + case (guard__h735561) 2'b0: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228 = - sfdin__h743784[56:5]; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228 = + sfdin__h743781[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228 = - _theResult___sfd__h744520; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228 = + _theResult___sfd__h744517; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h743784 or + sfdin__h743781 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273 or - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228) + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = - sfdin__h743784[56:5]; + sfdin__h743781[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13275; @@ -42453,48 +42453,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13273; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q228; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q228; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13279 = 52'd0; endcase end - always@(guard__h735564 or - sfdin__h743784 or out_sfd__h744523 or _theResult___sfd__h744520) + always@(guard__h735561 or + sfdin__h743781 or out_sfd__h744520 or _theResult___sfd__h744517) begin - case (guard__h735564) + case (guard__h735561) 2'b0, 2'b01: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 = - sfdin__h743784[56:5]; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 = + sfdin__h743781[56:5]; 2'b10: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 = - out_sfd__h744523; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 = + out_sfd__h744520; 2'b11: - CASE_guard35564_0b0_sfdin43784_BITS_56_TO_5_0b_ETC__q229 = - _theResult___sfd__h744520; + CASE_guard35561_0b0_sfdin43781_BITS_56_TO_5_0b_ETC__q229 = + _theResult___sfd__h744517; endcase end - always@(guard__h744633 or - _theResult___snd__h752569 or _theResult___sfd__h753304) + always@(guard__h744630 or + _theResult___snd__h752566 or _theResult___sfd__h753301) begin - case (guard__h744633) + case (guard__h744630) 2'b0: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230 = - _theResult___snd__h752569[56:5]; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230 = + _theResult___snd__h752566[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230 = - _theResult___sfd__h753304; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230 = + _theResult___sfd__h753301; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h752569 or + _theResult___snd__h752566 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292 or - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230) + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = - _theResult___snd__h752569[56:5]; + _theResult___snd__h752566[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13294; @@ -42503,49 +42503,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13292; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q230; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q230; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13298 = 52'd0; endcase end - always@(guard__h744633 or - _theResult___snd__h752569 or - out_sfd__h753307 or _theResult___sfd__h753304) + always@(guard__h744630 or + _theResult___snd__h752566 or + out_sfd__h753304 or _theResult___sfd__h753301) begin - case (guard__h744633) + case (guard__h744630) 2'b0, 2'b01: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 = - _theResult___snd__h752569[56:5]; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 = + _theResult___snd__h752566[56:5]; 2'b10: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 = - out_sfd__h753307; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 = + out_sfd__h753304; 2'b11: - CASE_guard44633_0b0_theResult___snd52569_BITS__ETC__q231 = - _theResult___sfd__h753304; + CASE_guard44630_0b0_theResult___snd52566_BITS__ETC__q231 = + _theResult___sfd__h753301; endcase end - always@(guard__h804409 or - _theResult___snd__h812321 or _theResult___sfd__h813026) + always@(guard__h804406 or + _theResult___snd__h812318 or _theResult___sfd__h813023) begin - case (guard__h804409) + case (guard__h804406) 2'b0: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232 = - _theResult___snd__h812321[56:5]; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232 = + _theResult___snd__h812318[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232 = - _theResult___sfd__h813026; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232 = + _theResult___sfd__h813023; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h812321 or + _theResult___snd__h812318 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956 or - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232) + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = - _theResult___snd__h812321[56:5]; + _theResult___snd__h812318[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13958; @@ -42554,48 +42554,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13956; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q232; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q232; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13962 = 52'd0; endcase end - always@(guard__h804409 or - _theResult___snd__h812321 or - out_sfd__h813029 or _theResult___sfd__h813026) + always@(guard__h804406 or + _theResult___snd__h812318 or + out_sfd__h813026 or _theResult___sfd__h813023) begin - case (guard__h804409) + case (guard__h804406) 2'b0, 2'b01: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = - _theResult___snd__h812321[56:5]; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 = + _theResult___snd__h812318[56:5]; 2'b10: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = - out_sfd__h813029; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 = + out_sfd__h813026; 2'b11: - CASE_guard04409_0b0_theResult___snd12321_BITS__ETC__q233 = - _theResult___sfd__h813026; + CASE_guard04406_0b0_theResult___snd12318_BITS__ETC__q233 = + _theResult___sfd__h813023; endcase end - always@(guard__h813721 or sfdin__h821941 or _theResult___sfd__h822677) + always@(guard__h813718 or sfdin__h821938 or _theResult___sfd__h822674) begin - case (guard__h813721) + case (guard__h813718) 2'b0: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234 = - sfdin__h821941[56:5]; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234 = + sfdin__h821938[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234 = - _theResult___sfd__h822677; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234 = + _theResult___sfd__h822674; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h821941 or + sfdin__h821938 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982 or - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234) + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = - sfdin__h821941[56:5]; + sfdin__h821938[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13984; @@ -42604,24 +42604,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13982; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q234; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q234; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d13988 = 52'd0; endcase end - always@(guard__h813721 or - sfdin__h821941 or out_sfd__h822680 or _theResult___sfd__h822677) + always@(guard__h813718 or + sfdin__h821938 or out_sfd__h822677 or _theResult___sfd__h822674) begin - case (guard__h813721) + case (guard__h813718) 2'b0, 2'b01: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = - sfdin__h821941[56:5]; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 = + sfdin__h821938[56:5]; 2'b10: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = - out_sfd__h822680; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 = + out_sfd__h822677; 2'b11: - CASE_guard13721_0b0_sfdin21941_BITS_56_TO_5_0b_ETC__q235 = - _theResult___sfd__h822677; + CASE_guard13718_0b0_sfdin21938_BITS_56_TO_5_0b_ETC__q235 = + _theResult___sfd__h822674; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -42656,28 +42656,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__2504_B_ETC___d14985; endcase end - always@(guard__h822790 or - _theResult___snd__h830726 or _theResult___sfd__h831461) + always@(guard__h822787 or + _theResult___snd__h830723 or _theResult___sfd__h831458) begin - case (guard__h822790) + case (guard__h822787) 2'b0: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236 = - _theResult___snd__h830726[56:5]; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236 = + _theResult___snd__h830723[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236 = - _theResult___sfd__h831461; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236 = + _theResult___sfd__h831458; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h830726 or + _theResult___snd__h830723 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001 or - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236) + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = - _theResult___snd__h830726[56:5]; + _theResult___snd__h830723[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14003; @@ -42686,25 +42686,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14001; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q236; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q236; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14007 = 52'd0; endcase end - always@(guard__h822790 or - _theResult___snd__h830726 or - out_sfd__h831464 or _theResult___sfd__h831461) + always@(guard__h822787 or + _theResult___snd__h830723 or + out_sfd__h831461 or _theResult___sfd__h831458) begin - case (guard__h822790) + case (guard__h822787) 2'b0, 2'b01: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = - _theResult___snd__h830726[56:5]; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 = + _theResult___snd__h830723[56:5]; 2'b10: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = - out_sfd__h831464; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 = + out_sfd__h831461; 2'b11: - CASE_guard22790_0b0_theResult___snd30726_BITS__ETC__q237 = - _theResult___sfd__h831461; + CASE_guard22787_0b0_theResult___snd30723_BITS__ETC__q237 = + _theResult___sfd__h831458; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43256,10 +43256,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h942684 or + always@(k__h942679 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h942684) + case (k__h942679) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__097_ETC___d20984 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -43279,10 +43279,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h942684 or + always@(k__h942679 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h942684) + case (k__h942679) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__0973_co_ETC___d21007 = coreFix_aluExe_0_rsAlu$canEnq; @@ -43499,7 +43499,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h966426 or + always@(idx__h966421 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21423 or coreFix_aluExe_0_rsAlu$canEnq or @@ -43509,7 +43509,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0049_BITS_267_TO_ETC___d21428 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h966426) + case (idx__h966421) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0047_AN_ETC___d21451 = fetchStage$pipelines_0_canDeq && @@ -43613,15 +43613,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1068_AND__ETC___d21413; endcase end - always@(k__h942684 or + always@(k__h942679 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h942684) + case (k__h942679) 1'd0: - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k42684_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = + CASE_k42679_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q267 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -43657,7 +43657,7 @@ module mkCore(CLK, regRenamingTable_RDY_rename_0_getRename__0810__ETC___d21625; endcase end - always@(idx__h966426 or + always@(idx__h966421 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -43667,7 +43667,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0049_BITS_26_ETC___d21682 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h966426) + case (idx__h966421) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__004_ETC___d21687 = (!fetchStage$pipelines_0_canDeq || @@ -44039,87 +44039,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_1[63:0]; - endcase - end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_1[63:0]; - endcase - end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_1[127:64]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_1[127:64]; - endcase - end - always@(commitStage_commitTrap or - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448) - begin - case (commitStage_commitTrap[36:32]) - 5'd0, 5'd3: - trap_val__h994359 = - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448; - 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h994359 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h994359 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h994359 = 64'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = - 3'd0; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -44346,6 +44265,87 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0]; endcase end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_1[63:0]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_1[63:0]; + endcase + end + always@(commitStage_commitTrap or + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, 5'd3: + trap_val__h994354 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22448; + 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: + trap_val__h994354 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h994354 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h994354 = 64'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__250_ETC___d14850 = + 3'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -45825,17 +45825,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h857278 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h857278 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h857278 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h857278 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h857275 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h857275 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h857275 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h857275 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h857278 = + thin_reserved__h857275 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17009; - 5'd28: thin_reserved__h857278 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h857278 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h857278 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h857278 = + 5'd28: thin_reserved__h857275 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h857275 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h857275 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h857275 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17015; endcase end @@ -45849,17 +45849,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h896912 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h896912 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h896912 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h896912 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h896908 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h896908 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h896908 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h896908 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h896912 = + thin_reserved__h896908 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17009; - 5'd28: thin_reserved__h896912 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h896912 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h896912 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h896912 = + 5'd28: thin_reserved__h896908 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h896908 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h896908 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h896908 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17015; endcase end @@ -45873,17 +45873,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h857526 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h857526 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h857526 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h857526 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h857523 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h857523 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h857523 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h857523 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h857526 = + thin_perms_soft__h857523 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16695; - 5'd28: thin_perms_soft__h857526 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h857526 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h857526 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h857526 = + 5'd28: thin_perms_soft__h857523 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h857523 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h857523 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h857523 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16701; endcase end @@ -45897,17 +45897,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h897088 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h897088 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h897088 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h897088 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h897084 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h897084 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h897084 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h897084 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h897088 = + thin_perms_soft__h897084 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16695; - 5'd28: thin_perms_soft__h897088 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h897088 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h897088 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h897088 = + 5'd28: thin_perms_soft__h897084 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h897084 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h897084 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h897084 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16701; endcase end @@ -45921,17 +45921,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h857274 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h857274 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h857274 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h857274 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h857271 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h857271 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h857271 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h857271 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h857274 = + thin_address__h857271 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16651; - 5'd28: thin_address__h857274 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h857274 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h857274 = csrf_mScratchC_reg[151:86]; - default: thin_address__h857274 = + 5'd28: thin_address__h857271 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h857271 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h857271 = csrf_mScratchC_reg[151:86]; + default: thin_address__h857271 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16657; endcase end @@ -45945,17 +45945,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h896908 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h896908 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h896908 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h896908 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h896904 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h896904 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h896904 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h896904 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h896908 = + thin_address__h896904 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16651; - 5'd28: thin_address__h896908 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h896908 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h896908 = csrf_mScratchC_reg[151:86]; - default: thin_address__h896908 = + 5'd28: thin_address__h896904 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h896904 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h896904 = csrf_mScratchC_reg[151:86]; + default: thin_address__h896904 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16657; endcase end @@ -45969,17 +45969,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h859273 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h859273 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h859273 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h859273 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h859270 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h859270 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h859270 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h859270 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h859273 = + thin_bounds_baseBits__h859270 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17102; - 5'd28: thin_bounds_baseBits__h859273 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h859273 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h859273 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h859273 = + 5'd28: thin_bounds_baseBits__h859270 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h859270 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h859270 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h859270 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17108; endcase end @@ -45993,17 +45993,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h898315 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h898315 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h898315 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h898315 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h898311 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h898311 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h898311 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h898311 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h898315 = + thin_bounds_baseBits__h898311 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17102; - 5'd28: thin_bounds_baseBits__h898315 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h898315 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h898315 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h898315 = + 5'd28: thin_bounds_baseBits__h898311 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h898311 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h898311 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h898311 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17108; endcase end @@ -46017,17 +46017,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h859272 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h859272 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h859272 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h859272 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h859269 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h859269 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h859269 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h859269 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h859272 = + thin_bounds_topBits__h859269 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17126; - 5'd28: thin_bounds_topBits__h859272 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h859272 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h859272 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h859272 = + 5'd28: thin_bounds_topBits__h859269 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h859269 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h859269 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h859269 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132; endcase end @@ -46041,17 +46041,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h898314 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h898314 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h898314 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h898314 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h898310 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h898310 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h898310 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h898310 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h898314 = + thin_bounds_topBits__h898310 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17126; - 5'd28: thin_bounds_topBits__h898314 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h898314 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h898314 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h898314 = + 5'd28: thin_bounds_topBits__h898310 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h898310 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h898310 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h898310 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132; endcase end @@ -46065,17 +46065,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h857275 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h857275 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h857275 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h857275 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h857272 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h857272 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h857272 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h857272 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h857275 = + thin_addrBits__h857272 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16673; - 5'd28: thin_addrBits__h857275 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h857275 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h857275 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h857275 = + 5'd28: thin_addrBits__h857272 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h857272 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h857272 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h857272 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16679; endcase end @@ -46089,17 +46089,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h896909 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h896909 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h896909 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h896909 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h896905 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h896905 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h896905 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h896905 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h896909 = + thin_addrBits__h896905 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16673; - 5'd28: thin_addrBits__h896909 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h896909 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h896909 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h896909 = + 5'd28: thin_addrBits__h896905 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h896905 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h896905 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h896905 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16679; endcase end @@ -46683,17 +46683,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h857279 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h857279 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h857279 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h857279 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h857276 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h857276 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h857276 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h857276 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h857279 = + thin_otype__h857276 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17031; - 5'd28: thin_otype__h857279 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h857279 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h857279 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h857279 = + 5'd28: thin_otype__h857276 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h857276 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h857276 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h857276 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17037; endcase end @@ -46707,17 +46707,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h896913 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h896913 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h896913 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h896913 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h896909 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h896909 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h896909 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h896909 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h896913 = + thin_otype__h896909 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17031; - 5'd28: thin_otype__h896913 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h896913 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h896913 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h896913 = + 5'd28: thin_otype__h896909 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h896909 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h896909 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h896909 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17037; endcase end @@ -46808,99 +46808,13 @@ module mkCore(CLK, { 2'd3, mmio_dataReqQ_data_0[148:145] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 = - 4'd15; - endcase - end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[7:3]) - 5'd0, - 5'd1, - 5'd2, - 5'd3, - 5'd4, - 5'd5, - 5'd6, - 5'd7, - 5'd8, - 5'd9, - 5'd10, - 5'd11, - 5'd16, - 5'd17, - 5'd18, - 5'd19, - 5'd20, - 5'd21, - 5'd22, - 5'd23, - 5'd24, - 5'd25, - 5'd26: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 = - coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 = - 5'd27; - endcase - end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[7:3]) - 5'd0, - 5'd1, - 5'd2, - 5'd3, - 5'd4, - 5'd5, - 5'd6, - 5'd7, - 5'd8, - 5'd9, - 5'd11, - 5'd12, - 5'd13, - 5'd15: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332 = - coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332 = - 5'd28; - endcase - end - always@(coreFix_memExe_lsq$firstLd or - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332) - begin - case (coreFix_memExe_lsq$firstLd[15:14]) - 2'd0: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 = - { 2'd0, - coreFix_memExe_lsq$firstLd[13:8], - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q331 }; - 2'd1: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 = - { coreFix_memExe_lsq$firstLd[15:14], - 6'h2A, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q332 }; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q333 = - { 9'd298, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q330 }; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 = 4'd15; endcase end @@ -46930,9 +46844,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 = 5'd27; endcase end @@ -46953,31 +46867,117 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstSt or - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336) + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332) begin case (coreFix_memExe_lsq$firstSt[12:11]) 2'd0: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = { 2'd0, coreFix_memExe_lsq$firstSt[10:5], - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q331 }; 2'd1: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = { coreFix_memExe_lsq$firstSt[12:11], 6'h2A, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 }; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q332 }; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q333 = { 9'd298, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q330 }; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[7:3]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd10, + 5'd11, + 5'd16, + 5'd17, + 5'd18, + 5'd19, + 5'd20, + 5'd21, + 5'd22, + 5'd23, + 5'd24, + 5'd25, + 5'd26: + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 = + coreFix_memExe_lsq$firstLd[7:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 = + 5'd27; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[7:3]) + 5'd0, + 5'd1, + 5'd2, + 5'd3, + 5'd4, + 5'd5, + 5'd6, + 5'd7, + 5'd8, + 5'd9, + 5'd11, + 5'd12, + 5'd13, + 5'd15: + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 = + coreFix_memExe_lsq$firstLd[7:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 = + 5'd28; + endcase + end + always@(coreFix_memExe_lsq$firstLd or + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336) + begin + case (coreFix_memExe_lsq$firstLd[15:14]) + 2'd0: + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { 2'd0, + coreFix_memExe_lsq$firstLd[13:8], + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q335 }; + 2'd1: + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { coreFix_memExe_lsq$firstLd[15:14], + 6'h2A, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q336 }; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q337 = + { 9'd298, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q334 }; endcase end always@(mmioToPlatform_pRq_enq_x) @@ -55802,17 +55802,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254401); + $write("'h%h", value__h254399); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254565); + $write("'h%h", value__h254563); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h254677[64:0]); + $write("'h%h", x__h254675[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -57606,14 +57606,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h213381 = $time; + v__h213380 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h213381, "[doRespLdMem]", " "); + $write("%t : ", v__h213380, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212809); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212808); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -57752,15 +57752,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h215650 = $time; + v__h215649 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h215650, "[doRespLdForward]", " "); + $write("%t : ", v__h215649, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h215095); + $write("'h%h", t__h215094); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -57985,17 +57985,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239635); + $write("'h%h", value__h239634); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239799); + $write("'h%h", value__h239798); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h239911[64:0]); + $write("'h%h", x__h239910[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58035,17 +58035,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240792); + $write("'h%h", value__h240791); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240956); + $write("'h%h", value__h240955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h241068[64:0]); + $write("'h%h", x__h241067[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -66194,14 +66194,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) begin - v__h271867 = $time; + v__h271864 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5573) - $write("%t : [Ld resp] ", v__h271867); + $write("%t : [Ld resp] ", v__h271864); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -67841,13 +67841,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) begin - v__h347385 = $time; + v__h347382 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) - $write("%t : [Ld resp] ", v__h347385); + $write("%t : [Ld resp] ", v__h347382); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5577) @@ -69721,7 +69721,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h423711 = $time; + v__h423708 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -69729,7 +69729,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h423711); + $write("%t : [Ld resp] ", v__h423708); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -72133,7 +72133,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h836568 == 2'd0) + v__h836565 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index 85d3746..fb00579 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:47:29 BST 2020 +// On Wed Jun 24 20:36:49 BST 2020 // // // Ports: @@ -81,18 +81,22 @@ // start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 +// cpu_imem_master_bvalid I 1 // cpu_imem_master_bid I 6 // cpu_imem_master_bresp I 2 // cpu_imem_master_arready I 1 +// cpu_imem_master_rvalid I 1 // cpu_imem_master_rid I 6 // cpu_imem_master_rdata I 64 // cpu_imem_master_rresp I 2 // cpu_imem_master_rlast I 1 // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 +// cpu_dmem_master_bvalid I 1 // cpu_dmem_master_bid I 6 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 +// cpu_dmem_master_rvalid I 1 // cpu_dmem_master_rid I 6 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg @@ -120,10 +124,6 @@ // ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 // EN_start I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_rvalid I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_rvalid I 1 // EN_dmi_read_addr I 1 // EN_dmi_write I 1 // EN_ndm_reset_client_response_put I 1 @@ -197,9 +197,9 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_imem_master_wready, + cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, - cpu_imem_master_bvalid, cpu_imem_master_bready, @@ -227,11 +227,11 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_imem_master_arready, + cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, - cpu_imem_master_rvalid, cpu_imem_master_rready, @@ -269,9 +269,9 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_dmem_master_wready, + cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, - cpu_dmem_master_bvalid, cpu_dmem_master_bready, @@ -299,11 +299,11 @@ module mkCoreW(RST_N_dm_power_on_reset, cpu_dmem_master_arready, + cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, - cpu_dmem_master_rvalid, cpu_dmem_master_rready, @@ -434,9 +434,9 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_imem_master_wready; // action method cpu_imem_master_b_bflit + input cpu_imem_master_bvalid; input [5 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; - input cpu_imem_master_bvalid; // value method cpu_imem_master_b_bready output cpu_imem_master_bready; @@ -480,11 +480,11 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_imem_master_arready; // action method cpu_imem_master_r_rflit + input cpu_imem_master_rvalid; input [5 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; - input cpu_imem_master_rvalid; // value method cpu_imem_master_r_rready output cpu_imem_master_rready; @@ -545,9 +545,9 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_dmem_master_wready; // action method cpu_dmem_master_b_bflit + input cpu_dmem_master_bvalid; input [5 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; - input cpu_dmem_master_bvalid; // value method cpu_dmem_master_b_bready output cpu_dmem_master_bready; @@ -591,11 +591,11 @@ module mkCoreW(RST_N_dm_power_on_reset, input cpu_dmem_master_arready; // action method cpu_dmem_master_r_rflit + input cpu_dmem_master_rvalid; input [5 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; - input cpu_dmem_master_rvalid; // value method cpu_dmem_master_r_rready output cpu_dmem_master_rready; @@ -746,6 +746,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // inlined wires wire [172 : 0] split_0_doPut$wget, split_1_doPut$wget, split_2_doPut$wget; + wire [171 : 0] merged_0_outflit$wget, merged_1_outflit$wget; wire [99 : 0] tagController_tmp_shimMaster_arff_rv$port0__write_1, tagController_tmp_shimMaster_arff_rv$port1__read, tagController_tmp_shimMaster_arff_rv$port2__read, @@ -762,29 +763,36 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_awff_rv$port1__read, tagController_tmp_shimSlave_awff_rv$port2__read, tagController_tmp_shimSlave_awff_rv$port3__read, - ug_uncached_mem_shim_master_u_ar_peekWire$wget, - ug_uncached_mem_shim_master_u_aw_peekWire$wget; - wire [97 : 0] ssNoSynth_0_ar_buffer_enqw$wget, - ssNoSynth_1_ar_buffer_enqw$wget, - ssNoSynth_1_aw_buffer_enqw$wget, - ssNoSynth_2_ar_buffer_enqw$wget, - ssNoSynth_2_aw_buffer_enqw$wget, + uncached_mem_master_arSynth_src_peekWire$wget, + uncached_mem_master_awSynth_src_peekWire$wget; + wire [97 : 0] slave_vector_0_arSynth_snk_putWire$wget, + slave_vector_0_awSynth_snk_putWire$wget, + ssNoSynth_0_arNoSynth_buffer_enqw$wget, + ssNoSynth_1_arNoSynth_buffer_enqw$wget, + ssNoSynth_1_arNoSynth_src_peekWire$wget, + ssNoSynth_1_awNoSynth_src_peekWire$wget, + ssNoSynth_2_arNoSynth_buffer_enqw$wget, + ssNoSynth_2_arNoSynth_src_peekWire$wget, + ssNoSynth_2_awNoSynth_src_peekWire$wget, tagController_tmp_ug_slave_u_ar_putWire$wget, - tagController_tmp_ug_slave_u_aw_putWire$wget; - wire [96 : 0] ifcs_0_1_noRoute_currentReq$port0__write_1, - ifcs_0_1_noRoute_currentReq$port1__read, - ifcs_0_noRoute_inner_currentReq$port0__write_1, + tagController_tmp_ug_slave_u_aw_putWire$wget, + tmp2_arNoSynth_buffer_enqw$wget, + tmp2_awNoSynth_buffer_enqw$wget; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$port1__read, ifcs_0_noRoute_inner_currentReq$port1__read, - ifcs_1_1_noRoute_currentReq$port0__write_1, ifcs_1_1_noRoute_currentReq$port1__read, - ifcs_1_noRoute_inner_currentReq$port0__write_1, - ifcs_1_noRoute_inner_currentReq$port1__read; + ifcs_1_noRoute_inner_currentReq$port1__read, + msNoSynth_1_arNoSynth_buffer_enqw$wget, + msNoSynth_1_awNoSynth_buffer_enqw$wget; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, tagController_tmp_shimSlave_wff_rv$port1__read, tagController_tmp_shimSlave_wff_rv$port2__read, tagController_tmp_shimSlave_wff_rv$port3__read; - wire [73 : 0] ssNoSynth_1_w_buffer_enqw$wget, - ssNoSynth_2_w_buffer_enqw$wget, + wire [73 : 0] msNoSynth_1_wNoSynth_buffer_enqw$wget, + proc_uncached_wSynth_src_peekWire$wget, + slave_vector_0_wSynth_snk_putWire$wget, + ssNoSynth_1_wNoSynth_src_peekWire$wget, + ssNoSynth_2_wNoSynth_src_peekWire$wget, tagController_tmp_shimMaster_rff_rv$port0__write_1, tagController_tmp_shimMaster_rff_rv$port1__read, tagController_tmp_shimMaster_rff_rv$port2__read, @@ -797,13 +805,17 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_rff_rv$port1__read, tagController_tmp_shimSlave_rff_rv$port2__read, tagController_tmp_shimSlave_rff_rv$port3__read, - tagController_tmp_ug_slave_u_w_putWire$wget; - wire [72 : 0] tagController_tmp_ug_master_u_r_putWire$wget, - tmp2_r_buffer_enqw$wget, - ug_uncached_mem_shim_master_u_r_putWire$wget; - wire [71 : 0] msNoSynth_0_r_buffer_enqw$wget, - msNoSynth_1_r_buffer_enqw$wget, - tmp0_r_buffer_enqw$wget; + tagController_tmp_ug_slave_u_w_putWire$wget, + tmp2_wNoSynth_buffer_enqw$wget; + wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_enqw$wget, + ssNoSynth_2_rNoSynth_buffer_enqw$wget, + tagController_tmp_ug_master_u_r_putWire$wget, + tmp2_rNoSynth_src_peekWire$wget, + uncached_mem_master_rSynth_snk_putWire$wget; + wire [71 : 0] msNoSynth_0_rNoSynth_buffer_enqw$wget, + msNoSynth_1_rNoSynth_buffer_enqw$wget, + msNoSynth_1_rNoSynth_src_peekWire$wget, + proc_uncached_rSynth_snk_putWire$wget; wire [8 : 0] ifcs_0_1_noRoute_flitCount$port0__write_1, ifcs_0_1_noRoute_flitCount$port1__write_1, ifcs_0_1_noRoute_flitCount$port2__read, @@ -819,12 +831,18 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimSlave_bff_rv$port2__read, tagController_tmp_shimSlave_bff_rv$port3__read, tagController_tmp_ug_master_u_b_putWire$wget, - ug_uncached_mem_shim_master_u_b_putWire$wget; - wire [6 : 0] tmp2_b_buffer_enqw$wget; - wire [5 : 0] msNoSynth_0_b_buffer_enqw$wget, - msNoSynth_1_b_buffer_enqw$wget, - tmp0_b_buffer_enqw$wget; - wire flitToSink_0$whas, + uncached_mem_master_bSynth_snk_putWire$wget; + wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_enqw$wget, + ssNoSynth_2_bNoSynth_buffer_enqw$wget, + tmp2_bNoSynth_src_peekWire$wget; + wire [5 : 0] msNoSynth_0_bNoSynth_buffer_enqw$wget, + msNoSynth_1_bNoSynth_buffer_enqw$wget, + msNoSynth_1_bNoSynth_src_peekWire$wget, + proc_uncached_bSynth_snk_putWire$wget; + wire cached_mem_master_arSynth_src_dropWire$whas, + cached_mem_master_awSynth_src_dropWire$whas, + cached_mem_master_wSynth_src_dropWire$whas, + flitToSink_0$whas, flitToSink_1$whas, flitToSink_1_0$whas, flitToSink_1_0_1$whas, @@ -834,24 +852,22 @@ module mkCoreW(RST_N_dm_power_on_reset, flitToSink_1_1_1_1$whas, flitToSink_1_2$whas, flitToSink_2$whas, + ifcs_0_1_snk_putWire$whas, ifcs_0_noRoute_inner_currentReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$EN_port0__write, ifcs_0_noRoute_inner_pendingReq$port1__read, ifcs_0_noRoute_inner_pendingReq$port2__read, + ifcs_0_snk_putWire$whas, + ifcs_1_1_snk_putWire$whas, ifcs_1_noRoute_inner_currentReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$EN_port0__write, ifcs_1_noRoute_inner_pendingReq$port1__read, ifcs_1_noRoute_inner_pendingReq$port2__read, + ifcs_1_snk_putWire$whas, merged_0_doDrop$whas, merged_1_doDrop$whas, - msNoSynth_0_ar_dwReady$whas, - msNoSynth_0_b_buffer_enqw$whas, - msNoSynth_0_r_buffer_enqw$whas, - msNoSynth_0_w_dwReady$whas, - msNoSynth_1_ar_dwReady$whas, - msNoSynth_1_b_buffer_enqw$whas, - msNoSynth_1_r_buffer_enqw$whas, - msNoSynth_1_w_dwReady$whas, + msNoSynth_0_arNoSynth_buffer_dequeueing$whas, + msNoSynth_1_arNoSynth_buffer_dequeueing$whas, reqWires_0$wget, reqWires_1$wget, reqWires_1_0$wget, @@ -867,35 +883,25 @@ module mkCoreW(RST_N_dm_power_on_reset, sourceSelect_1_1$whas, sourceSelect_1_1_1$whas, sourceSelect_1_2$whas, - ssNoSynth_0_b_dwReady$whas, - ssNoSynth_0_r_dwReady$whas, - ssNoSynth_0_w_buffer_enqw$whas, - ssNoSynth_1_b_dwReady$whas, - ssNoSynth_1_r_dwReady$whas, - ssNoSynth_1_w_buffer_enqw$whas, - ssNoSynth_2_b_dwReady$whas, - ssNoSynth_2_r_dwReady$whas, - ssNoSynth_2_w_buffer_enqw$whas, + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_0_wNoSynth_buffer_enqw$whas, + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_1_wNoSynth_buffer_enqw$whas, + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas, + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas, + ssNoSynth_2_wNoSynth_buffer_enqw$whas, tagController_tmp_shimMaster_arff_rv$EN_port0__write, tagController_tmp_shimMaster_awff_rv$EN_port0__write, tagController_tmp_shimMaster_wff_rv$EN_port0__write, tagController_tmp_shimSlave_bff_rv$EN_port0__write, tagController_tmp_shimSlave_rff_rv$EN_port0__write, - tagController_tmp_ug_master_u_ar_dropWire$whas, - tagController_tmp_ug_master_u_aw_dropWire$whas, - tagController_tmp_ug_master_u_b_putWire$whas, - tagController_tmp_ug_master_u_r_putWire$whas, - tagController_tmp_ug_master_u_w_dropWire$whas, - tmp0_ar_dwReady$whas, - tmp0_aw_dwReady$whas, - tmp0_b_buffer_enqw$whas, - tmp0_r_buffer_enqw$whas, - tmp0_w_dwReady$whas, - ug_uncached_mem_shim_master_u_ar_dropWire$whas, - ug_uncached_mem_shim_master_u_aw_dropWire$whas, - ug_uncached_mem_shim_master_u_b_putWire$whas, - ug_uncached_mem_shim_master_u_r_putWire$whas, - ug_uncached_mem_shim_master_u_w_dropWire$whas; + uncached_mem_master_arSynth_src_dropWire$whas, + uncached_mem_master_awSynth_src_dropWire$whas, + uncached_mem_master_bSynth_snk_putWire$whas, + uncached_mem_master_rSynth_snk_putWire$whas, + uncached_mem_master_wSynth_src_dropWire$whas; // register activeSource_0 reg activeSource_0; @@ -1469,57 +1475,177 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_2_rspBack$ENQ, ifcs_2_rspBack$FULL_N; - // ports of submodule msNoSynth_0_b_buffer_ff - wire [5 : 0] msNoSynth_0_b_buffer_ff$D_IN, msNoSynth_0_b_buffer_ff$D_OUT; - wire msNoSynth_0_b_buffer_ff$CLR, - msNoSynth_0_b_buffer_ff$DEQ, - msNoSynth_0_b_buffer_ff$EMPTY_N, - msNoSynth_0_b_buffer_ff$ENQ, - msNoSynth_0_b_buffer_ff$FULL_N; + // ports of submodule merged_0_awff + wire [96 : 0] merged_0_awff$D_IN, merged_0_awff$D_OUT; + wire merged_0_awff$CLR, + merged_0_awff$DEQ, + merged_0_awff$EMPTY_N, + merged_0_awff$ENQ, + merged_0_awff$FULL_N; - // ports of submodule msNoSynth_0_b_buffer_firstValid - wire msNoSynth_0_b_buffer_firstValid$D_IN, - msNoSynth_0_b_buffer_firstValid$EN, - msNoSynth_0_b_buffer_firstValid$Q_OUT; + // ports of submodule merged_0_wff + wire [73 : 0] merged_0_wff$D_IN, merged_0_wff$D_OUT; + wire merged_0_wff$CLR, + merged_0_wff$DEQ, + merged_0_wff$EMPTY_N, + merged_0_wff$ENQ, + merged_0_wff$FULL_N; - // ports of submodule msNoSynth_0_r_buffer_ff - wire [71 : 0] msNoSynth_0_r_buffer_ff$D_IN, msNoSynth_0_r_buffer_ff$D_OUT; - wire msNoSynth_0_r_buffer_ff$CLR, - msNoSynth_0_r_buffer_ff$DEQ, - msNoSynth_0_r_buffer_ff$EMPTY_N, - msNoSynth_0_r_buffer_ff$ENQ, - msNoSynth_0_r_buffer_ff$FULL_N; + // ports of submodule merged_1_awff + wire [96 : 0] merged_1_awff$D_IN, merged_1_awff$D_OUT; + wire merged_1_awff$CLR, + merged_1_awff$DEQ, + merged_1_awff$EMPTY_N, + merged_1_awff$ENQ, + merged_1_awff$FULL_N; - // ports of submodule msNoSynth_0_r_buffer_firstValid - wire msNoSynth_0_r_buffer_firstValid$D_IN, - msNoSynth_0_r_buffer_firstValid$EN, - msNoSynth_0_r_buffer_firstValid$Q_OUT; + // ports of submodule merged_1_wff + wire [73 : 0] merged_1_wff$D_IN, merged_1_wff$D_OUT; + wire merged_1_wff$CLR, + merged_1_wff$DEQ, + merged_1_wff$EMPTY_N, + merged_1_wff$ENQ, + merged_1_wff$FULL_N; - // ports of submodule msNoSynth_1_b_buffer_ff - wire [5 : 0] msNoSynth_1_b_buffer_ff$D_IN, msNoSynth_1_b_buffer_ff$D_OUT; - wire msNoSynth_1_b_buffer_ff$CLR, - msNoSynth_1_b_buffer_ff$DEQ, - msNoSynth_1_b_buffer_ff$EMPTY_N, - msNoSynth_1_b_buffer_ff$ENQ, - msNoSynth_1_b_buffer_ff$FULL_N; + // ports of submodule msNoSynth_0_arNoSynth_buffer_ff + wire [96 : 0] msNoSynth_0_arNoSynth_buffer_ff$D_IN, + msNoSynth_0_arNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_arNoSynth_buffer_ff$CLR, + msNoSynth_0_arNoSynth_buffer_ff$DEQ, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_arNoSynth_buffer_ff$ENQ, + msNoSynth_0_arNoSynth_buffer_ff$FULL_N; - // ports of submodule msNoSynth_1_b_buffer_firstValid - wire msNoSynth_1_b_buffer_firstValid$D_IN, - msNoSynth_1_b_buffer_firstValid$EN, - msNoSynth_1_b_buffer_firstValid$Q_OUT; + // ports of submodule msNoSynth_0_arNoSynth_buffer_firstValid + wire msNoSynth_0_arNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_arNoSynth_buffer_firstValid$EN, + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule msNoSynth_1_r_buffer_ff - wire [71 : 0] msNoSynth_1_r_buffer_ff$D_IN, msNoSynth_1_r_buffer_ff$D_OUT; - wire msNoSynth_1_r_buffer_ff$CLR, - msNoSynth_1_r_buffer_ff$DEQ, - msNoSynth_1_r_buffer_ff$EMPTY_N, - msNoSynth_1_r_buffer_ff$ENQ, - msNoSynth_1_r_buffer_ff$FULL_N; + // ports of submodule msNoSynth_0_awNoSynth_buffer_ff + wire [96 : 0] msNoSynth_0_awNoSynth_buffer_ff$D_IN, + msNoSynth_0_awNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_awNoSynth_buffer_ff$CLR, + msNoSynth_0_awNoSynth_buffer_ff$DEQ, + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_awNoSynth_buffer_ff$ENQ, + msNoSynth_0_awNoSynth_buffer_ff$FULL_N; - // ports of submodule msNoSynth_1_r_buffer_firstValid - wire msNoSynth_1_r_buffer_firstValid$D_IN, - msNoSynth_1_r_buffer_firstValid$EN, - msNoSynth_1_r_buffer_firstValid$Q_OUT; + // ports of submodule msNoSynth_0_awNoSynth_buffer_firstValid + wire msNoSynth_0_awNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_awNoSynth_buffer_firstValid$EN, + msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_bNoSynth_buffer_ff + wire [5 : 0] msNoSynth_0_bNoSynth_buffer_ff$D_IN, + msNoSynth_0_bNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_bNoSynth_buffer_ff$CLR, + msNoSynth_0_bNoSynth_buffer_ff$DEQ, + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_bNoSynth_buffer_ff$ENQ, + msNoSynth_0_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_bNoSynth_buffer_firstValid + wire msNoSynth_0_bNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_bNoSynth_buffer_firstValid$EN, + msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_rNoSynth_buffer_ff + wire [71 : 0] msNoSynth_0_rNoSynth_buffer_ff$D_IN, + msNoSynth_0_rNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_rNoSynth_buffer_ff$CLR, + msNoSynth_0_rNoSynth_buffer_ff$DEQ, + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_rNoSynth_buffer_ff$ENQ, + msNoSynth_0_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_rNoSynth_buffer_firstValid + wire msNoSynth_0_rNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_rNoSynth_buffer_firstValid$EN, + msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_wNoSynth_buffer_ff + wire [73 : 0] msNoSynth_0_wNoSynth_buffer_ff$D_IN, + msNoSynth_0_wNoSynth_buffer_ff$D_OUT; + wire msNoSynth_0_wNoSynth_buffer_ff$CLR, + msNoSynth_0_wNoSynth_buffer_ff$DEQ, + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, + msNoSynth_0_wNoSynth_buffer_ff$ENQ, + msNoSynth_0_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_wNoSynth_buffer_firstValid + wire msNoSynth_0_wNoSynth_buffer_firstValid$D_IN, + msNoSynth_0_wNoSynth_buffer_firstValid$EN, + msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_arNoSynth_buffer_ff + wire [96 : 0] msNoSynth_1_arNoSynth_buffer_ff$D_IN, + msNoSynth_1_arNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_arNoSynth_buffer_ff$CLR, + msNoSynth_1_arNoSynth_buffer_ff$DEQ, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_arNoSynth_buffer_ff$ENQ, + msNoSynth_1_arNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_arNoSynth_buffer_firstValid + wire msNoSynth_1_arNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_arNoSynth_buffer_firstValid$EN, + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_awNoSynth_buffer_ff + wire [96 : 0] msNoSynth_1_awNoSynth_buffer_ff$D_IN, + msNoSynth_1_awNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_awNoSynth_buffer_ff$CLR, + msNoSynth_1_awNoSynth_buffer_ff$DEQ, + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_awNoSynth_buffer_ff$ENQ, + msNoSynth_1_awNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_awNoSynth_buffer_firstValid + wire msNoSynth_1_awNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_awNoSynth_buffer_firstValid$EN, + msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_bNoSynth_buffer_ff + wire [5 : 0] msNoSynth_1_bNoSynth_buffer_ff$D_IN, + msNoSynth_1_bNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_bNoSynth_buffer_ff$CLR, + msNoSynth_1_bNoSynth_buffer_ff$DEQ, + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_bNoSynth_buffer_ff$ENQ, + msNoSynth_1_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_bNoSynth_buffer_firstValid + wire msNoSynth_1_bNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_bNoSynth_buffer_firstValid$EN, + msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_rNoSynth_buffer_ff + wire [71 : 0] msNoSynth_1_rNoSynth_buffer_ff$D_IN, + msNoSynth_1_rNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_rNoSynth_buffer_ff$CLR, + msNoSynth_1_rNoSynth_buffer_ff$DEQ, + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_rNoSynth_buffer_ff$ENQ, + msNoSynth_1_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_rNoSynth_buffer_firstValid + wire msNoSynth_1_rNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_rNoSynth_buffer_firstValid$EN, + msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_wNoSynth_buffer_ff + wire [73 : 0] msNoSynth_1_wNoSynth_buffer_ff$D_IN, + msNoSynth_1_wNoSynth_buffer_ff$D_OUT; + wire msNoSynth_1_wNoSynth_buffer_ff$CLR, + msNoSynth_1_wNoSynth_buffer_ff$DEQ, + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, + msNoSynth_1_wNoSynth_buffer_ff$ENQ, + msNoSynth_1_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_wNoSynth_buffer_firstValid + wire msNoSynth_1_wNoSynth_buffer_firstValid$D_IN, + msNoSynth_1_wNoSynth_buffer_firstValid$EN, + msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, @@ -1591,7 +1717,10 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip; // ports of submodule proc + wire [96 : 0] proc$master1_ar_peek, proc$master1_aw_peek; wire [76 : 0] proc$hart0_csr_mem_server_request_put; + wire [73 : 0] proc$master1_w_peek; + wire [71 : 0] proc$master1_r_put_val; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; wire [64 : 0] proc$hart0_csr_mem_server_response_get, @@ -1604,10 +1733,6 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awaddr, proc$master0_rdata, proc$master0_wdata, - proc$master1_araddr, - proc$master1_awaddr, - proc$master1_rdata, - proc$master1_wdata, proc$start_fromhostAddr, proc$start_startpc, proc$start_tohostAddr; @@ -1616,10 +1741,8 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$debug_module_mem_server_wstrb, proc$master0_arlen, proc$master0_awlen, - proc$master0_wstrb, - proc$master1_arlen, - proc$master1_awlen, - proc$master1_wstrb; + proc$master0_wstrb; + wire [5 : 0] proc$master1_b_put_val; wire [4 : 0] proc$debug_module_mem_server_arid, proc$debug_module_mem_server_awid, proc$debug_module_mem_server_bid, @@ -1641,16 +1764,6 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awcache, proc$master0_awqos, proc$master0_awregion, - proc$master1_arcache, - proc$master1_arid, - proc$master1_arqos, - proc$master1_arregion, - proc$master1_awcache, - proc$master1_awid, - proc$master1_awqos, - proc$master1_awregion, - proc$master1_bid, - proc$master1_rid, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, @@ -1659,11 +1772,7 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arprot, proc$master0_arsize, proc$master0_awprot, - proc$master0_awsize, - proc$master1_arprot, - proc$master1_arsize, - proc$master1_awprot, - proc$master1_awsize; + proc$master0_awsize; wire [1 : 0] proc$debug_module_mem_server_arburst, proc$debug_module_mem_server_awburst, proc$debug_module_mem_server_bresp, @@ -1671,11 +1780,7 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arburst, proc$master0_awburst, proc$master0_bresp, - proc$master0_rresp, - proc$master1_arburst, - proc$master1_awburst, - proc$master1_bresp, - proc$master1_rresp; + proc$master0_rresp; wire proc$EN_hart0_csr_mem_server_request_put, proc$EN_hart0_csr_mem_server_response_get, proc$EN_hart0_fpr_mem_server_request_put, @@ -1685,6 +1790,11 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$EN_hart0_put_other_req_put, proc$EN_hart0_run_halt_server_request_put, proc$EN_hart0_run_halt_server_response_get, + proc$EN_master1_ar_drop, + proc$EN_master1_aw_drop, + proc$EN_master1_b_put, + proc$EN_master1_r_put, + proc$EN_master1_w_drop, proc$EN_set_verbosity, proc$EN_start, proc$RDY_hart0_csr_mem_server_request_put, @@ -1693,6 +1803,14 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$RDY_hart0_gpr_mem_server_response_get, proc$RDY_hart0_run_halt_server_request_put, proc$RDY_hart0_run_halt_server_response_get, + proc$RDY_master1_ar_drop, + proc$RDY_master1_ar_peek, + proc$RDY_master1_aw_drop, + proc$RDY_master1_aw_peek, + proc$RDY_master1_b_put, + proc$RDY_master1_r_put, + proc$RDY_master1_w_drop, + proc$RDY_master1_w_peek, proc$RDY_start, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, @@ -1729,21 +1847,11 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_wready, proc$master0_wuser, proc$master0_wvalid, - proc$master1_arlock, - proc$master1_arready, - proc$master1_arvalid, - proc$master1_awlock, - proc$master1_awready, - proc$master1_awvalid, - proc$master1_bready, - proc$master1_bvalid, - proc$master1_rlast, - proc$master1_rready, - proc$master1_ruser, - proc$master1_rvalid, - proc$master1_wlast, - proc$master1_wready, - proc$master1_wvalid, + proc$master1_ar_canPeek, + proc$master1_aw_canPeek, + proc$master1_b_canPut, + proc$master1_r_canPut, + proc$master1_w_canPeek, proc$non_maskable_interrupt_req_set_not_clear, proc$s_external_interrupt_req_set_not_clear, proc$start_running; @@ -1755,122 +1863,215 @@ module mkCoreW(RST_N_dm_power_on_reset, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr; - // ports of submodule ssNoSynth_0_ar_buffer_ff - wire [97 : 0] ssNoSynth_0_ar_buffer_ff$D_IN, ssNoSynth_0_ar_buffer_ff$D_OUT; - wire ssNoSynth_0_ar_buffer_ff$CLR, - ssNoSynth_0_ar_buffer_ff$DEQ, - ssNoSynth_0_ar_buffer_ff$EMPTY_N, - ssNoSynth_0_ar_buffer_ff$ENQ, - ssNoSynth_0_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_0_arNoSynth_buffer_ff$D_IN, + ssNoSynth_0_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_arNoSynth_buffer_ff$CLR, + ssNoSynth_0_arNoSynth_buffer_ff$DEQ, + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_arNoSynth_buffer_ff$ENQ, + ssNoSynth_0_arNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_ar_buffer_firstValid - wire ssNoSynth_0_ar_buffer_firstValid$D_IN, - ssNoSynth_0_ar_buffer_firstValid$EN, - ssNoSynth_0_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_arNoSynth_buffer_firstValid + wire ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_arNoSynth_buffer_firstValid$EN, + ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_0_aw_buffer_ff - wire [97 : 0] ssNoSynth_0_aw_buffer_ff$D_IN, ssNoSynth_0_aw_buffer_ff$D_OUT; - wire ssNoSynth_0_aw_buffer_ff$CLR, - ssNoSynth_0_aw_buffer_ff$DEQ, - ssNoSynth_0_aw_buffer_ff$EMPTY_N, - ssNoSynth_0_aw_buffer_ff$ENQ, - ssNoSynth_0_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_0_awNoSynth_buffer_ff$D_IN, + ssNoSynth_0_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_awNoSynth_buffer_ff$CLR, + ssNoSynth_0_awNoSynth_buffer_ff$DEQ, + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_awNoSynth_buffer_ff$ENQ, + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_aw_buffer_firstValid - wire ssNoSynth_0_aw_buffer_firstValid$D_IN, - ssNoSynth_0_aw_buffer_firstValid$EN, - ssNoSynth_0_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_awNoSynth_buffer_firstValid + wire ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_awNoSynth_buffer_firstValid$EN, + ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_0_w_buffer_ff - wire [73 : 0] ssNoSynth_0_w_buffer_ff$D_IN, ssNoSynth_0_w_buffer_ff$D_OUT; - wire ssNoSynth_0_w_buffer_ff$CLR, - ssNoSynth_0_w_buffer_ff$DEQ, - ssNoSynth_0_w_buffer_ff$EMPTY_N, - ssNoSynth_0_w_buffer_ff$ENQ, - ssNoSynth_0_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_0_bNoSynth_buffer_ff$D_IN, + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_bNoSynth_buffer_ff$CLR, + ssNoSynth_0_bNoSynth_buffer_ff$DEQ, + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_bNoSynth_buffer_ff$ENQ, + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_0_w_buffer_firstValid - wire ssNoSynth_0_w_buffer_firstValid$D_IN, - ssNoSynth_0_w_buffer_firstValid$EN, - ssNoSynth_0_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_bNoSynth_buffer_firstValid + wire ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_bNoSynth_buffer_firstValid$EN, + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_ar_buffer_ff - wire [97 : 0] ssNoSynth_1_ar_buffer_ff$D_IN, ssNoSynth_1_ar_buffer_ff$D_OUT; - wire ssNoSynth_1_ar_buffer_ff$CLR, - ssNoSynth_1_ar_buffer_ff$DEQ, - ssNoSynth_1_ar_buffer_ff$EMPTY_N, - ssNoSynth_1_ar_buffer_ff$ENQ, - ssNoSynth_1_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_0_rNoSynth_buffer_ff$D_IN, + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_rNoSynth_buffer_ff$CLR, + ssNoSynth_0_rNoSynth_buffer_ff$DEQ, + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_rNoSynth_buffer_ff$ENQ, + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_ar_buffer_firstValid - wire ssNoSynth_1_ar_buffer_firstValid$D_IN, - ssNoSynth_1_ar_buffer_firstValid$EN, - ssNoSynth_1_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_rNoSynth_buffer_firstValid + wire ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_rNoSynth_buffer_firstValid$EN, + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_aw_buffer_ff - wire [97 : 0] ssNoSynth_1_aw_buffer_ff$D_IN, ssNoSynth_1_aw_buffer_ff$D_OUT; - wire ssNoSynth_1_aw_buffer_ff$CLR, - ssNoSynth_1_aw_buffer_ff$DEQ, - ssNoSynth_1_aw_buffer_ff$EMPTY_N, - ssNoSynth_1_aw_buffer_ff$ENQ, - ssNoSynth_1_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_0_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_0_wNoSynth_buffer_ff$D_IN, + ssNoSynth_0_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_0_wNoSynth_buffer_ff$CLR, + ssNoSynth_0_wNoSynth_buffer_ff$DEQ, + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_0_wNoSynth_buffer_ff$ENQ, + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_aw_buffer_firstValid - wire ssNoSynth_1_aw_buffer_firstValid$D_IN, - ssNoSynth_1_aw_buffer_firstValid$EN, - ssNoSynth_1_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_0_wNoSynth_buffer_firstValid + wire ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_0_wNoSynth_buffer_firstValid$EN, + ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_1_w_buffer_ff - wire [73 : 0] ssNoSynth_1_w_buffer_ff$D_IN, ssNoSynth_1_w_buffer_ff$D_OUT; - wire ssNoSynth_1_w_buffer_ff$CLR, - ssNoSynth_1_w_buffer_ff$DEQ, - ssNoSynth_1_w_buffer_ff$EMPTY_N, - ssNoSynth_1_w_buffer_ff$ENQ, - ssNoSynth_1_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_1_arNoSynth_buffer_ff$D_IN, + ssNoSynth_1_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_arNoSynth_buffer_ff$CLR, + ssNoSynth_1_arNoSynth_buffer_ff$DEQ, + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_arNoSynth_buffer_ff$ENQ, + ssNoSynth_1_arNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_1_w_buffer_firstValid - wire ssNoSynth_1_w_buffer_firstValid$D_IN, - ssNoSynth_1_w_buffer_firstValid$EN, - ssNoSynth_1_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_arNoSynth_buffer_firstValid + wire ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_arNoSynth_buffer_firstValid$EN, + ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_ar_buffer_ff - wire [97 : 0] ssNoSynth_2_ar_buffer_ff$D_IN, ssNoSynth_2_ar_buffer_ff$D_OUT; - wire ssNoSynth_2_ar_buffer_ff$CLR, - ssNoSynth_2_ar_buffer_ff$DEQ, - ssNoSynth_2_ar_buffer_ff$EMPTY_N, - ssNoSynth_2_ar_buffer_ff$ENQ, - ssNoSynth_2_ar_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_1_awNoSynth_buffer_ff$D_IN, + ssNoSynth_1_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_awNoSynth_buffer_ff$CLR, + ssNoSynth_1_awNoSynth_buffer_ff$DEQ, + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_awNoSynth_buffer_ff$ENQ, + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_ar_buffer_firstValid - wire ssNoSynth_2_ar_buffer_firstValid$D_IN, - ssNoSynth_2_ar_buffer_firstValid$EN, - ssNoSynth_2_ar_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_awNoSynth_buffer_firstValid + wire ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_awNoSynth_buffer_firstValid$EN, + ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_aw_buffer_ff - wire [97 : 0] ssNoSynth_2_aw_buffer_ff$D_IN, ssNoSynth_2_aw_buffer_ff$D_OUT; - wire ssNoSynth_2_aw_buffer_ff$CLR, - ssNoSynth_2_aw_buffer_ff$DEQ, - ssNoSynth_2_aw_buffer_ff$EMPTY_N, - ssNoSynth_2_aw_buffer_ff$ENQ, - ssNoSynth_2_aw_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_1_bNoSynth_buffer_ff$D_IN, + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_bNoSynth_buffer_ff$CLR, + ssNoSynth_1_bNoSynth_buffer_ff$DEQ, + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_bNoSynth_buffer_ff$ENQ, + ssNoSynth_1_bNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_aw_buffer_firstValid - wire ssNoSynth_2_aw_buffer_firstValid$D_IN, - ssNoSynth_2_aw_buffer_firstValid$EN, - ssNoSynth_2_aw_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_bNoSynth_buffer_firstValid + wire ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_bNoSynth_buffer_firstValid$EN, + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule ssNoSynth_2_w_buffer_ff - wire [73 : 0] ssNoSynth_2_w_buffer_ff$D_IN, ssNoSynth_2_w_buffer_ff$D_OUT; - wire ssNoSynth_2_w_buffer_ff$CLR, - ssNoSynth_2_w_buffer_ff$DEQ, - ssNoSynth_2_w_buffer_ff$EMPTY_N, - ssNoSynth_2_w_buffer_ff$ENQ, - ssNoSynth_2_w_buffer_ff$FULL_N; + // ports of submodule ssNoSynth_1_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_1_rNoSynth_buffer_ff$D_IN, + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_rNoSynth_buffer_ff$CLR, + ssNoSynth_1_rNoSynth_buffer_ff$DEQ, + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_rNoSynth_buffer_ff$ENQ, + ssNoSynth_1_rNoSynth_buffer_ff$FULL_N; - // ports of submodule ssNoSynth_2_w_buffer_firstValid - wire ssNoSynth_2_w_buffer_firstValid$D_IN, - ssNoSynth_2_w_buffer_firstValid$EN, - ssNoSynth_2_w_buffer_firstValid$Q_OUT; + // ports of submodule ssNoSynth_1_rNoSynth_buffer_firstValid + wire ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_rNoSynth_buffer_firstValid$EN, + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_1_wNoSynth_buffer_ff$D_IN, + ssNoSynth_1_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_1_wNoSynth_buffer_ff$CLR, + ssNoSynth_1_wNoSynth_buffer_ff$DEQ, + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_1_wNoSynth_buffer_ff$ENQ, + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_wNoSynth_buffer_firstValid + wire ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_1_wNoSynth_buffer_firstValid$EN, + ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_arNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_2_arNoSynth_buffer_ff$D_IN, + ssNoSynth_2_arNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_arNoSynth_buffer_ff$CLR, + ssNoSynth_2_arNoSynth_buffer_ff$DEQ, + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_arNoSynth_buffer_ff$ENQ, + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_arNoSynth_buffer_firstValid + wire ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_arNoSynth_buffer_firstValid$EN, + ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_awNoSynth_buffer_ff + wire [97 : 0] ssNoSynth_2_awNoSynth_buffer_ff$D_IN, + ssNoSynth_2_awNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_awNoSynth_buffer_ff$CLR, + ssNoSynth_2_awNoSynth_buffer_ff$DEQ, + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_awNoSynth_buffer_ff$ENQ, + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_awNoSynth_buffer_firstValid + wire ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_awNoSynth_buffer_firstValid$EN, + ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_bNoSynth_buffer_ff + wire [6 : 0] ssNoSynth_2_bNoSynth_buffer_ff$D_IN, + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_bNoSynth_buffer_ff$CLR, + ssNoSynth_2_bNoSynth_buffer_ff$DEQ, + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_bNoSynth_buffer_ff$ENQ, + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_bNoSynth_buffer_firstValid + wire ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_bNoSynth_buffer_firstValid$EN, + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_rNoSynth_buffer_ff + wire [72 : 0] ssNoSynth_2_rNoSynth_buffer_ff$D_IN, + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_rNoSynth_buffer_ff$CLR, + ssNoSynth_2_rNoSynth_buffer_ff$DEQ, + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_rNoSynth_buffer_ff$ENQ, + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_rNoSynth_buffer_firstValid + wire ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_rNoSynth_buffer_firstValid$EN, + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_wNoSynth_buffer_ff + wire [73 : 0] ssNoSynth_2_wNoSynth_buffer_ff$D_IN, + ssNoSynth_2_wNoSynth_buffer_ff$D_OUT; + wire ssNoSynth_2_wNoSynth_buffer_ff$CLR, + ssNoSynth_2_wNoSynth_buffer_ff$DEQ, + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N, + ssNoSynth_2_wNoSynth_buffer_ff$ENQ, + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_wNoSynth_buffer_firstValid + wire ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN, + ssNoSynth_2_wNoSynth_buffer_firstValid$EN, + ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule tagController_tmp_awreqff wire [97 : 0] tagController_tmp_awreqff$D_IN, @@ -1898,57 +2099,70 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_tagCon$RDY_memory_request_get, tagController_tmp_tagCon$RDY_memory_response_put; - // ports of submodule tmp0_b_buffer_ff - wire [5 : 0] tmp0_b_buffer_ff$D_IN, tmp0_b_buffer_ff$D_OUT; - wire tmp0_b_buffer_ff$CLR, - tmp0_b_buffer_ff$DEQ, - tmp0_b_buffer_ff$EMPTY_N, - tmp0_b_buffer_ff$ENQ, - tmp0_b_buffer_ff$FULL_N; + // ports of submodule tmp2_arNoSynth_buffer_ff + wire [97 : 0] tmp2_arNoSynth_buffer_ff$D_IN, tmp2_arNoSynth_buffer_ff$D_OUT; + wire tmp2_arNoSynth_buffer_ff$CLR, + tmp2_arNoSynth_buffer_ff$DEQ, + tmp2_arNoSynth_buffer_ff$EMPTY_N, + tmp2_arNoSynth_buffer_ff$ENQ, + tmp2_arNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp0_b_buffer_firstValid - wire tmp0_b_buffer_firstValid$D_IN, - tmp0_b_buffer_firstValid$EN, - tmp0_b_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_arNoSynth_buffer_firstValid + wire tmp2_arNoSynth_buffer_firstValid$D_IN, + tmp2_arNoSynth_buffer_firstValid$EN, + tmp2_arNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp0_r_buffer_ff - wire [71 : 0] tmp0_r_buffer_ff$D_IN, tmp0_r_buffer_ff$D_OUT; - wire tmp0_r_buffer_ff$CLR, - tmp0_r_buffer_ff$DEQ, - tmp0_r_buffer_ff$EMPTY_N, - tmp0_r_buffer_ff$ENQ, - tmp0_r_buffer_ff$FULL_N; + // ports of submodule tmp2_awNoSynth_buffer_ff + wire [97 : 0] tmp2_awNoSynth_buffer_ff$D_IN, tmp2_awNoSynth_buffer_ff$D_OUT; + wire tmp2_awNoSynth_buffer_ff$CLR, + tmp2_awNoSynth_buffer_ff$DEQ, + tmp2_awNoSynth_buffer_ff$EMPTY_N, + tmp2_awNoSynth_buffer_ff$ENQ, + tmp2_awNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp0_r_buffer_firstValid - wire tmp0_r_buffer_firstValid$D_IN, - tmp0_r_buffer_firstValid$EN, - tmp0_r_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_awNoSynth_buffer_firstValid + wire tmp2_awNoSynth_buffer_firstValid$D_IN, + tmp2_awNoSynth_buffer_firstValid$EN, + tmp2_awNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp2_b_buffer_ff - wire [6 : 0] tmp2_b_buffer_ff$D_IN, tmp2_b_buffer_ff$D_OUT; - wire tmp2_b_buffer_ff$CLR, - tmp2_b_buffer_ff$DEQ, - tmp2_b_buffer_ff$EMPTY_N, - tmp2_b_buffer_ff$ENQ, - tmp2_b_buffer_ff$FULL_N; + // ports of submodule tmp2_bNoSynth_buffer_ff + wire [6 : 0] tmp2_bNoSynth_buffer_ff$D_IN, tmp2_bNoSynth_buffer_ff$D_OUT; + wire tmp2_bNoSynth_buffer_ff$CLR, + tmp2_bNoSynth_buffer_ff$DEQ, + tmp2_bNoSynth_buffer_ff$EMPTY_N, + tmp2_bNoSynth_buffer_ff$ENQ, + tmp2_bNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp2_b_buffer_firstValid - wire tmp2_b_buffer_firstValid$D_IN, - tmp2_b_buffer_firstValid$EN, - tmp2_b_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_bNoSynth_buffer_firstValid + wire tmp2_bNoSynth_buffer_firstValid$D_IN, + tmp2_bNoSynth_buffer_firstValid$EN, + tmp2_bNoSynth_buffer_firstValid$Q_OUT; - // ports of submodule tmp2_r_buffer_ff - wire [72 : 0] tmp2_r_buffer_ff$D_IN, tmp2_r_buffer_ff$D_OUT; - wire tmp2_r_buffer_ff$CLR, - tmp2_r_buffer_ff$DEQ, - tmp2_r_buffer_ff$EMPTY_N, - tmp2_r_buffer_ff$ENQ, - tmp2_r_buffer_ff$FULL_N; + // ports of submodule tmp2_rNoSynth_buffer_ff + wire [72 : 0] tmp2_rNoSynth_buffer_ff$D_IN, tmp2_rNoSynth_buffer_ff$D_OUT; + wire tmp2_rNoSynth_buffer_ff$CLR, + tmp2_rNoSynth_buffer_ff$DEQ, + tmp2_rNoSynth_buffer_ff$EMPTY_N, + tmp2_rNoSynth_buffer_ff$ENQ, + tmp2_rNoSynth_buffer_ff$FULL_N; - // ports of submodule tmp2_r_buffer_firstValid - wire tmp2_r_buffer_firstValid$D_IN, - tmp2_r_buffer_firstValid$EN, - tmp2_r_buffer_firstValid$Q_OUT; + // ports of submodule tmp2_rNoSynth_buffer_firstValid + wire tmp2_rNoSynth_buffer_firstValid$D_IN, + tmp2_rNoSynth_buffer_firstValid$EN, + tmp2_rNoSynth_buffer_firstValid$Q_OUT; + + // ports of submodule tmp2_wNoSynth_buffer_ff + wire [73 : 0] tmp2_wNoSynth_buffer_ff$D_IN, tmp2_wNoSynth_buffer_ff$D_OUT; + wire tmp2_wNoSynth_buffer_ff$CLR, + tmp2_wNoSynth_buffer_ff$DEQ, + tmp2_wNoSynth_buffer_ff$EMPTY_N, + tmp2_wNoSynth_buffer_ff$ENQ, + tmp2_wNoSynth_buffer_ff$FULL_N; + + // ports of submodule tmp2_wNoSynth_buffer_firstValid + wire tmp2_wNoSynth_buffer_firstValid$D_IN, + tmp2_wNoSynth_buffer_firstValid$EN, + tmp2_wNoSynth_buffer_firstValid$Q_OUT; // ports of submodule uncached_mem_shim_arff wire [97 : 0] uncached_mem_shim_arff$D_IN, uncached_mem_shim_arff$D_OUT; @@ -1997,11 +2211,36 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_ClientServerResponse, CAN_FIRE_RL_ClientServerResponse_1, CAN_FIRE_RL_ClientServerResponse_2, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, CAN_FIRE_RL_arbitrate, CAN_FIRE_RL_arbitrate_1, CAN_FIRE_RL_arbitrate_2, @@ -2016,6 +2255,19 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_burst_7, CAN_FIRE_RL_burst_8, CAN_FIRE_RL_burst_9, + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut, + CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut, + CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop, + CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek, + CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_checkSinkReady, CAN_FIRE_RL_checkSinkReady_1, CAN_FIRE_RL_checkSinkReady_2, @@ -2042,67 +2294,132 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_ifcs_0_1_firstFlit_1, CAN_FIRE_RL_ifcs_0_1_followFlits, CAN_FIRE_RL_ifcs_0_1_followFlits_1, - CAN_FIRE_RL_ifcs_0_1_forwardRsp, CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_1_snk_doPut, + CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_0_drainFlits, CAN_FIRE_RL_ifcs_0_drainNoRouteResponse, CAN_FIRE_RL_ifcs_0_firstFlit, CAN_FIRE_RL_ifcs_0_firstFlit_1, CAN_FIRE_RL_ifcs_0_followFlits, CAN_FIRE_RL_ifcs_0_followFlits_1, - CAN_FIRE_RL_ifcs_0_forwardRsp, CAN_FIRE_RL_ifcs_0_nonRoutableFlit, CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_snk_doPut, + CAN_FIRE_RL_ifcs_0_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_1_drainFlits, CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_1_firstFlit, CAN_FIRE_RL_ifcs_1_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_1_followFlits, CAN_FIRE_RL_ifcs_1_1_followFlits_1, - CAN_FIRE_RL_ifcs_1_1_forwardRsp, CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_1_snk_doPut, + CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_1_drainFlits, CAN_FIRE_RL_ifcs_1_drainNoRouteResponse, CAN_FIRE_RL_ifcs_1_firstFlit, CAN_FIRE_RL_ifcs_1_firstFlit_1, CAN_FIRE_RL_ifcs_1_followFlits, CAN_FIRE_RL_ifcs_1_followFlits_1, - CAN_FIRE_RL_ifcs_1_forwardRsp, CAN_FIRE_RL_ifcs_1_nonRoutableFlit, CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_snk_doPut, + CAN_FIRE_RL_ifcs_1_snk_warnDoPut, CAN_FIRE_RL_ifcs_2_1_firstFlit, CAN_FIRE_RL_ifcs_2_1_followFlits, CAN_FIRE_RL_ifcs_2_firstFlit, CAN_FIRE_RL_ifcs_2_followFlits, + CAN_FIRE_RL_merged_0_awFlit, CAN_FIRE_RL_merged_0_genFirst, CAN_FIRE_RL_merged_0_genOther, + CAN_FIRE_RL_merged_0_passFlit, + CAN_FIRE_RL_merged_0_wFlit, + CAN_FIRE_RL_merged_1_awFlit, CAN_FIRE_RL_merged_1_genFirst, CAN_FIRE_RL_merged_1_genOther, + CAN_FIRE_RL_merged_1_passFlit, + CAN_FIRE_RL_merged_1_wFlit, CAN_FIRE_RL_mkConnectionGetPut, - CAN_FIRE_RL_msNoSynth_0_ar_forwardReady, - CAN_FIRE_RL_msNoSynth_0_aw_forwardReady, - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_0_b_dropFlit, - CAN_FIRE_RL_msNoSynth_0_b_forwardFlit, - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_0_r_dropFlit, - CAN_FIRE_RL_msNoSynth_0_r_forwardFlit, - CAN_FIRE_RL_msNoSynth_0_w_forwardReady, - CAN_FIRE_RL_msNoSynth_1_ar_forwardReady, - CAN_FIRE_RL_msNoSynth_1_aw_forwardReady, - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_1_b_dropFlit, - CAN_FIRE_RL_msNoSynth_1_b_forwardFlit, - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue, - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue, - CAN_FIRE_RL_msNoSynth_1_r_dropFlit, - CAN_FIRE_RL_msNoSynth_1_r_forwardFlit, - CAN_FIRE_RL_msNoSynth_1_w_forwardReady, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, + CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut, + CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut, + CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop, + CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek, + CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, CAN_FIRE_RL_rl_dm_hart0_reset, CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_relay_external_interrupts, @@ -2116,6 +2433,38 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_sink_selected_7, CAN_FIRE_RL_sink_selected_8, CAN_FIRE_RL_sink_selected_9, + CAN_FIRE_RL_sinks_0_doPut, + CAN_FIRE_RL_sinks_0_warnDoPut, + CAN_FIRE_RL_sinks_1_0_doPut, + CAN_FIRE_RL_sinks_1_0_doPut_1, + CAN_FIRE_RL_sinks_1_0_warnDoPut, + CAN_FIRE_RL_sinks_1_0_warnDoPut_1, + CAN_FIRE_RL_sinks_1_1_0_doPut, + CAN_FIRE_RL_sinks_1_1_0_warnDoPut, + CAN_FIRE_RL_sinks_1_1_1_doPut, + CAN_FIRE_RL_sinks_1_1_1_warnDoPut, + CAN_FIRE_RL_sinks_1_1_doPut, + CAN_FIRE_RL_sinks_1_1_doPut_1, + CAN_FIRE_RL_sinks_1_1_warnDoPut, + CAN_FIRE_RL_sinks_1_1_warnDoPut_1, + CAN_FIRE_RL_sinks_1_2_doPut, + CAN_FIRE_RL_sinks_1_2_warnDoPut, + CAN_FIRE_RL_sinks_1_doPut, + CAN_FIRE_RL_sinks_1_warnDoPut, + CAN_FIRE_RL_sinks_2_doPut, + CAN_FIRE_RL_sinks_2_warnDoPut, + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop, + CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek, + CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop, + CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek, + CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut, + CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, CAN_FIRE_RL_source_selected, CAN_FIRE_RL_source_selected_1, CAN_FIRE_RL_source_selected_2, @@ -2132,48 +2481,105 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_split_1_putOther, CAN_FIRE_RL_split_2_putFirst, CAN_FIRE_RL_split_2_putOther, - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_0_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_0_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_0_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_1_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_1_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit, - CAN_FIRE_RL_ssNoSynth_2_b_forwardReady, - CAN_FIRE_RL_ssNoSynth_2_r_forwardReady, - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit, - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, CAN_FIRE_RL_tagController_tmp_getCacheAW, CAN_FIRE_RL_tagController_tmp_passCacheRead, CAN_FIRE_RL_tagController_tmp_passCacheResponse, @@ -2207,77 +2613,87 @@ module mkCoreW(RST_N_dm_power_on_reset, CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, - CAN_FIRE_RL_tmp0_ar_forwardReady, - CAN_FIRE_RL_tmp0_aw_forwardReady, - CAN_FIRE_RL_tmp0_b_buffer_dequeue, - CAN_FIRE_RL_tmp0_b_buffer_enqueue, - CAN_FIRE_RL_tmp0_b_dropFlit, - CAN_FIRE_RL_tmp0_b_forwardFlit, - CAN_FIRE_RL_tmp0_r_buffer_dequeue, - CAN_FIRE_RL_tmp0_r_buffer_enqueue, - CAN_FIRE_RL_tmp0_r_dropFlit, - CAN_FIRE_RL_tmp0_r_forwardFlit, - CAN_FIRE_RL_tmp0_w_forwardReady, - CAN_FIRE_RL_tmp2_ar_forwardReady, - CAN_FIRE_RL_tmp2_aw_forwardReady, - CAN_FIRE_RL_tmp2_b_buffer_dequeue, - CAN_FIRE_RL_tmp2_b_buffer_enqueue, - CAN_FIRE_RL_tmp2_b_dropFlit, - CAN_FIRE_RL_tmp2_b_forwardFlit, - CAN_FIRE_RL_tmp2_r_buffer_dequeue, - CAN_FIRE_RL_tmp2_r_buffer_enqueue, - CAN_FIRE_RL_tmp2_r_dropFlit, - CAN_FIRE_RL_tmp2_r_forwardFlit, - CAN_FIRE_RL_tmp2_w_forwardReady, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, - CAN_FIRE___me_check_156, - CAN_FIRE___me_check_157, - CAN_FIRE___me_check_158, - CAN_FIRE___me_check_160, - CAN_FIRE___me_check_163, - CAN_FIRE___me_check_164, - CAN_FIRE___me_check_165, - CAN_FIRE___me_check_167, - CAN_FIRE___me_check_170, - CAN_FIRE___me_check_172, - CAN_FIRE___me_check_174, - CAN_FIRE___me_check_182, - CAN_FIRE___me_check_184, - CAN_FIRE___me_check_186, - CAN_FIRE___me_check_195, - CAN_FIRE___me_check_197, - CAN_FIRE___me_check_199, - CAN_FIRE___me_check_201, - CAN_FIRE___me_check_203, - CAN_FIRE___me_check_204, - CAN_FIRE___me_check_205, - CAN_FIRE___me_check_207, - CAN_FIRE___me_check_210, - CAN_FIRE___me_check_211, - CAN_FIRE___me_check_212, - CAN_FIRE___me_check_214, - CAN_FIRE___me_check_217, - CAN_FIRE___me_check_219, - CAN_FIRE___me_check_221, - CAN_FIRE___me_check_229, - CAN_FIRE___me_check_231, - CAN_FIRE___me_check_233, - CAN_FIRE___me_check_242, - CAN_FIRE___me_check_244, - CAN_FIRE___me_check_246, - CAN_FIRE___me_check_248, + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_arNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_awNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit, + CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop, + CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek, + CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit, + CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop, + CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek, + CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit, + CAN_FIRE_RL_tmp2_wNoSynth_forwardReady, + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut, + CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, + CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, + CAN_FIRE___me_check_323, + CAN_FIRE___me_check_324, + CAN_FIRE___me_check_325, + CAN_FIRE___me_check_327, + CAN_FIRE___me_check_331, + CAN_FIRE___me_check_332, + CAN_FIRE___me_check_333, + CAN_FIRE___me_check_335, + CAN_FIRE___me_check_337, + CAN_FIRE___me_check_339, + CAN_FIRE___me_check_341, + CAN_FIRE___me_check_355, + CAN_FIRE___me_check_357, + CAN_FIRE___me_check_359, + CAN_FIRE___me_check_372, + CAN_FIRE___me_check_374, + CAN_FIRE___me_check_376, + CAN_FIRE___me_check_378, + CAN_FIRE___me_check_382, + CAN_FIRE___me_check_383, + CAN_FIRE___me_check_384, + CAN_FIRE___me_check_386, + CAN_FIRE___me_check_390, + CAN_FIRE___me_check_391, + CAN_FIRE___me_check_392, + CAN_FIRE___me_check_394, + CAN_FIRE___me_check_396, + CAN_FIRE___me_check_398, + CAN_FIRE___me_check_400, + CAN_FIRE___me_check_414, + CAN_FIRE___me_check_416, + CAN_FIRE___me_check_418, + CAN_FIRE___me_check_431, + CAN_FIRE___me_check_433, + CAN_FIRE___me_check_435, + CAN_FIRE___me_check_437, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -2318,11 +2734,36 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ClientServerResponse, WILL_FIRE_RL_ClientServerResponse_1, WILL_FIRE_RL_ClientServerResponse_2, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut, - WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek, + WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop, WILL_FIRE_RL_arbitrate, WILL_FIRE_RL_arbitrate_1, WILL_FIRE_RL_arbitrate_2, @@ -2337,6 +2778,19 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_burst_7, WILL_FIRE_RL_burst_8, WILL_FIRE_RL_burst_9, + WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut, + WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut, + WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop, + WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek, + WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_checkSinkReady, WILL_FIRE_RL_checkSinkReady_1, WILL_FIRE_RL_checkSinkReady_2, @@ -2363,67 +2817,132 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ifcs_0_1_firstFlit_1, WILL_FIRE_RL_ifcs_0_1_followFlits, WILL_FIRE_RL_ifcs_0_1_followFlits_1, - WILL_FIRE_RL_ifcs_0_1_forwardRsp, WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_1_snk_doPut, + WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_0_drainFlits, WILL_FIRE_RL_ifcs_0_drainNoRouteResponse, WILL_FIRE_RL_ifcs_0_firstFlit, WILL_FIRE_RL_ifcs_0_firstFlit_1, WILL_FIRE_RL_ifcs_0_followFlits, WILL_FIRE_RL_ifcs_0_followFlits_1, - WILL_FIRE_RL_ifcs_0_forwardRsp, WILL_FIRE_RL_ifcs_0_nonRoutableFlit, WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_snk_doPut, + WILL_FIRE_RL_ifcs_0_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_1_drainFlits, WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_1_firstFlit, WILL_FIRE_RL_ifcs_1_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_1_followFlits, WILL_FIRE_RL_ifcs_1_1_followFlits_1, - WILL_FIRE_RL_ifcs_1_1_forwardRsp, WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_1_snk_doPut, + WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_1_drainFlits, WILL_FIRE_RL_ifcs_1_drainNoRouteResponse, WILL_FIRE_RL_ifcs_1_firstFlit, WILL_FIRE_RL_ifcs_1_firstFlit_1, WILL_FIRE_RL_ifcs_1_followFlits, WILL_FIRE_RL_ifcs_1_followFlits_1, - WILL_FIRE_RL_ifcs_1_forwardRsp, WILL_FIRE_RL_ifcs_1_nonRoutableFlit, WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_snk_doPut, + WILL_FIRE_RL_ifcs_1_snk_warnDoPut, WILL_FIRE_RL_ifcs_2_1_firstFlit, WILL_FIRE_RL_ifcs_2_1_followFlits, WILL_FIRE_RL_ifcs_2_firstFlit, WILL_FIRE_RL_ifcs_2_followFlits, + WILL_FIRE_RL_merged_0_awFlit, WILL_FIRE_RL_merged_0_genFirst, WILL_FIRE_RL_merged_0_genOther, + WILL_FIRE_RL_merged_0_passFlit, + WILL_FIRE_RL_merged_0_wFlit, + WILL_FIRE_RL_merged_1_awFlit, WILL_FIRE_RL_merged_1_genFirst, WILL_FIRE_RL_merged_1_genOther, + WILL_FIRE_RL_merged_1_passFlit, + WILL_FIRE_RL_merged_1_wFlit, WILL_FIRE_RL_mkConnectionGetPut, - WILL_FIRE_RL_msNoSynth_0_ar_forwardReady, - WILL_FIRE_RL_msNoSynth_0_aw_forwardReady, - WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_0_b_dropFlit, - WILL_FIRE_RL_msNoSynth_0_b_forwardFlit, - WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_0_r_dropFlit, - WILL_FIRE_RL_msNoSynth_0_r_forwardFlit, - WILL_FIRE_RL_msNoSynth_0_w_forwardReady, - WILL_FIRE_RL_msNoSynth_1_ar_forwardReady, - WILL_FIRE_RL_msNoSynth_1_aw_forwardReady, - WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_1_b_dropFlit, - WILL_FIRE_RL_msNoSynth_1_b_forwardFlit, - WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue, - WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue, - WILL_FIRE_RL_msNoSynth_1_r_dropFlit, - WILL_FIRE_RL_msNoSynth_1_r_forwardFlit, - WILL_FIRE_RL_msNoSynth_1_w_forwardReady, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek, + WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut, + WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop, + WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop, + WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut, + WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut, + WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut, + WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop, + WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek, + WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop, WILL_FIRE_RL_rl_dm_hart0_reset, WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_relay_external_interrupts, @@ -2437,6 +2956,38 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_sink_selected_7, WILL_FIRE_RL_sink_selected_8, WILL_FIRE_RL_sink_selected_9, + WILL_FIRE_RL_sinks_0_doPut, + WILL_FIRE_RL_sinks_0_warnDoPut, + WILL_FIRE_RL_sinks_1_0_doPut, + WILL_FIRE_RL_sinks_1_0_doPut_1, + WILL_FIRE_RL_sinks_1_0_warnDoPut, + WILL_FIRE_RL_sinks_1_0_warnDoPut_1, + WILL_FIRE_RL_sinks_1_1_0_doPut, + WILL_FIRE_RL_sinks_1_1_0_warnDoPut, + WILL_FIRE_RL_sinks_1_1_1_doPut, + WILL_FIRE_RL_sinks_1_1_1_warnDoPut, + WILL_FIRE_RL_sinks_1_1_doPut, + WILL_FIRE_RL_sinks_1_1_doPut_1, + WILL_FIRE_RL_sinks_1_1_warnDoPut, + WILL_FIRE_RL_sinks_1_1_warnDoPut_1, + WILL_FIRE_RL_sinks_1_2_doPut, + WILL_FIRE_RL_sinks_1_2_warnDoPut, + WILL_FIRE_RL_sinks_1_doPut, + WILL_FIRE_RL_sinks_1_warnDoPut, + WILL_FIRE_RL_sinks_2_doPut, + WILL_FIRE_RL_sinks_2_warnDoPut, + WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut, + WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut, + WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop, + WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek, + WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop, + WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop, + WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek, + WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop, + WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut, + WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut, WILL_FIRE_RL_source_selected, WILL_FIRE_RL_source_selected_1, WILL_FIRE_RL_source_selected_2, @@ -2453,48 +3004,105 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_split_1_putOther, WILL_FIRE_RL_split_2_putFirst, WILL_FIRE_RL_split_2_putOther, - WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_0_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_0_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_1_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_1_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_1_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit, - WILL_FIRE_RL_ssNoSynth_2_b_forwardReady, - WILL_FIRE_RL_ssNoSynth_2_r_forwardReady, - WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, - WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, - WILL_FIRE_RL_ssNoSynth_2_w_dropFlit, - WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut, + WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek, + WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop, WILL_FIRE_RL_tagController_tmp_getCacheAW, WILL_FIRE_RL_tagController_tmp_passCacheRead, WILL_FIRE_RL_tagController_tmp_passCacheResponse, @@ -2528,77 +3136,87 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut, WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut, - WILL_FIRE_RL_tmp0_ar_forwardReady, - WILL_FIRE_RL_tmp0_aw_forwardReady, - WILL_FIRE_RL_tmp0_b_buffer_dequeue, - WILL_FIRE_RL_tmp0_b_buffer_enqueue, - WILL_FIRE_RL_tmp0_b_dropFlit, - WILL_FIRE_RL_tmp0_b_forwardFlit, - WILL_FIRE_RL_tmp0_r_buffer_dequeue, - WILL_FIRE_RL_tmp0_r_buffer_enqueue, - WILL_FIRE_RL_tmp0_r_dropFlit, - WILL_FIRE_RL_tmp0_r_forwardFlit, - WILL_FIRE_RL_tmp0_w_forwardReady, - WILL_FIRE_RL_tmp2_ar_forwardReady, - WILL_FIRE_RL_tmp2_aw_forwardReady, - WILL_FIRE_RL_tmp2_b_buffer_dequeue, - WILL_FIRE_RL_tmp2_b_buffer_enqueue, - WILL_FIRE_RL_tmp2_b_dropFlit, - WILL_FIRE_RL_tmp2_b_forwardFlit, - WILL_FIRE_RL_tmp2_r_buffer_dequeue, - WILL_FIRE_RL_tmp2_r_buffer_enqueue, - WILL_FIRE_RL_tmp2_r_dropFlit, - WILL_FIRE_RL_tmp2_r_forwardFlit, - WILL_FIRE_RL_tmp2_w_forwardReady, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek, - WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop, - WILL_FIRE___me_check_156, - WILL_FIRE___me_check_157, - WILL_FIRE___me_check_158, - WILL_FIRE___me_check_160, - WILL_FIRE___me_check_163, - WILL_FIRE___me_check_164, - WILL_FIRE___me_check_165, - WILL_FIRE___me_check_167, - WILL_FIRE___me_check_170, - WILL_FIRE___me_check_172, - WILL_FIRE___me_check_174, - WILL_FIRE___me_check_182, - WILL_FIRE___me_check_184, - WILL_FIRE___me_check_186, - WILL_FIRE___me_check_195, - WILL_FIRE___me_check_197, - WILL_FIRE___me_check_199, - WILL_FIRE___me_check_201, - WILL_FIRE___me_check_203, - WILL_FIRE___me_check_204, - WILL_FIRE___me_check_205, - WILL_FIRE___me_check_207, - WILL_FIRE___me_check_210, - WILL_FIRE___me_check_211, - WILL_FIRE___me_check_212, - WILL_FIRE___me_check_214, - WILL_FIRE___me_check_217, - WILL_FIRE___me_check_219, - WILL_FIRE___me_check_221, - WILL_FIRE___me_check_229, - WILL_FIRE___me_check_231, - WILL_FIRE___me_check_233, - WILL_FIRE___me_check_242, - WILL_FIRE___me_check_244, - WILL_FIRE___me_check_246, - WILL_FIRE___me_check_248, + WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_arNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut, + WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_awNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut, + WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_bNoSynth_dropFlit, + WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop, + WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek, + WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop, + WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_rNoSynth_dropFlit, + WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop, + WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek, + WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop, + WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue, + WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue, + WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit, + WILL_FIRE_RL_tmp2_wNoSynth_forwardReady, + WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut, + WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut, + WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut, + WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek, + WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop, + WILL_FIRE___me_check_323, + WILL_FIRE___me_check_324, + WILL_FIRE___me_check_325, + WILL_FIRE___me_check_327, + WILL_FIRE___me_check_331, + WILL_FIRE___me_check_332, + WILL_FIRE___me_check_333, + WILL_FIRE___me_check_335, + WILL_FIRE___me_check_337, + WILL_FIRE___me_check_339, + WILL_FIRE___me_check_341, + WILL_FIRE___me_check_355, + WILL_FIRE___me_check_357, + WILL_FIRE___me_check_359, + WILL_FIRE___me_check_372, + WILL_FIRE___me_check_374, + WILL_FIRE___me_check_376, + WILL_FIRE___me_check_378, + WILL_FIRE___me_check_382, + WILL_FIRE___me_check_383, + WILL_FIRE___me_check_384, + WILL_FIRE___me_check_386, + WILL_FIRE___me_check_390, + WILL_FIRE___me_check_391, + WILL_FIRE___me_check_392, + WILL_FIRE___me_check_394, + WILL_FIRE___me_check_396, + WILL_FIRE___me_check_398, + WILL_FIRE___me_check_400, + WILL_FIRE___me_check_414, + WILL_FIRE___me_check_416, + WILL_FIRE___me_check_418, + WILL_FIRE___me_check_431, + WILL_FIRE___me_check_433, + WILL_FIRE___me_check_435, + WILL_FIRE___me_check_437, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -2635,16 +3253,16 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_start; // inputs to muxes for submodule ports - reg [71 : 0] MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2, - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2; - reg [5 : 0] MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2, - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2; + reg [71 : 0] MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1, + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1; + reg [5 : 0] MUX_ifcs_0_snk_putWire$wset_1__VAL_1, + MUX_ifcs_1_snk_putWire$wset_1__VAL_1; wire [140 : 0] MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1, MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_2; wire [76 : 0] MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_1, MUX_tagController_tmp_tagCon$memory_response_put_1__VAL_2; - wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_1, - MUX_merged_1_flitLeft$write_1__VAL_1, + wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_2, + MUX_merged_1_flitLeft$write_1__VAL_2, MUX_rg_hart0_reset_delay$write_1__VAL_1, MUX_split_0_flitLeft$write_1__VAL_1, MUX_split_1_flitLeft$write_1__VAL_1, @@ -2720,99 +3338,105 @@ module mkCoreW(RST_N_dm_power_on_reset, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h22825; - reg [31 : 0] v__h22968; - reg [63 : 0] v__h50461; - reg [63 : 0] v__h49850; - reg [63 : 0] v__h54470; - reg [63 : 0] v__h53859; - reg [63 : 0] v__h84222; - reg [63 : 0] v__h83611; - reg [63 : 0] v__h87115; - reg [63 : 0] v__h86504; - reg [63 : 0] v__h65165; - reg [63 : 0] v__h64784; - reg [63 : 0] v__h67235; - reg [63 : 0] v__h66854; - reg [63 : 0] v__h69134; - reg [63 : 0] v__h68753; - reg [63 : 0] v__h96395; - reg [63 : 0] v__h96014; - reg [63 : 0] v__h98886; - reg [63 : 0] v__h98505; - reg [63 : 0] v__h101196; - reg [63 : 0] v__h100815; - reg [31 : 0] v__h103640; - reg [31 : 0] v__h22819; - reg [31 : 0] v__h22962; - reg [31 : 0] v__h103634; + reg [31 : 0] v__h27371; + reg [31 : 0] v__h27514; + reg [63 : 0] v__h71925; + reg [63 : 0] v__h71314; + reg [63 : 0] v__h75934; + reg [63 : 0] v__h75323; + reg [63 : 0] v__h87100; + reg [63 : 0] v__h86719; + reg [63 : 0] v__h89170; + reg [63 : 0] v__h88789; + reg [63 : 0] v__h91069; + reg [63 : 0] v__h90688; + reg [63 : 0] v__h107698; + reg [63 : 0] v__h107087; + reg [63 : 0] v__h110591; + reg [63 : 0] v__h109980; + reg [63 : 0] v__h120378; + reg [63 : 0] v__h119997; + reg [63 : 0] v__h122869; + reg [63 : 0] v__h122488; + reg [63 : 0] v__h125179; + reg [63 : 0] v__h124798; + reg [31 : 0] v__h128907; + reg [31 : 0] v__h27365; + reg [31 : 0] v__h27508; + reg [31 : 0] v__h128901; // synopsys translate_on // remaining internal signals + wire [171 : 0] IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645; wire [98 : 0] tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4, tagController_tmp_shimMaster_awff_rvport1__re_ETC__q2; wire [72 : 0] tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3, uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1; - wire [63 : 0] araddr__h15540, - aw_awaddr__h10808, - tmp__h10591, - tmp__h8366, - v_araddr__h15557, - x__h37445, - x__h37480, - x__h40162, - x__h40187, - x__h71737, - x__h71762, - x__h74126, - x__h74151, - x__h8207, - x_rdata__h25045; - wire [39 : 0] x__h10840; - wire [8 : 0] x_port1__read__h72781, x_port1__read__h75154; - wire [7 : 0] arlen__h15541, v_arlen__h15558; - wire [5 : 0] v_arid__h15556; - wire [4 : 0] a_awid__h38523, - a_awid__h41194, - fatReq_arid__h72223, - fatReq_arid__h74597; - wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245, - arcache__h15545, - x__h10883, - x__h12617, - x__h12629, - x__h12641, - x__h12653, - x__h12665, - x__h12677, - x__h12689, - x__h14213, - x__h15621, - x_rid__h25044, - y__h12618, - y__h12630, - y__h12642, - y__h12654, - y__h12666, - y__h12678, - y__h12690; - wire [2 : 0] aw_awsize_val__h12547, v_arsize_val__h15603; - wire [1 : 0] IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207, - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211, - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310, - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945, - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858, - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863, - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22, - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17, - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12, - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7, + wire [63 : 0] addr__h93758, + addr__h96375, + araddr__h15343, + aw_awaddr__h10611, + tmp__h10394, + tmp__h8169, + v_araddr__h15360, + x__h56232, + x__h56267, + x__h59744, + x__h59769, + x__h8010, + x__h93834, + x__h93859, + x__h96451, + x__h96476; + wire [39 : 0] x__h10643; + wire [8 : 0] x__h95023, x__h97622; + wire [7 : 0] arlen__h15344, v_arlen__h15361, x__h94920, x__h97519; + wire [5 : 0] v_arid__h15359; + wire [4 : 0] fatReq_arid__h94342, + fatReq_arid__h96944, + x__h100325, + x__h62625, + x__h63516, + x__h64407, + x__h98415, + x__h99370; + wire [3 : 0] _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224, + arcache__h15348, + x__h10686, + x__h12420, + x__h12432, + x__h12444, + x__h12456, + x__h12468, + x__h12480, + x__h12492, + x__h14016, + x__h15424, + y__h12421, + y__h12433, + y__h12445, + y__h12457, + y__h12469, + y__h12481, + y__h12493; + wire [2 : 0] aw_awsize_val__h12350, v_arsize_val__h15406; + wire [1 : 0] IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531, + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535, + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629, + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231, + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326, + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331, + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22, + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12, + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17, + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7, SEXT_arbiter_1_1_firstHot__q19, SEXT_arbiter_1_1_lastSelect_1__q21, SEXT_arbiter_1_1_lastSelect__q20, @@ -2823,146 +3447,146 @@ module mkCoreW(RST_N_dm_power_on_reset, SEXT_arbiter_1_lastSelect__q10, SEXT_arbiter_firstHot__q5, SEXT_arbiter_lastSelect__q6, - SEXT_x2747__q18, - SEXT_x3466__q13, - SEXT_x3500__q14, - SEXT_x4692__q23, - SEXT_x4726__q24, - SEXT_x8980__q8; - wire IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098, - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455, - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114, - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356, - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362, - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150, - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723, - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729, - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507, - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200, - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300, - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302, - IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425, - IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426, - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427, - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331, - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325, - SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319, - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138, - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698, - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692, - SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134, - SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686, - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495, - SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491, - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932, - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937, - debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930, - debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935, - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845, - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850, - proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843, - proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848, - reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669, - reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302, - split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093, - split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122, - split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151, - state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193, - state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233, - state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400, - state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436, - state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472, - state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761, - state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794, - state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828, - state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556, - state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600, - x__h48453, - x__h48556, - x__h48921, - x__h48980, - x__h49062, - x__h62645, - x__h62647, - x__h62796, - x__h62798, - x__h62932, - x__h62934, - x__h63404, - x__h63406, - x__h63466, - x__h63500, - x__h63592, - x__h63594, - x__h63773, - x__h63775, - x__h82220, - x__h82323, - x__h82688, - x__h82747, - x__h82829, - x__h93871, - x__h93873, - x__h94022, - x__h94024, - x__h94158, - x__h94160, - x__h94630, - x__h94632, - x__h94692, - x__h94726, - x__h94818, - x__h94820, - x__h94999, - x__h95001, - y__h48454, - y__h48557, - y__h48922, - y__h49063, - y__h62646, - y__h62648, - y__h62797, - y__h62799, - y__h62933, - y__h62935, - y__h63405, - y__h63407, - y__h63593, - y__h63595, - y__h63774, - y__h63776, - y__h82221, - y__h82324, - y__h82689, - y__h82830, - y__h93872, - y__h93874, - y__h94023, - y__h94025, - y__h94159, - y__h94161, - y__h94631, - y__h94633, - y__h94819, - y__h94821, - y__h95000, - y__h95002; + SEXT_x0450__q8, + SEXT_x06223__q18, + SEXT_x18675__q23, + SEXT_x18709__q24, + SEXT_x5401__q13, + SEXT_x5435__q14; + wire IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513, + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812, + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529, + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775, + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084, + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090, + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565, + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569, + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864, + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868, + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524, + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556, + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561, + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619, + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650, + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221, + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316, + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764, + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773, + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782, + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750, + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744, + SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738, + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059, + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553, + SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047, + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053, + SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549, + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852, + SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848, + reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030, + reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721, + split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409, + split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438, + split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467, + state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122, + state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155, + state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189, + state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819, + state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855, + state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891, + state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608, + state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648, + state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913, + state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957, + x__h105696, + x__h105799, + x__h106164, + x__h106223, + x__h106305, + x__h117854, + x__h117856, + x__h118005, + x__h118007, + x__h118141, + x__h118143, + x__h118613, + x__h118615, + x__h118675, + x__h118709, + x__h118801, + x__h118803, + x__h118982, + x__h118984, + x__h69923, + x__h70026, + x__h70391, + x__h70450, + x__h70532, + x__h84580, + x__h84582, + x__h84731, + x__h84733, + x__h84867, + x__h84869, + x__h85339, + x__h85341, + x__h85401, + x__h85435, + x__h85527, + x__h85529, + x__h85708, + x__h85710, + y__h105697, + y__h105800, + y__h106165, + y__h106306, + y__h117855, + y__h117857, + y__h118006, + y__h118008, + y__h118142, + y__h118144, + y__h118614, + y__h118616, + y__h118802, + y__h118804, + y__h118983, + y__h118985, + y__h69924, + y__h70027, + y__h70392, + y__h70533, + y__h84581, + y__h84583, + y__h84732, + y__h84734, + y__h84868, + y__h84870, + y__h85340, + y__h85342, + y__h85528, + y__h85530, + y__h85709, + y__h85711; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; @@ -3044,7 +3668,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_imem_master_b_bflit assign CAN_FIRE_cpu_imem_master_b_bflit = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_b_bflit = cpu_imem_master_bvalid ; + assign WILL_FIRE_cpu_imem_master_b_bflit = 1'd1 ; // value method cpu_imem_master_b_bready assign cpu_imem_master_bready = !tagController_tmp_shimMaster_bff_rv[8] ; @@ -3099,50 +3723,50 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_imem_master_r_rflit assign CAN_FIRE_cpu_imem_master_r_rflit = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_r_rflit = cpu_imem_master_rvalid ; + assign WILL_FIRE_cpu_imem_master_r_rflit = 1'd1 ; // value method cpu_imem_master_r_rready assign cpu_imem_master_rready = !tagController_tmp_shimMaster_rff_rv[73] ; // value method cpu_dmem_master_aw_awid assign cpu_dmem_master_awid = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[98:93] ; + uncached_mem_master_awSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_aw_awaddr assign cpu_dmem_master_awaddr = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[92:29] ; + uncached_mem_master_awSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_aw_awlen assign cpu_dmem_master_awlen = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[28:21] ; + uncached_mem_master_awSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_aw_awsize assign cpu_dmem_master_awsize = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[20:18] ; + uncached_mem_master_awSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_aw_awburst assign cpu_dmem_master_awburst = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[17:16] ; + uncached_mem_master_awSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_aw_awlock assign cpu_dmem_master_awlock = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[15] ; + uncached_mem_master_awSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_aw_awcache assign cpu_dmem_master_awcache = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[14:11] ; + uncached_mem_master_awSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_aw_awprot assign cpu_dmem_master_awprot = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[10:8] ; + uncached_mem_master_awSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_aw_awqos assign cpu_dmem_master_awqos = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[7:4] ; + uncached_mem_master_awSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_aw_awregion assign cpu_dmem_master_awregion = - ug_uncached_mem_shim_master_u_aw_peekWire$wget[3:0] ; + uncached_mem_master_awSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_aw_awvalid assign cpu_dmem_master_awvalid = uncached_mem_shim_awff$EMPTY_N ; @@ -3172,50 +3796,50 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_dmem_master_b_bflit assign CAN_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_b_bflit = cpu_dmem_master_bvalid ; + assign WILL_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; // value method cpu_dmem_master_b_bready assign cpu_dmem_master_bready = uncached_mem_shim_bff$FULL_N ; // value method cpu_dmem_master_ar_arid assign cpu_dmem_master_arid = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[98:93] ; + uncached_mem_master_arSynth_src_peekWire$wget[98:93] ; // value method cpu_dmem_master_ar_araddr assign cpu_dmem_master_araddr = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[92:29] ; + uncached_mem_master_arSynth_src_peekWire$wget[92:29] ; // value method cpu_dmem_master_ar_arlen assign cpu_dmem_master_arlen = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[28:21] ; + uncached_mem_master_arSynth_src_peekWire$wget[28:21] ; // value method cpu_dmem_master_ar_arsize assign cpu_dmem_master_arsize = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[20:18] ; + uncached_mem_master_arSynth_src_peekWire$wget[20:18] ; // value method cpu_dmem_master_ar_arburst assign cpu_dmem_master_arburst = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[17:16] ; + uncached_mem_master_arSynth_src_peekWire$wget[17:16] ; // value method cpu_dmem_master_ar_arlock assign cpu_dmem_master_arlock = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[15] ; + uncached_mem_master_arSynth_src_peekWire$wget[15] ; // value method cpu_dmem_master_ar_arcache assign cpu_dmem_master_arcache = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[14:11] ; + uncached_mem_master_arSynth_src_peekWire$wget[14:11] ; // value method cpu_dmem_master_ar_arprot assign cpu_dmem_master_arprot = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[10:8] ; + uncached_mem_master_arSynth_src_peekWire$wget[10:8] ; // value method cpu_dmem_master_ar_arqos assign cpu_dmem_master_arqos = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[7:4] ; + uncached_mem_master_arSynth_src_peekWire$wget[7:4] ; // value method cpu_dmem_master_ar_arregion assign cpu_dmem_master_arregion = - ug_uncached_mem_shim_master_u_ar_peekWire$wget[3:0] ; + uncached_mem_master_arSynth_src_peekWire$wget[3:0] ; // value method cpu_dmem_master_ar_arvalid assign cpu_dmem_master_arvalid = uncached_mem_shim_arff$EMPTY_N ; @@ -3226,7 +3850,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // action method cpu_dmem_master_r_rflit assign CAN_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_r_rflit = cpu_dmem_master_rvalid ; + assign WILL_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; // value method cpu_dmem_master_r_rready assign cpu_dmem_master_rready = uncached_mem_shim_rff$FULL_N ; @@ -3348,11 +3972,13 @@ module mkCoreW(RST_N_dm_power_on_reset, .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), .master_bresp(debug_module$master_bresp), + .master_bvalid(debug_module$master_bvalid), .master_rdata(debug_module$master_rdata), .master_rid(debug_module$master_rid), .master_rlast(debug_module$master_rlast), .master_rresp(debug_module$master_rresp), .master_ruser(debug_module$master_ruser), + .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), @@ -3371,8 +3997,6 @@ module mkCoreW(RST_N_dm_power_on_reset, .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), - .master_bvalid(debug_module$master_bvalid), - .master_rvalid(debug_module$master_rvalid), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), @@ -3705,79 +4329,239 @@ module mkCoreW(RST_N_dm_power_on_reset, .FULL_N(ifcs_2_rspBack$FULL_N), .EMPTY_N(ifcs_2_rspBack$EMPTY_N)); - // submodule msNoSynth_0_b_buffer_ff - FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_0_b_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_0_b_buffer_ff$D_IN), - .ENQ(msNoSynth_0_b_buffer_ff$ENQ), - .DEQ(msNoSynth_0_b_buffer_ff$DEQ), - .CLR(msNoSynth_0_b_buffer_ff$CLR), - .D_OUT(msNoSynth_0_b_buffer_ff$D_OUT), - .FULL_N(msNoSynth_0_b_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_0_b_buffer_ff$EMPTY_N)); + // submodule merged_0_awff + FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_0_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_0_awff$D_IN), + .ENQ(merged_0_awff$ENQ), + .DEQ(merged_0_awff$DEQ), + .CLR(merged_0_awff$CLR), + .D_OUT(merged_0_awff$D_OUT), + .FULL_N(merged_0_awff$FULL_N), + .EMPTY_N(merged_0_awff$EMPTY_N)); - // submodule msNoSynth_0_b_buffer_firstValid + // submodule merged_0_wff + FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_0_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_0_wff$D_IN), + .ENQ(merged_0_wff$ENQ), + .DEQ(merged_0_wff$DEQ), + .CLR(merged_0_wff$CLR), + .D_OUT(merged_0_wff$D_OUT), + .FULL_N(merged_0_wff$FULL_N), + .EMPTY_N(merged_0_wff$EMPTY_N)); + + // submodule merged_1_awff + FIFO2 #(.width(32'd97), .guarded(32'd1)) merged_1_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_1_awff$D_IN), + .ENQ(merged_1_awff$ENQ), + .DEQ(merged_1_awff$DEQ), + .CLR(merged_1_awff$CLR), + .D_OUT(merged_1_awff$D_OUT), + .FULL_N(merged_1_awff$FULL_N), + .EMPTY_N(merged_1_awff$EMPTY_N)); + + // submodule merged_1_wff + FIFO2 #(.width(32'd74), .guarded(32'd1)) merged_1_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(merged_1_wff$D_IN), + .ENQ(merged_1_wff$ENQ), + .DEQ(merged_1_wff$DEQ), + .CLR(merged_1_wff$CLR), + .D_OUT(merged_1_wff$D_OUT), + .FULL_N(merged_1_wff$FULL_N), + .EMPTY_N(merged_1_wff$EMPTY_N)); + + // submodule msNoSynth_0_arNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_arNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_arNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_arNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_arNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_arNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_0_b_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_0_b_buffer_firstValid$D_IN), - .EN(msNoSynth_0_b_buffer_firstValid$EN), - .Q_OUT(msNoSynth_0_b_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_arNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_arNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_0_r_buffer_ff + // submodule msNoSynth_0_awNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_awNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_awNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_awNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_awNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_awNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_awNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_awNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_bNoSynth_buffer_ff + FIFO1 #(.width(32'd6), + .guarded(32'd0)) msNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_bNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_bNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_bNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_bNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_bNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_bNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_bNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), - .guarded(32'd0)) msNoSynth_0_r_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_0_r_buffer_ff$D_IN), - .ENQ(msNoSynth_0_r_buffer_ff$ENQ), - .DEQ(msNoSynth_0_r_buffer_ff$DEQ), - .CLR(msNoSynth_0_r_buffer_ff$CLR), - .D_OUT(msNoSynth_0_r_buffer_ff$D_OUT), - .FULL_N(msNoSynth_0_r_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_0_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) msNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_rNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_rNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_rNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_rNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_rNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_0_r_buffer_firstValid + // submodule msNoSynth_0_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_0_r_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_0_r_buffer_firstValid$D_IN), - .EN(msNoSynth_0_r_buffer_firstValid$EN), - .Q_OUT(msNoSynth_0_r_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_rNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_rNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_1_b_buffer_ff - FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_1_b_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_1_b_buffer_ff$D_IN), - .ENQ(msNoSynth_1_b_buffer_ff$ENQ), - .DEQ(msNoSynth_1_b_buffer_ff$DEQ), - .CLR(msNoSynth_1_b_buffer_ff$CLR), - .D_OUT(msNoSynth_1_b_buffer_ff$D_OUT), - .FULL_N(msNoSynth_1_b_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_1_b_buffer_ff$EMPTY_N)); + // submodule msNoSynth_0_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) msNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_wNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_0_wNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_0_wNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_0_wNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_0_wNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_1_b_buffer_firstValid + // submodule msNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_1_b_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_1_b_buffer_firstValid$D_IN), - .EN(msNoSynth_1_b_buffer_firstValid$EN), - .Q_OUT(msNoSynth_1_b_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_wNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_0_wNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule msNoSynth_1_r_buffer_ff + // submodule msNoSynth_1_arNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_arNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_arNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_arNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_arNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_arNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_arNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_arNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_arNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_awNoSynth_buffer_ff + FIFO1 #(.width(32'd97), + .guarded(32'd0)) msNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_awNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_awNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_awNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_awNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_awNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_awNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_awNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_bNoSynth_buffer_ff + FIFO1 #(.width(32'd6), + .guarded(32'd0)) msNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_bNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_bNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_bNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_bNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_bNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_bNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_bNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_rNoSynth_buffer_ff FIFO1 #(.width(32'd72), - .guarded(32'd0)) msNoSynth_1_r_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(msNoSynth_1_r_buffer_ff$D_IN), - .ENQ(msNoSynth_1_r_buffer_ff$ENQ), - .DEQ(msNoSynth_1_r_buffer_ff$DEQ), - .CLR(msNoSynth_1_r_buffer_ff$CLR), - .D_OUT(msNoSynth_1_r_buffer_ff$D_OUT), - .FULL_N(msNoSynth_1_r_buffer_ff$FULL_N), - .EMPTY_N(msNoSynth_1_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) msNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_rNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_rNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_rNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_rNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_rNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); - // submodule msNoSynth_1_r_buffer_firstValid + // submodule msNoSynth_1_rNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) msNoSynth_1_r_buffer_firstValid(.CLK(CLK), - .D_IN(msNoSynth_1_r_buffer_firstValid$D_IN), - .EN(msNoSynth_1_r_buffer_firstValid$EN), - .Q_OUT(msNoSynth_1_r_buffer_firstValid$Q_OUT)); + .init(1'd1)) msNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_rNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_rNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) msNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_wNoSynth_buffer_ff$D_IN), + .ENQ(msNoSynth_1_wNoSynth_buffer_ff$ENQ), + .DEQ(msNoSynth_1_wNoSynth_buffer_ff$DEQ), + .CLR(msNoSynth_1_wNoSynth_buffer_ff$CLR), + .D_OUT(msNoSynth_1_wNoSynth_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_wNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_wNoSynth_buffer_firstValid$D_IN), + .EN(msNoSynth_1_wNoSynth_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), @@ -3792,6 +4576,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), + .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), @@ -3802,12 +4587,14 @@ module mkCoreW(RST_N_dm_power_on_reset, .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), + .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wuser(plic$axi4_slave_wuser), + .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), @@ -3832,9 +4619,6 @@ module mkCoreW(RST_N_dm_power_on_reset, .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(), @@ -3868,6 +4652,7 @@ module mkCoreW(RST_N_dm_power_on_reset, .debug_module_mem_server_arqos(proc$debug_module_mem_server_arqos), .debug_module_mem_server_arregion(proc$debug_module_mem_server_arregion), .debug_module_mem_server_arsize(proc$debug_module_mem_server_arsize), + .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), .debug_module_mem_server_awaddr(proc$debug_module_mem_server_awaddr), .debug_module_mem_server_awburst(proc$debug_module_mem_server_awburst), .debug_module_mem_server_awcache(proc$debug_module_mem_server_awcache), @@ -3878,12 +4663,14 @@ module mkCoreW(RST_N_dm_power_on_reset, .debug_module_mem_server_awqos(proc$debug_module_mem_server_awqos), .debug_module_mem_server_awregion(proc$debug_module_mem_server_awregion), .debug_module_mem_server_awsize(proc$debug_module_mem_server_awsize), + .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wuser(proc$debug_module_mem_server_wuser), + .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), .hart0_csr_mem_server_request_put(proc$hart0_csr_mem_server_request_put), .hart0_fpr_mem_server_request_put(proc$hart0_fpr_mem_server_request_put), .hart0_gpr_mem_server_request_put(proc$hart0_gpr_mem_server_request_put), @@ -3894,22 +4681,16 @@ module mkCoreW(RST_N_dm_power_on_reset, .master0_awready(proc$master0_awready), .master0_bid(proc$master0_bid), .master0_bresp(proc$master0_bresp), + .master0_bvalid(proc$master0_bvalid), .master0_rdata(proc$master0_rdata), .master0_rid(proc$master0_rid), .master0_rlast(proc$master0_rlast), .master0_rresp(proc$master0_rresp), .master0_ruser(proc$master0_ruser), + .master0_rvalid(proc$master0_rvalid), .master0_wready(proc$master0_wready), - .master1_arready(proc$master1_arready), - .master1_awready(proc$master1_awready), - .master1_bid(proc$master1_bid), - .master1_bresp(proc$master1_bresp), - .master1_rdata(proc$master1_rdata), - .master1_rid(proc$master1_rid), - .master1_rlast(proc$master1_rlast), - .master1_rresp(proc$master1_rresp), - .master1_ruser(proc$master1_ruser), - .master1_wready(proc$master1_wready), + .master1_b_put_val(proc$master1_b_put_val), + .master1_r_put_val(proc$master1_r_put_val), .non_maskable_interrupt_req_set_not_clear(proc$non_maskable_interrupt_req_set_not_clear), .s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear), .set_verbosity_verbosity(proc$set_verbosity_verbosity), @@ -3918,14 +4699,12 @@ module mkCoreW(RST_N_dm_power_on_reset, .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), .EN_start(proc$EN_start), - .master0_bvalid(proc$master0_bvalid), - .master0_rvalid(proc$master0_rvalid), - .master1_bvalid(proc$master1_bvalid), - .master1_rvalid(proc$master1_rvalid), + .EN_master1_aw_drop(proc$EN_master1_aw_drop), + .EN_master1_w_drop(proc$EN_master1_w_drop), + .EN_master1_b_put(proc$EN_master1_b_put), + .EN_master1_ar_drop(proc$EN_master1_ar_drop), + .EN_master1_r_put(proc$EN_master1_r_put), .EN_set_verbosity(proc$EN_set_verbosity), - .debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid), - .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), - .debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid), .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), .EN_hart0_run_halt_server_response_get(proc$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(proc$EN_hart0_gpr_mem_server_request_put), @@ -3965,35 +4744,22 @@ module mkCoreW(RST_N_dm_power_on_reset, .master0_arregion(proc$master0_arregion), .master0_arvalid(proc$master0_arvalid), .master0_rready(proc$master0_rready), - .master1_awid(proc$master1_awid), - .master1_awaddr(proc$master1_awaddr), - .master1_awlen(proc$master1_awlen), - .master1_awsize(proc$master1_awsize), - .master1_awburst(proc$master1_awburst), - .master1_awlock(proc$master1_awlock), - .master1_awcache(proc$master1_awcache), - .master1_awprot(proc$master1_awprot), - .master1_awqos(proc$master1_awqos), - .master1_awregion(proc$master1_awregion), - .master1_awvalid(proc$master1_awvalid), - .master1_wdata(proc$master1_wdata), - .master1_wstrb(proc$master1_wstrb), - .master1_wlast(proc$master1_wlast), - .master1_wuser(), - .master1_wvalid(proc$master1_wvalid), - .master1_bready(proc$master1_bready), - .master1_arid(proc$master1_arid), - .master1_araddr(proc$master1_araddr), - .master1_arlen(proc$master1_arlen), - .master1_arsize(proc$master1_arsize), - .master1_arburst(proc$master1_arburst), - .master1_arlock(proc$master1_arlock), - .master1_arcache(proc$master1_arcache), - .master1_arprot(proc$master1_arprot), - .master1_arqos(proc$master1_arqos), - .master1_arregion(proc$master1_arregion), - .master1_arvalid(proc$master1_arvalid), - .master1_rready(proc$master1_rready), + .master1_aw_canPeek(proc$master1_aw_canPeek), + .master1_aw_peek(proc$master1_aw_peek), + .RDY_master1_aw_peek(proc$RDY_master1_aw_peek), + .RDY_master1_aw_drop(proc$RDY_master1_aw_drop), + .master1_w_canPeek(proc$master1_w_canPeek), + .master1_w_peek(proc$master1_w_peek), + .RDY_master1_w_peek(proc$RDY_master1_w_peek), + .RDY_master1_w_drop(proc$RDY_master1_w_drop), + .master1_b_canPut(proc$master1_b_canPut), + .RDY_master1_b_put(proc$RDY_master1_b_put), + .master1_ar_canPeek(proc$master1_ar_canPeek), + .master1_ar_peek(proc$master1_ar_peek), + .RDY_master1_ar_peek(proc$RDY_master1_ar_peek), + .RDY_master1_ar_drop(proc$RDY_master1_ar_drop), + .master1_r_canPut(proc$master1_r_canPut), + .RDY_master1_r_put(proc$RDY_master1_r_put), .RDY_set_verbosity(), .debug_module_mem_server_awready(proc$debug_module_mem_server_awready), .debug_module_mem_server_wready(proc$debug_module_mem_server_wready), @@ -4045,176 +4811,290 @@ module mkCoreW(RST_N_dm_power_on_reset, .m_mtvec_reset_value(), .m_nmivec_reset_value()); - // submodule ssNoSynth_0_ar_buffer_ff + // submodule ssNoSynth_0_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_0_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_0_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_ar_buffer_firstValid + // submodule ssNoSynth_0_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_0_aw_buffer_ff + // submodule ssNoSynth_0_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_0_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_0_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_aw_buffer_firstValid + // submodule ssNoSynth_0_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_0_w_buffer_ff + // submodule ssNoSynth_0_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_0_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_0_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_0_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_0_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_0_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_0_w_buffer_ff$DEQ), - .CLR(ssNoSynth_0_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_0_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_0_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_0_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_0_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_0_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_0_w_buffer_firstValid + // submodule ssNoSynth_0_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_0_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_0_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_0_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_0_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_0_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_ar_buffer_ff + // submodule ssNoSynth_1_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_1_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_1_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_ar_buffer_firstValid + // submodule ssNoSynth_1_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_aw_buffer_ff + // submodule ssNoSynth_1_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_1_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_1_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_aw_buffer_firstValid + // submodule ssNoSynth_1_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_1_w_buffer_ff + // submodule ssNoSynth_1_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_1_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_1_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_1_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_1_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_1_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_1_w_buffer_ff$DEQ), - .CLR(ssNoSynth_1_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_1_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_1_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_1_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_1_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_1_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_1_w_buffer_firstValid + // submodule ssNoSynth_1_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_1_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_1_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_1_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_1_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_1_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_ar_buffer_ff + // submodule ssNoSynth_2_arNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_2_ar_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_ar_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_ar_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_ar_buffer_ff$DEQ), - .CLR(ssNoSynth_2_ar_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_ar_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_ar_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_ar_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_arNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_arNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_arNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_arNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_arNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_arNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_ar_buffer_firstValid + // submodule ssNoSynth_2_arNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_ar_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_ar_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_ar_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_ar_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_arNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_aw_buffer_ff + // submodule ssNoSynth_2_awNoSynth_buffer_ff FIFO1 #(.width(32'd98), - .guarded(32'd0)) ssNoSynth_2_aw_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_aw_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_aw_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_aw_buffer_ff$DEQ), - .CLR(ssNoSynth_2_aw_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_aw_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_aw_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_aw_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_awNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_awNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_awNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_awNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_awNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_awNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_aw_buffer_firstValid + // submodule ssNoSynth_2_awNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_aw_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_aw_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_aw_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_aw_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_awNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule ssNoSynth_2_w_buffer_ff + // submodule ssNoSynth_2_bNoSynth_buffer_ff + FIFO1 #(.width(32'd7), + .guarded(32'd0)) ssNoSynth_2_bNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_bNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_bNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_bNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_bNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_bNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_bNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_rNoSynth_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_2_rNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_rNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_rNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_rNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_rNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_rNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_rNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_wNoSynth_buffer_ff FIFO1 #(.width(32'd74), - .guarded(32'd0)) ssNoSynth_2_w_buffer_ff(.RST(RST_N), - .CLK(CLK), - .D_IN(ssNoSynth_2_w_buffer_ff$D_IN), - .ENQ(ssNoSynth_2_w_buffer_ff$ENQ), - .DEQ(ssNoSynth_2_w_buffer_ff$DEQ), - .CLR(ssNoSynth_2_w_buffer_ff$CLR), - .D_OUT(ssNoSynth_2_w_buffer_ff$D_OUT), - .FULL_N(ssNoSynth_2_w_buffer_ff$FULL_N), - .EMPTY_N(ssNoSynth_2_w_buffer_ff$EMPTY_N)); + .guarded(32'd0)) ssNoSynth_2_wNoSynth_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_wNoSynth_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_wNoSynth_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_wNoSynth_buffer_ff$DEQ), + .CLR(ssNoSynth_2_wNoSynth_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_wNoSynth_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N)); - // submodule ssNoSynth_2_w_buffer_firstValid + // submodule ssNoSynth_2_wNoSynth_buffer_firstValid RevertReg #(.width(32'd1), - .init(1'd1)) ssNoSynth_2_w_buffer_firstValid(.CLK(CLK), - .D_IN(ssNoSynth_2_w_buffer_firstValid$D_IN), - .EN(ssNoSynth_2_w_buffer_firstValid$EN), - .Q_OUT(ssNoSynth_2_w_buffer_firstValid$Q_OUT)); + .init(1'd1)) ssNoSynth_2_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_wNoSynth_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule tagController_tmp_awreqff FIFO2 #(.width(32'd98), @@ -4259,77 +5139,100 @@ module mkCoreW(RST_N_dm_power_on_reset, .memory_response_canPut(), .RDY_memory_response_put(tagController_tmp_tagCon$RDY_memory_response_put)); - // submodule tmp0_b_buffer_ff - FIFO1 #(.width(32'd6), - .guarded(32'd0)) tmp0_b_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp0_b_buffer_ff$D_IN), - .ENQ(tmp0_b_buffer_ff$ENQ), - .DEQ(tmp0_b_buffer_ff$DEQ), - .CLR(tmp0_b_buffer_ff$CLR), - .D_OUT(tmp0_b_buffer_ff$D_OUT), - .FULL_N(tmp0_b_buffer_ff$FULL_N), - .EMPTY_N(tmp0_b_buffer_ff$EMPTY_N)); + // submodule tmp2_arNoSynth_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) tmp2_arNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_arNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_arNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_arNoSynth_buffer_ff$DEQ), + .CLR(tmp2_arNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_arNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_arNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_arNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp0_b_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp0_b_buffer_firstValid(.CLK(CLK), - .D_IN(tmp0_b_buffer_firstValid$D_IN), - .EN(tmp0_b_buffer_firstValid$EN), - .Q_OUT(tmp0_b_buffer_firstValid$Q_OUT)); + // submodule tmp2_arNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_arNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_arNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_arNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_arNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp0_r_buffer_ff - FIFO1 #(.width(32'd72), - .guarded(32'd0)) tmp0_r_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp0_r_buffer_ff$D_IN), - .ENQ(tmp0_r_buffer_ff$ENQ), - .DEQ(tmp0_r_buffer_ff$DEQ), - .CLR(tmp0_r_buffer_ff$CLR), - .D_OUT(tmp0_r_buffer_ff$D_OUT), - .FULL_N(tmp0_r_buffer_ff$FULL_N), - .EMPTY_N(tmp0_r_buffer_ff$EMPTY_N)); + // submodule tmp2_awNoSynth_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) tmp2_awNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_awNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_awNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_awNoSynth_buffer_ff$DEQ), + .CLR(tmp2_awNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_awNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_awNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_awNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp0_r_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp0_r_buffer_firstValid(.CLK(CLK), - .D_IN(tmp0_r_buffer_firstValid$D_IN), - .EN(tmp0_r_buffer_firstValid$EN), - .Q_OUT(tmp0_r_buffer_firstValid$Q_OUT)); + // submodule tmp2_awNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_awNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_awNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_awNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_awNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp2_b_buffer_ff + // submodule tmp2_bNoSynth_buffer_ff FIFO1 #(.width(32'd7), - .guarded(32'd0)) tmp2_b_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp2_b_buffer_ff$D_IN), - .ENQ(tmp2_b_buffer_ff$ENQ), - .DEQ(tmp2_b_buffer_ff$DEQ), - .CLR(tmp2_b_buffer_ff$CLR), - .D_OUT(tmp2_b_buffer_ff$D_OUT), - .FULL_N(tmp2_b_buffer_ff$FULL_N), - .EMPTY_N(tmp2_b_buffer_ff$EMPTY_N)); + .guarded(32'd0)) tmp2_bNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_bNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_bNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_bNoSynth_buffer_ff$DEQ), + .CLR(tmp2_bNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_bNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_bNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_bNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp2_b_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp2_b_buffer_firstValid(.CLK(CLK), - .D_IN(tmp2_b_buffer_firstValid$D_IN), - .EN(tmp2_b_buffer_firstValid$EN), - .Q_OUT(tmp2_b_buffer_firstValid$Q_OUT)); + // submodule tmp2_bNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_bNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_bNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_bNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_bNoSynth_buffer_firstValid$Q_OUT)); - // submodule tmp2_r_buffer_ff + // submodule tmp2_rNoSynth_buffer_ff FIFO1 #(.width(32'd73), - .guarded(32'd0)) tmp2_r_buffer_ff(.RST(hart0_reset$RST_OUT), - .CLK(CLK), - .D_IN(tmp2_r_buffer_ff$D_IN), - .ENQ(tmp2_r_buffer_ff$ENQ), - .DEQ(tmp2_r_buffer_ff$DEQ), - .CLR(tmp2_r_buffer_ff$CLR), - .D_OUT(tmp2_r_buffer_ff$D_OUT), - .FULL_N(tmp2_r_buffer_ff$FULL_N), - .EMPTY_N(tmp2_r_buffer_ff$EMPTY_N)); + .guarded(32'd0)) tmp2_rNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_rNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_rNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_rNoSynth_buffer_ff$DEQ), + .CLR(tmp2_rNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_rNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_rNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_rNoSynth_buffer_ff$EMPTY_N)); - // submodule tmp2_r_buffer_firstValid - RevertReg #(.width(32'd1), .init(1'd1)) tmp2_r_buffer_firstValid(.CLK(CLK), - .D_IN(tmp2_r_buffer_firstValid$D_IN), - .EN(tmp2_r_buffer_firstValid$EN), - .Q_OUT(tmp2_r_buffer_firstValid$Q_OUT)); + // submodule tmp2_rNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_rNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_rNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_rNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_rNoSynth_buffer_firstValid$Q_OUT)); + + // submodule tmp2_wNoSynth_buffer_ff + FIFO1 #(.width(32'd74), + .guarded(32'd0)) tmp2_wNoSynth_buffer_ff(.RST(hart0_reset$RST_OUT), + .CLK(CLK), + .D_IN(tmp2_wNoSynth_buffer_ff$D_IN), + .ENQ(tmp2_wNoSynth_buffer_ff$ENQ), + .DEQ(tmp2_wNoSynth_buffer_ff$DEQ), + .CLR(tmp2_wNoSynth_buffer_ff$CLR), + .D_OUT(tmp2_wNoSynth_buffer_ff$D_OUT), + .FULL_N(tmp2_wNoSynth_buffer_ff$FULL_N), + .EMPTY_N(tmp2_wNoSynth_buffer_ff$EMPTY_N)); + + // submodule tmp2_wNoSynth_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) tmp2_wNoSynth_buffer_firstValid(.CLK(CLK), + .D_IN(tmp2_wNoSynth_buffer_firstValid$D_IN), + .EN(tmp2_wNoSynth_buffer_firstValid$EN), + .Q_OUT(tmp2_wNoSynth_buffer_firstValid$Q_OUT)); // submodule uncached_mem_shim_arff FIFO2 #(.width(32'd98), @@ -4478,7 +5381,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst assign CAN_FIRE_RL_burst = ifcs_0_innerReq$EMPTY_N && ifcs_0_innerRoute$EMPTY_N && - state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556 ; + state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 ; assign WILL_FIRE_RL_burst = CAN_FIRE_RL_burst ; // rule RL_source_selected_1 @@ -4491,38 +5394,132 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_1 assign CAN_FIRE_RL_burst_1 = ifcs_1_innerReq$EMPTY_N && ifcs_1_innerRoute$EMPTY_N && - state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600 ; + state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 ; assign WILL_FIRE_RL_burst_1 = CAN_FIRE_RL_burst_1 ; - // rule __me_check_182 - assign CAN_FIRE___me_check_182 = 1'b1 ; - assign WILL_FIRE___me_check_182 = 1'b1 ; + // rule __me_check_355 + assign CAN_FIRE___me_check_355 = 1'b1 ; + assign WILL_FIRE___me_check_355 = 1'b1 ; - // rule __me_check_184 - assign CAN_FIRE___me_check_184 = 1'b1 ; - assign WILL_FIRE___me_check_184 = 1'b1 ; + // rule __me_check_357 + assign CAN_FIRE___me_check_357 = 1'b1 ; + assign WILL_FIRE___me_check_357 = 1'b1 ; // rule RL_sink_selected assign CAN_FIRE_RL_sink_selected = - IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425 && - flitToSink_0$whas ; + flitToSink_0$whas && + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 ; assign WILL_FIRE_RL_sink_selected = CAN_FIRE_RL_sink_selected ; // rule RL_sink_selected_1 assign CAN_FIRE_RL_sink_selected_1 = - IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426 && - flitToSink_1$whas ; + flitToSink_1$whas && + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 ; assign WILL_FIRE_RL_sink_selected_1 = CAN_FIRE_RL_sink_selected_1 ; // rule RL_sink_selected_2 assign CAN_FIRE_RL_sink_selected_2 = - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 && - flitToSink_2$whas ; + flitToSink_2$whas && + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 ; assign WILL_FIRE_RL_sink_selected_2 = CAN_FIRE_RL_sink_selected_2 ; - // rule __me_check_186 - assign CAN_FIRE___me_check_186 = 1'b1 ; - assign WILL_FIRE___me_check_186 = 1'b1 ; + // rule __me_check_359 + assign CAN_FIRE___me_check_359 = 1'b1 ; + assign WILL_FIRE___me_check_359 = 1'b1 ; + + // rule RL_checkSinkReady_3 + assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + + // rule RL_checkSinkReady_4 + assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + + // rule RL_craftReq_2 + assign CAN_FIRE_RL_craftReq_2 = + ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; + + // rule RL_craftReq_3 + assign CAN_FIRE_RL_craftReq_3 = + ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; + + // rule RL_craftReq_4 + assign CAN_FIRE_RL_craftReq_4 = + ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; + + // rule RL_arbitrate_1 + assign CAN_FIRE_RL_arbitrate_1 = + reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 && + !state_1 ; + assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; + + // rule RL_source_selected_2 + assign CAN_FIRE_RL_source_selected_2 = + (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_0$whas ; + assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; + + // rule RL_burst_2 + assign CAN_FIRE_RL_burst_2 = + ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 ; + assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; + + // rule RL_source_selected_3 + assign CAN_FIRE_RL_source_selected_3 = + (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_1$whas ; + assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; + + // rule RL_burst_3 + assign CAN_FIRE_RL_burst_3 = + ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 ; + assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; + + // rule __me_check_374 + assign CAN_FIRE___me_check_374 = 1'b1 ; + assign WILL_FIRE___me_check_374 = 1'b1 ; + + // rule RL_source_selected_4 + assign CAN_FIRE_RL_source_selected_4 = + (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_2$whas ; + assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; + + // rule RL_burst_4 + assign CAN_FIRE_RL_burst_4 = + ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && + state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 ; + assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; + + // rule __me_check_372 + assign CAN_FIRE___me_check_372 = 1'b1 ; + assign WILL_FIRE___me_check_372 = 1'b1 ; + + // rule __me_check_376 + assign CAN_FIRE___me_check_376 = 1'b1 ; + assign WILL_FIRE___me_check_376 = 1'b1 ; + + // rule RL_sink_selected_3 + assign CAN_FIRE_RL_sink_selected_3 = + flitToSink_1_0$whas && msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; + + // rule RL_sink_selected_4 + assign CAN_FIRE_RL_sink_selected_4 = + flitToSink_1_1$whas && msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; + + // rule __me_check_378 + assign CAN_FIRE___me_check_378 = 1'b1 ; + assign WILL_FIRE___me_check_378 = 1'b1 ; // rule RL_checkSinkReady_5 assign CAN_FIRE_RL_checkSinkReady_5 = 1'd1 ; @@ -4563,7 +5560,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_5 assign CAN_FIRE_RL_burst_5 = ifcs_0_1_innerReq$EMPTY_N && ifcs_0_1_innerRoute$EMPTY_N && - state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193 ; + state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 ; assign WILL_FIRE_RL_burst_5 = CAN_FIRE_RL_burst_5 ; // rule RL_source_selected_6 @@ -4576,92 +5573,205 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_burst_6 assign CAN_FIRE_RL_burst_6 = ifcs_1_1_innerReq$EMPTY_N && ifcs_1_1_innerRoute$EMPTY_N && - state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233 ; + state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 ; assign WILL_FIRE_RL_burst_6 = CAN_FIRE_RL_burst_6 ; - // rule __me_check_229 - assign CAN_FIRE___me_check_229 = 1'b1 ; - assign WILL_FIRE___me_check_229 = 1'b1 ; + // rule __me_check_414 + assign CAN_FIRE___me_check_414 = 1'b1 ; + assign WILL_FIRE___me_check_414 = 1'b1 ; - // rule __me_check_231 - assign CAN_FIRE___me_check_231 = 1'b1 ; - assign WILL_FIRE___me_check_231 = 1'b1 ; + // rule __me_check_416 + assign CAN_FIRE___me_check_416 = 1'b1 ; + assign WILL_FIRE___me_check_416 = 1'b1 ; // rule RL_sink_selected_5 assign CAN_FIRE_RL_sink_selected_5 = - ssNoSynth_0_ar_buffer_ff$FULL_N && flitToSink_1_0_1$whas ; + flitToSink_1_0_1$whas && ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_5 = CAN_FIRE_RL_sink_selected_5 ; // rule RL_sink_selected_6 assign CAN_FIRE_RL_sink_selected_6 = - ssNoSynth_1_ar_buffer_ff$FULL_N && flitToSink_1_1_1$whas ; + flitToSink_1_1_1$whas && ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_6 = CAN_FIRE_RL_sink_selected_6 ; // rule RL_sink_selected_7 assign CAN_FIRE_RL_sink_selected_7 = - ssNoSynth_2_ar_buffer_ff$FULL_N && flitToSink_1_2$whas ; + flitToSink_1_2$whas && ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; assign WILL_FIRE_RL_sink_selected_7 = CAN_FIRE_RL_sink_selected_7 ; - // rule __me_check_233 - assign CAN_FIRE___me_check_233 = 1'b1 ; - assign WILL_FIRE___me_check_233 = 1'b1 ; + // rule __me_check_418 + assign CAN_FIRE___me_check_418 = 1'b1 ; + assign WILL_FIRE___me_check_418 = 1'b1 ; + + // rule RL_checkSinkReady_8 + assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; + + // rule RL_checkSinkReady_9 + assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; + + // rule RL_craftReq_7 + assign CAN_FIRE_RL_craftReq_7 = + ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; + + // rule RL_craftReq_8 + assign CAN_FIRE_RL_craftReq_8 = + ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; + + // rule RL_craftReq_9 + assign CAN_FIRE_RL_craftReq_9 = + ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; + + // rule RL_arbitrate_3 + assign CAN_FIRE_RL_arbitrate_3 = + reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 && + !state_1_1_1 ; + assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; + + // rule RL_source_selected_7 + assign CAN_FIRE_RL_source_selected_7 = + (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; + + // rule RL_burst_7 + assign CAN_FIRE_RL_burst_7 = + ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 ; + assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; + + // rule RL_source_selected_8 + assign CAN_FIRE_RL_source_selected_8 = + (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_1_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; + + // rule RL_burst_8 + assign CAN_FIRE_RL_burst_8 = + ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 ; + assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; + + // rule __me_check_433 + assign CAN_FIRE___me_check_433 = 1'b1 ; + assign WILL_FIRE___me_check_433 = 1'b1 ; + + // rule RL_source_selected_9 + assign CAN_FIRE_RL_source_selected_9 = + (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_2$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; + + // rule RL_burst_9 + assign CAN_FIRE_RL_burst_9 = + ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && + state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 ; + assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; + + // rule __me_check_431 + assign CAN_FIRE___me_check_431 = 1'b1 ; + assign WILL_FIRE___me_check_431 = 1'b1 ; + + // rule __me_check_435 + assign CAN_FIRE___me_check_435 = 1'b1 ; + assign WILL_FIRE___me_check_435 = 1'b1 ; + + // rule RL_sink_selected_8 + assign CAN_FIRE_RL_sink_selected_8 = + flitToSink_1_1_0$whas && msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; + + // rule RL_sink_selected_9 + assign CAN_FIRE_RL_sink_selected_9 = + flitToSink_1_1_1_1$whas && + msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; + + // rule __me_check_437 + assign CAN_FIRE___me_check_437 = 1'b1 ; + assign WILL_FIRE___me_check_437 = 1'b1 ; // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_ug_uncached_mem_shim_master_u_aw_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + // rule RL_proc_uncached_awSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_awSynth_src_setPeek = + proc$RDY_master1_aw_peek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_setPeek = + proc$RDY_master1_aw_peek ; + + // rule RL_proc_uncached_wSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_wSynth_src_setPeek = + proc$RDY_master1_w_peek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_setPeek = + proc$RDY_master1_w_peek ; + + // rule RL_proc_uncached_arSynth_src_setPeek + assign CAN_FIRE_RL_proc_uncached_arSynth_src_setPeek = + proc$RDY_master1_ar_peek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_setPeek = + proc$RDY_master1_ar_peek ; + + // rule RL_uncached_mem_master_awSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_setPeek = uncached_mem_shim_awff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = - ug_uncached_mem_shim_master_u_aw_dropWire$whas && + // rule RL_uncached_mem_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = + uncached_mem_master_awSynth_src_dropWire$whas && !uncached_mem_shim_awff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_w_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + // rule RL_uncached_mem_master_wSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_setPeek = uncached_mem_shim_wff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_w_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = - ug_uncached_mem_shim_master_u_w_dropWire$whas && + // rule RL_uncached_mem_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = + uncached_mem_master_wSynth_src_dropWire$whas && !uncached_mem_shim_wff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_b_warnDoPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = - ug_uncached_mem_shim_master_u_b_putWire$whas && + // rule RL_uncached_mem_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = + uncached_mem_master_bSynth_snk_putWire$whas && !uncached_mem_shim_bff$FULL_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut ; - // rule RL_ug_uncached_mem_shim_master_u_ar_setPeek - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + // rule RL_uncached_mem_master_arSynth_src_setPeek + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_setPeek = + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_setPeek = uncached_mem_shim_arff$EMPTY_N ; - // rule RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = - ug_uncached_mem_shim_master_u_ar_dropWire$whas && + // rule RL_uncached_mem_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = + uncached_mem_master_arSynth_src_dropWire$whas && !uncached_mem_shim_arff$EMPTY_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_r_warnDoPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = - ug_uncached_mem_shim_master_u_r_putWire$whas && + // rule RL_uncached_mem_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = + uncached_mem_master_rSynth_snk_putWire$whas && !uncached_mem_shim_rff$FULL_N ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut ; // rule RL_tagController_tmp_passCacheResponse assign CAN_FIRE_RL_tagController_tmp_passCacheResponse = @@ -4699,113 +5809,176 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_setPeek ; - // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = - tagController_tmp_ug_master_u_aw_dropWire$whas && - !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; - - // rule RL_tagController_tmp_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = - tagController_tmp_shimMaster_awff_rv$port1__read[99] && - tagController_tmp_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; - // rule RL_tagController_tmp_ug_master_u_w_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = tagController_tmp_shimMaster_wff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_w_setPeek ; - // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = - tagController_tmp_ug_master_u_w_dropWire$whas && - !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; - - // rule RL_tagController_tmp_ug_master_u_w_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = - tagController_tmp_shimMaster_wff_rv$port1__read[73] && - tagController_tmp_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; - - // rule RL_tagController_tmp_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = - tagController_tmp_ug_master_u_b_putWire$whas && - tagController_tmp_shimMaster_bff_rv[8] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; - - // rule RL_tagController_tmp_ug_master_u_b_doPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = - !tagController_tmp_shimMaster_bff_rv[8] && - tagController_tmp_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; - // rule RL_tagController_tmp_ug_master_u_ar_setPeek assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = tagController_tmp_shimMaster_arff_rv$port1__read[99] ; assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek = CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_setPeek ; - // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = - tagController_tmp_ug_master_u_ar_dropWire$whas && - !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; + // rule RL_tmp2_awNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit = + proc$master0_awvalid && tmp2_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; - // rule RL_tagController_tmp_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = - tagController_tmp_shimMaster_arff_rv$port1__read[99] && - tagController_tmp_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = - CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; + // rule RL_tmp2_awNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_awNoSynth_forwardReady = 1'd1 ; - // rule RL_tagController_tmp_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = - tagController_tmp_ug_master_u_r_putWire$whas && - tagController_tmp_shimMaster_rff_rv[73] ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; + // rule RL_tmp2_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit && + !tmp2_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut ; - // rule RL_tagController_tmp_ug_master_u_r_doPut - assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = - !tagController_tmp_shimMaster_rff_rv[73] && - tagController_tmp_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = - CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; + // rule RL_tmp2_awNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut = + tmp2_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_awNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut ; - // rule RL_tagController_tmp_passMemoryResponseWrite - assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = - tagController_tmp_shimMaster_bff_rv$port1__read[8] && - tagController_tmp_tagCon$RDY_memory_response_put ; - assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = - CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && - !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + // rule RL_tmp2_wNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit = + proc$master0_wvalid && tmp2_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; - // rule RL_tagController_tmp_passMemoryResponseRead - assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = - tagController_tmp_shimMaster_rff_rv$port1__read[73] && - tagController_tmp_tagCon$RDY_memory_response_put ; - assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = - CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + // rule RL_tmp2_wNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_wNoSynth_forwardReady = 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = - !tagController_tmp_shimSlave_awff_rv[98] && - proc$master0_awvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + // rule RL_tmp2_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit && + !tmp2_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut ; + + // rule RL_tmp2_wNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut = + tmp2_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_wNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut ; + + // rule RL_tmp2_bNoSynth_dropFlit + assign CAN_FIRE_RL_tmp2_bNoSynth_dropFlit = + tmp2_bNoSynth_buffer_ff$EMPTY_N && proc$master0_bready ; + assign WILL_FIRE_RL_tmp2_bNoSynth_dropFlit = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit ; + + // rule RL_tmp2_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && + !tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop ; + + // rule RL_tmp2_arNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit = + proc$master0_arvalid && tmp2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_forwardFlit = + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; + + // rule RL_tmp2_arNoSynth_forwardReady + assign CAN_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_tmp2_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_tmp2_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit && + !tmp2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut ; + + // rule RL_tmp2_arNoSynth_snk_doPut + assign CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut = + tmp2_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_tmp2_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_tmp2_arNoSynth_snk_doPut = + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut ; + + // rule RL_tmp2_rNoSynth_dropFlit + assign CAN_FIRE_RL_tmp2_rNoSynth_dropFlit = + tmp2_rNoSynth_buffer_ff$EMPTY_N && proc$master0_rready ; + assign WILL_FIRE_RL_tmp2_rNoSynth_dropFlit = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit ; + + // rule RL_tmp2_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && + !tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = + tmp2_awNoSynth_buffer_firstValid$Q_OUT && + (tmp2_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_setPeek ; + + // rule RL_Prelude_inst_changeSpecialWires_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + !tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; + + // rule RL_tmp2_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop || + tmp2_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; + + // rule RL_tmp2_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop && + tmp2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && + tagController_tmp_shimSlave_awff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = + tmp2_awNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_awff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_aw_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut && tagController_tmp_shimSlave_awff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut ; @@ -4813,7 +5986,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_aw_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = !tagController_tmp_shimSlave_awff_rv[98] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_aw_doPut ; @@ -4824,19 +5997,66 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_getCacheAW = CAN_FIRE_RL_tagController_tmp_getCacheAW ; - // rule RL_tmp2_aw_forwardReady - assign CAN_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_aw_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = + tmp2_wNoSynth_buffer_firstValid$Q_OUT && + (tmp2_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_setPeek ; - // rule RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = - !tagController_tmp_shimSlave_wff_rv[74] && proc$master0_wvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + // rule RL_Prelude_inst_changeSpecialWires_1_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + !tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; + + // rule RL_tmp2_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop || + tmp2_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; + + // rule RL_tmp2_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop && + tmp2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && + tagController_tmp_shimSlave_wff_rv[74] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = + tmp2_wNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_wff_rv[74] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_w_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut && tagController_tmp_shimSlave_wff_rv[74] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut ; @@ -4844,24 +6064,39 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_w_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = !tagController_tmp_shimSlave_wff_rv[74] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_w_doPut ; - // rule RL_tmp2_w_forwardReady - assign CAN_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_w_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_setPeek = + 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = + // rule RL_Prelude_inst_changeSpecialWires_2_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = tagController_tmp_shimSlave_bff_rv$port1__read[7] && - tmp2_b_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + tmp2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; + + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + tagController_tmp_shimSlave_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_b_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop && !tagController_tmp_shimSlave_bff_rv$port1__read[7] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop ; @@ -4869,47 +6104,118 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_b_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = tagController_tmp_shimSlave_bff_rv$port1__read[7] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_b_doDrop ; - // rule RL_tmp2_b_forwardFlit - assign CAN_FIRE_RL_tmp2_b_forwardFlit = - tmp2_b_buffer_firstValid$Q_OUT && - (tmp2_b_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) ; - assign WILL_FIRE_RL_tmp2_b_forwardFlit = CAN_FIRE_RL_tmp2_b_forwardFlit ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect && + !tmp2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut ; - // rule RL_tmp2_b_dropFlit - assign CAN_FIRE_RL_tmp2_b_dropFlit = - (tmp2_b_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut) && - proc$master0_bready ; - assign WILL_FIRE_RL_tmp2_b_dropFlit = CAN_FIRE_RL_tmp2_b_dropFlit ; + // rule RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = + tmp2_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_connect ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut ; - // rule RL_tmp2_b_buffer_enqueue - assign CAN_FIRE_RL_tmp2_b_buffer_enqueue = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_mkConnectionGetPut && - (!CAN_FIRE_RL_tmp2_b_dropFlit || tmp2_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp2_b_buffer_enqueue = - CAN_FIRE_RL_tmp2_b_buffer_enqueue ; + // rule RL_tmp2_bNoSynth_src_setPeek + assign CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek = + tmp2_bNoSynth_buffer_firstValid$Q_OUT && + (tmp2_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut) ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_setPeek = + CAN_FIRE_RL_tmp2_bNoSynth_src_setPeek ; - // rule RL_tmp2_b_buffer_dequeue - assign CAN_FIRE_RL_tmp2_b_buffer_dequeue = - CAN_FIRE_RL_tmp2_b_dropFlit && tmp2_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp2_b_buffer_dequeue = - CAN_FIRE_RL_tmp2_b_buffer_dequeue ; + // rule RL_tmp2_bNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_tmp2_bNoSynth_forwardFlit = 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = - !tagController_tmp_shimSlave_arff_rv[98] && - proc$master0_arvalid ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + // rule RL_tmp2_bNoSynth_src_doDrop + assign CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_bNoSynth_dropFlit && + tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; + + // rule RL_tmp2_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_doPut && + (!CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop || + tmp2_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; + + // rule RL_tmp2_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop && + tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = + tmp2_arNoSynth_buffer_firstValid$Q_OUT && + (tmp2_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_setPeek ; + + // rule RL_Prelude_inst_changeSpecialWires_3_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + !tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; + + // rule RL_tmp2_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_arNoSynth_snk_doPut && + (!CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop || + tmp2_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; + + // rule RL_tmp2_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop && + tmp2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && + tagController_tmp_shimSlave_arff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut ; + + // rule RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = + tmp2_arNoSynth_buffer_ff$EMPTY_N && + !tagController_tmp_shimSlave_arff_rv[98] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; // rule RL_tagController_tmp_ug_slave_u_ar_warnDoPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut && tagController_tmp_shimSlave_arff_rv[98] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut ; @@ -4917,7 +6223,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_ar_doPut assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = !tagController_tmp_shimSlave_arff_rv[98] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_doPut ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut = CAN_FIRE_RL_tagController_tmp_ug_slave_u_ar_doPut ; @@ -4937,20 +6243,35 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_tagController_tmp_passCacheRead = CAN_FIRE_RL_tagController_tmp_passCacheRead ; - // rule RL_tmp2_ar_forwardReady - assign CAN_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp2_ar_forwardReady = 1'd1 ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_setPeek = + 1'd1 ; - // rule RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut - assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = + // rule RL_Prelude_inst_changeSpecialWires_4_connect + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = tagController_tmp_shimSlave_rff_rv$port1__read[73] && - tmp2_r_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + tmp2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; + + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop ; + + // rule RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + tagController_tmp_shimSlave_rff_rv$port1__read[73] ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; // rule RL_tagController_tmp_ug_slave_u_r_warnDoDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop && !tagController_tmp_shimSlave_rff_rv$port1__read[73] ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop ; @@ -4958,1182 +6279,1319 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_tagController_tmp_ug_slave_u_r_doDrop assign CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = tagController_tmp_shimSlave_rff_rv$port1__read[73] && - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut ; + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_doDrop ; assign WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop = CAN_FIRE_RL_tagController_tmp_ug_slave_u_r_doDrop ; - // rule RL_tagController_tmp_propagateReset - assign CAN_FIRE_RL_tagController_tmp_propagateReset = - !tagController_tmp_reset_done ; - assign WILL_FIRE_RL_tagController_tmp_propagateReset = - CAN_FIRE_RL_tagController_tmp_propagateReset ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect && + !tmp2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut ; - // rule RL_tmp2_r_forwardFlit - assign CAN_FIRE_RL_tmp2_r_forwardFlit = - tmp2_r_buffer_firstValid$Q_OUT && - (tmp2_r_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) ; - assign WILL_FIRE_RL_tmp2_r_forwardFlit = CAN_FIRE_RL_tmp2_r_forwardFlit ; + // rule RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut + assign CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = + tmp2_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_connect ; + assign WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut ; - // rule RL_tmp2_r_dropFlit - assign CAN_FIRE_RL_tmp2_r_dropFlit = - (tmp2_r_buffer_ff$EMPTY_N || - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut) && - proc$master0_rready ; - assign WILL_FIRE_RL_tmp2_r_dropFlit = CAN_FIRE_RL_tmp2_r_dropFlit ; + // rule RL_tmp2_rNoSynth_src_setPeek + assign CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek = + tmp2_rNoSynth_buffer_firstValid$Q_OUT && + (tmp2_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut) ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_setPeek = + CAN_FIRE_RL_tmp2_rNoSynth_src_setPeek ; - // rule RL_tmp2_r_buffer_enqueue - assign CAN_FIRE_RL_tmp2_r_buffer_enqueue = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_mkConnectionGetPut && - (!CAN_FIRE_RL_tmp2_r_dropFlit || tmp2_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp2_r_buffer_enqueue = - CAN_FIRE_RL_tmp2_r_buffer_enqueue ; + // rule RL_tmp2_rNoSynth_forwardFlit + assign CAN_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_tmp2_rNoSynth_forwardFlit = 1'd1 ; - // rule RL_tmp2_r_buffer_dequeue - assign CAN_FIRE_RL_tmp2_r_buffer_dequeue = - CAN_FIRE_RL_tmp2_r_dropFlit && tmp2_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp2_r_buffer_dequeue = - CAN_FIRE_RL_tmp2_r_buffer_dequeue ; + // rule RL_tmp2_rNoSynth_src_doDrop + assign CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_rNoSynth_dropFlit && + tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_src_doDrop = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; - // rule RL_ssNoSynth_0_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit = - !uncached_mem_shim_arff$FULL_N || - ssNoSynth_0_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_0_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_5) && - uncached_mem_shim_arff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + // rule RL_tmp2_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_doPut && + (!CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop || + tmp2_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; - // rule RL_ssNoSynth_0_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit = - (ssNoSynth_0_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_5) && - uncached_mem_shim_arff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit ; + // rule RL_tmp2_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop && + tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_tmp2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; - // rule RL_ug_uncached_mem_shim_master_u_ar_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = - uncached_mem_shim_arff$EMPTY_N && - ug_uncached_mem_shim_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + // rule RL_slave_vector_0_bSynth_src_setPeek + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_setPeek = + uncached_mem_shim_bff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_setPeek = + uncached_mem_shim_bff$EMPTY_N ; - // rule RL_ssNoSynth_0_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_5 && - (!WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit || - ssNoSynth_0_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + // rule RL_slave_vector_0_rSynth_src_setPeek + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_setPeek = + uncached_mem_shim_rff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_setPeek = + uncached_mem_shim_rff$EMPTY_N ; - // rule RL_ssNoSynth_0_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit && - ssNoSynth_0_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + // rule RL_msNoSynth_0_awNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = + proc$master1_aw_canPeek && + msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; - // rule RL_ssNoSynth_1_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit = - ssNoSynth_1_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_1_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_6) ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; + // rule RL_msNoSynth_0_awNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_1_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit = - (ssNoSynth_1_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_6) && - plic$axi4_slave_arready ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + // rule RL_proc_uncached_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + !proc$master1_aw_canPeek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_6 && - (!CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit || - ssNoSynth_1_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + // rule RL_proc_uncached_awSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop = + proc$RDY_master1_aw_drop && + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + proc$master1_aw_canPeek ; + assign WILL_FIRE_RL_proc_uncached_awSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; - // rule RL_ssNoSynth_1_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit && - ssNoSynth_1_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + // rule RL_msNoSynth_0_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit && + !msNoSynth_0_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut ; - // rule RL_ssNoSynth_2_ar_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit = - ssNoSynth_2_ar_buffer_firstValid$Q_OUT && - (ssNoSynth_2_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_7) ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + // rule RL_msNoSynth_0_awNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = + msNoSynth_0_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut ; - // rule RL_ssNoSynth_2_ar_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit = - (ssNoSynth_2_ar_buffer_ff$EMPTY_N || - CAN_FIRE_RL_sink_selected_7) && - proc$debug_module_mem_server_arready ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + // rule RL_msNoSynth_0_wNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = + proc$master1_w_canPeek && msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; - // rule RL_ssNoSynth_2_ar_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = - CAN_FIRE_RL_sink_selected_7 && - (!CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit || - ssNoSynth_2_ar_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + // rule RL_msNoSynth_0_wNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_2_ar_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit && - ssNoSynth_2_ar_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + // rule RL_proc_uncached_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + !proc$master1_w_canPeek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop ; - // rule RL_split_0_putFirst - assign CAN_FIRE_RL_split_0_putFirst = - split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 && - split_0_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + // rule RL_proc_uncached_wSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop = + proc$RDY_master1_w_drop && + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + proc$master1_w_canPeek ; + assign WILL_FIRE_RL_proc_uncached_wSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; - // rule RL_ssNoSynth_0_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit = - !uncached_mem_shim_awff$FULL_N || - ssNoSynth_0_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_0_aw_buffer_ff$EMPTY_N || - MUX_split_0_flitLeft$write_1__SEL_2) && + // rule RL_msNoSynth_0_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit && + !msNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_0_wNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = + msNoSynth_0_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && proc$master1_b_canPut ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; + + // rule RL_msNoSynth_0_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + !msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_0_arNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = + proc$master1_ar_canPeek && + msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; + + // rule RL_msNoSynth_0_arNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_proc_uncached_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + !proc$master1_ar_canPeek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop = + CAN_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop ; + + // rule RL_proc_uncached_arSynth_src_doDrop + assign CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop = + proc$RDY_master1_ar_drop && + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + proc$master1_ar_canPeek ; + assign WILL_FIRE_RL_proc_uncached_arSynth_src_doDrop = + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; + + // rule RL_msNoSynth_0_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit && + !msNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_0_arNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = + msNoSynth_0_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_0_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && proc$master1_r_canPut ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; + + // rule RL_msNoSynth_0_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + !msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_1_bNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + debug_module$master_bready ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit ; + + // rule RL_msNoSynth_1_bNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && + !msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop ; + + // rule RL_msNoSynth_1_rNoSynth_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + debug_module$master_rready ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit ; + + // rule RL_msNoSynth_1_rNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && + !msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_0_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_awff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_0_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit = - (ssNoSynth_0_aw_buffer_ff$EMPTY_N || - MUX_split_0_flitLeft$write_1__SEL_2) && - uncached_mem_shim_awff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit ; + // rule RL_ssNoSynth_0_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + !ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_aw_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = - uncached_mem_shim_awff$EMPTY_N && - ug_uncached_mem_shim_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; - - // rule RL_ssNoSynth_0_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = - MUX_split_0_flitLeft$write_1__SEL_2 && - (!WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit || - ssNoSynth_0_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; - - // rule RL_ssNoSynth_0_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit && - ssNoSynth_0_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; - - // rule RL_split_0_putOther - assign CAN_FIRE_RL_split_0_putOther = - CAN_FIRE_RL_sink_selected && - (!split_0_doPut$wget[172] || ssNoSynth_0_w_buffer_ff$FULL_N) && - split_0_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; - - // rule RL_ssNoSynth_0_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit = - !uncached_mem_shim_wff$FULL_N || - ssNoSynth_0_w_buffer_firstValid$Q_OUT && - (ssNoSynth_0_w_buffer_ff$EMPTY_N || - ssNoSynth_0_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_0_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N && uncached_mem_shim_wff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit && - !WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_0_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_0_w_dropFlit = - (ssNoSynth_0_w_buffer_ff$EMPTY_N || - ssNoSynth_0_w_buffer_enqw$whas) && - uncached_mem_shim_wff$FULL_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_0_w_dropFlit && - !WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit ; + // rule RL_ssNoSynth_0_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + !ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop ; - // rule RL_ug_uncached_mem_shim_master_u_w_doDrop - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = - uncached_mem_shim_wff$EMPTY_N && - ug_uncached_mem_shim_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + // rule RL_ssNoSynth_0_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = + uncached_mem_shim_bff$EMPTY_N && + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; - // rule RL_ssNoSynth_0_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = - ssNoSynth_0_w_buffer_enqw$whas && - (!WILL_FIRE_RL_ssNoSynth_0_w_dropFlit || - ssNoSynth_0_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + // rule RL_ssNoSynth_0_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_0_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit && - ssNoSynth_0_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + // rule RL_slave_vector_0_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && + !uncached_mem_shim_bff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop = + CAN_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop ; - // rule RL_split_1_putFirst - assign CAN_FIRE_RL_split_1_putFirst = - split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 && - split_1_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + // rule RL_slave_vector_0_bSynth_src_doDrop + assign CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop = + uncached_mem_shim_bff$EMPTY_N && + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_slave_vector_0_bSynth_src_doDrop = + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; - // rule RL_ssNoSynth_1_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit = - ssNoSynth_1_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_1_aw_buffer_ff$EMPTY_N || - MUX_split_1_flitLeft$write_1__SEL_2) ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + // rule RL_uncached_mem_master_bSynth_snk_doPut + assign CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = + uncached_mem_shim_bff$FULL_N && + uncached_mem_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_bSynth_snk_doPut = + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; - // rule RL_ssNoSynth_1_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit = - (ssNoSynth_1_aw_buffer_ff$EMPTY_N || - MUX_split_1_flitLeft$write_1__SEL_2) && + // rule RL_ssNoSynth_0_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit && + !ssNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_0_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = + ssNoSynth_0_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_0_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + !ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_0_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = + uncached_mem_shim_rff$EMPTY_N && + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_0_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_slave_vector_0_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && + !uncached_mem_shim_rff$EMPTY_N ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop = + CAN_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop ; + + // rule RL_slave_vector_0_rSynth_src_doDrop + assign CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop = + uncached_mem_shim_rff$EMPTY_N && + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_slave_vector_0_rSynth_src_doDrop = + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; + + // rule RL_uncached_mem_master_rSynth_snk_doPut + assign CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = + uncached_mem_shim_rff$FULL_N && + uncached_mem_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_rSynth_snk_doPut = + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit && + !ssNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_0_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = + ssNoSynth_0_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_1_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_awready ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_1_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = - MUX_split_1_flitLeft$write_1__SEL_2 && - (!CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit || - ssNoSynth_1_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + // rule RL_ssNoSynth_1_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && + !ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit && - ssNoSynth_1_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; - - // rule RL_split_1_putOther - assign CAN_FIRE_RL_split_1_putOther = - CAN_FIRE_RL_sink_selected_1 && - (!split_1_doPut$wget[172] || ssNoSynth_1_w_buffer_ff$FULL_N) && - split_1_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; - - // rule RL_ssNoSynth_1_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit = - ssNoSynth_1_w_buffer_firstValid$Q_OUT && - (ssNoSynth_1_w_buffer_ff$EMPTY_N || - ssNoSynth_1_w_buffer_enqw$whas) ; - assign WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; - - // rule RL_ssNoSynth_1_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_1_w_dropFlit = - (ssNoSynth_1_w_buffer_ff$EMPTY_N || - ssNoSynth_1_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_1_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N && plic$axi4_slave_wready ; - assign WILL_FIRE_RL_ssNoSynth_1_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_1_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = - ssNoSynth_1_w_buffer_enqw$whas && - (!CAN_FIRE_RL_ssNoSynth_1_w_dropFlit || - ssNoSynth_1_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + // rule RL_ssNoSynth_1_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && + !ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_1_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit && - ssNoSynth_1_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + // rule RL_ssNoSynth_1_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = + plic$axi4_slave_bvalid && ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; - // rule RL_split_2_putFirst - assign CAN_FIRE_RL_split_2_putFirst = - split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 && - split_2_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + // rule RL_ssNoSynth_1_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_forwardReady = 1'd1 ; - // rule RL_ssNoSynth_2_aw_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit = - ssNoSynth_2_aw_buffer_firstValid$Q_OUT && - (ssNoSynth_2_aw_buffer_ff$EMPTY_N || - MUX_split_2_flitLeft$write_1__SEL_2) ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + // rule RL_ssNoSynth_1_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit && + !ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut ; - // rule RL_ssNoSynth_2_aw_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit = - (ssNoSynth_2_aw_buffer_ff$EMPTY_N || - MUX_split_2_flitLeft$write_1__SEL_2) && + // rule RL_ssNoSynth_1_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = + ssNoSynth_1_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_1_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + plic$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_1_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && + !ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop ; + + // rule RL_ssNoSynth_1_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = + plic$axi4_slave_rvalid && ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_1_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_1_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit && + !ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_1_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = + ssNoSynth_1_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_2_awNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_awready ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit ; - // rule RL_ssNoSynth_2_aw_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = - MUX_split_2_flitLeft$write_1__SEL_2 && - (!CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit || - ssNoSynth_2_aw_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + // rule RL_ssNoSynth_2_awNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && + !ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_2_aw_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit && - ssNoSynth_2_aw_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; - - // rule RL_split_2_putOther - assign CAN_FIRE_RL_split_2_putOther = - CAN_FIRE_RL_sink_selected_2 && - (!split_2_doPut$wget[172] || ssNoSynth_2_w_buffer_ff$FULL_N) && - split_2_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; - - // rule RL_ssNoSynth_2_w_forwardFlit - assign CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit = - ssNoSynth_2_w_buffer_firstValid$Q_OUT && - (ssNoSynth_2_w_buffer_ff$EMPTY_N || - ssNoSynth_2_w_buffer_enqw$whas) ; - assign WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit = - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; - - // rule RL_ssNoSynth_2_w_dropFlit - assign CAN_FIRE_RL_ssNoSynth_2_w_dropFlit = - (ssNoSynth_2_w_buffer_ff$EMPTY_N || - ssNoSynth_2_w_buffer_enqw$whas) && + // rule RL_ssNoSynth_2_wNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N && proc$debug_module_mem_server_wready ; - assign WILL_FIRE_RL_ssNoSynth_2_w_dropFlit = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit ; - // rule RL_ssNoSynth_2_w_buffer_enqueue - assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = - ssNoSynth_2_w_buffer_enqw$whas && - (!CAN_FIRE_RL_ssNoSynth_2_w_dropFlit || - ssNoSynth_2_w_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + // rule RL_ssNoSynth_2_wNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && + !ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop ; - // rule RL_ssNoSynth_2_w_buffer_dequeue - assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit && - ssNoSynth_2_w_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + // rule RL_ssNoSynth_2_arNoSynth_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N && + proc$debug_module_mem_server_arready ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit ; + + // rule RL_ssNoSynth_2_arNoSynth_src_warnDoDrop + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && + !ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop ; + + // rule RL_merged_0_passFlit + assign CAN_FIRE_RL_merged_0_passFlit = + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_passFlit = CAN_FIRE_RL_merged_0_passFlit ; + + // rule RL_merged_1_passFlit + assign CAN_FIRE_RL_merged_1_passFlit = + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_passFlit = CAN_FIRE_RL_merged_1_passFlit ; // rule RL_ifcs_0_firstFlit assign CAN_FIRE_RL_ifcs_0_firstFlit = - proc$master1_wvalid && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && ifcs_0_innerRoute$FULL_N && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd0 && - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 == + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit = CAN_FIRE_RL_ifcs_0_firstFlit ; // rule RL_ifcs_0_followFlits assign CAN_FIRE_RL_ifcs_0_followFlits = - proc$master1_wvalid && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && ifcs_0_innerReq$FULL_N && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_followFlits = CAN_FIRE_RL_ifcs_0_followFlits ; // rule RL_ifcs_0_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_nonRoutableFlit = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250 && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + (!CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171] || + !ifcs_0_noRoute_inner_pendingReq) && ifcs_0_state == 2'd0 && - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 != + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_nonRoutableFlit ; // rule RL_ifcs_0_drainFlits assign CAN_FIRE_RL_ifcs_0_drainFlits = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - proc$master1_wvalid && + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) && ifcs_0_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_drainFlits = CAN_FIRE_RL_ifcs_0_drainFlits ; - // rule __me_check_158 - assign CAN_FIRE___me_check_158 = 1'b1 ; - assign WILL_FIRE___me_check_158 = 1'b1 ; + // rule __me_check_325 + assign CAN_FIRE___me_check_325 = 1'b1 ; + assign WILL_FIRE___me_check_325 = 1'b1 ; - // rule RL_ifcs_0_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = - msNoSynth_0_b_buffer_ff$FULL_N && ifcs_0_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + // rule RL_ifcs_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_firstFlit = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_innerReq$FULL_N && + ifcs_1_innerRoute$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; - // rule RL_checkSinkReady_3 - assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + // rule RL_ifcs_1_followFlits + assign CAN_FIRE_RL_ifcs_1_followFlits = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_innerReq$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; - // rule RL_ifcs_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = - msNoSynth_1_b_buffer_ff$FULL_N && ifcs_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + // rule RL_ifcs_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + (!CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171] || + !ifcs_1_noRoute_inner_pendingReq) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; - // rule RL_checkSinkReady_4 - assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + // rule RL_ifcs_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_drainFlits = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) && + ifcs_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; - // rule RL_craftReq_2 - assign CAN_FIRE_RL_craftReq_2 = - ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; - - // rule RL_craftReq_3 - assign CAN_FIRE_RL_craftReq_3 = - ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; - - // rule RL_craftReq_4 - assign CAN_FIRE_RL_craftReq_4 = - ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; - - // rule RL_arbitrate_1 - assign CAN_FIRE_RL_arbitrate_1 = - reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669 && - !state_1 ; - assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; - - // rule RL_source_selected_2 - assign CAN_FIRE_RL_source_selected_2 = - (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_0$whas ; - assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; - - // rule RL_burst_2 - assign CAN_FIRE_RL_burst_2 = - ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761 ; - assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; - - // rule RL_source_selected_3 - assign CAN_FIRE_RL_source_selected_3 = - (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_1$whas ; - assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; - - // rule RL_burst_3 - assign CAN_FIRE_RL_burst_3 = - ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794 ; - assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; - - // rule __me_check_197 - assign CAN_FIRE___me_check_197 = 1'b1 ; - assign WILL_FIRE___me_check_197 = 1'b1 ; - - // rule RL_source_selected_4 - assign CAN_FIRE_RL_source_selected_4 = - (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && - !state_1 && - sourceSelect_1_2$whas ; - assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; - - // rule RL_burst_4 - assign CAN_FIRE_RL_burst_4 = - ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && - state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828 ; - assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; - - // rule __me_check_195 - assign CAN_FIRE___me_check_195 = 1'b1 ; - assign WILL_FIRE___me_check_195 = 1'b1 ; - - // rule __me_check_199 - assign CAN_FIRE___me_check_199 = 1'b1 ; - assign WILL_FIRE___me_check_199 = 1'b1 ; - - // rule RL_sink_selected_3 - assign CAN_FIRE_RL_sink_selected_3 = - !CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && flitToSink_1_0$whas ; - assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; - - // rule RL_sink_selected_4 - assign CAN_FIRE_RL_sink_selected_4 = - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && flitToSink_1_1$whas ; - assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; - - // rule __me_check_201 - assign CAN_FIRE___me_check_201 = 1'b1 ; - assign WILL_FIRE___me_check_201 = 1'b1 ; - - // rule RL_ifcs_0_forwardRsp - assign CAN_FIRE_RL_ifcs_0_forwardRsp = - msNoSynth_0_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_3 && - !ifcs_0_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_forwardRsp = CAN_FIRE_RL_ifcs_0_forwardRsp ; - - // rule RL_msNoSynth_0_b_forwardFlit - assign CAN_FIRE_RL_msNoSynth_0_b_forwardFlit = - !tmp0_b_buffer_ff$FULL_N || - msNoSynth_0_b_buffer_firstValid$Q_OUT && - (msNoSynth_0_b_buffer_ff$EMPTY_N || - msNoSynth_0_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_0_b_forwardFlit = - CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; - - // rule RL_tmp0_b_forwardFlit - assign CAN_FIRE_RL_tmp0_b_forwardFlit = - tmp0_b_buffer_firstValid$Q_OUT && - (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_tmp0_b_forwardFlit = CAN_FIRE_RL_tmp0_b_forwardFlit ; - - // rule RL_tmp0_b_dropFlit - assign CAN_FIRE_RL_tmp0_b_dropFlit = - (tmp0_b_buffer_ff$EMPTY_N || tmp0_b_buffer_enqw$whas) && - proc$master1_bready ; - assign WILL_FIRE_RL_tmp0_b_dropFlit = CAN_FIRE_RL_tmp0_b_dropFlit ; - - // rule RL_tmp0_b_buffer_enqueue - assign CAN_FIRE_RL_tmp0_b_buffer_enqueue = - tmp0_b_buffer_enqw$whas && - (!CAN_FIRE_RL_tmp0_b_dropFlit || tmp0_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp0_b_buffer_enqueue = - CAN_FIRE_RL_tmp0_b_buffer_enqueue ; - - // rule RL_tmp0_b_buffer_dequeue - assign CAN_FIRE_RL_tmp0_b_buffer_dequeue = - CAN_FIRE_RL_tmp0_b_dropFlit && tmp0_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp0_b_buffer_dequeue = - CAN_FIRE_RL_tmp0_b_buffer_dequeue ; - - // rule RL_msNoSynth_0_b_dropFlit - assign CAN_FIRE_RL_msNoSynth_0_b_dropFlit = - (msNoSynth_0_b_buffer_ff$EMPTY_N || - msNoSynth_0_b_buffer_enqw$whas) && - tmp0_b_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_msNoSynth_0_b_dropFlit = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; - - // rule RL_msNoSynth_0_b_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue = - msNoSynth_0_b_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_0_b_dropFlit || - msNoSynth_0_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; - - // rule RL_msNoSynth_0_b_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit && - msNoSynth_0_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; - - // rule RL_ifcs_0_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 && - ifcs_0_noRoute_inner_pendingReq$port1__read && - ifcs_0_noRouteRsp$FULL_N && - proc$master1_wvalid ; - assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; - - // rule __me_check_156 - assign CAN_FIRE___me_check_156 = 1'b1 ; - assign WILL_FIRE___me_check_156 = 1'b1 ; - - // rule __me_check_157 - assign CAN_FIRE___me_check_157 = 1'b1 ; - assign WILL_FIRE___me_check_157 = 1'b1 ; - - // rule __me_check_160 - assign CAN_FIRE___me_check_160 = 1'b1 ; - assign WILL_FIRE___me_check_160 = 1'b1 ; - - // rule RL_merged_0_genFirst - assign CAN_FIRE_RL_merged_0_genFirst = - proc$master1_awvalid && proc$master1_wvalid && - merged_0_doDrop$whas && - merged_0_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; - - // rule RL_msNoSynth_0_aw_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; - - // rule RL_tmp0_aw_forwardReady - assign CAN_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_aw_forwardReady = 1'd1 ; - - // rule RL_merged_0_genOther - assign CAN_FIRE_RL_merged_0_genOther = - proc$master1_wvalid && merged_0_doDrop$whas && - merged_0_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; - - // rule RL_msNoSynth_0_w_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; - - // rule RL_tmp0_w_forwardReady - assign CAN_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_w_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_forwardRsp - assign CAN_FIRE_RL_ifcs_1_forwardRsp = - msNoSynth_1_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_4 && - !ifcs_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_forwardRsp = CAN_FIRE_RL_ifcs_1_forwardRsp ; - - // rule RL_msNoSynth_1_b_forwardFlit - assign CAN_FIRE_RL_msNoSynth_1_b_forwardFlit = - msNoSynth_1_b_buffer_firstValid$Q_OUT && - (msNoSynth_1_b_buffer_ff$EMPTY_N || - msNoSynth_1_b_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_1_b_forwardFlit = - CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; - - // rule RL_msNoSynth_1_b_dropFlit - assign CAN_FIRE_RL_msNoSynth_1_b_dropFlit = - (msNoSynth_1_b_buffer_ff$EMPTY_N || - msNoSynth_1_b_buffer_enqw$whas) && - debug_module$master_bready ; - assign WILL_FIRE_RL_msNoSynth_1_b_dropFlit = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; - - // rule RL_msNoSynth_1_b_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue = - msNoSynth_1_b_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_1_b_dropFlit || - msNoSynth_1_b_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; - - // rule RL_msNoSynth_1_b_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit && - msNoSynth_1_b_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + // rule __me_check_333 + assign CAN_FIRE___me_check_333 = 1'b1 ; + assign WILL_FIRE___me_check_333 = 1'b1 ; // rule RL_ifcs_0_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_firstFlit_1 = - uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && + ifcs_0_rspBack$FULL_N && ifcs_0_routeBack$FULL_N && !ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_firstFlit_1 = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; // rule RL_ifcs_0_followFlits_1 assign CAN_FIRE_RL_ifcs_0_followFlits_1 = - uncached_mem_shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ssNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N && + ifcs_0_rspBack$FULL_N && ifcs_0_state_1 ; assign WILL_FIRE_RL_ifcs_0_followFlits_1 = CAN_FIRE_RL_ifcs_0_followFlits_1 ; - // rule __me_check_170 - assign CAN_FIRE___me_check_170 = 1'b1 ; - assign WILL_FIRE___me_check_170 = 1'b1 ; + // rule __me_check_337 + assign CAN_FIRE___me_check_337 = 1'b1 ; + assign WILL_FIRE___me_check_337 = 1'b1 ; - // rule RL_ssNoSynth_0_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; - assign WILL_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'b1 ; + // rule RL_ssNoSynth_0_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_snk_doPut && + (!ssNoSynth_0_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; - // rule RL_ug_uncached_mem_shim_master_u_b_doPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = - uncached_mem_shim_bff$FULL_N && - ug_uncached_mem_shim_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + // rule RL_ssNoSynth_0_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; // rule RL_ifcs_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_firstFlit_1 = - plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + ifcs_1_rspBack$FULL_N && ifcs_1_routeBack$FULL_N && !ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; // rule RL_ifcs_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_followFlits_1 = - plic$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ssNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N && + ifcs_1_rspBack$FULL_N && ifcs_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_followFlits_1 ; - // rule __me_check_172 - assign CAN_FIRE___me_check_172 = 1'b1 ; - assign WILL_FIRE___me_check_172 = 1'b1 ; + // rule __me_check_339 + assign CAN_FIRE___me_check_339 = 1'b1 ; + assign WILL_FIRE___me_check_339 = 1'b1 ; - // rule RL_ssNoSynth_1_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_1_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_snk_doPut && + (!ssNoSynth_1_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; - // rule RL_ifcs_2_firstFlit - assign CAN_FIRE_RL_ifcs_2_firstFlit = - proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && - ifcs_2_routeBack$FULL_N && - !ifcs_2_state ; - assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + // rule RL_ssNoSynth_1_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; - // rule RL_ifcs_2_followFlits - assign CAN_FIRE_RL_ifcs_2_followFlits = - proc$debug_module_mem_server_bvalid && ifcs_2_rspBack$FULL_N && - ifcs_2_state ; - assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + // rule RL_sinks_0_warnDoPut + assign CAN_FIRE_RL_sinks_0_warnDoPut = + CAN_FIRE_RL_sink_selected && + ((split_0_flitLeft == 8'd0) ? + !ssNoSynth_0_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_0_warnDoPut = CAN_FIRE_RL_sinks_0_warnDoPut ; - // rule __me_check_174 - assign CAN_FIRE___me_check_174 = 1'b1 ; - assign WILL_FIRE___me_check_174 = 1'b1 ; + // rule RL_sinks_0_doPut + assign CAN_FIRE_RL_sinks_0_doPut = + IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 && + CAN_FIRE_RL_sink_selected ; + assign WILL_FIRE_RL_sinks_0_doPut = CAN_FIRE_RL_sinks_0_doPut ; - // rule RL_ssNoSynth_2_b_forwardReady - assign CAN_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + // rule RL_split_0_putFirst + assign CAN_FIRE_RL_split_0_putFirst = + split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 && + split_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + + // rule RL_ssNoSynth_0_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = + ssNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + !uncached_mem_shim_awff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_awSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = + uncached_mem_shim_awff$EMPTY_N && + uncached_mem_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_awSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; + + // rule RL_slave_vector_0_awSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut = + uncached_mem_shim_awff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_awSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_dropFlit && + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = + MUX_split_0_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop || + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop && + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; + + // rule RL_split_0_putOther + assign CAN_FIRE_RL_split_0_putOther = + CAN_FIRE_RL_sinks_0_doPut && + (!split_0_doPut$wget[172] || + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) && + split_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; + + // rule RL_ssNoSynth_0_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = + ssNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_0_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + !uncached_mem_shim_wff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_wSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = + uncached_mem_shim_wff$EMPTY_N && + uncached_mem_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_wSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; + + // rule RL_slave_vector_0_wSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut = + uncached_mem_shim_wff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_wSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_dropFlit && + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = + ssNoSynth_0_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop || + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop && + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_warnDoPut = + CAN_FIRE_RL_sink_selected_1 && + ((split_1_flitLeft == 8'd0) ? + !ssNoSynth_1_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_1_warnDoPut = CAN_FIRE_RL_sinks_1_warnDoPut ; + + // rule RL_sinks_1_doPut + assign CAN_FIRE_RL_sinks_1_doPut = + IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 && + CAN_FIRE_RL_sink_selected_1 ; + assign WILL_FIRE_RL_sinks_1_doPut = CAN_FIRE_RL_sinks_1_doPut ; + + // rule RL_split_1_putFirst + assign CAN_FIRE_RL_split_1_putFirst = + split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 && + split_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + + // rule RL_ssNoSynth_1_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = + ssNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_1_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_dropFlit && + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = + MUX_split_1_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop || + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop && + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; + + // rule RL_split_1_putOther + assign CAN_FIRE_RL_split_1_putOther = + CAN_FIRE_RL_sinks_1_doPut && + (!split_1_doPut$wget[172] || + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) && + split_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; + + // rule RL_ssNoSynth_1_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = + ssNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_1_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_1_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_dropFlit && + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = + ssNoSynth_1_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop || + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop && + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_2_warnDoPut + assign CAN_FIRE_RL_sinks_2_warnDoPut = + CAN_FIRE_RL_sink_selected_2 && + ((split_2_flitLeft == 8'd0) ? + !ssNoSynth_2_awNoSynth_buffer_ff$FULL_N || + !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : + !ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; + assign WILL_FIRE_RL_sinks_2_warnDoPut = CAN_FIRE_RL_sinks_2_warnDoPut ; + + // rule RL_sinks_2_doPut + assign CAN_FIRE_RL_sinks_2_doPut = + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 && + CAN_FIRE_RL_sink_selected_2 ; + assign WILL_FIRE_RL_sinks_2_doPut = CAN_FIRE_RL_sinks_2_doPut ; + + // rule RL_split_2_putFirst + assign CAN_FIRE_RL_split_2_putFirst = + split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 && + split_2_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + + // rule RL_ssNoSynth_2_awNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = + ssNoSynth_2_awNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_awNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_awNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_dropFlit && + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = + MUX_split_2_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop || + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop && + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; + + // rule RL_split_2_putOther + assign CAN_FIRE_RL_split_2_putOther = + CAN_FIRE_RL_sinks_2_doPut && + (!split_2_doPut$wget[172] || + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) && + split_2_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; + + // rule RL_ssNoSynth_2_wNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = + ssNoSynth_2_wNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N || + ssNoSynth_2_wNoSynth_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_wNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_wNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_dropFlit && + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = + ssNoSynth_2_wNoSynth_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop || + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop && + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_0_warnDoPut + assign CAN_FIRE_RL_sinks_1_0_warnDoPut = + CAN_FIRE_RL_sink_selected_3 && + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_0_warnDoPut = CAN_FIRE_RL_sinks_1_0_warnDoPut ; + + // rule RL_sinks_1_0_doPut + assign CAN_FIRE_RL_sinks_1_0_doPut = + msNoSynth_0_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_3 ; + assign WILL_FIRE_RL_sinks_1_0_doPut = CAN_FIRE_RL_sinks_1_0_doPut ; + + // rule RL_ifcs_0_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = + ifcs_0_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_0_doPut && + msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_0_doPut ; + + // rule RL_ifcs_0_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = + IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 && + ifcs_0_noRoute_inner_pendingReq$port1__read && + ifcs_0_noRouteRsp$FULL_N && + (CAN_FIRE_RL_merged_0_passFlit || merged_0_wff$EMPTY_N) ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + + // rule __me_check_323 + assign CAN_FIRE___me_check_323 = 1'b1 ; + assign WILL_FIRE___me_check_323 = 1'b1 ; + + // rule __me_check_324 + assign CAN_FIRE___me_check_324 = 1'b1 ; + assign WILL_FIRE___me_check_324 = 1'b1 ; + + // rule __me_check_327 + assign CAN_FIRE___me_check_327 = 1'b1 ; + assign WILL_FIRE___me_check_327 = 1'b1 ; + + // rule RL_merged_0_awFlit + assign CAN_FIRE_RL_merged_0_awFlit = + msNoSynth_0_awNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut) && + merged_0_awff$FULL_N ; + assign WILL_FIRE_RL_merged_0_awFlit = CAN_FIRE_RL_merged_0_awFlit ; + + // rule RL_msNoSynth_0_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_0_awFlit || + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_0_awFlit && + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; + + // rule RL_merged_0_wFlit + assign CAN_FIRE_RL_merged_0_wFlit = + msNoSynth_0_wNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut) && + merged_0_wff$FULL_N ; + assign WILL_FIRE_RL_merged_0_wFlit = CAN_FIRE_RL_merged_0_wFlit ; + + // rule RL_msNoSynth_0_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_0_wFlit || + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_0_wFlit && + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; + + // rule RL_merged_0_genFirst + assign CAN_FIRE_RL_merged_0_genFirst = + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N && + merged_0_doDrop$whas && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; + + // rule RL_merged_0_genOther + assign CAN_FIRE_RL_merged_0_genOther = + merged_0_wff$EMPTY_N && merged_0_doDrop$whas && + merged_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; + + // rule RL_ifcs_0_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_0_snk_warnDoPut = + ifcs_0_snk_putWire$whas && + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_snk_warnDoPut = + CAN_FIRE_RL_ifcs_0_snk_warnDoPut ; + + // rule RL_ifcs_0_snk_doPut + assign CAN_FIRE_RL_ifcs_0_snk_doPut = + msNoSynth_0_bNoSynth_buffer_ff$FULL_N && + ifcs_0_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_0_snk_doPut = CAN_FIRE_RL_ifcs_0_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = + msNoSynth_0_bNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_0_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_setPeek ; + + // rule RL_msNoSynth_0_bNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_forwardFlit = 1'd1 ; + + // rule RL_proc_uncached_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + !proc$master1_b_canPut ; + assign WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut = + CAN_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut ; + + // rule RL_proc_uncached_bSynth_snk_doPut + assign CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut = + proc$RDY_master1_b_put && + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit ; + assign WILL_FIRE_RL_proc_uncached_bSynth_snk_doPut = + CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; + + // rule RL_msNoSynth_0_bNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_dropFlit && + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; + + // rule RL_msNoSynth_0_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_0_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop || + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop && + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_warnDoPut = + CAN_FIRE_RL_sink_selected_4 && + !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_warnDoPut = CAN_FIRE_RL_sinks_1_1_warnDoPut ; + + // rule RL_sinks_1_1_doPut + assign CAN_FIRE_RL_sinks_1_1_doPut = + msNoSynth_1_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_4 ; + assign WILL_FIRE_RL_sinks_1_1_doPut = CAN_FIRE_RL_sinks_1_1_doPut ; + + // rule RL_ifcs_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = + ifcs_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_doPut && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_doPut ; + + // rule RL_ifcs_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = + IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 && + ifcs_1_noRoute_inner_pendingReq$port1__read && + ifcs_1_noRouteRsp$FULL_N && + (CAN_FIRE_RL_merged_1_passFlit || merged_1_wff$EMPTY_N) ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + + // rule __me_check_331 + assign CAN_FIRE___me_check_331 = 1'b1 ; + assign WILL_FIRE___me_check_331 = 1'b1 ; + + // rule __me_check_332 + assign CAN_FIRE___me_check_332 = 1'b1 ; + assign WILL_FIRE___me_check_332 = 1'b1 ; + + // rule __me_check_335 + assign CAN_FIRE___me_check_335 = 1'b1 ; + assign WILL_FIRE___me_check_335 = 1'b1 ; + + // rule RL_merged_1_genFirst + assign CAN_FIRE_RL_merged_1_genFirst = + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N && + merged_1_doDrop$whas && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; + + // rule RL_merged_1_genOther + assign CAN_FIRE_RL_merged_1_genOther = + merged_1_wff$EMPTY_N && merged_1_doDrop$whas && + merged_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; + + // rule RL_ifcs_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_1_snk_warnDoPut = + ifcs_1_snk_putWire$whas && + !msNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_1_snk_warnDoPut ; + + // rule RL_ifcs_1_snk_doPut + assign CAN_FIRE_RL_ifcs_1_snk_doPut = + msNoSynth_1_bNoSynth_buffer_ff$FULL_N && + ifcs_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_1_snk_doPut = CAN_FIRE_RL_ifcs_1_snk_doPut ; + + // rule RL_msNoSynth_1_bNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = + msNoSynth_1_bNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_setPeek ; + + // rule RL_msNoSynth_1_bNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_forwardFlit = 1'd1 ; + + // rule RL_msNoSynth_1_bNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_dropFlit && + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; + + // rule RL_msNoSynth_1_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop || + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop && + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; // rule RL_ifcs_0_1_firstFlit assign CAN_FIRE_RL_ifcs_0_1_firstFlit = - proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_innerReq$FULL_N && ifcs_0_1_innerRoute$FULL_N && ifcs_0_1_state == 2'd0 && - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 == + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 == 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit = CAN_FIRE_RL_ifcs_0_1_firstFlit ; // rule RL_ifcs_0_1_followFlits assign CAN_FIRE_RL_ifcs_0_1_followFlits = - proc$master1_arvalid && ifcs_0_1_innerReq$FULL_N && - ifcs_0_1_state == 2'd1 ; + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_state == 2'd1 && + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; assign WILL_FIRE_RL_ifcs_0_1_followFlits = CAN_FIRE_RL_ifcs_0_1_followFlits ; // rule RL_ifcs_0_1_nonRoutableFlit assign CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit = - ifcs_0_1_noRoute_flitCount == 9'd0 && proc$master1_arvalid && + msNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_0_1_noRoute_flitCount == 9'd0 && ifcs_0_1_state == 2'd0 && - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 != + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 != 2'd1 ; assign WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ; // rule RL_ifcs_0_1_drainFlits assign CAN_FIRE_RL_ifcs_0_1_drainFlits = - proc$master1_arvalid && ifcs_0_1_state == 2'd2 ; + (msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) && + ifcs_0_1_state == 2'd2 ; assign WILL_FIRE_RL_ifcs_0_1_drainFlits = CAN_FIRE_RL_ifcs_0_1_drainFlits ; - // rule __me_check_205 - assign CAN_FIRE___me_check_205 = 1'b1 ; - assign WILL_FIRE___me_check_205 = 1'b1 ; - - // rule RL_ifcs_0_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = - msNoSynth_0_r_buffer_ff$FULL_N && ifcs_0_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; - - // rule RL_checkSinkReady_8 - assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; - - // rule RL_ifcs_1_1_drainNoRouteResponse - assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = - msNoSynth_1_r_buffer_ff$FULL_N && ifcs_1_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = - CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; - - // rule RL_checkSinkReady_9 - assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; - assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; - - // rule RL_craftReq_7 - assign CAN_FIRE_RL_craftReq_7 = - ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; - - // rule RL_craftReq_8 - assign CAN_FIRE_RL_craftReq_8 = - ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; - - // rule RL_craftReq_9 - assign CAN_FIRE_RL_craftReq_9 = - ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; - assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; - - // rule RL_arbitrate_3 - assign CAN_FIRE_RL_arbitrate_3 = - reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302 && - !state_1_1_1 ; - assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; - - // rule RL_source_selected_7 - assign CAN_FIRE_RL_source_selected_7 = - (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_0$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; - - // rule RL_burst_7 - assign CAN_FIRE_RL_burst_7 = - ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400 ; - assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; - - // rule RL_source_selected_8 - assign CAN_FIRE_RL_source_selected_8 = - (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_1_1$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; - - // rule RL_burst_8 - assign CAN_FIRE_RL_burst_8 = - ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436 ; - assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; - - // rule __me_check_244 - assign CAN_FIRE___me_check_244 = 1'b1 ; - assign WILL_FIRE___me_check_244 = 1'b1 ; - - // rule RL_source_selected_9 - assign CAN_FIRE_RL_source_selected_9 = - (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && - !state_1_1_1 && - MUX_activeSource_1_1_2$write_1__VAL_1 ; - assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; - - // rule RL_burst_9 - assign CAN_FIRE_RL_burst_9 = - ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && - state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472 ; - assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; - - // rule __me_check_242 - assign CAN_FIRE___me_check_242 = 1'b1 ; - assign WILL_FIRE___me_check_242 = 1'b1 ; - - // rule __me_check_246 - assign CAN_FIRE___me_check_246 = 1'b1 ; - assign WILL_FIRE___me_check_246 = 1'b1 ; - - // rule RL_sink_selected_8 - assign CAN_FIRE_RL_sink_selected_8 = - !CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && - flitToSink_1_1_0$whas ; - assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; - - // rule RL_sink_selected_9 - assign CAN_FIRE_RL_sink_selected_9 = - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && - flitToSink_1_1_1_1$whas ; - assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; - - // rule __me_check_248 - assign CAN_FIRE___me_check_248 = 1'b1 ; - assign WILL_FIRE___me_check_248 = 1'b1 ; - - // rule RL_ifcs_0_1_forwardRsp - assign CAN_FIRE_RL_ifcs_0_1_forwardRsp = - msNoSynth_0_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_8 && - !ifcs_0_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_0_1_forwardRsp = CAN_FIRE_RL_ifcs_0_1_forwardRsp ; - - // rule RL_msNoSynth_0_r_forwardFlit - assign CAN_FIRE_RL_msNoSynth_0_r_forwardFlit = - !tmp0_r_buffer_ff$FULL_N || - msNoSynth_0_r_buffer_firstValid$Q_OUT && - (msNoSynth_0_r_buffer_ff$EMPTY_N || - msNoSynth_0_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_0_r_forwardFlit = - CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; - - // rule RL_tmp0_r_forwardFlit - assign CAN_FIRE_RL_tmp0_r_forwardFlit = - tmp0_r_buffer_firstValid$Q_OUT && - (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_tmp0_r_forwardFlit = CAN_FIRE_RL_tmp0_r_forwardFlit ; - - // rule RL_tmp0_r_dropFlit - assign CAN_FIRE_RL_tmp0_r_dropFlit = - (tmp0_r_buffer_ff$EMPTY_N || tmp0_r_buffer_enqw$whas) && - proc$master1_rready ; - assign WILL_FIRE_RL_tmp0_r_dropFlit = CAN_FIRE_RL_tmp0_r_dropFlit ; - - // rule RL_tmp0_r_buffer_enqueue - assign CAN_FIRE_RL_tmp0_r_buffer_enqueue = - tmp0_r_buffer_enqw$whas && - (!CAN_FIRE_RL_tmp0_r_dropFlit || tmp0_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_tmp0_r_buffer_enqueue = - CAN_FIRE_RL_tmp0_r_buffer_enqueue ; - - // rule RL_tmp0_r_buffer_dequeue - assign CAN_FIRE_RL_tmp0_r_buffer_dequeue = - CAN_FIRE_RL_tmp0_r_dropFlit && tmp0_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_tmp0_r_buffer_dequeue = - CAN_FIRE_RL_tmp0_r_buffer_dequeue ; - - // rule RL_msNoSynth_0_r_dropFlit - assign CAN_FIRE_RL_msNoSynth_0_r_dropFlit = - (msNoSynth_0_r_buffer_ff$EMPTY_N || - msNoSynth_0_r_buffer_enqw$whas) && - tmp0_r_buffer_ff$FULL_N ; - assign WILL_FIRE_RL_msNoSynth_0_r_dropFlit = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; - - // rule RL_msNoSynth_0_r_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue = - msNoSynth_0_r_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_0_r_dropFlit || - msNoSynth_0_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; - - // rule RL_msNoSynth_0_r_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit && - msNoSynth_0_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; - - // rule RL_ifcs_0_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = - x_port1__read__h72781 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && - (x_port1__read__h72781 != 9'd1 || proc$master1_arvalid) ; - assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; - - // rule __me_check_203 - assign CAN_FIRE___me_check_203 = 1'b1 ; - assign WILL_FIRE___me_check_203 = 1'b1 ; - - // rule __me_check_204 - assign CAN_FIRE___me_check_204 = 1'b1 ; - assign WILL_FIRE___me_check_204 = 1'b1 ; - - // rule __me_check_207 - assign CAN_FIRE___me_check_207 = 1'b1 ; - assign WILL_FIRE___me_check_207 = 1'b1 ; - - // rule RL_msNoSynth_0_ar_forwardReady - assign CAN_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; - - // rule RL_tmp0_ar_forwardReady - assign CAN_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_tmp0_ar_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_1_forwardRsp - assign CAN_FIRE_RL_ifcs_1_1_forwardRsp = - msNoSynth_1_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_9 && - !ifcs_1_1_noRouteRsp$EMPTY_N ; - assign WILL_FIRE_RL_ifcs_1_1_forwardRsp = CAN_FIRE_RL_ifcs_1_1_forwardRsp ; - - // rule RL_msNoSynth_1_r_forwardFlit - assign CAN_FIRE_RL_msNoSynth_1_r_forwardFlit = - msNoSynth_1_r_buffer_firstValid$Q_OUT && - (msNoSynth_1_r_buffer_ff$EMPTY_N || - msNoSynth_1_r_buffer_enqw$whas) ; - assign WILL_FIRE_RL_msNoSynth_1_r_forwardFlit = - CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; - - // rule RL_msNoSynth_1_r_dropFlit - assign CAN_FIRE_RL_msNoSynth_1_r_dropFlit = - (msNoSynth_1_r_buffer_ff$EMPTY_N || - msNoSynth_1_r_buffer_enqw$whas) && - debug_module$master_rready ; - assign WILL_FIRE_RL_msNoSynth_1_r_dropFlit = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; - - // rule RL_msNoSynth_1_r_buffer_enqueue - assign CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue = - msNoSynth_1_r_buffer_enqw$whas && - (!CAN_FIRE_RL_msNoSynth_1_r_dropFlit || - msNoSynth_1_r_buffer_ff$EMPTY_N) ; - assign WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue = - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; - - // rule RL_msNoSynth_1_r_buffer_dequeue - assign CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit && - msNoSynth_1_r_buffer_ff$EMPTY_N ; - assign WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue = - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; - - // rule RL_ifcs_1_firstFlit - assign CAN_FIRE_RL_ifcs_1_firstFlit = - debug_module$master_wvalid && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_innerReq$FULL_N && - ifcs_1_innerRoute$FULL_N && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - ifcs_1_state == 2'd0 && - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 == - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; - - // rule RL_ifcs_1_followFlits - assign CAN_FIRE_RL_ifcs_1_followFlits = - debug_module$master_wvalid && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_innerReq$FULL_N && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - ifcs_1_state == 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; - - // rule RL_ifcs_1_nonRoutableFlit - assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350 && - ifcs_1_state == 2'd0 && - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 != - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = - CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; - - // rule RL_ifcs_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - ifcs_1_noRoute_inner_pendingReq$port1__read && - ifcs_1_noRouteRsp$FULL_N && - debug_module$master_wvalid ; - assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; - - // rule RL_ifcs_1_drainFlits - assign CAN_FIRE_RL_ifcs_1_drainFlits = - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 && - debug_module$master_wvalid && - ifcs_1_state == 2'd2 ; - assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; - - // rule __me_check_163 - assign CAN_FIRE___me_check_163 = 1'b1 ; - assign WILL_FIRE___me_check_163 = 1'b1 ; - - // rule __me_check_164 - assign CAN_FIRE___me_check_164 = 1'b1 ; - assign WILL_FIRE___me_check_164 = 1'b1 ; - - // rule __me_check_165 - assign CAN_FIRE___me_check_165 = 1'b1 ; - assign WILL_FIRE___me_check_165 = 1'b1 ; - - // rule __me_check_167 - assign CAN_FIRE___me_check_167 = 1'b1 ; - assign WILL_FIRE___me_check_167 = 1'b1 ; - - // rule RL_merged_1_genFirst - assign CAN_FIRE_RL_merged_1_genFirst = - debug_module$master_awvalid && debug_module$master_wvalid && - merged_1_doDrop$whas && - merged_1_flitLeft == 8'd0 ; - assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; - - // rule RL_msNoSynth_1_aw_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; - - // rule RL_merged_1_genOther - assign CAN_FIRE_RL_merged_1_genOther = - debug_module$master_wvalid && merged_1_doDrop$whas && - merged_1_flitLeft != 8'd0 ; - assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; - - // rule RL_msNoSynth_1_w_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; - - // rule RL_ifcs_1_1_firstFlit - assign CAN_FIRE_RL_ifcs_1_1_firstFlit = - debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && - ifcs_1_1_innerRoute$FULL_N && - ifcs_1_1_state == 2'd0 && - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 == - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; - - // rule RL_ifcs_1_1_followFlits - assign CAN_FIRE_RL_ifcs_1_1_followFlits = - debug_module$master_arvalid && ifcs_1_1_innerReq$FULL_N && - ifcs_1_1_state == 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_followFlits = - CAN_FIRE_RL_ifcs_1_1_followFlits ; - - // rule RL_ifcs_1_1_nonRoutableFlit - assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = - ifcs_1_1_noRoute_flitCount == 9'd0 && - debug_module$master_arvalid && - ifcs_1_1_state == 2'd0 && - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 != - 2'd1 ; - assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = - CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; - - // rule RL_ifcs_1_1_nonRoutableGenRsp - assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = - x_port1__read__h75154 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && - (x_port1__read__h75154 != 9'd1 || debug_module$master_arvalid) ; - assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = - CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; - - // rule RL_ifcs_1_1_drainFlits - assign CAN_FIRE_RL_ifcs_1_1_drainFlits = - debug_module$master_arvalid && ifcs_1_1_state == 2'd2 ; - assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; - - // rule __me_check_210 - assign CAN_FIRE___me_check_210 = 1'b1 ; - assign WILL_FIRE___me_check_210 = 1'b1 ; - - // rule __me_check_211 - assign CAN_FIRE___me_check_211 = 1'b1 ; - assign WILL_FIRE___me_check_211 = 1'b1 ; - - // rule __me_check_212 - assign CAN_FIRE___me_check_212 = 1'b1 ; - assign WILL_FIRE___me_check_212 = 1'b1 ; - - // rule __me_check_214 - assign CAN_FIRE___me_check_214 = 1'b1 ; - assign WILL_FIRE___me_check_214 = 1'b1 ; - - // rule RL_msNoSynth_1_ar_forwardReady - assign CAN_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + // rule __me_check_384 + assign CAN_FIRE___me_check_384 = 1'b1 ; + assign WILL_FIRE___me_check_384 = 1'b1 ; // rule RL_ifcs_0_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_0_1_firstFlit_1 = - uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && + ifcs_0_1_rspBack$FULL_N && ifcs_0_1_routeBack$FULL_N && !ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_firstFlit_1 = @@ -6141,29 +7599,37 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ifcs_0_1_followFlits_1 assign CAN_FIRE_RL_ifcs_0_1_followFlits_1 = - uncached_mem_shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ssNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N && + ifcs_0_1_rspBack$FULL_N && ifcs_0_1_state_1 ; assign WILL_FIRE_RL_ifcs_0_1_followFlits_1 = CAN_FIRE_RL_ifcs_0_1_followFlits_1 ; - // rule __me_check_217 - assign CAN_FIRE___me_check_217 = 1'b1 ; - assign WILL_FIRE___me_check_217 = 1'b1 ; + // rule __me_check_396 + assign CAN_FIRE___me_check_396 = 1'b1 ; + assign WILL_FIRE___me_check_396 = 1'b1 ; - // rule RL_ssNoSynth_0_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; - assign WILL_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'b1 ; + // rule RL_ssNoSynth_0_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_snk_doPut && + (!ssNoSynth_0_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; - // rule RL_ug_uncached_mem_shim_master_u_r_doPut - assign CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = - uncached_mem_shim_rff$FULL_N && - ug_uncached_mem_shim_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + // rule RL_ssNoSynth_0_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; // rule RL_ifcs_1_1_firstFlit_1 assign CAN_FIRE_RL_ifcs_1_1_firstFlit_1 = - plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + ifcs_1_1_rspBack$FULL_N && ifcs_1_1_routeBack$FULL_N && !ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_firstFlit_1 = @@ -6171,18 +7637,124 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ifcs_1_1_followFlits_1 assign CAN_FIRE_RL_ifcs_1_1_followFlits_1 = - plic$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ssNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N && + ifcs_1_1_rspBack$FULL_N && ifcs_1_1_state_1 ; assign WILL_FIRE_RL_ifcs_1_1_followFlits_1 = CAN_FIRE_RL_ifcs_1_1_followFlits_1 ; - // rule __me_check_219 - assign CAN_FIRE___me_check_219 = 1'b1 ; - assign WILL_FIRE___me_check_219 = 1'b1 ; + // rule __me_check_398 + assign CAN_FIRE___me_check_398 = 1'b1 ; + assign WILL_FIRE___me_check_398 = 1'b1 ; - // rule RL_ssNoSynth_1_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_1_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_snk_doPut && + (!ssNoSynth_1_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_0_warnDoPut_1 + assign CAN_FIRE_RL_sinks_1_0_warnDoPut_1 = + CAN_FIRE_RL_sink_selected_5 && + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_0_warnDoPut_1 = + CAN_FIRE_RL_sinks_1_0_warnDoPut_1 ; + + // rule RL_sinks_1_0_doPut_1 + assign CAN_FIRE_RL_sinks_1_0_doPut_1 = + ssNoSynth_0_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_5 ; + assign WILL_FIRE_RL_sinks_1_0_doPut_1 = CAN_FIRE_RL_sinks_1_0_doPut_1 ; + + // rule RL_ssNoSynth_0_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = + ssNoSynth_0_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_0_doPut_1) ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_0_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_forwardFlit = 1'd1 ; + + // rule RL_slave_vector_0_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + !uncached_mem_shim_arff$FULL_N ; + assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut = + CAN_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut ; + + // rule RL_uncached_mem_master_arSynth_src_doDrop + assign CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = + uncached_mem_shim_arff$EMPTY_N && + uncached_mem_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_uncached_mem_master_arSynth_src_doDrop = + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; + + // rule RL_slave_vector_0_arSynth_snk_doPut + assign CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut = + uncached_mem_shim_arff$FULL_N && + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit ; + assign WILL_FIRE_RL_slave_vector_0_arSynth_snk_doPut = + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; + + // rule RL_ssNoSynth_0_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_dropFlit && + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_0_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_0_doPut_1 && + (!CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop || + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_0_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop && + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_warnDoPut_1 + assign CAN_FIRE_RL_sinks_1_1_warnDoPut_1 = + CAN_FIRE_RL_sink_selected_6 && + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_warnDoPut_1 = + CAN_FIRE_RL_sinks_1_1_warnDoPut_1 ; + + // rule RL_sinks_1_1_doPut_1 + assign CAN_FIRE_RL_sinks_1_1_doPut_1 = + ssNoSynth_1_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_6 ; + assign WILL_FIRE_RL_sinks_1_1_doPut_1 = CAN_FIRE_RL_sinks_1_1_doPut_1 ; + + // rule RL_ssNoSynth_1_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = + ssNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_1_doPut_1) ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_1_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_forwardFlit = 1'd1 ; // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = @@ -6198,27 +7770,752 @@ module mkCoreW(RST_N_dm_power_on_reset, assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; + // rule RL_ssNoSynth_1_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_dropFlit && + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_1_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_1_doPut_1 && + (!CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop || + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_1_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop && + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_2_warnDoPut + assign CAN_FIRE_RL_sinks_1_2_warnDoPut = + CAN_FIRE_RL_sink_selected_7 && + !ssNoSynth_2_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_2_warnDoPut = CAN_FIRE_RL_sinks_1_2_warnDoPut ; + + // rule RL_sinks_1_2_doPut + assign CAN_FIRE_RL_sinks_1_2_doPut = + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_7 ; + assign WILL_FIRE_RL_sinks_1_2_doPut = CAN_FIRE_RL_sinks_1_2_doPut ; + + // rule RL_ssNoSynth_2_arNoSynth_src_setPeek + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = + ssNoSynth_2_arNoSynth_buffer_firstValid$Q_OUT && + (ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sinks_1_2_doPut) ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_setPeek ; + + // rule RL_ssNoSynth_2_arNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_forwardFlit = 1'd1 ; + + // rule RL_ssNoSynth_2_bNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = + proc$debug_module_mem_server_bvalid && + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_2_bNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_2_bNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit && + !ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_2_bNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut ; + + // rule RL_ssNoSynth_2_arNoSynth_src_doDrop + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_dropFlit && + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; + + // rule RL_ssNoSynth_2_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_sinks_1_2_doPut && + (!CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop || + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop && + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; + + // rule RL_ssNoSynth_2_rNoSynth_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = + proc$debug_module_mem_server_rvalid && + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; + + // rule RL_ssNoSynth_2_rNoSynth_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_forwardReady = 1'd1 ; + + // rule RL_ssNoSynth_2_rNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit && + !ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut ; + + // rule RL_ssNoSynth_2_rNoSynth_snk_doPut + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_forwardFlit ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut ; + + // rule RL_ifcs_2_firstFlit + assign CAN_FIRE_RL_ifcs_2_firstFlit = + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && + ifcs_2_rspBack$FULL_N && + ifcs_2_routeBack$FULL_N && + !ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + + // rule RL_ifcs_2_followFlits + assign CAN_FIRE_RL_ifcs_2_followFlits = + ssNoSynth_2_bNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N && + ifcs_2_rspBack$FULL_N && + ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + + // rule __me_check_341 + assign CAN_FIRE___me_check_341 = 1'b1 ; + assign WILL_FIRE___me_check_341 = 1'b1 ; + + // rule RL_ssNoSynth_2_bNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_snk_doPut && + (!ssNoSynth_2_bNoSynth_buffer_dequeueing$whas || + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_bNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas && + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; + // rule RL_ifcs_2_1_firstFlit assign CAN_FIRE_RL_ifcs_2_1_firstFlit = - proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && + ifcs_2_1_rspBack$FULL_N && ifcs_2_1_routeBack$FULL_N && !ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_firstFlit = CAN_FIRE_RL_ifcs_2_1_firstFlit ; // rule RL_ifcs_2_1_followFlits assign CAN_FIRE_RL_ifcs_2_1_followFlits = - proc$debug_module_mem_server_rvalid && ifcs_2_1_rspBack$FULL_N && + ssNoSynth_2_rNoSynth_buffer_firstValid$Q_OUT && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N && + ifcs_2_1_rspBack$FULL_N && ifcs_2_1_state ; assign WILL_FIRE_RL_ifcs_2_1_followFlits = CAN_FIRE_RL_ifcs_2_1_followFlits ; - // rule __me_check_221 - assign CAN_FIRE___me_check_221 = 1'b1 ; - assign WILL_FIRE___me_check_221 = 1'b1 ; + // rule __me_check_400 + assign CAN_FIRE___me_check_400 = 1'b1 ; + assign WILL_FIRE___me_check_400 = 1'b1 ; - // rule RL_ssNoSynth_2_r_forwardReady - assign CAN_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; - assign WILL_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + // rule RL_ssNoSynth_2_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_snk_doPut && + (!ssNoSynth_2_rNoSynth_buffer_dequeueing$whas || + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; + + // rule RL_ssNoSynth_2_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas && + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_0_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_0_warnDoPut = + CAN_FIRE_RL_sink_selected_8 && + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_0_warnDoPut = + CAN_FIRE_RL_sinks_1_1_0_warnDoPut ; + + // rule RL_sinks_1_1_0_doPut + assign CAN_FIRE_RL_sinks_1_1_0_doPut = + msNoSynth_0_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_8 ; + assign WILL_FIRE_RL_sinks_1_1_0_doPut = CAN_FIRE_RL_sinks_1_1_0_doPut ; + + // rule RL_ifcs_0_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + ifcs_0_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_0_doPut && + msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_0_doPut ; + + // rule RL_ifcs_0_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + x__h95023 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && + (x__h95023 != 9'd1 || msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + + // rule __me_check_382 + assign CAN_FIRE___me_check_382 = 1'b1 ; + assign WILL_FIRE___me_check_382 = 1'b1 ; + + // rule __me_check_383 + assign CAN_FIRE___me_check_383 = 1'b1 ; + assign WILL_FIRE___me_check_383 = 1'b1 ; + + // rule __me_check_386 + assign CAN_FIRE___me_check_386 = 1'b1 ; + assign WILL_FIRE___me_check_386 = 1'b1 ; + + // rule RL_msNoSynth_0_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_snk_doPut && + (!msNoSynth_0_arNoSynth_buffer_dequeueing$whas || + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = + msNoSynth_0_arNoSynth_buffer_dequeueing$whas && + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; + + // rule RL_ifcs_0_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut = + ifcs_0_1_snk_putWire$whas && + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_0_1_snk_warnDoPut ; + + // rule RL_ifcs_0_1_snk_doPut + assign CAN_FIRE_RL_ifcs_0_1_snk_doPut = + msNoSynth_0_rNoSynth_buffer_ff$FULL_N && + ifcs_0_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_0_1_snk_doPut = CAN_FIRE_RL_ifcs_0_1_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = + msNoSynth_0_rNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_0_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_setPeek ; + + // rule RL_msNoSynth_0_rNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_forwardFlit = 1'd1 ; + + // rule RL_proc_uncached_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + !proc$master1_r_canPut ; + assign WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut = + CAN_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut ; + + // rule RL_proc_uncached_rSynth_snk_doPut + assign CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut = + proc$RDY_master1_r_put && + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit ; + assign WILL_FIRE_RL_proc_uncached_rSynth_snk_doPut = + CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; + + // rule RL_msNoSynth_0_rNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_dropFlit && + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; + + // rule RL_msNoSynth_0_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_0_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop || + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_0_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop && + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; + + // rule RL_sinks_1_1_1_warnDoPut + assign CAN_FIRE_RL_sinks_1_1_1_warnDoPut = + CAN_FIRE_RL_sink_selected_9 && + !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_sinks_1_1_1_warnDoPut = + CAN_FIRE_RL_sinks_1_1_1_warnDoPut ; + + // rule RL_sinks_1_1_1_doPut + assign CAN_FIRE_RL_sinks_1_1_1_doPut = + msNoSynth_1_rNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_sink_selected_9 ; + assign WILL_FIRE_RL_sinks_1_1_1_doPut = CAN_FIRE_RL_sinks_1_1_1_doPut ; + + // rule RL_ifcs_1_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + ifcs_1_1_noRouteRsp$EMPTY_N && !CAN_FIRE_RL_sinks_1_1_1_doPut && + msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && + !WILL_FIRE_RL_sinks_1_1_1_doPut ; + + // rule RL_ifcs_1_1_snk_warnDoPut + assign CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut = + ifcs_1_1_snk_putWire$whas && + !msNoSynth_1_rNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut = + CAN_FIRE_RL_ifcs_1_1_snk_warnDoPut ; + + // rule RL_ifcs_1_1_snk_doPut + assign CAN_FIRE_RL_ifcs_1_1_snk_doPut = + msNoSynth_1_rNoSynth_buffer_ff$FULL_N && + ifcs_1_1_snk_putWire$whas ; + assign WILL_FIRE_RL_ifcs_1_1_snk_doPut = CAN_FIRE_RL_ifcs_1_1_snk_doPut ; + + // rule RL_msNoSynth_1_rNoSynth_src_setPeek + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = + msNoSynth_1_rNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_ifcs_1_1_snk_doPut) ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_setPeek ; + + // rule RL_msNoSynth_1_rNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_forwardFlit = 1'd1 ; + + // rule RL_msNoSynth_1_awNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = + debug_module$master_awvalid && + msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_awNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_awNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit && + !msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_awNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = + msNoSynth_1_awNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_awNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_wNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = + debug_module$master_wvalid && + msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_wNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_wNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit && + !msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_wNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = + msNoSynth_1_wNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_wNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_arNoSynth_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = + debug_module$master_arvalid && + msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; + + // rule RL_msNoSynth_1_arNoSynth_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_forwardReady = 1'd1 ; + + // rule RL_msNoSynth_1_arNoSynth_snk_warnDoPut + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit && + !msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut ; + + // rule RL_msNoSynth_1_arNoSynth_snk_doPut + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = + msNoSynth_1_arNoSynth_buffer_ff$FULL_N && + CAN_FIRE_RL_msNoSynth_1_arNoSynth_forwardFlit ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut ; + + // rule RL_msNoSynth_1_rNoSynth_src_doDrop + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_dropFlit && + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; + + // rule RL_msNoSynth_1_rNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_ifcs_1_1_snk_doPut && + (!CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop || + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_rNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop && + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; + + // rule RL_merged_1_awFlit + assign CAN_FIRE_RL_merged_1_awFlit = + msNoSynth_1_awNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut) && + merged_1_awff$FULL_N ; + assign WILL_FIRE_RL_merged_1_awFlit = CAN_FIRE_RL_merged_1_awFlit ; + + // rule RL_msNoSynth_1_awNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_1_awFlit || + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_awNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_1_awFlit && + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; + + // rule RL_merged_1_wFlit + assign CAN_FIRE_RL_merged_1_wFlit = + msNoSynth_1_wNoSynth_buffer_firstValid$Q_OUT && + (msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut) && + merged_1_wff$FULL_N ; + assign WILL_FIRE_RL_merged_1_wFlit = CAN_FIRE_RL_merged_1_wFlit ; + + // rule RL_msNoSynth_1_wNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_snk_doPut && + (!CAN_FIRE_RL_merged_1_wFlit || + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_wNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_merged_1_wFlit && + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; + + // rule RL_ifcs_1_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_1_firstFlit = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_innerRoute$FULL_N && + ifcs_1_1_state == 2'd0 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + + // rule RL_ifcs_1_1_followFlits + assign CAN_FIRE_RL_ifcs_1_1_followFlits = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_state == 2'd1 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits = + CAN_FIRE_RL_ifcs_1_1_followFlits ; + + // rule RL_ifcs_1_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = + msNoSynth_1_arNoSynth_buffer_firstValid$Q_OUT && + ifcs_1_1_noRoute_flitCount == 9'd0 && + ifcs_1_1_state == 2'd0 && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N && + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; + + // rule RL_ifcs_1_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + x__h97622 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && + (x__h97622 != 9'd1 || msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_1_drainFlits = + (msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N || + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut) && + ifcs_1_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; + + // rule __me_check_390 + assign CAN_FIRE___me_check_390 = 1'b1 ; + assign WILL_FIRE___me_check_390 = 1'b1 ; + + // rule __me_check_391 + assign CAN_FIRE___me_check_391 = 1'b1 ; + assign WILL_FIRE___me_check_391 = 1'b1 ; + + // rule __me_check_392 + assign CAN_FIRE___me_check_392 = 1'b1 ; + assign WILL_FIRE___me_check_392 = 1'b1 ; + + // rule __me_check_394 + assign CAN_FIRE___me_check_394 = 1'b1 ; + assign WILL_FIRE___me_check_394 = 1'b1 ; + + // rule RL_msNoSynth_1_arNoSynth_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_snk_doPut && + (!msNoSynth_1_arNoSynth_buffer_dequeueing$whas || + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; + + // rule RL_msNoSynth_1_arNoSynth_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = + msNoSynth_1_arNoSynth_buffer_dequeueing$whas && + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; + + // rule RL_cached_mem_master_awSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = + cached_mem_master_awSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_awSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop = + cached_mem_master_awSynth_src_dropWire$whas && + tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_awSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop && + !tagController_tmp_shimMaster_awff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + CAN_FIRE_RL_cached_mem_master_awSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_aw_doDrop ; + + // rule RL_cached_mem_master_wSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = + cached_mem_master_wSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_wSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop = + cached_mem_master_wSynth_src_dropWire$whas && + tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cached_mem_master_wSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop && + !tagController_tmp_shimMaster_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_w_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + CAN_FIRE_RL_cached_mem_master_wSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_w_doDrop ; + + // rule RL_cached_mem_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && + tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut ; + + // rule RL_cached_mem_master_bSynth_snk_doPut + assign CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut = + cpu_imem_master_bvalid && + !tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_cached_mem_master_bSynth_snk_doPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; + + // rule RL_tagController_tmp_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut && + tagController_tmp_shimMaster_bff_rv[8] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_b_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + !tagController_tmp_shimMaster_bff_rv[8] && + CAN_FIRE_RL_cached_mem_master_bSynth_snk_doPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_b_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_b_doPut ; + + // rule RL_cached_mem_master_arSynth_src_setPeek + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_setPeek = 1'd1 ; + + // rule RL_cached_mem_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = + cached_mem_master_arSynth_src_dropWire$whas && + !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop ; + + // rule RL_cached_mem_master_arSynth_src_doDrop + assign CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop = + cached_mem_master_arSynth_src_dropWire$whas && + tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_cached_mem_master_arSynth_src_doDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; + + // rule RL_tagController_tmp_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop && + !tagController_tmp_shimMaster_arff_rv$port1__read[99] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop ; + + // rule RL_tagController_tmp_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + CAN_FIRE_RL_cached_mem_master_arSynth_src_doDrop ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop = + CAN_FIRE_RL_tagController_tmp_ug_master_u_ar_doDrop ; + + // rule RL_cached_mem_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && + tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut ; + + // rule RL_cached_mem_master_rSynth_snk_doPut + assign CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut = + cpu_imem_master_rvalid && + !tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_cached_mem_master_rSynth_snk_doPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; + + // rule RL_tagController_tmp_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut && + tagController_tmp_shimMaster_rff_rv[73] ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut ; + + // rule RL_tagController_tmp_ug_master_u_r_doPut + assign CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + !tagController_tmp_shimMaster_rff_rv[73] && + CAN_FIRE_RL_cached_mem_master_rSynth_snk_doPut ; + assign WILL_FIRE_RL_tagController_tmp_ug_master_u_r_doPut = + CAN_FIRE_RL_tagController_tmp_ug_master_u_r_doPut ; + + // rule RL_tagController_tmp_passMemoryResponseWrite + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + tagController_tmp_shimMaster_bff_rv$port1__read[8] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseWrite && + !WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_tagController_tmp_passMemoryResponseRead + assign CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead = + tagController_tmp_shimMaster_rff_rv$port1__read[73] && + tagController_tmp_tagCon$RDY_memory_response_put ; + assign WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead = + CAN_FIRE_RL_tagController_tmp_passMemoryResponseRead ; + + // rule RL_tagController_tmp_propagateReset + assign CAN_FIRE_RL_tagController_tmp_propagateReset = + !tagController_tmp_reset_done ; + assign WILL_FIRE_RL_tagController_tmp_propagateReset = + CAN_FIRE_RL_tagController_tmp_propagateReset ; // inputs to muxes for submodule ports assign MUX_activeSource_0$write_1__SEL_1 = @@ -6325,31 +8622,37 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_0_innerRoute$D_OUT[2] ; assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && - uncached_mem_shim_rff$D_OUT[1] ; + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_0_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits ; assign MUX_ifcs_0_state$write_1__SEL_1 = - MUX_ifcs_0_state$write_1__PSEL_1 && proc$master1_wlast ; + MUX_ifcs_0_state$write_1__PSEL_1 && + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; assign MUX_ifcs_0_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast ; + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_0_state$write_1__SEL_3 = - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast ; + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_ifcs_1_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits ; assign MUX_ifcs_1_state$write_1__SEL_1 = - MUX_ifcs_1_state$write_1__PSEL_1 && debug_module$master_wlast ; + MUX_ifcs_1_state$write_1__PSEL_1 && + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; assign MUX_ifcs_1_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast ; + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_1_state$write_1__SEL_3 = WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - !debug_module$master_wlast ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_2_1_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_2_1_followFlits && - proc$debug_module_mem_server_rlast ; + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; assign MUX_proc$start_1__SEL_1 = WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 ; @@ -6377,41 +8680,19 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] ; assign MUX_activeSource_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign MUX_activeSource_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate && - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign MUX_activeSource_1_1_0$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign MUX_activeSource_1_1_1_1$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign MUX_activeSource_1_1_2$write_1__VAL_1 = WILL_FIRE_RL_arbitrate_3 && - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 ; - assign MUX_merged_0_flitLeft$write_1__VAL_1 = merged_0_flitLeft - 8'd1 ; - assign MUX_merged_1_flitLeft$write_1__VAL_1 = merged_1_flitLeft - 8'd1 ; - always@(MUX_flitToSink_1_0$wset_1__SEL_1 or - MUX_flitToSink_1_0$wset_1__SEL_4 or - ifcs_0_rspBack$D_OUT or - MUX_flitToSink_1_0$wset_1__SEL_2 or - MUX_flitToSink_1_0$wset_1__SEL_5 or - ifcs_1_rspBack$D_OUT or - MUX_flitToSink_1_0$wset_1__SEL_3 or - MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) - begin - case (1'b1) // synopsys parallel_case - MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; - MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; - MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; - default: MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 = - 6'b101010 /* unspecified value */ ; - endcase - end + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; always@(MUX_flitToSink_1_1_0$wset_1__SEL_1 or MUX_flitToSink_1_1_0$wset_1__SEL_4 or ifcs_0_1_rspBack$D_OUT or @@ -6424,37 +8705,34 @@ module mkCoreW(RST_N_dm_power_on_reset, case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_0$wset_1__SEL_1 || MUX_flitToSink_1_1_0$wset_1__SEL_4: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_0_1_rspBack$D_OUT; + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_2 || MUX_flitToSink_1_1_0$wset_1__SEL_5: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_1_1_rspBack$D_OUT; + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_0$wset_1__SEL_3 || MUX_flitToSink_1_1_0$wset_1__SEL_6: - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = - ifcs_2_1_rspBack$D_OUT; - default: MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 = + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; + default: MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(MUX_flitToSink_1_1$wset_1__SEL_1 or - MUX_flitToSink_1_1$wset_1__SEL_4 or + always@(MUX_flitToSink_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_0$wset_1__SEL_4 or ifcs_0_rspBack$D_OUT or - MUX_flitToSink_1_1$wset_1__SEL_2 or - MUX_flitToSink_1_1$wset_1__SEL_5 or + MUX_flitToSink_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_0$wset_1__SEL_5 or ifcs_1_rspBack$D_OUT or - MUX_flitToSink_1_1$wset_1__SEL_3 or - MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + MUX_flitToSink_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) begin case (1'b1) // synopsys parallel_case - MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_0_rspBack$D_OUT; - MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_1_rspBack$D_OUT; - MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = ifcs_2_rspBack$D_OUT; - default: MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 = + MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_ifcs_0_snk_putWire$wset_1__VAL_1 = 6'b101010 /* unspecified value */ ; endcase end @@ -6470,27 +8748,46 @@ module mkCoreW(RST_N_dm_power_on_reset, case (1'b1) // synopsys parallel_case MUX_flitToSink_1_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1_1$wset_1__SEL_4: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_0_1_rspBack$D_OUT; + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_0_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1_1_1$wset_1__SEL_5: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_1_1_rspBack$D_OUT; + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_1_1_rspBack$D_OUT; MUX_flitToSink_1_1_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1_1_1$wset_1__SEL_6: - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = - ifcs_2_1_rspBack$D_OUT; - default: MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 = + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = ifcs_2_1_rspBack$D_OUT; + default: MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + always@(MUX_flitToSink_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_ifcs_1_snk_putWire$wset_1__VAL_1 = + 6'b101010 /* unspecified value */ ; + endcase + end + assign MUX_merged_0_flitLeft$write_1__VAL_2 = merged_0_flitLeft - 8'd1 ; + assign MUX_merged_1_flitLeft$write_1__VAL_2 = merged_1_flitLeft - 8'd1 ; assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = rg_hart0_reset_delay - 8'd1 ; assign MUX_split_0_flitLeft$write_1__VAL_1 = split_0_flitLeft - 8'd1 ; assign MUX_split_1_flitLeft$write_1__VAL_1 = split_1_flitLeft - 8'd1 ; assign MUX_split_2_flitLeft$write_1__VAL_1 = split_2_flitLeft - 8'd1 ; assign MUX_tagController_tmp_tagCon$cache_request_put_1__VAL_1 = - { tmp__h8366[39:3], + { tmp__h8169[39:3], 4'd0, tagController_tmp_awreqff$D_OUT[97:93], 3'd1, @@ -6521,48 +8818,51 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_rff_rv$port1__read[67:3] } ; // inlined wires - assign tmp0_aw_dwReady$whas = - proc$master1_awvalid && CAN_FIRE_RL_merged_0_genFirst ; - assign tmp0_w_dwReady$whas = - proc$master1_wvalid && msNoSynth_0_w_dwReady$whas ; - assign tmp0_b_buffer_enqw$wget = - msNoSynth_0_b_buffer_ff$EMPTY_N ? - msNoSynth_0_b_buffer_ff$D_OUT : - msNoSynth_0_b_buffer_enqw$wget ; - assign tmp0_b_buffer_enqw$whas = - WILL_FIRE_RL_msNoSynth_0_b_forwardFlit && - tmp0_b_buffer_ff$FULL_N ; - assign tmp0_ar_dwReady$whas = - proc$master1_arvalid && msNoSynth_0_ar_dwReady$whas ; - assign tmp0_r_buffer_enqw$wget = - { x_rid__h25044, - x_rdata__h25045, - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[3:2] : - msNoSynth_0_r_buffer_enqw$wget[3:2], - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[1] : - msNoSynth_0_r_buffer_enqw$wget[1], - 1'd0 } ; - assign tmp0_r_buffer_enqw$whas = - WILL_FIRE_RL_msNoSynth_0_r_forwardFlit && - tmp0_r_buffer_ff$FULL_N ; - assign ug_uncached_mem_shim_master_u_aw_peekWire$wget = + assign proc_uncached_wSynth_src_peekWire$wget = + { proc$master1_w_peek[73:1], 1'd0 } ; + assign proc_uncached_bSynth_snk_putWire$wget = + msNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_bNoSynth_buffer_ff$D_OUT : + msNoSynth_0_bNoSynth_buffer_enqw$wget ; + assign proc_uncached_rSynth_snk_putWire$wget = + msNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_rNoSynth_buffer_ff$D_OUT : + msNoSynth_0_rNoSynth_buffer_enqw$wget ; + assign uncached_mem_master_awSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_awff$D_OUT } ; - assign ug_uncached_mem_shim_master_u_b_putWire$wget = + assign uncached_mem_master_bSynth_snk_putWire$wget = { cpu_dmem_master_bid, cpu_dmem_master_bresp } ; - assign ug_uncached_mem_shim_master_u_b_putWire$whas = + assign uncached_mem_master_bSynth_snk_putWire$whas = cpu_dmem_master_bvalid && uncached_mem_shim_bff$FULL_N ; - assign ug_uncached_mem_shim_master_u_ar_peekWire$wget = + assign uncached_mem_master_arSynth_src_peekWire$wget = { 1'd0, uncached_mem_shim_arff$D_OUT } ; - assign ug_uncached_mem_shim_master_u_r_putWire$wget = + assign uncached_mem_master_rSynth_snk_putWire$wget = { cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast } ; - assign ug_uncached_mem_shim_master_u_r_putWire$whas = + assign uncached_mem_master_rSynth_snk_putWire$whas = cpu_dmem_master_rvalid && uncached_mem_shim_rff$FULL_N ; assign tagController_tmp_ug_slave_u_aw_putWire$wget = + tmp2_awNoSynth_buffer_ff$EMPTY_N ? + tmp2_awNoSynth_buffer_ff$D_OUT : + tmp2_awNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_slave_u_w_putWire$wget = + tmp2_wNoSynth_buffer_ff$EMPTY_N ? + tmp2_wNoSynth_buffer_ff$D_OUT : + tmp2_wNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_slave_u_ar_putWire$wget = + tmp2_arNoSynth_buffer_ff$EMPTY_N ? + tmp2_arNoSynth_buffer_ff$D_OUT : + tmp2_arNoSynth_buffer_enqw$wget ; + assign tagController_tmp_ug_master_u_b_putWire$wget = + { cpu_imem_master_bid, cpu_imem_master_bresp } ; + assign tagController_tmp_ug_master_u_r_putWire$wget = + { cpu_imem_master_rid, + cpu_imem_master_rdata, + cpu_imem_master_rresp, + cpu_imem_master_rlast } ; + assign tmp2_awNoSynth_buffer_enqw$wget = { proc$master0_awid, proc$master0_awaddr, proc$master0_awlen, @@ -6573,12 +8873,16 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_awprot, proc$master0_awqos, proc$master0_awregion } ; - assign tagController_tmp_ug_slave_u_w_putWire$wget = + assign tmp2_wNoSynth_buffer_enqw$wget = { proc$master0_wdata, proc$master0_wstrb, proc$master0_wlast, proc$master0_wuser } ; - assign tagController_tmp_ug_slave_u_ar_putWire$wget = + assign tmp2_bNoSynth_src_peekWire$wget = + tmp2_bNoSynth_buffer_ff$EMPTY_N ? + tmp2_bNoSynth_buffer_ff$D_OUT : + tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; + assign tmp2_arNoSynth_buffer_enqw$wget = { proc$master0_arid, proc$master0_araddr, proc$master0_arlen, @@ -6589,115 +8893,142 @@ module mkCoreW(RST_N_dm_power_on_reset, proc$master0_arprot, proc$master0_arqos, proc$master0_arregion } ; - assign tagController_tmp_ug_master_u_b_putWire$wget = - { cpu_imem_master_bid, cpu_imem_master_bresp } ; - assign tagController_tmp_ug_master_u_b_putWire$whas = - cpu_imem_master_bvalid && - !tagController_tmp_shimMaster_bff_rv[8] ; - assign tagController_tmp_ug_master_u_r_putWire$wget = - { cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast } ; - assign tagController_tmp_ug_master_u_r_putWire$whas = - cpu_imem_master_rvalid && - !tagController_tmp_shimMaster_rff_rv[73] ; - assign tmp2_b_buffer_enqw$wget = - tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; - assign tmp2_r_buffer_enqw$wget = - tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; - assign msNoSynth_0_w_dwReady$whas = - WILL_FIRE_RL_merged_0_genOther || - WILL_FIRE_RL_merged_0_genFirst ; - assign msNoSynth_0_b_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ? - ifcs_0_noRouteRsp$D_OUT : - MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_0_b_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_0_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_0_forwardRsp ; - assign msNoSynth_0_ar_dwReady$whas = - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && - x_port1__read__h72781 == 9'd1 || - WILL_FIRE_RL_ifcs_0_1_drainFlits || - WILL_FIRE_RL_ifcs_0_1_followFlits || - WILL_FIRE_RL_ifcs_0_1_firstFlit ; - assign msNoSynth_0_r_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ? - ifcs_0_1_noRouteRsp$D_OUT : - MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_0_r_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_0_1_forwardRsp ; - assign msNoSynth_1_w_dwReady$whas = - WILL_FIRE_RL_merged_1_genOther || - WILL_FIRE_RL_merged_1_genFirst ; - assign msNoSynth_1_b_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ? - ifcs_1_noRouteRsp$D_OUT : - MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_1_b_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_1_forwardRsp ; - assign msNoSynth_1_ar_dwReady$whas = - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && - x_port1__read__h75154 == 9'd1 || - WILL_FIRE_RL_ifcs_1_1_drainFlits || - WILL_FIRE_RL_ifcs_1_1_followFlits || - WILL_FIRE_RL_ifcs_1_1_firstFlit ; - assign msNoSynth_1_r_buffer_enqw$wget = - WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ? - ifcs_1_1_noRouteRsp$D_OUT : - MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_2 ; - assign msNoSynth_1_r_buffer_enqw$whas = - WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse || - WILL_FIRE_RL_ifcs_1_1_forwardRsp ; - assign ssNoSynth_0_w_buffer_enqw$whas = + assign tmp2_rNoSynth_src_peekWire$wget = + tmp2_rNoSynth_buffer_ff$EMPTY_N ? + tmp2_rNoSynth_buffer_ff$D_OUT : + tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; + assign slave_vector_0_awSynth_snk_putWire$wget = + ssNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_awNoSynth_buffer_ff$D_OUT : + split_0_doPut$wget[171:74] ; + assign slave_vector_0_wSynth_snk_putWire$wget = + ssNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_wNoSynth_buffer_ff$D_OUT : + split_0_doPut$wget[73:0] ; + assign slave_vector_0_arSynth_snk_putWire$wget = + ssNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_0_arNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_bNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_0_doPut ? + MUX_ifcs_0_snk_putWire$wset_1__VAL_1 : + ifcs_0_noRouteRsp$D_OUT ; + assign msNoSynth_0_rNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_0_doPut ? + MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 : + ifcs_0_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_awNoSynth_buffer_enqw$wget = + { debug_module$master_awid, + debug_module$master_awaddr, + debug_module$master_awlen, + debug_module$master_awsize, + debug_module$master_awburst, + debug_module$master_awlock, + debug_module$master_awcache, + debug_module$master_awprot, + debug_module$master_awqos, + debug_module$master_awregion } ; + assign msNoSynth_1_wNoSynth_buffer_enqw$wget = + { debug_module$master_wdata, + debug_module$master_wstrb, + debug_module$master_wlast, + debug_module$master_wuser } ; + assign msNoSynth_1_bNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_doPut ? + MUX_ifcs_1_snk_putWire$wset_1__VAL_1 : + ifcs_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_bNoSynth_src_peekWire$wget = + msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_bNoSynth_buffer_ff$D_OUT : + msNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_arNoSynth_buffer_enqw$wget = + { debug_module$master_arid, + debug_module$master_araddr, + debug_module$master_arlen, + debug_module$master_arsize, + debug_module$master_arburst, + debug_module$master_arlock, + debug_module$master_arcache, + debug_module$master_arprot, + debug_module$master_arqos, + debug_module$master_arregion } ; + assign msNoSynth_1_rNoSynth_buffer_enqw$wget = + WILL_FIRE_RL_sinks_1_1_1_doPut ? + MUX_ifcs_1_1_snk_putWire$wset_1__VAL_1 : + ifcs_1_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_rNoSynth_src_peekWire$wget = + msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_rNoSynth_buffer_ff$D_OUT : + msNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_0_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] || WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[172] ; - assign ssNoSynth_0_b_dwReady$whas = - WILL_FIRE_RL_ifcs_0_followFlits_1 || - WILL_FIRE_RL_ifcs_0_firstFlit_1 ; - assign ssNoSynth_0_ar_buffer_enqw$wget = + assign ssNoSynth_0_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_0_1$wset_1__SEL_1 || MUX_flitToSink_1_0_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_0_r_dwReady$whas = - WILL_FIRE_RL_ifcs_0_1_followFlits_1 || - WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; - assign ssNoSynth_1_aw_buffer_enqw$wget = split_1_doPut$wget[171:74] ; - assign ssNoSynth_1_w_buffer_enqw$wget = split_1_doPut$wget[73:0] ; - assign ssNoSynth_1_w_buffer_enqw$whas = + assign ssNoSynth_1_awNoSynth_src_peekWire$wget = + ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_awNoSynth_buffer_ff$D_OUT : + split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] || WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[172] ; - assign ssNoSynth_1_b_dwReady$whas = - WILL_FIRE_RL_ifcs_1_followFlits_1 || - WILL_FIRE_RL_ifcs_1_firstFlit_1 ; - assign ssNoSynth_1_ar_buffer_enqw$wget = + assign ssNoSynth_1_wNoSynth_src_peekWire$wget = + ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_wNoSynth_buffer_ff$D_OUT : + split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_bNoSynth_buffer_enqw$wget = + { plic$axi4_slave_bid, plic$axi4_slave_bresp } ; + assign ssNoSynth_1_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1_1$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_1_r_dwReady$whas = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 || - WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; - assign ssNoSynth_2_aw_buffer_enqw$wget = split_2_doPut$wget[171:74] ; - assign ssNoSynth_2_w_buffer_enqw$wget = split_2_doPut$wget[73:0] ; - assign ssNoSynth_2_w_buffer_enqw$whas = + assign ssNoSynth_1_arNoSynth_src_peekWire$wget = + ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_rNoSynth_buffer_enqw$wget = + { plic$axi4_slave_rid, + plic$axi4_slave_rdata, + plic$axi4_slave_rresp, + plic$axi4_slave_rlast, + plic$axi4_slave_ruser } ; + assign ssNoSynth_2_awNoSynth_src_peekWire$wget = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_awNoSynth_buffer_ff$D_OUT : + split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_wNoSynth_buffer_enqw$whas = WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] || WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[172] ; - assign ssNoSynth_2_b_dwReady$whas = - WILL_FIRE_RL_ifcs_2_followFlits || - WILL_FIRE_RL_ifcs_2_firstFlit ; - assign ssNoSynth_2_ar_buffer_enqw$wget = + assign ssNoSynth_2_wNoSynth_src_peekWire$wget = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_wNoSynth_buffer_ff$D_OUT : + split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_bNoSynth_buffer_enqw$wget = + { proc$debug_module_mem_server_bid, + proc$debug_module_mem_server_bresp } ; + assign ssNoSynth_2_arNoSynth_buffer_enqw$wget = (MUX_flitToSink_1_2$wset_1__SEL_1 || MUX_flitToSink_1_2$wset_1__SEL_3) ? ifcs_0_1_innerReq$D_OUT : ifcs_1_1_innerReq$D_OUT ; - assign ssNoSynth_2_r_dwReady$whas = - WILL_FIRE_RL_ifcs_2_1_followFlits || - WILL_FIRE_RL_ifcs_2_1_firstFlit ; + assign ssNoSynth_2_arNoSynth_src_peekWire$wget = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_arNoSynth_buffer_ff$D_OUT : + ssNoSynth_2_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_rNoSynth_buffer_enqw$wget = + { proc$debug_module_mem_server_rid, + proc$debug_module_mem_server_rdata, + proc$debug_module_mem_server_rresp, + proc$debug_module_mem_server_rlast, + proc$debug_module_mem_server_ruser } ; + assign merged_0_outflit$wget = + { 1'd0, merged_0_awff$D_OUT, merged_0_wff$D_OUT } ; + assign merged_1_outflit$wget = + { 1'd0, merged_1_awff$D_OUT, merged_1_wff$D_OUT } ; assign split_0_doPut$wget = (MUX_flitToSink_0$wset_1__SEL_1 || MUX_flitToSink_0$wset_1__SEL_3) ? @@ -6713,15 +9044,21 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_flitToSink_2$wset_1__SEL_3) ? ifcs_0_innerReq$D_OUT : ifcs_1_innerReq$D_OUT ; + assign ifcs_0_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_0_doPut || + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_doPut || + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign reqWires_0$wget = (!ifcs_0_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0] ; assign reqWires_1$wget = (!ifcs_1_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0] ; assign flitToSink_0$whas = WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] || @@ -6746,21 +9083,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_innerRoute$D_OUT[2] ; assign reqWires_1_0$wget = (!ifcs_0_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_0_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_0_routeBack$D_OUT[0] ; assign reqWires_1_1$wget = (!ifcs_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_1_routeBack$D_OUT[0] ; assign reqWires_1_2$wget = (!ifcs_2_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? ifcs_2_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : ifcs_2_routeBack$D_OUT[0] ; assign flitToSink_1_0$whas = WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] || @@ -6782,15 +9119,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && ifcs_2_routeBack$D_OUT[1] ; + assign ifcs_0_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_0_doPut || + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_1_1_snk_putWire$whas = + WILL_FIRE_RL_sinks_1_1_1_doPut || + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign reqWires_1_0_1$wget = (!ifcs_0_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 : + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : ifcs_0_1_innerRoute$D_OUT[0] ; assign reqWires_1_1_1$wget = (!ifcs_1_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 : + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : ifcs_1_1_innerRoute$D_OUT[0] ; assign flitToSink_1_0_1$whas = WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] || @@ -6815,21 +9158,21 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_innerRoute$D_OUT[2] ; assign reqWires_1_1_0$wget = (!ifcs_0_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0] ; assign reqWires_1_1_1_1$wget = (!ifcs_1_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0] ; assign reqWires_1_1_2$wget = (!ifcs_2_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0] ; assign flitToSink_1_1_0$whas = WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] || @@ -6851,21 +9194,40 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_routeBack$D_OUT[1] || WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_routeBack$D_OUT[1] ; - assign ug_uncached_mem_shim_master_u_aw_dropWire$whas = + assign uncached_mem_master_awSynth_src_dropWire$whas = uncached_mem_shim_awff$EMPTY_N && cpu_dmem_master_awready ; - assign ug_uncached_mem_shim_master_u_w_dropWire$whas = + assign uncached_mem_master_wSynth_src_dropWire$whas = uncached_mem_shim_wff$EMPTY_N && cpu_dmem_master_wready ; - assign ug_uncached_mem_shim_master_u_ar_dropWire$whas = + assign uncached_mem_master_arSynth_src_dropWire$whas = uncached_mem_shim_arff$EMPTY_N && cpu_dmem_master_arready ; - assign tagController_tmp_ug_master_u_aw_dropWire$whas = - tagController_tmp_shimMaster_awff_rv$port1__read[99] && - cpu_imem_master_awready ; - assign tagController_tmp_ug_master_u_w_dropWire$whas = - tagController_tmp_shimMaster_wff_rv$port1__read[73] && - cpu_imem_master_wready ; - assign tagController_tmp_ug_master_u_ar_dropWire$whas = - tagController_tmp_shimMaster_arff_rv$port1__read[99] && - cpu_imem_master_arready ; + assign msNoSynth_0_arNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && x__h95023 == 9'd1 || + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign msNoSynth_1_arNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && x__h97622 == 9'd1 || + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign ssNoSynth_0_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_followFlits_1 || + WILL_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ssNoSynth_0_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ssNoSynth_1_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ssNoSynth_1_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ssNoSynth_2_bNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_2_followFlits || + WILL_FIRE_RL_ifcs_2_firstFlit ; + assign ssNoSynth_2_rNoSynth_buffer_dequeueing$whas = + WILL_FIRE_RL_ifcs_2_1_followFlits || + WILL_FIRE_RL_ifcs_2_1_firstFlit ; assign merged_0_doDrop$whas = WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp || WILL_FIRE_RL_ifcs_0_drainFlits || @@ -6878,19 +9240,28 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_ifcs_1_firstFlit ; assign sourceSelect_1_0$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign sourceSelect_1_1$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign sourceSelect_1_2$whas = WILL_FIRE_RL_arbitrate_1 && - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign sourceSelect_1_0_1$whas = WILL_FIRE_RL_arbitrate_2 && - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign sourceSelect_1_1_1$whas = WILL_FIRE_RL_arbitrate_2 && - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; + assign cached_mem_master_awSynth_src_dropWire$whas = + tagController_tmp_shimMaster_awff_rv$port1__read[99] && + cpu_imem_master_awready ; + assign cached_mem_master_wSynth_src_dropWire$whas = + tagController_tmp_shimMaster_wff_rv$port1__read[73] && + cpu_imem_master_wready ; + assign cached_mem_master_arSynth_src_dropWire$whas = + tagController_tmp_shimMaster_arff_rv$port1__read[99] && + cpu_imem_master_arready ; assign tagController_tmp_shimSlave_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_ug_slave_u_aw_putWire$wget } ; assign tagController_tmp_shimSlave_awff_rv$port1__read = @@ -6983,11 +9354,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign tagController_tmp_shimMaster_awff_rv$port0__write_1 = { 1'd1, tagController_tmp_tagCon$memory_request_get[100:95], - aw_awaddr__h10808, + aw_awaddr__h10611, tagController_tmp_tagCon$memory_request_get[7:0], - aw_awsize_val__h12547, + aw_awsize_val__h12350, 3'd2, - x__h14213, + x__h14016, 11'd0 } ; assign tagController_tmp_shimMaster_awff_rv$port1__read = tagController_tmp_shimMaster_awff_rv$EN_port0__write ? @@ -7040,12 +9411,12 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_tagCon$memory_request_get[93:92] != 2'd1 ; assign tagController_tmp_shimMaster_arff_rv$port0__write_1 = { 1'd1, - v_arid__h15556, - v_araddr__h15557, - v_arlen__h15558, - v_arsize_val__h15603, + v_arid__h15359, + v_araddr__h15360, + v_arlen__h15361, + v_arsize_val__h15406, 3'd2, - x__h15621, + x__h15424, 11'd0 } ; assign tagController_tmp_shimMaster_arff_rv$port1__read = tagController_tmp_shimMaster_arff_rv$EN_port0__write ? @@ -7075,25 +9446,16 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_rff_rv$port2__read ; assign ifcs_0_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - merged_0_flitLeft == 8'd0 ; - assign ifcs_0_noRoute_inner_currentReq$port0__write_1 = - { proc$master1_awid, - proc$master1_awaddr, - proc$master1_awlen, - proc$master1_awsize, - proc$master1_awburst, - proc$master1_awlock, - proc$master1_awcache, - proc$master1_awprot, - proc$master1_awqos, - proc$master1_awregion } ; + CAN_FIRE_RL_merged_0_passFlit && + !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_currentReq$port1__read = ifcs_0_noRoute_inner_currentReq$EN_port0__write ? - ifcs_0_noRoute_inner_currentReq$port0__write_1 : + merged_0_outflit$wget[170:74] : ifcs_0_noRoute_inner_currentReq ; assign ifcs_0_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - merged_0_flitLeft == 8'd0 ; + CAN_FIRE_RL_merged_0_passFlit && + !merged_0_outflit$wget[171] ; assign ifcs_0_noRoute_inner_pendingReq$port1__read = ifcs_0_noRoute_inner_pendingReq$EN_port0__write || ifcs_0_noRoute_inner_pendingReq ; @@ -7102,77 +9464,44 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_0_noRoute_inner_pendingReq$port1__read ; assign ifcs_1_noRoute_inner_currentReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - merged_1_flitLeft == 8'd0 ; - assign ifcs_1_noRoute_inner_currentReq$port0__write_1 = - { debug_module$master_awid, - debug_module$master_awaddr, - debug_module$master_awlen, - debug_module$master_awsize, - debug_module$master_awburst, - debug_module$master_awlock, - debug_module$master_awcache, - debug_module$master_awprot, - debug_module$master_awqos, - debug_module$master_awregion } ; + CAN_FIRE_RL_merged_1_passFlit && + !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_currentReq$port1__read = ifcs_1_noRoute_inner_currentReq$EN_port0__write ? - ifcs_1_noRoute_inner_currentReq$port0__write_1 : + merged_1_outflit$wget[170:74] : ifcs_1_noRoute_inner_currentReq ; assign ifcs_1_noRoute_inner_pendingReq$EN_port0__write = WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - merged_1_flitLeft == 8'd0 ; + CAN_FIRE_RL_merged_1_passFlit && + !merged_1_outflit$wget[171] ; assign ifcs_1_noRoute_inner_pendingReq$port1__read = ifcs_1_noRoute_inner_pendingReq$EN_port0__write || ifcs_1_noRoute_inner_pendingReq ; assign ifcs_1_noRoute_inner_pendingReq$port2__read = !CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp && ifcs_1_noRoute_inner_pendingReq$port1__read ; - assign ifcs_0_1_noRoute_currentReq$port0__write_1 = - { proc$master1_arid, - proc$master1_araddr, - proc$master1_arlen, - proc$master1_arsize, - proc$master1_arburst, - proc$master1_arlock, - proc$master1_arcache, - proc$master1_arprot, - proc$master1_arqos, - proc$master1_arregion } ; assign ifcs_0_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? - ifcs_0_1_noRoute_currentReq$port0__write_1 : + msNoSynth_0_arNoSynth_buffer_ff$D_OUT : ifcs_0_1_noRoute_currentReq ; assign ifcs_0_1_noRoute_flitCount$port0__write_1 = - { 1'd0, proc$master1_arlen } + 9'd1 ; - assign ifcs_0_1_noRoute_flitCount$port1__write_1 = - x_port1__read__h72781 - 9'd1 ; + { 1'd0, x__h94920 } + 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port1__write_1 = x__h95023 - 9'd1 ; assign ifcs_0_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ? ifcs_0_1_noRoute_flitCount$port1__write_1 : - x_port1__read__h72781 ; - assign ifcs_1_1_noRoute_currentReq$port0__write_1 = - { debug_module$master_arid, - debug_module$master_araddr, - debug_module$master_arlen, - debug_module$master_arsize, - debug_module$master_arburst, - debug_module$master_arlock, - debug_module$master_arcache, - debug_module$master_arprot, - debug_module$master_arqos, - debug_module$master_arregion } ; + x__h95023 ; assign ifcs_1_1_noRoute_currentReq$port1__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? - ifcs_1_1_noRoute_currentReq$port0__write_1 : + msNoSynth_1_arNoSynth_buffer_ff$D_OUT : ifcs_1_1_noRoute_currentReq ; assign ifcs_1_1_noRoute_flitCount$port0__write_1 = - { 1'd0, debug_module$master_arlen } + 9'd1 ; - assign ifcs_1_1_noRoute_flitCount$port1__write_1 = - x_port1__read__h75154 - 9'd1 ; + { 1'd0, x__h97519 } + 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port1__write_1 = x__h97622 - 9'd1 ; assign ifcs_1_1_noRoute_flitCount$port2__read = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ? ifcs_1_1_noRoute_flitCount$port1__write_1 : - x_port1__read__h75154 ; + x__h97622 ; // register activeSource_0 assign activeSource_0$D_IN = @@ -7290,52 +9619,52 @@ module mkCoreW(RST_N_dm_power_on_reset, // register arbiter_1_1_firstHot assign arbiter_1_1_firstHot$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 ; assign arbiter_1_1_firstHot$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect assign arbiter_1_1_lastSelect$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 ; assign arbiter_1_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_1_lastSelect_1 assign arbiter_1_1_lastSelect_1$D_IN = - IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 ; + IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 ; assign arbiter_1_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_3 ; // register arbiter_1_firstHot assign arbiter_1_firstHot$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 ; assign arbiter_1_firstHot$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_firstHot_1 assign arbiter_1_firstHot_1$D_IN = - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 ; assign arbiter_1_firstHot_1$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_1_lastSelect assign arbiter_1_lastSelect$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 ; assign arbiter_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_1 assign arbiter_1_lastSelect_1$D_IN = - IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 ; + IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 ; assign arbiter_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_1 ; // register arbiter_1_lastSelect_2 assign arbiter_1_lastSelect_2$D_IN = - IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 ; + IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 ; assign arbiter_1_lastSelect_2$EN = CAN_FIRE_RL_arbitrate_2 ; // register arbiter_firstHot assign arbiter_firstHot$D_IN = - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 ; assign arbiter_firstHot$EN = CAN_FIRE_RL_arbitrate ; // register arbiter_lastSelect assign arbiter_lastSelect$D_IN = - IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 ; + IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 ; assign arbiter_lastSelect$EN = CAN_FIRE_RL_arbitrate ; // register ifcs_0_1_noRoute_currentReq @@ -7358,9 +9687,9 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_state_1$D_IN = !MUX_ifcs_0_1_state_1$write_1__SEL_1 ; assign ifcs_0_1_state_1$EN = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && - uncached_mem_shim_rff$D_OUT[1] || + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && - !uncached_mem_shim_rff$D_OUT[1] ; + !ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_0_noRoute_inner_currentReq assign ifcs_0_noRoute_inner_currentReq$D_IN = @@ -7386,9 +9715,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_state$EN = (WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits) && - proc$master1_wlast || - WILL_FIRE_RL_ifcs_0_firstFlit && !proc$master1_wlast || - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !proc$master1_wlast ; + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 || + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; // register ifcs_0_state_1 assign ifcs_0_state_1$D_IN = 1'd0 ; @@ -7413,8 +9744,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // register ifcs_1_1_state_1 assign ifcs_1_1_state_1$D_IN = !MUX_ifcs_1_1_state_1$write_1__SEL_1 ; assign ifcs_1_1_state_1$EN = - WILL_FIRE_RL_ifcs_1_1_followFlits_1 && plic$axi4_slave_rlast || - WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && !plic$axi4_slave_rlast ; + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + !ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_1_noRoute_inner_currentReq assign ifcs_1_noRoute_inner_currentReq$D_IN = @@ -7440,10 +9773,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_state$EN = (WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits) && - debug_module$master_wlast || - WILL_FIRE_RL_ifcs_1_firstFlit && !debug_module$master_wlast || + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 || + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - !debug_module$master_wlast ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; // register ifcs_1_state_1 assign ifcs_1_state_1$D_IN = 1'd0 ; @@ -7453,9 +9787,9 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_2_1_state$D_IN = !MUX_ifcs_2_1_state$write_1__SEL_1 ; assign ifcs_2_1_state$EN = WILL_FIRE_RL_ifcs_2_1_followFlits && - proc$debug_module_mem_server_rlast || + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] || WILL_FIRE_RL_ifcs_2_1_firstFlit && - !proc$debug_module_mem_server_rlast ; + !ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; // register ifcs_2_state assign ifcs_2_state$D_IN = 1'd0 ; @@ -7463,17 +9797,21 @@ module mkCoreW(RST_N_dm_power_on_reset, // register merged_0_flitLeft assign merged_0_flitLeft$D_IN = - WILL_FIRE_RL_merged_0_genOther ? - MUX_merged_0_flitLeft$write_1__VAL_1 : - proc$master1_awlen ; - assign merged_0_flitLeft$EN = msNoSynth_0_w_dwReady$whas ; + WILL_FIRE_RL_merged_0_genFirst ? + merged_0_awff$D_OUT[28:21] : + MUX_merged_0_flitLeft$write_1__VAL_2 ; + assign merged_0_flitLeft$EN = + WILL_FIRE_RL_merged_0_genFirst || + WILL_FIRE_RL_merged_0_genOther ; // register merged_1_flitLeft assign merged_1_flitLeft$D_IN = - WILL_FIRE_RL_merged_1_genOther ? - MUX_merged_1_flitLeft$write_1__VAL_1 : - debug_module$master_awlen ; - assign merged_1_flitLeft$EN = msNoSynth_1_w_dwReady$whas ; + WILL_FIRE_RL_merged_1_genFirst ? + merged_1_awff$D_OUT[28:21] : + MUX_merged_1_flitLeft$write_1__VAL_2 ; + assign merged_1_flitLeft$EN = + WILL_FIRE_RL_merged_1_genFirst || + WILL_FIRE_RL_merged_1_genOther ; // register rg_fromhost_addr assign rg_fromhost_addr$D_IN = start_fromhost_addr ; @@ -7497,21 +9835,21 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_split_0_flitLeft$write_1__SEL_1 ? MUX_split_0_flitLeft$write_1__VAL_1 : split_0_doPut$wget[102:95] ; - assign split_0_flitLeft$EN = ssNoSynth_0_w_buffer_enqw$whas ; + assign split_0_flitLeft$EN = ssNoSynth_0_wNoSynth_buffer_enqw$whas ; // register split_1_flitLeft assign split_1_flitLeft$D_IN = MUX_split_1_flitLeft$write_1__SEL_1 ? MUX_split_1_flitLeft$write_1__VAL_1 : split_1_doPut$wget[102:95] ; - assign split_1_flitLeft$EN = ssNoSynth_1_w_buffer_enqw$whas ; + assign split_1_flitLeft$EN = ssNoSynth_1_wNoSynth_buffer_enqw$whas ; // register split_2_flitLeft assign split_2_flitLeft$D_IN = MUX_split_2_flitLeft$write_1__SEL_1 ? MUX_split_2_flitLeft$write_1__VAL_1 : split_2_doPut$wget[102:95] ; - assign split_2_flitLeft$EN = ssNoSynth_2_w_buffer_enqw$whas ; + assign split_2_flitLeft$EN = ssNoSynth_2_wNoSynth_buffer_enqw$whas ; // register state assign state$D_IN = !MUX_state$write_1__SEL_1 && !MUX_state$write_1__SEL_2 ; @@ -7553,7 +9891,7 @@ module mkCoreW(RST_N_dm_power_on_reset, assign tagController_tmp_addrOffset$D_IN = tagController_tmp_shimSlave_wff_rv$port1__read[1] ? 64'd0 : - x__h8207 ; + x__h8010 ; assign tagController_tmp_addrOffset$EN = WILL_FIRE_RL_tagController_tmp_passCacheWrite ; @@ -7631,37 +9969,27 @@ module mkCoreW(RST_N_dm_power_on_reset, assign debug_module$hart0_gpr_mem_client_response_put = proc$hart0_gpr_mem_server_response_get ; assign debug_module$hart0_reset_client_response_put = 1'd1 ; - assign debug_module$master_arready = msNoSynth_1_ar_dwReady$whas ; - assign debug_module$master_awready = CAN_FIRE_RL_merged_1_genFirst ; + assign debug_module$master_arready = + msNoSynth_1_arNoSynth_buffer_ff$FULL_N ; + assign debug_module$master_awready = + msNoSynth_1_awNoSynth_buffer_ff$FULL_N ; assign debug_module$master_bid = - msNoSynth_1_b_buffer_ff$EMPTY_N ? - msNoSynth_1_b_buffer_ff$D_OUT[5:2] : - msNoSynth_1_b_buffer_enqw$wget[5:2] ; + msNoSynth_1_bNoSynth_src_peekWire$wget[5:2] ; assign debug_module$master_bresp = - msNoSynth_1_b_buffer_ff$EMPTY_N ? - msNoSynth_1_b_buffer_ff$D_OUT[1:0] : - msNoSynth_1_b_buffer_enqw$wget[1:0] ; + msNoSynth_1_bNoSynth_src_peekWire$wget[1:0] ; + assign debug_module$master_bvalid = msNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ; assign debug_module$master_rdata = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[67:4] : - msNoSynth_1_r_buffer_enqw$wget[67:4] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[67:4] ; assign debug_module$master_rid = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[71:68] : - msNoSynth_1_r_buffer_enqw$wget[71:68] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[71:68] ; assign debug_module$master_rlast = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[1] : - msNoSynth_1_r_buffer_enqw$wget[1] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[1] ; assign debug_module$master_rresp = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[3:2] : - msNoSynth_1_r_buffer_enqw$wget[3:2] ; + msNoSynth_1_rNoSynth_src_peekWire$wget[3:2] ; assign debug_module$master_ruser = - msNoSynth_1_r_buffer_ff$EMPTY_N ? - msNoSynth_1_r_buffer_ff$D_OUT[0] : - msNoSynth_1_r_buffer_enqw$wget[0] ; - assign debug_module$master_wready = msNoSynth_1_w_dwReady$whas ; + msNoSynth_1_rNoSynth_src_peekWire$wget[0] ; + assign debug_module$master_rvalid = msNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ; + assign debug_module$master_wready = msNoSynth_1_wNoSynth_buffer_ff$FULL_N ; assign debug_module$ndm_reset_client_response_put = ndm_reset_client_response_put ; assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; @@ -7691,24 +10019,16 @@ module mkCoreW(RST_N_dm_power_on_reset, EN_ndm_reset_client_request_get ; assign debug_module$EN_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; - assign debug_module$master_bvalid = CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; - assign debug_module$master_rvalid = CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; // submodule dm_hart0_reset_controller assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; // submodule ifcs_0_1_innerReq assign ifcs_0_1_innerReq$D_IN = - { fatReq_arid__h72223, - proc$master1_araddr, - proc$master1_arlen, - proc$master1_arsize, - proc$master1_arburst, - proc$master1_arlock, - proc$master1_arcache, - proc$master1_arprot, - proc$master1_arqos, - proc$master1_arregion } ; + { fatReq_arid__h94342, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:0] : + proc$master1_ar_peek[92:0] } ; assign ifcs_0_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_1_followFlits || WILL_FIRE_RL_ifcs_0_1_firstFlit ; @@ -7719,16 +10039,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_1_innerRoute assign ifcs_0_1_innerRoute$D_IN = - { !proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845, - (proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - !proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850, - (proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - (proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850) } ; + { !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218, + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223, + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) } ; assign ifcs_0_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit ; assign ifcs_0_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || @@ -7739,14 +10059,15 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_noRouteRsp$D_IN = { ifcs_0_1_noRoute_currentReq$port1__read[96:93], 66'h2AAAAAAAAAAAAAAAB, - x_port1__read__h72781 == 9'd1, + x__h95023 == 9'd1, 1'h0 } ; assign ifcs_0_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; - assign ifcs_0_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_0_1_noRouteRsp$DEQ = + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; assign ifcs_0_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_1_routeBack - assign ifcs_0_1_routeBack$D_IN = 2'd1 << uncached_mem_shim_rff$D_OUT[72] ; + assign ifcs_0_1_routeBack$D_IN = 2'd1 << x__h98415[4] ; assign ifcs_0_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; assign ifcs_0_1_routeBack$DEQ = WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[1] || @@ -7755,8 +10076,12 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_1_routeBack$CLR = 1'b0 ; // submodule ifcs_0_1_rspBack - assign ifcs_0_1_rspBack$D_IN = uncached_mem_shim_rff$D_OUT[71:0] ; - assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_r_dwReady$whas ; + assign ifcs_0_1_rspBack$D_IN = + { x__h98415[3:0], + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[67:0] : + uncached_mem_shim_rff$D_OUT[67:0] } ; + assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; assign ifcs_0_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_7 ; @@ -7764,21 +10089,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_innerReq assign ifcs_0_innerReq$D_IN = - { merged_0_flitLeft != 8'd0, - a_awid__h38523, - proc$master1_awaddr, - proc$master1_awlen, - proc$master1_awsize, - proc$master1_awburst, - proc$master1_awlock, - proc$master1_awcache, - proc$master1_awprot, - proc$master1_awqos, - proc$master1_awregion, - proc$master1_wdata, - proc$master1_wstrb, - proc$master1_wlast, - 1'd0 } ; + { !CAN_FIRE_RL_merged_0_passFlit || merged_0_outflit$wget[171], + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 } ; assign ifcs_0_innerReq$ENQ = WILL_FIRE_RL_ifcs_0_followFlits || WILL_FIRE_RL_ifcs_0_firstFlit ; @@ -7789,16 +10101,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_0_innerRoute assign ifcs_0_innerRoute$D_IN = - { !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195, - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203, - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203) } ; + { !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519, + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527, + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) } ; assign ifcs_0_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit ; assign ifcs_0_innerRoute$DEQ = WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[1] || @@ -7810,11 +10122,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_noRouteRsp$D_IN = { ifcs_0_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_0_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; - assign ifcs_0_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_0_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; assign ifcs_0_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_0_routeBack - assign ifcs_0_routeBack$D_IN = 2'd1 << uncached_mem_shim_bff$D_OUT[6] ; + assign ifcs_0_routeBack$D_IN = 2'd1 << x__h62625[4] ; assign ifcs_0_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; assign ifcs_0_routeBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || @@ -7822,8 +10134,12 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_0_routeBack$CLR = 1'b0 ; // submodule ifcs_0_rspBack - assign ifcs_0_rspBack$D_IN = uncached_mem_shim_bff$D_OUT[5:0] ; - assign ifcs_0_rspBack$ENQ = ssNoSynth_0_b_dwReady$whas ; + assign ifcs_0_rspBack$D_IN = + { x__h62625[3:0], + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[1:0] : + uncached_mem_shim_bff$D_OUT[1:0] } ; + assign ifcs_0_rspBack$ENQ = ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; assign ifcs_0_rspBack$DEQ = WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || WILL_FIRE_RL_burst_2 ; @@ -7831,16 +10147,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_innerReq assign ifcs_1_1_innerReq$D_IN = - { fatReq_arid__h74597, - debug_module$master_araddr, - debug_module$master_arlen, - debug_module$master_arsize, - debug_module$master_arburst, - debug_module$master_arlock, - debug_module$master_arcache, - debug_module$master_arprot, - debug_module$master_arqos, - debug_module$master_arregion } ; + { fatReq_arid__h96944, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:0] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[92:0] } ; assign ifcs_1_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_1_followFlits || WILL_FIRE_RL_ifcs_1_1_firstFlit ; @@ -7851,16 +10161,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_innerRoute assign ifcs_1_1_innerRoute$D_IN = - { !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932, - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937, - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937) } ; + { !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313, + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318, + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) } ; assign ifcs_1_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit ; assign ifcs_1_1_innerRoute$DEQ = WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || @@ -7871,14 +10181,15 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_1_noRouteRsp$D_IN = { ifcs_1_1_noRoute_currentReq$port1__read[96:93], 66'h2AAAAAAAAAAAAAAAB, - x_port1__read__h75154 == 9'd1, + x__h97622 == 9'd1, 1'h0 } ; assign ifcs_1_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; - assign ifcs_1_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ifcs_1_1_noRouteRsp$DEQ = + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; assign ifcs_1_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_1_routeBack - assign ifcs_1_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_rid[4] ; + assign ifcs_1_1_routeBack$D_IN = 2'd1 << x__h99370[4] ; assign ifcs_1_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; assign ifcs_1_1_routeBack$DEQ = WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[1] || @@ -7888,12 +10199,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_1_rspBack assign ifcs_1_1_rspBack$D_IN = - { plic$axi4_slave_rid[3:0], - plic$axi4_slave_rdata, - plic$axi4_slave_rresp, - plic$axi4_slave_rlast, - plic$axi4_slave_ruser } ; - assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_r_dwReady$whas ; + { x__h99370[3:0], + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[67:0] : + ssNoSynth_1_rNoSynth_buffer_enqw$wget[67:0] } ; + assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; assign ifcs_1_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_8 ; @@ -7901,21 +10211,8 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_innerReq assign ifcs_1_innerReq$D_IN = - { merged_1_flitLeft != 8'd0, - a_awid__h41194, - debug_module$master_awaddr, - debug_module$master_awlen, - debug_module$master_awsize, - debug_module$master_awburst, - debug_module$master_awlock, - debug_module$master_awcache, - debug_module$master_awprot, - debug_module$master_awqos, - debug_module$master_awregion, - debug_module$master_wdata, - debug_module$master_wstrb, - debug_module$master_wlast, - debug_module$master_wuser } ; + { !CAN_FIRE_RL_merged_1_passFlit || merged_1_outflit$wget[171], + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 } ; assign ifcs_1_innerReq$ENQ = WILL_FIRE_RL_ifcs_1_followFlits || WILL_FIRE_RL_ifcs_1_firstFlit ; @@ -7926,16 +10223,16 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_innerRoute assign ifcs_1_innerRoute$D_IN = - { !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297, - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302, - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302) } ; + { !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616, + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621, + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) } ; assign ifcs_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit ; assign ifcs_1_innerRoute$DEQ = WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[1] || @@ -7947,11 +10244,11 @@ module mkCoreW(RST_N_dm_power_on_reset, assign ifcs_1_noRouteRsp$D_IN = { ifcs_1_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; assign ifcs_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; - assign ifcs_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign ifcs_1_noRouteRsp$DEQ = WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; assign ifcs_1_noRouteRsp$CLR = 1'b0 ; // submodule ifcs_1_routeBack - assign ifcs_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_bid[4] ; + assign ifcs_1_routeBack$D_IN = 2'd1 << x__h63516[4] ; assign ifcs_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; assign ifcs_1_routeBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || @@ -7960,16 +10257,18 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_1_rspBack assign ifcs_1_rspBack$D_IN = - { plic$axi4_slave_bid[3:0], plic$axi4_slave_bresp } ; - assign ifcs_1_rspBack$ENQ = ssNoSynth_1_b_dwReady$whas ; + { x__h63516[3:0], + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[1:0] : + ssNoSynth_1_bNoSynth_buffer_enqw$wget[1:0] } ; + assign ifcs_1_rspBack$ENQ = ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; assign ifcs_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_3 ; assign ifcs_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_1_routeBack - assign ifcs_2_1_routeBack$D_IN = - 2'd1 << proc$debug_module_mem_server_rid[4] ; + assign ifcs_2_1_routeBack$D_IN = 2'd1 << x__h100325[4] ; assign ifcs_2_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_1_firstFlit ; assign ifcs_2_1_routeBack$DEQ = WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[1] || @@ -7979,19 +10278,18 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_2_1_rspBack assign ifcs_2_1_rspBack$D_IN = - { proc$debug_module_mem_server_rid[3:0], - proc$debug_module_mem_server_rdata, - proc$debug_module_mem_server_rresp, - proc$debug_module_mem_server_rlast, - proc$debug_module_mem_server_ruser } ; - assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_r_dwReady$whas ; + { x__h100325[3:0], + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[67:0] : + ssNoSynth_2_rNoSynth_buffer_enqw$wget[67:0] } ; + assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; assign ifcs_2_1_rspBack$DEQ = WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N || WILL_FIRE_RL_burst_9 ; assign ifcs_2_1_rspBack$CLR = 1'b0 ; // submodule ifcs_2_routeBack - assign ifcs_2_routeBack$D_IN = 2'd1 << proc$debug_module_mem_server_bid[4] ; + assign ifcs_2_routeBack$D_IN = 2'd1 << x__h64407[4] ; assign ifcs_2_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_firstFlit ; assign ifcs_2_routeBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || @@ -8000,165 +10298,245 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule ifcs_2_rspBack assign ifcs_2_rspBack$D_IN = - { proc$debug_module_mem_server_bid[3:0], - proc$debug_module_mem_server_bresp } ; - assign ifcs_2_rspBack$ENQ = ssNoSynth_2_b_dwReady$whas ; + { x__h64407[3:0], + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[1:0] : + ssNoSynth_2_bNoSynth_buffer_enqw$wget[1:0] } ; + assign ifcs_2_rspBack$ENQ = ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; assign ifcs_2_rspBack$DEQ = WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || WILL_FIRE_RL_burst_4 ; assign ifcs_2_rspBack$CLR = 1'b0 ; - // submodule msNoSynth_0_b_buffer_ff - assign msNoSynth_0_b_buffer_ff$D_IN = msNoSynth_0_b_buffer_enqw$wget ; - assign msNoSynth_0_b_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; - assign msNoSynth_0_b_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; - assign msNoSynth_0_b_buffer_ff$CLR = 1'b0 ; + // submodule merged_0_awff + assign merged_0_awff$D_IN = + msNoSynth_0_awNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_awNoSynth_buffer_ff$D_OUT : + proc$master1_aw_peek ; + assign merged_0_awff$ENQ = CAN_FIRE_RL_merged_0_awFlit ; + assign merged_0_awff$DEQ = CAN_FIRE_RL_merged_0_genFirst ; + assign merged_0_awff$CLR = 1'b0 ; - // submodule msNoSynth_0_b_buffer_firstValid - assign msNoSynth_0_b_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_0_b_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + // submodule merged_0_wff + assign merged_0_wff$D_IN = + msNoSynth_0_wNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_wNoSynth_buffer_ff$D_OUT : + proc_uncached_wSynth_src_peekWire$wget ; + assign merged_0_wff$ENQ = CAN_FIRE_RL_merged_0_wFlit ; + assign merged_0_wff$DEQ = + WILL_FIRE_RL_merged_0_genOther || + WILL_FIRE_RL_merged_0_genFirst ; + assign merged_0_wff$CLR = 1'b0 ; - // submodule msNoSynth_0_r_buffer_ff - assign msNoSynth_0_r_buffer_ff$D_IN = msNoSynth_0_r_buffer_enqw$wget ; - assign msNoSynth_0_r_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; - assign msNoSynth_0_r_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; - assign msNoSynth_0_r_buffer_ff$CLR = 1'b0 ; + // submodule merged_1_awff + assign merged_1_awff$D_IN = + msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_awNoSynth_buffer_ff$D_OUT : + msNoSynth_1_awNoSynth_buffer_enqw$wget ; + assign merged_1_awff$ENQ = CAN_FIRE_RL_merged_1_awFlit ; + assign merged_1_awff$DEQ = CAN_FIRE_RL_merged_1_genFirst ; + assign merged_1_awff$CLR = 1'b0 ; - // submodule msNoSynth_0_r_buffer_firstValid - assign msNoSynth_0_r_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_0_r_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; + // submodule merged_1_wff + assign merged_1_wff$D_IN = + msNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_wNoSynth_buffer_ff$D_OUT : + msNoSynth_1_wNoSynth_buffer_enqw$wget ; + assign merged_1_wff$ENQ = CAN_FIRE_RL_merged_1_wFlit ; + assign merged_1_wff$DEQ = + WILL_FIRE_RL_merged_1_genOther || + WILL_FIRE_RL_merged_1_genFirst ; + assign merged_1_wff$CLR = 1'b0 ; - // submodule msNoSynth_1_b_buffer_ff - assign msNoSynth_1_b_buffer_ff$D_IN = msNoSynth_1_b_buffer_enqw$wget ; - assign msNoSynth_1_b_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; - assign msNoSynth_1_b_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; - assign msNoSynth_1_b_buffer_ff$CLR = 1'b0 ; + // submodule msNoSynth_0_arNoSynth_buffer_ff + assign msNoSynth_0_arNoSynth_buffer_ff$D_IN = proc$master1_ar_peek ; + assign msNoSynth_0_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_enqueue ; + assign msNoSynth_0_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_arNoSynth_buffer_dequeue ; + assign msNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule msNoSynth_1_b_buffer_firstValid - assign msNoSynth_1_b_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_1_b_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + // submodule msNoSynth_0_arNoSynth_buffer_firstValid + assign msNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_arNoSynth_buffer_firstValid$EN = + msNoSynth_0_arNoSynth_buffer_dequeueing$whas ; - // submodule msNoSynth_1_r_buffer_ff - assign msNoSynth_1_r_buffer_ff$D_IN = msNoSynth_1_r_buffer_enqw$wget ; - assign msNoSynth_1_r_buffer_ff$ENQ = - CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; - assign msNoSynth_1_r_buffer_ff$DEQ = - CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; - assign msNoSynth_1_r_buffer_ff$CLR = 1'b0 ; + // submodule msNoSynth_0_awNoSynth_buffer_ff + assign msNoSynth_0_awNoSynth_buffer_ff$D_IN = proc$master1_aw_peek ; + assign msNoSynth_0_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_enqueue ; + assign msNoSynth_0_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_awNoSynth_buffer_dequeue ; + assign msNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule msNoSynth_1_r_buffer_firstValid - assign msNoSynth_1_r_buffer_firstValid$D_IN = 1'd1 ; - assign msNoSynth_1_r_buffer_firstValid$EN = - CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; + // submodule msNoSynth_0_awNoSynth_buffer_firstValid + assign msNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_0_awFlit ; + + // submodule msNoSynth_0_bNoSynth_buffer_ff + assign msNoSynth_0_bNoSynth_buffer_ff$D_IN = + msNoSynth_0_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_enqueue ; + assign msNoSynth_0_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_buffer_dequeue ; + assign msNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_bNoSynth_buffer_firstValid + assign msNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_bNoSynth_src_doDrop ; + + // submodule msNoSynth_0_rNoSynth_buffer_ff + assign msNoSynth_0_rNoSynth_buffer_ff$D_IN = + msNoSynth_0_rNoSynth_buffer_enqw$wget ; + assign msNoSynth_0_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_enqueue ; + assign msNoSynth_0_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_buffer_dequeue ; + assign msNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_rNoSynth_buffer_firstValid + assign msNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_rNoSynth_src_doDrop ; + + // submodule msNoSynth_0_wNoSynth_buffer_ff + assign msNoSynth_0_wNoSynth_buffer_ff$D_IN = + proc_uncached_wSynth_src_peekWire$wget ; + assign msNoSynth_0_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_enqueue ; + assign msNoSynth_0_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_wNoSynth_buffer_dequeue ; + assign msNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_wNoSynth_buffer_firstValid + assign msNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_0_wFlit ; + + // submodule msNoSynth_1_arNoSynth_buffer_ff + assign msNoSynth_1_arNoSynth_buffer_ff$D_IN = + msNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_enqueue ; + assign msNoSynth_1_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_arNoSynth_buffer_dequeue ; + assign msNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_arNoSynth_buffer_firstValid + assign msNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_arNoSynth_buffer_firstValid$EN = + msNoSynth_1_arNoSynth_buffer_dequeueing$whas ; + + // submodule msNoSynth_1_awNoSynth_buffer_ff + assign msNoSynth_1_awNoSynth_buffer_ff$D_IN = + msNoSynth_1_awNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; + assign msNoSynth_1_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_dequeue ; + assign msNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_awNoSynth_buffer_firstValid + assign msNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_1_awFlit ; + + // submodule msNoSynth_1_bNoSynth_buffer_ff + assign msNoSynth_1_bNoSynth_buffer_ff$D_IN = + msNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_enqueue ; + assign msNoSynth_1_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_buffer_dequeue ; + assign msNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_bNoSynth_buffer_firstValid + assign msNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_bNoSynth_src_doDrop ; + + // submodule msNoSynth_1_rNoSynth_buffer_ff + assign msNoSynth_1_rNoSynth_buffer_ff$D_IN = + msNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_enqueue ; + assign msNoSynth_1_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_buffer_dequeue ; + assign msNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_rNoSynth_buffer_firstValid + assign msNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_rNoSynth_src_doDrop ; + + // submodule msNoSynth_1_wNoSynth_buffer_ff + assign msNoSynth_1_wNoSynth_buffer_ff$D_IN = + msNoSynth_1_wNoSynth_buffer_enqw$wget ; + assign msNoSynth_1_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_enqueue ; + assign msNoSynth_1_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_wNoSynth_buffer_dequeue ; + assign msNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_wNoSynth_buffer_firstValid + assign msNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_merged_1_wFlit ; // submodule plic assign plic$axi4_slave_araddr = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[92:29] : - ssNoSynth_1_ar_buffer_enqw$wget[92:29] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_arburst = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[17:16] : - ssNoSynth_1_ar_buffer_enqw$wget[17:16] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_arcache = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[14:11] : - ssNoSynth_1_ar_buffer_enqw$wget[14:11] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_arid = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[97:93] : - ssNoSynth_1_ar_buffer_enqw$wget[97:93] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_arlen = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[28:21] : - ssNoSynth_1_ar_buffer_enqw$wget[28:21] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_arlock = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[15] : - ssNoSynth_1_ar_buffer_enqw$wget[15] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_arprot = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[10:8] : - ssNoSynth_1_ar_buffer_enqw$wget[10:8] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_arqos = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[7:4] : - ssNoSynth_1_ar_buffer_enqw$wget[7:4] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_arregion = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[3:0] : - ssNoSynth_1_ar_buffer_enqw$wget[3:0] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_arsize = - ssNoSynth_1_ar_buffer_ff$EMPTY_N ? - ssNoSynth_1_ar_buffer_ff$D_OUT[20:18] : - ssNoSynth_1_ar_buffer_enqw$wget[20:18] ; + ssNoSynth_1_arNoSynth_src_peekWire$wget[20:18] ; + assign plic$axi4_slave_arvalid = ssNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ; assign plic$axi4_slave_awaddr = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[92:29] : - ssNoSynth_1_aw_buffer_enqw$wget[92:29] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[92:29] ; assign plic$axi4_slave_awburst = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[17:16] : - ssNoSynth_1_aw_buffer_enqw$wget[17:16] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[17:16] ; assign plic$axi4_slave_awcache = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[14:11] : - ssNoSynth_1_aw_buffer_enqw$wget[14:11] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[14:11] ; assign plic$axi4_slave_awid = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[97:93] : - ssNoSynth_1_aw_buffer_enqw$wget[97:93] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[97:93] ; assign plic$axi4_slave_awlen = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[28:21] : - ssNoSynth_1_aw_buffer_enqw$wget[28:21] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[28:21] ; assign plic$axi4_slave_awlock = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[15] : - ssNoSynth_1_aw_buffer_enqw$wget[15] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[15] ; assign plic$axi4_slave_awprot = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[10:8] : - ssNoSynth_1_aw_buffer_enqw$wget[10:8] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[10:8] ; assign plic$axi4_slave_awqos = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[7:4] : - ssNoSynth_1_aw_buffer_enqw$wget[7:4] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[7:4] ; assign plic$axi4_slave_awregion = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[3:0] : - ssNoSynth_1_aw_buffer_enqw$wget[3:0] ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[3:0] ; assign plic$axi4_slave_awsize = - ssNoSynth_1_aw_buffer_ff$EMPTY_N ? - ssNoSynth_1_aw_buffer_ff$D_OUT[20:18] : - ssNoSynth_1_aw_buffer_enqw$wget[20:18] ; - assign plic$axi4_slave_bready = ssNoSynth_1_b_dwReady$whas ; - assign plic$axi4_slave_rready = ssNoSynth_1_r_dwReady$whas ; + ssNoSynth_1_awNoSynth_src_peekWire$wget[20:18] ; + assign plic$axi4_slave_awvalid = ssNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ; + assign plic$axi4_slave_bready = ssNoSynth_1_bNoSynth_buffer_ff$FULL_N ; + assign plic$axi4_slave_rready = ssNoSynth_1_rNoSynth_buffer_ff$FULL_N ; assign plic$axi4_slave_wdata = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[73:10] : - ssNoSynth_1_w_buffer_enqw$wget[73:10] ; - assign plic$axi4_slave_wlast = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[1] : - ssNoSynth_1_w_buffer_enqw$wget[1] ; - assign plic$axi4_slave_wstrb = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[9:2] : - ssNoSynth_1_w_buffer_enqw$wget[9:2] ; - assign plic$axi4_slave_wuser = - ssNoSynth_1_w_buffer_ff$EMPTY_N ? - ssNoSynth_1_w_buffer_ff$D_OUT[0] : - ssNoSynth_1_w_buffer_enqw$wget[0] ; + ssNoSynth_1_wNoSynth_src_peekWire$wget[73:10] ; + assign plic$axi4_slave_wlast = ssNoSynth_1_wNoSynth_src_peekWire$wget[1] ; + assign plic$axi4_slave_wstrb = ssNoSynth_1_wNoSynth_src_peekWire$wget[9:2] ; + assign plic$axi4_slave_wuser = ssNoSynth_1_wNoSynth_src_peekWire$wget[0] ; + assign plic$axi4_slave_wvalid = ssNoSynth_1_wNoSynth_buffer_ff$EMPTY_N ; assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_range[127:64] ; assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_range[127:64] + @@ -8201,109 +10579,66 @@ module mkCoreW(RST_N_dm_power_on_reset, assign plic$EN_server_reset_request_put = 1'b0 ; assign plic$EN_server_reset_response_get = 1'b0 ; assign plic$EN_set_addr_map = EN_start ; - assign plic$axi4_slave_awvalid = CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; - assign plic$axi4_slave_wvalid = CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; - assign plic$axi4_slave_arvalid = CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; // submodule proc assign proc$debug_module_mem_server_araddr = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[92:29] : - ssNoSynth_2_ar_buffer_enqw$wget[92:29] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_arburst = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[17:16] : - ssNoSynth_2_ar_buffer_enqw$wget[17:16] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_arcache = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[14:11] : - ssNoSynth_2_ar_buffer_enqw$wget[14:11] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_arid = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[97:93] : - ssNoSynth_2_ar_buffer_enqw$wget[97:93] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_arlen = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[28:21] : - ssNoSynth_2_ar_buffer_enqw$wget[28:21] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_arlock = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[15] : - ssNoSynth_2_ar_buffer_enqw$wget[15] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_arprot = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[10:8] : - ssNoSynth_2_ar_buffer_enqw$wget[10:8] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_arqos = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[7:4] : - ssNoSynth_2_ar_buffer_enqw$wget[7:4] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_arregion = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[3:0] : - ssNoSynth_2_ar_buffer_enqw$wget[3:0] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_arsize = - ssNoSynth_2_ar_buffer_ff$EMPTY_N ? - ssNoSynth_2_ar_buffer_ff$D_OUT[20:18] : - ssNoSynth_2_ar_buffer_enqw$wget[20:18] ; + ssNoSynth_2_arNoSynth_src_peekWire$wget[20:18] ; + assign proc$debug_module_mem_server_arvalid = + ssNoSynth_2_arNoSynth_buffer_ff$EMPTY_N ; assign proc$debug_module_mem_server_awaddr = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[92:29] : - ssNoSynth_2_aw_buffer_enqw$wget[92:29] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[92:29] ; assign proc$debug_module_mem_server_awburst = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[17:16] : - ssNoSynth_2_aw_buffer_enqw$wget[17:16] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[17:16] ; assign proc$debug_module_mem_server_awcache = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[14:11] : - ssNoSynth_2_aw_buffer_enqw$wget[14:11] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[14:11] ; assign proc$debug_module_mem_server_awid = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[97:93] : - ssNoSynth_2_aw_buffer_enqw$wget[97:93] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[97:93] ; assign proc$debug_module_mem_server_awlen = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[28:21] : - ssNoSynth_2_aw_buffer_enqw$wget[28:21] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[28:21] ; assign proc$debug_module_mem_server_awlock = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[15] : - ssNoSynth_2_aw_buffer_enqw$wget[15] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[15] ; assign proc$debug_module_mem_server_awprot = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[10:8] : - ssNoSynth_2_aw_buffer_enqw$wget[10:8] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[10:8] ; assign proc$debug_module_mem_server_awqos = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[7:4] : - ssNoSynth_2_aw_buffer_enqw$wget[7:4] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[7:4] ; assign proc$debug_module_mem_server_awregion = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[3:0] : - ssNoSynth_2_aw_buffer_enqw$wget[3:0] ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[3:0] ; assign proc$debug_module_mem_server_awsize = - ssNoSynth_2_aw_buffer_ff$EMPTY_N ? - ssNoSynth_2_aw_buffer_ff$D_OUT[20:18] : - ssNoSynth_2_aw_buffer_enqw$wget[20:18] ; - assign proc$debug_module_mem_server_bready = ssNoSynth_2_b_dwReady$whas ; - assign proc$debug_module_mem_server_rready = ssNoSynth_2_r_dwReady$whas ; + ssNoSynth_2_awNoSynth_src_peekWire$wget[20:18] ; + assign proc$debug_module_mem_server_awvalid = + ssNoSynth_2_awNoSynth_buffer_ff$EMPTY_N ; + assign proc$debug_module_mem_server_bready = + ssNoSynth_2_bNoSynth_buffer_ff$FULL_N ; + assign proc$debug_module_mem_server_rready = + ssNoSynth_2_rNoSynth_buffer_ff$FULL_N ; assign proc$debug_module_mem_server_wdata = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[73:10] : - ssNoSynth_2_w_buffer_enqw$wget[73:10] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[73:10] ; assign proc$debug_module_mem_server_wlast = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[1] : - ssNoSynth_2_w_buffer_enqw$wget[1] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[1] ; assign proc$debug_module_mem_server_wstrb = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[9:2] : - ssNoSynth_2_w_buffer_enqw$wget[9:2] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[9:2] ; assign proc$debug_module_mem_server_wuser = - ssNoSynth_2_w_buffer_ff$EMPTY_N ? - ssNoSynth_2_w_buffer_ff$D_OUT[0] : - ssNoSynth_2_w_buffer_enqw$wget[0] ; + ssNoSynth_2_wNoSynth_src_peekWire$wget[0] ; + assign proc$debug_module_mem_server_wvalid = + ssNoSynth_2_wNoSynth_buffer_ff$EMPTY_N ; assign proc$hart0_csr_mem_server_request_put = debug_module$hart0_csr_mem_client_request_get ; assign proc$hart0_fpr_mem_server_request_put = 70'h0 ; @@ -8314,71 +10649,21 @@ module mkCoreW(RST_N_dm_power_on_reset, debug_module$hart0_client_run_halt_request_get ; assign proc$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign proc$master0_arready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_mkConnectionGetPut ; - assign proc$master0_awready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_mkConnectionGetPut ; - assign proc$master0_bid = - tmp2_b_buffer_ff$EMPTY_N ? - tmp2_b_buffer_ff$D_OUT[6:2] : - tmp2_b_buffer_enqw$wget[6:2] ; - assign proc$master0_bresp = - tmp2_b_buffer_ff$EMPTY_N ? - tmp2_b_buffer_ff$D_OUT[1:0] : - tmp2_b_buffer_enqw$wget[1:0] ; - assign proc$master0_rdata = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[67:4] : - tmp2_r_buffer_enqw$wget[67:4] ; - assign proc$master0_rid = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[72:68] : - tmp2_r_buffer_enqw$wget[72:68] ; - assign proc$master0_rlast = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[1] : - tmp2_r_buffer_enqw$wget[1] ; - assign proc$master0_rresp = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[3:2] : - tmp2_r_buffer_enqw$wget[3:2] ; - assign proc$master0_ruser = - tmp2_r_buffer_ff$EMPTY_N ? - tmp2_r_buffer_ff$D_OUT[0] : - tmp2_r_buffer_enqw$wget[0] ; - assign proc$master0_wready = - CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_mkConnectionGetPut ; - assign proc$master1_arready = tmp0_ar_dwReady$whas ; - assign proc$master1_awready = tmp0_aw_dwReady$whas ; - assign proc$master1_bid = - tmp0_b_buffer_ff$EMPTY_N ? - tmp0_b_buffer_ff$D_OUT[5:2] : - tmp0_b_buffer_enqw$wget[5:2] ; - assign proc$master1_bresp = - tmp0_b_buffer_ff$EMPTY_N ? - tmp0_b_buffer_ff$D_OUT[1:0] : - tmp0_b_buffer_enqw$wget[1:0] ; - assign proc$master1_rdata = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[67:4] : - tmp0_r_buffer_enqw$wget[67:4] ; - assign proc$master1_rid = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[71:68] : - tmp0_r_buffer_enqw$wget[71:68] ; - assign proc$master1_rlast = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[1] : - tmp0_r_buffer_enqw$wget[1] ; - assign proc$master1_rresp = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[3:2] : - tmp0_r_buffer_enqw$wget[3:2] ; - assign proc$master1_ruser = - tmp0_r_buffer_ff$EMPTY_N ? - tmp0_r_buffer_ff$D_OUT[0] : - tmp0_r_buffer_enqw$wget[0] ; - assign proc$master1_wready = tmp0_w_dwReady$whas ; + assign proc$master0_arready = tmp2_arNoSynth_buffer_ff$FULL_N ; + assign proc$master0_awready = tmp2_awNoSynth_buffer_ff$FULL_N ; + assign proc$master0_bid = tmp2_bNoSynth_src_peekWire$wget[6:2] ; + assign proc$master0_bresp = tmp2_bNoSynth_src_peekWire$wget[1:0] ; + assign proc$master0_bvalid = tmp2_bNoSynth_buffer_ff$EMPTY_N ; + assign proc$master0_rdata = tmp2_rNoSynth_src_peekWire$wget[67:4] ; + assign proc$master0_rid = tmp2_rNoSynth_src_peekWire$wget[72:68] ; + assign proc$master0_rlast = tmp2_rNoSynth_src_peekWire$wget[1] ; + assign proc$master0_rresp = tmp2_rNoSynth_src_peekWire$wget[3:2] ; + assign proc$master0_ruser = tmp2_rNoSynth_src_peekWire$wget[0] ; + assign proc$master0_rvalid = tmp2_rNoSynth_buffer_ff$EMPTY_N ; + assign proc$master0_wready = tmp2_wNoSynth_buffer_ff$FULL_N ; + assign proc$master1_b_put_val = proc_uncached_bSynth_snk_putWire$wget ; + assign proc$master1_r_put_val = + { proc_uncached_rSynth_snk_putWire$wget[71:1], 1'd0 } ; assign proc$non_maskable_interrupt_req_set_not_clear = 1'd0 ; assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; @@ -8395,17 +10680,15 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1 || EN_start ; - assign proc$master0_bvalid = CAN_FIRE_RL_tmp2_b_forwardFlit ; - assign proc$master0_rvalid = CAN_FIRE_RL_tmp2_r_forwardFlit ; - assign proc$master1_bvalid = CAN_FIRE_RL_tmp0_b_forwardFlit ; - assign proc$master1_rvalid = CAN_FIRE_RL_tmp0_r_forwardFlit ; + assign proc$EN_master1_aw_drop = + CAN_FIRE_RL_proc_uncached_awSynth_src_doDrop ; + assign proc$EN_master1_w_drop = + CAN_FIRE_RL_proc_uncached_wSynth_src_doDrop ; + assign proc$EN_master1_b_put = CAN_FIRE_RL_proc_uncached_bSynth_snk_doPut ; + assign proc$EN_master1_ar_drop = + CAN_FIRE_RL_proc_uncached_arSynth_src_doDrop ; + assign proc$EN_master1_r_put = CAN_FIRE_RL_proc_uncached_rSynth_snk_doPut ; assign proc$EN_set_verbosity = EN_set_verbosity ; - assign proc$debug_module_mem_server_awvalid = - CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; - assign proc$debug_module_mem_server_wvalid = - CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; - assign proc$debug_module_mem_server_arvalid = - CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; assign proc$EN_hart0_run_halt_server_request_put = CAN_FIRE_RL_ClientServerRequest ; assign proc$EN_hart0_run_halt_server_response_get = @@ -8428,122 +10711,207 @@ module mkCoreW(RST_N_dm_power_on_reset, assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - // submodule ssNoSynth_0_ar_buffer_ff - assign ssNoSynth_0_ar_buffer_ff$D_IN = ssNoSynth_0_ar_buffer_enqw$wget ; - assign ssNoSynth_0_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; - assign ssNoSynth_0_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; - assign ssNoSynth_0_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_arNoSynth_buffer_ff + assign ssNoSynth_0_arNoSynth_buffer_ff$D_IN = + ssNoSynth_0_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_0_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_enqueue ; + assign ssNoSynth_0_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_buffer_dequeue ; + assign ssNoSynth_0_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_ar_buffer_firstValid - assign ssNoSynth_0_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_ar_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + // submodule ssNoSynth_0_arNoSynth_buffer_firstValid + assign ssNoSynth_0_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_arNoSynth_src_doDrop ; - // submodule ssNoSynth_0_aw_buffer_ff - assign ssNoSynth_0_aw_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; - assign ssNoSynth_0_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; - assign ssNoSynth_0_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; - assign ssNoSynth_0_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_awNoSynth_buffer_ff + assign ssNoSynth_0_awNoSynth_buffer_ff$D_IN = split_0_doPut$wget[171:74] ; + assign ssNoSynth_0_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_enqueue ; + assign ssNoSynth_0_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_buffer_dequeue ; + assign ssNoSynth_0_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_aw_buffer_firstValid - assign ssNoSynth_0_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_aw_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + // submodule ssNoSynth_0_awNoSynth_buffer_firstValid + assign ssNoSynth_0_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_awNoSynth_src_doDrop ; - // submodule ssNoSynth_0_w_buffer_ff - assign ssNoSynth_0_w_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; - assign ssNoSynth_0_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; - assign ssNoSynth_0_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; - assign ssNoSynth_0_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_bNoSynth_buffer_ff + assign ssNoSynth_0_bNoSynth_buffer_ff$D_IN = uncached_mem_shim_bff$D_OUT ; + assign ssNoSynth_0_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_enqueue ; + assign ssNoSynth_0_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_bNoSynth_buffer_dequeue ; + assign ssNoSynth_0_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_0_w_buffer_firstValid - assign ssNoSynth_0_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_0_w_buffer_firstValid$EN = - WILL_FIRE_RL_ssNoSynth_0_w_dropFlit ; + // submodule ssNoSynth_0_bNoSynth_buffer_firstValid + assign ssNoSynth_0_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_bNoSynth_buffer_firstValid$EN = + ssNoSynth_0_bNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_1_ar_buffer_ff - assign ssNoSynth_1_ar_buffer_ff$D_IN = ssNoSynth_1_ar_buffer_enqw$wget ; - assign ssNoSynth_1_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; - assign ssNoSynth_1_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; - assign ssNoSynth_1_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_rNoSynth_buffer_ff + assign ssNoSynth_0_rNoSynth_buffer_ff$D_IN = uncached_mem_shim_rff$D_OUT ; + assign ssNoSynth_0_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_enqueue ; + assign ssNoSynth_0_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_rNoSynth_buffer_dequeue ; + assign ssNoSynth_0_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_ar_buffer_firstValid - assign ssNoSynth_1_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_ar_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + // submodule ssNoSynth_0_rNoSynth_buffer_firstValid + assign ssNoSynth_0_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_rNoSynth_buffer_firstValid$EN = + ssNoSynth_0_rNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_1_aw_buffer_ff - assign ssNoSynth_1_aw_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; - assign ssNoSynth_1_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; - assign ssNoSynth_1_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; - assign ssNoSynth_1_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_0_wNoSynth_buffer_ff + assign ssNoSynth_0_wNoSynth_buffer_ff$D_IN = split_0_doPut$wget[73:0] ; + assign ssNoSynth_0_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_enqueue ; + assign ssNoSynth_0_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_buffer_dequeue ; + assign ssNoSynth_0_wNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_aw_buffer_firstValid - assign ssNoSynth_1_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_aw_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + // submodule ssNoSynth_0_wNoSynth_buffer_firstValid + assign ssNoSynth_0_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_wNoSynth_src_doDrop ; - // submodule ssNoSynth_1_w_buffer_ff - assign ssNoSynth_1_w_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; - assign ssNoSynth_1_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; - assign ssNoSynth_1_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; - assign ssNoSynth_1_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_arNoSynth_buffer_ff + assign ssNoSynth_1_arNoSynth_buffer_ff$D_IN = + ssNoSynth_1_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_enqueue ; + assign ssNoSynth_1_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_buffer_dequeue ; + assign ssNoSynth_1_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_1_w_buffer_firstValid - assign ssNoSynth_1_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_1_w_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + // submodule ssNoSynth_1_arNoSynth_buffer_firstValid + assign ssNoSynth_1_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_arNoSynth_src_doDrop ; - // submodule ssNoSynth_2_ar_buffer_ff - assign ssNoSynth_2_ar_buffer_ff$D_IN = ssNoSynth_2_ar_buffer_enqw$wget ; - assign ssNoSynth_2_ar_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; - assign ssNoSynth_2_ar_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; - assign ssNoSynth_2_ar_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_awNoSynth_buffer_ff + assign ssNoSynth_1_awNoSynth_buffer_ff$D_IN = split_1_doPut$wget[171:74] ; + assign ssNoSynth_1_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_enqueue ; + assign ssNoSynth_1_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_buffer_dequeue ; + assign ssNoSynth_1_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_ar_buffer_firstValid - assign ssNoSynth_2_ar_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_ar_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + // submodule ssNoSynth_1_awNoSynth_buffer_firstValid + assign ssNoSynth_1_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_awNoSynth_src_doDrop ; - // submodule ssNoSynth_2_aw_buffer_ff - assign ssNoSynth_2_aw_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; - assign ssNoSynth_2_aw_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; - assign ssNoSynth_2_aw_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; - assign ssNoSynth_2_aw_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_bNoSynth_buffer_ff + assign ssNoSynth_1_bNoSynth_buffer_ff$D_IN = + ssNoSynth_1_bNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_enqueue ; + assign ssNoSynth_1_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_bNoSynth_buffer_dequeue ; + assign ssNoSynth_1_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_aw_buffer_firstValid - assign ssNoSynth_2_aw_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_aw_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + // submodule ssNoSynth_1_bNoSynth_buffer_firstValid + assign ssNoSynth_1_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_bNoSynth_buffer_firstValid$EN = + ssNoSynth_1_bNoSynth_buffer_dequeueing$whas ; - // submodule ssNoSynth_2_w_buffer_ff - assign ssNoSynth_2_w_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; - assign ssNoSynth_2_w_buffer_ff$ENQ = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; - assign ssNoSynth_2_w_buffer_ff$DEQ = - CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; - assign ssNoSynth_2_w_buffer_ff$CLR = 1'b0 ; + // submodule ssNoSynth_1_rNoSynth_buffer_ff + assign ssNoSynth_1_rNoSynth_buffer_ff$D_IN = + ssNoSynth_1_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_1_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_enqueue ; + assign ssNoSynth_1_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_rNoSynth_buffer_dequeue ; + assign ssNoSynth_1_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule ssNoSynth_2_w_buffer_firstValid - assign ssNoSynth_2_w_buffer_firstValid$D_IN = 1'd1 ; - assign ssNoSynth_2_w_buffer_firstValid$EN = - CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + // submodule ssNoSynth_1_rNoSynth_buffer_firstValid + assign ssNoSynth_1_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_rNoSynth_buffer_firstValid$EN = + ssNoSynth_1_rNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_1_wNoSynth_buffer_ff + assign ssNoSynth_1_wNoSynth_buffer_ff$D_IN = split_1_doPut$wget[73:0] ; + assign ssNoSynth_1_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_enqueue ; + assign ssNoSynth_1_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_buffer_dequeue ; + assign ssNoSynth_1_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_wNoSynth_buffer_firstValid + assign ssNoSynth_1_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_wNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_arNoSynth_buffer_ff + assign ssNoSynth_2_arNoSynth_buffer_ff$D_IN = + ssNoSynth_2_arNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_enqueue ; + assign ssNoSynth_2_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_buffer_dequeue ; + assign ssNoSynth_2_arNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_arNoSynth_buffer_firstValid + assign ssNoSynth_2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_arNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_awNoSynth_buffer_ff + assign ssNoSynth_2_awNoSynth_buffer_ff$D_IN = split_2_doPut$wget[171:74] ; + assign ssNoSynth_2_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_enqueue ; + assign ssNoSynth_2_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_buffer_dequeue ; + assign ssNoSynth_2_awNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_awNoSynth_buffer_firstValid + assign ssNoSynth_2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_awNoSynth_src_doDrop ; + + // submodule ssNoSynth_2_bNoSynth_buffer_ff + assign ssNoSynth_2_bNoSynth_buffer_ff$D_IN = + ssNoSynth_2_bNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_enqueue ; + assign ssNoSynth_2_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_bNoSynth_buffer_dequeue ; + assign ssNoSynth_2_bNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_bNoSynth_buffer_firstValid + assign ssNoSynth_2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_bNoSynth_buffer_firstValid$EN = + ssNoSynth_2_bNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_2_rNoSynth_buffer_ff + assign ssNoSynth_2_rNoSynth_buffer_ff$D_IN = + ssNoSynth_2_rNoSynth_buffer_enqw$wget ; + assign ssNoSynth_2_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_enqueue ; + assign ssNoSynth_2_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_rNoSynth_buffer_dequeue ; + assign ssNoSynth_2_rNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_rNoSynth_buffer_firstValid + assign ssNoSynth_2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_rNoSynth_buffer_firstValid$EN = + ssNoSynth_2_rNoSynth_buffer_dequeueing$whas ; + + // submodule ssNoSynth_2_wNoSynth_buffer_ff + assign ssNoSynth_2_wNoSynth_buffer_ff$D_IN = split_2_doPut$wget[73:0] ; + assign ssNoSynth_2_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_enqueue ; + assign ssNoSynth_2_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_buffer_dequeue ; + assign ssNoSynth_2_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_wNoSynth_buffer_firstValid + assign ssNoSynth_2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_wNoSynth_src_doDrop ; // submodule tagController_tmp_awreqff assign tagController_tmp_awreqff$D_IN = @@ -8579,505 +10947,543 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_tagController_tmp_passMemoryResponseWrite || WILL_FIRE_RL_tagController_tmp_passMemoryResponseRead ; - // submodule tmp0_b_buffer_ff - assign tmp0_b_buffer_ff$D_IN = tmp0_b_buffer_enqw$wget ; - assign tmp0_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_b_buffer_enqueue ; - assign tmp0_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_b_buffer_dequeue ; - assign tmp0_b_buffer_ff$CLR = 1'b0 ; + // submodule tmp2_arNoSynth_buffer_ff + assign tmp2_arNoSynth_buffer_ff$D_IN = tmp2_arNoSynth_buffer_enqw$wget ; + assign tmp2_arNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_enqueue ; + assign tmp2_arNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_arNoSynth_buffer_dequeue ; + assign tmp2_arNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp0_b_buffer_firstValid - assign tmp0_b_buffer_firstValid$D_IN = 1'd1 ; - assign tmp0_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_b_dropFlit ; + // submodule tmp2_arNoSynth_buffer_firstValid + assign tmp2_arNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_arNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_doDrop ; - // submodule tmp0_r_buffer_ff - assign tmp0_r_buffer_ff$D_IN = tmp0_r_buffer_enqw$wget ; - assign tmp0_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp0_r_buffer_enqueue ; - assign tmp0_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp0_r_buffer_dequeue ; - assign tmp0_r_buffer_ff$CLR = 1'b0 ; + // submodule tmp2_awNoSynth_buffer_ff + assign tmp2_awNoSynth_buffer_ff$D_IN = tmp2_awNoSynth_buffer_enqw$wget ; + assign tmp2_awNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_enqueue ; + assign tmp2_awNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_awNoSynth_buffer_dequeue ; + assign tmp2_awNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp0_r_buffer_firstValid - assign tmp0_r_buffer_firstValid$D_IN = 1'd1 ; - assign tmp0_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp0_r_dropFlit ; + // submodule tmp2_awNoSynth_buffer_firstValid + assign tmp2_awNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_awNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_doDrop ; - // submodule tmp2_b_buffer_ff - assign tmp2_b_buffer_ff$D_IN = + // submodule tmp2_bNoSynth_buffer_ff + assign tmp2_bNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_bff_rv$port1__read[6:0] ; - assign tmp2_b_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_b_buffer_enqueue ; - assign tmp2_b_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_b_buffer_dequeue ; - assign tmp2_b_buffer_ff$CLR = 1'b0 ; + assign tmp2_bNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_enqueue ; + assign tmp2_bNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_bNoSynth_buffer_dequeue ; + assign tmp2_bNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp2_b_buffer_firstValid - assign tmp2_b_buffer_firstValid$D_IN = 1'd1 ; - assign tmp2_b_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_b_dropFlit ; + // submodule tmp2_bNoSynth_buffer_firstValid + assign tmp2_bNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_bNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_tmp2_bNoSynth_src_doDrop ; - // submodule tmp2_r_buffer_ff - assign tmp2_r_buffer_ff$D_IN = + // submodule tmp2_rNoSynth_buffer_ff + assign tmp2_rNoSynth_buffer_ff$D_IN = tagController_tmp_shimSlave_rff_rv$port1__read[72:0] ; - assign tmp2_r_buffer_ff$ENQ = CAN_FIRE_RL_tmp2_r_buffer_enqueue ; - assign tmp2_r_buffer_ff$DEQ = CAN_FIRE_RL_tmp2_r_buffer_dequeue ; - assign tmp2_r_buffer_ff$CLR = 1'b0 ; + assign tmp2_rNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_enqueue ; + assign tmp2_rNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_rNoSynth_buffer_dequeue ; + assign tmp2_rNoSynth_buffer_ff$CLR = 1'b0 ; - // submodule tmp2_r_buffer_firstValid - assign tmp2_r_buffer_firstValid$D_IN = 1'd1 ; - assign tmp2_r_buffer_firstValid$EN = CAN_FIRE_RL_tmp2_r_dropFlit ; + // submodule tmp2_rNoSynth_buffer_firstValid + assign tmp2_rNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_rNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_tmp2_rNoSynth_src_doDrop ; + + // submodule tmp2_wNoSynth_buffer_ff + assign tmp2_wNoSynth_buffer_ff$D_IN = tmp2_wNoSynth_buffer_enqw$wget ; + assign tmp2_wNoSynth_buffer_ff$ENQ = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_enqueue ; + assign tmp2_wNoSynth_buffer_ff$DEQ = + CAN_FIRE_RL_tmp2_wNoSynth_buffer_dequeue ; + assign tmp2_wNoSynth_buffer_ff$CLR = 1'b0 ; + + // submodule tmp2_wNoSynth_buffer_firstValid + assign tmp2_wNoSynth_buffer_firstValid$D_IN = 1'd1 ; + assign tmp2_wNoSynth_buffer_firstValid$EN = + CAN_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_doDrop ; // submodule uncached_mem_shim_arff assign uncached_mem_shim_arff$D_IN = - ssNoSynth_0_ar_buffer_ff$EMPTY_N ? - ssNoSynth_0_ar_buffer_ff$D_OUT : - ssNoSynth_0_ar_buffer_enqw$wget ; + slave_vector_0_arSynth_snk_putWire$wget ; assign uncached_mem_shim_arff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit && - uncached_mem_shim_arff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_arSynth_snk_doPut ; assign uncached_mem_shim_arff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_ar_doDrop ; + CAN_FIRE_RL_uncached_mem_master_arSynth_src_doDrop ; assign uncached_mem_shim_arff$CLR = 1'b0 ; // submodule uncached_mem_shim_awff assign uncached_mem_shim_awff$D_IN = - ssNoSynth_0_aw_buffer_ff$EMPTY_N ? - ssNoSynth_0_aw_buffer_ff$D_OUT : - split_0_doPut$wget[171:74] ; + slave_vector_0_awSynth_snk_putWire$wget ; assign uncached_mem_shim_awff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit && - uncached_mem_shim_awff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_awSynth_snk_doPut ; assign uncached_mem_shim_awff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_aw_doDrop ; + CAN_FIRE_RL_uncached_mem_master_awSynth_src_doDrop ; assign uncached_mem_shim_awff$CLR = 1'b0 ; // submodule uncached_mem_shim_bff assign uncached_mem_shim_bff$D_IN = - ug_uncached_mem_shim_master_u_b_putWire$wget[6:0] ; + uncached_mem_master_bSynth_snk_putWire$wget[6:0] ; assign uncached_mem_shim_bff$ENQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_b_doPut ; + CAN_FIRE_RL_uncached_mem_master_bSynth_snk_doPut ; assign uncached_mem_shim_bff$DEQ = - uncached_mem_shim_bff$EMPTY_N && ssNoSynth_0_b_dwReady$whas ; + CAN_FIRE_RL_slave_vector_0_bSynth_src_doDrop ; assign uncached_mem_shim_bff$CLR = 1'b0 ; // submodule uncached_mem_shim_rff assign uncached_mem_shim_rff$D_IN = - { ug_uncached_mem_shim_master_u_r_putWire$wget[71:0], 1'd0 } ; + { uncached_mem_master_rSynth_snk_putWire$wget[71:0], 1'd0 } ; assign uncached_mem_shim_rff$ENQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_r_doPut ; + CAN_FIRE_RL_uncached_mem_master_rSynth_snk_doPut ; assign uncached_mem_shim_rff$DEQ = - uncached_mem_shim_rff$EMPTY_N && ssNoSynth_0_r_dwReady$whas ; + CAN_FIRE_RL_slave_vector_0_rSynth_src_doDrop ; assign uncached_mem_shim_rff$CLR = 1'b0 ; // submodule uncached_mem_shim_wff - assign uncached_mem_shim_wff$D_IN = - ssNoSynth_0_w_buffer_ff$EMPTY_N ? - ssNoSynth_0_w_buffer_ff$D_OUT : - split_0_doPut$wget[73:0] ; + assign uncached_mem_shim_wff$D_IN = slave_vector_0_wSynth_snk_putWire$wget ; assign uncached_mem_shim_wff$ENQ = - WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit && - uncached_mem_shim_wff$FULL_N ; + CAN_FIRE_RL_slave_vector_0_wSynth_snk_doPut ; assign uncached_mem_shim_wff$DEQ = - CAN_FIRE_RL_ug_uncached_mem_shim_master_u_w_doDrop ; + CAN_FIRE_RL_uncached_mem_master_wSynth_src_doDrop ; assign uncached_mem_shim_wff$CLR = 1'b0 ; // remaining internal signals - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207 = - ((IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203)) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 = + ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + (IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527)) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211 = - ((IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 || - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) && - !IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 = + ((IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 || + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) && + !IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1216 = - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1207 + - IF_IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ETC___d1211 + - ((!IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 && - IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195) ? + assign IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1540 = + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1531 + + IF_IF_merged_0_outflit_whas__501_AND_NOT_merge_ETC___d1535 + + ((!IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 && + IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519) ? 2'd1 : 2'd0) ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306 = - ((IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302)) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 = + ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + (IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621)) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310 = - ((IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 || - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) && - !IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 = + ((IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 || + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) && + !IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621) ? 2'd1 : 2'd0 ; - assign IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1315 = - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1306 + - IF_IF_merged_1_flitLeft_070_EQ_0_071_THEN_debu_ETC___d1310 + - ((!IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 && - IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297) ? + assign IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1634 = + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1625 + + IF_IF_merged_1_outflit_whas__601_AND_NOT_merge_ETC___d1629 + + ((!IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 && + IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616) ? 2'd1 : 2'd0) ; - assign IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 = + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 = + ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + (IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 = + ((IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 || + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) && + !IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2236 = + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2227 + + IF_IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmp_ETC___d2231 + + ((!IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 && + IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218) ? + 2'd1 : + 2'd0) ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 = + ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + (IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 = + ((IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 || + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) && + !IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318) ? + 2'd1 : + 2'd0 ; + assign IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2331 = + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2322 + + IF_IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmp_ETC___d2326 + + ((!IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 && + IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313) ? + 2'd1 : + 2'd0) ; + assign IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 = (!ifcs_0_1_innerRoute$D_OUT[1] || - !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_innerRoute$D_OUT[2] && - ssNoSynth_2_ar_buffer_ff$FULL_N : + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_0_1_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 = + assign IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 = (!ifcs_0_innerRoute$D_OUT[1] || - !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426) ? + !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_0_innerRoute$D_OUT[2] && - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 : + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_0_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 = + assign IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 = (!ifcs_1_1_innerRoute$D_OUT[1] || - !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + !ssNoSynth_1_arNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_innerRoute$D_OUT[2] && - ssNoSynth_2_ar_buffer_ff$FULL_N : + ssNoSynth_2_arNoSynth_buffer_ff$FULL_N : ifcs_1_1_innerRoute$D_OUT[1] ; - assign IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 = + assign IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 = (!ifcs_1_innerRoute$D_OUT[1] || - !IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426) ? + !IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773) ? ifcs_1_innerRoute$D_OUT[2] && - IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 : + IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 : ifcs_1_innerRoute$D_OUT[1] ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2350 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94630 | y__h94631 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2769 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118613 | y__h118614 : arbiter_1_1_lastSelect ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2356 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94818 | y__h94819 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2775 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118801 | y__h118802 : arbiter_1_1_lastSelect_1 ; - assign IF_SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_3_ETC___d2362 = - (SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 || - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 || - SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) ? - x__h94999 | y__h95000 : + assign IF_SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_7_ETC___d2781 = + (SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 || + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 || + SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) ? + x__h118982 | y__h118983 : arbiter_1_1_firstHot ; - assign IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2150 = - (SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 || - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) ? - x__h82688 | y__h82689 : - arbiter_1_lastSelect_2 ; - assign IF_SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_1_ETC___d2154 = - (SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 || - SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) ? - x__h82829 | y__h82830 : - arbiter_1_firstHot_1 ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1717 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63404 | y__h63405 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2078 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85339 | y__h85340 : arbiter_1_lastSelect ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1723 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63592 | y__h63593 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2084 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85527 | y__h85528 : arbiter_1_lastSelect_1 ; - assign IF_SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_ETC___d1729 = - (SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 || - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 || - SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) ? - x__h63773 | y__h63774 : + assign IF_SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_ETC___d2090 = + (SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 || + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 || + SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) ? + x__h85708 | y__h85709 : arbiter_1_firstHot ; - assign IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1507 = - (SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 || - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) ? - x__h48921 | y__h48922 : + assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2565 = + (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? + x__h106164 | y__h106165 : + arbiter_1_lastSelect_2 ; + assign IF_SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_5_ETC___d2569 = + (SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 || + SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) ? + x__h106305 | y__h106306 : + arbiter_1_firstHot_1 ; + assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1864 = + (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? + x__h70391 | y__h70392 : arbiter_lastSelect ; - assign IF_SEXT_arbiter_lastSelect_483_484_BIT_0_485_A_ETC___d1511 = - (SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 || - SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) ? - x__h49062 | y__h49063 : + assign IF_SEXT_arbiter_lastSelect_840_841_BIT_0_842_A_ETC___d1868 = + (SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 || + SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) ? + x__h70532 | y__h70533 : arbiter_firstHot ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941 = - ((debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - (debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937)) ? - 2'd1 : - 2'd0 ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945 = - ((debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 || - !debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) && - !debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937) ? - 2'd1 : - 2'd0 ; - assign IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1950 = - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1941 + - IF_debug_module_master_ar_araddr__929_ULT_soc__ETC___d1945 + - ((!debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 && - debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932) ? - 2'd1 : - 2'd0) ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 = - ((merged_0_flitLeft == 8'd0) ? - !proc$master1_awvalid || !proc$master1_wvalid : - !proc$master1_wvalid) || - merged_0_flitLeft != 8'd0 ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1250 = - (IF_merged_0_flitLeft_050_EQ_0_051_THEN_NOT_pro_ETC___d1180 || - proc$master1_awvalid) && - (merged_0_flitLeft != 8'd0 || - !ifcs_0_noRoute_inner_pendingReq && proc$master1_awvalid) ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1173 = + assign IF_merged_0_flitLeft_341_EQ_0_342_THEN_merged__ETC___d1498 = (merged_0_flitLeft == 8'd0) ? - proc$master1_awvalid && proc$master1_wvalid : - proc$master1_wvalid ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1192 = - proc$master1_awaddr < + merged_0_awff$EMPTY_N && merged_0_wff$EMPTY_N : + merged_0_wff$EMPTY_N ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1516 = + merged_0_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1195 = - x__h37445 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1200 = - proc$master1_awaddr < soc_map$m_plic_addr_range[127:64] ; - assign IF_merged_0_flitLeft_050_EQ_0_051_THEN_proc_ma_ETC___d1203 = - x__h37480 < soc_map$m_plic_addr_range[63:0] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 = - ((merged_1_flitLeft == 8'd0) ? - !debug_module$master_awvalid || !debug_module$master_wvalid : - !debug_module$master_wvalid) || - merged_1_flitLeft != 8'd0 ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1350 = - (IF_merged_1_flitLeft_070_EQ_0_071_THEN_NOT_deb_ETC___d1285 || - debug_module$master_awvalid) && - (merged_1_flitLeft != 8'd0 || - !ifcs_1_noRoute_inner_pendingReq && - debug_module$master_awvalid) ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1278 = + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1519 = + x__h56232 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1524 = + merged_0_outflit$wget[166:103] < + soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1527 = + x__h56267 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_0_outflit_whas__501_AND_NOT_merged_0_ETC___d1551 = + (CAN_FIRE_RL_merged_0_passFlit && !merged_0_outflit$wget[171]) ? + { 1'd0, merged_0_outflit$wget[170:0] } : + { 98'h2AAAAAAAAAAAAAAAAAAAAAAAA, + CAN_FIRE_RL_merged_0_passFlit ? + merged_0_outflit$wget[73:0] : + merged_0_wff$D_OUT } ; + assign IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 = + CAN_FIRE_RL_merged_0_passFlit ? + !merged_0_outflit$wget[1] : + !merged_0_wff$D_OUT[1] ; + assign IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 = + CAN_FIRE_RL_merged_0_passFlit ? + merged_0_outflit$wget[1] : + merged_0_wff$D_OUT[1] ; + assign IF_merged_1_flitLeft_381_EQ_0_382_THEN_merged__ETC___d1598 = (merged_1_flitLeft == 8'd0) ? - debug_module$master_awvalid && debug_module$master_wvalid : - debug_module$master_wvalid ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1295 = - debug_module$master_awaddr < + merged_1_awff$EMPTY_N && merged_1_wff$EMPTY_N : + merged_1_wff$EMPTY_N ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1614 = + merged_1_outflit$wget[166:103] < soc_map$m_mem0_controller_addr_range[127:64] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1297 = - x__h40162 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1300 = - debug_module$master_awaddr < soc_map$m_plic_addr_range[127:64] ; - assign IF_merged_1_flitLeft_070_EQ_0_071_THEN_debug_m_ETC___d1302 = - x__h40187 < soc_map$m_plic_addr_range[63:0] ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854 = - ((proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - (proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850)) ? - 2'd1 : - 2'd0 ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858 = - ((proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 || - !proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) && - !proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850) ? - 2'd1 : - 2'd0 ; - assign IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1863 = - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1854 + - IF_proc_master1_ar_araddr__842_ULT_soc_map_m_m_ETC___d1858 + - ((!proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 && - proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845) ? - 2'd1 : - 2'd0) ; - assign IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425 = + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1616 = + x__h59744 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1619 = + merged_1_outflit$wget[166:103] < + soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1621 = + x__h59769 < soc_map$m_plic_addr_range[63:0] ; + assign IF_merged_1_outflit_whas__601_AND_NOT_merged_1_ETC___d1645 = + (CAN_FIRE_RL_merged_1_passFlit && !merged_1_outflit$wget[171]) ? + { 1'd1, merged_1_outflit$wget[170:0] } : + { 98'h2AAAAAAAAAAAAAAAAAAAAAAAA, + CAN_FIRE_RL_merged_1_passFlit ? + merged_1_outflit$wget[73:0] : + merged_1_wff$D_OUT } ; + assign IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 = + CAN_FIRE_RL_merged_1_passFlit ? + !merged_1_outflit$wget[1] : + !merged_1_wff$D_OUT[1] ; + assign IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 = + CAN_FIRE_RL_merged_1_passFlit ? + merged_1_outflit$wget[1] : + merged_1_wff$D_OUT[1] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2216 = + addr__h93758 < soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2218 = + x__h93834 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2221 = + addr__h93758 < soc_map$m_plic_addr_range[127:64] ; + assign IF_msNoSynth_0_arNoSynth_buffer_ff_i_notEmpty__ETC___d2223 = + x__h93859 < soc_map$m_plic_addr_range[63:0] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2311 = + addr__h96375 < soc_map$m_mem0_controller_addr_range[127:64] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2313 = + x__h96451 < soc_map$m_mem0_controller_addr_range[63:0] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2316 = + addr__h96375 < soc_map$m_plic_addr_range[127:64] ; + assign IF_msNoSynth_1_arNoSynth_buffer_ff_i_notEmpty__ETC___d2318 = + x__h96476 < soc_map$m_plic_addr_range[63:0] ; + assign IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764 = (split_0_flitLeft == 8'd0) ? - ssNoSynth_0_aw_buffer_ff$FULL_N && - ssNoSynth_0_w_buffer_ff$FULL_N : - ssNoSynth_0_w_buffer_ff$FULL_N ; - assign IF_split_1_flitLeft_123_EQ_0_124_THEN_ssNoSynt_ETC___d1426 = + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N ; + assign IF_split_1_flitLeft_439_EQ_0_440_THEN_ssNoSynt_ETC___d1773 = (split_1_flitLeft == 8'd0) ? - ssNoSynth_1_aw_buffer_ff$FULL_N && - ssNoSynth_1_w_buffer_ff$FULL_N : - ssNoSynth_1_w_buffer_ff$FULL_N ; - assign IF_split_2_flitLeft_152_EQ_0_153_THEN_ssNoSynt_ETC___d1427 = + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N ; + assign IF_split_2_flitLeft_468_EQ_0_469_THEN_ssNoSynt_ETC___d1782 = (split_2_flitLeft == 8'd0) ? - ssNoSynth_2_aw_buffer_ff$FULL_N && - ssNoSynth_2_w_buffer_ff$FULL_N : - ssNoSynth_2_w_buffer_ff$FULL_N ; - assign SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22 = - {2{SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331}} ; - assign SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17 = - {2{SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138}} ; - assign SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12 = - {2{SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698}} ; - assign SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7 = - {2{SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495}} ; - assign SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 = - x__h94158 | y__h94159 ; + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N : + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N ; + assign SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22 = + {2{SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750}} ; + assign SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12 = + {2{SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059}} ; + assign SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17 = + {2{SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553}} ; + assign SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7 = + {2{SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852}} ; + assign SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 = + x__h118141 | y__h118142 ; assign SEXT_arbiter_1_1_firstHot__q19 = {2{arbiter_1_1_firstHot}} ; - assign SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 = - x__h94022 | y__h94023 ; + assign SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 = + x__h118005 | y__h118006 ; assign SEXT_arbiter_1_1_lastSelect_1__q21 = {2{arbiter_1_1_lastSelect_1}} ; - assign SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 = - x__h93871 | y__h93872 ; + assign SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 = + x__h117854 | y__h117855 ; assign SEXT_arbiter_1_1_lastSelect__q20 = {2{arbiter_1_1_lastSelect}} ; - assign SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138 = - x__h82323 | y__h82324 ; + assign SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 = + x__h84867 | y__h84868 ; + assign SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 = + x__h105799 | y__h105800 ; assign SEXT_arbiter_1_firstHot_1__q15 = {2{arbiter_1_firstHot_1}} ; - assign SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 = - x__h62932 | y__h62933 ; assign SEXT_arbiter_1_firstHot__q9 = {2{arbiter_1_firstHot}} ; - assign SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 = - x__h62796 | y__h62797 ; + assign SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 = + x__h84580 | y__h84581 ; + assign SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 = + x__h84731 | y__h84732 ; assign SEXT_arbiter_1_lastSelect_1__q11 = {2{arbiter_1_lastSelect_1}} ; - assign SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 = - x__h82220 | y__h82221 ; + assign SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 = + x__h105696 | y__h105697 ; assign SEXT_arbiter_1_lastSelect_2__q16 = {2{arbiter_1_lastSelect_2}} ; - assign SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 = - x__h62645 | y__h62646 ; assign SEXT_arbiter_1_lastSelect__q10 = {2{arbiter_1_lastSelect}} ; - assign SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495 = - x__h48556 | y__h48557 ; + assign SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 = + x__h70026 | y__h70027 ; assign SEXT_arbiter_firstHot__q5 = {2{arbiter_firstHot}} ; - assign SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 = - x__h48453 | y__h48454 ; + assign SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 = + x__h69923 | y__h69924 ; assign SEXT_arbiter_lastSelect__q6 = {2{arbiter_lastSelect}} ; - assign SEXT_x2747__q18 = {2{x__h82747}} ; - assign SEXT_x3466__q13 = {2{x__h63466}} ; - assign SEXT_x3500__q14 = {2{x__h63500}} ; - assign SEXT_x4692__q23 = {2{x__h94692}} ; - assign SEXT_x4726__q24 = {2{x__h94726}} ; - assign SEXT_x8980__q8 = {2{x__h48980}} ; - assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245 = - x__h12617 + y__h12618 ; - assign a_awid__h38523 = { 1'd0, proc$master1_awid } ; - assign a_awid__h41194 = { 1'd1, debug_module$master_awid } ; - assign araddr__h15540 = + assign SEXT_x0450__q8 = {2{x__h70450}} ; + assign SEXT_x06223__q18 = {2{x__h106223}} ; + assign SEXT_x18675__q23 = {2{x__h118675}} ; + assign SEXT_x18709__q24 = {2{x__h118709}} ; + assign SEXT_x5401__q13 = {2{x__h85401}} ; + assign SEXT_x5435__q14 = {2{x__h85435}} ; + assign _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224 = + x__h12420 + y__h12421 ; + assign addr__h93758 = + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[92:29] : + proc$master1_ar_peek[92:29] ; + assign addr__h96375 = + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[92:29] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[92:29] ; + assign araddr__h15343 = { 24'd0, tagController_tmp_tagCon$memory_request_get[140:101] } ; - assign arcache__h15545 = + assign arcache__h15348 = tagController_tmp_tagCon$memory_request_get[8] ? 4'd0 : 4'd15 ; - assign arlen__h15541 = + assign arlen__h15344 = { 5'd0, tagController_tmp_tagCon$memory_request_get[5:3] } ; - assign aw_awaddr__h10808 = tmp__h10591 + { 60'd0, x__h10883 } ; - assign aw_awsize_val__h12547 = - _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[0] ? + assign aw_awaddr__h10611 = tmp__h10394 + { 60'd0, x__h10686 } ; + assign aw_awsize_val__h12350 = + _0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[0] ? 3'd0 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[1] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[1] ? 3'd1 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[2] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[2] ? 3'd2 : - (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d245[3] ? + (_0_CONCAT_tagController_tmp_tagCon_memory_reque_ETC___d224[3] ? 3'd3 : 3'd4))) ; - assign debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1932 = - x__h74126 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign debug_module_master_ar_araddr__929_MINUS_soc_m_ETC___d1937 = - x__h74151 < soc_map$m_plic_addr_range[63:0] ; - assign debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1930 = - debug_module$master_araddr < - soc_map$m_mem0_controller_addr_range[127:64] ; - assign debug_module_master_ar_araddr__929_ULT_soc_map_ETC___d1935 = - debug_module$master_araddr < soc_map$m_plic_addr_range[127:64] ; - assign fatReq_arid__h72223 = { 1'd0, proc$master1_arid } ; - assign fatReq_arid__h74597 = { 1'd1, debug_module$master_arid } ; - assign proc_master1_ar_araddr__842_MINUS_soc_map_m_me_ETC___d1845 = - x__h71737 < soc_map$m_mem0_controller_addr_range[63:0] ; - assign proc_master1_ar_araddr__842_MINUS_soc_map_m_pl_ETC___d1850 = - x__h71762 < soc_map$m_plic_addr_range[63:0] ; - assign proc_master1_ar_araddr__842_ULT_soc_map_m_mem0_ETC___d1843 = - proc$master1_araddr < - soc_map$m_mem0_controller_addr_range[127:64] ; - assign proc_master1_ar_araddr__842_ULT_soc_map_m_plic_ETC___d1848 = - proc$master1_araddr < soc_map$m_plic_addr_range[127:64] ; - assign reqWires_1_0_whas__659_AND_reqWires_1_0_wget___ETC___d1669 = + assign fatReq_arid__h94342 = + { 1'd0, + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[96:93] : + proc$master1_ar_peek[96:93] } ; + assign fatReq_arid__h96944 = + { 1'd1, + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[96:93] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[96:93] } ; + assign reqWires_1_0_whas__020_AND_reqWires_1_0_wget___ETC___d2030 = CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget || CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget || CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget ; - assign reqWires_1_1_0_whas__292_AND_reqWires_1_1_0_wg_ETC___d2302 = + assign reqWires_1_1_0_whas__711_AND_reqWires_1_1_0_wg_ETC___d2721 = CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget || CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget || CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget ; - assign split_0_doPut_whas__086_AND_split_0_doPut_wget_ETC___d1093 = - CAN_FIRE_RL_sink_selected && + assign split_0_doPut_whas__402_AND_split_0_doPut_wget_ETC___d1409 = + CAN_FIRE_RL_sinks_0_doPut && (split_0_doPut$wget[172] || - ssNoSynth_0_aw_buffer_ff$FULL_N && - ssNoSynth_0_w_buffer_ff$FULL_N) ; - assign split_1_doPut_whas__115_AND_split_1_doPut_wget_ETC___d1122 = - CAN_FIRE_RL_sink_selected_1 && + ssNoSynth_0_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_0_wNoSynth_buffer_ff$FULL_N) ; + assign split_1_doPut_whas__431_AND_split_1_doPut_wget_ETC___d1438 = + CAN_FIRE_RL_sinks_1_doPut && (split_1_doPut$wget[172] || - ssNoSynth_1_aw_buffer_ff$FULL_N && - ssNoSynth_1_w_buffer_ff$FULL_N) ; - assign split_2_doPut_whas__144_AND_split_2_doPut_wget_ETC___d1151 = - CAN_FIRE_RL_sink_selected_2 && + ssNoSynth_1_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_1_wNoSynth_buffer_ff$FULL_N) ; + assign split_2_doPut_whas__460_AND_split_2_doPut_wget_ETC___d1467 = + CAN_FIRE_RL_sinks_2_doPut && (split_2_doPut$wget[172] || - ssNoSynth_2_aw_buffer_ff$FULL_N && - ssNoSynth_2_w_buffer_ff$FULL_N) ; - assign state_1_1_123_AND_activeSource_1_0_1_190_191_A_ETC___d2193 = - state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && - ((!ifcs_0_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_0_1_innerRoute_first__076_BIT_1_08_ETC___d2098 : - ifcs_0_1_innerRoute$D_OUT[0]) ; - assign state_1_1_123_AND_activeSource_1_1_1_230_231_A_ETC___d2233 = - state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && - ((!ifcs_1_1_innerRoute$D_OUT[0] || - !ssNoSynth_0_ar_buffer_ff$FULL_N) ? - IF_NOT_ifcs_1_1_innerRoute_first__105_BIT_1_10_ETC___d2114 : - ifcs_1_1_innerRoute$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_0_397_398_ETC___d2400 = + ssNoSynth_2_awNoSynth_buffer_ff$FULL_N && + ssNoSynth_2_wNoSynth_buffer_ff$FULL_N) ; + assign state_1_031_AND_activeSource_1_0_119_120_AND_i_ETC___d2122 = + state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && + ((!ifcs_0_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_0_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_0_routeBack$D_OUT[0]) ; + assign state_1_031_AND_activeSource_1_1_152_153_AND_i_ETC___d2155 = + state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && + ((!ifcs_1_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_1_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_1_routeBack$D_OUT[0]) ; + assign state_1_031_AND_activeSource_1_2_186_187_AND_i_ETC___d2189 = + state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && + ((!ifcs_2_routeBack$D_OUT[0] || + !msNoSynth_0_bNoSynth_buffer_ff$FULL_N) ? + ifcs_2_routeBack$D_OUT[1] && + msNoSynth_1_bNoSynth_buffer_ff$FULL_N : + ifcs_2_routeBack$D_OUT[0]) ; + assign state_1_1_1_722_AND_activeSource_1_1_0_816_817_ETC___d2819 = state_1_1_1 && activeSource_1_1_0 && ifcs_0_1_routeBack$EMPTY_N && ((!ifcs_0_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_0_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_0_1_routeBack$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_1_1_433_4_ETC___d2436 = + assign state_1_1_1_722_AND_activeSource_1_1_1_1_852_8_ETC___d2855 = state_1_1_1 && activeSource_1_1_1_1 && ifcs_1_1_routeBack$EMPTY_N && ((!ifcs_1_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_1_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_1_1_routeBack$D_OUT[0]) ; - assign state_1_1_1_303_AND_activeSource_1_1_2_469_470_ETC___d2472 = + assign state_1_1_1_722_AND_activeSource_1_1_2_888_889_ETC___d2891 = state_1_1_1 && activeSource_1_1_2 && ifcs_2_1_routeBack$EMPTY_N && ((!ifcs_2_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + !msNoSynth_0_rNoSynth_buffer_ff$FULL_N) ? ifcs_2_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + msNoSynth_1_rNoSynth_buffer_ff$FULL_N : ifcs_2_1_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_0_758_759_AND_i_ETC___d1761 = - state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && - ((!ifcs_0_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_0_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_0_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_1_791_792_AND_i_ETC___d1794 = - state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && - ((!ifcs_1_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_1_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_1_routeBack$D_OUT[0]) ; - assign state_1_670_AND_activeSource_1_2_825_826_AND_i_ETC___d1828 = - state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && - ((!ifcs_2_routeBack$D_OUT[0] || - !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? - ifcs_2_routeBack$D_OUT[1] && - !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : - ifcs_2_routeBack$D_OUT[0]) ; - assign state_480_AND_activeSource_0_553_554_AND_ifcs__ETC___d1556 = + assign state_1_1_538_AND_activeSource_1_0_1_605_606_A_ETC___d2608 = + state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && + ((!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__491_BIT_1_50_ETC___d2513 : + ifcs_0_1_innerRoute$D_OUT[0]) ; + assign state_1_1_538_AND_activeSource_1_1_1_645_646_A_ETC___d2648 = + state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && + ((!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_arNoSynth_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__520_BIT_1_52_ETC___d2529 : + ifcs_1_1_innerRoute$D_OUT[0]) ; + assign state_837_AND_activeSource_0_910_911_AND_ifcs__ETC___d1913 = state && activeSource_0 && ifcs_0_innerRoute$EMPTY_N && ((!ifcs_0_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_0_innerRoute_first__433_BIT_1_442__ETC___d1455 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_0_innerRoute_first__790_BIT_1_799__ETC___d1812 : ifcs_0_innerRoute$D_OUT[0]) ; - assign state_480_AND_activeSource_1_597_598_AND_ifcs__ETC___d1600 = + assign state_837_AND_activeSource_1_954_955_AND_ifcs__ETC___d1957 = state && activeSource_1 && ifcs_1_innerRoute$EMPTY_N && ((!ifcs_1_innerRoute$D_OUT[0] || - !IF_split_0_flitLeft_094_EQ_0_095_THEN_ssNoSynt_ETC___d1425) ? - IF_NOT_ifcs_1_innerRoute_first__462_BIT_1_466__ETC___d1471 : + !IF_split_0_flitLeft_410_EQ_0_411_THEN_ssNoSynt_ETC___d1764) ? + IF_NOT_ifcs_1_innerRoute_first__819_BIT_1_823__ETC___d1828 : ifcs_1_innerRoute$D_OUT[0]) ; assign tagController_tmp_shimMaster_arff_rvport1__re_ETC__q4 = tagController_tmp_shimMaster_arff_rv$port1__read[98:0] ; @@ -9085,31 +11491,48 @@ module mkCoreW(RST_N_dm_power_on_reset, tagController_tmp_shimMaster_awff_rv$port1__read[98:0] ; assign tagController_tmp_shimMaster_wff_rvport1__rea_ETC__q3 = tagController_tmp_shimMaster_wff_rv$port1__read[72:0] ; - assign tmp__h10591 = { 24'd0, x__h10840 } ; - assign tmp__h8366 = + assign tmp__h10394 = { 24'd0, x__h10643 } ; + assign tmp__h8169 = tagController_tmp_awreqff$D_OUT[92:29] + tagController_tmp_addrOffset ; assign uncached_mem_shim_wffD_OUT_BITS_73_TO_1__q1 = uncached_mem_shim_wff$D_OUT[73:1] ; - assign v_araddr__h15557 = + assign v_araddr__h15360 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - araddr__h15540 : + araddr__h15343 : 64'hAAAAAAAAAAAAAAAA ; - assign v_arid__h15556 = + assign v_arid__h15359 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[100:95] : 6'd0 ; - assign v_arlen__h15558 = + assign v_arlen__h15361 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - arlen__h15541 : + arlen__h15344 : 8'd0 ; - assign v_arsize_val__h15603 = + assign v_arsize_val__h15406 = (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? tagController_tmp_tagCon$memory_request_get[2:0] : 3'b0 ; - assign x__h10840 = + assign x__h100325 = + ssNoSynth_2_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[72:68] : + ssNoSynth_2_rNoSynth_buffer_enqw$wget[72:68] ; + assign x__h105696 = + SEXT_arbiter_1_lastSelect_2__q16[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h105799 = + SEXT_arbiter_1_firstHot_1__q15[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h106164 = + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & + arbiter_1_firstHot_1 ; + assign x__h106223 = + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553 && + SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 ; + assign x__h106305 = SEXT_x06223__q18[0] & arbiter_1_firstHot_1 ; + assign x__h10643 = { tagController_tmp_tagCon$memory_request_get[140:104], 3'd0 } ; - assign x__h10883 = + assign x__h10686 = tagController_tmp_tagCon$memory_request_get[81] ? 4'd0 : (tagController_tmp_tagCon$memory_request_get[82] ? @@ -9127,227 +11550,234 @@ module mkCoreW(RST_N_dm_power_on_reset, (tagController_tmp_tagCon$memory_request_get[88] ? 4'd7 : 4'd8))))))) ; - assign x__h12617 = x__h12629 + y__h12630 ; - assign x__h12629 = x__h12641 + y__h12642 ; - assign x__h12641 = x__h12653 + y__h12654 ; - assign x__h12653 = x__h12665 + y__h12666 ; - assign x__h12665 = x__h12677 + y__h12678 ; - assign x__h12677 = x__h12689 + y__h12690 ; - assign x__h12689 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; - assign x__h14213 = - tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; - assign x__h15621 = - (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? - arcache__h15545 : - 4'd0 ; - assign x__h37445 = - proc$master1_awaddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h37480 = proc$master1_awaddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h40162 = - debug_module$master_awaddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h40187 = - debug_module$master_awaddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h48453 = - SEXT_arbiter_lastSelect__q6[0] & - (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; - assign x__h48556 = - SEXT_arbiter_firstHot__q5[0] & - (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; - assign x__h48921 = - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7[0] & - arbiter_firstHot ; - assign x__h48980 = - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495 && - SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 ; - assign x__h49062 = SEXT_x8980__q8[0] & arbiter_firstHot ; - assign x__h62645 = x__h62647 | y__h62648 ; - assign x__h62647 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h62796 = x__h62798 | y__h62799 ; - assign x__h62798 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h62932 = x__h62934 | y__h62935 ; - assign x__h62934 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; - assign x__h63404 = x__h63406 | y__h63407 ; - assign x__h63406 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_firstHot ; - assign x__h63466 = - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 && - SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 ; - assign x__h63500 = - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698 && - SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 ; - assign x__h63592 = x__h63594 | y__h63595 ; - assign x__h63594 = SEXT_x3466__q13[0] & arbiter_1_firstHot ; - assign x__h63773 = x__h63775 | y__h63776 ; - assign x__h63775 = SEXT_x3500__q14[0] & arbiter_1_firstHot ; - assign x__h71737 = - proc$master1_araddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h71762 = proc$master1_araddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h74126 = - debug_module$master_araddr - - soc_map$m_mem0_controller_addr_range[127:64] ; - assign x__h74151 = - debug_module$master_araddr - soc_map$m_plic_addr_range[127:64] ; - assign x__h8207 = - tagController_tmp_addrOffset + - (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; - assign x__h82220 = - SEXT_arbiter_1_lastSelect_2__q16[0] & - (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; - assign x__h82323 = - SEXT_arbiter_1_firstHot_1__q15[0] & - (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; - assign x__h82688 = - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17[0] & - arbiter_1_firstHot_1 ; - assign x__h82747 = - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138 && - SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 ; - assign x__h82829 = SEXT_x2747__q18[0] & arbiter_1_firstHot_1 ; - assign x__h93871 = x__h93873 | y__h93874 ; - assign x__h93873 = + assign x__h117854 = x__h117856 | y__h117857 ; + assign x__h117856 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94022 = x__h94024 | y__h94025 ; - assign x__h94024 = + assign x__h118005 = x__h118007 | y__h118008 ; + assign x__h118007 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94158 = x__h94160 | y__h94161 ; - assign x__h94160 = + assign x__h118141 = x__h118143 | y__h118144 ; + assign x__h118143 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; - assign x__h94630 = x__h94632 | y__h94633 ; - assign x__h94632 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign x__h118613 = x__h118615 | y__h118616 ; + assign x__h118615 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_firstHot ; - assign x__h94692 = - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 && - SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 ; - assign x__h94726 = - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331 && - SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 ; - assign x__h94818 = x__h94820 | y__h94821 ; - assign x__h94820 = SEXT_x4692__q23[0] & arbiter_1_1_firstHot ; - assign x__h94999 = x__h95001 | y__h95002 ; - assign x__h95001 = SEXT_x4726__q24[0] & arbiter_1_1_firstHot ; - assign x_port1__read__h72781 = + assign x__h118675 = + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && + SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 ; + assign x__h118709 = + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750 && + SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 ; + assign x__h118801 = x__h118803 | y__h118804 ; + assign x__h118803 = SEXT_x18675__q23[0] & arbiter_1_1_firstHot ; + assign x__h118982 = x__h118984 | y__h118985 ; + assign x__h118984 = SEXT_x18709__q24[0] & arbiter_1_1_firstHot ; + assign x__h12420 = x__h12432 + y__h12433 ; + assign x__h12432 = x__h12444 + y__h12445 ; + assign x__h12444 = x__h12456 + y__h12457 ; + assign x__h12456 = x__h12468 + y__h12469 ; + assign x__h12468 = x__h12480 + y__h12481 ; + assign x__h12480 = x__h12492 + y__h12493 ; + assign x__h12492 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[88] } ; + assign x__h14016 = + tagController_tmp_tagCon$memory_request_get[90] ? 4'd0 : 4'd15 ; + assign x__h15424 = + (tagController_tmp_tagCon$memory_request_get[93:92] == 2'd0) ? + arcache__h15348 : + 4'd0 ; + assign x__h56232 = + merged_0_outflit$wget[166:103] - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h56267 = + merged_0_outflit$wget[166:103] - + soc_map$m_plic_addr_range[127:64] ; + assign x__h59744 = + merged_1_outflit$wget[166:103] - + soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h59769 = + merged_1_outflit$wget[166:103] - + soc_map$m_plic_addr_range[127:64] ; + assign x__h62625 = + ssNoSynth_0_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_bNoSynth_buffer_ff$D_OUT[6:2] : + uncached_mem_shim_bff$D_OUT[6:2] ; + assign x__h63516 = + ssNoSynth_1_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_bNoSynth_buffer_ff$D_OUT[6:2] : + ssNoSynth_1_bNoSynth_buffer_enqw$wget[6:2] ; + assign x__h64407 = + ssNoSynth_2_bNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_2_bNoSynth_buffer_ff$D_OUT[6:2] : + ssNoSynth_2_bNoSynth_buffer_enqw$wget[6:2] ; + assign x__h69923 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h70026 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h70391 = + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & + arbiter_firstHot ; + assign x__h70450 = + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852 && + SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 ; + assign x__h70532 = SEXT_x0450__q8[0] & arbiter_firstHot ; + assign x__h8010 = + tagController_tmp_addrOffset + + (64'd1 << tagController_tmp_awreqff$D_OUT[20:18]) ; + assign x__h84580 = x__h84582 | y__h84583 ; + assign x__h84582 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h84731 = x__h84733 | y__h84734 ; + assign x__h84733 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h84867 = x__h84869 | y__h84870 ; + assign x__h84869 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h85339 = x__h85341 | y__h85342 ; + assign x__h85341 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_firstHot ; + assign x__h85401 = + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && + SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 ; + assign x__h85435 = + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059 && + SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 ; + assign x__h85527 = x__h85529 | y__h85530 ; + assign x__h85529 = SEXT_x5401__q13[0] & arbiter_1_firstHot ; + assign x__h85708 = x__h85710 | y__h85711 ; + assign x__h85710 = SEXT_x5435__q14[0] & arbiter_1_firstHot ; + assign x__h93834 = + addr__h93758 - soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h93859 = addr__h93758 - soc_map$m_plic_addr_range[127:64] ; + assign x__h94920 = + msNoSynth_0_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_0_arNoSynth_buffer_ff$D_OUT[28:21] : + proc$master1_ar_peek[28:21] ; + assign x__h95023 = CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? ifcs_0_1_noRoute_flitCount$port0__write_1 : ifcs_0_1_noRoute_flitCount ; - assign x_port1__read__h75154 = + assign x__h96451 = + addr__h96375 - soc_map$m_mem0_controller_addr_range[127:64] ; + assign x__h96476 = addr__h96375 - soc_map$m_plic_addr_range[127:64] ; + assign x__h97519 = + msNoSynth_1_arNoSynth_buffer_ff$EMPTY_N ? + msNoSynth_1_arNoSynth_buffer_ff$D_OUT[28:21] : + msNoSynth_1_arNoSynth_buffer_enqw$wget[28:21] ; + assign x__h97622 = CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? ifcs_1_1_noRoute_flitCount$port0__write_1 : ifcs_1_1_noRoute_flitCount ; - assign x_rdata__h25045 = - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[67:4] : - msNoSynth_0_r_buffer_enqw$wget[67:4] ; - assign x_rid__h25044 = - msNoSynth_0_r_buffer_ff$EMPTY_N ? - msNoSynth_0_r_buffer_ff$D_OUT[71:68] : - msNoSynth_0_r_buffer_enqw$wget[71:68] ; - assign y__h12618 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; - assign y__h12630 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; - assign y__h12642 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; - assign y__h12654 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; - assign y__h12666 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; - assign y__h12678 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; - assign y__h12690 = - { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; - assign y__h48454 = - SEXT_arbiter_firstHot__q5[0] & - (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; - assign y__h48557 = - SEXT_arbiter_lastSelect__q6[0] & - (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; - assign y__h48922 = SEXT_x8980__q8[0] & arbiter_lastSelect ; - assign y__h49063 = - SEXT_SEXT_arbiter_firstHot_487_488_BIT_0_489_A_ETC__q7[0] & - arbiter_lastSelect ; - assign y__h62646 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62648 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h62797 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62799 = - SEXT_arbiter_1_firstHot__q9[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h62933 = - SEXT_arbiter_1_lastSelect_1__q11[0] & - (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; - assign y__h62935 = - SEXT_arbiter_1_lastSelect__q10[0] & - (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; - assign y__h63405 = SEXT_x3500__q14[0] & arbiter_1_lastSelect ; - assign y__h63407 = SEXT_x3466__q13[0] & arbiter_1_lastSelect_1 ; - assign y__h63593 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_lastSelect ; - assign y__h63595 = SEXT_x3500__q14[0] & arbiter_1_lastSelect_1 ; - assign y__h63774 = SEXT_x3466__q13[0] & arbiter_1_lastSelect ; - assign y__h63776 = - SEXT_SEXT_arbiter_1_firstHot_682_683_BIT_0_684_ETC__q12[0] & - arbiter_1_lastSelect_1 ; - assign y__h82221 = + assign x__h98415 = + ssNoSynth_0_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[72:68] : + uncached_mem_shim_rff$D_OUT[72:68] ; + assign x__h99370 = + ssNoSynth_1_rNoSynth_buffer_ff$EMPTY_N ? + ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[72:68] : + ssNoSynth_1_rNoSynth_buffer_enqw$wget[72:68] ; + assign y__h105697 = SEXT_arbiter_1_firstHot_1__q15[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; - assign y__h82324 = + assign y__h105800 = SEXT_arbiter_1_lastSelect_2__q16[0] & (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; - assign y__h82689 = SEXT_x2747__q18[0] & arbiter_1_lastSelect_2 ; - assign y__h82830 = - SEXT_SEXT_arbiter_1_firstHot_1_130_131_BIT_0_1_ETC__q17[0] & + assign y__h106165 = SEXT_x06223__q18[0] & arbiter_1_lastSelect_2 ; + assign y__h106306 = + SEXT_SEXT_arbiter_1_firstHot_1_545_546_BIT_0_5_ETC__q17[0] & arbiter_1_lastSelect_2 ; - assign y__h93872 = + assign y__h117855 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h93874 = + assign y__h117857 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94023 = + assign y__h118006 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h94025 = + assign y__h118008 = SEXT_arbiter_1_1_firstHot__q19[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94159 = + assign y__h118142 = SEXT_arbiter_1_1_lastSelect_1__q21[0] & (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; - assign y__h94161 = + assign y__h118144 = SEXT_arbiter_1_1_lastSelect__q20[0] & (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; - assign y__h94631 = SEXT_x4726__q24[0] & arbiter_1_1_lastSelect ; - assign y__h94633 = SEXT_x4692__q23[0] & arbiter_1_1_lastSelect_1 ; - assign y__h94819 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign y__h118614 = SEXT_x18709__q24[0] & arbiter_1_1_lastSelect ; + assign y__h118616 = SEXT_x18675__q23[0] & arbiter_1_1_lastSelect_1 ; + assign y__h118802 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect ; - assign y__h94821 = SEXT_x4726__q24[0] & arbiter_1_1_lastSelect_1 ; - assign y__h95000 = SEXT_x4692__q23[0] & arbiter_1_1_lastSelect ; - assign y__h95002 = - SEXT_SEXT_arbiter_1_1_firstHot_315_316_BIT_0_3_ETC__q22[0] & + assign y__h118804 = SEXT_x18709__q24[0] & arbiter_1_1_lastSelect_1 ; + assign y__h118983 = SEXT_x18675__q23[0] & arbiter_1_1_lastSelect ; + assign y__h118985 = + SEXT_SEXT_arbiter_1_1_firstHot_734_735_BIT_0_7_ETC__q22[0] & arbiter_1_1_lastSelect_1 ; + assign y__h12421 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[81] } ; + assign y__h12433 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[82] } ; + assign y__h12445 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[83] } ; + assign y__h12457 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[84] } ; + assign y__h12469 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[85] } ; + assign y__h12481 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[86] } ; + assign y__h12493 = + { 3'd0, tagController_tmp_tagCon$memory_request_get[87] } ; + assign y__h69924 = + SEXT_arbiter_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h70027 = + SEXT_arbiter_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h70392 = SEXT_x0450__q8[0] & arbiter_lastSelect ; + assign y__h70533 = + SEXT_SEXT_arbiter_firstHot_844_845_BIT_0_846_A_ETC__q7[0] & + arbiter_lastSelect ; + assign y__h84581 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84583 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h84732 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84734 = + SEXT_arbiter_1_firstHot__q9[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h84868 = + SEXT_arbiter_1_lastSelect_1__q11[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h84870 = + SEXT_arbiter_1_lastSelect__q10[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h85340 = SEXT_x5435__q14[0] & arbiter_1_lastSelect ; + assign y__h85342 = SEXT_x5401__q13[0] & arbiter_1_lastSelect_1 ; + assign y__h85528 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_lastSelect ; + assign y__h85530 = SEXT_x5435__q14[0] & arbiter_1_lastSelect_1 ; + assign y__h85709 = SEXT_x5401__q13[0] & arbiter_1_lastSelect ; + assign y__h85711 = + SEXT_SEXT_arbiter_1_firstHot_043_044_BIT_0_045_ETC__q12[0] & + arbiter_1_lastSelect_1 ; // handling of inlined registers @@ -9677,15 +12107,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) begin - v__h22825 = $stime; + v__h27371 = $stime; #0; end - v__h22819 = v__h22825 / 32'd10; + v__h27365 = v__h27371 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset) $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", - v__h22819, + v__h27365, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) @@ -9693,29 +12123,29 @@ module mkCoreW(RST_N_dm_power_on_reset, if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) begin - v__h22968 = $stime; + v__h27514 = $stime; #0; end - v__h22962 = v__h22968 / 32'd10; + v__h27508 = v__h27514 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && rg_hart0_reset_delay == 8'd1) $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h22962, + v__h27508, 64'h0000000070000000, rg_tohost_addr, rg_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && - !SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 && - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) + !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate && - !SEXT_arbiter_lastSelect_483_484_BIT_0_485_AND__ETC___d1491 && - !SEXT_arbiter_firstHot_487_488_BIT_0_489_AND_re_ETC___d1495) + !SEXT_arbiter_lastSelect_840_841_BIT_0_842_AND__ETC___d1848 && + !SEXT_arbiter_firstHot_844_845_BIT_0_846_AND_re_ETC___d1852) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && @@ -9724,7 +12154,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h50461 = $time; + v__h71925 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -9734,7 +12164,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h50461, + v__h71925, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && @@ -9843,13 +12273,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) begin - v__h49850 = $time; + v__h71314 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h49850, + v__h71314, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) @@ -9861,7 +12291,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h54470 = $time; + v__h75934 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -9871,7 +12301,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h54470, + v__h75934, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && @@ -9980,13 +12410,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) begin - v__h53859 = $time; + v__h75323 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h53859, + v__h75323, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) @@ -10008,15 +12438,352 @@ module mkCoreW(RST_N_dm_power_on_reset, if ((WILL_FIRE_RL_sink_selected || WILL_FIRE_RL_sink_selected_1) && WILL_FIRE_RL_sink_selected_2) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected,\n RL_sink_selected_1] and [RL_sink_selected_2] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_034_035_BIT_0_036_AN_ETC___d2047 && + !SEXT_arbiter_1_lastSelect_1_038_039_BIT_0_040__ETC___d2053 && + !SEXT_arbiter_1_firstHot_043_044_BIT_0_045_AND__ETC___d2059) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h87100 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h87100, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + begin + v__h86719 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h86719, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h89170 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h89170, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + begin + v__h88789 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h88789, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h91069 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", + v__h91069, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + begin + v__h90688 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", + v__h90688, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && + (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || + WILL_FIRE_RL_source_selected_3 || + WILL_FIRE_RL_burst_3) && + (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && - !SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 && - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) + !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_2 && - !SEXT_arbiter_1_lastSelect_2_126_127_BIT_0_128__ETC___d2134 && - !SEXT_arbiter_1_firstHot_1_130_131_BIT_0_132_AN_ETC___d2138) + !SEXT_arbiter_1_lastSelect_2_541_542_BIT_0_543__ETC___d2549 && + !SEXT_arbiter_1_firstHot_1_545_546_BIT_0_547_AN_ETC___d2553) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && @@ -10025,7 +12792,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h84222 = $time; + v__h107698 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10035,7 +12802,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h84222, + v__h107698, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && @@ -10144,13 +12911,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) begin - v__h83611 = $time; + v__h107087 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h83611, + v__h107087, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) @@ -10162,7 +12929,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) begin - v__h87115 = $time; + v__h110591 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10172,7 +12939,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h87115, + v__h110591, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && @@ -10281,13 +13048,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) begin - v__h86504 = $time; + v__h109980 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h86504, + v__h109980, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) @@ -10309,575 +13076,17 @@ module mkCoreW(RST_N_dm_power_on_reset, if ((WILL_FIRE_RL_sink_selected_5 || WILL_FIRE_RL_sink_selected_6) && WILL_FIRE_RL_sink_selected_7) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5,\n RL_sink_selected_6] and [RL_sink_selected_7] ) fired in the same clock\n cycle.\n"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ug_uncached_mem_shim_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - split_0_doPut$wget[1] && - split_0_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - split_0_doPut$wget[1] && - split_0_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - !split_0_doPut$wget[1] && - split_0_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && - !split_0_doPut$wget[1] && - split_0_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - split_1_doPut$wget[1] && - split_1_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - split_1_doPut$wget[1] && - split_1_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - !split_1_doPut$wget[1] && - split_1_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && - !split_1_doPut$wget[1] && - split_1_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) - $display("Expecting FirstFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - split_2_doPut$wget[1] && - split_2_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - split_2_doPut$wget[1] && - split_2_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - !split_2_doPut$wget[1] && - split_2_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && - !split_2_doPut$wget[1] && - split_2_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) - $display("Expecting OtherFlit of merged write"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && - WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_arbitrate_1 && - !SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 && - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) - $display("mkOneHotArbiter: next method should not be run with no pending request"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_arbitrate_1 && - !SEXT_arbiter_1_lastSelect_673_674_BIT_0_675_AN_ETC___d1686 && - !SEXT_arbiter_1_lastSelect_1_677_678_BIT_0_679__ETC___d1692 && - !SEXT_arbiter_1_firstHot_682_683_BIT_0_684_AND__ETC___d1698) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h65165 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h65165, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && - (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - begin - v__h64784 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h64784, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h67235 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h67235, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && - (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - begin - v__h66854 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h66854, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - begin - v__h69134 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h69134, - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $write(" is not a valid one-hot path.", "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && - (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + - (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != - 2'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - begin - v__h68753 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h68753, - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && - (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || - WILL_FIRE_RL_source_selected_3 || - WILL_FIRE_RL_burst_3) && - (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && - WILL_FIRE_RL_ifcs_0_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_followFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_drainFlits && - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && - merged_0_flitLeft > 8'd1) - $display("Expecting more write data flits"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && proc$master1_wlast && - merged_0_flitLeft > 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && - merged_0_flitLeft == 8'd1) - $display("Expecting last write data flit"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_0_genOther && !proc$master1_wlast && - merged_0_flitLeft == 8'd1) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && - WILL_FIRE_RL_ifcs_0_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && - WILL_FIRE_RL_ifcs_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && - !SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 && - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) + !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $display("mkOneHotArbiter: next method should not be run with no pending request"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate_3 && - !SEXT_arbiter_1_1_lastSelect_306_307_BIT_0_308__ETC___d2319 && - !SEXT_arbiter_1_1_lastSelect_1_310_311_BIT_0_31_ETC___d2325 && - !SEXT_arbiter_1_1_firstHot_315_316_BIT_0_317_AN_ETC___d2331) + !SEXT_arbiter_1_1_lastSelect_725_726_BIT_0_727__ETC___d2738 && + !SEXT_arbiter_1_1_lastSelect_1_729_730_BIT_0_73_ETC___d2744 && + !SEXT_arbiter_1_1_firstHot_734_735_BIT_0_736_AN_ETC___d2750) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && @@ -10885,7 +13094,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h96395 = $time; + v__h120378 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10894,7 +13103,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h96395, + v__h120378, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && @@ -10969,13 +13178,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) begin - v__h96014 = $time; + v__h119997 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h96014, + v__h119997, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) @@ -10986,7 +13195,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h98886 = $time; + v__h122869 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -10995,7 +13204,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h98886, + v__h122869, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && @@ -11070,13 +13279,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) begin - v__h98505 = $time; + v__h122488 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h98505, + v__h122488, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) @@ -11090,7 +13299,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) begin - v__h101196 = $time; + v__h125179 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -11099,7 +13308,7 @@ module mkCoreW(RST_N_dm_power_on_reset, (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != 2'd1) $write("%0t -- mkOneWayBus error: input %0d was selected but the requested path ", - v__h101196, + v__h125179, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && @@ -11174,13 +13383,13 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) begin - v__h100815 = $time; + v__h124798 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) $display("%0t -- mkOneWayBus error: input %0d was selected but there was no requested path.", - v__h100815, + v__h124798, $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) @@ -11204,183 +13413,576 @@ module mkCoreW(RST_N_dm_power_on_reset, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sink_selected_8 && WILL_FIRE_RL_sink_selected_9) $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 154, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_8] and\n [RL_sink_selected_9] ) fired in the same clock cycle.\n"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_uncached_mem_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tmp2_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_aw_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_1_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_w_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_b_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_2_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_3_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_ar_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_slave_u_r_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_Prelude_inst_changeSpecialWires_4_ug_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_0_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_bNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_rNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit && - WILL_FIRE_RL_ifcs_0_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_0_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_1_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_awNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_wNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_arNoSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[172]) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + split_0_doPut$wget[1] && + split_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[172] && + !split_0_doPut$wget[1] && + split_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[172]) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_followFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_slave_vector_0_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + split_1_doPut$wget[1] && + split_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[172] && + !split_1_doPut$wget[1] && + split_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_2_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $display("splitWrite - Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $display("splitWrite - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + split_2_doPut$wget[1] && + split_2_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $display("splitWrite - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[172] && + !split_2_doPut$wget[1] && + split_2_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $display("splitWrite - Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[172]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_drainFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && + merged_0_flitLeft > 8'd1) + $display("%m - Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && merged_0_wff$D_OUT[1] && + merged_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && + merged_0_flitLeft == 8'd1) + $display("%m - Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !merged_0_wff$D_OUT[1] && + merged_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_drainFlits && - WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_sinks_1_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && - WILL_FIRE_RL_ifcs_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_followFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_drainFlits && - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_drainFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && - merged_1_flitLeft > 8'd1) - $display("Expecting more write data flits"); + if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && + merged_1_flitLeft > 8'd1) + $display("%m - Expecting more write data flits"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && debug_module$master_wlast && - merged_1_flitLeft > 8'd1) - $finish(32'd0); + if (WILL_FIRE_RL_merged_1_genOther && merged_1_wff$D_OUT[1] && + merged_1_flitLeft > 8'd1) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && - merged_1_flitLeft == 8'd1) - $display("Expecting last write data flit"); + if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && + merged_1_flitLeft == 8'd1) + $display("%m - Expecting last write data flit"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_merged_1_genOther && !debug_module$master_wlast && - merged_1_flitLeft == 8'd1) - $finish(32'd0); + if (WILL_FIRE_RL_merged_1_genOther && !merged_1_wff$D_OUT[1] && + merged_1_flitLeft == 8'd1) + $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_firstFlit && - WILL_FIRE_RL_ifcs_1_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_followFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && - WILL_FIRE_RL_ifcs_1_1_drainFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_1_1_drainFlits && - WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 216, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && - WILL_FIRE_RL_ifcs_0_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_1_followFlits_1) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && WILL_FIRE_RL_ifcs_1_1_followFlits_1) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 283, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_0_warnDoPut_1) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_vector_0_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_warnDoPut_1) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h103640 = $stime; + v__h128907 = $stime; #0; end - v__h103634 = v__h103640 / 32'd10; + v__h128901 = v__h128907 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h103634, + v__h128901, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_2_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_bNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ssNoSynth_2_rNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_1_firstFlit && + WILL_FIRE_RL_ifcs_2_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 281, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_0_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_drainFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_ifcs_2_1_firstFlit && - WILL_FIRE_RL_ifcs_2_1_followFlits) - $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 282, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_proc_uncached_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sinks_1_1_1_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_awNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_wNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_msNoSynth_1_arNoSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_followFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 214, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_drainFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff/Interconnect.bsv\", line 215, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_aw_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_w_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_b_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_ar_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cached_mem_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_tagController_tmp_ug_master_u_r_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v index e65be88..9a7f2e1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:10 BST 2020 +// On Wed Jun 24 20:31:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v index a004347..a5ea406 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:00 BST 2020 +// On Wed Jun 24 20:23:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v index 4176804..52cd854 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:59 BST 2020 +// On Wed Jun 24 20:23:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v index 8261ced..69cefb4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:15 BST 2020 +// On Wed Jun 24 20:24:14 BST 2020 // // // Ports: @@ -46,9 +46,11 @@ // write_dm_word I 32 // master_awready I 1 // master_wready I 1 +// master_bvalid I 1 // master_bid I 4 // master_bresp I 2 // master_arready I 1 +// master_rvalid I 1 // master_rid I 4 // master_rdata I 64 // master_rresp I 2 @@ -56,154 +58,153 @@ // master_ruser I 1 // EN_reset I 1 // EN_write I 1 -// master_bvalid I 1 -// master_rvalid I 1 // EN_av_read I 1 // // Combinational paths from inputs to outputs: // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awid +// EN_write) -> master_awid // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awaddr +// EN_write) -> master_awaddr // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awlen +// EN_write) -> master_awlen // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awsize +// EN_write) -> master_awsize // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awburst +// EN_write) -> master_awburst // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awlock +// EN_write) -> master_awlock // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awcache +// EN_write) -> master_awcache // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awprot +// EN_write) -> master_awprot // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awqos +// EN_write) -> master_awqos // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awregion +// EN_write) -> master_awregion // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awuser +// EN_write) -> master_awuser // (write_dm_addr, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_awvalid +// EN_write) -> master_awvalid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wdata +// EN_write) -> master_wdata // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wstrb +// EN_write) -> master_wstrb // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wlast +// EN_write) -> master_wlast // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wuser +// EN_write) -> master_wuser // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, -// EN_write, -// master_rvalid) -> master_wvalid +// EN_write) -> master_wvalid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -211,10 +212,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arid // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -222,10 +223,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_araddr // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -233,10 +234,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arlen // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -244,10 +245,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arsize // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -255,10 +256,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arburst // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -266,10 +267,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arlock // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -277,10 +278,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arcache // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -288,10 +289,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arprot // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -299,10 +300,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arqos // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -310,10 +311,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arregion // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -321,10 +322,10 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_aruser // (write_dm_addr, // write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, @@ -332,7 +333,6 @@ // master_ruser, // av_read_dm_addr, // EN_write, -// master_rvalid, // EN_av_read) -> master_arvalid // av_read_dm_addr -> av_read // @@ -403,9 +403,9 @@ module mkDM_System_Bus(CLK, master_wready, + master_bvalid, master_bid, master_bresp, - master_bvalid, master_bready, @@ -433,12 +433,12 @@ module mkDM_System_Bus(CLK, master_arready, + master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, master_ruser, - master_rvalid, master_rready); input CLK; @@ -517,9 +517,9 @@ module mkDM_System_Bus(CLK, input master_wready; // action method master_b_bflit + input master_bvalid; input [3 : 0] master_bid; input [1 : 0] master_bresp; - input master_bvalid; // value method master_b_bready output master_bready; @@ -563,12 +563,12 @@ module mkDM_System_Bus(CLK, input master_arready; // action method master_r_rflit + input master_rvalid; input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; input master_ruser; - input master_rvalid; // value method master_r_rready output master_rready; @@ -617,18 +617,18 @@ module mkDM_System_Bus(CLK, master_xactor_shim_rff_rv$port1__read, master_xactor_shim_rff_rv$port2__read, master_xactor_shim_rff_rv$port3__read; - wire [71 : 0] master_xactor_ug_master_u_r_putWire$wget; + wire [71 : 0] master_xactor_master_rSynth_snk_putWire$wget; wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1, master_xactor_shim_bff_rv$port1__read, master_xactor_shim_bff_rv$port2__read, master_xactor_shim_bff_rv$port3__read; - wire [5 : 0] master_xactor_ug_master_u_b_putWire$wget; - wire master_xactor_shim_arff_rv$EN_port0__write, - master_xactor_ug_master_u_ar_dropWire$whas, - master_xactor_ug_master_u_aw_dropWire$whas, - master_xactor_ug_master_u_b_putWire$whas, - master_xactor_ug_master_u_r_putWire$whas, - master_xactor_ug_master_u_w_dropWire$whas; + wire [5 : 0] master_xactor_master_bSynth_snk_putWire$wget; + wire master_xactor_master_arSynth_src_dropWire$whas, + master_xactor_master_awSynth_src_dropWire$whas, + master_xactor_master_bSynth_snk_putWire$whas, + master_xactor_master_rSynth_snk_putWire$whas, + master_xactor_master_wSynth_src_dropWire$whas, + master_xactor_shim_arff_rv$EN_port0__write; // register master_xactor_clearing reg master_xactor_clearing; @@ -713,19 +713,19 @@ module mkDM_System_Bus(CLK, // rule scheduling signals wire CAN_FIRE_RL_master_xactor_do_clear, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut, + CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut, + CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop, + CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek, + CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, CAN_FIRE_av_read, @@ -737,19 +737,19 @@ module mkDM_System_Bus(CLK, CAN_FIRE_reset, CAN_FIRE_write, WILL_FIRE_RL_master_xactor_do_clear, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut, + WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut, + WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop, + WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek, + WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_rl_sb_read_finish, WILL_FIRE_RL_rl_sb_write_response, WILL_FIRE_av_read, @@ -784,38 +784,38 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117, IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155, IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_IF_rg_sbaddr_ETC___d130, - wrd_wdata__h7269; - reg [7 : 0] wrd_wstrb__h7270; - reg [2 : 0] _theResult___snd_snd_val__h7160, axi4_size_val__h5415; + wrd_wdata__h7347; + reg [7 : 0] wrd_wstrb__h7348; + reg [2 : 0] _theResult___snd_snd_val__h7238, axi4_size_val__h5493; wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3, master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1; wire [73 : 0] master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2; - wire [63 : 0] _theResult___fst__h7145, - addr64__h6432, - result__h3808, - result__h3838, - result__h3865, - result__h3892, - result__h3919, - result__h3946, - result__h3973, - result__h4000, - result__h4045, - result__h4072, - result__h4099, - result__h4126, - result__h4167, - result__h4194, + wire [63 : 0] _theResult___fst__h7223, + addr64__h6510, + result__h3886, + result__h3916, + result__h3943, + result__h3970, + result__h3997, + result__h4024, + result__h4051, + result__h4078, + result__h4123, + result__h4150, + result__h4177, + result__h4204, + result__h4245, + result__h4272, rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156, rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354, - sbaddress__h3099, - word64__h7090; + sbaddress__h3177, + word64__h7168; wire [31 : 0] IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365, IF_write_dm_addr_EQ_0x39_13_THEN_rg_sbaddress1_ETC___d356, - v__h4807, - v__h4941; - wire [7 : 0] strobe64__h7143, strobe64__h7147, strobe64__h7151; - wire [5 : 0] shift_bits__h7093; + v__h4885, + v__h5019; + wire [7 : 0] strobe64__h7221, strobe64__h7225, strobe64__h7229; + wire [5 : 0] shift_bits__h7171; wire rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147, rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162, rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d371, @@ -834,13 +834,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h4807 or rg_sbaddress0 or rg_sbaddress1 or v__h4941) + v__h4885 or rg_sbaddress0 or rg_sbaddress1 or v__h5019) begin case (av_read_dm_addr) - 7'h38: av_read = v__h4807; + 7'h38: av_read = v__h4885; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h4941; + 7'h3C: av_read = v__h5019; default: av_read = 32'd0; endcase end @@ -906,7 +906,8 @@ module mkDM_System_Bus(CLK, master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[3:0] ; // value method master_aw_awvalid - assign master_awvalid = CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + assign master_awvalid = + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ; // action method master_aw_awready assign CAN_FIRE_master_aw_awready = 1'd1 ; @@ -929,7 +930,7 @@ module mkDM_System_Bus(CLK, master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2[0] ; // value method master_w_wvalid - assign master_wvalid = CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + assign master_wvalid = CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ; // action method master_w_wready assign CAN_FIRE_master_w_wready = 1'd1 ; @@ -937,7 +938,7 @@ module mkDM_System_Bus(CLK, // action method master_b_bflit assign CAN_FIRE_master_b_bflit = 1'd1 ; - assign WILL_FIRE_master_b_bflit = master_bvalid ; + assign WILL_FIRE_master_b_bflit = 1'd1 ; // value method master_b_bready assign master_bready = !master_xactor_shim_bff_rv[6] ; @@ -983,7 +984,8 @@ module mkDM_System_Bus(CLK, master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[3:0] ; // value method master_ar_arvalid - assign master_arvalid = CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + assign master_arvalid = + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ; // action method master_ar_arready assign CAN_FIRE_master_ar_arready = 1'd1 ; @@ -991,38 +993,38 @@ module mkDM_System_Bus(CLK, // action method master_r_rflit assign CAN_FIRE_master_r_rflit = 1'd1 ; - assign WILL_FIRE_master_r_rflit = master_rvalid ; + assign WILL_FIRE_master_r_rflit = 1'd1 ; // value method master_r_rready assign master_rready = !master_xactor_shim_rff_rv[72] ; - // rule RL_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = - master_xactor_ug_master_u_b_putWire$whas && + // rule RL_master_xactor_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut = + master_xactor_master_bSynth_snk_putWire$whas && master_xactor_shim_bff_rv[6] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut ; - // rule RL_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut = + // rule RL_master_xactor_master_bSynth_snk_doPut + assign CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut = !master_xactor_shim_bff_rv[6] && - master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ; + master_xactor_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_bSynth_snk_doPut = + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ; - // rule RL_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = - master_xactor_ug_master_u_r_putWire$whas && + // rule RL_master_xactor_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut = + master_xactor_master_rSynth_snk_putWire$whas && master_xactor_shim_rff_rv[72] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut ; - // rule RL_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut = + // rule RL_master_xactor_master_rSynth_snk_doPut + assign CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut = !master_xactor_shim_rff_rv[72] && - master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ; + master_xactor_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_rSynth_snk_doPut = + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ; // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = @@ -1039,65 +1041,65 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_RL_rl_sb_write_response = CAN_FIRE_RL_rl_sb_write_response ; - // rule RL_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + // rule RL_master_xactor_master_awSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek = master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_awSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = - master_xactor_ug_master_u_aw_dropWire$whas && + // rule RL_master_xactor_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop = + master_xactor_master_awSynth_src_dropWire$whas && !master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + // rule RL_master_xactor_master_awSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop = master_xactor_shim_awff_rv$port1__read[97] && - master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ; + master_xactor_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_awSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ; - // rule RL_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + // rule RL_master_xactor_master_wSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek = master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_wSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = - master_xactor_ug_master_u_w_dropWire$whas && + // rule RL_master_xactor_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop = + master_xactor_master_wSynth_src_dropWire$whas && !master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + // rule RL_master_xactor_master_wSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop = master_xactor_shim_wff_rv$port1__read[74] && - master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ; + master_xactor_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_wSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ; - // rule RL_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + // rule RL_master_xactor_master_arSynth_src_setPeek + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek = master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_setPeek = + CAN_FIRE_RL_master_xactor_master_arSynth_src_setPeek ; - // rule RL_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = - master_xactor_ug_master_u_ar_dropWire$whas && + // rule RL_master_xactor_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop = + master_xactor_master_arSynth_src_dropWire$whas && !master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop ; - // rule RL_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + // rule RL_master_xactor_master_arSynth_src_doDrop + assign CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop = master_xactor_shim_arff_rv$port1__read[97] && - master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ; + master_xactor_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_master_arSynth_src_doDrop = + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ; // rule RL_master_xactor_do_clear assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; @@ -1144,12 +1146,12 @@ module mkDM_System_Bus(CLK, write_dm_addr_EQ_0x3C_16_AND_rg_sb_state_7_EQ__ETC___d381 ; assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = { 5'd16, - sbaddress__h3099, + sbaddress__h3177, 8'd0, - axi4_size_val__h5415, + axi4_size_val__h5493, 18'd65536 } ; assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = - { 5'd16, addr64__h6432, 8'd0, axi4_size_val__h5415, 18'd65536 } ; + { 5'd16, addr64__h6510, 8'd0, axi4_size_val__h5493, 18'd65536 } ; always@(write_dm_addr or rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 or IF_rg_sbcs_sbreadonaddr_76_THEN_IF_rg_sbcs_sba_ETC___d365) @@ -1183,36 +1185,36 @@ module mkDM_System_Bus(CLK, end // inlined wires - assign master_xactor_ug_master_u_b_putWire$wget = + assign master_xactor_master_bSynth_snk_putWire$wget = { master_bid, master_bresp } ; - assign master_xactor_ug_master_u_b_putWire$whas = + assign master_xactor_master_bSynth_snk_putWire$whas = master_bvalid && !master_xactor_shim_bff_rv[6] ; - assign master_xactor_ug_master_u_r_putWire$wget = + assign master_xactor_master_rSynth_snk_putWire$wget = { master_rid, master_rdata, master_rresp, master_rlast, master_ruser } ; - assign master_xactor_ug_master_u_r_putWire$whas = + assign master_xactor_master_rSynth_snk_putWire$whas = master_rvalid && !master_xactor_shim_rff_rv[72] ; - assign master_xactor_ug_master_u_aw_dropWire$whas = + assign master_xactor_master_awSynth_src_dropWire$whas = master_xactor_shim_awff_rv$port1__read[97] && master_awready ; - assign master_xactor_ug_master_u_w_dropWire$whas = + assign master_xactor_master_wSynth_src_dropWire$whas = master_xactor_shim_wff_rv$port1__read[74] && master_wready ; - assign master_xactor_ug_master_u_ar_dropWire$whas = + assign master_xactor_master_arSynth_src_dropWire$whas = master_xactor_shim_arff_rv$port1__read[97] && master_arready ; assign master_xactor_shim_awff_rv$port0__write_1 = { 5'd16, - sbaddress__h3099, + sbaddress__h3177, 8'd0, - _theResult___snd_snd_val__h7160, + _theResult___snd_snd_val__h7238, 18'd65536 } ; assign master_xactor_shim_awff_rv$port1__read = MUX_rg_sbdata0$write_1__SEL_3 ? master_xactor_shim_awff_rv$port0__write_1 : master_xactor_shim_awff_rv ; assign master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ? + CAN_FIRE_RL_master_xactor_master_awSynth_src_doDrop ? 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_awff_rv$port1__read ; assign master_xactor_shim_awff_rv$port3__read = @@ -1220,13 +1222,13 @@ module mkDM_System_Bus(CLK, 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_awff_rv$port2__read ; assign master_xactor_shim_wff_rv$port0__write_1 = - { 1'd1, wrd_wdata__h7269, wrd_wstrb__h7270, 2'd2 } ; + { 1'd1, wrd_wdata__h7347, wrd_wstrb__h7348, 2'd2 } ; assign master_xactor_shim_wff_rv$port1__read = MUX_rg_sbdata0$write_1__SEL_3 ? master_xactor_shim_wff_rv$port0__write_1 : master_xactor_shim_wff_rv ; assign master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ? + CAN_FIRE_RL_master_xactor_master_wSynth_src_doDrop ? 75'h2AAAAAAAAAAAAAAAAAA : master_xactor_shim_wff_rv$port1__read ; assign master_xactor_shim_wff_rv$port3__read = @@ -1234,9 +1236,9 @@ module mkDM_System_Bus(CLK, 75'h2AAAAAAAAAAAAAAAAAA : master_xactor_shim_wff_rv$port2__read ; assign master_xactor_shim_bff_rv$port0__write_1 = - { 1'd1, master_xactor_ug_master_u_b_putWire$wget } ; + { 1'd1, master_xactor_master_bSynth_snk_putWire$wget } ; assign master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ? + CAN_FIRE_RL_master_xactor_master_bSynth_snk_doPut ? master_xactor_shim_bff_rv$port0__write_1 : master_xactor_shim_bff_rv ; assign master_xactor_shim_bff_rv$port2__read = @@ -1261,7 +1263,7 @@ module mkDM_System_Bus(CLK, master_xactor_shim_arff_rv$port0__write_1 : master_xactor_shim_arff_rv ; assign master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ? + CAN_FIRE_RL_master_xactor_master_arSynth_src_doDrop ? 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_arff_rv$port1__read ; assign master_xactor_shim_arff_rv$port3__read = @@ -1269,9 +1271,9 @@ module mkDM_System_Bus(CLK, 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : master_xactor_shim_arff_rv$port2__read ; assign master_xactor_shim_rff_rv$port0__write_1 = - { 1'd1, master_xactor_ug_master_u_r_putWire$wget } ; + { 1'd1, master_xactor_master_rSynth_snk_putWire$wget } ; assign master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ? + CAN_FIRE_RL_master_xactor_master_rSynth_snk_doPut ? master_xactor_shim_rff_rv$port0__write_1 : master_xactor_shim_rff_rv ; assign master_xactor_shim_rff_rv$port2__read = @@ -1368,8 +1370,8 @@ module mkDM_System_Bus(CLK, // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? - sbaddress__h3099 : - addr64__h6432 ; + sbaddress__h3177 : + addr64__h6510 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d162 || @@ -1474,41 +1476,41 @@ module mkDM_System_Bus(CLK, (write_dm_addr == 7'h39) ? rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354[63:32] : write_dm_word ; - assign _theResult___fst__h7145 = word64__h7090 << shift_bits__h7093 ; - assign addr64__h6432 = { rg_sbaddress1, write_dm_word } ; + assign _theResult___fst__h7223 = word64__h7168 << shift_bits__h7171 ; + assign addr64__h6510 = { rg_sbaddress1, write_dm_word } ; assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3 = master_xactor_shim_arff_rv$port1__read[96:0] ; assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1 = master_xactor_shim_awff_rv$port1__read[96:0] ; assign master_xactor_shim_wff_rvport1__read_BITS_73__ETC__q2 = master_xactor_shim_wff_rv$port1__read[73:0] ; - assign result__h3808 = + assign result__h3886 = { 56'd0, master_xactor_shim_rff_rv$port1__read[11:4] } ; - assign result__h3838 = + assign result__h3916 = { 56'd0, master_xactor_shim_rff_rv$port1__read[19:12] } ; - assign result__h3865 = + assign result__h3943 = { 56'd0, master_xactor_shim_rff_rv$port1__read[27:20] } ; - assign result__h3892 = + assign result__h3970 = { 56'd0, master_xactor_shim_rff_rv$port1__read[35:28] } ; - assign result__h3919 = + assign result__h3997 = { 56'd0, master_xactor_shim_rff_rv$port1__read[43:36] } ; - assign result__h3946 = + assign result__h4024 = { 56'd0, master_xactor_shim_rff_rv$port1__read[51:44] } ; - assign result__h3973 = + assign result__h4051 = { 56'd0, master_xactor_shim_rff_rv$port1__read[59:52] } ; - assign result__h4000 = + assign result__h4078 = { 56'd0, master_xactor_shim_rff_rv$port1__read[67:60] } ; - assign result__h4045 = + assign result__h4123 = { 48'd0, master_xactor_shim_rff_rv$port1__read[19:4] } ; - assign result__h4072 = + assign result__h4150 = { 48'd0, master_xactor_shim_rff_rv$port1__read[35:20] } ; - assign result__h4099 = + assign result__h4177 = { 48'd0, master_xactor_shim_rff_rv$port1__read[51:36] } ; - assign result__h4126 = + assign result__h4204 = { 48'd0, master_xactor_shim_rff_rv$port1__read[67:52] } ; - assign result__h4167 = + assign result__h4245 = { 32'd0, master_xactor_shim_rff_rv$port1__read[35:4] } ; - assign result__h4194 = + assign result__h4272 = { 32'd0, master_xactor_shim_rff_rv$port1__read[67:36] } ; assign rg_sb_state_7_EQ_0_39_AND_NOT_rg_sbcs_sbbusyer_ETC___d147 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && @@ -1523,21 +1525,21 @@ module mkDM_System_Bus(CLK, rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadonaddr ; assign rg_sbaddress1_49_CONCAT_rg_sbaddress0_50_51_PL_ETC___d156 = - sbaddress__h3099 + + sbaddress__h3177 + IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ; assign rg_sbaddress1_49_CONCAT_write_dm_word_53_PLUS__ETC___d354 = - addr64__h6432 + + addr64__h6510 + IF_rg_sbcs_sbaccess_9_EQ_0_0_THEN_1_ELSE_IF_rg_ETC___d155 ; assign rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d346 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress__h3099 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h7093 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h7143 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h7147 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h7151 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h4807 = + assign sbaddress__h3177 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h7171 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h7221 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h7225 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h7229 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h4885 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1547,12 +1549,12 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd2055 } ; - assign v__h4941 = + assign v__h5019 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h7090 = { 32'd0, write_dm_word } ; + assign word64__h7168 = { 32'd0, write_dm_word } ; assign write_dm_addr_EQ_0x38_96_AND_rg_sbcs_sberror_9_ETC___d311 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && @@ -1585,34 +1587,34 @@ module mkDM_System_Bus(CLK, always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: axi4_size_val__h5415 = rg_sbcs_sbaccess; - default: axi4_size_val__h5415 = 3'b011; + 3'd0, 3'd1, 3'd2: axi4_size_val__h5493 = rg_sbcs_sbaccess; + default: axi4_size_val__h5493 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) 3'd0, 3'd1, 3'd2, 3'd3: - _theResult___snd_snd_val__h7160 = rg_sbcs_sbaccess; - default: _theResult___snd_snd_val__h7160 = 3'b111; + _theResult___snd_snd_val__h7238 = rg_sbcs_sbaccess; + default: _theResult___snd_snd_val__h7238 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h7143 or strobe64__h7147 or strobe64__h7151) + strobe64__h7221 or strobe64__h7225 or strobe64__h7229) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h7270 = strobe64__h7143; - 3'd1: wrd_wstrb__h7270 = strobe64__h7147; - 3'd2: wrd_wstrb__h7270 = strobe64__h7151; - 3'd3: wrd_wstrb__h7270 = 8'b11111111; - default: wrd_wstrb__h7270 = 8'd0; + 3'd0: wrd_wstrb__h7348 = strobe64__h7221; + 3'd1: wrd_wstrb__h7348 = strobe64__h7225; + 3'd2: wrd_wstrb__h7348 = strobe64__h7229; + 3'd3: wrd_wstrb__h7348 = 8'b11111111; + default: wrd_wstrb__h7348 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h7090 or _theResult___fst__h7145) + always@(rg_sbcs_sbaccess or word64__h7168 or _theResult___fst__h7223) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h7269 = _theResult___fst__h7145; - default: wrd_wdata__h7269 = word64__h7090; + 3'd0, 3'd1, 3'd2: wrd_wdata__h7347 = _theResult___fst__h7223; + default: wrd_wdata__h7347 = word64__h7168; endcase end always@(rg_sbcs_sbaccess) @@ -1627,68 +1629,68 @@ module mkDM_System_Bus(CLK, endcase end always@(rg_sbaddress_reading or - result__h3808 or - result__h3838 or - result__h3865 or - result__h3892 or - result__h3919 or result__h3946 or result__h3973 or result__h4000) + result__h3886 or + result__h3916 or + result__h3943 or + result__h3970 or + result__h3997 or result__h4024 or result__h4051 or result__h4078) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3808; + result__h3886; 3'h1: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3838; + result__h3916; 3'h2: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3865; + result__h3943; 3'h3: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3892; + result__h3970; 3'h4: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3919; + result__h3997; 3'h5: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3946; + result__h4024; 3'h6: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h3973; + result__h4051; 3'h7: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d104 = - result__h4000; + result__h4078; endcase end always@(rg_sbaddress_reading or - result__h4045 or result__h4072 or result__h4099 or result__h4126) + result__h4123 or result__h4150 or result__h4177 or result__h4204) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4045; + result__h4123; 3'h2: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4072; + result__h4150; 3'h4: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4099; + result__h4177; 3'h6: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = - result__h4126; + result__h4204; default: IF_rg_sbaddress_reading_1_BITS_2_TO_0_2_EQ_0x0_ETC___d117 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h4167 or result__h4194) + always@(rg_sbaddress_reading or result__h4245 or result__h4272) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = - result__h4167; + result__h4245; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = - result__h4194; + result__h4272; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q4 = 64'd0; endcase end @@ -1943,11 +1945,11 @@ module mkDM_System_Bus(CLK, av_read_dm_addr != 7'h3C) $write("] not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_master_xactor_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_master_xactor_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 && write_dm_word[14:12] == 3'd0) @@ -2204,14 +2206,14 @@ module mkDM_System_Bus(CLK, master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_master_xactor_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkDM_System_Bus diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v index 467c728..4e8f32a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:10 BST 2020 +// On Wed Jun 24 20:31:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v index 16d4073..055e7a2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:13 BST 2020 +// On Wed Jun 24 20:31:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v index 1f96002..6dcc0cb 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:43 BST 2020 +// On Wed Jun 24 20:31:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v index e4dd9c6..e9cc1ac 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:16 BST 2020 +// On Wed Jun 24 20:24:16 BST 2020 // // // Ports: @@ -72,9 +72,11 @@ // ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 +// master_bvalid I 1 // master_bid I 4 // master_bresp I 2 // master_arready I 1 +// master_rvalid I 1 // master_rid I 4 // master_rdata I 64 // master_rresp I 2 @@ -88,8 +90,6 @@ // EN_hart0_fpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 // EN_ndm_reset_client_response_put I 1 -// master_bvalid I 1 -// master_rvalid I 1 // EN_dmi_read_data I 1 // EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 @@ -101,265 +101,265 @@ // // Combinational paths from inputs to outputs: // (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awid -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awaddr -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awlen -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awsize -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awburst -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awlock -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awcache -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awprot -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awqos -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awregion -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awuser -// (dmi_write_dm_addr, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_awvalid -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wdata -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wstrb -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wlast -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wuser -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, -// master_rvalid) -> master_wvalid -// (dmi_write_dm_addr, -// dmi_write_dm_word, -// master_rid, -// master_rdata, -// master_rresp, -// master_rlast, -// master_ruser, -// EN_dmi_write, // master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awid +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awaddr +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awlen +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awsize +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awburst +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awlock +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awcache +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awprot +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awqos +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awregion +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awuser +// (dmi_write_dm_addr, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_awvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wdata +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wstrb +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wlast +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wuser +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write) -> master_wvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rvalid, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_ruser, +// EN_dmi_write, // EN_dmi_read_data) -> master_arid // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_araddr // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arlen // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arsize // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arburst // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arlock // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arcache // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arprot // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arqos // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arregion // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_aruser // (dmi_write_dm_addr, // dmi_write_dm_word, +// master_rvalid, // master_rid, // master_rdata, // master_rresp, // master_rlast, // master_ruser, // EN_dmi_write, -// master_rvalid, // EN_dmi_read_data) -> master_arvalid // EN_dmi_read_data -> dmi_read_data // @@ -482,9 +482,9 @@ module mkDebug_Module(CLK, master_wready, + master_bvalid, master_bid, master_bresp, - master_bvalid, master_bready, @@ -512,12 +512,12 @@ module mkDebug_Module(CLK, master_arready, + master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, master_ruser, - master_rvalid, master_rready); input CLK; @@ -661,9 +661,9 @@ module mkDebug_Module(CLK, input master_wready; // action method master_b_bflit + input master_bvalid; input [3 : 0] master_bid; input [1 : 0] master_bresp; - input master_bvalid; // value method master_b_bready output master_bready; @@ -707,12 +707,12 @@ module mkDebug_Module(CLK, input master_arready; // action method master_r_rflit + input master_rvalid; input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; input master_ruser; - input master_rvalid; // value method master_r_rready output master_rready; @@ -928,8 +928,8 @@ module mkDebug_Module(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h756; - reg [31 : 0] v__h750; + reg [31 : 0] v__h772; + reg [31 : 0] v__h766; // synopsys translate_on // action method dmi_read_addr @@ -1173,7 +1173,7 @@ module mkDebug_Module(CLK, // action method master_b_bflit assign CAN_FIRE_master_b_bflit = 1'd1 ; - assign WILL_FIRE_master_b_bflit = master_bvalid ; + assign WILL_FIRE_master_b_bflit = 1'd1 ; // value method master_b_bready assign master_bready = dm_system_bus$master_bready ; @@ -1217,7 +1217,7 @@ module mkDebug_Module(CLK, // action method master_r_rflit assign CAN_FIRE_master_r_rflit = 1'd1 ; - assign WILL_FIRE_master_r_rflit = master_rvalid ; + assign WILL_FIRE_master_r_rflit = 1'd1 ; // value method master_r_rready assign master_rready = dm_system_bus$master_rready ; @@ -1299,19 +1299,19 @@ module mkDebug_Module(CLK, .master_awready(dm_system_bus$master_awready), .master_bid(dm_system_bus$master_bid), .master_bresp(dm_system_bus$master_bresp), + .master_bvalid(dm_system_bus$master_bvalid), .master_rdata(dm_system_bus$master_rdata), .master_rid(dm_system_bus$master_rid), .master_rlast(dm_system_bus$master_rlast), .master_rresp(dm_system_bus$master_rresp), .master_ruser(dm_system_bus$master_ruser), + .master_rvalid(dm_system_bus$master_rvalid), .master_wready(dm_system_bus$master_wready), .write_dm_addr(dm_system_bus$write_dm_addr), .write_dm_word(dm_system_bus$write_dm_word), .EN_reset(dm_system_bus$EN_reset), .EN_av_read(dm_system_bus$EN_av_read), .EN_write(dm_system_bus$EN_write), - .master_bvalid(dm_system_bus$master_bvalid), - .master_rvalid(dm_system_bus$master_rvalid), .RDY_reset(dm_system_bus$RDY_reset), .av_read(dm_system_bus$av_read), .RDY_av_read(dm_system_bus$RDY_av_read), @@ -1474,11 +1474,13 @@ module mkDebug_Module(CLK, assign dm_system_bus$master_awready = master_awready ; assign dm_system_bus$master_bid = master_bid ; assign dm_system_bus$master_bresp = master_bresp ; + assign dm_system_bus$master_bvalid = master_bvalid ; assign dm_system_bus$master_rdata = master_rdata ; assign dm_system_bus$master_rid = master_rid ; assign dm_system_bus$master_rlast = master_rlast ; assign dm_system_bus$master_rresp = master_rresp ; assign dm_system_bus$master_ruser = master_ruser ; + assign dm_system_bus$master_rvalid = master_rvalid ; assign dm_system_bus$master_wready = master_wready ; assign dm_system_bus$write_dm_addr = dmi_write_dm_addr ; assign dm_system_bus$write_dm_word = dmi_write_dm_word ; @@ -1501,8 +1503,6 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h3D || dmi_write_dm_addr == 7'h3E || dmi_write_dm_addr == 7'h3F) ; - assign dm_system_bus$master_bvalid = master_bvalid ; - assign dm_system_bus$master_rvalid = master_rvalid ; // submodule f_read_addr assign f_read_addr$D_IN = dmi_read_addr_dm_addr ; @@ -1519,12 +1519,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h756 = $stime; + v__h772 = $stime; #0; end - v__h750 = v__h756 / 32'd10; + v__h766 = v__h772 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h750); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h766); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v index 7eeadfd..6a74a77 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:00 BST 2020 +// On Wed Jun 24 20:34:13 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v index eadd60c..911dc8a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:03 BST 2020 +// On Wed Jun 24 20:33:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v index 8dbe0fd..fe9629b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:43 BST 2020 +// On Wed Jun 24 20:32:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v index e75c361..bf9e380 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:49 BST 2020 +// On Wed Jun 24 20:32:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v index 6623d05..072da97 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:46 BST 2020 +// On Wed Jun 24 20:32:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v index eb75e18..8fd546d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:36:08 BST 2020 +// On Wed Jun 24 20:25:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v index 7621648..f45cb51 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:57 BST 2020 +// On Wed Jun 24 20:24:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v index 810ddac..0df28b8 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:14 BST 2020 +// On Wed Jun 24 20:34:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v index 394b4a6..4f7d456 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:51 BST 2020 +// On Wed Jun 24 20:33:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v index b40422c..81af6ae 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:04 BST 2020 +// On Wed Jun 24 20:33:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v index 56ad13d..b6b52a9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:05 BST 2020 +// On Wed Jun 24 20:33:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v index c73200c..0180a73 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:57 BST 2020 +// On Wed Jun 24 20:34:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v index 3c08a5c..d03e3b6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:57 BST 2020 +// On Wed Jun 24 20:34:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v index a6c8b6d..5111af7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v index 618d926..3fdb02d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v index 7fc1eae..16ccbdb 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:20 BST 2020 +// On Wed Jun 24 20:31:29 BST 2020 // // // Ports: @@ -585,7 +585,7 @@ module mkIBankWrapper(CLK, SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425, addr__h42425; reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31, x__h45568; reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38, @@ -616,7 +616,7 @@ module mkIBankWrapper(CLK, IF_m_pipeline_first__47_BITS_518_TO_516_52_EQ__ETC___d595; wire [5 : 0] IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d600, SEL_ARR_m_rqToPQ_data_0_84_BITS_5_TO_4_94_m_rq_ETC___d806; - wire [3 : 0] sel__h51069; + wire [3 : 0] sel__h51068; wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d615, SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461, SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d739, @@ -1055,7 +1055,7 @@ module mkIBankWrapper(CLK, WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[575] ; assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 = { 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, 1'd1, CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ; assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 = @@ -1714,7 +1714,7 @@ module mkIBankWrapper(CLK, assign resp_addr__h45726 = { m_cRqMshr$sendRsToP_cRq_getSlot[53:1], m_cRqMshr$sendRsToP_cRq_getRq[10:0] } ; - assign sel__h51069 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; + assign sel__h51068 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; assign v__h10212 = IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ? v__h10363 : @@ -2150,56 +2150,56 @@ module mkIBankWrapper(CLK, m_fromPQ_data_1[586]; endcase end - always@(sel__h51069 or m_pipeline$first) + always@(sel__h51068 or m_pipeline$first) begin - case (sel__h51069) + case (sel__h51068) 4'd0: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[31:0]; 4'd1: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[63:32]; 4'd2: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[95:64]; 4'd3: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[127:96]; 4'd4: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[159:128]; 4'd5: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[191:160]; 4'd6: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[223:192]; 4'd7: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[255:224]; 4'd8: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[287:256]; 4'd9: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[319:288]; 4'd10: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[351:320]; 4'd11: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[383:352]; 4'd12: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[415:384]; 4'd13: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[447:416]; 4'd14: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[479:448]; 4'd15: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[511:480]; endcase end diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v index 8f8a8f1..3415259 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:14 BST 2020 +// On Wed Jun 24 20:31:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v index 1291863..ba24afa 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:20 BST 2020 +// On Wed Jun 24 20:31:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v index b90ae70..5f3183a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:15 BST 2020 +// On Wed Jun 24 20:31:24 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v index 3fd92c5..2ce4a9c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:17 BST 2020 +// On Wed Jun 24 20:31:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v index a23f2b3..4fb2738 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:55 BST 2020 +// On Wed Jun 24 20:24:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v index 2edf342..45ffba2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:28 BST 2020 +// On Wed Jun 24 20:23:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v index 0eba9aa..9d8d163 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:41:46 BST 2020 +// On Wed Jun 24 20:30:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v index d1a386c..77af758 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:36 BST 2020 +// On Wed Jun 24 20:32:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v index 27be9d4..45331a0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:23 BST 2020 +// On Wed Jun 24 20:32:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v index aa267b2..5951f84 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:14 BST 2020 +// On Wed Jun 24 20:29:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v index 79241f5..defd5a8 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:15 BST 2020 +// On Wed Jun 24 20:32:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v index e494fc6..f8addaf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:45 BST 2020 +// On Wed Jun 24 20:24:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v index 8557c30..c5b2dc5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:34 BST 2020 +// On Wed Jun 24 20:31:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v index f1b13c4..47e788a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:51 BST 2020 +// On Wed Jun 24 20:32:01 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v index 3cc03bd..468f746 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:34 BST 2020 +// On Wed Jun 24 20:31:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v index 10cdea1..e713911 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:51 BST 2020 +// On Wed Jun 24 20:33:01 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v index e61cdd6..6b1d524 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:03 BST 2020 +// On Wed Jun 24 20:33:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v index 874419a..50c0aff 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:39 BST 2020 +// On Wed Jun 24 20:24:39 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index de0c878..ceae4bd 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:47:39 BST 2020 +// On Wed Jun 24 20:36:59 BST 2020 // // // Ports: @@ -69,18 +69,22 @@ // RST_N I 1 reset // master0_awready I 1 // master0_wready I 1 +// master0_bvalid I 1 // master0_bid I 6 // master0_bresp I 2 // master0_arready I 1 +// master0_rvalid I 1 // master0_rid I 6 // master0_rdata I 64 // master0_rresp I 2 // master0_rlast I 1 // master1_awready I 1 // master1_wready I 1 +// master1_bvalid I 1 // master1_bid I 6 reg // master1_bresp I 2 reg // master1_arready I 1 +// master1_rvalid I 1 // master1_rid I 6 reg // master1_rdata I 64 reg // master1_rresp I 2 reg @@ -90,10 +94,6 @@ // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 -// master0_bvalid I 1 -// master0_rvalid I 1 -// master1_bvalid I 1 -// master1_rvalid I 1 // // No combinational paths from inputs to outputs // @@ -149,9 +149,9 @@ module mkP3_Core(CLK, master0_wready, + master0_bvalid, master0_bid, master0_bresp, - master0_bvalid, master0_bready, @@ -179,11 +179,11 @@ module mkP3_Core(CLK, master0_arready, + master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, - master0_rvalid, master0_rready, @@ -221,9 +221,9 @@ module mkP3_Core(CLK, master1_wready, + master1_bvalid, master1_bid, master1_bresp, - master1_bvalid, master1_bready, @@ -251,11 +251,11 @@ module mkP3_Core(CLK, master1_arready, + master1_rvalid, master1_rid, master1_rdata, master1_rresp, master1_rlast, - master1_rvalid, master1_rready, @@ -332,9 +332,9 @@ module mkP3_Core(CLK, input master0_wready; // action method master0_b_bflit + input master0_bvalid; input [5 : 0] master0_bid; input [1 : 0] master0_bresp; - input master0_bvalid; // value method master0_b_bready output master0_bready; @@ -378,11 +378,11 @@ module mkP3_Core(CLK, input master0_arready; // action method master0_r_rflit + input master0_rvalid; input [5 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; - input master0_rvalid; // value method master0_r_rready output master0_rready; @@ -443,9 +443,9 @@ module mkP3_Core(CLK, input master1_wready; // action method master1_b_bflit + input master1_bvalid; input [5 : 0] master1_bid; input [1 : 0] master1_bresp; - input master1_bvalid; // value method master1_b_bready output master1_bready; @@ -489,11 +489,11 @@ module mkP3_Core(CLK, input master1_arready; // action method master1_r_rflit + input master1_rvalid; input [5 : 0] master1_rid; input [63 : 0] master1_rdata; input [1 : 0] master1_rresp; input master1_rlast; - input master1_rvalid; // value method master1_r_rready output master1_rready; @@ -854,10 +854,10 @@ module mkP3_Core(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1321; - reg [31 : 0] v__h1469; - reg [31 : 0] v__h1315; - reg [31 : 0] v__h1463; + reg [31 : 0] v__h1353; + reg [31 : 0] v__h1501; + reg [31 : 0] v__h1347; + reg [31 : 0] v__h1495; // synopsys translate_on // remaining internal signals @@ -925,7 +925,7 @@ module mkP3_Core(CLK, // action method master0_b_bflit assign CAN_FIRE_master0_b_bflit = 1'd1 ; - assign WILL_FIRE_master0_b_bflit = master0_bvalid ; + assign WILL_FIRE_master0_b_bflit = 1'd1 ; // value method master0_b_bready assign master0_bready = corew$cpu_imem_master_bready ; @@ -969,7 +969,7 @@ module mkP3_Core(CLK, // action method master0_r_rflit assign CAN_FIRE_master0_r_rflit = 1'd1 ; - assign WILL_FIRE_master0_r_rflit = master0_rvalid ; + assign WILL_FIRE_master0_r_rflit = 1'd1 ; // value method master0_r_rready assign master0_rready = corew$cpu_imem_master_rready ; @@ -1029,7 +1029,7 @@ module mkP3_Core(CLK, // action method master1_b_bflit assign CAN_FIRE_master1_b_bflit = 1'd1 ; - assign WILL_FIRE_master1_b_bflit = master1_bvalid ; + assign WILL_FIRE_master1_b_bflit = 1'd1 ; // value method master1_b_bready assign master1_bready = corew$cpu_dmem_master_bready ; @@ -1073,7 +1073,7 @@ module mkP3_Core(CLK, // action method master1_r_rflit assign CAN_FIRE_master1_r_rflit = 1'd1 ; - assign WILL_FIRE_master1_r_rflit = master1_rvalid ; + assign WILL_FIRE_master1_r_rflit = 1'd1 ; // value method master1_r_rready assign master1_rready = corew$cpu_dmem_master_rready ; @@ -1136,19 +1136,23 @@ module mkP3_Core(CLK, .cpu_dmem_master_awready(corew$cpu_dmem_master_awready), .cpu_dmem_master_bid(corew$cpu_dmem_master_bid), .cpu_dmem_master_bresp(corew$cpu_dmem_master_bresp), + .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), .cpu_dmem_master_rdata(corew$cpu_dmem_master_rdata), .cpu_dmem_master_rid(corew$cpu_dmem_master_rid), .cpu_dmem_master_rlast(corew$cpu_dmem_master_rlast), .cpu_dmem_master_rresp(corew$cpu_dmem_master_rresp), + .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), .cpu_dmem_master_wready(corew$cpu_dmem_master_wready), .cpu_imem_master_arready(corew$cpu_imem_master_arready), .cpu_imem_master_awready(corew$cpu_imem_master_awready), .cpu_imem_master_bid(corew$cpu_imem_master_bid), .cpu_imem_master_bresp(corew$cpu_imem_master_bresp), + .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), .cpu_imem_master_rdata(corew$cpu_imem_master_rdata), .cpu_imem_master_rid(corew$cpu_imem_master_rid), .cpu_imem_master_rlast(corew$cpu_imem_master_rlast), .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), + .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), .dmi_read_addr_dm_addr(corew$dmi_read_addr_dm_addr), .dmi_write_dm_addr(corew$dmi_write_dm_addr), @@ -1162,10 +1166,6 @@ module mkP3_Core(CLK, .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), .EN_start(corew$EN_start), - .cpu_imem_master_bvalid(corew$cpu_imem_master_bvalid), - .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), - .cpu_dmem_master_bvalid(corew$cpu_dmem_master_bvalid), - .cpu_dmem_master_rvalid(corew$cpu_dmem_master_rvalid), .EN_dmi_read_addr(corew$EN_dmi_read_addr), .EN_dmi_read_data(corew$EN_dmi_read_data), .EN_dmi_write(corew$EN_dmi_write), @@ -1554,19 +1554,23 @@ module mkP3_Core(CLK, assign corew$cpu_dmem_master_awready = master1_awready ; assign corew$cpu_dmem_master_bid = master1_bid ; assign corew$cpu_dmem_master_bresp = master1_bresp ; + assign corew$cpu_dmem_master_bvalid = master1_bvalid ; assign corew$cpu_dmem_master_rdata = master1_rdata ; assign corew$cpu_dmem_master_rid = master1_rid ; assign corew$cpu_dmem_master_rlast = master1_rlast ; assign corew$cpu_dmem_master_rresp = master1_rresp ; + assign corew$cpu_dmem_master_rvalid = master1_rvalid ; assign corew$cpu_dmem_master_wready = master1_wready ; assign corew$cpu_imem_master_arready = master0_arready ; assign corew$cpu_imem_master_awready = master0_awready ; assign corew$cpu_imem_master_bid = master0_bid ; assign corew$cpu_imem_master_bresp = master0_bresp ; + assign corew$cpu_imem_master_bvalid = master0_bvalid ; assign corew$cpu_imem_master_rdata = master0_rdata ; assign corew$cpu_imem_master_rid = master0_rid ; assign corew$cpu_imem_master_rlast = master0_rlast ; assign corew$cpu_imem_master_rresp = master0_rresp ; + assign corew$cpu_imem_master_rvalid = master0_rvalid ; assign corew$cpu_imem_master_wready = master0_wready ; assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; @@ -1582,10 +1586,6 @@ module mkP3_Core(CLK, assign corew$EN_start = WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || WILL_FIRE_RL_rl_step_0 && rg_corew_start_after_por == 8'd1 ; - assign corew$cpu_imem_master_bvalid = master0_bvalid ; - assign corew$cpu_imem_master_rvalid = master0_rvalid ; - assign corew$cpu_dmem_master_bvalid = master1_bvalid ; - assign corew$cpu_dmem_master_rvalid = master1_rvalid ; assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; @@ -1682,31 +1682,31 @@ module mkP3_Core(CLK, if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset) begin - v__h1321 = $stime; + v__h1353 = $stime; #0; end - v__h1315 = v__h1321 / 32'd10; + v__h1347 = v__h1353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset) $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - v__h1315, + v__h1347, $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) begin - v__h1469 = $stime; + v__h1501 = $stime; #0; end - v__h1463 = v__h1469 / 32'd10; + v__h1495 = v__h1501 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) if (por_ifc$RST_N_gen_rst != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - v__h1463); + v__h1495); end // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v index 9299a7a..c0fd0bf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:09 BST 2020 +// On Wed Jun 24 20:24:08 BST 2020 // // // Ports: @@ -30,6 +30,7 @@ // set_verbosity_verbosity I 4 reg // set_addr_map_addr_base I 64 reg // set_addr_map_addr_lim I 64 reg +// axi4_slave_awvalid I 1 // axi4_slave_awid I 5 reg // axi4_slave_awaddr I 64 reg // axi4_slave_awlen I 8 reg @@ -40,11 +41,13 @@ // axi4_slave_awprot I 3 reg // axi4_slave_awqos I 4 reg // axi4_slave_awregion I 4 reg +// axi4_slave_wvalid I 1 // axi4_slave_wdata I 64 reg // axi4_slave_wstrb I 8 reg // axi4_slave_wlast I 1 reg // axi4_slave_wuser I 1 reg // axi4_slave_bready I 1 +// axi4_slave_arvalid I 1 // axi4_slave_arid I 5 reg // axi4_slave_araddr I 64 reg // axi4_slave_arlen I 8 reg @@ -77,9 +80,6 @@ // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_set_addr_map I 1 -// axi4_slave_awvalid I 1 -// axi4_slave_wvalid I 1 -// axi4_slave_arvalid I 1 // // No combinational paths from inputs to outputs // @@ -119,6 +119,7 @@ module mkPLIC_16_2_7(CLK, EN_set_addr_map, RDY_set_addr_map, + axi4_slave_awvalid, axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -129,15 +130,14 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion, - axi4_slave_awvalid, axi4_slave_awready, + axi4_slave_wvalid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, axi4_slave_wuser, - axi4_slave_wvalid, axi4_slave_wready, @@ -149,6 +149,7 @@ module mkPLIC_16_2_7(CLK, axi4_slave_bready, + axi4_slave_arvalid, axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -159,7 +160,6 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion, - axi4_slave_arvalid, axi4_slave_arready, @@ -239,6 +239,7 @@ module mkPLIC_16_2_7(CLK, output RDY_set_addr_map; // action method axi4_slave_aw_awflit + input axi4_slave_awvalid; input [4 : 0] axi4_slave_awid; input [63 : 0] axi4_slave_awaddr; input [7 : 0] axi4_slave_awlen; @@ -249,17 +250,16 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_awprot; input [3 : 0] axi4_slave_awqos; input [3 : 0] axi4_slave_awregion; - input axi4_slave_awvalid; // value method axi4_slave_aw_awready output axi4_slave_awready; // action method axi4_slave_w_wflit + input axi4_slave_wvalid; input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; input axi4_slave_wuser; - input axi4_slave_wvalid; // value method axi4_slave_w_wready output axi4_slave_wready; @@ -279,6 +279,7 @@ module mkPLIC_16_2_7(CLK, input axi4_slave_bready; // action method axi4_slave_ar_arflit + input axi4_slave_arvalid; input [4 : 0] axi4_slave_arid; input [63 : 0] axi4_slave_araddr; input [7 : 0] axi4_slave_arlen; @@ -289,7 +290,6 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_arprot; input [3 : 0] axi4_slave_arqos; input [3 : 0] axi4_slave_arregion; - input axi4_slave_arvalid; // value method axi4_slave_ar_arready output axi4_slave_arready; @@ -389,15 +389,15 @@ module mkPLIC_16_2_7(CLK, v_targets_1_m_eip; // inlined wires - wire [97 : 0] m_slave_xactor_ug_slave_u_ar_putWire$wget, - m_slave_xactor_ug_slave_u_aw_putWire$wget; - wire [73 : 0] m_slave_xactor_ug_slave_u_w_putWire$wget; - wire [72 : 0] m_slave_xactor_ug_slave_u_r_peekWire$wget; - wire m_slave_xactor_ug_slave_u_ar_putWire$whas, - m_slave_xactor_ug_slave_u_aw_putWire$whas, - m_slave_xactor_ug_slave_u_b_dropWire$whas, - m_slave_xactor_ug_slave_u_r_dropWire$whas, - m_slave_xactor_ug_slave_u_w_putWire$whas; + wire [97 : 0] m_slave_xactor_slvSynth_arSynth_snk_putWire$wget, + m_slave_xactor_slvSynth_awSynth_snk_putWire$wget; + wire [73 : 0] m_slave_xactor_slvSynth_wSynth_snk_putWire$wget; + wire [72 : 0] m_slave_xactor_slvSynth_rSynth_src_peekWire$wget; + wire m_slave_xactor_slvSynth_arSynth_snk_putWire$whas, + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas, + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas, + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas, + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas; // register m_cfg_verbosity reg [3 : 0] m_cfg_verbosity; @@ -854,18 +854,18 @@ module mkPLIC_16_2_7(CLK, CAN_FIRE_RL_m_rl_process_wr_req, CAN_FIRE_RL_m_rl_reset, CAN_FIRE_RL_m_slave_xactor_do_clear, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek, + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek, + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut, + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut, CAN_FIRE_axi4_slave_ar_arflit, CAN_FIRE_axi4_slave_aw_awflit, CAN_FIRE_axi4_slave_b_bready, @@ -896,18 +896,18 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_wr_req, WILL_FIRE_RL_m_rl_reset, WILL_FIRE_RL_m_slave_xactor_do_clear, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, - WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek, + WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek, + WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut, + WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut, WILL_FIRE_axi4_slave_ar_arflit, WILL_FIRE_axi4_slave_aw_awflit, WILL_FIRE_axi4_slave_b_bready, @@ -1061,142 +1061,142 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h77333; - reg [31 : 0] v__h77531; - reg [31 : 0] v__h77729; - reg [31 : 0] v__h77927; - reg [31 : 0] v__h78125; - reg [31 : 0] v__h78323; - reg [31 : 0] v__h78521; - reg [31 : 0] v__h78719; - reg [31 : 0] v__h78917; - reg [31 : 0] v__h79115; - reg [31 : 0] v__h79313; - reg [31 : 0] v__h79511; - reg [31 : 0] v__h79709; - reg [31 : 0] v__h79907; - reg [31 : 0] v__h80105; - reg [31 : 0] v__h80303; - reg [31 : 0] v__h7530; - reg [31 : 0] v__h28194; - reg [31 : 0] v__h28448; - reg [31 : 0] v__h29372; - reg [31 : 0] v__h29558; - reg [31 : 0] v__h68542; - reg [31 : 0] v__h68832; - reg [31 : 0] v__h69364; - reg [31 : 0] v__h69450; - reg [31 : 0] v__h69661; - reg [31 : 0] v__h69907; - reg [31 : 0] v__h14375; - reg [31 : 0] v__h14590; - reg [31 : 0] v__h14818; - reg [31 : 0] v__h15069; - reg [31 : 0] v__h19543; - reg [31 : 0] v__h25160; - reg [31 : 0] v__h27336; - reg [31 : 0] v__h25416; - reg [31 : 0] v__h27627; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h76288; - reg [31 : 0] v__h76398; - reg [31 : 0] v__h76511; - reg [31 : 0] v__h7524; - reg [31 : 0] v__h14369; - reg [31 : 0] v__h14584; - reg [31 : 0] v__h14812; - reg [31 : 0] v__h15063; - reg [31 : 0] v__h19537; - reg [31 : 0] v__h25154; - reg [31 : 0] v__h25410; - reg [31 : 0] v__h27330; - reg [31 : 0] v__h27621; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28188; - reg [31 : 0] v__h28442; - reg [31 : 0] v__h29366; - reg [31 : 0] v__h29552; - reg [31 : 0] v__h68536; - reg [31 : 0] v__h68826; - reg [31 : 0] v__h69358; - reg [31 : 0] v__h69444; - reg [31 : 0] v__h69655; - reg [31 : 0] v__h69901; - reg [31 : 0] v__h76282; - reg [31 : 0] v__h76392; - reg [31 : 0] v__h76505; - reg [31 : 0] v__h77327; - reg [31 : 0] v__h77525; - reg [31 : 0] v__h77723; - reg [31 : 0] v__h77921; - reg [31 : 0] v__h78119; - reg [31 : 0] v__h78317; - reg [31 : 0] v__h78515; - reg [31 : 0] v__h78713; - reg [31 : 0] v__h78911; - reg [31 : 0] v__h79109; - reg [31 : 0] v__h79307; - reg [31 : 0] v__h79505; - reg [31 : 0] v__h79703; - reg [31 : 0] v__h79901; - reg [31 : 0] v__h80099; - reg [31 : 0] v__h80297; + reg [31 : 0] v__h77354; + reg [31 : 0] v__h77552; + reg [31 : 0] v__h77750; + reg [31 : 0] v__h77948; + reg [31 : 0] v__h78146; + reg [31 : 0] v__h78344; + reg [31 : 0] v__h78542; + reg [31 : 0] v__h78740; + reg [31 : 0] v__h78938; + reg [31 : 0] v__h79136; + reg [31 : 0] v__h79334; + reg [31 : 0] v__h79532; + reg [31 : 0] v__h79730; + reg [31 : 0] v__h79928; + reg [31 : 0] v__h80126; + reg [31 : 0] v__h80324; + reg [31 : 0] v__h7589; + reg [31 : 0] v__h28253; + reg [31 : 0] v__h28507; + reg [31 : 0] v__h29431; + reg [31 : 0] v__h29617; + reg [31 : 0] v__h68601; + reg [31 : 0] v__h68891; + reg [31 : 0] v__h69423; + reg [31 : 0] v__h69509; + reg [31 : 0] v__h69720; + reg [31 : 0] v__h69966; + reg [31 : 0] v__h14434; + reg [31 : 0] v__h14649; + reg [31 : 0] v__h14877; + reg [31 : 0] v__h15128; + reg [31 : 0] v__h19602; + reg [31 : 0] v__h25219; + reg [31 : 0] v__h27395; + reg [31 : 0] v__h25475; + reg [31 : 0] v__h27686; + reg [31 : 0] v__h27924; + reg [31 : 0] v__h76347; + reg [31 : 0] v__h76457; + reg [31 : 0] v__h76570; + reg [31 : 0] v__h7583; + reg [31 : 0] v__h14428; + reg [31 : 0] v__h14643; + reg [31 : 0] v__h14871; + reg [31 : 0] v__h15122; + reg [31 : 0] v__h19596; + reg [31 : 0] v__h25213; + reg [31 : 0] v__h25469; + reg [31 : 0] v__h27389; + reg [31 : 0] v__h27680; + reg [31 : 0] v__h27918; + reg [31 : 0] v__h28247; + reg [31 : 0] v__h28501; + reg [31 : 0] v__h29425; + reg [31 : 0] v__h29611; + reg [31 : 0] v__h68595; + reg [31 : 0] v__h68885; + reg [31 : 0] v__h69417; + reg [31 : 0] v__h69503; + reg [31 : 0] v__h69714; + reg [31 : 0] v__h69960; + reg [31 : 0] v__h76341; + reg [31 : 0] v__h76451; + reg [31 : 0] v__h76564; + reg [31 : 0] v__h77348; + reg [31 : 0] v__h77546; + reg [31 : 0] v__h77744; + reg [31 : 0] v__h77942; + reg [31 : 0] v__h78140; + reg [31 : 0] v__h78338; + reg [31 : 0] v__h78536; + reg [31 : 0] v__h78734; + reg [31 : 0] v__h78932; + reg [31 : 0] v__h79130; + reg [31 : 0] v__h79328; + reg [31 : 0] v__h79526; + reg [31 : 0] v__h79724; + reg [31 : 0] v__h79922; + reg [31 : 0] v__h80120; + reg [31 : 0] v__h80318; // synopsys translate_on // remaining internal signals - reg [63 : 0] y_avValue_fst__h27509; - reg [4 : 0] x__h25371, x__h69004; - reg [2 : 0] x__h14848, x__h25190; - reg [1 : 0] CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49, - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50; - reg CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, + reg [63 : 0] y_avValue_fst__h27568; + reg [4 : 0] x__h25430, x__h69063; + reg [2 : 0] x__h14907, x__h25249; + reg [1 : 0] CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49, + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50; + reg CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029, SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164, SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168, @@ -1294,127 +1294,127 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581, SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586; - wire [63 : 0] addr_offset__h14540, - addr_offset__h28408, - rdata___1__h27806, - rdata__h27563, - v__h14777, - v__h15027, - v__h19501, - v__h25119, - v__h26816, - v__h26835, - x__h27766, - y_avValue_fst__h27455, - y_avValue_fst__h27476, - y_avValue_fst__h27488, - y_avValue_fst__h27504, - y_avValue_fst__h27520, - y_avValue_fst__h27525, - y_avValue_fst__h27536, - y_avValue_fst__h27541, - y_avValue_fst__h27555; - wire [31 : 0] v_ie__h19504, - v_ip__h15030, - wdata32__h28409, - x__h25030, - x__h68623; - wire [9 : 0] source_id__h17021, - source_id__h17128, - source_id__h17201, - source_id__h17274, - source_id__h17347, - source_id__h17420, - source_id__h17493, - source_id__h17566, - source_id__h17639, - source_id__h17712, - source_id__h17785, - source_id__h17858, - source_id__h17931, - source_id__h18004, - source_id__h18077, - source_id__h18150, - source_id__h18223, - source_id__h18296, - source_id__h18369, - source_id__h18442, - source_id__h18515, - source_id__h18588, - source_id__h18661, - source_id__h18734, - source_id__h18807, - source_id__h18880, - source_id__h18953, - source_id__h19026, - source_id__h19099, - source_id__h19172, - source_id__h19245, - source_id__h21494, - source_id__h21670, - source_id__h21778, - source_id__h21886, - source_id__h21994, - source_id__h22102, - source_id__h22210, - source_id__h22318, - source_id__h22426, - source_id__h22534, - source_id__h22642, - source_id__h22750, - source_id__h22858, - source_id__h22966, - source_id__h23074, - source_id__h23182, - source_id__h23290, - source_id__h23398, - source_id__h23506, - source_id__h23614, - source_id__h23722, - source_id__h23830, - source_id__h23938, - source_id__h24046, - source_id__h24154, - source_id__h24262, - source_id__h24370, - source_id__h24478, - source_id__h24586, - source_id__h24694, - source_id__h24802, - source_id__h30987, - source_id__h32197, - source_id__h33407, - source_id__h34617, - source_id__h35827, - source_id__h37037, - source_id__h38247, - source_id__h39457, - source_id__h40667, - source_id__h41877, - source_id__h43087, - source_id__h44297, - source_id__h45507, - source_id__h46717, - source_id__h47927, - source_id__h49137, - source_id__h50347, - source_id__h51557, - source_id__h52767, - source_id__h53977, - source_id__h55187, - source_id__h56397, - source_id__h57607, - source_id__h58817, - source_id__h60027, - source_id__h61237, - source_id__h62447, - source_id__h63657, - source_id__h64867, - source_id__h66077, - source_id__h67287, - source_id__h68952, - source_id_base__h14985, - source_id_base__h29659; + wire [63 : 0] addr_offset__h14599, + addr_offset__h28467, + rdata___1__h27865, + rdata__h27622, + v__h14836, + v__h15086, + v__h19560, + v__h25178, + v__h26875, + v__h26894, + x__h27825, + y_avValue_fst__h27514, + y_avValue_fst__h27535, + y_avValue_fst__h27547, + y_avValue_fst__h27563, + y_avValue_fst__h27579, + y_avValue_fst__h27584, + y_avValue_fst__h27595, + y_avValue_fst__h27600, + y_avValue_fst__h27614; + wire [31 : 0] v_ie__h19563, + v_ip__h15089, + wdata32__h28468, + x__h25089, + x__h68682; + wire [9 : 0] source_id__h17080, + source_id__h17187, + source_id__h17260, + source_id__h17333, + source_id__h17406, + source_id__h17479, + source_id__h17552, + source_id__h17625, + source_id__h17698, + source_id__h17771, + source_id__h17844, + source_id__h17917, + source_id__h17990, + source_id__h18063, + source_id__h18136, + source_id__h18209, + source_id__h18282, + source_id__h18355, + source_id__h18428, + source_id__h18501, + source_id__h18574, + source_id__h18647, + source_id__h18720, + source_id__h18793, + source_id__h18866, + source_id__h18939, + source_id__h19012, + source_id__h19085, + source_id__h19158, + source_id__h19231, + source_id__h19304, + source_id__h21553, + source_id__h21729, + source_id__h21837, + source_id__h21945, + source_id__h22053, + source_id__h22161, + source_id__h22269, + source_id__h22377, + source_id__h22485, + source_id__h22593, + source_id__h22701, + source_id__h22809, + source_id__h22917, + source_id__h23025, + source_id__h23133, + source_id__h23241, + source_id__h23349, + source_id__h23457, + source_id__h23565, + source_id__h23673, + source_id__h23781, + source_id__h23889, + source_id__h23997, + source_id__h24105, + source_id__h24213, + source_id__h24321, + source_id__h24429, + source_id__h24537, + source_id__h24645, + source_id__h24753, + source_id__h24861, + source_id__h31046, + source_id__h32256, + source_id__h33466, + source_id__h34676, + source_id__h35886, + source_id__h37096, + source_id__h38306, + source_id__h39516, + source_id__h40726, + source_id__h41936, + source_id__h43146, + source_id__h44356, + source_id__h45566, + source_id__h46776, + source_id__h47986, + source_id__h49196, + source_id__h50406, + source_id__h51616, + source_id__h52826, + source_id__h54036, + source_id__h55246, + source_id__h56456, + source_id__h57666, + source_id__h58876, + source_id__h60086, + source_id__h61296, + source_id__h62506, + source_id__h63716, + source_id__h64926, + source_id__h66136, + source_id__h67346, + source_id__h69011, + source_id_base__h15044, + source_id_base__h29718; wire [4 : 0] IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d3227, IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d3321, IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d733, @@ -1436,9 +1436,9 @@ module mkPLIC_16_2_7(CLK, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3225, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3319, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d731, - b__h72911, - b__h74916, - max_id__h25318; + b__h72970, + b__h74975, + max_id__h25377; wire [2 : 0] IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d3186, IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d3280, IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d681, @@ -1483,8 +1483,8 @@ module mkPLIC_16_2_7(CLK, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3181, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d3275, IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d674, - a__h72910, - a__h74915; + a__h72969, + a__h74974; wire [1 : 0] IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d875, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d876, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877, @@ -1546,22 +1546,22 @@ module mkPLIC_16_2_7(CLK, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086, NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962, - NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439, - NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447, - NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455, - NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463, - NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471, - NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479, - NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487, - NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368, - NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375, - NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383, - NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391, - NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399, - NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407, - NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415, - NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423, - NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431, + NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442, + NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450, + NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458, + NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466, + NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474, + NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482, + NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490, + NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371, + NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378, + NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386, + NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394, + NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402, + NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410, + NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418, + NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426, + NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434, _dfoo1, _dfoo10, _dfoo100, @@ -3242,14 +3242,14 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_aw_awflit assign CAN_FIRE_axi4_slave_aw_awflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_aw_awflit = axi4_slave_awvalid ; + assign WILL_FIRE_axi4_slave_aw_awflit = 1'd1 ; // value method axi4_slave_aw_awready assign axi4_slave_awready = m_slave_xactor_shim_awff$FULL_N ; // action method axi4_slave_w_wflit assign CAN_FIRE_axi4_slave_w_wflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_w_wflit = axi4_slave_wvalid ; + assign WILL_FIRE_axi4_slave_w_wflit = 1'd1 ; // value method axi4_slave_w_wready assign axi4_slave_wready = m_slave_xactor_shim_wff$FULL_N ; @@ -3269,25 +3269,30 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_ar_arflit assign CAN_FIRE_axi4_slave_ar_arflit = 1'd1 ; - assign WILL_FIRE_axi4_slave_ar_arflit = axi4_slave_arvalid ; + assign WILL_FIRE_axi4_slave_ar_arflit = 1'd1 ; // value method axi4_slave_ar_arready assign axi4_slave_arready = m_slave_xactor_shim_arff$FULL_N ; // value method axi4_slave_r_rid - assign axi4_slave_rid = m_slave_xactor_ug_slave_u_r_peekWire$wget[72:68] ; + assign axi4_slave_rid = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[72:68] ; // value method axi4_slave_r_rdata - assign axi4_slave_rdata = m_slave_xactor_ug_slave_u_r_peekWire$wget[67:4] ; + assign axi4_slave_rdata = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[67:4] ; // value method axi4_slave_r_rresp - assign axi4_slave_rresp = m_slave_xactor_ug_slave_u_r_peekWire$wget[3:2] ; + assign axi4_slave_rresp = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[3:2] ; // value method axi4_slave_r_rlast - assign axi4_slave_rlast = m_slave_xactor_ug_slave_u_r_peekWire$wget[1] ; + assign axi4_slave_rlast = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[1] ; // value method axi4_slave_r_ruser - assign axi4_slave_ruser = m_slave_xactor_ug_slave_u_r_peekWire$wget[0] ; + assign axi4_slave_ruser = + m_slave_xactor_slvSynth_rSynth_src_peekWire$wget[0] ; // value method axi4_slave_r_rvalid assign axi4_slave_rvalid = m_slave_xactor_shim_rff$EMPTY_N ; @@ -3361,10 +3366,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h72910 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h72969 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h74915 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h74974 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3460,39 +3465,39 @@ module mkPLIC_16_2_7(CLK, m_f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - // rule RL_m_slave_xactor_ug_slave_u_aw_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = - m_slave_xactor_ug_slave_u_aw_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas && !m_slave_xactor_shim_awff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_w_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = - m_slave_xactor_ug_slave_u_w_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas && !m_slave_xactor_shim_wff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_b_setPeek - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + // rule RL_m_slave_xactor_slvSynth_bSynth_src_setPeek + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek = m_slave_xactor_shim_bff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_setPeek = m_slave_xactor_shim_bff$EMPTY_N ; - // rule RL_m_slave_xactor_ug_slave_u_b_warnDoDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = - m_slave_xactor_ug_slave_u_b_dropWire$whas && + // rule RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas && !m_slave_xactor_shim_bff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop ; - // rule RL_m_slave_xactor_ug_slave_u_b_doDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = + // rule RL_m_slave_xactor_slvSynth_bSynth_src_doDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop = m_slave_xactor_shim_bff$EMPTY_N && - m_slave_xactor_ug_slave_u_b_dropWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + m_slave_xactor_slvSynth_bSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop ; // rule RL_m_rl_process_wr_req assign CAN_FIRE_RL_m_rl_process_wr_req = @@ -3504,46 +3509,46 @@ module mkPLIC_16_2_7(CLK, CAN_FIRE_RL_m_rl_process_wr_req && !WILL_FIRE_RL_m_rl_process_rd_req ; - // rule RL_m_slave_xactor_ug_slave_u_aw_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = + // rule RL_m_slave_xactor_slvSynth_awSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut = m_slave_xactor_shim_awff$FULL_N && - m_slave_xactor_ug_slave_u_aw_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + m_slave_xactor_slvSynth_awSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut ; - // rule RL_m_slave_xactor_ug_slave_u_w_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = + // rule RL_m_slave_xactor_slvSynth_wSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut = m_slave_xactor_shim_wff$FULL_N && - m_slave_xactor_ug_slave_u_w_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + m_slave_xactor_slvSynth_wSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut ; - // rule RL_m_slave_xactor_ug_slave_u_ar_warnDoPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = - m_slave_xactor_ug_slave_u_ar_putWire$whas && + // rule RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + m_slave_xactor_slvSynth_arSynth_snk_putWire$whas && !m_slave_xactor_shim_arff$FULL_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut ; - // rule RL_m_slave_xactor_ug_slave_u_r_setPeek - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + // rule RL_m_slave_xactor_slvSynth_rSynth_src_setPeek + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek = m_slave_xactor_shim_rff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_setPeek = m_slave_xactor_shim_rff$EMPTY_N ; - // rule RL_m_slave_xactor_ug_slave_u_r_warnDoDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = - m_slave_xactor_ug_slave_u_r_dropWire$whas && + // rule RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas && !m_slave_xactor_shim_rff$EMPTY_N ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop ; - // rule RL_m_slave_xactor_ug_slave_u_r_doDrop - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = + // rule RL_m_slave_xactor_slvSynth_rSynth_src_doDrop + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop = m_slave_xactor_shim_rff$EMPTY_N && - m_slave_xactor_ug_slave_u_r_dropWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + m_slave_xactor_slvSynth_rSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop = + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop ; // rule RL_m_rl_process_rd_req assign CAN_FIRE_RL_m_rl_process_rd_req = @@ -3552,12 +3557,12 @@ module mkPLIC_16_2_7(CLK, !m_f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - // rule RL_m_slave_xactor_ug_slave_u_ar_doPut - assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = + // rule RL_m_slave_xactor_slvSynth_arSynth_snk_doPut + assign CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut = m_slave_xactor_shim_arff$FULL_N && - m_slave_xactor_ug_slave_u_ar_putWire$whas ; - assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + m_slave_xactor_slvSynth_arSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut = + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut ; // rule RL_m_slave_xactor_do_clear assign CAN_FIRE_RL_m_slave_xactor_do_clear = m_slave_xactor_clearing ; @@ -3566,139 +3571,139 @@ module mkPLIC_16_2_7(CLK, // inputs to muxes for submodule ports assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd0 && + addr_offset__h14599[16:12] == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd1 && + addr_offset__h14599[16:12] == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd0 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd1 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd10 && + source_id__h69011 == 10'd10 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd11 && + source_id__h69011 == 10'd11 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd12 && + source_id__h69011 == 10'd12 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd13 && + source_id__h69011 == 10'd13 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd14 && + source_id__h69011 == 10'd14 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd15 && + source_id__h69011 == 10'd15 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd16 && + source_id__h69011 == 10'd16 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd2 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd2 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd3 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd3 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd4 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd4 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd5 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd5 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd6 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd6 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd7 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd7 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd8 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd8 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd9 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd9 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[11:2] == 10'd0 && + addr_offset__h28467[11:2] == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && @@ -3823,178 +3828,178 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h29659 == 10'd0 && + (source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h29659 == 10'd1 && + (source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h29659 == 10'd10 && + (source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h29659 == 10'd11 && + (source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h29659 == 10'd12 && + (source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h29659 == 10'd13 && + (source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h29659 == 10'd14 && + (source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h29659 == 10'd15 && + (source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h29659 == 10'd16 && + (source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h29659 == 10'd2 && + (source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h29659 == 10'd3 && + (source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h29659 == 10'd4 && + (source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h29659 == 10'd5 && + (source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h29659 == 10'd6 && + (source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h29659 == 10'd7 && + (source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h29659 == 10'd8 && + (source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h29659 == 10'd9 && + (source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h29659 == 10'd0 && + (source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h29659 == 10'd1 && + (source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h29659 == 10'd10 && + (source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h29659 == 10'd11 && + (source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h29659 == 10'd12 && + (source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h29659 == 10'd13 && + (source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h29659 == 10'd14 && + (source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h29659 == 10'd15 && + (source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h29659 == 10'd16 && + (source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h29659 == 10'd2 && + (source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h29659 == 10'd3 && + (source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h29659 == 10'd4 && + (source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h29659 == 10'd5 && + (source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h29659 == 10'd6 && + (source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h29659 == 10'd7 && + (source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h29659 == 10'd8 && + (source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h29659 == 10'd9 && + (source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067) ? - wdata32__h28409[0] : + wdata32__h28468[0] : _dfoo1988 ; // inlined wires - assign m_slave_xactor_ug_slave_u_aw_putWire$wget = + assign m_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -4005,16 +4010,16 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion } ; - assign m_slave_xactor_ug_slave_u_aw_putWire$whas = + assign m_slave_xactor_slvSynth_awSynth_snk_putWire$whas = axi4_slave_awvalid && m_slave_xactor_shim_awff$FULL_N ; - assign m_slave_xactor_ug_slave_u_w_putWire$wget = + assign m_slave_xactor_slvSynth_wSynth_snk_putWire$wget = { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, axi4_slave_wuser } ; - assign m_slave_xactor_ug_slave_u_w_putWire$whas = + assign m_slave_xactor_slvSynth_wSynth_snk_putWire$whas = axi4_slave_wvalid && m_slave_xactor_shim_wff$FULL_N ; - assign m_slave_xactor_ug_slave_u_ar_putWire$wget = + assign m_slave_xactor_slvSynth_arSynth_snk_putWire$wget = { axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -4025,13 +4030,13 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion } ; - assign m_slave_xactor_ug_slave_u_ar_putWire$whas = + assign m_slave_xactor_slvSynth_arSynth_snk_putWire$whas = axi4_slave_arvalid && m_slave_xactor_shim_arff$FULL_N ; - assign m_slave_xactor_ug_slave_u_r_peekWire$wget = + assign m_slave_xactor_slvSynth_rSynth_src_peekWire$wget = { m_slave_xactor_shim_rff$D_OUT, 1'd0 } ; - assign m_slave_xactor_ug_slave_u_b_dropWire$whas = + assign m_slave_xactor_slvSynth_bSynth_src_dropWire$whas = m_slave_xactor_shim_bff$EMPTY_N && axi4_slave_bready ; - assign m_slave_xactor_ug_slave_u_r_dropWire$whas = + assign m_slave_xactor_slvSynth_rSynth_src_dropWire$whas = m_slave_xactor_shim_rff$EMPTY_N && axi4_slave_rready ; // register m_cfg_verbosity @@ -4054,30 +4059,30 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_servicing_source_0 assign m_vrg_servicing_source_0$D_IN = MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h25318 : + max_id__h25377 : 5'd0 ; assign m_vrg_servicing_source_0$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd0 && + addr_offset__h14599[16:12] == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[16:12] == 5'd0 && + addr_offset__h28467[16:12] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 assign m_vrg_servicing_source_1$D_IN = MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h25318 : + max_id__h25377 : 5'd0 ; assign m_vrg_servicing_source_1$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h14540[16:12] == 5'd1 && + addr_offset__h14599[16:12] == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[16:12] == 5'd1 && + addr_offset__h28467[16:12] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4086,10 +4091,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_0$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd0 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd0 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4098,10 +4103,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_1$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd1 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4110,11 +4115,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_10$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd10 && + source_id__h69011 == 10'd10 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4123,11 +4128,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_11$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd11 && + source_id__h69011 == 10'd11 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4136,11 +4141,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_12$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd12 && + source_id__h69011 == 10'd12 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4149,11 +4154,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_13$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd13 && + source_id__h69011 == 10'd13 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4162,11 +4167,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_14$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd14 && + source_id__h69011 == 10'd14 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4175,11 +4180,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_15$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd15 && + source_id__h69011 == 10'd15 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4188,11 +4193,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_16$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h68952 == 10'd16 && + source_id__h69011 == 10'd16 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4201,10 +4206,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_2$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd2 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd2 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4213,10 +4218,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_3$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd3 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd3 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4225,10 +4230,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_4$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd4 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd4 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4237,10 +4242,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_5$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd5 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd5 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4249,10 +4254,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_6$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd6 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd6 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4261,10 +4266,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_7$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd7 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd7 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4273,10 +4278,10 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_8$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd8 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd8 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; @@ -4285,17 +4290,17 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_9$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h68952 == 10'd9 && + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h69011 == 10'd9 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 assign m_vrg_source_ip_0$D_IN = 1'd0 ; assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd0 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd0 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4307,7 +4312,7 @@ module mkPLIC_16_2_7(CLK, v_sources_0_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_1$EN = !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd1 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd1 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4319,7 +4324,7 @@ module mkPLIC_16_2_7(CLK, v_sources_9_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_10$EN = !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd10 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd10 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4331,7 +4336,7 @@ module mkPLIC_16_2_7(CLK, v_sources_10_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_11$EN = !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd11 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd11 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4343,7 +4348,7 @@ module mkPLIC_16_2_7(CLK, v_sources_11_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_12$EN = !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd12 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd12 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4355,7 +4360,7 @@ module mkPLIC_16_2_7(CLK, v_sources_12_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_13$EN = !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd13 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd13 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4367,7 +4372,7 @@ module mkPLIC_16_2_7(CLK, v_sources_13_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_14$EN = !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd14 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd14 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4379,7 +4384,7 @@ module mkPLIC_16_2_7(CLK, v_sources_14_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_15$EN = !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd15 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd15 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4391,7 +4396,7 @@ module mkPLIC_16_2_7(CLK, v_sources_15_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_16$EN = !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd16 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd16 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4403,7 +4408,7 @@ module mkPLIC_16_2_7(CLK, v_sources_1_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_2$EN = !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd2 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd2 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4415,7 +4420,7 @@ module mkPLIC_16_2_7(CLK, v_sources_2_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_3$EN = !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd3 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd3 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4427,7 +4432,7 @@ module mkPLIC_16_2_7(CLK, v_sources_3_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_4$EN = !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd4 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd4 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4439,7 +4444,7 @@ module mkPLIC_16_2_7(CLK, v_sources_4_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_5$EN = !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd5 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd5 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4451,7 +4456,7 @@ module mkPLIC_16_2_7(CLK, v_sources_5_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_6$EN = !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd6 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd6 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4463,7 +4468,7 @@ module mkPLIC_16_2_7(CLK, v_sources_6_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_7$EN = !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd7 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd7 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4475,7 +4480,7 @@ module mkPLIC_16_2_7(CLK, v_sources_7_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_8$EN = !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd8 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd8 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4487,7 +4492,7 @@ module mkPLIC_16_2_7(CLK, v_sources_8_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_9$EN = !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25318 == 5'd9 && + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h25377 == 5'd9 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 || WILL_FIRE_RL_m_rl_reset ; @@ -4495,18 +4500,18 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h28408[11:2] == 10'd0 && + addr_offset__h28467[11:2] == 10'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4516,7 +4521,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4526,7 +4531,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4536,7 +4541,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4546,7 +4551,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4556,7 +4561,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4566,7 +4571,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4576,7 +4581,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4586,7 +4591,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4596,7 +4601,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4606,7 +4611,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4616,7 +4621,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4626,7 +4631,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4636,7 +4641,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4646,7 +4651,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4656,7 +4661,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4666,7 +4671,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4676,7 +4681,7 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h28409[2:0] : + wdata32__h28468[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && @@ -4967,17 +4972,17 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_shim_arff assign m_slave_xactor_shim_arff$D_IN = - m_slave_xactor_ug_slave_u_ar_putWire$wget ; + m_slave_xactor_slvSynth_arSynth_snk_putWire$wget ; assign m_slave_xactor_shim_arff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_doPut ; assign m_slave_xactor_shim_arff$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; assign m_slave_xactor_shim_arff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_awff assign m_slave_xactor_shim_awff$D_IN = - m_slave_xactor_ug_slave_u_aw_putWire$wget ; + m_slave_xactor_slvSynth_awSynth_snk_putWire$wget ; assign m_slave_xactor_shim_awff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_doPut ; assign m_slave_xactor_shim_awff$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_awff$CLR = m_slave_xactor_clearing ; @@ -4989,27 +4994,27 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3123 } ; assign m_slave_xactor_shim_bff$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_bff$DEQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_doDrop ; assign m_slave_xactor_shim_bff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_rff assign m_slave_xactor_shim_rff$D_IN = { m_slave_xactor_shim_arff$D_OUT[97:93], - x__h27766, + x__h27825, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 ? 2'd3 : IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877, 1'd1 } ; assign m_slave_xactor_shim_rff$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; assign m_slave_xactor_shim_rff$DEQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_doDrop ; assign m_slave_xactor_shim_rff$CLR = m_slave_xactor_clearing ; // submodule m_slave_xactor_shim_wff assign m_slave_xactor_shim_wff$D_IN = - m_slave_xactor_ug_slave_u_w_putWire$wget[73:1] ; + m_slave_xactor_slvSynth_wSynth_snk_putWire$wget[73:1] ; assign m_slave_xactor_shim_wff$ENQ = - CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + CAN_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_doPut ; assign m_slave_xactor_shim_wff$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_shim_wff$CLR = m_slave_xactor_clearing ; @@ -5018,14 +5023,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 : - ((x__h25030 == 32'h00200000) ? + ((x__h25089 == 32'h00200000) ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 : - x__h25030 != 32'h00200004 || + x__h25089 != 32'h00200004 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 || - x__h25371 != 5'd0) ; + x__h25430 != 5'd0) ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - addr_offset__h14540[11:2] == 10'd0 || + addr_offset__h14599[11:2] == 10'd0 || !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 : (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 : @@ -5036,7 +5041,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308) ? 2'd0 : 2'd2) : - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 ; + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d876 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 ? @@ -5045,7 +5050,7 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d875 ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d877 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - ((addr_offset__h14540[11:2] != 10'd0 && + ((addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106) ? 2'd0 : 2'd2) : @@ -5054,14 +5059,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 : - ((x__h25030 == 32'h00200000) ? + ((x__h25089 == 32'h00200000) ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 : - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0) ; + x__h25430 == 5'd0) ; assign IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d888 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - addr_offset__h14540[11:2] != 10'd0 && + addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 : (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 ? m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 : @@ -5070,14 +5075,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 : - ((x__h68623 == 32'h00200000) ? + ((x__h68682 == 32'h00200000) ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 : - x__h68623 != 32'h00200004 || + x__h68682 != 32'h00200004 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 || !SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - addr_offset__h28408[11:2] == 10'd0 || + addr_offset__h28467[11:2] == 10'd0 || !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 : (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 : @@ -5088,7 +5093,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025) ? 2'd0 : 2'd2) : - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 ; + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3122 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 ? @@ -5097,7 +5102,7 @@ module mkPLIC_16_2_7(CLK, IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3121 ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3123 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - ((addr_offset__h28408[11:2] != 10'd0 && + ((addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959) ? 2'd0 : 2'd2) : @@ -5106,14 +5111,14 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 : - ((x__h68623 == 32'h00200000) ? + ((x__h68682 == 32'h00200000) ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 : - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) ; assign IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3131 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 ? - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 : (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 ? m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 : @@ -5449,23 +5454,23 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200000 && + x__h25089 == 32'h00200000 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d766 = !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0 && + x__h25430 == 5'd0 && m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810 = !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 == 5'd0 && + x__h25430 == 5'd0 && m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822 = @@ -5473,9 +5478,9 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 && - x__h25030 == 32'h00200004 && + x__h25089 == 32'h00200004 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 && - x__h25371 != 5'd0 ; + x__h25430 != 5'd0 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && @@ -5493,7 +5498,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h30987 <= 10'd16 ; + source_id__h31046 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5501,7 +5506,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h32197 <= 10'd16 ; + source_id__h32256 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5509,7 +5514,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h33407 <= 10'd16 ; + source_id__h33466 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5517,7 +5522,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h34617 <= 10'd16 ; + source_id__h34676 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5525,7 +5530,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h35827 <= 10'd16 ; + source_id__h35886 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5533,7 +5538,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h37037 <= 10'd16 ; + source_id__h37096 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5541,7 +5546,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h38247 <= 10'd16 ; + source_id__h38306 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5549,7 +5554,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h39457 <= 10'd16 ; + source_id__h39516 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5557,7 +5562,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h40667 <= 10'd16 ; + source_id__h40726 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5565,7 +5570,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h41877 <= 10'd16 ; + source_id__h41936 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5573,7 +5578,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h43087 <= 10'd16 ; + source_id__h43146 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5581,7 +5586,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h44297 <= 10'd16 ; + source_id__h44356 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5589,7 +5594,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h45507 <= 10'd16 ; + source_id__h45566 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5597,7 +5602,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h46717 <= 10'd16 ; + source_id__h46776 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5605,7 +5610,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h47927 <= 10'd16 ; + source_id__h47986 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5613,7 +5618,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h49137 <= 10'd16 ; + source_id__h49196 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5621,7 +5626,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h50347 <= 10'd16 ; + source_id__h50406 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5629,7 +5634,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h51557 <= 10'd16 ; + source_id__h51616 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5637,7 +5642,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h52767 <= 10'd16 ; + source_id__h52826 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5645,7 +5650,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h53977 <= 10'd16 ; + source_id__h54036 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5653,7 +5658,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h55187 <= 10'd16 ; + source_id__h55246 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5661,7 +5666,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h56397 <= 10'd16 ; + source_id__h56456 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5669,7 +5674,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h57607 <= 10'd16 ; + source_id__h57666 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5677,7 +5682,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h58817 <= 10'd16 ; + source_id__h58876 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5685,7 +5690,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h60027 <= 10'd16 ; + source_id__h60086 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5693,7 +5698,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h61237 <= 10'd16 ; + source_id__h61296 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5701,7 +5706,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h62447 <= 10'd16 ; + source_id__h62506 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5709,7 +5714,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h63657 <= 10'd16 ; + source_id__h63716 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5717,7 +5722,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h64867 <= 10'd16 ; + source_id__h64926 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5725,7 +5730,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h66077 <= 10'd16 ; + source_id__h66136 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5733,7 +5738,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 && - source_id__h67287 <= 10'd16 ; + source_id__h67346 <= 10'd16 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && @@ -5745,14 +5750,14 @@ module mkPLIC_16_2_7(CLK, assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200000 && + x__h68682 == 32'h00200000 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200000 && + x__h68682 == 32'h00200000 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && m_cfg_verbosity != 4'd0 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3035 = @@ -5760,14 +5765,14 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 && m_cfg_verbosity != 4'd0 ; @@ -5776,10631 +5781,10631 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 && - x__h68623 == 32'h00200004 && + x__h68682 == 32'h00200004 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 && !SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ; assign NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d962 = !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; - assign NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439 = + assign NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447 = + assign NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455 = + assign NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463 = + assign NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471 = + assign NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479 = + assign NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487 = + assign NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490 = !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_16 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368 = + assign NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375 = + assign NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383 = + assign NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391 = + assign NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399 = + assign NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407 = + assign NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415 = + assign NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423 = + assign NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431 = + assign NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo10 = - (source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo100 = - (source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo865 ; assign _dfoo1002 = - (source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo867 ; assign _dfoo1004 = - (source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo869 ; assign _dfoo1006 = - (source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo871 ; assign _dfoo1008 = - (source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo873 ; assign _dfoo1010 = - (source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo875 ; assign _dfoo1012 = - (source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo877 ; assign _dfoo1014 = - (source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo879 ; assign _dfoo1016 = - (source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo881 ; assign _dfoo1018 = - (source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo883 ; assign _dfoo102 = - (source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946) ? - wdata32__h28409[15] : + wdata32__h28468[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo953 ; assign _dfoo1090 = - (source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo955 ; assign _dfoo1092 = - (source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo957 ; assign _dfoo1094 = - (source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo959 ; assign _dfoo1096 = - (source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo961 ; assign _dfoo1098 = - (source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo963 ; assign _dfoo11 = - source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo110 = - (source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo965 ; assign _dfoo1102 = - (source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo967 ; assign _dfoo1104 = - (source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo969 ; assign _dfoo1106 = - (source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo971 ; assign _dfoo1108 = - (source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo973 ; assign _dfoo1110 = - (source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo975 ; assign _dfoo1112 = - (source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo977 ; assign _dfoo1114 = - (source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo979 ; assign _dfoo1116 = - (source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo981 ; assign _dfoo1118 = - (source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo983 ; assign _dfoo112 = - (source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo985 ; assign _dfoo1122 = - (source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo987 ; assign _dfoo1124 = - (source_id__h46717 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo989 ; assign _dfoo1126 = - (source_id__h46717 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo991 ; assign _dfoo1128 = - (source_id__h46717 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo993 ; assign _dfoo1130 = - (source_id__h46717 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo995 ; assign _dfoo1132 = - (source_id__h46717 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo997 ; assign _dfoo1134 = - (source_id__h46717 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo999 ; assign _dfoo1136 = - (source_id__h46717 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h46717 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1003 ; assign _dfoo114 = - (source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h46717 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h46717 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h46717 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h46717 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h46717 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h46717 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h46717 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h46717 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885 || - source_id__h47927 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h47986 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1946 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h46717 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h46776 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1885) ? - wdata32__h28409[14] : + wdata32__h28468[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo120 = - (source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824) ? - wdata32__h28409[13] : + wdata32__h28468[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1103 ; assign _dfoo124 = - (source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1123 ; assign _dfoo126 = - (source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h44297 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h44297 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h44297 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h44297 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h44297 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h44297 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h44297 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h44297 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h44297 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h44297 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1143 ; assign _dfoo128 = - (source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h44297 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h44297 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h44297 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h44297 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h44297 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h44297 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763 || - source_id__h45507 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h45566 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1824 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h44297 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h44356 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1763) ? - wdata32__h28409[12] : + wdata32__h28468[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo130 = - (source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702) ? - wdata32__h28409[11] : + wdata32__h28468[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1233 ; assign _dfoo137 = - source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo1 ; assign _dfoo1370 = - (source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1243 ; assign _dfoo138 = - (source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1253 ; assign _dfoo139 = - source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo3 ; assign _dfoo1390 = - (source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h41877 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h41877 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1263 ; assign _dfoo14 = - (source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo140 = - (source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h41877 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h41877 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h41877 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h41877 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h41877 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1273 ; assign _dfoo141 = - source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo5 ; assign _dfoo1410 = - (source_id__h41877 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h41877 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h41877 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h41877 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h41877 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1283 ; assign _dfoo142 = - (source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h41877 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h41877 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h41877 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h41877 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641 || - source_id__h43087 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h43146 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1702 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h41877 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h41936 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1641) ? - wdata32__h28409[10] : + wdata32__h28468[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo7 ; assign _dfoo1430 = - (source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo9 ; assign _dfoo1450 = - (source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo11 ; assign _dfoo1470 = - (source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo13 ; assign _dfoo1490 = - (source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580) ? - wdata32__h28409[9] : + wdata32__h28468[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1363 ; assign _dfoo15 = - source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo150 = - (source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1373 ; assign _dfoo151 = - source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo15 ; assign _dfoo1510 = - (source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1383 ; assign _dfoo152 = - (source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1393 ; assign _dfoo153 = - source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo17 ; assign _dfoo1530 = - (source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h39457 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h39457 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h39457 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h39457 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1403 ; assign _dfoo154 = - (source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h39457 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h39457 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h39457 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h39457 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h39457 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1413 ; assign _dfoo155 = - source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo19 ; assign _dfoo1550 = - (source_id__h39457 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h39457 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h39457 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h39457 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h39457 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1423 ; assign _dfoo156 = - (source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h39457 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h39457 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519 || - source_id__h40667 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h40726 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1580 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h39457 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h39516 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1519) ? - wdata32__h28409[8] : + wdata32__h28468[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo21 ; assign _dfoo1570 = - (source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo23 ; assign _dfoo1590 = - (source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo160 = - (source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo25 ; assign _dfoo1610 = - (source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo27 ; assign _dfoo1630 = - (source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458) ? - wdata32__h28409[7] : + wdata32__h28468[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1503 ; assign _dfoo164 = - (source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1513 ; assign _dfoo165 = - source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo29 ; assign _dfoo1650 = - (source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1523 ; assign _dfoo166 = - (source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h37037 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1533 ; assign _dfoo167 = - source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo31 ; assign _dfoo1670 = - (source_id__h37037 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h37037 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h37037 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h37037 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h37037 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1543 ; assign _dfoo168 = - (source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h37037 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h37037 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h37037 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h37037 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h37037 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1553 ; assign _dfoo169 = - source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo33 ; assign _dfoo1690 = - (source_id__h37037 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h37037 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h37037 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h37037 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h37037 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397 || - source_id__h38247 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h38306 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1458 || _dfoo1563 ; assign _dfoo17 = - source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo170 = - (source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h37037 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h37096 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1397) ? - wdata32__h28409[6] : + wdata32__h28468[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo35 ; assign _dfoo1710 = - (source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h63657 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo37 ; assign _dfoo1730 = - (source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h63657 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo39 ; assign _dfoo1750 = - (source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h63657 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336) ? - wdata32__h28409[5] : + wdata32__h28468[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1633 ; assign _dfoo177 = - source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo41 ; assign _dfoo1770 = - (source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1643 ; assign _dfoo178 = - (source_id__h63657 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1653 ; assign _dfoo179 = - source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo43 ; assign _dfoo1790 = - (source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1663 ; assign _dfoo18 = - (source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo180 = - (source_id__h63657 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h34617 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h34617 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h34617 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1673 ; assign _dfoo181 = - source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo45 ; assign _dfoo1810 = - (source_id__h34617 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h34617 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h34617 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h34617 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h34617 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1683 ; assign _dfoo182 = - (source_id__h63657 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h34617 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h34617 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h34617 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h34617 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h34617 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1693 ; assign _dfoo183 = - source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo47 ; assign _dfoo1830 = - (source_id__h34617 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h34617 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h34617 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275 || - source_id__h35827 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h35886 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1336 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h34617 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h34676 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1275) ? - wdata32__h28409[4] : + wdata32__h28468[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h63657 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo49 ; assign _dfoo1850 = - (source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h63657 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo51 ; assign _dfoo1870 = - (source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h63657 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo53 ; assign _dfoo1890 = - (source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo190 = - (source_id__h63657 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214) ? - wdata32__h28409[3] : + wdata32__h28468[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1773 ; assign _dfoo191 = - source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo55 ; assign _dfoo1910 = - (source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1783 ; assign _dfoo192 = - (source_id__h63657 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1793 ; assign _dfoo193 = - source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo57 ; assign _dfoo1930 = - (source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1803 ; assign _dfoo194 = - (source_id__h63657 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h32197 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h32197 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h32197 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h32197 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h32197 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1813 ; assign _dfoo195 = - source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo59 ; assign _dfoo1950 = - (source_id__h32197 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h32197 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h32197 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h32197 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h32197 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1823 ; assign _dfoo196 = - (source_id__h63657 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h32197 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h32197 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h32197 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h32197 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h32197 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1833 ; assign _dfoo197 = - source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo61 ; assign _dfoo1970 = - (source_id__h32197 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153 || - source_id__h33407 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h33466 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1214 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h32197 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h32256 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1153) ? - wdata32__h28409[2] : + wdata32__h28468[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h63657 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo63 ; assign _dfoo1990 = - (source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo20 = - (source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo200 = - (source_id__h63657 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo65 ; assign _dfoo2010 = - (source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h63657 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739 || - source_id__h64867 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h64926 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800 || _dfoo67 ; assign _dfoo2030 = - (source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h63657 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h63716 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2739) ? - wdata32__h28409[28] : + wdata32__h28468[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092) ? - wdata32__h28409[1] : + wdata32__h28468[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h29659 == 10'd16 && + source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h29659 == 10'd15 && + source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h29659 == 10'd14 && + source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h29659 == 10'd13 && + source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h29659 == 10'd12 && + source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h29659 == 10'd11 && + source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h29659 == 10'd10 && + source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h29659 == 10'd9 && + source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h29659 == 10'd8 && + source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h29659 == 10'd7 && + source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1923 ; assign _dfoo206 = - (source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h29659 == 10'd6 && + source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h29659 == 10'd5 && + source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h29659 == 10'd4 && + source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h29659 == 10'd3 && + source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h29659 == 10'd2 && + source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h29659 == 10'd1 && + source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h29659 == 10'd0 && + source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 || - source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h29659 == 10'd16 && + source_id_base__h29718 == 10'd16 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h29659 == 10'd15 && + source_id_base__h29718 == 10'd15 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h29659 == 10'd14 && + source_id_base__h29718 == 10'd14 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1943 ; assign _dfoo208 = - (source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h29659 == 10'd13 && + source_id_base__h29718 == 10'd13 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h29659 == 10'd12 && + source_id_base__h29718 == 10'd12 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h29659 == 10'd11 && + source_id_base__h29718 == 10'd11 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h29659 == 10'd10 && + source_id_base__h29718 == 10'd10 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h29659 == 10'd9 && + source_id_base__h29718 == 10'd9 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h29659 == 10'd8 && + source_id_base__h29718 == 10'd8 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h29659 == 10'd7 && + source_id_base__h29718 == 10'd7 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h29659 == 10'd6 && + source_id_base__h29718 == 10'd6 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h29659 == 10'd5 && + source_id_base__h29718 == 10'd5 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h29659 == 10'd4 && + source_id_base__h29718 == 10'd4 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1963 ; assign _dfoo21 = - source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo210 = - (source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h29659 == 10'd3 && + source_id_base__h29718 == 10'd3 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h29659 == 10'd2 && + source_id_base__h29718 == 10'd2 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h29659 == 10'd1 && + source_id_base__h29718 == 10'd1 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h29659 == 10'd0 && + source_id_base__h29718 == 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 || - source_id__h30987 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h31046 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1092 || _dfoo1971 ; assign _dfoo212 = - (source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo220 = - (source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo160 ; assign _dfoo23 = - source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo230 = - (source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo240 = - (source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo180 ; assign _dfoo25 = - source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo250 = - (source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo260 = - (source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo200 ; assign _dfoo27 = - source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo270 = - (source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678) ? - wdata32__h28409[27] : + wdata32__h28468[27] : _dfoo204 ; assign _dfoo273 = - source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo137 ; assign _dfoo274 = - (source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo206 ; assign _dfoo275 = - source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo139 ; assign _dfoo276 = - (source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo208 ; assign _dfoo277 = - source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo141 ; assign _dfoo278 = - (source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo210 ; assign _dfoo279 = - source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo143 ; assign _dfoo28 = - (source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo280 = - (source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo212 ; assign _dfoo281 = - source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo145 ; assign _dfoo282 = - (source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo214 ; assign _dfoo283 = - source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo147 ; assign _dfoo284 = - (source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo216 ; assign _dfoo285 = - source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo149 ; assign _dfoo286 = - (source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo218 ; assign _dfoo287 = - source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo151 ; assign _dfoo288 = - (source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo220 ; assign _dfoo289 = - source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo153 ; assign _dfoo29 = - source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo290 = - (source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo222 ; assign _dfoo291 = - source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo155 ; assign _dfoo292 = - (source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo224 ; assign _dfoo293 = - source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo157 ; assign _dfoo294 = - (source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo226 ; assign _dfoo295 = - source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo159 ; assign _dfoo296 = - (source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo228 ; assign _dfoo297 = - source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo161 ; assign _dfoo298 = - (source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo230 ; assign _dfoo299 = - source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo163 ; assign _dfoo3 = - source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo30 = - (source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo300 = - (source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo232 ; assign _dfoo301 = - source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo165 ; assign _dfoo302 = - (source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo234 ; assign _dfoo303 = - source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo167 ; assign _dfoo304 = - (source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo236 ; assign _dfoo305 = - source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo169 ; assign _dfoo306 = - (source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo238 ; assign _dfoo307 = - source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo171 ; assign _dfoo308 = - (source_id__h61237 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo240 ; assign _dfoo309 = - source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo173 ; assign _dfoo31 = - source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo310 = - (source_id__h61237 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo242 ; assign _dfoo311 = - source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo175 ; assign _dfoo312 = - (source_id__h61237 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo244 ; assign _dfoo313 = - source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo177 ; assign _dfoo314 = - (source_id__h61237 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo246 ; assign _dfoo315 = - source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo179 ; assign _dfoo316 = - (source_id__h61237 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo248 ; assign _dfoo317 = - source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo181 ; assign _dfoo318 = - (source_id__h61237 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo250 ; assign _dfoo319 = - source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo183 ; assign _dfoo32 = - (source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo320 = - (source_id__h61237 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo252 ; assign _dfoo321 = - source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo185 ; assign _dfoo322 = - (source_id__h61237 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo254 ; assign _dfoo323 = - source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo187 ; assign _dfoo324 = - (source_id__h61237 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo256 ; assign _dfoo325 = - source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo189 ; assign _dfoo326 = - (source_id__h61237 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo258 ; assign _dfoo327 = - source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo191 ; assign _dfoo328 = - (source_id__h61237 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo260 ; assign _dfoo329 = - source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo193 ; assign _dfoo33 = - source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo330 = - (source_id__h61237 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo262 ; assign _dfoo331 = - source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo195 ; assign _dfoo332 = - (source_id__h61237 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo264 ; assign _dfoo333 = - source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo197 ; assign _dfoo334 = - (source_id__h61237 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo266 ; assign _dfoo335 = - source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo199 ; assign _dfoo336 = - (source_id__h61237 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo268 ; assign _dfoo337 = - source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo201 ; assign _dfoo338 = - (source_id__h61237 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo270 ; assign _dfoo339 = - source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617 || - source_id__h62447 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h62506 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2678 || _dfoo203 ; assign _dfoo34 = - (source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo340 = - (source_id__h61237 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h61296 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2617) ? - wdata32__h28409[26] : + wdata32__h28468[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo280 ; assign _dfoo35 = - source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo350 = - (source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h66077 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo360 = - (source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo300 ; assign _dfoo37 = - source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo370 = - (source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo380 = - (source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo320 ; assign _dfoo39 = - source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo390 = - (source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h66077 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo40 = - (source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo400 = - (source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556) ? - wdata32__h28409[25] : + wdata32__h28468[25] : _dfoo340 ; assign _dfoo409 = - source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo273 ; assign _dfoo41 = - source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo410 = - (source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo342 ; assign _dfoo411 = - source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo275 ; assign _dfoo412 = - (source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo344 ; assign _dfoo413 = - source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo277 ; assign _dfoo414 = - (source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo346 ; assign _dfoo415 = - source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo279 ; assign _dfoo416 = - (source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo348 ; assign _dfoo417 = - source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo281 ; assign _dfoo418 = - (source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo350 ; assign _dfoo419 = - source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo283 ; assign _dfoo42 = - (source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo420 = - (source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo352 ; assign _dfoo421 = - source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo285 ; assign _dfoo422 = - (source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo354 ; assign _dfoo423 = - source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo287 ; assign _dfoo424 = - (source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo356 ; assign _dfoo425 = - source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo289 ; assign _dfoo426 = - (source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo358 ; assign _dfoo427 = - source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo291 ; assign _dfoo428 = - (source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo360 ; assign _dfoo429 = - source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo293 ; assign _dfoo43 = - source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo430 = - (source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo362 ; assign _dfoo431 = - source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo295 ; assign _dfoo432 = - (source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo364 ; assign _dfoo433 = - source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo297 ; assign _dfoo434 = - (source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo366 ; assign _dfoo435 = - source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo299 ; assign _dfoo436 = - (source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo368 ; assign _dfoo437 = - source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo301 ; assign _dfoo438 = - (source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo370 ; assign _dfoo439 = - source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo303 ; assign _dfoo44 = - (source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo440 = - (source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo372 ; assign _dfoo441 = - source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo305 ; assign _dfoo442 = - (source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo374 ; assign _dfoo443 = - source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo307 ; assign _dfoo444 = - (source_id__h58817 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo376 ; assign _dfoo445 = - source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo309 ; assign _dfoo446 = - (source_id__h58817 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo378 ; assign _dfoo447 = - source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo311 ; assign _dfoo448 = - (source_id__h58817 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo380 ; assign _dfoo449 = - source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo313 ; assign _dfoo45 = - source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo450 = - (source_id__h58817 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo382 ; assign _dfoo451 = - source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo315 ; assign _dfoo452 = - (source_id__h58817 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo384 ; assign _dfoo453 = - source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo317 ; assign _dfoo454 = - (source_id__h58817 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo386 ; assign _dfoo455 = - source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo319 ; assign _dfoo456 = - (source_id__h58817 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo388 ; assign _dfoo457 = - source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo321 ; assign _dfoo458 = - (source_id__h58817 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo390 ; assign _dfoo459 = - source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo323 ; assign _dfoo46 = - (source_id__h66077 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo460 = - (source_id__h58817 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo392 ; assign _dfoo461 = - source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo325 ; assign _dfoo462 = - (source_id__h58817 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo394 ; assign _dfoo463 = - source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo327 ; assign _dfoo464 = - (source_id__h58817 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo396 ; assign _dfoo465 = - source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo329 ; assign _dfoo466 = - (source_id__h58817 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo398 ; assign _dfoo467 = - source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo331 ; assign _dfoo468 = - (source_id__h58817 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo400 ; assign _dfoo469 = - source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo333 ; assign _dfoo47 = - source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo470 = - (source_id__h58817 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo402 ; assign _dfoo471 = - source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo335 ; assign _dfoo472 = - (source_id__h58817 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo404 ; assign _dfoo473 = - source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo337 ; assign _dfoo474 = - (source_id__h58817 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo406 ; assign _dfoo475 = - source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495 || - source_id__h60027 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h60086 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2556 || _dfoo339 ; assign _dfoo476 = - (source_id__h58817 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h58876 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2495) ? - wdata32__h28409[24] : + wdata32__h28468[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h66077 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo480 = - (source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo420 ; assign _dfoo49 = - source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo490 = - (source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo430 ; assign _dfoo5 = - source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo50 = - (source_id__h66077 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo500 = - (source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo440 ; assign _dfoo51 = - source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo510 = - (source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h66077 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo520 = - (source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo460 ; assign _dfoo53 = - source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo530 = - (source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h66077 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo540 = - (source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434) ? - wdata32__h28409[23] : + wdata32__h28468[23] : _dfoo476 ; assign _dfoo545 = - source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo409 ; assign _dfoo546 = - (source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo478 ; assign _dfoo547 = - source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo411 ; assign _dfoo548 = - (source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo480 ; assign _dfoo549 = - source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo413 ; assign _dfoo55 = - source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo550 = - (source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo482 ; assign _dfoo551 = - source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo415 ; assign _dfoo552 = - (source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo484 ; assign _dfoo553 = - source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo417 ; assign _dfoo554 = - (source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo486 ; assign _dfoo555 = - source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo419 ; assign _dfoo556 = - (source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo488 ; assign _dfoo557 = - source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo421 ; assign _dfoo558 = - (source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo490 ; assign _dfoo559 = - source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo423 ; assign _dfoo56 = - (source_id__h66077 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo560 = - (source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo492 ; assign _dfoo561 = - source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo425 ; assign _dfoo562 = - (source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo494 ; assign _dfoo563 = - source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo427 ; assign _dfoo564 = - (source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo496 ; assign _dfoo565 = - source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo429 ; assign _dfoo566 = - (source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo498 ; assign _dfoo567 = - source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo431 ; assign _dfoo568 = - (source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo500 ; assign _dfoo569 = - source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo433 ; assign _dfoo57 = - source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo570 = - (source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo502 ; assign _dfoo571 = - source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo435 ; assign _dfoo572 = - (source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo504 ; assign _dfoo573 = - source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo437 ; assign _dfoo574 = - (source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo506 ; assign _dfoo575 = - source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo439 ; assign _dfoo576 = - (source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo508 ; assign _dfoo577 = - source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo441 ; assign _dfoo578 = - (source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo510 ; assign _dfoo579 = - source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo443 ; assign _dfoo58 = - (source_id__h66077 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo580 = - (source_id__h56397 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo512 ; assign _dfoo581 = - source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo445 ; assign _dfoo582 = - (source_id__h56397 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo514 ; assign _dfoo583 = - source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo447 ; assign _dfoo584 = - (source_id__h56397 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo516 ; assign _dfoo585 = - source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo449 ; assign _dfoo586 = - (source_id__h56397 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo518 ; assign _dfoo587 = - source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo451 ; assign _dfoo588 = - (source_id__h56397 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo520 ; assign _dfoo589 = - source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo453 ; assign _dfoo59 = - source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo590 = - (source_id__h56397 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo522 ; assign _dfoo591 = - source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo455 ; assign _dfoo592 = - (source_id__h56397 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo524 ; assign _dfoo593 = - source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo457 ; assign _dfoo594 = - (source_id__h56397 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo526 ; assign _dfoo595 = - source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo459 ; assign _dfoo596 = - (source_id__h56397 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo528 ; assign _dfoo597 = - source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo461 ; assign _dfoo598 = - (source_id__h56397 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo530 ; assign _dfoo599 = - source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo463 ; assign _dfoo6 = - (source_id__h66077 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo60 = - (source_id__h66077 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo600 = - (source_id__h56397 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo532 ; assign _dfoo601 = - source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo465 ; assign _dfoo602 = - (source_id__h56397 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo534 ; assign _dfoo603 = - source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo467 ; assign _dfoo604 = - (source_id__h56397 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo536 ; assign _dfoo605 = - source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo469 ; assign _dfoo606 = - (source_id__h56397 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo538 ; assign _dfoo607 = - source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo471 ; assign _dfoo608 = - (source_id__h56397 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo540 ; assign _dfoo609 = - source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo473 ; assign _dfoo61 = - source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo610 = - (source_id__h56397 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo542 ; assign _dfoo611 = - source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373 || - source_id__h57607 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h57666 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2434 || _dfoo475 ; assign _dfoo612 = - (source_id__h56397 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h56456 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2373) ? - wdata32__h28409[22] : + wdata32__h28468[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h66077 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo620 = - (source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo560 ; assign _dfoo63 = - source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo630 = - (source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h66077 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo640 = - (source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo580 ; assign _dfoo65 = - source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo650 = - (source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h66077 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo660 = - (source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo600 ; assign _dfoo67 = - source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h67346 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo670 = - (source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h66077 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h66136 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo680 = - (source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312) ? - wdata32__h28409[21] : + wdata32__h28468[21] : _dfoo612 ; assign _dfoo681 = - source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo545 ; assign _dfoo682 = - (source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo614 ; assign _dfoo683 = - source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo547 ; assign _dfoo684 = - (source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo616 ; assign _dfoo685 = - source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo549 ; assign _dfoo686 = - (source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo618 ; assign _dfoo687 = - source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo551 ; assign _dfoo688 = - (source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo620 ; assign _dfoo689 = - source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo553 ; assign _dfoo690 = - (source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo622 ; assign _dfoo691 = - source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo555 ; assign _dfoo692 = - (source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo624 ; assign _dfoo693 = - source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo557 ; assign _dfoo694 = - (source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo626 ; assign _dfoo695 = - source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo559 ; assign _dfoo696 = - (source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo628 ; assign _dfoo697 = - source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo561 ; assign _dfoo698 = - (source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo630 ; assign _dfoo699 = - source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo563 ; assign _dfoo7 = - source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo70 = - (source_id__h64867 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo632 ; assign _dfoo701 = - source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo565 ; assign _dfoo702 = - (source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo634 ; assign _dfoo703 = - source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo567 ; assign _dfoo704 = - (source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo636 ; assign _dfoo705 = - source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo569 ; assign _dfoo706 = - (source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo638 ; assign _dfoo707 = - source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo571 ; assign _dfoo708 = - (source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo640 ; assign _dfoo709 = - source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo573 ; assign _dfoo710 = - (source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo642 ; assign _dfoo711 = - source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo575 ; assign _dfoo712 = - (source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo644 ; assign _dfoo713 = - source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo577 ; assign _dfoo714 = - (source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo646 ; assign _dfoo715 = - source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo579 ; assign _dfoo716 = - (source_id__h53977 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo648 ; assign _dfoo717 = - source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo581 ; assign _dfoo718 = - (source_id__h53977 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo650 ; assign _dfoo719 = - source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo583 ; assign _dfoo72 = - (source_id__h64867 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h53977 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo652 ; assign _dfoo721 = - source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo585 ; assign _dfoo722 = - (source_id__h53977 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo654 ; assign _dfoo723 = - source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo587 ; assign _dfoo724 = - (source_id__h53977 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo656 ; assign _dfoo725 = - source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo589 ; assign _dfoo726 = - (source_id__h53977 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo658 ; assign _dfoo727 = - source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo591 ; assign _dfoo728 = - (source_id__h53977 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo660 ; assign _dfoo729 = - source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo593 ; assign _dfoo730 = - (source_id__h53977 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo662 ; assign _dfoo731 = - source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo595 ; assign _dfoo732 = - (source_id__h53977 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo664 ; assign _dfoo733 = - source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo597 ; assign _dfoo734 = - (source_id__h53977 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo666 ; assign _dfoo735 = - source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo599 ; assign _dfoo736 = - (source_id__h53977 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo668 ; assign _dfoo737 = - source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo601 ; assign _dfoo738 = - (source_id__h53977 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo670 ; assign _dfoo739 = - source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo603 ; assign _dfoo74 = - (source_id__h64867 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h53977 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo672 ; assign _dfoo741 = - source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo605 ; assign _dfoo742 = - (source_id__h53977 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo674 ; assign _dfoo743 = - source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo607 ; assign _dfoo744 = - (source_id__h53977 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo676 ; assign _dfoo745 = - source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo609 ; assign _dfoo746 = - (source_id__h53977 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo678 ; assign _dfoo747 = - source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251 || - source_id__h55187 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h55246 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2312 || _dfoo611 ; assign _dfoo748 = - (source_id__h53977 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h54036 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2251) ? - wdata32__h28409[20] : + wdata32__h28468[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h64867 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h64867 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h66077 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h66136 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861) ? - wdata32__h28409[30] : - wdata32__h28409[31] ; + wdata32__h28468[30] : + wdata32__h28468[31] ; assign _dfoo80 = - (source_id__h64867 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190) ? - wdata32__h28409[19] : + wdata32__h28468[19] : _dfoo748 ; assign _dfoo817 = - source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo681 ; assign _dfoo818 = - (source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo750 ; assign _dfoo819 = - source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo683 ; assign _dfoo82 = - (source_id__h64867 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo752 ; assign _dfoo821 = - source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo685 ; assign _dfoo822 = - (source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo754 ; assign _dfoo823 = - source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo687 ; assign _dfoo824 = - (source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo756 ; assign _dfoo825 = - source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo689 ; assign _dfoo826 = - (source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo758 ; assign _dfoo827 = - source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo691 ; assign _dfoo828 = - (source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo760 ; assign _dfoo829 = - source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo693 ; assign _dfoo830 = - (source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo762 ; assign _dfoo831 = - source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo695 ; assign _dfoo832 = - (source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo764 ; assign _dfoo833 = - source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo697 ; assign _dfoo834 = - (source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo766 ; assign _dfoo835 = - source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo699 ; assign _dfoo836 = - (source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo768 ; assign _dfoo837 = - source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo701 ; assign _dfoo838 = - (source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo770 ; assign _dfoo839 = - source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo703 ; assign _dfoo84 = - (source_id__h64867 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo772 ; assign _dfoo841 = - source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo705 ; assign _dfoo842 = - (source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo774 ; assign _dfoo843 = - source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo707 ; assign _dfoo844 = - (source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo776 ; assign _dfoo845 = - source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo709 ; assign _dfoo846 = - (source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo778 ; assign _dfoo847 = - source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo711 ; assign _dfoo848 = - (source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo780 ; assign _dfoo849 = - source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo713 ; assign _dfoo850 = - (source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo782 ; assign _dfoo851 = - source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo715 ; assign _dfoo852 = - (source_id__h51557 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo784 ; assign _dfoo853 = - source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo717 ; assign _dfoo854 = - (source_id__h51557 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo786 ; assign _dfoo855 = - source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo719 ; assign _dfoo856 = - (source_id__h51557 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo788 ; assign _dfoo857 = - source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo721 ; assign _dfoo858 = - (source_id__h51557 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo790 ; assign _dfoo859 = - source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo723 ; assign _dfoo86 = - (source_id__h64867 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h51557 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo792 ; assign _dfoo861 = - source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo725 ; assign _dfoo862 = - (source_id__h51557 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo794 ; assign _dfoo863 = - source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo727 ; assign _dfoo864 = - (source_id__h51557 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo796 ; assign _dfoo865 = - source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo729 ; assign _dfoo866 = - (source_id__h51557 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo798 ; assign _dfoo867 = - source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo731 ; assign _dfoo868 = - (source_id__h51557 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo800 ; assign _dfoo869 = - source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo733 ; assign _dfoo870 = - (source_id__h51557 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo802 ; assign _dfoo871 = - source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo735 ; assign _dfoo872 = - (source_id__h51557 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo804 ; assign _dfoo873 = - source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo737 ; assign _dfoo874 = - (source_id__h51557 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo806 ; assign _dfoo875 = - source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo739 ; assign _dfoo876 = - (source_id__h51557 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo808 ; assign _dfoo877 = - source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo741 ; assign _dfoo878 = - (source_id__h51557 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo810 ; assign _dfoo879 = - source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo743 ; assign _dfoo88 = - (source_id__h64867 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h51557 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo812 ; assign _dfoo881 = - source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo745 ; assign _dfoo882 = - (source_id__h51557 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo814 ; assign _dfoo883 = - source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129 || - source_id__h52767 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h52826 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2190 || _dfoo747 ; assign _dfoo884 = - (source_id__h51557 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h51616 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2129) ? - wdata32__h28409[18] : + wdata32__h28468[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo830 ; assign _dfoo9 = - source_id__h66077 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h66136 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2861 || - source_id__h67287 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h67346 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2922 ; assign _dfoo90 = - (source_id__h64867 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h64867 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h64867 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068) ? - wdata32__h28409[17] : + wdata32__h28468[17] : _dfoo884 ; assign _dfoo953 = - source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo817 ; assign _dfoo954 = - (source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo886 ; assign _dfoo955 = - source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo819 ; assign _dfoo956 = - (source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo888 ; assign _dfoo957 = - source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo821 ; assign _dfoo958 = - (source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo890 ; assign _dfoo959 = - source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo823 ; assign _dfoo96 = - (source_id__h64867 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo892 ; assign _dfoo961 = - source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo825 ; assign _dfoo962 = - (source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo894 ; assign _dfoo963 = - source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo827 ; assign _dfoo964 = - (source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo896 ; assign _dfoo965 = - source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo829 ; assign _dfoo966 = - (source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo898 ; assign _dfoo967 = - source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo831 ; assign _dfoo968 = - (source_id__h49137 == 10'd9 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd9 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo900 ; assign _dfoo969 = - source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo833 ; assign _dfoo970 = - (source_id__h49137 == 10'd8 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd8 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo902 ; assign _dfoo971 = - source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo835 ; assign _dfoo972 = - (source_id__h49137 == 10'd7 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd7 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo904 ; assign _dfoo973 = - source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo837 ; assign _dfoo974 = - (source_id__h49137 == 10'd6 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd6 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo906 ; assign _dfoo975 = - source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo839 ; assign _dfoo976 = - (source_id__h49137 == 10'd5 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd5 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo908 ; assign _dfoo977 = - source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo841 ; assign _dfoo978 = - (source_id__h49137 == 10'd4 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd4 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo910 ; assign _dfoo979 = - source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo843 ; assign _dfoo98 = - (source_id__h64867 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h64926 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2800) ? - wdata32__h28409[29] : + wdata32__h28468[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h49137 == 10'd3 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd3 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo912 ; assign _dfoo981 = - source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo845 ; assign _dfoo982 = - (source_id__h49137 == 10'd2 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd2 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo914 ; assign _dfoo983 = - source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo847 ; assign _dfoo984 = - (source_id__h49137 == 10'd1 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd1 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo916 ; assign _dfoo985 = - source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + source_id__h50406 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo849 ; assign _dfoo986 = - (source_id__h49137 == 10'd0 && - addr_offset__h28408[11:7] == 5'd1 && + (source_id__h49196 == 10'd0 && + addr_offset__h28467[11:7] == 5'd1 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo918 ; assign _dfoo987 = - source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo851 ; assign _dfoo988 = - (source_id__h49137 == 10'd16 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd16 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo920 ; assign _dfoo989 = - source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo853 ; assign _dfoo990 = - (source_id__h49137 == 10'd15 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd15 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo922 ; assign _dfoo991 = - source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo855 ; assign _dfoo992 = - (source_id__h49137 == 10'd14 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd14 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo924 ; assign _dfoo993 = - source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo857 ; assign _dfoo994 = - (source_id__h49137 == 10'd13 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd13 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo926 ; assign _dfoo995 = - source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo859 ; assign _dfoo996 = - (source_id__h49137 == 10'd12 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd12 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo928 ; assign _dfoo997 = - source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo861 ; assign _dfoo998 = - (source_id__h49137 == 10'd11 && - addr_offset__h28408[11:7] == 5'd0 && + (source_id__h49196 == 10'd11 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007) ? - wdata32__h28409[16] : + wdata32__h28468[16] : _dfoo930 ; assign _dfoo999 = - source_id__h49137 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h49196 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2007 || - source_id__h50347 == 10'd10 && - addr_offset__h28408[11:7] == 5'd0 && + source_id__h50406 == 10'd10 && + addr_offset__h28467[11:7] == 5'd0 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2068 || _dfoo863 ; - assign a__h72910 = + assign a__h72969 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 ? m_vrg_source_prio_16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3211 ; - assign a__h74915 = + assign a__h74974 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3309 ? m_vrg_source_prio_16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3305 ; - assign addr_offset__h14540 = + assign addr_offset__h14599 = m_slave_xactor_shim_arff$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h28408 = + assign addr_offset__h28467 = m_slave_xactor_shim_awff$D_OUT[92:29] - m_rg_addr_base ; - assign b__h72911 = + assign b__h72970 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3231 ; - assign b__h74916 = + assign b__h74975 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3309 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d3325 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 = - addr_offset__h14540 < 64'h0000000000001000 ; + addr_offset__h14599 < 64'h0000000000001000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 = - addr_offset__h14540[11:2] <= 10'd16 ; + addr_offset__h14599[11:2] <= 10'd16 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && - addr_offset__h14540[11:2] != 10'd0 && + addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106 && m_cfg_verbosity != 4'd0 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 = - addr_offset__h14540 < 64'h0000000000002000 ; + addr_offset__h14599 < 64'h0000000000002000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 = - source_id_base__h14985 <= 10'd16 ; + source_id_base__h15044 <= 10'd16 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306 = - addr_offset__h14540 < 64'h0000000000003000 ; + addr_offset__h14599 < 64'h0000000000003000 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308 = - addr_offset__h14540[11:7] <= 5'd1 ; + addr_offset__h14599[11:7] <= 5'd1 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 = - addr_offset__h14540[16:12] <= 5'd1 ; + addr_offset__h14599[16:12] <= 5'd1 ; assign m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 = m_slave_xactor_shim_arff$D_OUT[92:29] < m_rg_addr_base ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1001 = - addr_offset__h28408[11:2] == 10'd15 && + addr_offset__h28467[11:2] == 10'd15 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1003 = - addr_offset__h28408[11:2] == 10'd16 && + addr_offset__h28467[11:2] == 10'd16 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && - addr_offset__h28408[11:2] != 10'd0 && + addr_offset__h28467[11:2] != 10'd0 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 && m_cfg_verbosity != 4'd0 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1010 = - addr_offset__h28408 < 64'h0000000000002000 ; + addr_offset__h28467 < 64'h0000000000002000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1013 = - source_id_base__h29659 <= 10'd16 ; + source_id_base__h29718 <= 10'd16 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1024 = - addr_offset__h28408 < 64'h0000000000003000 ; + addr_offset__h28467 < 64'h0000000000003000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1025 = - addr_offset__h28408[11:7] <= 5'd1 ; + addr_offset__h28467[11:7] <= 5'd1 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1031 = - addr_offset__h28408[11:7] == 5'd0 && + addr_offset__h28467[11:7] == 5'd0 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1028 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1067 = - addr_offset__h28408[11:7] == 5'd1 && + addr_offset__h28467[11:7] == 5'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1028 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 = - addr_offset__h28408[16:12] <= 5'd1 ; + addr_offset__h28467[16:12] <= 5'd1 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2996 = - addr_offset__h28408[16:12] == 5'd0 && + addr_offset__h28467[16:12] == 5'd0 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2998 = - addr_offset__h28408[16:12] == 5'd1 && + addr_offset__h28467[16:12] == 5'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2993 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 = m_slave_xactor_shim_awff$D_OUT[92:29] < m_rg_addr_base ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 = - addr_offset__h28408 < 64'h0000000000001000 ; + addr_offset__h28467 < 64'h0000000000001000 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 = - addr_offset__h28408[11:2] <= 10'd16 ; + addr_offset__h28467[11:2] <= 10'd16 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d973 = - addr_offset__h28408[11:2] == 10'd1 && + addr_offset__h28467[11:2] == 10'd1 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d975 = - addr_offset__h28408[11:2] == 10'd2 && + addr_offset__h28467[11:2] == 10'd2 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d977 = - addr_offset__h28408[11:2] == 10'd3 && + addr_offset__h28467[11:2] == 10'd3 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d979 = - addr_offset__h28408[11:2] == 10'd4 && + addr_offset__h28467[11:2] == 10'd4 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d981 = - addr_offset__h28408[11:2] == 10'd5 && + addr_offset__h28467[11:2] == 10'd5 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d983 = - addr_offset__h28408[11:2] == 10'd6 && + addr_offset__h28467[11:2] == 10'd6 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d985 = - addr_offset__h28408[11:2] == 10'd7 && + addr_offset__h28467[11:2] == 10'd7 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d987 = - addr_offset__h28408[11:2] == 10'd8 && + addr_offset__h28467[11:2] == 10'd8 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d989 = - addr_offset__h28408[11:2] == 10'd9 && + addr_offset__h28467[11:2] == 10'd9 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d991 = - addr_offset__h28408[11:2] == 10'd10 && + addr_offset__h28467[11:2] == 10'd10 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d993 = - addr_offset__h28408[11:2] == 10'd11 && + addr_offset__h28467[11:2] == 10'd11 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d995 = - addr_offset__h28408[11:2] == 10'd12 && + addr_offset__h28467[11:2] == 10'd12 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d997 = - addr_offset__h28408[11:2] == 10'd13 && + addr_offset__h28467[11:2] == 10'd13 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; assign m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d999 = - addr_offset__h28408[11:2] == 10'd14 && + addr_offset__h28467[11:2] == 10'd14 && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d957 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d959 ; @@ -16418,7 +16423,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_10 && m_vrg_source_prio_10 > IF_m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_so_ETC___d674 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; assign m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_sour_ETC___d3190 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > @@ -16433,7 +16438,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_11 && m_vrg_source_prio_11 > IF_m_vrg_source_ip_10_read__56_AND_NOT_m_vrg_s_ETC___d681 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; assign m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_sour_ETC___d3195 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > @@ -16448,7 +16453,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_12 && m_vrg_source_prio_12 > IF_m_vrg_source_ip_11_read__57_AND_NOT_m_vrg_s_ETC___d688 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; assign m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d3200 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > @@ -16463,7 +16468,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 && m_vrg_source_prio_13 > IF_m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_s_ETC___d695 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; assign m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d757 = m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d701 || m_vrg_source_ip_12_read__58_AND_NOT_m_vrg_sour_ETC___d694 || @@ -16486,7 +16491,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_14 && m_vrg_source_prio_14 > IF_m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_s_ETC___d702 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; assign m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d3210 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > @@ -16501,7 +16506,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_15 && m_vrg_source_prio_15 > IF_m_vrg_source_ip_14_read__60_AND_NOT_m_vrg_s_ETC___d709 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d3215 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > @@ -16515,7 +16520,7 @@ module mkPLIC_16_2_7(CLK, assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 = m_vrg_source_ip_16 && !m_vrg_source_prio_16_29_ULE_IF_m_vrg_source_ip_ETC___d717 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; assign m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 || m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d715 || @@ -16523,7 +16528,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13_read__59_AND_NOT_m_vrg_sour_ETC___d757 ; assign m_vrg_source_ip_1_read__47_AND_NOT_m_vrg_sourc_ETC___d617 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; assign m_vrg_source_ip_2_read__48_AND_NOT_m_vrg_sourc_ETC___d3145 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > @@ -16538,7 +16543,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_2 && m_vrg_source_prio_2 > IF_m_vrg_source_ip_1_read__47_AND_NOT_m_vrg_so_ETC___d618 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; assign m_vrg_source_ip_3_read__49_AND_NOT_m_vrg_sourc_ETC___d3150 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > @@ -16553,7 +16558,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_3 && m_vrg_source_prio_3 > IF_m_vrg_source_ip_2_read__48_AND_NOT_m_vrg_so_ETC___d625 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; assign m_vrg_source_ip_4_read__50_AND_NOT_m_vrg_sourc_ETC___d3155 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > @@ -16568,7 +16573,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_4 && m_vrg_source_prio_4 > IF_m_vrg_source_ip_3_read__49_AND_NOT_m_vrg_so_ETC___d632 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; assign m_vrg_source_ip_5_read__51_AND_NOT_m_vrg_sourc_ETC___d3160 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > @@ -16583,7 +16588,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_5 && m_vrg_source_prio_5 > IF_m_vrg_source_ip_4_read__50_AND_NOT_m_vrg_so_ETC___d639 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; assign m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_sourc_ETC___d3165 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > @@ -16598,7 +16603,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_6 && m_vrg_source_prio_6 > IF_m_vrg_source_ip_5_read__51_AND_NOT_m_vrg_so_ETC___d646 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; assign m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d3170 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > @@ -16613,7 +16618,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_7 && m_vrg_source_prio_7 > IF_m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_so_ETC___d653 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; assign m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d751 = m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_sourc_ETC___d659 || m_vrg_source_ip_6_read__52_AND_NOT_m_vrg_sourc_ETC___d652 || @@ -16636,7 +16641,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_8 && m_vrg_source_prio_8 > IF_m_vrg_source_ip_7_read__53_AND_NOT_m_vrg_so_ETC___d660 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; assign m_vrg_source_ip_9_read__55_AND_NOT_m_vrg_sourc_ETC___d3180 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > @@ -16651,306 +16656,306 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_9 && m_vrg_source_prio_9 > IF_m_vrg_source_ip_8_read__54_AND_NOT_m_vrg_so_ETC___d667 && - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; assign m_vrg_source_prio_16_29_ULE_IF_m_vrg_source_ip_ETC___d717 = m_vrg_source_prio_16 <= (m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_sour_ETC___d715 ? m_vrg_source_prio_15 : IF_m_vrg_source_ip_14_read__60_AND_NOT_m_vrg_s_ETC___d709) ; - assign max_id__h25318 = + assign max_id__h25377 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d722 ? 5'd16 : IF_m_vrg_source_ip_15_read__61_AND_NOT_m_vrg_s_ETC___d737 ; - assign rdata___1__h27806 = { rdata__h27563[31:0], 32'h0 } ; - assign rdata__h27563 = + assign rdata___1__h27865 = { rdata__h27622[31:0], 32'h0 } ; + assign rdata__h27622 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 ? 64'd0 : - y_avValue_fst__h27555 ; - assign source_id__h17021 = { addr_offset__h14540[4:0], 5'd31 } ; - assign source_id__h17128 = { addr_offset__h14540[4:0], 5'd30 } ; - assign source_id__h17201 = { addr_offset__h14540[4:0], 5'd29 } ; - assign source_id__h17274 = { addr_offset__h14540[4:0], 5'd28 } ; - assign source_id__h17347 = { addr_offset__h14540[4:0], 5'd27 } ; - assign source_id__h17420 = { addr_offset__h14540[4:0], 5'd26 } ; - assign source_id__h17493 = { addr_offset__h14540[4:0], 5'd25 } ; - assign source_id__h17566 = { addr_offset__h14540[4:0], 5'd24 } ; - assign source_id__h17639 = { addr_offset__h14540[4:0], 5'd23 } ; - assign source_id__h17712 = { addr_offset__h14540[4:0], 5'd22 } ; - assign source_id__h17785 = { addr_offset__h14540[4:0], 5'd21 } ; - assign source_id__h17858 = { addr_offset__h14540[4:0], 5'd20 } ; - assign source_id__h17931 = { addr_offset__h14540[4:0], 5'd19 } ; - assign source_id__h18004 = { addr_offset__h14540[4:0], 5'd18 } ; - assign source_id__h18077 = { addr_offset__h14540[4:0], 5'd17 } ; - assign source_id__h18150 = { addr_offset__h14540[4:0], 5'd16 } ; - assign source_id__h18223 = { addr_offset__h14540[4:0], 5'd15 } ; - assign source_id__h18296 = { addr_offset__h14540[4:0], 5'd14 } ; - assign source_id__h18369 = { addr_offset__h14540[4:0], 5'd13 } ; - assign source_id__h18442 = { addr_offset__h14540[4:0], 5'd12 } ; - assign source_id__h18515 = { addr_offset__h14540[4:0], 5'd11 } ; - assign source_id__h18588 = { addr_offset__h14540[4:0], 5'd10 } ; - assign source_id__h18661 = { addr_offset__h14540[4:0], 5'd9 } ; - assign source_id__h18734 = { addr_offset__h14540[4:0], 5'd8 } ; - assign source_id__h18807 = { addr_offset__h14540[4:0], 5'd7 } ; - assign source_id__h18880 = { addr_offset__h14540[4:0], 5'd6 } ; - assign source_id__h18953 = { addr_offset__h14540[4:0], 5'd5 } ; - assign source_id__h19026 = { addr_offset__h14540[4:0], 5'd4 } ; - assign source_id__h19099 = { addr_offset__h14540[4:0], 5'd3 } ; - assign source_id__h19172 = { addr_offset__h14540[4:0], 5'd2 } ; - assign source_id__h19245 = { addr_offset__h14540[4:0], 5'd1 } ; - assign source_id__h21494 = 10'd31 + source_id_base__h14985 ; - assign source_id__h21670 = 10'd30 + source_id_base__h14985 ; - assign source_id__h21778 = 10'd29 + source_id_base__h14985 ; - assign source_id__h21886 = 10'd28 + source_id_base__h14985 ; - assign source_id__h21994 = 10'd27 + source_id_base__h14985 ; - assign source_id__h22102 = 10'd26 + source_id_base__h14985 ; - assign source_id__h22210 = 10'd25 + source_id_base__h14985 ; - assign source_id__h22318 = 10'd24 + source_id_base__h14985 ; - assign source_id__h22426 = 10'd23 + source_id_base__h14985 ; - assign source_id__h22534 = 10'd22 + source_id_base__h14985 ; - assign source_id__h22642 = 10'd21 + source_id_base__h14985 ; - assign source_id__h22750 = 10'd20 + source_id_base__h14985 ; - assign source_id__h22858 = 10'd19 + source_id_base__h14985 ; - assign source_id__h22966 = 10'd18 + source_id_base__h14985 ; - assign source_id__h23074 = 10'd17 + source_id_base__h14985 ; - assign source_id__h23182 = 10'd16 + source_id_base__h14985 ; - assign source_id__h23290 = 10'd15 + source_id_base__h14985 ; - assign source_id__h23398 = 10'd14 + source_id_base__h14985 ; - assign source_id__h23506 = 10'd13 + source_id_base__h14985 ; - assign source_id__h23614 = 10'd12 + source_id_base__h14985 ; - assign source_id__h23722 = 10'd11 + source_id_base__h14985 ; - assign source_id__h23830 = 10'd10 + source_id_base__h14985 ; - assign source_id__h23938 = 10'd9 + source_id_base__h14985 ; - assign source_id__h24046 = 10'd8 + source_id_base__h14985 ; - assign source_id__h24154 = 10'd7 + source_id_base__h14985 ; - assign source_id__h24262 = 10'd6 + source_id_base__h14985 ; - assign source_id__h24370 = 10'd5 + source_id_base__h14985 ; - assign source_id__h24478 = 10'd4 + source_id_base__h14985 ; - assign source_id__h24586 = 10'd3 + source_id_base__h14985 ; - assign source_id__h24694 = 10'd2 + source_id_base__h14985 ; - assign source_id__h24802 = 10'd1 + source_id_base__h14985 ; - assign source_id__h30987 = { addr_offset__h28408[4:0], 5'd1 } ; - assign source_id__h32197 = { addr_offset__h28408[4:0], 5'd2 } ; - assign source_id__h33407 = { addr_offset__h28408[4:0], 5'd3 } ; - assign source_id__h34617 = { addr_offset__h28408[4:0], 5'd4 } ; - assign source_id__h35827 = { addr_offset__h28408[4:0], 5'd5 } ; - assign source_id__h37037 = { addr_offset__h28408[4:0], 5'd6 } ; - assign source_id__h38247 = { addr_offset__h28408[4:0], 5'd7 } ; - assign source_id__h39457 = { addr_offset__h28408[4:0], 5'd8 } ; - assign source_id__h40667 = { addr_offset__h28408[4:0], 5'd9 } ; - assign source_id__h41877 = { addr_offset__h28408[4:0], 5'd10 } ; - assign source_id__h43087 = { addr_offset__h28408[4:0], 5'd11 } ; - assign source_id__h44297 = { addr_offset__h28408[4:0], 5'd12 } ; - assign source_id__h45507 = { addr_offset__h28408[4:0], 5'd13 } ; - assign source_id__h46717 = { addr_offset__h28408[4:0], 5'd14 } ; - assign source_id__h47927 = { addr_offset__h28408[4:0], 5'd15 } ; - assign source_id__h49137 = { addr_offset__h28408[4:0], 5'd16 } ; - assign source_id__h50347 = { addr_offset__h28408[4:0], 5'd17 } ; - assign source_id__h51557 = { addr_offset__h28408[4:0], 5'd18 } ; - assign source_id__h52767 = { addr_offset__h28408[4:0], 5'd19 } ; - assign source_id__h53977 = { addr_offset__h28408[4:0], 5'd20 } ; - assign source_id__h55187 = { addr_offset__h28408[4:0], 5'd21 } ; - assign source_id__h56397 = { addr_offset__h28408[4:0], 5'd22 } ; - assign source_id__h57607 = { addr_offset__h28408[4:0], 5'd23 } ; - assign source_id__h58817 = { addr_offset__h28408[4:0], 5'd24 } ; - assign source_id__h60027 = { addr_offset__h28408[4:0], 5'd25 } ; - assign source_id__h61237 = { addr_offset__h28408[4:0], 5'd26 } ; - assign source_id__h62447 = { addr_offset__h28408[4:0], 5'd27 } ; - assign source_id__h63657 = { addr_offset__h28408[4:0], 5'd28 } ; - assign source_id__h64867 = { addr_offset__h28408[4:0], 5'd29 } ; - assign source_id__h66077 = { addr_offset__h28408[4:0], 5'd30 } ; - assign source_id__h67287 = { addr_offset__h28408[4:0], 5'd31 } ; - assign source_id__h68952 = { 5'd0, x__h69004 } ; - assign source_id_base__h14985 = { addr_offset__h14540[4:0], 5'h0 } ; - assign source_id_base__h29659 = { addr_offset__h28408[4:0], 5'h0 } ; - assign v__h14777 = { 61'd0, x__h14848 } ; - assign v__h15027 = { 32'd0, v_ip__h15030 } ; - assign v__h19501 = { 32'd0, v_ie__h19504 } ; - assign v__h25119 = { 61'd0, x__h25190 } ; - assign v__h26816 = + y_avValue_fst__h27614 ; + assign source_id__h17080 = { addr_offset__h14599[4:0], 5'd31 } ; + assign source_id__h17187 = { addr_offset__h14599[4:0], 5'd30 } ; + assign source_id__h17260 = { addr_offset__h14599[4:0], 5'd29 } ; + assign source_id__h17333 = { addr_offset__h14599[4:0], 5'd28 } ; + assign source_id__h17406 = { addr_offset__h14599[4:0], 5'd27 } ; + assign source_id__h17479 = { addr_offset__h14599[4:0], 5'd26 } ; + assign source_id__h17552 = { addr_offset__h14599[4:0], 5'd25 } ; + assign source_id__h17625 = { addr_offset__h14599[4:0], 5'd24 } ; + assign source_id__h17698 = { addr_offset__h14599[4:0], 5'd23 } ; + assign source_id__h17771 = { addr_offset__h14599[4:0], 5'd22 } ; + assign source_id__h17844 = { addr_offset__h14599[4:0], 5'd21 } ; + assign source_id__h17917 = { addr_offset__h14599[4:0], 5'd20 } ; + assign source_id__h17990 = { addr_offset__h14599[4:0], 5'd19 } ; + assign source_id__h18063 = { addr_offset__h14599[4:0], 5'd18 } ; + assign source_id__h18136 = { addr_offset__h14599[4:0], 5'd17 } ; + assign source_id__h18209 = { addr_offset__h14599[4:0], 5'd16 } ; + assign source_id__h18282 = { addr_offset__h14599[4:0], 5'd15 } ; + assign source_id__h18355 = { addr_offset__h14599[4:0], 5'd14 } ; + assign source_id__h18428 = { addr_offset__h14599[4:0], 5'd13 } ; + assign source_id__h18501 = { addr_offset__h14599[4:0], 5'd12 } ; + assign source_id__h18574 = { addr_offset__h14599[4:0], 5'd11 } ; + assign source_id__h18647 = { addr_offset__h14599[4:0], 5'd10 } ; + assign source_id__h18720 = { addr_offset__h14599[4:0], 5'd9 } ; + assign source_id__h18793 = { addr_offset__h14599[4:0], 5'd8 } ; + assign source_id__h18866 = { addr_offset__h14599[4:0], 5'd7 } ; + assign source_id__h18939 = { addr_offset__h14599[4:0], 5'd6 } ; + assign source_id__h19012 = { addr_offset__h14599[4:0], 5'd5 } ; + assign source_id__h19085 = { addr_offset__h14599[4:0], 5'd4 } ; + assign source_id__h19158 = { addr_offset__h14599[4:0], 5'd3 } ; + assign source_id__h19231 = { addr_offset__h14599[4:0], 5'd2 } ; + assign source_id__h19304 = { addr_offset__h14599[4:0], 5'd1 } ; + assign source_id__h21553 = 10'd31 + source_id_base__h15044 ; + assign source_id__h21729 = 10'd30 + source_id_base__h15044 ; + assign source_id__h21837 = 10'd29 + source_id_base__h15044 ; + assign source_id__h21945 = 10'd28 + source_id_base__h15044 ; + assign source_id__h22053 = 10'd27 + source_id_base__h15044 ; + assign source_id__h22161 = 10'd26 + source_id_base__h15044 ; + assign source_id__h22269 = 10'd25 + source_id_base__h15044 ; + assign source_id__h22377 = 10'd24 + source_id_base__h15044 ; + assign source_id__h22485 = 10'd23 + source_id_base__h15044 ; + assign source_id__h22593 = 10'd22 + source_id_base__h15044 ; + assign source_id__h22701 = 10'd21 + source_id_base__h15044 ; + assign source_id__h22809 = 10'd20 + source_id_base__h15044 ; + assign source_id__h22917 = 10'd19 + source_id_base__h15044 ; + assign source_id__h23025 = 10'd18 + source_id_base__h15044 ; + assign source_id__h23133 = 10'd17 + source_id_base__h15044 ; + assign source_id__h23241 = 10'd16 + source_id_base__h15044 ; + assign source_id__h23349 = 10'd15 + source_id_base__h15044 ; + assign source_id__h23457 = 10'd14 + source_id_base__h15044 ; + assign source_id__h23565 = 10'd13 + source_id_base__h15044 ; + assign source_id__h23673 = 10'd12 + source_id_base__h15044 ; + assign source_id__h23781 = 10'd11 + source_id_base__h15044 ; + assign source_id__h23889 = 10'd10 + source_id_base__h15044 ; + assign source_id__h23997 = 10'd9 + source_id_base__h15044 ; + assign source_id__h24105 = 10'd8 + source_id_base__h15044 ; + assign source_id__h24213 = 10'd7 + source_id_base__h15044 ; + assign source_id__h24321 = 10'd6 + source_id_base__h15044 ; + assign source_id__h24429 = 10'd5 + source_id_base__h15044 ; + assign source_id__h24537 = 10'd4 + source_id_base__h15044 ; + assign source_id__h24645 = 10'd3 + source_id_base__h15044 ; + assign source_id__h24753 = 10'd2 + source_id_base__h15044 ; + assign source_id__h24861 = 10'd1 + source_id_base__h15044 ; + assign source_id__h31046 = { addr_offset__h28467[4:0], 5'd1 } ; + assign source_id__h32256 = { addr_offset__h28467[4:0], 5'd2 } ; + assign source_id__h33466 = { addr_offset__h28467[4:0], 5'd3 } ; + assign source_id__h34676 = { addr_offset__h28467[4:0], 5'd4 } ; + assign source_id__h35886 = { addr_offset__h28467[4:0], 5'd5 } ; + assign source_id__h37096 = { addr_offset__h28467[4:0], 5'd6 } ; + assign source_id__h38306 = { addr_offset__h28467[4:0], 5'd7 } ; + assign source_id__h39516 = { addr_offset__h28467[4:0], 5'd8 } ; + assign source_id__h40726 = { addr_offset__h28467[4:0], 5'd9 } ; + assign source_id__h41936 = { addr_offset__h28467[4:0], 5'd10 } ; + assign source_id__h43146 = { addr_offset__h28467[4:0], 5'd11 } ; + assign source_id__h44356 = { addr_offset__h28467[4:0], 5'd12 } ; + assign source_id__h45566 = { addr_offset__h28467[4:0], 5'd13 } ; + assign source_id__h46776 = { addr_offset__h28467[4:0], 5'd14 } ; + assign source_id__h47986 = { addr_offset__h28467[4:0], 5'd15 } ; + assign source_id__h49196 = { addr_offset__h28467[4:0], 5'd16 } ; + assign source_id__h50406 = { addr_offset__h28467[4:0], 5'd17 } ; + assign source_id__h51616 = { addr_offset__h28467[4:0], 5'd18 } ; + assign source_id__h52826 = { addr_offset__h28467[4:0], 5'd19 } ; + assign source_id__h54036 = { addr_offset__h28467[4:0], 5'd20 } ; + assign source_id__h55246 = { addr_offset__h28467[4:0], 5'd21 } ; + assign source_id__h56456 = { addr_offset__h28467[4:0], 5'd22 } ; + assign source_id__h57666 = { addr_offset__h28467[4:0], 5'd23 } ; + assign source_id__h58876 = { addr_offset__h28467[4:0], 5'd24 } ; + assign source_id__h60086 = { addr_offset__h28467[4:0], 5'd25 } ; + assign source_id__h61296 = { addr_offset__h28467[4:0], 5'd26 } ; + assign source_id__h62506 = { addr_offset__h28467[4:0], 5'd27 } ; + assign source_id__h63716 = { addr_offset__h28467[4:0], 5'd28 } ; + assign source_id__h64926 = { addr_offset__h28467[4:0], 5'd29 } ; + assign source_id__h66136 = { addr_offset__h28467[4:0], 5'd30 } ; + assign source_id__h67346 = { addr_offset__h28467[4:0], 5'd31 } ; + assign source_id__h69011 = { 5'd0, x__h69063 } ; + assign source_id_base__h15044 = { addr_offset__h14599[4:0], 5'h0 } ; + assign source_id_base__h29718 = { addr_offset__h28467[4:0], 5'h0 } ; + assign v__h14836 = { 61'd0, x__h14907 } ; + assign v__h15086 = { 32'd0, v_ip__h15089 } ; + assign v__h19560 = { 32'd0, v_ie__h19563 } ; + assign v__h25178 = { 61'd0, x__h25249 } ; + assign v__h26875 = m_vrg_source_ip_16_read__62_AND_NOT_m_vrg_sour_ETC___d760 ? - v__h26835 : + v__h26894 : 64'd0 ; - assign v__h26835 = { 59'd0, max_id__h25318 } ; - assign v_ie__h19504 = - { source_id__h21494 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h21670 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h21778 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h21886 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h21994 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h22102 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h22210 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h22318 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h22426 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h22534 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h22642 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h22750 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h22858 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h22966 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h23074 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h23182 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h23290 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h23398 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h23506 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h23614 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h23722 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h23830 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h23938 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h24046 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h24154 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h24262 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h24370 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h24478 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h24586 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h24694 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h24802 <= 10'd16 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + assign v__h26894 = { 59'd0, max_id__h25377 } ; + assign v_ie__h19563 = + { source_id__h21553 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, + source_id__h21729 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + source_id__h21837 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + source_id__h21945 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + source_id__h22053 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + source_id__h22161 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + source_id__h22269 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + source_id__h22377 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + source_id__h22485 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + source_id__h22593 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + source_id__h22701 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + source_id__h22809 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + source_id__h22917 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + source_id__h23025 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + source_id__h23133 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + source_id__h23241 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + source_id__h23349 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + source_id__h23457 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + source_id__h23565 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + source_id__h23673 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + source_id__h23781 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + source_id__h23889 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + source_id__h23997 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + source_id__h24105 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + source_id__h24213 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + source_id__h24321 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + source_id__h24429 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + source_id__h24537 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + source_id__h24645 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + source_id__h24753 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + source_id__h24861 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h15030 = - { source_id__h17021 <= 10'd16 && + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; + assign v_ip__h15089 = + { source_id__h17080 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164, - source_id__h17128 <= 10'd16 && + source_id__h17187 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168, - source_id__h17201 <= 10'd16 && + source_id__h17260 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d173, - source_id__h17274 <= 10'd16 && + source_id__h17333 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d177, - source_id__h17347 <= 10'd16 && + source_id__h17406 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d182, - source_id__h17420 <= 10'd16 && + source_id__h17479 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d186, - source_id__h17493 <= 10'd16 && + source_id__h17552 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d191, - source_id__h17566 <= 10'd16 && + source_id__h17625 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d195, - source_id__h17639 <= 10'd16 && + source_id__h17698 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d200, - source_id__h17712 <= 10'd16 && + source_id__h17771 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d204, - source_id__h17785 <= 10'd16 && + source_id__h17844 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d209, - source_id__h17858 <= 10'd16 && + source_id__h17917 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d213, - source_id__h17931 <= 10'd16 && + source_id__h17990 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d218, - source_id__h18004 <= 10'd16 && + source_id__h18063 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d222, - source_id__h18077 <= 10'd16 && + source_id__h18136 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d227, - source_id__h18150 <= 10'd16 && + source_id__h18209 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d231, - source_id__h18223 <= 10'd16 && + source_id__h18282 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d236, - source_id__h18296 <= 10'd16 && + source_id__h18355 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d240, - source_id__h18369 <= 10'd16 && + source_id__h18428 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d245, - source_id__h18442 <= 10'd16 && + source_id__h18501 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d249, - source_id__h18515 <= 10'd16 && + source_id__h18574 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d254, - source_id__h18588 <= 10'd16 && + source_id__h18647 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d258, - source_id__h18661 <= 10'd16 && + source_id__h18720 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d263, - source_id__h18734 <= 10'd16 && + source_id__h18793 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d267, - source_id__h18807 <= 10'd16 && + source_id__h18866 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d272, - source_id__h18880 <= 10'd16 && + source_id__h18939 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d276, - source_id__h18953 <= 10'd16 && + source_id__h19012 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d281, - source_id__h19026 <= 10'd16 && + source_id__h19085 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d285, - source_id__h19099 <= 10'd16 && + source_id__h19158 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d290, - source_id__h19172 <= 10'd16 && + source_id__h19231 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d294, - source_id__h19245 <= 10'd16 && + source_id__h19304 <= 10'd16 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d299, m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d301 } ; - assign wdata32__h28409 = - (addr_offset__h28408[2:0] == 3'd4) ? + assign wdata32__h28468 = + (addr_offset__h28467[2:0] == 3'd4) ? m_slave_xactor_shim_wff$D_OUT[72:41] : m_slave_xactor_shim_wff$D_OUT[40:9] ; - assign x__h25030 = - { addr_offset__h14540[31:16], 4'd0, addr_offset__h14540[11:0] } ; - assign x__h27766 = - (addr_offset__h14540[2:0] == 3'd4) ? - rdata___1__h27806 : - rdata__h27563 ; - assign x__h68623 = - { addr_offset__h28408[31:16], 4'd0, addr_offset__h28408[11:0] } ; - assign y_avValue_fst__h27455 = (x__h25371 == 5'd0) ? v__h26816 : 64'd0 ; - assign y_avValue_fst__h27476 = + assign x__h25089 = + { addr_offset__h14599[31:16], 4'd0, addr_offset__h14599[11:0] } ; + assign x__h27825 = + (addr_offset__h14599[2:0] == 3'd4) ? + rdata___1__h27865 : + rdata__h27622 ; + assign x__h68682 = + { addr_offset__h28467[31:16], 4'd0, addr_offset__h28467[11:0] } ; + assign y_avValue_fst__h27514 = (x__h25430 == 5'd0) ? v__h26875 : 64'd0 ; + assign y_avValue_fst__h27535 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - y_avValue_fst__h27455 : + y_avValue_fst__h27514 : 64'd0 ; - assign y_avValue_fst__h27488 = + assign y_avValue_fst__h27547 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - v__h25119 : + v__h25178 : 64'd0 ; - assign y_avValue_fst__h27504 = + assign y_avValue_fst__h27563 = (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d308) ? - v__h19501 : + v__h19560 : 64'd0 ; - assign y_avValue_fst__h27520 = + assign y_avValue_fst__h27579 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d137 ? - v__h15027 : + v__h15086 : 64'd0 ; - assign y_avValue_fst__h27525 = + assign y_avValue_fst__h27584 = (!m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d306) ? - y_avValue_fst__h27504 : - y_avValue_fst__h27509 ; - assign y_avValue_fst__h27536 = - (addr_offset__h14540[11:2] != 10'd0 && + y_avValue_fst__h27563 : + y_avValue_fst__h27568 ; + assign y_avValue_fst__h27595 = + (addr_offset__h14599[11:2] != 10'd0 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d106) ? - v__h14777 : + v__h14836 : 64'd0 ; - assign y_avValue_fst__h27541 = + assign y_avValue_fst__h27600 = (!m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d134) ? - y_avValue_fst__h27520 : - y_avValue_fst__h27525 ; - assign y_avValue_fst__h27555 = + y_avValue_fst__h27579 : + y_avValue_fst__h27584 ; + assign y_avValue_fst__h27614 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 ? - y_avValue_fst__h27536 : - y_avValue_fst__h27541 ; - always@(addr_offset__h14540 or + y_avValue_fst__h27595 : + y_avValue_fst__h27600 ; + always@(addr_offset__h14599 or m_vrg_source_prio_0 or m_vrg_source_prio_1 or m_vrg_source_prio_2 or @@ -16968,55 +16973,55 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_prio_14 or m_vrg_source_prio_15 or m_vrg_source_prio_16) begin - case (addr_offset__h14540[11:2]) - 10'd0: x__h14848 = m_vrg_source_prio_0; - 10'd1: x__h14848 = m_vrg_source_prio_1; - 10'd2: x__h14848 = m_vrg_source_prio_2; - 10'd3: x__h14848 = m_vrg_source_prio_3; - 10'd4: x__h14848 = m_vrg_source_prio_4; - 10'd5: x__h14848 = m_vrg_source_prio_5; - 10'd6: x__h14848 = m_vrg_source_prio_6; - 10'd7: x__h14848 = m_vrg_source_prio_7; - 10'd8: x__h14848 = m_vrg_source_prio_8; - 10'd9: x__h14848 = m_vrg_source_prio_9; - 10'd10: x__h14848 = m_vrg_source_prio_10; - 10'd11: x__h14848 = m_vrg_source_prio_11; - 10'd12: x__h14848 = m_vrg_source_prio_12; - 10'd13: x__h14848 = m_vrg_source_prio_13; - 10'd14: x__h14848 = m_vrg_source_prio_14; - 10'd15: x__h14848 = m_vrg_source_prio_15; - 10'd16: x__h14848 = m_vrg_source_prio_16; - default: x__h14848 = 3'b010 /* unspecified value */ ; + case (addr_offset__h14599[11:2]) + 10'd0: x__h14907 = m_vrg_source_prio_0; + 10'd1: x__h14907 = m_vrg_source_prio_1; + 10'd2: x__h14907 = m_vrg_source_prio_2; + 10'd3: x__h14907 = m_vrg_source_prio_3; + 10'd4: x__h14907 = m_vrg_source_prio_4; + 10'd5: x__h14907 = m_vrg_source_prio_5; + 10'd6: x__h14907 = m_vrg_source_prio_6; + 10'd7: x__h14907 = m_vrg_source_prio_7; + 10'd8: x__h14907 = m_vrg_source_prio_8; + 10'd9: x__h14907 = m_vrg_source_prio_9; + 10'd10: x__h14907 = m_vrg_source_prio_10; + 10'd11: x__h14907 = m_vrg_source_prio_11; + 10'd12: x__h14907 = m_vrg_source_prio_12; + 10'd13: x__h14907 = m_vrg_source_prio_13; + 10'd14: x__h14907 = m_vrg_source_prio_14; + 10'd15: x__h14907 = m_vrg_source_prio_15; + 10'd16: x__h14907 = m_vrg_source_prio_16; + default: x__h14907 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or m_vrg_target_threshold_0 or m_vrg_target_threshold_1) begin - case (addr_offset__h14540[16:12]) - 5'd0: x__h25190 = m_vrg_target_threshold_0; - 5'd1: x__h25190 = m_vrg_target_threshold_1; - default: x__h25190 = 3'b010 /* unspecified value */ ; + case (addr_offset__h14599[16:12]) + 5'd0: x__h25249 = m_vrg_target_threshold_0; + 5'd1: x__h25249 = m_vrg_target_threshold_1; + default: x__h25249 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h14540[16:12]) - 5'd0: x__h25371 = m_vrg_servicing_source_0; - 5'd1: x__h25371 = m_vrg_servicing_source_1; - default: x__h25371 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h14599[16:12]) + 5'd0: x__h25430 = m_vrg_servicing_source_0; + 5'd1: x__h25430 = m_vrg_servicing_source_1; + default: x__h25430 = 5'b01010 /* unspecified value */ ; endcase end - always@(addr_offset__h28408 or + always@(addr_offset__h28467 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h28408[16:12]) - 5'd0: x__h69004 = m_vrg_servicing_source_0; - 5'd1: x__h69004 = m_vrg_servicing_source_1; - default: x__h69004 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h28467[16:12]) + 5'd0: x__h69063 = m_vrg_servicing_source_0; + 5'd1: x__h69063 = m_vrg_servicing_source_1; + default: x__h69063 = 5'b01010 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17033,7 +17038,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d301 = m_vrg_source_ip_0; @@ -17089,7 +17094,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21670 or + always@(source_id__h21729 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17106,7 +17111,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21670) + case (source_id__h21729) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362 = m_vvrg_ie_0_0; @@ -17162,7 +17167,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21670 or + always@(source_id__h21729 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17179,7 +17184,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21670) + case (source_id__h21729) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363 = m_vvrg_ie_1_0; @@ -17235,7 +17240,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21494 or + always@(source_id__h21553 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17252,7 +17257,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21494) + case (source_id__h21553) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337 = m_vvrg_ie_0_0; @@ -17308,7 +17313,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21494 or + always@(source_id__h21553 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17325,7 +17330,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21494) + case (source_id__h21553) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356 = m_vvrg_ie_1_0; @@ -17381,7 +17386,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21778 or + always@(source_id__h21837 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17398,7 +17403,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21778) + case (source_id__h21837) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370 = m_vvrg_ie_0_0; @@ -17454,7 +17459,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17021 or + always@(source_id__h17080 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17471,7 +17476,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17021) + case (source_id__h17080) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d164 = m_vrg_source_ip_0; @@ -17527,7 +17532,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21778 or + always@(source_id__h21837 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17544,7 +17549,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21778) + case (source_id__h21837) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371 = m_vvrg_ie_1_0; @@ -17600,7 +17605,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21886 or + always@(source_id__h21945 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17617,7 +17622,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21886) + case (source_id__h21945) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378 = m_vvrg_ie_1_0; @@ -17673,7 +17678,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21886 or + always@(source_id__h21945 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17690,7 +17695,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21886) + case (source_id__h21945) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377 = m_vvrg_ie_0_0; @@ -17746,7 +17751,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17128 or + always@(source_id__h17187 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17763,7 +17768,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17128) + case (source_id__h17187) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d168 = m_vrg_source_ip_0; @@ -17819,7 +17824,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21994 or + always@(source_id__h22053 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17836,7 +17841,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21994) + case (source_id__h22053) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385 = m_vvrg_ie_0_0; @@ -17892,7 +17897,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21994 or + always@(source_id__h22053 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17909,7 +17914,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21994) + case (source_id__h22053) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386 = m_vvrg_ie_1_0; @@ -17965,7 +17970,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17201 or + always@(source_id__h17260 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17982,7 +17987,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17201) + case (source_id__h17260) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d173 = m_vrg_source_ip_0; @@ -18038,7 +18043,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22102 or + always@(source_id__h22161 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18055,7 +18060,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22102) + case (source_id__h22161) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392 = m_vvrg_ie_0_0; @@ -18111,7 +18116,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22102 or + always@(source_id__h22161 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18128,7 +18133,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22102) + case (source_id__h22161) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393 = m_vvrg_ie_1_0; @@ -18184,7 +18189,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17274 or + always@(source_id__h17333 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18201,7 +18206,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17274) + case (source_id__h17333) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d177 = m_vrg_source_ip_0; @@ -18257,7 +18262,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22210 or + always@(source_id__h22269 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18274,7 +18279,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22210) + case (source_id__h22269) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400 = m_vvrg_ie_0_0; @@ -18330,7 +18335,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22210 or + always@(source_id__h22269 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18347,7 +18352,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22210) + case (source_id__h22269) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401 = m_vvrg_ie_1_0; @@ -18403,7 +18408,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22318 or + always@(source_id__h22377 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18420,7 +18425,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22318) + case (source_id__h22377) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407 = m_vvrg_ie_0_0; @@ -18476,7 +18481,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17347 or + always@(source_id__h17406 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18493,7 +18498,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17347) + case (source_id__h17406) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d182 = m_vrg_source_ip_0; @@ -18549,7 +18554,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22318 or + always@(source_id__h22377 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18566,7 +18571,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22318) + case (source_id__h22377) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408 = m_vvrg_ie_1_0; @@ -18622,7 +18627,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17420 or + always@(source_id__h17479 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18639,7 +18644,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17420) + case (source_id__h17479) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d186 = m_vrg_source_ip_0; @@ -18695,7 +18700,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22426 or + always@(source_id__h22485 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18712,7 +18717,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22426) + case (source_id__h22485) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415 = m_vvrg_ie_0_0; @@ -18768,7 +18773,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22426 or + always@(source_id__h22485 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18785,7 +18790,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22426) + case (source_id__h22485) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416 = m_vvrg_ie_1_0; @@ -18841,7 +18846,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22534 or + always@(source_id__h22593 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18858,7 +18863,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22534) + case (source_id__h22593) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422 = m_vvrg_ie_0_0; @@ -18914,7 +18919,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17493 or + always@(source_id__h17552 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18931,7 +18936,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17493) + case (source_id__h17552) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d191 = m_vrg_source_ip_0; @@ -18987,7 +18992,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22534 or + always@(source_id__h22593 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19004,7 +19009,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22534) + case (source_id__h22593) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423 = m_vvrg_ie_1_0; @@ -19060,7 +19065,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17566 or + always@(source_id__h17625 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19077,7 +19082,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17566) + case (source_id__h17625) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d195 = m_vrg_source_ip_0; @@ -19133,7 +19138,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22642 or + always@(source_id__h22701 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19150,7 +19155,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22642) + case (source_id__h22701) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431 = m_vvrg_ie_1_0; @@ -19206,7 +19211,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22642 or + always@(source_id__h22701 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19223,7 +19228,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22642) + case (source_id__h22701) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430 = m_vvrg_ie_0_0; @@ -19279,7 +19284,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22750 or + always@(source_id__h22809 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19296,7 +19301,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22750) + case (source_id__h22809) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437 = m_vvrg_ie_0_0; @@ -19352,7 +19357,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17639 or + always@(source_id__h17698 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19369,7 +19374,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17639) + case (source_id__h17698) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d200 = m_vrg_source_ip_0; @@ -19425,7 +19430,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22750 or + always@(source_id__h22809 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19442,7 +19447,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22750) + case (source_id__h22809) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438 = m_vvrg_ie_1_0; @@ -19498,7 +19503,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17712 or + always@(source_id__h17771 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19515,7 +19520,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17712) + case (source_id__h17771) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d204 = m_vrg_source_ip_0; @@ -19571,7 +19576,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22858 or + always@(source_id__h22917 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19588,7 +19593,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22858) + case (source_id__h22917) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445 = m_vvrg_ie_0_0; @@ -19644,7 +19649,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22858 or + always@(source_id__h22917 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19661,7 +19666,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22858) + case (source_id__h22917) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446 = m_vvrg_ie_1_0; @@ -19717,7 +19722,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17785 or + always@(source_id__h17844 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19734,7 +19739,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17785) + case (source_id__h17844) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d209 = m_vrg_source_ip_0; @@ -19790,7 +19795,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22966 or + always@(source_id__h23025 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19807,7 +19812,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22966) + case (source_id__h23025) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452 = m_vvrg_ie_0_0; @@ -19863,7 +19868,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22966 or + always@(source_id__h23025 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19880,7 +19885,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22966) + case (source_id__h23025) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453 = m_vvrg_ie_1_0; @@ -19936,7 +19941,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18442 or + always@(source_id__h18501 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19953,7 +19958,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18442) + case (source_id__h18501) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d249 = m_vrg_source_ip_0; @@ -20009,7 +20014,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17858 or + always@(source_id__h17917 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20026,7 +20031,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17858) + case (source_id__h17917) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d213 = m_vrg_source_ip_0; @@ -20082,7 +20087,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23074 or + always@(source_id__h23133 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20099,7 +20104,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23074) + case (source_id__h23133) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460 = m_vvrg_ie_0_0; @@ -20155,7 +20160,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23074 or + always@(source_id__h23133 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20172,7 +20177,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23074) + case (source_id__h23133) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461 = m_vvrg_ie_1_0; @@ -20228,7 +20233,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23182 or + always@(source_id__h23241 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20245,7 +20250,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23182) + case (source_id__h23241) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467 = m_vvrg_ie_0_0; @@ -20301,7 +20306,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17931 or + always@(source_id__h17990 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20318,7 +20323,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17931) + case (source_id__h17990) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d218 = m_vrg_source_ip_0; @@ -20374,7 +20379,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23182 or + always@(source_id__h23241 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20391,7 +20396,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23182) + case (source_id__h23241) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468 = m_vvrg_ie_1_0; @@ -20447,7 +20452,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18004 or + always@(source_id__h18063 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20464,7 +20469,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18004) + case (source_id__h18063) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d222 = m_vrg_source_ip_0; @@ -20520,7 +20525,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23290 or + always@(source_id__h23349 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20537,7 +20542,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23290) + case (source_id__h23349) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475 = m_vvrg_ie_0_0; @@ -20593,7 +20598,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23290 or + always@(source_id__h23349 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20610,7 +20615,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23290) + case (source_id__h23349) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476 = m_vvrg_ie_1_0; @@ -20666,7 +20671,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23398 or + always@(source_id__h23457 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20683,7 +20688,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23398) + case (source_id__h23457) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482 = m_vvrg_ie_0_0; @@ -20739,7 +20744,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18077 or + always@(source_id__h18136 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20756,7 +20761,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18077) + case (source_id__h18136) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d227 = m_vrg_source_ip_0; @@ -20812,7 +20817,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23398 or + always@(source_id__h23457 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20829,7 +20834,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23398) + case (source_id__h23457) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483 = m_vvrg_ie_1_0; @@ -20885,7 +20890,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18150 or + always@(source_id__h18209 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20902,7 +20907,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18150) + case (source_id__h18209) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d231 = m_vrg_source_ip_0; @@ -20958,7 +20963,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23506 or + always@(source_id__h23565 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20975,7 +20980,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23506) + case (source_id__h23565) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491 = m_vvrg_ie_1_0; @@ -21031,7 +21036,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23506 or + always@(source_id__h23565 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21048,7 +21053,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23506) + case (source_id__h23565) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490 = m_vvrg_ie_0_0; @@ -21104,7 +21109,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23614 or + always@(source_id__h23673 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21121,7 +21126,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23614) + case (source_id__h23673) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497 = m_vvrg_ie_0_0; @@ -21177,7 +21182,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18223 or + always@(source_id__h18282 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21194,7 +21199,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18223) + case (source_id__h18282) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d236 = m_vrg_source_ip_0; @@ -21250,7 +21255,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23614 or + always@(source_id__h23673 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21267,7 +21272,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23614) + case (source_id__h23673) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498 = m_vvrg_ie_1_0; @@ -21323,7 +21328,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18296 or + always@(source_id__h18355 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21340,7 +21345,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18296) + case (source_id__h18355) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d240 = m_vrg_source_ip_0; @@ -21396,7 +21401,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23722 or + always@(source_id__h23781 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21413,7 +21418,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23722) + case (source_id__h23781) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505 = m_vvrg_ie_0_0; @@ -21469,7 +21474,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23722 or + always@(source_id__h23781 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21486,7 +21491,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23722) + case (source_id__h23781) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506 = m_vvrg_ie_1_0; @@ -21542,7 +21547,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23830 or + always@(source_id__h23889 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21559,7 +21564,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23830) + case (source_id__h23889) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512 = m_vvrg_ie_0_0; @@ -21615,7 +21620,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18369 or + always@(source_id__h18428 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21632,7 +21637,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18369) + case (source_id__h18428) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d245 = m_vrg_source_ip_0; @@ -21688,7 +21693,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23830 or + always@(source_id__h23889 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21705,7 +21710,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23830) + case (source_id__h23889) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513 = m_vvrg_ie_1_0; @@ -21761,7 +21766,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23938 or + always@(source_id__h23997 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21778,7 +21783,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23938) + case (source_id__h23997) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520 = m_vvrg_ie_0_0; @@ -21834,7 +21839,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23938 or + always@(source_id__h23997 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21851,7 +21856,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23938) + case (source_id__h23997) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521 = m_vvrg_ie_1_0; @@ -21907,7 +21912,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24046 or + always@(source_id__h24105 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21924,7 +21929,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24046) + case (source_id__h24105) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527 = m_vvrg_ie_0_0; @@ -21980,7 +21985,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24046 or + always@(source_id__h24105 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21997,7 +22002,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24046) + case (source_id__h24105) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528 = m_vvrg_ie_1_0; @@ -22053,7 +22058,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18588 or + always@(source_id__h18647 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22070,7 +22075,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18588) + case (source_id__h18647) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d258 = m_vrg_source_ip_0; @@ -22126,7 +22131,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18515 or + always@(source_id__h18574 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22143,7 +22148,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18515) + case (source_id__h18574) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d254 = m_vrg_source_ip_0; @@ -22199,7 +22204,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24154 or + always@(source_id__h24213 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22216,7 +22221,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24154) + case (source_id__h24213) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535 = m_vvrg_ie_0_0; @@ -22272,7 +22277,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24154 or + always@(source_id__h24213 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22289,7 +22294,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24154) + case (source_id__h24213) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536 = m_vvrg_ie_1_0; @@ -22345,7 +22350,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24262 or + always@(source_id__h24321 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22362,7 +22367,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24262) + case (source_id__h24321) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542 = m_vvrg_ie_0_0; @@ -22418,7 +22423,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24262 or + always@(source_id__h24321 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22435,7 +22440,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24262) + case (source_id__h24321) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543 = m_vvrg_ie_1_0; @@ -22491,7 +22496,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18734 or + always@(source_id__h18793 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22508,7 +22513,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18734) + case (source_id__h18793) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d267 = m_vrg_source_ip_0; @@ -22564,7 +22569,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18661 or + always@(source_id__h18720 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22581,7 +22586,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18661) + case (source_id__h18720) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d263 = m_vrg_source_ip_0; @@ -22637,7 +22642,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24370 or + always@(source_id__h24429 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22654,7 +22659,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24370) + case (source_id__h24429) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550 = m_vvrg_ie_0_0; @@ -22710,7 +22715,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24478 or + always@(source_id__h24537 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22727,7 +22732,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24478) + case (source_id__h24537) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557 = m_vvrg_ie_0_0; @@ -22783,7 +22788,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24370 or + always@(source_id__h24429 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22800,7 +22805,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24370) + case (source_id__h24429) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551 = m_vvrg_ie_1_0; @@ -22856,7 +22861,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24478 or + always@(source_id__h24537 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22873,7 +22878,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24478) + case (source_id__h24537) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558 = m_vvrg_ie_1_0; @@ -22929,7 +22934,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18880 or + always@(source_id__h18939 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22946,7 +22951,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18880) + case (source_id__h18939) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d276 = m_vrg_source_ip_0; @@ -23002,7 +23007,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18807 or + always@(source_id__h18866 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23019,7 +23024,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18807) + case (source_id__h18866) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d272 = m_vrg_source_ip_0; @@ -23075,7 +23080,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24586 or + always@(source_id__h24645 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23092,7 +23097,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24586) + case (source_id__h24645) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565 = m_vvrg_ie_0_0; @@ -23148,7 +23153,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24586 or + always@(source_id__h24645 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23165,7 +23170,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24586) + case (source_id__h24645) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566 = m_vvrg_ie_1_0; @@ -23221,7 +23226,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24694 or + always@(source_id__h24753 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23238,7 +23243,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24694) + case (source_id__h24753) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572 = m_vvrg_ie_0_0; @@ -23294,7 +23299,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24694 or + always@(source_id__h24753 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23311,7 +23316,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24694) + case (source_id__h24753) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573 = m_vvrg_ie_1_0; @@ -23367,7 +23372,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h18953 or + always@(source_id__h19012 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23384,7 +23389,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h18953) + case (source_id__h19012) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d281 = m_vrg_source_ip_0; @@ -23440,7 +23445,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19026 or + always@(source_id__h19085 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23457,7 +23462,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19026) + case (source_id__h19085) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d285 = m_vrg_source_ip_0; @@ -23513,7 +23518,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24802 or + always@(source_id__h24861 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23530,7 +23535,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h24802) + case (source_id__h24861) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580 = m_vvrg_ie_0_0; @@ -23586,7 +23591,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h24802 or + always@(source_id__h24861 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23603,7 +23608,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h24802) + case (source_id__h24861) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581 = m_vvrg_ie_1_0; @@ -23659,7 +23664,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23676,7 +23681,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585 = m_vvrg_ie_0_0; @@ -23732,7 +23737,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h14985 or + always@(source_id_base__h15044 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23749,7 +23754,7 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id_base__h14985) + case (source_id_base__h15044) 10'd0: SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586 = m_vvrg_ie_1_0; @@ -23805,487 +23810,487 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d337; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d356; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d362; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d363; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d370; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d371; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d377; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d378; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d385; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d386; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d392; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d393; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d400; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d401; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d407; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d408; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d415; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d416; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d422; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d423; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d430; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d431; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d437; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d438; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d445; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d446; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d452; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d453; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d460; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d461; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d467; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d468; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d475; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d476; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d482; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d483; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d490; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d491; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d497; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d498; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d505; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d506; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d512; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d513; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d520; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d521; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d527; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d528; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d535; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d536; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d542; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d543; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d550; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d551; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d557; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d558; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d565; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d566; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d572; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d573; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d580; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d581; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or + always@(addr_offset__h14599 or SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585 or SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586) begin - case (addr_offset__h14540[11:7]) + case (addr_offset__h14599[11:7]) 5'd0: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = SEL_ARR_m_vvrg_ie_0_0_19_m_vvrg_ie_0_1_20_m_vv_ETC___d585; 5'd1: - CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = SEL_ARR_m_vvrg_ie_1_0_38_m_vvrg_ie_1_1_39_m_vv_ETC___d586; - default: CASE_addr_offset4540_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + default: CASE_addr_offset4599_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19172 or + always@(source_id__h19231 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24302,7 +24307,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19172) + case (source_id__h19231) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d294 = m_vrg_source_ip_0; @@ -24358,7 +24363,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19099 or + always@(source_id__h19158 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24375,7 +24380,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19099) + case (source_id__h19158) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d290 = m_vrg_source_ip_0; @@ -24431,7 +24436,7 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h19245 or + always@(source_id__h19304 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24448,7 +24453,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h19245) + case (source_id__h19304) 10'd0: SEL_ARR_m_vrg_source_ip_0_read__46_m_vrg_sourc_ETC___d299 = m_vrg_source_ip_0; @@ -24504,223 +24509,223 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) + always@(addr_offset__h14599 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = m_vvrg_ie_0_1; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = m_vvrg_ie_1_1; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) + always@(addr_offset__h14599 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_0_2; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_1_2; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) + always@(addr_offset__h14599 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_0_3; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_1_3; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) + always@(addr_offset__h14599 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_0_4; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_1_4; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) + always@(addr_offset__h14599 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_0_5; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_1_5; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) + always@(addr_offset__h14599 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_0_6; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_1_6; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) + always@(addr_offset__h14599 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_0_7; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_1_7; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) + always@(addr_offset__h14599 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_0_8; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_1_8; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) + always@(addr_offset__h14599 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_0_9; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_1_9; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) + always@(addr_offset__h14599 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_0_10; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_1_10; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) + always@(addr_offset__h14599 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_0_11; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_1_11; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) + always@(addr_offset__h14599 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_0_12; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_1_12; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) + always@(addr_offset__h14599 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_0_13; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_1_13; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) + always@(addr_offset__h14599 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_0_14; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_1_14; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) + always@(addr_offset__h14599 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_0_15; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_1_15; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h14540 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) + always@(addr_offset__h14599 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) begin - case (addr_offset__h14540[16:12]) + case (addr_offset__h14599[16:12]) 5'd0: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_0_16; 5'd1: - CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_1_16; - default: CASE_addr_offset4540_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + default: CASE_addr_offset4599_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h25030 or y_avValue_fst__h27488 or y_avValue_fst__h27476) + always@(x__h25089 or y_avValue_fst__h27547 or y_avValue_fst__h27535) begin - case (x__h25030) - 32'h00200000: y_avValue_fst__h27509 = y_avValue_fst__h27488; - 32'h00200004: y_avValue_fst__h27509 = y_avValue_fst__h27476; - default: y_avValue_fst__h27509 = 64'd0; + case (x__h25089) + 32'h00200000: y_avValue_fst__h27568 = y_avValue_fst__h27547; + 32'h00200004: y_avValue_fst__h27568 = y_avValue_fst__h27535; + default: y_avValue_fst__h27568 = 64'd0; endcase end - always@(source_id__h68952 or + always@(source_id__h69011 or m_vrg_source_busy_0 or m_vrg_source_busy_1 or m_vrg_source_busy_2 or @@ -24738,7 +24743,7 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_busy_14 or m_vrg_source_busy_15 or m_vrg_source_busy_16) begin - case (source_id__h68952) + case (source_id__h69011) 10'd0: SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 = m_vrg_source_busy_0; @@ -24794,42 +24799,42 @@ module mkPLIC_16_2_7(CLK, 1'b0 /* unspecified value */ ; endcase end - always@(x__h25030 or + always@(x__h25089 or m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 or - x__h25371) + x__h25430) begin - case (x__h25030) + case (x__h25089) 32'h00200000: - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? 2'd0 : 2'd2; 32'h00200004: - CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = + CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d598 ? - ((x__h25371 == 5'd0) ? 2'd0 : 2'd2) : + ((x__h25430 == 5'd0) ? 2'd0 : 2'd2) : 2'd2; - default: CASE_x5030_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = 2'd2; + default: CASE_x5089_0x200000_IF_m_slave_xactor_shim_arf_ETC__q49 = 2'd2; endcase end - always@(x__h68623 or + always@(x__h68682 or m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 or SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029) begin - case (x__h68623) + case (x__h68682) 32'h00200000: - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ? 2'd0 : 2'd2; 32'h00200004: - CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = + CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d2990 ? (SEL_ARR_m_vrg_source_busy_0_011_m_vrg_source_b_ETC___d3029 ? 2'd0 : 2'd2) : 2'd2; - default: CASE_x8623_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = 2'd2; + default: CASE_x8682_0x200000_IF_m_slave_xactor_shim_awf_ETC__q50 = 2'd2; endcase end @@ -25421,9 +25426,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h72910, + a__h72969, m_vrg_target_threshold_0, - b__h72911, + b__h72970, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25464,249 +25469,249 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h74915, + a__h74974, m_vrg_target_threshold_1, - b__h74916, + b__h74975, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368) + if (NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371) begin - v__h77333 = $stime; + v__h77354 = $stime; #0; end - v__h77327 = v__h77333 / 32'd10; + v__h77348 = v__h77354 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_012_364_AND_NOT_m_cfg__ETC___d3368) + if (NOT_m_vrg_source_busy_1_012_367_AND_NOT_m_cfg__ETC___d3371) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77327, + v__h77348, $signed(32'd1), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375) + if (NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378) begin - v__h77531 = $stime; + v__h77552 = $stime; #0; end - v__h77525 = v__h77531 / 32'd10; + v__h77546 = v__h77552 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_013_371_AND_NOT_m_cfg__ETC___d3375) + if (NOT_m_vrg_source_busy_2_013_374_AND_NOT_m_cfg__ETC___d3378) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77525, + v__h77546, $signed(32'd2), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383) + if (NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386) begin - v__h77729 = $stime; + v__h77750 = $stime; #0; end - v__h77723 = v__h77729 / 32'd10; + v__h77744 = v__h77750 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_014_379_AND_NOT_m_cfg__ETC___d3383) + if (NOT_m_vrg_source_busy_3_014_382_AND_NOT_m_cfg__ETC___d3386) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77723, + v__h77744, $signed(32'd3), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391) + if (NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394) begin - v__h77927 = $stime; + v__h77948 = $stime; #0; end - v__h77921 = v__h77927 / 32'd10; + v__h77942 = v__h77948 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_015_387_AND_NOT_m_cfg__ETC___d3391) + if (NOT_m_vrg_source_busy_4_015_390_AND_NOT_m_cfg__ETC___d3394) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77921, + v__h77942, $signed(32'd4), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399) + if (NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402) begin - v__h78125 = $stime; + v__h78146 = $stime; #0; end - v__h78119 = v__h78125 / 32'd10; + v__h78140 = v__h78146 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_016_395_AND_NOT_m_cfg__ETC___d3399) + if (NOT_m_vrg_source_busy_5_016_398_AND_NOT_m_cfg__ETC___d3402) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78119, + v__h78140, $signed(32'd5), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407) + if (NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410) begin - v__h78323 = $stime; + v__h78344 = $stime; #0; end - v__h78317 = v__h78323 / 32'd10; + v__h78338 = v__h78344 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_017_403_AND_NOT_m_cfg__ETC___d3407) + if (NOT_m_vrg_source_busy_6_017_406_AND_NOT_m_cfg__ETC___d3410) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78317, + v__h78338, $signed(32'd6), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415) + if (NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418) begin - v__h78521 = $stime; + v__h78542 = $stime; #0; end - v__h78515 = v__h78521 / 32'd10; + v__h78536 = v__h78542 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_018_411_AND_NOT_m_cfg__ETC___d3415) + if (NOT_m_vrg_source_busy_7_018_414_AND_NOT_m_cfg__ETC___d3418) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78515, + v__h78536, $signed(32'd7), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423) + if (NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426) begin - v__h78719 = $stime; + v__h78740 = $stime; #0; end - v__h78713 = v__h78719 / 32'd10; + v__h78734 = v__h78740 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_019_419_AND_NOT_m_cfg__ETC___d3423) + if (NOT_m_vrg_source_busy_8_019_422_AND_NOT_m_cfg__ETC___d3426) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78713, + v__h78734, $signed(32'd8), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431) + if (NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434) begin - v__h78917 = $stime; + v__h78938 = $stime; #0; end - v__h78911 = v__h78917 / 32'd10; + v__h78932 = v__h78938 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_020_427_AND_NOT_m_cfg__ETC___d3431) + if (NOT_m_vrg_source_busy_9_020_430_AND_NOT_m_cfg__ETC___d3434) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78911, + v__h78932, $signed(32'd9), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439) + if (NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442) begin - v__h79115 = $stime; + v__h79136 = $stime; #0; end - v__h79109 = v__h79115 / 32'd10; + v__h79130 = v__h79136 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_021_435_AND_NOT_m_cfg_ETC___d3439) + if (NOT_m_vrg_source_busy_10_021_438_AND_NOT_m_cfg_ETC___d3442) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79109, + v__h79130, $signed(32'd10), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447) + if (NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450) begin - v__h79313 = $stime; + v__h79334 = $stime; #0; end - v__h79307 = v__h79313 / 32'd10; + v__h79328 = v__h79334 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_022_443_AND_NOT_m_cfg_ETC___d3447) + if (NOT_m_vrg_source_busy_11_022_446_AND_NOT_m_cfg_ETC___d3450) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79307, + v__h79328, $signed(32'd11), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455) + if (NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458) begin - v__h79511 = $stime; + v__h79532 = $stime; #0; end - v__h79505 = v__h79511 / 32'd10; + v__h79526 = v__h79532 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_023_451_AND_NOT_m_cfg_ETC___d3455) + if (NOT_m_vrg_source_busy_12_023_454_AND_NOT_m_cfg_ETC___d3458) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79505, + v__h79526, $signed(32'd12), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463) + if (NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466) begin - v__h79709 = $stime; + v__h79730 = $stime; #0; end - v__h79703 = v__h79709 / 32'd10; + v__h79724 = v__h79730 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_024_459_AND_NOT_m_cfg_ETC___d3463) + if (NOT_m_vrg_source_busy_13_024_462_AND_NOT_m_cfg_ETC___d3466) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79703, + v__h79724, $signed(32'd13), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471) + if (NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474) begin - v__h79907 = $stime; + v__h79928 = $stime; #0; end - v__h79901 = v__h79907 / 32'd10; + v__h79922 = v__h79928 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_025_467_AND_NOT_m_cfg_ETC___d3471) + if (NOT_m_vrg_source_busy_14_025_470_AND_NOT_m_cfg_ETC___d3474) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h79901, + v__h79922, $signed(32'd14), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479) + if (NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482) begin - v__h80105 = $stime; + v__h80126 = $stime; #0; end - v__h80099 = v__h80105 / 32'd10; + v__h80120 = v__h80126 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_026_475_AND_NOT_m_cfg_ETC___d3479) + if (NOT_m_vrg_source_busy_15_026_478_AND_NOT_m_cfg_ETC___d3482) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h80099, + v__h80120, $signed(32'd15), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487) + if (NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490) begin - v__h80303 = $stime; + v__h80324 = $stime; #0; end - v__h80297 = v__h80303 / 32'd10; + v__h80318 = v__h80324 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_027_483_AND_NOT_m_cfg_ETC___d3487) + if (NOT_m_vrg_source_busy_16_027_486_AND_NOT_m_cfg_ETC___d3490) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h80297, + v__h80318, $signed(32'd16), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) begin - v__h7530 = $stime; + v__h7589 = $stime; #0; end - v__h7524 = v__h7530 / 32'd10; + v__h7583 = v__h7589 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h7524); + $display("%0d: PLIC.rl_reset", v__h7583); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h28194 = $stime; + v__h28253 = $stime; #0; end - v__h28188 = v__h28194 / 32'd10; + v__h28247 = v__h28253 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_wr_req", v__h28188); + $display("%0d: PLIC.rl_process_wr_req", v__h28247); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -25881,15 +25886,15 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) begin - v__h28448 = $stime; + v__h28507 = $stime; #0; end - v__h28442 = v__h28448 / 32'd10; + v__h28501 = v__h28507 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h28442); + v__h28501); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942) @@ -26065,101 +26070,101 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005) begin - v__h29372 = $stime; + v__h29431 = $stime; #0; end - v__h29366 = v__h29372 / 32'd10; + v__h29425 = v__h29431 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d1005) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h29366, - addr_offset__h28408[11:2], - wdata32__h28409); + v__h29425, + addr_offset__h28467[11:2], + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016) begin - v__h29558 = $stime; + v__h29617 = $stime; #0; end - v__h29552 = v__h29558 / 32'd10; + v__h29611 = v__h29617 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d1016) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h29552, - source_id_base__h29659); + v__h29611, + source_id_base__h29718); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980) begin - v__h68542 = $stime; + v__h68601 = $stime; #0; end - v__h68536 = v__h68542 / 32'd10; + v__h68595 = v__h68601 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d2980) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h68536, - addr_offset__h28408[11:7], - source_id_base__h29659, - wdata32__h28409); + v__h68595, + addr_offset__h28467[11:7], + source_id_base__h29718, + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004) begin - v__h68832 = $stime; + v__h68891 = $stime; #0; end - v__h68826 = v__h68832 / 32'd10; + v__h68885 = v__h68891 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3004) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h68826, - addr_offset__h28408[16:12], - wdata32__h28409); + v__h68885, + addr_offset__h28467[16:12], + wdata32__h28468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076) begin - v__h69364 = $stime; + v__h69423 = $stime; #0; end - v__h69358 = v__h69364 / 32'd10; + v__h69417 = v__h69423 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && !m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3076) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h69358, - addr_offset__h28408[16:12], - source_id__h68952); + v__h69417, + addr_offset__h28467[16:12], + source_id__h69011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) begin - v__h69450 = $stime; + v__h69509 = $stime; #0; end - v__h69444 = v__h69450 / 32'd10; + v__h69503 = v__h69509 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h69444); + v__h69503); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) $display(" Completion message from target %0d to source %0d", - addr_offset__h28408[16:12], - source_id__h68952); + addr_offset__h28467[16:12], + source_id__h69011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_slave_xactor_shim_awff_first__09_BITS_92_ETC___d3086) @@ -26169,16 +26174,16 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101)) begin - v__h69661 = $stime; + v__h69720 = $stime; #0; end - v__h69655 = v__h69661 / 32'd10; + v__h69714 = v__h69720 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || IF_m_slave_xactor_shim_awff_first__09_BITS_92__ETC___d3101)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h69655); + v__h69714); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && (m_slave_xactor_shim_awff_first__09_BITS_92_TO__ETC___d942 || @@ -26393,14 +26398,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h69907 = $stime; + v__h69966 = $stime; #0; end - v__h69901 = v__h69907 / 32'd10; + v__h69960 = v__h69966 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h69901); + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h69960); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -26620,23 +26625,23 @@ module mkPLIC_16_2_7(CLK, NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_m_slave_xactor_slvSynth_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h14375 = $stime; + v__h14434 = $stime; #0; end - v__h14369 = v__h14375 / 32'd10; + v__h14428 = v__h14434 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_rd_req:", v__h14369); + $display("%0d: PLIC.rl_process_rd_req:", v__h14428); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -26765,15 +26770,15 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) begin - v__h14590 = $stime; + v__h14649 = $stime; #0; end - v__h14584 = v__h14590 / 32'd10; + v__h14643 = v__h14649 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h14584); + v__h14643); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91) @@ -26903,107 +26908,107 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109) begin - v__h14818 = $stime; + v__h14877 = $stime; #0; end - v__h14812 = v__h14818 / 32'd10; + v__h14871 = v__h14877 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d109) $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h14812, - addr_offset__h14540[11:2], - v__h14777); + v__h14871, + addr_offset__h14599[11:2], + v__h14836); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d140) begin - v__h15069 = $stime; + v__h15128 = $stime; #0; end - v__h15063 = v__h15069 / 32'd10; + v__h15122 = v__h15128 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d140) $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h15063, - source_id_base__h14985, - v__h15027); + v__h15122, + source_id_base__h15044, + v__h15086); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d314) begin - v__h19543 = $stime; + v__h19602 = $stime; #0; end - v__h19537 = v__h19543 / 32'd10; + v__h19596 = v__h19602 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d314) $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h19537, - source_id_base__h14985, - v__h19501); + v__h19596, + source_id_base__h15044, + v__h19560); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d604) begin - v__h25160 = $stime; + v__h25219 = $stime; #0; end - v__h25154 = v__h25160 / 32'd10; + v__h25213 = v__h25219 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d604) $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h25154, - addr_offset__h14540[16:12], - v__h25119); + v__h25213, + addr_offset__h14599[16:12], + v__h25178); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810) begin - v__h27336 = $stime; + v__h27395 = $stime; #0; end - v__h27330 = v__h27336 / 32'd10; + v__h27389 = v__h27395 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 && !m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d102 && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d810) $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h27330, - addr_offset__h14540[16:12], - v__h26835); + v__h27389, + addr_offset__h14599[16:12], + v__h26894); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) begin - v__h25416 = $stime; + v__h25475 = $stime; #0; end - v__h25410 = v__h25416 / 32'd10; + v__h25469 = v__h25475 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h25410, - addr_offset__h14540[16:12]); + v__h25469, + addr_offset__h14599[16:12]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) - $display(" Still servicing interrupt from source %0d", x__h25371); + $display(" Still servicing interrupt from source %0d", x__h25430); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) $display(" Trying to claim service for source %0d", - max_id__h25318); + max_id__h25377); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_slave_xactor_shim_arff_first__4_BITS_92__ETC___d822) @@ -27013,16 +27018,16 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837)) begin - v__h27627 = $stime; + v__h27686 = $stime; #0; end - v__h27621 = v__h27627 / 32'd10; + v__h27680 = v__h27686 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || IF_m_slave_xactor_shim_arff_first__4_BITS_92_T_ETC___d837)) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h27621); + v__h27680); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && (m_slave_xactor_shim_arff_first__4_BITS_92_TO_2_ETC___d91 || @@ -27180,14 +27185,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) begin - v__h27865 = $stime; + v__h27924 = $stime; #0; end - v__h27859 = v__h27865 / 32'd10; + v__h27918 = v__h27924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $display("%0d: PLIC.rl_process_rd_req", v__h27859); + $display("%0d: PLIC.rl_process_rd_req", v__h27918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -27331,7 +27336,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) - $write("'h%h", x__h27766); + $write("'h%h", x__h27825); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && NOT_m_cfg_verbosity_read__6_ULE_1_0___d61) @@ -27379,38 +27384,38 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h76288 = $stime; + v__h76347 = $stime; #0; end - v__h76282 = v__h76288 / 32'd10; + v__h76341 = v__h76347 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h76282, + v__h76341, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h76398 = $stime; + v__h76457 = $stime; #0; end - v__h76392 = v__h76398 / 32'd10; + v__h76451 = v__h76457 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h76392, + v__h76451, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h76511 = $stime; + v__h76570 = $stime; #0; end - v__h76505 = v__h76511 / 32'd10; + v__h76564 = v__h76570 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h76505, + v__h76564, set_addr_map_addr_base, set_addr_map_addr_lim); end diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v index 3022e50..1b21cdd 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:34:25 BST 2020 +// On Wed Jun 24 20:23:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 78c9db6..3ed86ce 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:47:18 BST 2020 +// On Wed Jun 24 20:36:37 BST 2020 // // // Ports: @@ -36,35 +36,22 @@ // master0_arregion O 4 // master0_arvalid O 1 // master0_rready O 1 -// master1_awid O 4 -// master1_awaddr O 64 -// master1_awlen O 8 -// master1_awsize O 3 -// master1_awburst O 2 -// master1_awlock O 1 -// master1_awcache O 4 -// master1_awprot O 3 -// master1_awqos O 4 -// master1_awregion O 4 -// master1_awvalid O 1 -// master1_wdata O 64 -// master1_wstrb O 8 -// master1_wlast O 1 -// master1_wuser O 1 -// master1_wvalid O 1 -// master1_bready O 1 -// master1_arid O 4 -// master1_araddr O 64 -// master1_arlen O 8 -// master1_arsize O 3 -// master1_arburst O 2 -// master1_arlock O 1 -// master1_arcache O 4 -// master1_arprot O 3 -// master1_arqos O 4 -// master1_arregion O 4 -// master1_arvalid O 1 -// master1_rready O 1 +// master1_aw_canPeek O 1 reg +// master1_aw_peek O 97 reg +// RDY_master1_aw_peek O 1 reg +// RDY_master1_aw_drop O 1 reg +// master1_w_canPeek O 1 reg +// master1_w_peek O 74 reg +// RDY_master1_w_peek O 1 reg +// RDY_master1_w_drop O 1 reg +// master1_b_canPut O 1 reg +// RDY_master1_b_put O 1 reg +// master1_ar_canPeek O 1 reg +// master1_ar_peek O 97 reg +// RDY_master1_ar_peek O 1 reg +// RDY_master1_ar_drop O 1 reg +// master1_r_canPut O 1 reg +// RDY_master1_r_put O 1 reg // RDY_set_verbosity O 1 const // debug_module_mem_server_awready O 1 // debug_module_mem_server_wready O 1 @@ -99,28 +86,23 @@ // start_fromhostAddr I 64 reg // master0_awready I 1 // master0_wready I 1 +// master0_bvalid I 1 // master0_bid I 5 // master0_bresp I 2 // master0_arready I 1 +// master0_rvalid I 1 // master0_rid I 5 // master0_rdata I 64 // master0_rresp I 2 // master0_rlast I 1 // master0_ruser I 1 -// master1_awready I 1 -// master1_wready I 1 -// master1_bid I 4 -// master1_bresp I 2 -// master1_arready I 1 -// master1_rid I 4 -// master1_rdata I 64 -// master1_rresp I 2 -// master1_rlast I 1 -// master1_ruser I 1 +// master1_b_put_val I 6 reg +// master1_r_put_val I 72 reg // m_external_interrupt_req_set_not_clear I 1 reg // s_external_interrupt_req_set_not_clear I 1 // non_maskable_interrupt_req_set_not_clear I 1 unused // set_verbosity_verbosity I 4 +// debug_module_mem_server_awvalid I 1 // debug_module_mem_server_awid I 5 // debug_module_mem_server_awaddr I 64 // debug_module_mem_server_awlen I 8 @@ -131,11 +113,13 @@ // debug_module_mem_server_awprot I 3 // debug_module_mem_server_awqos I 4 // debug_module_mem_server_awregion I 4 +// debug_module_mem_server_wvalid I 1 // debug_module_mem_server_wdata I 64 // debug_module_mem_server_wstrb I 8 // debug_module_mem_server_wlast I 1 // debug_module_mem_server_wuser I 1 // debug_module_mem_server_bready I 1 +// debug_module_mem_server_arvalid I 1 // debug_module_mem_server_arid I 5 // debug_module_mem_server_araddr I 64 // debug_module_mem_server_arlen I 8 @@ -153,14 +137,12 @@ // hart0_csr_mem_server_request_put I 77 reg // hart0_put_other_req_put I 4 // EN_start I 1 -// master0_bvalid I 1 -// master0_rvalid I 1 -// master1_bvalid I 1 -// master1_rvalid I 1 +// EN_master1_aw_drop I 1 +// EN_master1_w_drop I 1 +// EN_master1_b_put I 1 +// EN_master1_ar_drop I 1 +// EN_master1_r_put I 1 // EN_set_verbosity I 1 -// debug_module_mem_server_awvalid I 1 -// debug_module_mem_server_wvalid I 1 -// debug_module_mem_server_arvalid I 1 // EN_hart0_run_halt_server_request_put I 1 // EN_hart0_gpr_mem_server_request_put I 1 // EN_hart0_fpr_mem_server_request_put I 1 @@ -172,7 +154,8 @@ // EN_hart0_csr_mem_server_response_get I 1 // // Combinational paths from inputs to outputs: -// (debug_module_mem_server_awid, +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -182,13 +165,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bid -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bid +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -198,13 +181,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bresp -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bresp +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -214,13 +197,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_buser -// (debug_module_mem_server_awid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_buser +// (debug_module_mem_server_awvalid, +// debug_module_mem_server_awid, // debug_module_mem_server_awaddr, // debug_module_mem_server_awlen, // debug_module_mem_server_awsize, @@ -230,13 +213,13 @@ // debug_module_mem_server_awprot, // debug_module_mem_server_awqos, // debug_module_mem_server_awregion, +// debug_module_mem_server_wvalid, // debug_module_mem_server_wdata, // debug_module_mem_server_wstrb, // debug_module_mem_server_wlast, -// debug_module_mem_server_wuser, -// debug_module_mem_server_awvalid, -// debug_module_mem_server_wvalid) -> debug_module_mem_server_bvalid -// (debug_module_mem_server_arid, +// debug_module_mem_server_wuser) -> debug_module_mem_server_bvalid +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -245,9 +228,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rid -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rid +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -256,9 +239,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rdata -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rdata +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -267,9 +250,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rresp -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rresp +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -278,9 +261,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rlast -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_rlast +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -289,9 +272,9 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_ruser -// (debug_module_mem_server_arid, +// debug_module_mem_server_arregion) -> debug_module_mem_server_ruser +// (debug_module_mem_server_arvalid, +// debug_module_mem_server_arid, // debug_module_mem_server_araddr, // debug_module_mem_server_arlen, // debug_module_mem_server_arsize, @@ -300,8 +283,7 @@ // debug_module_mem_server_arcache, // debug_module_mem_server_arprot, // debug_module_mem_server_arqos, -// debug_module_mem_server_arregion, -// debug_module_mem_server_arvalid) -> debug_module_mem_server_rvalid +// debug_module_mem_server_arregion) -> debug_module_mem_server_rvalid // // @@ -364,9 +346,9 @@ module mkProc(CLK, master0_wready, + master0_bvalid, master0_bid, master0_bresp, - master0_bvalid, master0_bready, @@ -394,89 +376,50 @@ module mkProc(CLK, master0_arready, + master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, master0_ruser, - master0_rvalid, master0_rready, - master1_awid, + master1_aw_canPeek, - master1_awaddr, + master1_aw_peek, + RDY_master1_aw_peek, - master1_awlen, + EN_master1_aw_drop, + RDY_master1_aw_drop, - master1_awsize, + master1_w_canPeek, - master1_awburst, + master1_w_peek, + RDY_master1_w_peek, - master1_awlock, + EN_master1_w_drop, + RDY_master1_w_drop, - master1_awcache, + master1_b_canPut, - master1_awprot, + master1_b_put_val, + EN_master1_b_put, + RDY_master1_b_put, - master1_awqos, + master1_ar_canPeek, - master1_awregion, + master1_ar_peek, + RDY_master1_ar_peek, - master1_awvalid, + EN_master1_ar_drop, + RDY_master1_ar_drop, - master1_awready, + master1_r_canPut, - master1_wdata, - - master1_wstrb, - - master1_wlast, - - master1_wuser, - - master1_wvalid, - - master1_wready, - - master1_bid, - master1_bresp, - master1_bvalid, - - master1_bready, - - master1_arid, - - master1_araddr, - - master1_arlen, - - master1_arsize, - - master1_arburst, - - master1_arlock, - - master1_arcache, - - master1_arprot, - - master1_arqos, - - master1_arregion, - - master1_arvalid, - - master1_arready, - - master1_rid, - master1_rdata, - master1_rresp, - master1_rlast, - master1_ruser, - master1_rvalid, - - master1_rready, + master1_r_put_val, + EN_master1_r_put, + RDY_master1_r_put, m_external_interrupt_req_set_not_clear, @@ -488,6 +431,7 @@ module mkProc(CLK, EN_set_verbosity, RDY_set_verbosity, + debug_module_mem_server_awvalid, debug_module_mem_server_awid, debug_module_mem_server_awaddr, debug_module_mem_server_awlen, @@ -498,15 +442,14 @@ module mkProc(CLK, debug_module_mem_server_awprot, debug_module_mem_server_awqos, debug_module_mem_server_awregion, - debug_module_mem_server_awvalid, debug_module_mem_server_awready, + debug_module_mem_server_wvalid, debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, debug_module_mem_server_wuser, - debug_module_mem_server_wvalid, debug_module_mem_server_wready, @@ -518,6 +461,7 @@ module mkProc(CLK, debug_module_mem_server_bready, + debug_module_mem_server_arvalid, debug_module_mem_server_arid, debug_module_mem_server_araddr, debug_module_mem_server_arlen, @@ -528,7 +472,6 @@ module mkProc(CLK, debug_module_mem_server_arprot, debug_module_mem_server_arqos, debug_module_mem_server_arregion, - debug_module_mem_server_arvalid, debug_module_mem_server_arready, @@ -649,9 +592,9 @@ module mkProc(CLK, input master0_wready; // action method master0_b_bflit + input master0_bvalid; input [4 : 0] master0_bid; input [1 : 0] master0_bresp; - input master0_bvalid; // value method master0_b_bready output master0_bready; @@ -695,128 +638,64 @@ module mkProc(CLK, input master0_arready; // action method master0_r_rflit + input master0_rvalid; input [4 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; input master0_ruser; - input master0_rvalid; // value method master0_r_rready output master0_rready; - // value method master1_aw_awid - output [3 : 0] master1_awid; + // value method master1_aw_canPeek + output master1_aw_canPeek; - // value method master1_aw_awaddr - output [63 : 0] master1_awaddr; + // value method master1_aw_peek + output [96 : 0] master1_aw_peek; + output RDY_master1_aw_peek; - // value method master1_aw_awlen - output [7 : 0] master1_awlen; + // action method master1_aw_drop + input EN_master1_aw_drop; + output RDY_master1_aw_drop; - // value method master1_aw_awsize - output [2 : 0] master1_awsize; + // value method master1_w_canPeek + output master1_w_canPeek; - // value method master1_aw_awburst - output [1 : 0] master1_awburst; + // value method master1_w_peek + output [73 : 0] master1_w_peek; + output RDY_master1_w_peek; - // value method master1_aw_awlock - output master1_awlock; + // action method master1_w_drop + input EN_master1_w_drop; + output RDY_master1_w_drop; - // value method master1_aw_awcache - output [3 : 0] master1_awcache; + // value method master1_b_canPut + output master1_b_canPut; - // value method master1_aw_awprot - output [2 : 0] master1_awprot; + // action method master1_b_put + input [5 : 0] master1_b_put_val; + input EN_master1_b_put; + output RDY_master1_b_put; - // value method master1_aw_awqos - output [3 : 0] master1_awqos; + // value method master1_ar_canPeek + output master1_ar_canPeek; - // value method master1_aw_awregion - output [3 : 0] master1_awregion; + // value method master1_ar_peek + output [96 : 0] master1_ar_peek; + output RDY_master1_ar_peek; - // value method master1_aw_awuser + // action method master1_ar_drop + input EN_master1_ar_drop; + output RDY_master1_ar_drop; - // value method master1_aw_awvalid - output master1_awvalid; + // value method master1_r_canPut + output master1_r_canPut; - // action method master1_aw_awready - input master1_awready; - - // value method master1_w_wdata - output [63 : 0] master1_wdata; - - // value method master1_w_wstrb - output [7 : 0] master1_wstrb; - - // value method master1_w_wlast - output master1_wlast; - - // value method master1_w_wuser - output master1_wuser; - - // value method master1_w_wvalid - output master1_wvalid; - - // action method master1_w_wready - input master1_wready; - - // action method master1_b_bflit - input [3 : 0] master1_bid; - input [1 : 0] master1_bresp; - input master1_bvalid; - - // value method master1_b_bready - output master1_bready; - - // value method master1_ar_arid - output [3 : 0] master1_arid; - - // value method master1_ar_araddr - output [63 : 0] master1_araddr; - - // value method master1_ar_arlen - output [7 : 0] master1_arlen; - - // value method master1_ar_arsize - output [2 : 0] master1_arsize; - - // value method master1_ar_arburst - output [1 : 0] master1_arburst; - - // value method master1_ar_arlock - output master1_arlock; - - // value method master1_ar_arcache - output [3 : 0] master1_arcache; - - // value method master1_ar_arprot - output [2 : 0] master1_arprot; - - // value method master1_ar_arqos - output [3 : 0] master1_arqos; - - // value method master1_ar_arregion - output [3 : 0] master1_arregion; - - // value method master1_ar_aruser - - // value method master1_ar_arvalid - output master1_arvalid; - - // action method master1_ar_arready - input master1_arready; - - // action method master1_r_rflit - input [3 : 0] master1_rid; - input [63 : 0] master1_rdata; - input [1 : 0] master1_rresp; - input master1_rlast; - input master1_ruser; - input master1_rvalid; - - // value method master1_r_rready - output master1_rready; + // action method master1_r_put + input [71 : 0] master1_r_put_val; + input EN_master1_r_put; + output RDY_master1_r_put; // action method m_external_interrupt_req input m_external_interrupt_req_set_not_clear; @@ -833,6 +712,7 @@ module mkProc(CLK, output RDY_set_verbosity; // action method debug_module_mem_server_aw_awflit + input debug_module_mem_server_awvalid; input [4 : 0] debug_module_mem_server_awid; input [63 : 0] debug_module_mem_server_awaddr; input [7 : 0] debug_module_mem_server_awlen; @@ -843,17 +723,16 @@ module mkProc(CLK, input [2 : 0] debug_module_mem_server_awprot; input [3 : 0] debug_module_mem_server_awqos; input [3 : 0] debug_module_mem_server_awregion; - input debug_module_mem_server_awvalid; // value method debug_module_mem_server_aw_awready output debug_module_mem_server_awready; // action method debug_module_mem_server_w_wflit + input debug_module_mem_server_wvalid; input [63 : 0] debug_module_mem_server_wdata; input [7 : 0] debug_module_mem_server_wstrb; input debug_module_mem_server_wlast; input debug_module_mem_server_wuser; - input debug_module_mem_server_wvalid; // value method debug_module_mem_server_w_wready output debug_module_mem_server_wready; @@ -873,6 +752,7 @@ module mkProc(CLK, input debug_module_mem_server_bready; // action method debug_module_mem_server_ar_arflit + input debug_module_mem_server_arvalid; input [4 : 0] debug_module_mem_server_arid; input [63 : 0] debug_module_mem_server_araddr; input [7 : 0] debug_module_mem_server_arlen; @@ -883,7 +763,6 @@ module mkProc(CLK, input [2 : 0] debug_module_mem_server_arprot; input [3 : 0] debug_module_mem_server_arqos; input [3 : 0] debug_module_mem_server_arregion; - input debug_module_mem_server_arvalid; // value method debug_module_mem_server_ar_arready output debug_module_mem_server_arready; @@ -955,22 +834,16 @@ module mkProc(CLK, output RDY_hart0_put_other_req_put; // signals for module outputs + wire [96 : 0] master1_ar_peek, master1_aw_peek; + wire [73 : 0] master1_w_peek; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; wire [63 : 0] debug_module_mem_server_rdata, master0_araddr, master0_awaddr, - master0_wdata, - master1_araddr, - master1_awaddr, - master1_wdata; - wire [7 : 0] master0_arlen, - master0_awlen, - master0_wstrb, - master1_arlen, - master1_awlen, - master1_wstrb; + master0_wdata; + wire [7 : 0] master0_arlen, master0_awlen, master0_wstrb; wire [4 : 0] debug_module_mem_server_bid, debug_module_mem_server_rid, master0_arid, @@ -980,29 +853,12 @@ module mkProc(CLK, master0_arregion, master0_awcache, master0_awqos, - master0_awregion, - master1_arcache, - master1_arid, - master1_arqos, - master1_arregion, - master1_awcache, - master1_awid, - master1_awqos, - master1_awregion; - wire [2 : 0] master0_arprot, - master0_arsize, - master0_awprot, - master0_awsize, - master1_arprot, - master1_arsize, - master1_awprot, - master1_awsize; + master0_awregion; + wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, master0_awsize; wire [1 : 0] debug_module_mem_server_bresp, debug_module_mem_server_rresp, master0_arburst, - master0_awburst, - master1_arburst, - master1_awburst; + master0_awburst; wire RDY_hart0_csr_mem_server_request_put, RDY_hart0_csr_mem_server_response_get, RDY_hart0_fpr_mem_server_request_put, @@ -1012,6 +868,14 @@ module mkProc(CLK, RDY_hart0_put_other_req_put, RDY_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_response_get, + RDY_master1_ar_drop, + RDY_master1_ar_peek, + RDY_master1_aw_drop, + RDY_master1_aw_peek, + RDY_master1_b_put, + RDY_master1_r_put, + RDY_master1_w_drop, + RDY_master1_w_peek, RDY_set_verbosity, RDY_start, debug_module_mem_server_arready, @@ -1031,15 +895,11 @@ module mkProc(CLK, master0_wlast, master0_wuser, master0_wvalid, - master1_arlock, - master1_arvalid, - master1_awlock, - master1_awvalid, - master1_bready, - master1_rready, - master1_wlast, - master1_wuser, - master1_wvalid; + master1_ar_canPeek, + master1_aw_canPeek, + master1_b_canPut, + master1_r_canPut, + master1_w_canPeek; // inlined wires wire [584 : 0] enqDst_1_0_lat_0$wget; @@ -1060,16 +920,8 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read; - wire [97 : 0] llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read; + wire [97 : 0] llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget, + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget; wire [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read, llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read, @@ -1077,11 +929,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read, - llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read; + llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read; wire [73 : 0] enqDst_0_lat_0$wget, llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read, @@ -1091,30 +939,21 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget; - wire [72 : 0] llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget; + wire [72 : 0] llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget, propDstData_0_lat_0$wget, propDstData_1_lat_0$wget; - wire [71 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget; wire [65 : 0] llc_mem_server_enqDst_0_lat_0$wget; wire [64 : 0] mmioPlatform_toHostQ_enqReq_lat_0$wget; wire [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read, llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read, llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read, + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read; - wire [6 : 0] llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read, - mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read; - wire [5 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget; + wire [6 : 0] llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget; wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, @@ -1124,29 +963,21 @@ module mkProc(CLK, wire enqDst_0_lat_0$whas, enqDst_1_0_lat_0$whas, llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas, + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas, + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas, + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas, + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas, llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas, + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas, llc_mem_server_propDstIdx_0_lat_1$whas, mmioPlatform_fromHostQ_deqReq_lat_0$whas, mmioPlatform_toHostQ_enqReq_lat_0$whas, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write, - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas, - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas, propDstIdx_1_1_lat_1$whas, propDstIdx_1_lat_1$whas; @@ -1210,11 +1041,6 @@ module mkProc(CLK, wire [515 : 0] llc_axi4_adapter_rg_cline$D_IN; wire llc_axi4_adapter_rg_cline$EN; - // register llc_axi4_adapter_rg_rd_req_beat - reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat; - wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN; - wire llc_axi4_adapter_rg_rd_req_beat$EN; - // register llc_axi4_adapter_rg_rd_rsp_beat reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat; wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN; @@ -1453,41 +1279,26 @@ module mkProc(CLK, wire [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; wire mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN; - // register mmio_axi4_adapter_master_xactor_clearing - reg mmio_axi4_adapter_master_xactor_clearing; - wire mmio_axi4_adapter_master_xactor_clearing$D_IN, - mmio_axi4_adapter_master_xactor_clearing$EN; - - // register mmio_axi4_adapter_master_xactor_shim_arff_rv - reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv; - wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_arff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_awff_rv - reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv; - wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_awff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_bff_rv - reg [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv; - wire [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_bff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_rff_rv - reg [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv; - wire [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_rff_rv$EN; - - // register mmio_axi4_adapter_master_xactor_shim_wff_rv - reg [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv; - wire [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; - wire mmio_axi4_adapter_master_xactor_shim_wff_rv$EN; - // register mmio_axi4_adapter_read_req_addr reg [63 : 0] mmio_axi4_adapter_read_req_addr; wire [63 : 0] mmio_axi4_adapter_read_req_addr$D_IN; wire mmio_axi4_adapter_read_req_addr$EN; + // register mmio_axi4_adapter_rg_rd_rsp_beat + reg mmio_axi4_adapter_rg_rd_rsp_beat; + wire mmio_axi4_adapter_rg_rd_rsp_beat$D_IN, + mmio_axi4_adapter_rg_rd_rsp_beat$EN; + + // register mmio_axi4_adapter_rg_wr_req_beat + reg mmio_axi4_adapter_rg_wr_req_beat; + wire mmio_axi4_adapter_rg_wr_req_beat$D_IN, + mmio_axi4_adapter_rg_wr_req_beat$EN; + + // register mmio_axi4_adapter_rspData + reg [128 : 0] mmio_axi4_adapter_rspData; + wire [128 : 0] mmio_axi4_adapter_rspData$D_IN; + wire mmio_axi4_adapter_rspData$EN; + // register propDstData_0_rl reg [72 : 0] propDstData_0_rl; wire [72 : 0] propDstData_0_rl$D_IN; @@ -1721,6 +1532,51 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$ENQ, mmio_axi4_adapter_f_rsps_to_core$FULL_N; + // ports of submodule mmio_axi4_adapter_master_shim_arff + wire [96 : 0] mmio_axi4_adapter_master_shim_arff$D_IN, + mmio_axi4_adapter_master_shim_arff$D_OUT; + wire mmio_axi4_adapter_master_shim_arff$CLR, + mmio_axi4_adapter_master_shim_arff$DEQ, + mmio_axi4_adapter_master_shim_arff$EMPTY_N, + mmio_axi4_adapter_master_shim_arff$ENQ, + mmio_axi4_adapter_master_shim_arff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_awff + wire [96 : 0] mmio_axi4_adapter_master_shim_awff$D_IN, + mmio_axi4_adapter_master_shim_awff$D_OUT; + wire mmio_axi4_adapter_master_shim_awff$CLR, + mmio_axi4_adapter_master_shim_awff$DEQ, + mmio_axi4_adapter_master_shim_awff$EMPTY_N, + mmio_axi4_adapter_master_shim_awff$ENQ, + mmio_axi4_adapter_master_shim_awff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_bff + wire [5 : 0] mmio_axi4_adapter_master_shim_bff$D_IN, + mmio_axi4_adapter_master_shim_bff$D_OUT; + wire mmio_axi4_adapter_master_shim_bff$CLR, + mmio_axi4_adapter_master_shim_bff$DEQ, + mmio_axi4_adapter_master_shim_bff$EMPTY_N, + mmio_axi4_adapter_master_shim_bff$ENQ, + mmio_axi4_adapter_master_shim_bff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_rff + wire [71 : 0] mmio_axi4_adapter_master_shim_rff$D_IN, + mmio_axi4_adapter_master_shim_rff$D_OUT; + wire mmio_axi4_adapter_master_shim_rff$CLR, + mmio_axi4_adapter_master_shim_rff$DEQ, + mmio_axi4_adapter_master_shim_rff$EMPTY_N, + mmio_axi4_adapter_master_shim_rff$ENQ, + mmio_axi4_adapter_master_shim_rff$FULL_N; + + // ports of submodule mmio_axi4_adapter_master_shim_wff + wire [73 : 0] mmio_axi4_adapter_master_shim_wff$D_IN, + mmio_axi4_adapter_master_shim_wff$D_OUT; + wire mmio_axi4_adapter_master_shim_wff$CLR, + mmio_axi4_adapter_master_shim_wff$DEQ, + mmio_axi4_adapter_master_shim_wff$EMPTY_N, + mmio_axi4_adapter_master_shim_wff$ENQ, + mmio_axi4_adapter_master_shim_wff$FULL_N; + // ports of submodule mmio_axi4_adapter_soc_map wire [63 : 0] mmio_axi4_adapter_soc_map$m_is_IO_addr_addr, mmio_axi4_adapter_soc_map$m_is_mem_addr_addr, @@ -1736,36 +1592,36 @@ module mkProc(CLK, CAN_FIRE_RL_enqDst_0_canon, CAN_FIRE_RL_enqDst_1_0_canon, CAN_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek, + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop, CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut, + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut, CAN_FIRE_RL_llc_mem_server_doEnq, CAN_FIRE_RL_llc_mem_server_dstSelectSrc, CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, @@ -1812,20 +1668,6 @@ module mkProc(CLK, CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone, CAN_FIRE_RL_mmioPlatform_waitMTimeDone, CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, @@ -1879,11 +1721,11 @@ module mkProc(CLK, CAN_FIRE_master0_b_bflit, CAN_FIRE_master0_r_rflit, CAN_FIRE_master0_w_wready, - CAN_FIRE_master1_ar_arready, - CAN_FIRE_master1_aw_awready, - CAN_FIRE_master1_b_bflit, - CAN_FIRE_master1_r_rflit, - CAN_FIRE_master1_w_wready, + CAN_FIRE_master1_ar_drop, + CAN_FIRE_master1_aw_drop, + CAN_FIRE_master1_b_put, + CAN_FIRE_master1_r_put, + CAN_FIRE_master1_w_drop, CAN_FIRE_non_maskable_interrupt_req, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_set_verbosity, @@ -1896,36 +1738,36 @@ module mkProc(CLK, WILL_FIRE_RL_enqDst_0_canon, WILL_FIRE_RL_enqDst_1_0_canon, WILL_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek, + WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop, WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req, WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut, - WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut, + WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut, WILL_FIRE_RL_llc_mem_server_doEnq, WILL_FIRE_RL_llc_mem_server_dstSelectSrc, WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, @@ -1972,20 +1814,6 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone, WILL_FIRE_RL_mmioPlatform_waitMTimeDone, WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek, - WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req, @@ -2039,11 +1867,11 @@ module mkProc(CLK, WILL_FIRE_master0_b_bflit, WILL_FIRE_master0_r_rflit, WILL_FIRE_master0_w_wready, - WILL_FIRE_master1_ar_arready, - WILL_FIRE_master1_aw_awready, - WILL_FIRE_master1_b_bflit, - WILL_FIRE_master1_r_rflit, - WILL_FIRE_master1_w_wready, + WILL_FIRE_master1_ar_drop, + WILL_FIRE_master1_aw_drop, + WILL_FIRE_master1_b_put, + WILL_FIRE_master1_r_put, + WILL_FIRE_master1_w_drop, WILL_FIRE_non_maskable_interrupt_req, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_set_verbosity, @@ -2057,7 +1885,7 @@ module mkProc(CLK, MUX_llc$dma_memReq_enq_1__VAL_3, MUX_llc$dma_memReq_enq_1__VAL_4; wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, - MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; + MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2; wire [515 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [214 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, @@ -2074,7 +1902,7 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9; wire [129 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1, - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2; wire [128 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1, MUX_mmioPlatform_amoResp$write_1__VAL_2; wire [66 : 0] MUX_mmioPlatform_curReq$write_1__VAL_1, @@ -2115,46 +1943,51 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1, - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2, + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h221935; - reg [31 : 0] v__h221472; - reg [31 : 0] v__h11342; - reg [31 : 0] v__h15880; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h4363; - reg [31 : 0] v__h7984; - reg [31 : 0] v__h19409; - reg [31 : 0] v__h18412; - reg [31 : 0] v__h18942; - reg [31 : 0] v__h10403; - reg [31 : 0] v__h10598; - reg [31 : 0] v__h199123; - reg [31 : 0] v__h212832; - reg [31 : 0] v__h191102; - reg [31 : 0] v__h220458; - reg [31 : 0] v__h191691; - reg [31 : 0] v__h191877; - reg [31 : 0] v__h4357; - reg [31 : 0] v__h7978; - reg [31 : 0] v__h10397; - reg [31 : 0] v__h10592; - reg [31 : 0] v__h11336; - reg [31 : 0] v__h15874; - reg [31 : 0] v__h16017; - reg [31 : 0] v__h18406; - reg [31 : 0] v__h18936; - reg [31 : 0] v__h19403; - reg [31 : 0] v__h191096; - reg [31 : 0] v__h191685; - reg [31 : 0] v__h191871; - reg [31 : 0] v__h199117; - reg [31 : 0] v__h212826; - reg [31 : 0] v__h220452; - reg [31 : 0] v__h221466; - reg [31 : 0] v__h221929; + reg [31 : 0] v__h224105; + reg [31 : 0] v__h223657; + reg [31 : 0] v__h9702; + reg [31 : 0] v__h9897; + reg [31 : 0] v__h11307; + reg [31 : 0] v__h17239; + reg [31 : 0] v__h17410; + reg [31 : 0] v__h18103; + reg [31 : 0] v__h18189; + reg [31 : 0] v__h2280; + reg [31 : 0] v__h7388; + reg [31 : 0] v__h20501; + reg [31 : 0] v__h21031; + reg [31 : 0] v__h21496; + reg [31 : 0] v__h201308; + reg [31 : 0] v__h215017; + reg [31 : 0] v__h193285; + reg [31 : 0] v__h222643; + reg [31 : 0] v__h193874; + reg [31 : 0] v__h194060; + reg [31 : 0] v__h2274; + reg [31 : 0] v__h7382; + reg [31 : 0] v__h9696; + reg [31 : 0] v__h9891; + reg [31 : 0] v__h11301; + reg [31 : 0] v__h17233; + reg [31 : 0] v__h17404; + reg [31 : 0] v__h18097; + reg [31 : 0] v__h18183; + reg [31 : 0] v__h20495; + reg [31 : 0] v__h21025; + reg [31 : 0] v__h21490; + reg [31 : 0] v__h193279; + reg [31 : 0] v__h193868; + reg [31 : 0] v__h194054; + reg [31 : 0] v__h201302; + reg [31 : 0] v__h215011; + reg [31 : 0] v__h222637; + reg [31 : 0] v__h223651; + reg [31 : 0] v__h224099; // synopsys translate_on // remaining internal signals @@ -2162,210 +1995,248 @@ module mkProc(CLK, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937, - dword__h148173, - ld_data__h185995, - v_wdata__h213140; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351; - reg [7 : 0] v_wstrb__h213141; - reg [5 : 0] IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811; - reg [2 : 0] x__h98832; - reg [1 : 0] CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16; + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966, + dword__h150325, + ld_data__h188147, + v_wdata__h215325, + wflit_wdata__h18041; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379; + reg [7 : 0] v_wstrb__h215326, wflit_wstrb__h18042; + reg [5 : 0] IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839; + reg [2 : 0] x__h100922; + reg [1 : 0] CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677, - v_wuser__h213143, - x__h125469, - x__h98833; - wire [583 : 0] IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1648; - wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1797; - wire [517 : 0] IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1647; - wire [515 : 0] IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639, - IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1792; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1985, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1774; - wire [129 : 0] IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1131; - wire [128 : 0] amoExec___d1043, - amoExec___d1096, - amoExec___d1321, - amoExec___d887, - amoExec___d973; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1740, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1757, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1791, - _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213; - wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37, - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35; - wire [96 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13, - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11; - wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36, - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12; - wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34; - wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513, - IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511; - wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__258_BI_ETC___d1359; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619, - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126, - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885, - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021, - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949, - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073, - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571, - addr1__h88409, - data__h138449, - failed_testnum__h221515, - line_addr__h137882, - line_addr__h147990, - line_addr__h191238, - mmioPlatform_mtime__h57710, - newData__h43098, - newData__h51199, - v_awaddr__h212729, - value__h59417, - x__h46411, - x__h54489, - x__h62366, - x__h66321, - x__h68995, - x__h71490, - x__h77037; - wire [47 : 0] IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1112, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989; - wire [31 : 0] IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1107, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905, - IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984, - IF_mmioPlatform_fetchingWay_330_THEN_mmioPlatf_ETC___d1356, - amo_req_data__h36993, - lower_data__h42399, + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705, + v_wuser__h215328, + x__h100923, + x__h127559; + wire [583 : 0] IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1676; + wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1825; + wire [517 : 0] IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1675; + wire [515 : 0] IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667, + IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1820; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2014, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1802; + wire [129 : 0] IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1159; + wire [128 : 0] amoExec___d1001, + amoExec___d1071, + amoExec___d1124, + amoExec___d1349, + amoExec___d915, + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1768, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1785, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1819; + wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34, + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32; + wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33; + wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31; + wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541, + IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539; + wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__286_BI_ETC___d1387; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154, + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101, + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599, + addr1__h90499, + data__h140598, + failed_testnum__h223700, + line_addr__h140031, + line_addr__h150142, + line_addr__h193421, + mmioPlatform_mtime__h59797, + newData__h45185, + newData__h53286, + v_awaddr__h214914, + value__h61504, + x__h48498, + x__h56576, + x__h64456, + x__h68411, + x__h71085, + x__h73580, + x__h79127; + wire [47 : 0] IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1140, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942; + wire [31 : 0] IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1135, + IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933, + IF_mmioPlatform_fetchingWay_358_THEN_mmioPlatf_ETC___d1384, + amo_req_data__h39080, + lower_data__h44486, mmioPlatform_mtime_BITS_31_TO_0__q8, mmioPlatform_mtime_BITS_63_TO_32__q7, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, - upper_data__h42400, - v__h42255, - v__h42292, - x_data__h39934; - wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1500; - wire [7 : 0] IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872, - mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877; - wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33; - wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1499; - wire [3 : 0] b__h191029, b__h4263, mmioPlatform_reqAmofunc__h86179; - wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1715, - v_awsize_val__h15192; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576; - wire IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929, - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785, - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924, - IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645, - IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064, - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1138, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334, - IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850, - IF_mmio_axi4_adapter_f_rsps_to_core_first__258_ETC___d1334, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597, - IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446, - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383, - IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679, - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516, - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523, - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390, - NOT_enqDst_0_rl_412_BIT_73_413_418_AND_SEL_ARR_ETC___d1506, - NOT_enqDst_1_0_rl_607_BIT_584_608_613_AND_SEL__ETC___d1803, - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207, - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2286, - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2289, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1161, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1256, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1267, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1277, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1325, - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1337, - NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956, - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748, - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755, - core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2218, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902, - mmioPlatform_amoWaitWriteResp_271_OR_core_0_RD_ETC___d1274, - mmioPlatform_cycle_57_ULT_99___d458, - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339, - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996, - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621, - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796, - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941, - x__h114170, - x__h120734, - x__h98632; + upper_data__h44487, + v__h44342, + v__h44379, + x_data__h42021; + wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1528; + wire [7 : 0] IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900, + mem_req_rd_addr_arlen__h5411, + mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905; + wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30; + wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1527, + x__h15205, + x__h15217, + x__h15229, + x__h15241, + x__h15253, + x__h15265, + x__h15277, + x__h15289, + x__h15301, + x__h15313, + x__h15325, + x__h15337, + x__h15349, + x__h15361, + x__h15373, + y__h15206, + y__h15218, + y__h15230, + y__h15242, + y__h15254, + y__h15266, + y__h15278, + y__h15290, + y__h15302, + y__h15314, + y__h15326, + y__h15338, + y__h15350, + y__h15362, + y__h15374; + wire [3 : 0] b__h193221, b__h2174, mmioPlatform_reqAmofunc__h88269; + wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1743, + _theResult_____1_awsize_val__h17178; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604; + wire IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957, + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813, + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952, + IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673, + IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096, + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1166, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362, + IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878, + IF_mmio_axi4_adapter_f_rsps_to_core_first__286_ETC___d1362, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625, + IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474, + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411, + IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707, + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544, + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551, + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418, + NOT_enqDst_0_rl_440_BIT_73_441_446_AND_SEL_ARR_ETC___d1534, + NOT_enqDst_1_0_rl_635_BIT_584_636_641_AND_SEL__ETC___d1831, + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236, + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2315, + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2318, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1189, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1284, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1295, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1305, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1353, + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1365, + NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984, + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709, + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, + _theResult____h13554, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776, + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783, + core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2247, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931, + mmioPlatform_amoWaitWriteResp_299_OR_core_0_RD_ETC___d1302, + mmioPlatform_cycle_85_ULT_99___d486, + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367, + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024, + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649, + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824, + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252, + mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, + mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210, + whichHalf___1__h15117, + x__h100722, + x__h10759, + x__h116260, + x__h122824, + x__h17973; // action method start assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; @@ -2375,47 +2246,47 @@ module mkProc(CLK, // value method master0_aw_awid assign master0_awid = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[97:93] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[97:93] ; // value method master0_aw_awaddr assign master0_awaddr = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[92:29] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[92:29] ; // value method master0_aw_awlen assign master0_awlen = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[28:21] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[28:21] ; // value method master0_aw_awsize assign master0_awsize = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[20:18] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[20:18] ; // value method master0_aw_awburst assign master0_awburst = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[17:16] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[17:16] ; // value method master0_aw_awlock assign master0_awlock = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[15] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[15] ; // value method master0_aw_awcache assign master0_awcache = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[14:11] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[14:11] ; // value method master0_aw_awprot assign master0_awprot = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[10:8] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[10:8] ; // value method master0_aw_awqos assign master0_awqos = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[7:4] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[7:4] ; // value method master0_aw_awregion assign master0_awregion = - llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35[3:0] ; + llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32[3:0] ; // value method master0_aw_awvalid assign master0_awvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek ; // action method master0_aw_awready assign CAN_FIRE_master0_aw_awready = 1'd1 ; @@ -2423,23 +2294,23 @@ module mkProc(CLK, // value method master0_w_wdata assign master0_wdata = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[73:10] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[73:10] ; // value method master0_w_wstrb assign master0_wstrb = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[9:2] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[9:2] ; // value method master0_w_wlast assign master0_wlast = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[1] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[1] ; // value method master0_w_wuser assign master0_wuser = - llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36[0] ; + llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33[0] ; // value method master0_w_wvalid assign master0_wvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek ; // action method master0_w_wready assign CAN_FIRE_master0_w_wready = 1'd1 ; @@ -2447,54 +2318,54 @@ module mkProc(CLK, // action method master0_b_bflit assign CAN_FIRE_master0_b_bflit = 1'd1 ; - assign WILL_FIRE_master0_b_bflit = master0_bvalid ; + assign WILL_FIRE_master0_b_bflit = 1'd1 ; // value method master0_b_bready assign master0_bready = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; // value method master0_ar_arid assign master0_arid = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[97:93] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[97:93] ; // value method master0_ar_araddr assign master0_araddr = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[92:29] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[92:29] ; // value method master0_ar_arlen assign master0_arlen = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[28:21] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[28:21] ; // value method master0_ar_arsize assign master0_arsize = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[20:18] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[20:18] ; // value method master0_ar_arburst assign master0_arburst = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[17:16] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[17:16] ; // value method master0_ar_arlock assign master0_arlock = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[15] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[15] ; // value method master0_ar_arcache assign master0_arcache = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[14:11] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[14:11] ; // value method master0_ar_arprot assign master0_arprot = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[10:8] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[10:8] ; // value method master0_ar_arqos assign master0_arqos = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[7:4] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[7:4] ; // value method master0_ar_arregion assign master0_arregion = - llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37[3:0] ; + llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34[3:0] ; // value method master0_ar_arvalid assign master0_arvalid = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek ; // action method master0_ar_arready assign CAN_FIRE_master0_ar_arready = 1'd1 ; @@ -2502,144 +2373,64 @@ module mkProc(CLK, // action method master0_r_rflit assign CAN_FIRE_master0_r_rflit = 1'd1 ; - assign WILL_FIRE_master0_r_rflit = master0_rvalid ; + assign WILL_FIRE_master0_r_rflit = 1'd1 ; // value method master0_r_rready assign master0_rready = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - // value method master1_aw_awid - assign master1_awid = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[96:93] ; + // value method master1_aw_canPeek + assign master1_aw_canPeek = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; - // value method master1_aw_awaddr - assign master1_awaddr = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[92:29] ; + // value method master1_aw_peek + assign master1_aw_peek = mmio_axi4_adapter_master_shim_awff$D_OUT ; + assign RDY_master1_aw_peek = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; - // value method master1_aw_awlen - assign master1_awlen = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[28:21] ; + // action method master1_aw_drop + assign RDY_master1_aw_drop = mmio_axi4_adapter_master_shim_awff$EMPTY_N ; + assign CAN_FIRE_master1_aw_drop = + mmio_axi4_adapter_master_shim_awff$EMPTY_N ; + assign WILL_FIRE_master1_aw_drop = EN_master1_aw_drop ; - // value method master1_aw_awsize - assign master1_awsize = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[20:18] ; + // value method master1_w_canPeek + assign master1_w_canPeek = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; - // value method master1_aw_awburst - assign master1_awburst = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[17:16] ; + // value method master1_w_peek + assign master1_w_peek = mmio_axi4_adapter_master_shim_wff$D_OUT ; + assign RDY_master1_w_peek = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; - // value method master1_aw_awlock - assign master1_awlock = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[15] ; + // action method master1_w_drop + assign RDY_master1_w_drop = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; + assign CAN_FIRE_master1_w_drop = mmio_axi4_adapter_master_shim_wff$EMPTY_N ; + assign WILL_FIRE_master1_w_drop = EN_master1_w_drop ; - // value method master1_aw_awcache - assign master1_awcache = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[14:11] ; + // value method master1_b_canPut + assign master1_b_canPut = mmio_axi4_adapter_master_shim_bff$FULL_N ; - // value method master1_aw_awprot - assign master1_awprot = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[10:8] ; + // action method master1_b_put + assign RDY_master1_b_put = mmio_axi4_adapter_master_shim_bff$FULL_N ; + assign CAN_FIRE_master1_b_put = mmio_axi4_adapter_master_shim_bff$FULL_N ; + assign WILL_FIRE_master1_b_put = EN_master1_b_put ; - // value method master1_aw_awqos - assign master1_awqos = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[7:4] ; + // value method master1_ar_canPeek + assign master1_ar_canPeek = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; - // value method master1_aw_awregion - assign master1_awregion = - mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11[3:0] ; + // value method master1_ar_peek + assign master1_ar_peek = mmio_axi4_adapter_master_shim_arff$D_OUT ; + assign RDY_master1_ar_peek = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; - // value method master1_aw_awvalid - assign master1_awvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + // action method master1_ar_drop + assign RDY_master1_ar_drop = mmio_axi4_adapter_master_shim_arff$EMPTY_N ; + assign CAN_FIRE_master1_ar_drop = + mmio_axi4_adapter_master_shim_arff$EMPTY_N ; + assign WILL_FIRE_master1_ar_drop = EN_master1_ar_drop ; - // action method master1_aw_awready - assign CAN_FIRE_master1_aw_awready = 1'd1 ; - assign WILL_FIRE_master1_aw_awready = 1'd1 ; + // value method master1_r_canPut + assign master1_r_canPut = mmio_axi4_adapter_master_shim_rff$FULL_N ; - // value method master1_w_wdata - assign master1_wdata = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[73:10] ; - - // value method master1_w_wstrb - assign master1_wstrb = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[9:2] ; - - // value method master1_w_wlast - assign master1_wlast = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[1] ; - - // value method master1_w_wuser - assign master1_wuser = - mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12[0] ; - - // value method master1_w_wvalid - assign master1_wvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - - // action method master1_w_wready - assign CAN_FIRE_master1_w_wready = 1'd1 ; - assign WILL_FIRE_master1_w_wready = 1'd1 ; - - // action method master1_b_bflit - assign CAN_FIRE_master1_b_bflit = 1'd1 ; - assign WILL_FIRE_master1_b_bflit = master1_bvalid ; - - // value method master1_b_bready - assign master1_bready = !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - - // value method master1_ar_arid - assign master1_arid = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[96:93] ; - - // value method master1_ar_araddr - assign master1_araddr = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[92:29] ; - - // value method master1_ar_arlen - assign master1_arlen = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[28:21] ; - - // value method master1_ar_arsize - assign master1_arsize = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[20:18] ; - - // value method master1_ar_arburst - assign master1_arburst = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[17:16] ; - - // value method master1_ar_arlock - assign master1_arlock = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[15] ; - - // value method master1_ar_arcache - assign master1_arcache = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[14:11] ; - - // value method master1_ar_arprot - assign master1_arprot = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[10:8] ; - - // value method master1_ar_arqos - assign master1_arqos = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[7:4] ; - - // value method master1_ar_arregion - assign master1_arregion = - mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13[3:0] ; - - // value method master1_ar_arvalid - assign master1_arvalid = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - - // action method master1_ar_arready - assign CAN_FIRE_master1_ar_arready = 1'd1 ; - assign WILL_FIRE_master1_ar_arready = 1'd1 ; - - // action method master1_r_rflit - assign CAN_FIRE_master1_r_rflit = 1'd1 ; - assign WILL_FIRE_master1_r_rflit = master1_rvalid ; - - // value method master1_r_rready - assign master1_rready = !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; + // action method master1_r_put + assign RDY_master1_r_put = mmio_axi4_adapter_master_shim_rff$FULL_N ; + assign CAN_FIRE_master1_r_put = mmio_axi4_adapter_master_shim_rff$FULL_N ; + assign WILL_FIRE_master1_r_put = EN_master1_r_put ; // action method m_external_interrupt_req assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; @@ -2660,8 +2451,7 @@ module mkProc(CLK, // action method debug_module_mem_server_aw_awflit assign CAN_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_aw_awflit = - debug_module_mem_server_awvalid ; + assign WILL_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ; // value method debug_module_mem_server_aw_awready assign debug_module_mem_server_awready = @@ -2669,8 +2459,7 @@ module mkProc(CLK, // action method debug_module_mem_server_w_wflit assign CAN_FIRE_debug_module_mem_server_w_wflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_w_wflit = - debug_module_mem_server_wvalid ; + assign WILL_FIRE_debug_module_mem_server_w_wflit = 1'd1 ; // value method debug_module_mem_server_w_wready assign debug_module_mem_server_wready = @@ -2678,15 +2467,15 @@ module mkProc(CLK, // value method debug_module_mem_server_b_bid assign debug_module_mem_server_bid = - llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33[6:2] ; + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30[6:2] ; // value method debug_module_mem_server_b_bresp assign debug_module_mem_server_bresp = - llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33[1:0] ; + llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30[1:0] ; // value method debug_module_mem_server_b_bvalid assign debug_module_mem_server_bvalid = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek ; // action method debug_module_mem_server_b_bready assign CAN_FIRE_debug_module_mem_server_b_bready = 1'd1 ; @@ -2694,8 +2483,7 @@ module mkProc(CLK, // action method debug_module_mem_server_ar_arflit assign CAN_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ; - assign WILL_FIRE_debug_module_mem_server_ar_arflit = - debug_module_mem_server_arvalid ; + assign WILL_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ; // value method debug_module_mem_server_ar_arready assign debug_module_mem_server_arready = @@ -2703,27 +2491,27 @@ module mkProc(CLK, // value method debug_module_mem_server_r_rid assign debug_module_mem_server_rid = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[72:68] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[72:68] ; // value method debug_module_mem_server_r_rdata assign debug_module_mem_server_rdata = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[67:4] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[67:4] ; // value method debug_module_mem_server_r_rresp assign debug_module_mem_server_rresp = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[3:2] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[3:2] ; // value method debug_module_mem_server_r_rlast assign debug_module_mem_server_rlast = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[1] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[1] ; // value method debug_module_mem_server_r_ruser assign debug_module_mem_server_ruser = - llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34[0] ; + llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31[0] ; // value method debug_module_mem_server_r_rvalid assign debug_module_mem_server_rvalid = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek ; // action method debug_module_mem_server_r_rready assign CAN_FIRE_debug_module_mem_server_r_rready = 1'd1 ; @@ -3081,6 +2869,66 @@ module mkProc(CLK, .FULL_N(mmio_axi4_adapter_f_rsps_to_core$FULL_N), .EMPTY_N(mmio_axi4_adapter_f_rsps_to_core$EMPTY_N)); + // submodule mmio_axi4_adapter_master_shim_arff + FIFO2 #(.width(32'd97), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_arff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_arff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_arff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_arff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_arff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_arff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_arff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_arff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_awff + FIFO2 #(.width(32'd97), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_awff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_awff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_awff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_awff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_awff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_awff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_awff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_bff + FIFO2 #(.width(32'd6), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_bff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_bff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_bff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_bff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_bff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_bff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_bff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_bff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_rff + FIFO2 #(.width(32'd72), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_rff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_rff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_rff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_rff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_rff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_rff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_rff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_rff$EMPTY_N)); + + // submodule mmio_axi4_adapter_master_shim_wff + FIFO2 #(.width(32'd74), + .guarded(32'd1)) mmio_axi4_adapter_master_shim_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(mmio_axi4_adapter_master_shim_wff$D_IN), + .ENQ(mmio_axi4_adapter_master_shim_wff$ENQ), + .DEQ(mmio_axi4_adapter_master_shim_wff$DEQ), + .CLR(mmio_axi4_adapter_master_shim_wff$CLR), + .D_OUT(mmio_axi4_adapter_master_shim_wff$D_OUT), + .FULL_N(mmio_axi4_adapter_master_shim_wff$FULL_N), + .EMPTY_N(mmio_axi4_adapter_master_shim_wff$EMPTY_N)); + // submodule mmio_axi4_adapter_soc_map mkSoC_Map mmio_axi4_adapter_soc_map(.CLK(CLK), .RST_N(RST_N), @@ -3126,7 +2974,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && - IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414 ; + IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3150,7 +2998,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609 ; + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3240,22 +3088,41 @@ module mkProc(CLK, assign CAN_FIRE_RL_rl_tohost = !mmioPlatform_toHostQ_empty ; assign WILL_FIRE_RL_rl_tohost = CAN_FIRE_RL_rl_tohost ; + // rule RL_mmio_axi4_adapter_rl_handle_read_rsps + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + mmio_axi4_adapter_master_shim_rff$EMPTY_N && + (!mmio_axi4_adapter_master_shim_rff$D_OUT[1] || + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + // rule RL_mmio_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 && + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = - mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 && + mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd1 && - b__h4263 == 4'd0 ; + b__h2174 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + + // rule RL_mmio_axi4_adapter_rl_discard_write_rsp + assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + b__h2174 != 4'd0 && mmio_axi4_adapter_master_shim_bff$EMPTY_N && + (mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 || + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = + CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; // rule RL_mmio_axi4_adapter_rl_handle_non_Ld_St assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = @@ -3265,123 +3132,6 @@ module mkProc(CLK, assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ; - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && - mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && - mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = - !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] && - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ; - - // rule RL_mmio_axi4_adapter_rl_discard_write_rsp - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - !mmio_axi4_adapter_master_xactor_clearing && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[6] && - b__h4263 != 4'd0 && - (mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 || - mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && - !mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && - mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && - mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; - - // rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = - !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] && - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ; - - // rule RL_mmio_axi4_adapter_rl_handle_read_rsps - assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - !mmio_axi4_adapter_master_xactor_clearing && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72] && - mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps = - CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && - !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ; - - // rule RL_mmio_axi4_adapter_master_xactor_do_clear - assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = - mmio_axi4_adapter_master_xactor_clearing ; - assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear = - mmio_axi4_adapter_master_xactor_clearing ; - // rule RL_mmioPlatform_propagateTime assign CAN_FIRE_RL_mmioPlatform_propagateTime = mmioPlatform_state != 2'd0 ; assign WILL_FIRE_RL_mmioPlatform_propagateTime = @@ -3390,23 +3140,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_57_ULT_99___d458 ; + mmioPlatform_cycle_85_ULT_99___d486 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_57_ULT_99___d458 ; + !mmioPlatform_cycle_85_ULT_99___d486 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 && + NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3423,7 +3173,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786 && + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3432,7 +3182,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850 && + IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3478,7 +3228,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h71490 == 64'd0 || + x__h73580 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3496,7 +3246,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1161 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1189 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3504,37 +3254,37 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1256 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1284 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1267 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1295 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - mmioPlatform_amoWaitWriteResp_271_OR_core_0_RD_ETC___d1274 && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1277 ; + mmioPlatform_amoWaitWriteResp_299_OR_core_0_RD_ETC___d1302 && + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1305 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1325 ; + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1353 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__258_ETC___d1334 && - NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1337 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__286_ETC___d1362 && + NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1365 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3648,7 +3398,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3667,47 +3417,47 @@ module mkProc(CLK, assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas && llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut = !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ; + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut ; // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = @@ -3716,7 +3466,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3728,7 +3478,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3747,7 +3497,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3758,7 +3508,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3771,7 +3521,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3781,7 +3531,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3798,45 +3548,45 @@ module mkProc(CLK, !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_setPeek ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas && !llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ; + llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_setPeek ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas && + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas && !llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop ; - // rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop - assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = + // rule RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop + assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && - llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas ; - assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ; + llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop = + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop ; // rule RL_llc_mem_server_axi4_slave_xactor_do_clear assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear = @@ -3877,110 +3627,110 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && - b__h191029 == 4'd0 ; + b__h193221 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && - llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ; + llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ; + llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut = + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas && llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = + // rule RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] && - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ; + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = !llc_axi4_adapter_master_xactor_clearing && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] && - b__h191029 != 4'd0 ; + b__h193221 != 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_setPeek ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop = + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas && !llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = + // rule RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && - llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ; + llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas && + // rule RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut = + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas && llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut ; - // rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut - assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = + // rule RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut + assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] && - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ; - assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ; + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas ; + assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut = + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut ; // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2218 ; + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2247 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3993,7 +3743,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ; + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4001,25 +3751,25 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 ; + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 || + (!mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4049,12 +3799,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && @@ -4080,31 +3830,33 @@ module mkProc(CLK, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 && !mmio_axi4_adapter_soc_map$m_is_IO_addr ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_master_shim_rff$D_OUT[1] ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3 = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0 ; + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0 ; assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = - { 1'd0, llc$to_child_toC_first[586:1] } ; - assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd1, llc$to_child_toC_first[586:521], llc$to_child_toC_first[519:0] } ; + assign MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2 = + { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amo_req_data__h36993 : - x_data__h39934 } ; + amo_req_data__h39080 : + x_data__h42021 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4120,16 +3872,16 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 67'h60000000000000000, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 3'd6, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 65'h0AAAAAAAAAAAAAAAA, - mmio_axi4_adapter_f_rsps_to_core_first__258_BI_ETC___d1359 } ; + mmio_axi4_adapter_f_rsps_to_core_first__286_BI_ETC___d1387 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = @@ -4138,24 +3890,24 @@ module mkProc(CLK, { 3'd6, mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h42255, 32'd0 }, + { v__h44342, 32'd0 }, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1131 } ; + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1159 } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = { llc_mem_server_rg_cacheline_cache_addr, 64'hFFFFFFFFFFFFFFFF, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h137882, + { line_addr__h140031, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h147990, + { line_addr__h150142, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4175,14 +3927,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1985, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2014, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd0) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -4190,21 +3942,21 @@ module mkProc(CLK, { 65'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 } ; + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 } ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = { 1'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021, + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049, 64'd0 } ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) ? 67'h1AAAAAAAAAAAAAAAA : - ((!core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) ? + ((!core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) ? 67'h2AAAAAAAAAAAAAAAA : - IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513) ; + IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, (mmioPlatform_instSel == 2'd3) ? @@ -4217,11 +3969,11 @@ module mkProc(CLK, mmioPlatform_instSel + 2'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ? + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_3 = @@ -4232,32 +3984,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 or + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 or + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_5 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_5 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_5 = - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4265,95 +4017,79 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_6 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - (mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ? + (mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - amoExec___d1321 } ; + amoExec___d1349 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811, + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { addr1__h88409, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + { addr1__h90499, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ; - assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = - { mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0, - 1'd0, - _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 } ; + assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = + { mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0, + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 } ; // inlined wires - assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = - { master1_bid, master1_bresp } ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = - master1_bvalid && - !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = - { master1_rid, - master1_rdata, - master1_rresp, - master1_rlast, - master1_ruser } ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = - master1_rvalid && - !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ; - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h71490 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73580 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h71490 != 64'd0 ; + x__h73580 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h66321 == 64'd0 ; + x__h68411 == 64'd0 ; assign propDstIdx_1_lat_1$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 && - x__h98632 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 && + x__h100722 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17, - SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1500 } ; + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1528 } ; assign enqDst_0_lat_0$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 ; assign propDstIdx_1_1_lat_1$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 && - x__h120734 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 && + x__h122824 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1797 } ; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1825 } ; assign enqDst_1_0_lat_0$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 ; + assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { debug_module_mem_server_awid, debug_module_mem_server_awaddr, debug_module_mem_server_awlen, @@ -4364,18 +4100,18 @@ module mkProc(CLK, debug_module_mem_server_awprot, debug_module_mem_server_awqos, debug_module_mem_server_awregion } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$whas = debug_module_mem_server_awvalid && !llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget = + assign llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget = { debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, debug_module_mem_server_wuser } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$whas = debug_module_mem_server_wvalid && !llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget = + assign llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget = { debug_module_mem_server_arid, debug_module_mem_server_araddr, debug_module_mem_server_arlen, @@ -4386,159 +4122,60 @@ module mkProc(CLK, debug_module_mem_server_arprot, debug_module_mem_server_arqos, debug_module_mem_server_arregion } ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$whas = debug_module_mem_server_arvalid && !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071 } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget = + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103 } ; + assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas = + assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = master0_bvalid && !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ; - assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget = + assign llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget = { master0_rid, master0_rdata, master0_rresp, master0_rlast, master0_ruser } ; - assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas = + assign llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$whas = master0_rvalid && !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] && - master1_awready ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && - master1_wready ; - assign mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] && - master1_arready ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_dropWire$whas = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] && debug_module_mem_server_bready ; - assign llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas = + assign llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_dropWire$whas = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] && debug_module_mem_server_rready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_awSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] && master0_awready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_wSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] && master0_wready ; - assign llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas = + assign llc_axi4_adapter_master_xactor_master_arSynth_src_dropWire$whas = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] && master0_arready ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 5'd16, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], - 8'd0, - v_awsize_val__h15192, - 18'd65536 } ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_awff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129], - 2'd2 } ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_wff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? - 75'h2AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 75'h2AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ? - mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_bff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read = - WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? - 7'd42 : - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 7'd42 : - mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 5'd16, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], - 29'd851968 } ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read = - mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write ? - mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_arff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = - { 1'd1, - mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ? - mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : - mmio_axi4_adapter_master_xactor_shim_rff_rv ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ? - 73'h0AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read = - mmio_axi4_adapter_master_xactor_clearing ? - 73'h0AAAAAAAAAAAAAAAAAA : - mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map$m_is_IO_addr ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h4263 - 4'd1 ; + b__h2174 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h4263 ; + b__h2174 ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_awff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read = @@ -4551,9 +4188,9 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_wff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read = @@ -4564,12 +4201,16 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_clearing ? 75'h2AAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[97:93], + 2'd0 } ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read = WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? - 8'd128 : + llc_mem_server_axi4_slave_xactor_shim_bff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_bff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_doDrop ? 8'd42 : llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read = @@ -4578,9 +4219,9 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 = { 1'd1, - llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget } ; + llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_putWire$wget } ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_doPut ? llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_arff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read = @@ -4592,13 +4233,16 @@ module mkProc(CLK, 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 = - { 6'd32, dword__h148173, 4'd2 } ; + { 1'd1, + llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[97:93], + dword__h150325, + 4'd2 } ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 : llc_mem_server_axi4_slave_xactor_shim_rff_rv ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read = - CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ? + CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_doDrop ? 74'h0AAAAAAAAAAAAAAAAAA : llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read = @@ -4609,13 +4253,13 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 6'd32, v_awaddr__h212729, 29'd15532032 } ; + { 6'd32, v_awaddr__h214914, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read = llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_awff_rv ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_doDrop ? 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read = @@ -4624,16 +4268,16 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - v_wdata__h213140, - v_wstrb__h213141, + v_wdata__h215325, + v_wstrb__h215326, llc_axi4_adapter_rg_wr_req_beat == 3'd7, - v_wuser__h213143 } ; + v_wuser__h215328 } ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_wff_rv ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_doDrop ? 75'h2AAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read = @@ -4642,9 +4286,9 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 = { 1'd1, - llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ; + llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget } ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_doPut ? llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_bff_rv ; assign llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read = @@ -4656,13 +4300,13 @@ module mkProc(CLK, 8'd42 : llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 6'd32, line_addr__h191238, 29'd15532032 } ; + { 6'd32, line_addr__h193421, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ? llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_arff_rv ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_doDrop ? 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read = @@ -4671,9 +4315,9 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 = { 1'd1, - llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ; + llc_axi4_adapter_master_xactor_master_rSynth_snk_putWire$wget } ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read = - CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ? + CAN_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_doPut ? llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 : llc_axi4_adapter_master_xactor_shim_rff_rv ; assign llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read = @@ -4690,11 +4334,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h191029 - 4'd1 ; + b__h193221 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h191029 ; + b__h193221 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4706,7 +4350,7 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414, + IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : (enqDst_0_lat_0$whas ? @@ -4717,8 +4361,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609, - IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1648 } ; + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637, + IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1676 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4762,14 +4406,10 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253 ; + IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; - // register llc_axi4_adapter_rg_rd_req_beat - assign llc_axi4_adapter_rg_rd_req_beat$D_IN = 3'h0 ; - assign llc_axi4_adapter_rg_rd_req_beat$EN = 1'b0 ; - // register llc_axi4_adapter_rg_rd_rsp_beat assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN = llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; @@ -4815,7 +4455,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081, + IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4825,20 +4465,20 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h137882 : - line_addr__h147990 ; + line_addr__h140031 : + line_addr__h150142 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4921,7 +4561,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ; + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4934,11 +4574,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 && + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4948,11 +4588,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ; + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -5003,16 +4643,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 ; + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h51199 : + newData__h53286 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -5021,7 +4661,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h43098 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h45185 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -5031,9 +4671,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -5142,7 +4782,7 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = !mmioPlatform_toHostQ_clearReq_rl && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -5163,7 +4803,7 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = !mmioPlatform_toHostQ_clearReq_rl && - (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 || + (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl && mmioPlatform_toHostQ_full) ; @@ -5176,7 +4816,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5184,15 +4824,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5203,36 +4843,6 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; - // register mmio_axi4_adapter_master_xactor_clearing - assign mmio_axi4_adapter_master_xactor_clearing$D_IN = 1'd0 ; - assign mmio_axi4_adapter_master_xactor_clearing$EN = - mmio_axi4_adapter_master_xactor_clearing ; - - // register mmio_axi4_adapter_master_xactor_shim_arff_rv - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_awff_rv - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_bff_rv - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_bff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_rff_rv - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_rff_rv$EN = 1'b1 ; - - // register mmio_axi4_adapter_master_xactor_shim_wff_rv - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN = 1'b1 ; - // register mmio_axi4_adapter_read_req_addr assign mmio_axi4_adapter_read_req_addr$D_IN = mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; @@ -5240,6 +4850,30 @@ module mkProc(CLK, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr ; + // register mmio_axi4_adapter_rg_rd_rsp_beat + assign mmio_axi4_adapter_rg_rd_rsp_beat$D_IN = + !mmio_axi4_adapter_master_shim_rff$D_OUT[1] && x__h10759 ; + assign mmio_axi4_adapter_rg_rd_rsp_beat$EN = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + + // register mmio_axi4_adapter_rg_wr_req_beat + assign mmio_axi4_adapter_rg_wr_req_beat$D_IN = + !whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + !mmio_axi4_adapter_rg_wr_req_beat && + x__h17973 ; + assign mmio_axi4_adapter_rg_wr_req_beat$EN = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + + // register mmio_axi4_adapter_rspData + assign mmio_axi4_adapter_rspData$D_IN = + mmio_axi4_adapter_master_shim_rff$D_OUT[1] ? + 129'd0 : + mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 ; + assign mmio_axi4_adapter_rspData$EN = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + // register propDstData_0_rl assign propDstData_0_rl$D_IN = CAN_FIRE_RL_srcPropose ? @@ -5249,28 +4883,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533, - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538, + { IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561, + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[517] : propDstData_1_0_rl[517], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516:1] : propDstData_1_0_rl[516:1], - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559 } ; + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571, - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576, + { IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599, + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[517] : propDstData_1_1_rl[517], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516:1] : propDstData_1_1_rl[516:1], - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597 } ; + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5282,26 +4916,26 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = - !NOT_enqDst_0_rl_412_BIT_73_413_418_AND_SEL_ARR_ETC___d1506 && - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383 ; + !NOT_enqDst_0_rl_440_BIT_73_441_446_AND_SEL_ARR_ETC___d1534 && + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = - !NOT_enqDst_1_0_rl_607_BIT_584_608_613_AND_SEL__ETC___d1803 && - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516 ; + !NOT_enqDst_1_0_rl_635_BIT_584_636_641_AND_SEL__ETC___d1831 && + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523 ; + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390 ; + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 @@ -5320,9 +4954,9 @@ module mkProc(CLK, assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq ? + WILL_FIRE_RL_sendPRs ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : - MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; + MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2 ; assign core_0$hart0_csr_mem_server_request_put = hart0_csr_mem_server_request_put ; assign core_0$hart0_fpr_mem_server_request_put = @@ -5332,9 +4966,9 @@ module mkProc(CLK, assign core_0$hart0_run_halt_server_request_put = hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq_1 ? + WILL_FIRE_RL_sendPRs_1 ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : - MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; + MUX_core_0$iCacheToParent_fromP_enq_1__VAL_2 ; always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 or MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 or @@ -5420,7 +5054,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h185995, llc$dma_respLd_first[3] } ; + { ld_data__h188147, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5428,11 +5062,11 @@ module mkProc(CLK, assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ; assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ; assign core_0$EN_dCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ; + WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ; assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; + WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ; assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_llc_mem_server_srcPropose ; assign core_0$EN_tlbToMem_respLd_enq = @@ -5443,13 +5077,13 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp || WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 || + mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 || + (!mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -5459,15 +5093,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_processFromHost ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 || + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 ; + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5549,13 +5183,13 @@ module mkProc(CLK, enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639, - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645 } ; + { IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5648,8 +5282,8 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; assign mmio_axi4_adapter_f_reqs_from_core$DEQ = + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St || - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ; @@ -5657,8 +5291,8 @@ module mkProc(CLK, always@(MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 or MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 or MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 or - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps or - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3) + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 or + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3) begin case (1'b1) // synopsys parallel_case MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1: @@ -5666,10 +5300,10 @@ module mkProc(CLK, MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1; MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2: mmio_axi4_adapter_f_rsps_to_core$D_IN = - 130'h200000000000000000000000000000000; - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps: + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2; + MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_3: mmio_axi4_adapter_f_rsps_to_core$D_IN = - MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3; + 130'h200000000000000000000000000000000; default: mmio_axi4_adapter_f_rsps_to_core$D_IN = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -5678,16 +5312,69 @@ module mkProc(CLK, (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req) && !mmio_axi4_adapter_soc_map$m_is_IO_addr || + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_master_shim_rff$D_OUT[1] || WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0 || - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0 ; assign mmio_axi4_adapter_f_rsps_to_core$DEQ = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; assign mmio_axi4_adapter_f_rsps_to_core$CLR = 1'b0 ; + // submodule mmio_axi4_adapter_master_shim_arff + assign mmio_axi4_adapter_master_shim_arff$D_IN = + { 4'd0, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + mem_req_rd_addr_arlen__h5411, + 21'd851968 } ; + assign mmio_axi4_adapter_master_shim_arff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_shim_arff$DEQ = EN_master1_ar_drop ; + assign mmio_axi4_adapter_master_shim_arff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_awff + assign mmio_axi4_adapter_master_shim_awff$D_IN = + { 4'd0, + mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151], + mem_req_rd_addr_arlen__h5411, + _theResult_____1_awsize_val__h17178, + 18'd65536 } ; + assign mmio_axi4_adapter_master_shim_awff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 ; + assign mmio_axi4_adapter_master_shim_awff$DEQ = EN_master1_aw_drop ; + assign mmio_axi4_adapter_master_shim_awff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_bff + assign mmio_axi4_adapter_master_shim_bff$D_IN = master1_b_put_val ; + assign mmio_axi4_adapter_master_shim_bff$ENQ = EN_master1_b_put ; + assign mmio_axi4_adapter_master_shim_bff$DEQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ; + assign mmio_axi4_adapter_master_shim_bff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_rff + assign mmio_axi4_adapter_master_shim_rff$D_IN = master1_r_put_val ; + assign mmio_axi4_adapter_master_shim_rff$ENQ = EN_master1_r_put ; + assign mmio_axi4_adapter_master_shim_rff$DEQ = + CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ; + assign mmio_axi4_adapter_master_shim_rff$CLR = 1'b0 ; + + // submodule mmio_axi4_adapter_master_shim_wff + assign mmio_axi4_adapter_master_shim_wff$D_IN = + { wflit_wdata__h18041, + wflit_wstrb__h18042, + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat, + 1'd0 } ; + assign mmio_axi4_adapter_master_shim_wff$ENQ = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr ; + assign mmio_axi4_adapter_master_shim_wff$DEQ = EN_master1_w_drop ; + assign mmio_axi4_adapter_master_shim_wff$CLR = 1'b0 ; + // submodule mmio_axi4_adapter_soc_map assign mmio_axi4_adapter_soc_map$m_is_IO_addr_addr = mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ; @@ -5695,41 +5382,41 @@ module mkProc(CLK, assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current({ 65'd0, - value__h59417 }), + value__h61504 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d887)); - module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d915)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current({ 65'd0, - mmioPlatform_mtime__h57710 }), + mmioPlatform_mtime__h59797 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d973)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1001)); + module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), .amoExec_current(129'd0), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d1043)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1071)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - !IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] }), - .amoExec_current({ 65'd0, x__h77037 }), + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + !IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] }), + .amoExec_current({ 65'd0, x__h79127 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 }), - .amoExec(amoExec___d1096)); - module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h86179, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 }), + .amoExec(amoExec___d1124)); + module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88269, ((mmioPlatform_reqBE[0] ? 5'd1 : 5'd0) + @@ -5785,294 +5472,294 @@ module mkProc(CLK, .amoExec_wordIdx(mmioPlatform_curReq[3:2]), .amoExec_current(mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0]), .amoExec_inpt(mmioPlatform_reqData), - .amoExec(amoExec___d1321)); - assign IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929 = - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + .amoExec(amoExec___d1349)); + assign IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957 = + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1107 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - mmioPlatform_fromHostQ_data_0[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - mmioPlatform_fromHostQ_data_0[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - mmioPlatform_fromHostQ_data_0[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1112 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1107, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - mmioPlatform_fromHostQ_data_0[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - mmioPlatform_mtimecmp_0[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - mmioPlatform_mtimecmp_0[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - mmioPlatform_mtimecmp_0[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d905, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - mmioPlatform_mtimecmp_0[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : mmioPlatform_mtime[63:56], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : mmioPlatform_mtime[55:48], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : mmioPlatform_mtime[47:40], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d984, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1012, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : mmioPlatform_mtime[31:24], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_NOT_core_0_mmioToPlatform_cRq_first__88_BIT_ETC___d513 = - (!core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) ? + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1135 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + mmioPlatform_fromHostQ_data_0[63:56], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + mmioPlatform_fromHostQ_data_0[55:48], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + mmioPlatform_fromHostQ_data_0[47:40], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + mmioPlatform_fromHostQ_data_0[39:32] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1140 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1135, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + mmioPlatform_fromHostQ_data_0[31:24], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + mmioPlatform_fromHostQ_data_0[23:16] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + mmioPlatform_mtimecmp_0[63:56], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + mmioPlatform_mtimecmp_0[55:48], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + mmioPlatform_mtimecmp_0[47:40], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + mmioPlatform_mtimecmp_0[39:32] } ; + assign IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d933, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + mmioPlatform_mtimecmp_0[31:24], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + mmioPlatform_mtimecmp_0[23:16] } ; + assign IF_NOT_core_0_mmioToPlatform_cRq_first__16_BIT_ETC___d541 = + (!core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) ? 67'h3AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511) ; - assign IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785 = + IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539) ; + assign IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 = - newData__h43098 <= mmioPlatform_mtime ; - assign IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511 = - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 ? + assign IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 = + newData__h45185 <= mmioPlatform_mtime ; + assign IF_core_0_mmioToPlatform_cRq_first__16_BITS_21_ETC___d539 = + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 ? 67'h5AAAAAAAAAAAAAAAA : - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ? + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ; - assign IF_enqDst_0_lat_0_whas__409_THEN_enqDst_0_lat__ETC___d1414 = + assign IF_enqDst_0_lat_0_whas__437_THEN_enqDst_0_lat__ETC___d1442 = enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1609 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1637 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[584] : enqDst_1_0_rl[584] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[583:520] : enqDst_1_0_rl[583:520] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[519:518] : enqDst_1_0_rl[519:518] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[517] : enqDst_1_0_rl[517] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[516:1] : enqDst_1_0_rl[516:1] ; - assign IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645 = + assign IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1647 = + assign IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1675 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1629, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1657, CAN_FIRE_RL_doEnq_1 ? 516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1639, - x__h114170 } ; - assign IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1648 = + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1667, + x__h116260 } ; + assign IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1676 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1619, + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1647, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1624, - IF_enqDst_1_0_lat_1_whas__601_THEN_enqDst_1_0__ETC___d1647 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_211_BIT_0_2_ETC___d2253 = + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1652, + IF_enqDst_1_0_lat_1_whas__629_THEN_enqDst_1_0__ETC___d1675 } ; + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_240_BIT_0_2_ETC___d2282 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1985 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2014 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd6) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd5) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd4) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[319:256], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd3) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd2) ? - data__h138449 : + data__h140598 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__076_THE_ETC___d2081 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__108_THE_ETC___d2113 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__06_ETC___d2071 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2103 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__061_ETC___d2064 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__093_ETC___d2096 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_fetchingWay_330_THEN_mmioPlatf_ETC___d1356 = + assign IF_mmioPlatform_fetchingWay_358_THEN_mmioPlatf_ETC___d1384 = mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 ; - assign IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 ; + assign IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154 = (mmioPlatform_fromHostQ_empty || mmioPlatform_fromHostAddr[0]) ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124 = + assign IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152 = mmioPlatform_fromHostQ_empty ? 64'd0 : (mmioPlatform_fromHostAddr[0] ? mmioPlatform_fromHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005 = - ((mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + assign IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033 = + ((mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872 = + assign IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 8'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqBE[15:8] : mmioPlatform_reqBE[7:0]) ; - assign IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885 = + assign IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 64'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqData[127:64] : mmioPlatform_reqData[63:0]) ; - assign IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021 = + assign IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q7 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q8 } ; - assign IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 = + assign IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1078 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1106 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067, + { IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095, 1'd0, - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d1131 = + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101 } ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d1159 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121, + { IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149, 1'd0, - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124, - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126 } ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d786 = + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154 } ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d814 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d785 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d1022 = + IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d813 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d1050 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d1021 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_1_ETC___d949 = + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d1049 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_1_ETC___d977 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_72_BIT_4_73_THEN_SEXT_mm_ETC___d948 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067 = + IF_mmioPlatform_reqBE_00_BIT_4_01_THEN_SEXT_mm_ETC___d976 ; + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? mmioPlatform_toHostQ_empty : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h71490 == 64'd0 : - x__h66321 == 64'd0) : + x__h73580 == 64'd0 : + x__h68411 == 64'd0) : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1138 = + assign IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1166 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h71490 != 64'd0 : - x__h66321 != 64'd0) : + x__h73580 != 64'd0 : + x__h68411 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; - assign IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073 = + assign IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101 = (mmioPlatform_toHostQ_empty || mmioPlatform_toHostAddr[0]) ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071 = + assign IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099 = mmioPlatform_toHostQ_empty ? 64'd0 : (mmioPlatform_toHostAddr[0] ? mmioPlatform_toHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 = + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__53__ETC___d362 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_42_THEN_core__ETC___d850 = + assign IF_mmioPlatform_waitLowerMSIPCRs_70_THEN_core__ETC___d878 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6080,85 +5767,82 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__258_ETC___d1334 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__286_ETC___d1362 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 = + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d201 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? - !mmio_axi4_adapter_master_xactor_clearing && - !mmio_axi4_adapter_master_xactor_shim_awff_rv[97] && - !mmio_axi4_adapter_master_xactor_shim_wff_rv[74] : + mmio_axi4_adapter_master_shim_wff$FULL_N && + (!whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + mmio_axi4_adapter_rg_wr_req_beat || + mmio_axi4_adapter_master_shim_awff$FULL_N) : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 = - mmio_axi4_adapter_soc_map$m_is_IO_addr ? - !mmio_axi4_adapter_master_xactor_clearing && - !mmio_axi4_adapter_master_xactor_shim_arff_rv[97] : - mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533 = + assign IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[583:520] : propDstData_1_0_rl[583:520] ; - assign IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538 = + assign IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[519:518] : propDstData_1_0_rl[519:518] ; - assign IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559 = + assign IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571 = + assign IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[583:520] : propDstData_1_1_rl[583:520] ; - assign IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576 = + assign IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[519:518] : propDstData_1_1_rl[519:518] ; - assign IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597 = + assign IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446 = + assign IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474 = !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383 = + assign IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679 = + assign IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707 = !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516 = + assign IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523 = + assign IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390 = + assign IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_rl_412_BIT_73_413_418_AND_SEL_ARR_ETC___d1506 = + assign NOT_enqDst_0_rl_440_BIT_73_441_446_AND_SEL_ARR_ETC___d1534 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 && - (SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 ? + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 && + (SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 ? !srcRR_0 : - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383) ; - assign NOT_enqDst_1_0_rl_607_BIT_584_608_613_AND_SEL__ETC___d1803 = + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411) ; + assign NOT_enqDst_1_0_rl_635_BIT_584_636_641_AND_SEL__ETC___d1831 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 && - (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 ? + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 && + (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 ? !srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 = + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2286 = - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2315 = + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2289 = - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2318 = + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1161 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1189 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6169,7 +5853,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1256 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1284 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6180,7 +5864,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1267 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1295 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6192,7 +5876,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1277 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1305 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6204,7 +5888,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1325 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1353 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6214,7 +5898,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_64_BITS_66_TO_64_65_EQ_ETC___d1337 = + assign NOT_mmioPlatform_curReq_92_BITS_66_TO_64_93_EQ_ETC___d1365 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6224,96 +5908,105 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 = + assign NOT_mmioPlatform_mtip_0_93_00_AND_mmioPlatform_ETC___d508 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 || + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1028 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1056 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 && + !mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (!mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d838 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d866 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d956 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d984 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 && + !IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960 = + assign NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (!IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || !mmioPlatform_mtip_0) ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1499 = - { CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14, - x__h98832, - x__h98833 } ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1500 = - { CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15, - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16, - SEL_ARR_IF_propDstData_0_lat_0_whas__394_THEN__ETC___d1499 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1715 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1740 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1757 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1774 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1740, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1757, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1791 = - { CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1792 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1715, - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1774, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1791 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1797 = - { CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30, - !CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__528_THE_ETC___d1792, - x__h125469 } ; - assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1448 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 || - (IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446 ? - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390 : - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383) ; - assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1681 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 || - (IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679 ? - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523 : - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516) ; - assign _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 = - { 64'd0, - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4] } << - (mmio_axi4_adapter_read_req_addr[3] ? 32'd64 : 32'd0) ; - assign addr1__h88409 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign amo_req_data__h36993 = + assign SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1527 = + { CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + x__h100922, + x__h100923 } ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1528 = + { CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + SEL_ARR_IF_propDstData_0_lat_0_whas__422_THEN__ETC___d1527 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1743 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1768 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1785 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1802 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1768, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1785, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1819 = + { CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1820 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1743, + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1802, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1819 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1825 = + { CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, + !CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__556_THE_ETC___d1820, + x__h127559 } ; + assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1476 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 || + (IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474 ? + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418 : + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411) ; + assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1709 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 || + (IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707 ? + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551 : + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544) ; + assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat) ; + assign _theResult_____1_awsize_val__h17178 = + (x__h15205 + y__h15206 <= 5'd4) ? 3'b010 : 3'b011 ; + assign _theResult____h13554 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? + whichHalf___1__h15117 : + mmio_axi4_adapter_rg_wr_req_beat ; + assign addr1__h90499 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign amo_req_data__h39080 = (mmioPlatform_reqBE[3:0] == 4'd0 && mmioPlatform_reqBE[7:4] == 4'd0 && mmioPlatform_reqBE[11:8] == 4'd0 && @@ -6329,208 +6022,213 @@ module mkProc(CLK, ((mmioPlatform_reqBE[3:0] == 4'd0) ? mmioPlatform_reqData[63:32] : mmioPlatform_reqData[31:0]))) ; - assign b__h191029 = + assign b__h193221 = llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h4263 = + assign b__h2174 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554432 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556480 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_toHostAddr ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 = + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_fromHostAddr ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 ; + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ; - assign core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755 = - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497) && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ; + assign core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d503 && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d506 ; - assign core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731 = + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d531 && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d534 ; + assign core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759 = core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d495 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d497 ; - assign data__h138449 = + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d523 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d525 ; + assign data__h140598 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937[7:0] } ; - assign failed_testnum__h221515 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966[7:0] } ; + assign failed_testnum__h223700 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h137882 = + assign line_addr__h140031 = { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h147990 = + assign line_addr__h150142 = { llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h191238 = { llc$to_mem_toM_first[68:11], 6'h0 } ; - assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q37 = + assign line_addr__h193421 = { llc$to_mem_toM_first[68:11], 6'h0 } ; + assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34 = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q35 = + assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2218 = + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2247 = llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || llc$RDY_to_mem_rsFromM_enq && llc_axi4_adapter_f_pending_reads$EMPTY_N) ; - assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q36 = + assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2001 = - line_addr__h147990 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1902 = - line_addr__h137882 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q33 = + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2032 = + line_addr__h150142 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1931 = + line_addr__h140031 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q34 = + assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31 = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ; - assign lower_data__h42399 = - mmioPlatform_waitLowerMSIPCRs ? v__h42292 : 32'd0 ; - assign mmioPlatform_amoWaitWriteResp_271_OR_core_0_RD_ETC___d1274 = + assign lower_data__h44486 = + mmioPlatform_waitLowerMSIPCRs ? v__h44379 : 32'd0 ; + assign mem_req_rd_addr_arlen__h5411 = + (!whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? + 8'd1 : + 8'd0 ; + assign mmioPlatform_amoWaitWriteResp_299_OR_core_0_RD_ETC___d1302 = mmioPlatform_amoWaitWriteResp || core_0$RDY_mmioToPlatform_pRs_enq && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) ; - assign mmioPlatform_cycle_57_ULT_99___d458 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339 = + assign mmioPlatform_cycle_85_ULT_99___d486 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h57710 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 = - mmioPlatform_mtimecmp_0 <= newData__h51199 ; - assign mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 = + assign mmioPlatform_mtime__h59797 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 = + mmioPlatform_mtimecmp_0 <= newData__h53286 ; + assign mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd0 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd1 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd2 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd3 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd4 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd5 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd6 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd7 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd8 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -6544,162 +6242,215 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_first[148:145] != 4'd6 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd7 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd8 ; - assign mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727 = + assign mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492 ; - assign mmioPlatform_reqAmofunc__h86179 = mmioPlatform_reqAmofunc ; - assign mmioPlatform_reqFunc_69_BITS_3_TO_0_09_CONCAT__ETC___d877 = + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520 ; + assign mmioPlatform_reqAmofunc__h88269 = mmioPlatform_reqAmofunc ; + assign mmioPlatform_reqFunc_97_BITS_3_TO_0_37_CONCAT__ETC___d905 = { mmioPlatform_reqFunc[3:0], - (IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] && - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0]) ? + (IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] && + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0]) ? 2'd1 : 2'd2, 2'd0 } ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d1016 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d1044 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (!mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d996 || + (mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioPlat_ETC___d1024 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d796 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d824 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_71_ETC___d941 = + assign mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_99_ETC___d969 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (!IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70__ETC___d924 || + (IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98__ETC___d952 || !mmioPlatform_mtip_0) ; - assign mmio_axi4_adapter_f_rsps_to_core_first__258_BI_ETC___d1359 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) && + mmio_axi4_adapter_cfg_verbosity != 4'd0 ; + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252 = + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) && + mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15 ; + assign mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8 = + mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && + (mmio_axi4_adapter_soc_map$m_is_IO_addr ? + mmio_axi4_adapter_master_shim_arff$FULL_N : + mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; + assign mmio_axi4_adapter_f_rsps_to_core_first__286_BI_ETC___d1387 = { mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmioPlatform_fetchingWay, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - IF_mmioPlatform_fetchingWay_330_THEN_mmioPlatf_ETC___d1356 : + IF_mmioPlatform_fetchingWay_358_THEN_mmioPlatf_ETC___d1384 : mmioPlatform_fetchedInsts_0 } ; - assign mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q13 = - mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[96:0] ; - assign mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q11 = - mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[96:0] ; - assign mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q12 = - mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign newData__h43098 = + assign mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 = + mmio_axi4_adapter_read_req_addr[3] + + mmio_axi4_adapter_rg_rd_rsp_beat ; + assign mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187 = + { mmio_axi4_adapter_rspData[128], + mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 ? + { mmio_axi4_adapter_master_shim_rff$D_OUT[67:4], + mmio_axi4_adapter_rspData[63:0] } : + { mmio_axi4_adapter_rspData[127:64], + mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; + assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d210 = + mmio_axi4_adapter_soc_map$m_is_IO_addr && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat) ; + assign newData__h45185 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d887[63:0] : - x__h46411 ; - assign newData__h51199 = + amoExec___d915[63:0] : + x__h48498 ; + assign newData__h53286 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d973[63:0] : - x__h54489 ; - assign upper_data__h42400 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h42255 ; - assign v__h42255 = mmioPlatform_waitUpperMSIPCRs ? v__h42292 : 32'd0 ; - assign v__h42292 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign v_awaddr__h212729 = { llc$to_mem_toM_first[643:586], 6'h0 } ; - assign v_awsize_val__h15192 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:133] == 4'd0 || - mmio_axi4_adapter_f_reqs_from_core$D_OUT[132:129] == 4'd0) ? - 3'b010 : - 3'b011 ; - assign value__h59417 = mmioPlatform_mtimecmp_0 ; - assign x__h114170 = - !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__604_THEN_enqDst_1_0__ETC___d1645 ; - assign x__h120734 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 ? - srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__513_THEN_NOT_pro_ETC___d1679 ; - assign x__h46411 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d914, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_mtimecmp_0[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_mtimecmp_0[7:0] } ; - assign x__h54489 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d989, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_mtime[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_mtime[7:0] } ; - assign x__h62366 = - { IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[7] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[63:56] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[6] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[55:48] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[5] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[47:40] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[4] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[39:32] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[3] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[31:24] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[2] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[23:16] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - 8'd0, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - 8'd0 } ; - assign x__h66321 = - (mmioPlatform_reqFunc[5:4] != 2'd0 && - mmioPlatform_reqFunc[5:4] != 2'd1 && - mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1096[63:0] : - x__h68995 ; - assign x__h68995 = - { IF_IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ__ETC___d1112, - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[1] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[15:8] : - mmioPlatform_fromHostQ_data_0[15:8], - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d872[0] ? - IF_mmioPlatform_reqBE_72_BITS_7_TO_0_66_EQ_0_6_ETC___d885[7:0] : - mmioPlatform_fromHostQ_data_0[7:0] } ; - assign x__h71490 = - (mmioPlatform_reqFunc[5:4] != 2'd0 && - mmioPlatform_reqFunc[5:4] != 2'd1 && - mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1043[63:0] : - x__h62366 ; - assign x__h77037 = mmioPlatform_fromHostQ_data_0 ; - assign x__h98632 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 ? + amoExec___d1001[63:0] : + x__h56576 ; + assign upper_data__h44487 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44342 ; + assign v__h44342 = mmioPlatform_waitUpperMSIPCRs ? v__h44379 : 32'd0 ; + assign v__h44379 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign v_awaddr__h214914 = { llc$to_mem_toM_first[643:586], 6'h0 } ; + assign value__h61504 = mmioPlatform_mtimecmp_0 ; + assign whichHalf___1__h15117 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; + assign x__h100722 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 ? srcRR_0 : - IF_propDstIdx_0_lat_0_whas__380_THEN_NOT_propD_ETC___d1446 ; - assign x_data__h39934 = { 31'd0, mmioPlatform_reqData[0] } ; + IF_propDstIdx_0_lat_0_whas__408_THEN_NOT_propD_ETC___d1474 ; + assign x__h10759 = mmio_axi4_adapter_rg_rd_rsp_beat + 1'd1 ; + assign x__h116260 = + !CAN_FIRE_RL_doEnq_1 && + IF_enqDst_1_0_lat_0_whas__632_THEN_enqDst_1_0__ETC___d1673 ; + assign x__h122824 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 ? + srcRR_1_0 : + IF_propDstIdx_1_0_lat_0_whas__541_THEN_NOT_pro_ETC___d1707 ; + assign x__h15205 = x__h15217 + y__h15218 ; + assign x__h15217 = x__h15229 + y__h15230 ; + assign x__h15229 = x__h15241 + y__h15242 ; + assign x__h15241 = x__h15253 + y__h15254 ; + assign x__h15253 = x__h15265 + y__h15266 ; + assign x__h15265 = x__h15277 + y__h15278 ; + assign x__h15277 = x__h15289 + y__h15290 ; + assign x__h15289 = x__h15301 + y__h15302 ; + assign x__h15301 = x__h15313 + y__h15314 ; + assign x__h15313 = x__h15325 + y__h15326 ; + assign x__h15325 = x__h15337 + y__h15338 ; + assign x__h15337 = x__h15349 + y__h15350 ; + assign x__h15349 = x__h15361 + y__h15362 ; + assign x__h15361 = x__h15373 + y__h15374 ; + assign x__h15373 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144] } ; + assign x__h17973 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; + assign x__h48498 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d942, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_mtimecmp_0[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_mtimecmp_0[7:0] } ; + assign x__h56576 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1017, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_mtime[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_mtime[7:0] } ; + assign x__h64456 = + { IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[7] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[63:56] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[6] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[55:48] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[5] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[47:40] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[4] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[39:32] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[3] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[31:24] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[2] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[23:16] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + 8'd0, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + 8'd0 } ; + assign x__h68411 = + (mmioPlatform_reqFunc[5:4] != 2'd0 && + mmioPlatform_reqFunc[5:4] != 2'd1 && + mmioPlatform_reqFunc[5:4] != 2'd2) ? + amoExec___d1124[63:0] : + x__h71085 ; + assign x__h71085 = + { IF_IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ__ETC___d1140, + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[1] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[15:8] : + mmioPlatform_fromHostQ_data_0[15:8], + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d900[0] ? + IF_mmioPlatform_reqBE_00_BITS_7_TO_0_94_EQ_0_9_ETC___d913[7:0] : + mmioPlatform_fromHostQ_data_0[7:0] } ; + assign x__h73580 = + (mmioPlatform_reqFunc[5:4] != 2'd0 && + mmioPlatform_reqFunc[5:4] != 2'd1 && + mmioPlatform_reqFunc[5:4] != 2'd2) ? + amoExec___d1071[63:0] : + x__h64456 ; + assign x__h79127 = mmioPlatform_fromHostQ_data_0 ; + assign x_data__h42021 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h15206 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[129] } ; + assign y__h15218 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[130] } ; + assign y__h15230 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[131] } ; + assign y__h15242 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[132] } ; + assign y__h15254 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[133] } ; + assign y__h15266 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[134] } ; + assign y__h15278 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[135] } ; + assign y__h15290 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[136] } ; + assign y__h15302 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[137] } ; + assign y__h15314 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[138] } ; + assign y__h15326 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[139] } ; + assign y__h15338 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[140] } ; + assign y__h15350 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141] } ; + assign y__h15362 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[142] } ; + assign y__h15374 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[143] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h185995 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h185995 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h185995 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h185995 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h185995 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h185995 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h185995 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h185995 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h188147 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h188147 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h188147 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h188147 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h188147 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h188147 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h188147 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h188147 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) @@ -6754,49 +6505,71 @@ module mkProc(CLK, begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) 2'd0: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1; 2'd1: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2; 2'd2: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3; 2'd3: - v_wdata__h213140 = + v_wdata__h215325 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: v_wstrb__h213141 = llc$to_mem_toM_first[523:516]; - 3'd1: v_wstrb__h213141 = llc$to_mem_toM_first[531:524]; - 3'd2: v_wstrb__h213141 = llc$to_mem_toM_first[539:532]; - 3'd3: v_wstrb__h213141 = llc$to_mem_toM_first[547:540]; - 3'd4: v_wstrb__h213141 = llc$to_mem_toM_first[555:548]; - 3'd5: v_wstrb__h213141 = llc$to_mem_toM_first[563:556]; - 3'd6: v_wstrb__h213141 = llc$to_mem_toM_first[571:564]; - 3'd7: v_wstrb__h213141 = llc$to_mem_toM_first[579:572]; + 3'd0: v_wstrb__h215326 = llc$to_mem_toM_first[523:516]; + 3'd1: v_wstrb__h215326 = llc$to_mem_toM_first[531:524]; + 3'd2: v_wstrb__h215326 = llc$to_mem_toM_first[539:532]; + 3'd3: v_wstrb__h215326 = llc$to_mem_toM_first[547:540]; + 3'd4: v_wstrb__h215326 = llc$to_mem_toM_first[555:548]; + 3'd5: v_wstrb__h215326 = llc$to_mem_toM_first[563:556]; + 3'd6: v_wstrb__h215326 = llc$to_mem_toM_first[571:564]; + 3'd7: v_wstrb__h215326 = llc$to_mem_toM_first[579:572]; + endcase + end + always@(_theResult____h13554 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) + begin + case (_theResult____h13554) + 1'd0: + wflit_wdata__h18041 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]; + 1'd1: + wflit_wdata__h18041 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64]; + endcase + end + always@(_theResult____h13554 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) + begin + case (_theResult____h13554) + 1'd0: + wflit_wstrb__h18042 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129]; + 1'd1: + wflit_wstrb__h18042 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) - 2'd0: v_wuser__h213143 = llc$to_mem_toM_first[512]; - 2'd1: v_wuser__h213143 = llc$to_mem_toM_first[513]; - 2'd2: v_wuser__h213143 = llc$to_mem_toM_first[514]; - 2'd3: v_wuser__h213143 = llc$to_mem_toM_first[515]; + 2'd0: v_wuser__h215328 = llc$to_mem_toM_first[512]; + 2'd1: v_wuser__h215328 = llc$to_mem_toM_first[513]; + 2'd2: v_wuser__h215328 = llc$to_mem_toM_first[514]; + 2'd3: v_wuser__h215328 = llc$to_mem_toM_first[515]; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811 = + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_0_ETC___d811 = + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_0_ETC___d839 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6804,21 +6577,21 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 2'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 2'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; 2'd2: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64]; 2'd3: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929 or + IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6826,11 +6599,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = - IF_IF_NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4__ETC___d929; + IF_IF_NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4__ETC___d957; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005 or + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6838,452 +6611,452 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d1005; + IF_mmioPlatform_mtimecmp_0_94_ULE_IF_NOT_mmioP_ETC___d1033; endcase end always@(srcRR_0 or - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383 or - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390) + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411 or + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418) begin case (srcRR_0) 1'd0: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 = - IF_propDstIdx_0_lat_0_whas__380_THEN_propDstId_ETC___d1383; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 = + IF_propDstIdx_0_lat_0_whas__408_THEN_propDstId_ETC___d1411; 1'd1: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__380_THEN_p_ETC___d1444 = - IF_propDstIdx_1_lat_0_whas__387_THEN_propDstId_ETC___d1390; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__408_THEN_p_ETC___d1472 = + IF_propDstIdx_1_lat_0_whas__415_THEN_propDstId_ETC___d1418; endcase end always@(srcRR_1_0 or - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516 or - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523) + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544 or + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551) begin case (srcRR_1_0) 1'd0: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 = - IF_propDstIdx_1_0_lat_0_whas__513_THEN_propDst_ETC___d1516; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 = + IF_propDstIdx_1_0_lat_0_whas__541_THEN_propDst_ETC___d1544; 1'd1: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__513_THEN_ETC___d1677 = - IF_propDstIdx_1_1_lat_0_whas__520_THEN_propDst_ETC___d1523; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__541_THEN_ETC___d1705 = + IF_propDstIdx_1_1_lat_0_whas__548_THEN_propDst_ETC___d1551; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - x__h98832 = + x__h100922 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]; 1'd1: - x__h98832 = + x__h100922 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - x__h98833 = + x__h100923 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]; 1'd1: - x__h98833 = + x__h100923 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q14 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q15 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q16 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]; endcase end - always@(x__h98632 or + always@(x__h100722 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h98632) + case (x__h100722) 1'd0: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]; 1'd1: - CASE_x8632_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q17 = + CASE_x00722_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]; endcase end - always@(x__h120734 or - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559 or - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597) + always@(x__h122824 or + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587 or + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625) begin - case (x__h120734) + case (x__h122824) 1'd0: - x__h125469 = - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1559; + x__h127559 = + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1587; 1'd1: - x__h125469 = - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1597; + x__h127559 = + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1625; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516] : propDstData_1_0_rl[516]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516] : propDstData_1_1_rl[516]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515] : propDstData_1_0_rl[515]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515] : propDstData_1_1_rl[515]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[514] : propDstData_1_0_rl[514]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[514] : propDstData_1_1_rl[514]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q27 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q29 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513]; endcase end - always@(x__h120734 or - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538 or - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576) + always@(x__h122824 or + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566 or + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30 = - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1538; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1566; 1'd1: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q30 = - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1576; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1604; endcase end - always@(x__h120734 or + always@(x__h122824 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[517] : !propDstData_1_0_rl[517]; 1'd1: - CASE_x20734_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q31 = + CASE_x22824_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[517] : !propDstData_1_1_rl[517]; endcase end - always@(x__h120734 or - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533 or - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571) + always@(x__h122824 or + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561 or + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599) begin - case (x__h120734) + case (x__h122824) 1'd0: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32 = - IF_propDstData_1_0_lat_0_whas__528_THEN_propDs_ETC___d1533; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_0_lat_0_whas__556_THEN_propDs_ETC___d1561; 1'd1: - CASE_x20734_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q32 = - IF_propDstData_1_1_lat_0_whas__566_THEN_propDs_ETC___d1571; + CASE_x22824_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_1_lat_0_whas__594_THEN_propDs_ETC___d1599; endcase end always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or @@ -7291,28 +7064,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1937 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1966 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7320,14 +7093,14 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32]) - 3'd0: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h148173 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h150325 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7355,7 +7128,6 @@ module mkProc(CLK, 74'h0AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY 75'h2AAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0; llc_mem_server_axi4_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY @@ -7400,21 +7172,12 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY - 1'd0; - mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY - 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY - 7'd42; - mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY - 73'h0AAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY - 75'h2AAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmio_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmio_axi4_adapter_rspData <= `BSV_ASSIGNMENT_DELAY 129'd0; propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7460,9 +7223,6 @@ module mkProc(CLK, if (llc_axi4_adapter_master_xactor_shim_wff_rv$EN) llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN; - if (llc_axi4_adapter_rg_rd_req_beat$EN) - llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY - llc_axi4_adapter_rg_rd_req_beat$D_IN; if (llc_axi4_adapter_rg_rd_rsp_beat$EN) llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_rd_rsp_beat$D_IN; @@ -7565,24 +7325,15 @@ module mkProc(CLK, if (mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN) mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN; - if (mmio_axi4_adapter_master_xactor_clearing$EN) - mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_clearing$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_arff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_awff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_bff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_rff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN; - if (mmio_axi4_adapter_master_xactor_shim_wff_rv$EN) - mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY - mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN; + if (mmio_axi4_adapter_rg_rd_rsp_beat$EN) + mmio_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rg_rd_rsp_beat$D_IN; + if (mmio_axi4_adapter_rg_wr_req_beat$EN) + mmio_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rg_wr_req_beat$D_IN; + if (mmio_axi4_adapter_rspData$EN) + mmio_axi4_adapter_rspData <= `BSV_ASSIGNMENT_DELAY + mmio_axi4_adapter_rspData$D_IN; if (propDstData_0_rl$EN) propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN; if (propDstData_1_0_rl$EN) @@ -7669,7 +7420,6 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_rg_cline = 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_rg_rd_req_beat = 3'h2; llc_axi4_adapter_rg_rd_rsp_beat = 3'h2; llc_axi4_adapter_rg_wr_req_beat = 3'h2; llc_mem_server_axi4_slave_xactor_clearing = 1'h0; @@ -7723,15 +7473,10 @@ module mkProc(CLK, mmioPlatform_waitUpperMSIPCRs = 1'h0; mmio_axi4_adapter_cfg_verbosity = 4'hA; mmio_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA; - mmio_axi4_adapter_master_xactor_clearing = 1'h0; - mmio_axi4_adapter_master_xactor_shim_arff_rv = - 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_awff_rv = - 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_bff_rv = 7'h2A; - mmio_axi4_adapter_master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA; mmio_axi4_adapter_read_req_addr = 64'hAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_rg_rd_rsp_beat = 1'h0; + mmio_axi4_adapter_rg_wr_req_beat = 1'h0; + mmio_axi4_adapter_rspData = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl = 584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7757,14 +7502,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h221935 = $stime; + v__h224105 = $stime; #0; end - v__h221929 = v__h221935 / 32'd10; + v__h224099 = v__h224105 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h221929, + v__h224099, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -7774,14 +7519,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h221472 = $stime; + v__h223657 = $stime; #0; end - v__h221466 = v__h221472 / 32'd10; + v__h223651 = v__h223657 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h221466, + v__h223651, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7791,22 +7536,280 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h221515); + $display("FAIL %0d", failed_testnum__h223700); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h11342 = $stime; + v__h9702 = $stime; #0; end - v__h11336 = v__h11342 / 32'd10; + v__h9696 = v__h9702 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_handle_read_rsps ", v__h9696); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[71:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd1 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + begin + v__h9897 = $stime; + #0; + end + v__h9891 = v__h9897 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $display("%0d: %m.rl_handle_read_rsp: fabric response error", + v__h9891); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[71:68]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[67:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd1 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0 && + !mmio_axi4_adapter_master_shim_rff$D_OUT[1]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_rff$D_OUT[0], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" Response MMIO to core: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("MMIODataPRs { ", "valid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] == 2'd0) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_rff$D_OUT[3:2] != 2'd0) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("TaggedData { ", "tag: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_rspData[128]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !mmio_axi4_adapter_rspData[128]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "data: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: St request:", v__h11336); + begin + v__h11307 = $stime; + #0; + end + v__h11301 = v__h11307 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%d: %m.rl_handle_write_req: St request:", v__h11301); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8128,37 +8131,259 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) begin - v__h15880 = $stime; + v__h17239 = $stime; #0; end - v__h15874 = v__h15880 / 32'd10; + v__h17233 = v__h17239 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h15874); + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $display("%d: %m.rl_handle_write_req: sent aw flit:", v__h17233); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", mem_req_rd_addr_arlen__h5411); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", _theResult_____1_awsize_val__h17178, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d246) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) + begin + v__h17410 = $stime; + #0; + end + v__h17404 = v__h17410 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) + $display("%0d: ERROR: CreditCounter: overflow", v__h17404); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d252) $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + begin + v__h18103 = $stime; + #0; + end + v__h18097 = v__h18103 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%d: %m.rl_handle_write_req: sent w flit:", v__h18097); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", wflit_wdata__h18041); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", wflit_wstrb__h18042); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + !whichHalf___1__h15117 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + !mmio_axi4_adapter_rg_wr_req_beat) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + (whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat)) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + mmio_axi4_adapter_soc_map$m_is_IO_addr && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("first: %d, last: %d, whichHalf: %d", + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + !mmio_axi4_adapter_rg_wr_req_beat, + whichHalf___1__h15117 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat, + _theResult____h13554, + "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h16023 = $stime; + v__h18189 = $stime; #0; end - v__h16017 = v__h16023 / 32'd10; + v__h18183 = v__h18189 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h16017); + v__h18183); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8552,14 +8777,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4363 = $stime; + v__h2280 = $stime; #0; end - v__h4357 = v__h4363 / 32'd10; + v__h2274 = v__h2280 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_req: Ld request", v__h4357); + $display("%0d: %m.rl_handle_read_req: Ld request", v__h2274); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8912,7 +9137,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 8'd0); + $write("'h%h", mem_req_rd_addr_arlen__h5411); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9008,16 +9233,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h7984 = $stime; + v__h7388 = $stime; #0; end - v__h7978 = v__h7984 / 32'd10; + v__h7382 = v__h7388 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response", - v__h7978); + v__h7382); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9408,16 +9633,137 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h19409 = $stime; + v__h20501 = $stime; #0; end - v__h19403 = v__h19409 / 32'd10; + v__h20495 = v__h20501 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_discard_write_rsp", v__h20495); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_bff$D_OUT[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd1 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + begin + v__h21031 = $stime; + #0; + end + v__h21025 = v__h21031 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", + v__h21025); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("'h%h", mmio_axi4_adapter_master_shim_bff$D_OUT[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd1 && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && + mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) + begin + v__h21496 = $stime; + #0; + end + v__h21490 = v__h21496 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h19403); + v__h21490); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9707,572 +10053,130 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - begin - v__h18412 = $stime; - #0; - end - v__h18406 = v__h18412 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h18406); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_BFlit { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd0) - $write("OKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - begin - v__h18942 = $stime; - #0; - end - v__h18936 = v__h18942 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h18936); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("AXI4_BFlit { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && - mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != - 2'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - begin - v__h10403 = $stime; - #0; - end - v__h10397 = v__h10403 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_handle_read_rsps ", v__h10397); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_RFlit { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0) - $write("OKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - begin - v__h10598 = $stime; - #0; - end - v__h10592 = v__h10598 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $display("%0d: %m.rl_handle_read_rsp: fabric response error", - v__h10592); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("AXI4_RFlit { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd1) - $write("EXOKAY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd2) - $write("SLVERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd1 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd2) - $write("DECERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0 && - !mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("'h%h", - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" Response MMIO to core: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("MMIODataPRs { ", "valid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == - 2'd0) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != - 2'd0) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("TaggedData { ", "tag: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write("[Platform - SelectReq] timer interrupt", ", mtime %x", mmioPlatform_mtime, ", mtimcmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(", old mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(", new interrupts "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) + mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("[Platform - SelectReq] core %d, req ", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write("tagged Inst ", "'h%h", core_0$mmioToPlatform_cRq_first[145]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write("tagged Ld ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write("tagged St ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -10281,542 +10185,542 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d551) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d579) $write("Swap"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d557) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d585) $write("Add"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d563) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d591) $write("Xor"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d569) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d597) $write("And"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d575) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d603) $write("Or"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d581) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d609) $write("Min"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d587) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d615) $write("Max"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d593) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d621) $write("Minu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d599) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d627) $write("Maxu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d621) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d649) $write("None"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("TaggedData { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[128]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && !core_0$mmioToPlatform_cRq_first[128]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write(" req type "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_65_OR_NOT_mmioPlatform_mti_ETC___d727) + mmioPlatform_mtip_0_93_OR_NOT_mmioPlatform_mti_ETC___d755) $write("tagged MSIP ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && - core_0_mmioToPlatform_cRq_notEmpty__74_AND_cor_ETC___d731) + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && + core_0_mmioToPlatform_cRq_notEmpty__02_AND_cor_ETC___d759) $write("tagged MTimeCmp ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d736) + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d764) $write("tagged MTime ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d742) + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d770) $write("tagged ToHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d748) + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d776) $write("tagged FromHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d490 || - !core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d492) && - core_0_mmioToPlatform_cRq_first__88_BITS_214_T_ETC___d755) + (core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d518 || + !core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d520) && + core_0_mmioToPlatform_cRq_first__16_BITS_214_T_ETC___d783) $write("tagged MMIO_Fabric_Adapter ", "'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) && + !mmioPlatform_mtimecmp_0_94_ULE_mmioPlatform_mt_ETC___d495) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) @@ -10879,8 +10783,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h42399, - upper_data__h42400); + lower_data__h44486, + upper_data__h44487); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -10892,62 +10796,62 @@ module mkProc(CLK, mmioPlatform_mtimecmp_0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write("[Platform - process mtimecmp] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(", mtime %x", mmioPlatform_mtime, ", old mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d960) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h43098, "\n"); + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d988) + $write(", new mtimecmp[%d] %x", 1'd0, newData__h45185, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -10992,61 +10896,61 @@ module mkProc(CLK, mmioPlatform_mtime); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write("[Platform - process mtime] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) - $write(", new mtime %x", newData__h51199, ", mtimecmp "); + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) + $write(", new mtime %x", newData__h53286, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ__ETC___d1032) + NOT_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ__ETC___d1060) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeDone) @@ -11103,7 +11007,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1067) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1095) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11129,13 +11033,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_81_OR_mmioPlatfo_ETC___d1073, + IF_mmioPlatform_toHostQ_empty_09_OR_mmioPlatfo_ETC___d1101, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_81_THEN_0_ELSE_I_ETC___d1071, + IF_mmioPlatform_toHostQ_empty_09_THEN_0_ELSE_I_ETC___d1099, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11172,12 +11076,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1138) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1166) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_69_BITS_5_TO_4_70_EQ_2_ETC___d1121) + IF_mmioPlatform_reqFunc_97_BITS_5_TO_4_98_EQ_2_ETC___d1149) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11203,13 +11107,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_47_OR_mmioPlat_ETC___d1126, + IF_mmioPlatform_fromHostQ_empty_75_OR_mmioPlat_ETC___d1154, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_47_THEN_0_ELSE_ETC___d1124, + IF_mmioPlatform_fromHostQ_empty_75_THEN_0_ELSE_ETC___d1152, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11704,7 +11608,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", addr1__h88409); + $write("'h%h", addr1__h90499); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -11789,76 +11693,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $display(" fetchingWay %0d instSel %0d inst 0x%0h", mmioPlatform_fetchingWay, mmioPlatform_instSel, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1351); + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1379); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp: final resp to core:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_330_ULT_mmioPlatform__ETC___d1339) + !mmioPlatform_fetchingWay_358_ULT_mmioPlatform__ETC___d1367) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && @@ -11907,35 +11811,35 @@ module mkProc(CLK, !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_wSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_arSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_bSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_slvSynth_rSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h199123 = $stime; + v__h201308 = $stime; #0; end - v__h199117 = v__h199123 / 32'd10; + v__h201302 = v__h201308 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h199117); + v__h201302); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -13392,15 +13296,15 @@ module mkProc(CLK, llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h212832 = $stime; + v__h215017 = $stime; #0; end - v__h212826 = v__h212832 / 32'd10; + v__h215011 = v__h215017 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h212826); + $display("%0d: ERROR: CreditCounter: overflow", v__h215011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && @@ -13408,209 +13312,193 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h191102 = $stime; + v__h193285 = $stime; #0; end - v__h191096 = v__h191102 / 32'd10; + v__h193279 = v__h193285 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) - $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h191096, - llc_axi4_adapter_rg_rd_req_beat); + llc_axi4_adapter_cfg_verbosity != 4'd0) + $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory", + v__h193279); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("LdMemRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", llc$to_mem_toM_first[68:5]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0 && llc$to_mem_toM_first[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0 && !llc$to_mem_toM_first[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("'h%h", llc$to_mem_toM_first[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - llc_axi4_adapter_cfg_verbosity != 4'd0 && - llc_axi4_adapter_rg_rd_req_beat == 3'd0) + llc_axi4_adapter_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) - $write("'h%h", line_addr__h191238); + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) + $write("'h%h", line_addr__h193421); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_wSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_bSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) begin - v__h220458 = $stime; + v__h222643 = $stime; #0; end - v__h220452 = v__h220458 / 32'd10; + v__h222637 = v__h222643 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h220452); + v__h222637); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) @@ -13661,69 +13549,69 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop) - $display("WARNING: dropping from Source that can't be dropped from"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_arSynth_src_warnDoDrop) + $display("WARNING: %m - dropping from Source that can't be dropped from"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut) - $display("WARNING: putting into a Sink that can't be put into"); + if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_rSynth_snk_warnDoPut) + $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) begin - v__h191691 = $stime; + v__h193874 = $stime; #0; end - v__h191685 = v__h191691 / 32'd10; + v__h193868 = v__h193874 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h191685, + v__h193868, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13732,45 +13620,45 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) begin - v__h191877 = $stime; + v__h194060 = $stime; #0; end - v__h191871 = v__h191877 / 32'd10; + v__h194054 = v__h194060 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h191871); + v__h194054); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) @@ -13850,27 +13738,27 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207 && + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__189_U_ETC___d2207) + NOT_llc_axi4_adapter_cfg_verbosity_read__221_U_ETC___d2236) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v index 176b18d..93125a7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:03 BST 2020 +// On Wed Jun 24 20:28:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v index fd5a0ae..76c10b4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:08 BST 2020 +// On Wed Jun 24 20:29:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v index 07ad852..7aa37d4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:36:35 BST 2020 +// On Wed Jun 24 20:25:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v index e75ac21..7fa8e2d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:44 BST 2020 +// On Wed Jun 24 20:28:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v index e07452b..b46fbd0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:45:26 BST 2020 +// On Wed Jun 24 20:34:41 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v index bd6d4ae..2b2e2fc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:58 BST 2020 +// On Wed Jun 24 20:29:02 BST 2020 // // // Ports: @@ -8963,71 +8963,6 @@ module mkReservationStationFpuMulDiv(CLK, m_data_15[1]; endcase end - always@(idx__h87141 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h87141) - 4'd0: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_0[0]; - 4'd1: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_1[0]; - 4'd2: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_2[0]; - 4'd3: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_3[0]; - 4'd4: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_4[0]; - 4'd5: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_5[0]; - 4'd6: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_6[0]; - 4'd7: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_7[0]; - 4'd8: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_8[0]; - 4'd9: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_9[0]; - 4'd10: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_10[0]; - 4'd11: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_11[0]; - 4'd12: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_12[0]; - 4'd13: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_13[0]; - 4'd14: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_14[0]; - 4'd15: - SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = - m_data_15[0]; - endcase - end always@(idx__h87141 or m_data_0 or m_data_1 or @@ -9093,6 +9028,71 @@ module mkReservationStationFpuMulDiv(CLK, m_data_15[2]; endcase end + always@(idx__h87141 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h87141) + 4'd0: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_0[0]; + 4'd1: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_1[0]; + 4'd2: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_2[0]; + 4'd3: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_3[0]; + 4'd4: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_4[0]; + 4'd5: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_5[0]; + 4'd6: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_6[0]; + 4'd7: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_7[0]; + 4'd8: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_8[0]; + 4'd9: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_9[0]; + 4'd10: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_10[0]; + 4'd11: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_11[0]; + 4'd12: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_12[0]; + 4'd13: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_13[0]; + 4'd14: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_14[0]; + 4'd15: + SEL_ARR_m_data_0_73_BIT_0_519_m_data_1_76_BIT__ETC___d1536 = + m_data_15[0]; + endcase + end always@(idx__h87141 or m_data_0 or m_data_1 or diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v index b5be7f3..29350a6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:53 BST 2020 +// On Wed Jun 24 20:28:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v index 3b81235..cee4a98 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:39:13 BST 2020 +// On Wed Jun 24 20:28:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v index 131067b..0a7f7de 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:41:26 BST 2020 +// On Wed Jun 24 20:30:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v index bcc2e21..6d17c92 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:41:19 BST 2020 +// On Wed Jun 24 20:30:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v index 2095ab1..95ecaa4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:51 BST 2020 +// On Wed Jun 24 20:33:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v index 1d9b270..b60a26c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:04 BST 2020 +// On Wed Jun 24 20:24:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v index 7eb938c..c66410d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:38:54 BST 2020 +// On Wed Jun 24 20:27:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v index 84b7b29..f3adfdb 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:51 BST 2020 +// On Wed Jun 24 20:29:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v index 9a91803..7159584 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:38 BST 2020 +// On Wed Jun 24 20:24:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v index 4706f80..449811b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:36:07 BST 2020 +// On Wed Jun 24 20:25:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v index 707f069..3570f20 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:46 BST 2020 +// On Wed Jun 24 20:31:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v b/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v index 60af2a2..1a41439 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:42:46 BST 2020 +// On Wed Jun 24 20:31:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v b/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v index 7e42390..8ec3206 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:52 BST 2020 +// On Wed Jun 24 20:34:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v index 7b93571..1bf9ae5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v index 29fc3bc..4b153c6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:58 BST 2020 +// On Wed Jun 24 20:34:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v index 3d77cfe..d8f1d08 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:44:59 BST 2020 +// On Wed Jun 24 20:34:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v index 012d58a..6ccee51 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v index df685fc..cae3995 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v index 2699fb2..bdc6945 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v index 11c4ad2..c118fe7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v index 53f40d4..b2c85cf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v index a9de33f..3b0d41f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v index 3dea0ff..c8f3301 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v index b61d7ea..2c53437 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v index 50dce32..89c5e28 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:39 BST 2020 +// On Wed Jun 24 20:32:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v index 0830d8e..030a399 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:23 BST 2020 +// On Wed Jun 24 20:24:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v index f47d598..d911b0a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v index f3d83fd..5d8e2b6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:01 BST 2020 +// On Wed Jun 24 20:24:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v index 95627f3..192297d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v index c31d7fe..fda6208 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v b/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v index 3e899d6..46aa618 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:23 BST 2020 +// On Wed Jun 24 20:24:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v b/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v index 93414fd..0500e55 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:26 BST 2020 +// On Wed Jun 24 20:24:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v b/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v index c120409..3413ac0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:25 BST 2020 +// On Wed Jun 24 20:24:24 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v index b1ccbbb..1213985 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:27 BST 2020 +// On Wed Jun 24 20:24:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v index 81b141c..486ee3c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:04 BST 2020 +// On Wed Jun 24 20:29:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v index d42b9f5..fca467c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:40:01 BST 2020 +// On Wed Jun 24 20:29:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v index e851af6..a66d32f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:43:58 BST 2020 +// On Wed Jun 24 20:33:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v b/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v index 501bab3..4c58c0d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:23 BST 2020 +// On Wed Jun 24 20:24:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v b/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v index beaae24..e6585e1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:24 BST 2020 +// On Wed Jun 24 20:24:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v b/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v index a44941d..4f2e316 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 17 12:35:25 BST 2020 +// On Wed Jun 24 20:24:24 BST 2020 // // // Ports: