From a6771219ba64ed8673a1ab10c0f4b8e5d992efff Mon Sep 17 00:00:00 2001
From: jon <>
Date: Fri, 8 Jan 2021 11:57:46 +0000
Subject: [PATCH] Fold the fragment count into the standard pipeline structs.

---
 .../RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv  | 30 +++++++++++--------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index c84cf6f..8cee6da 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -186,6 +186,7 @@ typedef struct {
 `ifdef RVFI_DII
     Dii_Parcel_Id dii_pid;
 `endif
+    Bit#(TLog#(SupSizeX2)) inst_frags_fetched;
     Maybe#(PcCompressed) pred_next_pc;
     Bool decode_epoch;
     Epoch main_epoch;
@@ -196,6 +197,7 @@ typedef struct {
 `ifdef RVFI_DII
     Dii_Parcel_Id dii_pid;
 `endif
+    Bit#(TLog#(SupSizeX2)) inst_frags_fetched;
     Maybe#(PcCompressed) pred_next_pc;
     Maybe#(Exception) cause;
     Bool access_mmio; // inst fetch from MMIO
@@ -362,8 +364,8 @@ module mkFetchStage(FetchStage);
     Reg#(Epoch) f_main_epoch <- mkReg(0); // fetch estimate of main epoch
 
     // Pipeline Stage FIFOs
-    Fifo#(2, Tuple2#(Bit#(TLog#(SupSizeX2)),Fetch1ToFetch2)) f12f2 <- mkCFFifo;
-    Fifo#(4, Tuple2#(Bit#(TLog#(SupSizeX2)),Fetch2ToFetch3)) f22f3 <- mkCFFifo; // FIFO should match I$ latency
+    Fifo#(2, Fetch1ToFetch2) f12f2 <- mkCFFifo;
+    Fifo#(4, Fetch2ToFetch3) f22f3 <- mkCFFifo; // FIFO should match I$ latency
     // These two fifos needs a capacity of 3 for full throughput if we fire only when we can enq on on channels.
     SupFifo#(SupSizeX2, 3, Fetch3ToDecode) f32d <- mkUGSupFifo; // Unguarded to prevent the static analyser from exploding.
     SupFifo#(SupSize, 3, FromFetchStage) out_fifo <- mkSupFifo;
@@ -470,17 +472,18 @@ module mkFetchStage(FetchStage);
 `ifdef RVFI_DII
             dii_pid: dii_pid,
 `endif
+            inst_frags_fetched: posLastSupX2,
             pred_next_pc: isValid(pred_next_pc) ?
                 Valid(compressPc(ppc_idx, validValue(pred_next_pc))) : Invalid,
             decode_epoch: decode_epoch[0],
             main_epoch: f_main_epoch};
 
-        f12f2.enq(tuple2(posLastSupX2,out));
+        f12f2.enq(out);
         if (verbose) $display("Fetch1: ", fshow(out), " posLastSupX2: %d", posLastSupX2);
     endrule
 
     rule doFetch2;
-        let {nbSupX2,in} = f12f2.first;
+        let in = f12f2.first;
         f12f2.deq;
 
         // Get TLB response
@@ -511,7 +514,7 @@ module mkFetchStage(FetchStage);
                     // cache line size, so all nbSup+1 insts can be fetched
                     // from boot rom. It won't happen that insts fetched from
                     // boot rom is less than requested.
-                    mmio.bootRomReq(phys_pc, nbSupX2);
+                    mmio.bootRomReq(phys_pc, in.inst_frags_fetched);
                     access_mmio = True;
 `ifdef DEBUG_WEDGE
                     lastImemReq <= phys_pc;
@@ -539,17 +542,18 @@ module mkFetchStage(FetchStage);
 `ifdef RVFI_DII
             dii_pid: in.dii_pid,
 `endif
+            inst_frags_fetched: in.inst_frags_fetched,
             pred_next_pc: in.pred_next_pc,
             cause: cause,
             access_mmio: access_mmio,
             decode_epoch: in.decode_epoch,
             main_epoch: in.main_epoch };
-        f22f3.enq(tuple2(nbSupX2,out));
+        f22f3.enq(out);
 
        if (verbosity >= 2) begin
-          $display ("----------------");
-          $display ("Fetch2: TLB response pyhs_pc 0x%0h  cause ", phys_pc, fshow (cause));
-          $display ("Fetch2: f2_tof3.enq: nbSupX2 %0d out ", nbSupX2, fshow (out));
+	          $display ("----------------");
+	          $display ("Fetch2: TLB response pyhs_pc 0x%0h  cause ", phys_pc, fshow (cause));
+	          $display ("Fetch2: f2_tof3.enq: out ", fshow (out));
        end
     endrule
 
@@ -557,10 +561,10 @@ module mkFetchStage(FetchStage);
     Vector#(SupSizeX2,Integer) indexes = genVector;
     function Bool f32d_lane_notFull(Integer i) = f32d.enqS[i].canEnq;
     rule doFetch3(all(f32d_lane_notFull, indexes));
-        let {nbSupX2In, fetch3In} = f22f3.first;
+        let fetch3In = f22f3.first;
         if (verbosity >= 2) begin
             if (f22f3.notEmpty)
-                $display("Fetch3: nbSupX2In: %0d fetch3In: ", nbSupX2In, fshow (fetch3In));
+                $display("Fetch3: fetch3In: ", fshow (fetch3In));
             else
                 $display("Fetch3: Nothing else from Fetch2");
         end
@@ -592,7 +596,7 @@ module mkFetchStage(FetchStage);
 `endif
         end
 
-        for (Integer i = 0; i < valueOf(SupSizeX2) && fromInteger(i) <= nbSupX2In; i = i + 1) begin
+        for (Integer i = 0; i < valueOf(SupSizeX2) && fromInteger(i) <= fetch3In.inst_frags_fetched; i = i + 1) begin
            PcCompressed pc = fetch3In.pc;
            pc.lsb = pc.lsb + (2 * fromInteger(i));
            f32d.enqS[i].enq (Fetch3ToDecode {
@@ -600,7 +604,7 @@ module mkFetchStage(FetchStage);
 `ifdef RVFI_DII
                dii_pid: fetch3In.dii_pid + fromInteger(i),
 `endif
-               ppc: (fromInteger(i)==nbSupX2In) ? fetch3In.pred_next_pc : Invalid,
+               ppc: (fromInteger(i)==fetch3In.inst_frags_fetched) ? fetch3In.pred_next_pc : Invalid,
                inst_frag: validValue(inst_d[i]),
                cause: fetch3In.cause,
                decode_epoch: fetch3In.decode_epoch,