diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 7ce2467..dd31fff 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -735,8 +735,19 @@ module mkCore#(CoreId coreId)(Core);
     endinterface);
     CommitStage commitStage <- mkCommitStage(commitInput);
 
-`ifdef RVFI
+`ifdef RVFI_DII
     mkConnection(commitStage.rvfi, rvfi_bridge.rvfi);
+`else
+`ifdef RVFI
+    // XXX Currently RVFI can only be connected to the outside world
+    // via the RVFI_DII bridge i.e. when DII is also being used.
+    rule drop;
+        let packets <- commitStage.rvfi.get();
+        for (Integer i = 0; i < valueOf(SupSize); i = i+1) begin
+            if (isValid(packets[i])) $display("%t: RVFI ", $time, fshow(packets[i].Valid));
+        end
+    endrule
+`endif
 `endif
 
     // send rob enq time to reservation stations
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
index 8e14907..192f844 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -199,7 +199,7 @@ typedef struct {
     Addr addr;
     Trap trap;
     Bit #(32) orig_inst;
-`ifdef RVFI_DII
+`ifdef RVFI
     ToReorderBuffer x;
 `endif
 } CommitTrap deriving(Bits, FShow);
@@ -686,7 +686,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
             pc: x.pc,
             addr: vaddr,
             orig_inst: x.orig_inst
-`ifdef RVFI_DII
+`ifdef RVFI
             , x: x
 `endif
         });
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
index 2434320..3059123 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
@@ -260,7 +260,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
                               data,
 `endif
                               fflags
-`ifdef RVFI_DII
+`ifdef RVFI
                               , ExtraTraceBundle{regWriteData: data, memByteEn: ?}
 `endif
         );
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index b4d79ec..ac1310c 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -523,7 +523,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         });
     endrule
 
-`ifdef RVFI_DII
+`ifdef RVFI
     Vector#(TExp#(SizeOf#(LdStQTag)), Reg#(Data)) memData <- replicateM(mkReg(?));
 `endif
 
@@ -538,7 +538,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         CapPipe data = x.rVal2;
         MemTaggedData toMemData = unpack(pack(toMem(data)));
 
-`ifdef RVFI_DII
+`ifdef RVFI
         memData[pack(x.ldstq_tag)] <= getAddr(data);
         $display("%t : memData[%x] <= %x", $time(), pack(x.ldstq_tag), getAddr(data));
 `endif
diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
index 9840277..e03a490 100644
--- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
@@ -46,7 +46,7 @@ import MemoryTypes::*;
 import CHERICap::*;
 import CHERICC_Fat::*;
 import ISA_Decls_CHERI::*;
-`ifdef RVFI_DII
+`ifdef RVFI
 import GetPut::*;
 import RVFI_DII_Types::*;
 `endif
@@ -86,8 +86,10 @@ typedef struct {
 `endif
 } InstTag deriving(Bits, Eq, FShow);
 
-`ifdef RVFI_DII
+`ifdef RVFI
 typedef Vector#(SupSize, Maybe#(RVFI_DII_Execution #(64, 64))) Rvfi_Traces;
+`endif
+`ifdef RVFI_DII
 typedef Vector#(TMul#(SupSize, 2), RVFI_DII_Parcel_Resp) Dii_Parcel_Resps;
 typedef Vector#(TMul#(SupSize, 2), Bit#(16)) Dii_Parcels;