From a8299cfc018965e2ea1a12107cf5d25ec73cb1af Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Sun, 2 Nov 2025 14:24:17 +0000 Subject: [PATCH] CCTypes: Fix misleading bit width for MESI/Msi enum 4 does not fit in 2 bits. This appears to not matter in practice, as a spot check of the generated Verilog shows 3'dN for state-related constants, but we should not be relying on this surprisingly lax behaviour from bsc, and who knows if there are ways in which bsc does end up using the as-written bit width somewhere. Fixes: 6d4644ce7310 ("Add tag-only state to MESI and interface with tagOnlyReq of tag controller") --- src_Core/RISCY_OOO/coherence/src/CCTypes.bsv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src_Core/RISCY_OOO/coherence/src/CCTypes.bsv b/src_Core/RISCY_OOO/coherence/src/CCTypes.bsv index 08fab81..e822b64 100644 --- a/src_Core/RISCY_OOO/coherence/src/CCTypes.bsv +++ b/src_Core/RISCY_OOO/coherence/src/CCTypes.bsv @@ -46,11 +46,11 @@ import GetPut::*; import ClientServer::*; typedef enum { - I = 2'd0, - T = 2'd1, - S = 2'd2, - E = 2'd3, - M = 2'd4 + I = 3'd0, + T = 3'd1, + S = 3'd2, + E = 3'd3, + M = 3'd4 } MESI deriving(Bits, Eq, FShow); typedef MESI Msi;