From a8c4ce073d7a764c2e987c07fa78c6512c27029a Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Mon, 12 Jul 2021 15:21:58 +0100 Subject: [PATCH] Factor out bsc flags to include_common --- .../Makefile | 49 ++++--------------- .../Makefile | 48 ++++-------------- .../Makefile | 47 ++---------------- .../Makefile | 48 ++---------------- builds/Resources/Include_Common.mk | 31 ++++++++++++ 5 files changed, 59 insertions(+), 164 deletions(-) diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile index 763e626..c39df8c 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile @@ -1,21 +1,9 @@ ### -*-Makefile-*- # ================================================================ -# Path to RISCY-OOO sources +# Path to RISCY-OOO sources not included in Common -RISCY_HOME ?= ../../src_Core/RISCY_OOO -# RISCY_HOME ?= $(HOME)/Projects/RISCV/MIT-riscy/riscy-OOO - -RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib - -CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv - -RVFI_DII_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII - -CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib - -# ALL_RISCY_DIRS = $(RISCY_DIRS) -ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(RVFI_DII_DIRS):$(CHERI_DIRS) +ALL_RISCY_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII # ================================================================ @@ -26,45 +14,26 @@ ARCH ?= RV64ACDFIMSUxCHERI # RISC-V config macros passed into Bluespec 'bsc' compiler BSC_COMPILATION_FLAGS += \ - -D RV64 \ - -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ - -D SV39 \ - -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \ - -D SHIFT_BARREL \ - -D MULT_SYNTH \ - -D Near_Mem_Caches \ - -D FABRIC64 \ - -D CheriBusBytes=8 \ - -D CheriMasterIDWidth=1 \ - -D CheriTransactionIDWidth=5 \ - -D CAP128 -D BLUESIM \ - -D PERFORMANCE_MONITORING \ - -D MEM64 \ - -D RISCV \ -D RVFI_DII \ -D RVFI \ -D CONTRACTS_VERIFY \ - # Default ISA test TEST ?= rv64ui-p-add -#================================================================ -# Parameter settings for MIT RISCY - -BSC_COMPILATION_FLAGS += -D BSIM \ - - -CACHE_SIZE ?= TEST - -include $(REPO)/builds/Resources/Include_RISCY_Config.mk - #================================================================ # Common boilerplate rules include $(REPO)/builds/Resources/Include_Common.mk +#================================================================ +# Parameter settings for MIT RISCY + +CACHE_SIZE ?= TEST + +include $(REPO)/builds/Resources/Include_RISCY_Config.mk + #================================================================ # Makefile rules for building for specific simulator: bluesim diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile index e92ce69..6f776b0 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile @@ -1,21 +1,9 @@ ### -*-Makefile-*- # ================================================================ -# Path to RISCY-OOO sources +# Path to RISCY-OOO sources not included in Common -RISCY_HOME ?= ../../src_Core/RISCY_OOO -# RISCY_HOME ?= $(HOME)/Projects/RISCV/MIT-riscy/riscy-OOO - -RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib - -CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv - -RVFI_DII_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII - -CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib - -# ALL_RISCY_DIRS = $(RISCY_DIRS) -ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(RVFI_DII_DIRS):$(CHERI_DIRS) +ALL_RISCY_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII # ================================================================ @@ -26,43 +14,25 @@ ARCH ?= RV64ACDFIMSUxCHERI # RISC-V config macros passed into Bluespec 'bsc' compiler BSC_COMPILATION_FLAGS += \ - -D RV64 \ - -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ - -D SV39 \ - -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \ - -D SHIFT_BARREL \ - -D MULT_SYNTH \ - -D Near_Mem_Caches \ - -D FABRIC64 \ - -D CheriBusBytes=8 \ - -D CheriMasterIDWidth=1 \ - -D CheriTransactionIDWidth=5 \ - -D CAP128 -D BLUESIM \ - -D MEM64 \ - -D RISCV \ -D RVFI_DII \ -D RVFI \ - # Default ISA test TEST ?= rv64ui-p-add -#================================================================ -# Parameter settings for MIT RISCY - -BSC_COMPILATION_FLAGS += -D BSIM \ - - -CACHE_SIZE ?= TEST - -include $(REPO)/builds/Resources/Include_RISCY_Config.mk - #================================================================ # Common boilerplate rules include $(REPO)/builds/Resources/Include_Common.mk +#================================================================ +# Parameter settings for MIT RISCY + +CACHE_SIZE ?= TEST + +include $(REPO)/builds/Resources/Include_RISCY_Config.mk + #================================================================ # Makefile rules for building for specific simulator: verilator diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile index ecc3d43..a29def0 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile @@ -1,62 +1,25 @@ ### -*-Makefile-*- -# ================================================================ -# Path to RISCY-OOO sources - -RISCY_HOME ?= ../../src_Core/RISCY_OOO -# RISCY_HOME ?= $(HOME)/Projects/RISCV/MIT-riscy/riscy-OOO - -RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib - -CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv - -CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib - -# ALL_RISCY_DIRS = $(RISCY_DIRS) -ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS) - -# ================================================================ - REPO ?= ../.. ARCH ?= RV64ACDFIMSUxCHERI # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler -BSC_COMPILATION_FLAGS += \ - -D RV64 \ - -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ - -D SV39 \ - -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \ - -D SHIFT_BARREL \ - -D MULT_SYNTH \ - -D Near_Mem_Caches \ - -D FABRIC64 \ - -D CheriBusBytes=8 \ - -D CheriMasterIDWidth=1 \ - -D CheriTransactionIDWidth=5 \ - -D CAP128 -D BLUESIM \ - -D MEM64 \ - -D RISCV \ - - # Default ISA test TEST ?= rv64ui-p-add -#================================================================ -# Parameter settings for MIT RISCY - -BSC_COMPILATION_FLAGS += -D BSIM \ - - -include $(REPO)/builds/Resources/Include_RISCY_Config.mk - #================================================================ # Common boilerplate rules include $(REPO)/builds/Resources/Include_Common.mk +#================================================================ +# Parameter settings for MIT RISCY + +include $(REPO)/builds/Resources/Include_RISCY_Config.mk + #================================================================ # Makefile rules for building for specific simulator: bluesim diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile index 03f4209..b111495 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile @@ -1,63 +1,25 @@ ### -*-Makefile-*- -# ================================================================ -# Path to RISCY-OOO sources - -RISCY_HOME ?= ../../src_Core/RISCY_OOO -# RISCY_HOME ?= $(HOME)/Projects/RISCV/MIT-riscy/riscy-OOO - -RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib - -CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv - -CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib - -# ALL_RISCY_DIRS = $(RISCY_DIRS) -ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS) - -# ================================================================ - REPO ?= ../.. ARCH ?= RV64ACDFIMSUxCHERI # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler -BSC_COMPILATION_FLAGS += \ - -D RV64 \ - -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ - -D SV39 \ - -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \ - -D SHIFT_BARREL \ - -D MULT_SYNTH \ - -D Near_Mem_Caches \ - -D FABRIC64 \ - -D CheriBusBytes=8 \ - -D CheriMasterIDWidth=1 \ - -D CheriTransactionIDWidth=5 \ - -D CAP128 -D BLUESIM \ - -D MEM64 \ - -D RISCV \ - -D PERFORMANCE_MONITORING - - # Default ISA test TEST ?= rv64ui-p-add -#================================================================ -# Parameter settings for MIT RISCY - -BSC_COMPILATION_FLAGS += -D BSIM \ - - -include $(REPO)/builds/Resources/Include_RISCY_Config.mk - #================================================================ # Common boilerplate rules include $(REPO)/builds/Resources/Include_Common.mk +#================================================================ +# Parameter settings for MIT RISCY + +include $(REPO)/builds/Resources/Include_RISCY_Config.mk + #================================================================ # Makefile rules for building for specific simulator: verilator diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index 1f63d32..c40c02d 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -32,6 +32,21 @@ help: .PHONY: all all: compile simulator +# ================================================================ +# Path to RISCY-OOO sources + +RISCY_HOME ?= ../../src_Core/RISCY_OOO +# RISCY_HOME ?= $(HOME)/Projects/RISCV/MIT-riscy/riscy-OOO + +RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib + +CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv + +CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib + +# ALL_RISCY_DIRS = $(RISCY_DIRS) +ALL_RISCY_DIRS +=$(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS) + # ================================================================ # Search path for bsc for .bsv files @@ -55,6 +70,22 @@ TOPMODULE ?= mkTop_HW_Side # bsc compilation flags BSC_COMPILATION_FLAGS += \ + -D BSIM \ + -D RV64 \ + -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ + -D SV39 \ + -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \ + -D SHIFT_BARREL \ + -D MULT_SYNTH \ + -D Near_Mem_Caches \ + -D FABRIC64 \ + -D CheriBusBytes=8 \ + -D CheriMasterIDWidth=1 \ + -D CheriTransactionIDWidth=5 \ + -D CAP128 -D BLUESIM \ + -D MEM64 \ + -D RISCV \ + -D PERFORMANCE_MONITORING \ -keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \ -suppress-warnings G0020 -steps-max-intervals 10000000 \ -steps-warn-interval 1000000 \