From 34e753a7369b7333141ef9647da8c1c1b38740d6 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Wed, 16 Nov 2022 07:22:13 +0000 Subject: [PATCH 01/10] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 48ca4c3..b4c948d 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 48ca4c33911a86d562804defa4dfebaf28ade54b +Subproject commit b4c948d4b4ed670128470b34e2bee184f4843ccc From 522de50334c01ea09629471a0c22e22a3169c905 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 17 Nov 2022 14:58:45 +0000 Subject: [PATCH 02/10] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index b4c948d..af67c45 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit b4c948d4b4ed670128470b34e2bee184f4843ccc +Subproject commit af67c45b763ff23ac4d484f8e8778231006b926f From 2a69ecb33ede5d1236294a53476497f8b582290a Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 17 Nov 2022 15:15:29 +0000 Subject: [PATCH 03/10] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index af67c45..4dec54b 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit af67c45b763ff23ac4d484f8e8778231006b926f +Subproject commit 4dec54bc42f1705ecd5066bc0d65cd64ab12e32e From d9e842b785ec01b117cb5b71c941b583bd094a0d Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Mon, 16 Jan 2023 17:45:07 +0000 Subject: [PATCH 04/10] Extend ID field to match current design. This is likely to be cause of lockup in hardware. --- src_SSITH_P3/xilinx_ip/component.xml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index bd8f871..e3eb438 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -1109,7 +1109,7 @@ out - 5 + 6 0 @@ -1295,7 +1295,7 @@ in - 5 + 6 0 @@ -1391,7 +1391,7 @@ out - 5 + 6 0 @@ -1648,7 +1648,7 @@ in - 5 + 6 0 @@ -1710,7 +1710,7 @@ out - 5 + 6 0 @@ -1896,7 +1896,7 @@ in - 5 + 6 0 From 6931201a1440a903be9892c52134a4e69ca74cc9 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Tue, 31 Jan 2023 21:02:17 +0000 Subject: [PATCH 05/10] Avoid wedge on repeated debug resumes (with jdw57 and aj443) ConfigReg avoids a compile error --- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 0102058..4c0950f 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -63,6 +63,7 @@ import ReservationStationAlu::*; import ReservationStationMem::*; import ReservationStationFpuMulDiv::*; import SplitLSQ::*; +import ConfigReg::*; import CHERICap::*; import CHERICC_Fat::*; import ISA_Decls_CHERI::*; @@ -199,7 +200,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); // Is set to Valid intrDebugStep on dcsr[stepbit]==1 and one instruction has been processed. // Note (step): 1st instruction is guaranteed architectural, cannot possibly be speculative. // Note (step): 1st instruction may trap; we halt pointing at the trap vector - Reg #(Maybe #(Interrupt)) rg_m_halt_req <- mkReg (tagged Invalid); + Reg #(Maybe #(Interrupt)) rg_m_halt_req <- mkConfigReg (tagged Invalid); function Action fa_step_check; action @@ -1234,7 +1235,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); `endif `ifdef INCLUDE_GDB_CONTROL - method Action debug_halt_req () if (rg_m_halt_req == tagged Invalid); + method Action debug_halt_req (); rg_m_halt_req <= tagged Valid intrDebugHalt; if (verbosity >= 1) $display ("%0d: %m.renameStage.renameStage.debug_halt_req", cur_cycle); From 0f081d9441c695baf404a73764ae94a1b8efd80c Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Thu, 9 Feb 2023 14:20:13 +0000 Subject: [PATCH 06/10] Connect ndm reset up in src_SSITH_P3 build --- src_SSITH_P3/src_BSV/P3_Core.bsv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 7f5ff60..f42ccf8 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -168,6 +168,11 @@ module mkP3_Core (P3_Core_IFC); `ifdef INCLUDE_GDB_CONTROL + (* no_implicit_conditions, fire_when_enabled *) + rule rl_forward_debug_reset (otherRst); + ndm_reset_controller.assertReset(); + endrule + // ================================================================ // Instantiate JTAG TAP controller, // connect to corew.dmi; From 50c51e93a126d355a5f2cc471e0a10f6dec6ed9c Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Thu, 9 Feb 2023 14:34:13 +0000 Subject: [PATCH 07/10] Add assertion that ndm resets don't get dropped --- src_Core/Core/CoreW.bsv | 1 + 1 file changed, 1 insertion(+) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 59eda10..ecd6880 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -147,6 +147,7 @@ module mkCoreW (CoreW_IFC #(t_n_irq)); `endif , .ifc} <- mkCoreW_reset ( rst, reset_by newRst.new_rst); + (* no_implicit_conditions, fire_when_enabled *) rule rl_forward_debug_reset (otherRst); newRst.assertReset; endrule From b0316afcb7c39a214736ca2c9f75904f58e94181 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Fri, 10 Feb 2023 17:01:32 +0000 Subject: [PATCH 08/10] Extend missed id field width --- src_SSITH_P3/xilinx_ip/component.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index e3eb438..6f961eb 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -790,7 +790,7 @@ out - 5 + 6 0 From 69b96cc68f2d35b3ffb46754fc9265809af90cb2 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Fri, 10 Feb 2023 17:09:20 +0000 Subject: [PATCH 09/10] Extend the final missed id width --- src_SSITH_P3/xilinx_ip/component.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index 6f961eb..a764e79 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -1047,7 +1047,7 @@ in - 5 + 6 0 From e981b7625fcf9d0d7b81080790abdd6a631be713 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Thu, 16 Feb 2023 16:41:00 +0000 Subject: [PATCH 10/10] Ban illegal JALR and Br encodings --- src_Core/RISCY_OOO/procs/lib/Decode.bsv | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv index b9d84df..11b2821 100644 --- a/src_Core/RISCY_OOO/procs/lib/Decode.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Decode.bsv @@ -519,6 +519,8 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); dInst.csr = tagged Invalid; dInst.execFunc = tagged Br AT; + if (funct3 != 0) illegalInst = True; + dInst.capChecks.check_enable = True; dInst.capChecks.check_low_src = Src1Addr; dInst.capChecks.check_high_src = Src1AddrPlus2; @@ -542,14 +544,18 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); opcBranch: begin dInst.iType = Br; - dInst.execFunc = tagged Br (case(funct3) - fnBEQ: Eq; - fnBNE: Neq; - fnBLT: Lt; - fnBLTU: Ltu; - fnBGE: Ge; - fnBGEU: Geu; - endcase); + ExecFunc execFunc = ?; + {illegalInst, execFunc} = case(funct3) + fnBEQ: tuple2(False, Br(Eq)); + fnBNE: tuple2(False, Br(Neq)); + fnBLT: tuple2(False, Br(Lt)); + fnBLTU: tuple2(False, Br(Ltu)); + fnBGE: tuple2(False, Br(Ge)); + fnBGEU: tuple2(False, Br(Geu)); + default: tuple2(True, Br(?)); + endcase; + dInst.execFunc = execFunc; + regs.dst = Invalid; regs.src1 = Valid(tagged Gpr rs1); regs.src2 = Valid(tagged Gpr rs2);