removed debug prints

src_Core/CPU/Core.bsv

@@ -366,6 +366,11 @@ module mkCore#(CoreId coreId)(Core);
         // whether perf data is collected
         Reg#(Bool) doStatsReg <- mkConfigReg(True);
 
+        // Hack to get set stat reg to true
+        // rule forceSetStatRegToTrue;
+        //     doStatsReg <= True;
+        // endrule
+
         // write aggressive elements + wakupe reservation stations
         function Action writeAggr(Integer wrAggrPort, PhyRIndx dst);
         action

src_Core/CPU/CsrFile.bsv

@@ -330,7 +330,8 @@ interface StatsCsr;
 endinterface
 
 module mkStatsCsr(StatsCsr);
-    Reg#(Bool) doStats <- mkConfigReg(False);
+    // Seeting CSR stat to true
+    Reg#(Bool) doStats <- mkConfigReg(True);
 
     FIFO#(Bool) writeQ <- mkFIFO1;