From aa792406292be784fbecdcc3fb77322fdc6b6119 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 23 Apr 2020 02:04:19 +0100 Subject: [PATCH] generalise genDependencies a bit with env variables (no obvious getoptsin tcl AFAIK) --- builds/Resources/genDependencies.tcl | 104 ++++++++++++++++++--------- 1 file changed, 72 insertions(+), 32 deletions(-) diff --git a/builds/Resources/genDependencies.tcl b/builds/Resources/genDependencies.tcl index d59a5d7..5095339 100755 --- a/builds/Resources/genDependencies.tcl +++ b/builds/Resources/genDependencies.tcl @@ -2,43 +2,83 @@ namespace import ::Bluetcl::* -flags set -p "../RV64ACDFIMSU_Toooba_verilator:../../libs/BlueStuff:../../libs/BlueStuff/AXI:../../libs/BlueStuff/BlueUtils:../../libs/BlueStuff/BlueBasics:../../src_Core/RISCY_OOO/procs/RV64G_OOO:../../src_Core/RISCY_OOO/procs/lib:../../src_Core/RISCY_OOO/coherence/src:../../src_Core/RISCY_OOO/fpgautils/lib:../../src_Core/RISCY_OOO/connectal/bsv:../../src_Core/RISCY_OOO/connectal/tests/spi:../../src_Core/RISCY_OOO/connectal/lib/bsv:../../src_Core/RISCY_OOO/../../src_Verifier:../../src_Core/RISCY_OOO/../../src_Verifier/BSV-RVFI-DII:../../src_Core/RISCY_OOO/../CHERI:../../src_Core/RISCY_OOO/../../libs/cheri-cap-lib:../../src_Core/CPU:../../src_Core/ISA:../../src_Core/Core:../../src_Core/PLIC:../../src_Core/Debug_Module:../../src_Core/BSV_Additional_Libs:../../src_Testbench/Top:../../src_Testbench/SoC:../../libs/TagController/TagController:../../libs/TagController/TagController/CacheCore:+" +# there does not seam to be a nice "getopt" in tcl, so for now, falling back on: +# +# - env variables: +# BSC_PATH +# BSC_DEFINES +# BSC_BUILDDIR +# BSC_TOPFILE +# OUTPUTFILE +# +# - if argv is non empty, each arg is passed individually to a flags set command +# (that is, can't pass flags that expect arguments themselves like -D XXX) +################################################################################ -flags set -D RISCV -flags set -D RV64 -flags set -D ISA_PRIV_M -flags set -D ISA_PRIV_U -flags set -D ISA_PRIV_S -flags set -D SV39 -flags set -D ISA_I -flags set -D ISA_M -flags set -D ISA_A -flags set -D ISA_F -flags set -D ISA_D -flags set -D ISA_FD_DIV -flags set -D ISA_C -flags set -D SHIFT_BARREL -flags set -D MULT_SYNTH -flags set -D Near_Mem_Caches -flags set -D FABRIC64 -flags set -D CAP128 -flags set -D MEM64 -#flags set -D RVFI_DII -#flags set -D RVFI -flags set -D BSIM -flags set -D CORE_SMALL -flags set -D NUM_CORES=1 -flags set -D CACHE_SMALL -flags set -D XILINX_FP_FMA_LATENCY=3 -flags set -D XILINX_INT_MUL_LATENCY=2 -flags set -D USE_BSV_BRAM_SYNC_FIFO +if { [info exists env(BSC_PATH)] } { + set path $env(BSC_PATH) +} else { + #set path ".:+" + set path "../../libs/BlueStuff:../../libs/BlueStuff/AXI:../../libs/BlueStuff/BlueUtils:../../libs/BlueStuff/BlueBasics:../../src_Core/RISCY_OOO/procs/RV64G_OOO:../../src_Core/RISCY_OOO/procs/lib:../../src_Core/RISCY_OOO/coherence/src:../../src_Core/RISCY_OOO/fpgautils/lib:../../src_Core/RISCY_OOO/connectal/bsv:../../src_Core/RISCY_OOO/connectal/tests/spi:../../src_Core/RISCY_OOO/connectal/lib/bsv:../../src_Core/RISCY_OOO/../../src_Verifier:../../src_Core/RISCY_OOO/../../src_Verifier/BSV-RVFI-DII:../../src_Core/RISCY_OOO/../CHERI:../../src_Core/RISCY_OOO/../../libs/cheri-cap-lib:../../src_Core/CPU:../../src_Core/ISA:../../src_Core/Core:../../src_Core/PLIC:../../src_Core/Debug_Module:../../src_Core/BSV_Additional_Libs:../../src_Testbench/Top:../../src_Testbench/SoC:../../libs/TagController/TagController:../../libs/TagController/TagController/CacheCore:+" +} -flags set -bdir build_dir +if { [info exists env(BSC_DEFINES)] } { + set defines [split $env(BSC_DEFINES)] +} else { + #set defines {} + set defines [split "RISCV RV64 ISA_PRIV_M ISA_PRIV_U ISA_PRIV_S SV39 ISA_I ISA_M ISA_A ISA_F ISA_D ISA_FD_DIV ISA_C SHIFT_BARREL MULT_SYNTH Near_Mem_Caches FABRIC64 CAP128 MEM64 BSIM CORE_SMALL NUM_CORES=1 CACHE_SMALL XILINX_FP_FMA_LATENCY=3 XILINX_INT_MUL_LATENCY=2 USE_BSV_BRAM_SYNC_FIFO"] +} -set topfile [lindex $argv 0] +if { [info exists env(BSC_BUILDDIR)] } { + set builddir $env(BSC_BUILDDIR) +} else { + set builddir "build" +} +if { [info exists env(BSC_TOPFILE)] } { + set topfile $env(BSC_TOPFILE) +} else { + set topfile "Top.bsv" +} + +if { [info exists env(OUTPUTFILE)] } { + set outputfile $env(OUTPUTFILE) +} else { + set outputfile ".depends.mk" +} + +# debug prints +#puts "path: $path" +#puts "defines: $defines" +#puts "builddir: $builddir" +#puts "topfile: $topfile" +#puts "outputfile: $outputfile" +#puts "argv: $argv" + +# setting compiler flags +################################################################################ + +flags set -p $path +flags set -bdir $builddir +flags set -verilog +foreach i $defines { + flags set -D $i +} +if { $argc > 0 } { foreach i $argv { flags set $i } } + +# output of "depend make" seams to be of the form +# { {tgtA {depA0 depA1 ...}} +# {tgtB {depB0 depB1 ...}} +# ... +# } +# reformating it for make +################################################################################ + +set fd [open $outputfile w] foreach i [depend make $topfile] { set tgt [lindex $i 0] set deps [join [lindex $i 1]] - puts [append tgt ": " $deps] + puts $fd [append tgt ": " $deps] } +close $fd +puts "generated make dependency rules for \"$topfile\" in: $outputfile"