From fe95337a979db4813ad90c92055c9b8c61eaabd8 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Mon, 20 Mar 2023 11:41:03 +0000 Subject: [PATCH 1/2] Add STRIDE_ADAPTIVE to makefile --- builds/Resources/Include_RISCY_Config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk index 5d64b76..e60ebd8 100644 --- a/builds/Resources/Include_RISCY_Config.mk +++ b/builds/Resources/Include_RISCY_Config.mk @@ -77,7 +77,7 @@ endif ifeq (,$(filter $(DATA_PREFETCHER_LOCATION),NONE L1 L1LL LL)) $(error unsupported DATA_PREFETCHER_LOCATION) endif -ifeq (,$(filter $(DATA_PREFETCHER_TYPE),MARKOV BLOCK STRIDE)) +ifeq (,$(filter $(DATA_PREFETCHER_TYPE),MARKOV BLOCK STRIDE STRIDE_ADAPTIVE)) $(error unsupported DATA_PREFETCHER_TYPE) endif From 1123f43423a8fabe1179afe996dbedf67385be87 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Mon, 20 Mar 2023 13:04:21 +0000 Subject: [PATCH 2/2] Config for L1D Markov-2-Bigtable --- builds/Resources/Include_RISCY_Config.mk | 2 +- src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk index e60ebd8..0d31f47 100644 --- a/builds/Resources/Include_RISCY_Config.mk +++ b/builds/Resources/Include_RISCY_Config.mk @@ -48,7 +48,7 @@ RENAME_DEBUG ?= false INSTR_PREFETCHER_LOCATION ?= NONE INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW DATA_PREFETCHER_LOCATION ?= L1 -DATA_PREFETCHER_TYPE ?= STRIDE_ADAPTIVE +DATA_PREFETCHER_TYPE ?= MARKOV # clk frequency depends on core size ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM)) diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index 6d5c091..feb495f 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -435,9 +435,9 @@ module mkTargetTableBRAM(TargetTableBRAM#(narrowTableSize, wideTableSize)) provi ( NumAlias#(narrowTableIdxBits, TLog#(narrowTableSize)), NumAlias#(wideTableIdxBits, TLog#(wideTableSize)), - NumAlias#(narrowTableTagBits, TSub#(32, narrowTableIdxBits)), - NumAlias#(wideTableTagBits, TSub#(32, wideTableIdxBits)), - NumAlias#(narrowDistanceBits, 10), + NumAlias#(narrowTableTagBits, TSub#(24, narrowTableIdxBits)), + NumAlias#(wideTableTagBits, TSub#(24, wideTableIdxBits)), + NumAlias#(narrowDistanceBits, 16), NumAlias#(narrowMaxDistanceAbs, TExp#(TSub#(narrowDistanceBits, 1))), Alias#(narrowTargetEntryT, NarrowTargetEntry#(narrowTableTagBits, narrowDistanceBits)), Alias#(wideTargetEntryT, WideTargetEntry#(wideTableTagBits)), @@ -456,7 +456,7 @@ module mkTargetTableBRAM(TargetTableBRAM#(narrowTableSize, wideTableSize)) provi if (abs(distance) < fromInteger(valueOf(narrowMaxDistanceAbs))) begin //Store in narrow table narrowTargetEntryT entry; - entry.tag = prevAddrHash[31:valueOf(narrowTableIdxBits)]; + entry.tag = prevAddrHash[23:valueOf(narrowTableIdxBits)]; entry.distance = truncate(distance); Bit#(narrowTableIdxBits) idx = truncate(prevAddrHash); narrowTable.wrReq(idx, tagged Valid entry); @@ -464,7 +464,7 @@ module mkTargetTableBRAM(TargetTableBRAM#(narrowTableSize, wideTableSize)) provi else begin //Store in wide table wideTargetEntryT entry; - entry.tag = prevAddrHash[31:valueOf(wideTableIdxBits)]; + entry.tag = prevAddrHash[23:valueOf(wideTableIdxBits)]; entry.target = currAddr; Bit#(wideTableIdxBits) idx = truncate(prevAddrHash); wideTable.wrReq(idx, tagged Valid entry); @@ -488,7 +488,7 @@ module mkTargetTableBRAM(TargetTableBRAM#(narrowTableSize, wideTableSize)) provi Bit#(narrowTableIdxBits) narrowIdx = truncate(addr); Bit#(wideTableIdxBits) wideIdx = truncate(addr); if (narrowTable.rdResp matches tagged Valid .entry - &&& entry.tag == addr[31:valueOf(narrowTableIdxBits)]) begin + &&& entry.tag == addr[23:valueOf(narrowTableIdxBits)]) begin if (clearEntry) begin narrowTable.wrReq(narrowIdx, Invalid); end @@ -496,7 +496,7 @@ module mkTargetTableBRAM(TargetTableBRAM#(narrowTableSize, wideTableSize)) provi return Valid(addr + signExtend(pack(entry.distance))); end else if (wideTable.rdResp matches tagged Valid .entry - &&& entry.tag == addr[31:valueOf(wideTableIdxBits)]) begin + &&& entry.tag == addr[23:valueOf(wideTableIdxBits)]) begin if (clearEntry) begin wideTable.wrReq(wideIdx, Invalid); end @@ -715,7 +715,7 @@ module mkBRAMMarkovPrefetcher(Prefetcher) provisos ); Reg#(LineAddr) lastLastChildRequest <- mkReg(0); Reg#(LineAddr) lastChildRequest <- mkReg(0); - TargetTableBRAM#(1024, 64) targetTable <- mkTargetTableBRAM; + TargetTableBRAM#(65536, 4096) targetTable <- mkTargetTableBRAM; FIFOF#(LineAddr) targetTableReadResp <- mkBypassFIFOF; // Stores how many prefetches we can still do in the current chain