Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization
(1) riscy-ooo was mapping all unimplemented CSRs to a benign, user-privilege read-write CSR
Instead, we now catch this RenameStage and steer it to a trap.
(2) MSTATUS.FS was initialized to 2'b00 (absent/off); should be 2'b01 (present and initial)
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@@ -310,7 +310,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
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// Machine level CSRs
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// mstatus
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Reg#(Bit#(2)) xs_reg <- mkReadOnlyReg(0); // XXX no extension
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Reg#(Bit#(2)) fs_reg <- (isa.f || isa.d) ? mkCsrReg(0) : mkReadOnlyReg(0);
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Reg#(Bit#(2)) fs_reg <- (isa.f || isa.d) ? mkCsrReg(2'b01) : mkReadOnlyReg(0);
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Reg#(Bit#(1)) sd_reg = readOnlyReg(
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((xs_reg == 2'b11) || (fs_reg == 2'b11)) ? 1 : 0
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);
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@@ -64,7 +64,7 @@ typedef struct {
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Bool stbEmpty;
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Bool stqEmpty;
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Bool tlbNoPendingReq;
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// CSR info: previlige mode
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// CSR info: privilege mode
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Bit#(2) prv;
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// inst count
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Data instCount;
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@@ -254,7 +254,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
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Bool read_only = (csr_addr [11:10] == 2'b11);
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Bool write_deny = (writes_csr && read_only);
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Bool priv_deny = (csrf.decodeInfo.prv < csr_addr [9:8]);
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csr_access_trap = (write_deny || priv_deny);
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Bool unimplemented = (csr_addr == 12'h8ff); // Added by Bluespec
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csr_access_trap = (write_deny || priv_deny || unimplemented);
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end
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// Check WFI trap (using a time-out of 0)
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@@ -1,5 +1,6 @@
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// Copyright (c) 2017 Massachusetts Institute of Technology
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// Portions (c) 2020 Bluespec, Inc.
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//
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// Permission is hereby granted, free of charge, to any person
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// obtaining a copy of this software and associated documentation
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@@ -284,6 +285,7 @@ typedef enum {
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// CSR that catches all the unimplemented CSRs. To avoid exception on this,
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// make it a user non-standard read/write CSR.
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// Bluespec: in RenameStage.getTrap(), we force this to be a csr_access_trap
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CSRnone = 12'h8ff
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} CSR deriving(Bits, Eq, FShow);
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