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Merge pull request #46 from CTSRD-CHERI/CHERI-benchmarks

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Cheri benchmarks
This commit is contained in:
Jonathan Woodruff
2025-06-12 10:15:45 +01:00
committed by GitHub
parent 8af3b2e85a 16de32f2d4
commit acbf07ddf0
11 changed files with 475 additions and 72 deletions
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5
src_Core/CPU/Core.bsv
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@@ -337,6 +337,8 @@ module mkCore#(CoreId coreId)(Core);
endinterface);
MMIOCore mmio <- mkMMIOCore(mmioInIfc);
PulseWire commitRedirect <- mkPulseWire;
// fix point module to instantiate other function units
module mkCoreFixPoint#(CoreFixPoint fix)(CoreFixPoint);
// spec update
@@ -420,7 +422,7 @@ module mkCore#(CoreId coreId)(Core);
method setRegReadyAggr = writeAggr(aluWrAggrPort(i));
interface sendBypass = sendBypassIfc;
method writeRegFile = writeCons(aluWrConsPort(i));
method Action redirect(CapMem new_pc, SpecTag spec_tag, InstTag inst_tag, SpecBits spec_bits);
method Action redirect(CapMem new_pc, SpecTag spec_tag, InstTag inst_tag, SpecBits spec_bits) if (!commitRedirect);
if (verbose) begin
$display("[ALU redirect - %d] ", i, fshow(new_pc),
"; ", fshow(spec_tag), "; ", fshow(inst_tag));
@@ -526,6 +528,7 @@ module mkCore#(CoreId coreId)(Core);
interface memExeIfc = memExe;
method Action killAll;
globalSpecUpdate.incorrectSpec(True, ?, ?, 0);
commitRedirect.send();
endmethod
interface doStatsIfc = doStatsReg;
method pendingIncorrectSpec = globalSpecUpdate.pendingIncorrectSpec;

38
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
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@@ -36,6 +36,8 @@ import Vector::*;
import BuildVector::*;
import ProcTypes::*;
Bool verbose = False;
typedef enum {
HIT = 1'b0, MISS = 1'b1
} HitOrMiss deriving (Bits, Eq, FShow);
@@ -193,7 +195,7 @@ module mkSingleWindowL1LLPrefetcher(Prefetcher);
method ActionValue#(Addr) getNextPrefetchAddr if (nextToAsk != rangeEnd);
nextToAsk <= nextToAsk + 1;
let retAddr = Addr'{nextToAsk, '0}; //extend cache line address to regular address
if(verbose) $display("%t Prefetcher getNextPrefetchAddr requesting %h", $time, retAddr);
if (verbose) $display("%t Prefetcher getNextPrefetchAddr requesting %h", $time, retAddr);
return retAddr;
endmethod
endmodule
@@ -446,13 +448,13 @@ module mkTargetTable(TargetTable#(narrowTableSize, wideTableSize)) provisos
if (narrowTable[narrowIdx][0] matches tagged Valid .entry
&&& entry.tag == addr[31:valueOf(narrowTableIdxBits)]) begin
narrowTable[narrowIdx][0] <= Invalid;
//$display("%t found narrow table entry %h", $time, addr + signExtend(pack(entry.distance)));
//if (verbose) $display("%t found narrow table entry %h", $time, addr + signExtend(pack(entry.distance)));
return Valid(addr + signExtend(pack(entry.distance)));
end
else if (wideTable[wideIdx][0] matches tagged Valid .entry
&&& entry.tag == addr[31:valueOf(wideTableIdxBits)]) begin
wideTable[wideIdx][0] <= Invalid;
//$display("%t found wide table entry %h", $time, entry.target);
//if (verbose) $display("%t found wide table entry %h", $time, entry.target);
return Valid(entry.target);
end
else
@@ -620,12 +622,12 @@ module mkTargetTableDouble(TargetTableDouble#(narrowTableSize, wideTableSize)) p
actionvalue
if (narrowWrapped matches tagged Valid .narrow
&&& narrowTagMatch(addrHash, narrow)) begin
//$display("%t found narrow table entry %h", $time, addr + signExtend(pack(narrow.distance)));
//if (verbose) $display("%t found narrow table entry %h", $time, addr + signExtend(pack(narrow.distance)));
return Valid(addr + signExtend(pack(narrow.distance)));
end
else if (wideWrapped matches tagged Valid .wide
&&& wideTagMatch(addrHash, wide)) begin
//$display("%t found wide table entry %h", $time, wide.target);
//if (verbose) $display("%t found wide table entry %h", $time, wide.target);
return Valid(wide.target);
end
else
@@ -690,7 +692,7 @@ module mkTargetTableDouble(TargetTableDouble#(narrowTableSize, wideTableSize)) p
entry.distance = truncate(distance);
if (Valid(entry) != lastMissNarrowMRUEntry) begin
//$display("%t Recording miss -- modifying narrow table", $time);
//if (verbose) $display("%t Recording miss -- modifying narrow table", $time);
//Maintain the property that one address can only have
// at most 2 of 4 table entries for it.
//Shift narrow table entries down, storing in MRU.
@@ -710,7 +712,7 @@ module mkTargetTableDouble(TargetTableDouble#(narrowTableSize, wideTableSize)) p
entry.target = currAddr;
if (Valid(entry) != lastMissWideMRUEntry) begin
//$display("%t Recording miss -- modifying wide table", $time);
//if (verbose) $display("%t Recording miss -- modifying wide table", $time);
wideTableMRU.wrReq(idx, Valid(entry));
wideTableLRU.wrReq(idx, lastMissWideMRUEntry);
Bit#(narrowTableIdxBits) narrowIdx = truncate(lastMissAddrHash);
@@ -748,9 +750,9 @@ module mkTargetTableDouble(TargetTableDouble#(narrowTableSize, wideTableSize)) p
//Update the entries for the last miss to point to this one
writeMissEntry(addr);
//Save the raw table entries
//$display("idx: %x", addrHash);
//$display("%t Read resp: nMRU: ", fshow(narrowTableMRU.rdResp), "wMRU: ", fshow(wideTableMRU.rdResp));
//$display("%t Read resp: nLRU: ", fshow(narrowTableLRU.rdResp), "wLRU: ", fshow(wideTableLRU.rdResp));
//if (verbose) $display("idx: %x", addrHash);
//if (verbose) $display("%t Read resp: nMRU: ", fshow(narrowTableMRU.rdResp), "wMRU: ", fshow(wideTableMRU.rdResp));
//if (verbose) $display("%t Read resp: nLRU: ", fshow(narrowTableLRU.rdResp), "wLRU: ", fshow(wideTableLRU.rdResp));
lastMissWideMRUEntry <= wideTableMRU.rdResp;
lastMissNarrowMRUEntry <= narrowTableMRU.rdResp;
lastMissWideLRUEntry <= wideTableLRU.rdResp;
@@ -1036,7 +1038,7 @@ module mkBRAMMarkovPrefetcher(Prefetcher) provisos
if (hitMiss == MISS) begin
//Don't start markov chain if its very recent
//$display("%t Prefetcher start new chain with %h", $time, addr);
//if (verbose) $display("%t Prefetcher start new chain with %h", $time, addr);
chainNextToLookup <= cl;
chainNumberToPrefetch <= fromInteger(valueOf(maxChainLength));
end
@@ -1291,7 +1293,7 @@ provisos(
strideTable.deqRdResp;
StrideEntry seNext = se;
Bit#(13) observedStride = {1'b0, addr[11:0]} - {1'b0, se.lastAddr};
if (verbose) $writeh("%t Stride Prefetcher updateStrideEntry ", $time,
if (verbose) $display("%t Stride Prefetcher updateStrideEntry ", $time,
fshow(hitMiss), " ", addr,
". Entry ", index, " state is ", fshow(se.state));
if (se.state == EMPTY) begin
@@ -1415,7 +1417,7 @@ provisos(
);
Bool verbose = False;
RWBramCore#(strideTableIndexT, StrideEntry2) strideTable <- mkRWBramCoreForwarded;
FIFOF#(Tuple3#(Addr, Bit#(16), HitOrMiss)) memAccesses <- mkSizedBypassFIFOF(8);
FIFOF#(Tuple3#(Addr, Bit#(16), HitOrMiss)) memAccesses <- mkUGSizedFIFOF(8);
Reg#(Tuple3#(Addr, Bit#(16), HitOrMiss)) rdRespEntry <- mkReg(?);
Fifo#(8, Addr) addrToPrefetch <- mkOverflowPipelineFifo;
@@ -1423,7 +1425,7 @@ provisos(
Reg#(Maybe#(Bit#(2))) cLinesPrefetchedLatest <- mkReg(?);
PulseWire holdReadReq <- mkPulseWire;
rule sendReadReq if (!holdReadReq);
rule sendReadReq if (!holdReadReq && memAccesses.notEmpty);
match {.addr, .pcHash, .hitMiss} = memAccesses.first;
if (verbose) $display("%t Sending read req for %h!", $time, pcHash);
strideTable.rdReq(truncate(pcHash));
@@ -1445,7 +1447,7 @@ provisos(
strideTable.deqRdResp;
StrideEntry2 seNext = se;
Int#(12) observedStride = unpack(addr[11:0] - se.lastAddr);
if (verbose) $writeh("%t Stride Prefetcher updateStrideEntry ", $time,
if (verbose) $display("%t Stride Prefetcher updateStrideEntry ", $time,
fshow(hitMiss), " ", addr,
". Entry ", index, " state is ", fshow(se.state));
if (se.state == INIT && observedStride != 0) begin
@@ -1548,7 +1550,7 @@ provisos(
endrule
method Action reportAccess(Addr addr, Bit#(16) pcHash, HitOrMiss hitMiss);
memAccesses.enq(tuple3 (addr, pcHash, hitMiss));
if (memAccesses.notFull) memAccesses.enq(tuple3 (addr, pcHash, hitMiss));
endmethod
method ActionValue#(Addr) getNextPrefetchAddr;
@@ -1726,7 +1728,7 @@ provisos(
strideTable.deqRdResp;
StrideEntryAdaptive seNext = se;
Bit#(13) observedStride = {1'b0, addr[11:0]} - {1'b0, se.lastAddr};
if (verbose) $writeh("%t Stride Prefetcher updateStrideEntry ", $time,
if (verbose) $display("%t Stride Prefetcher updateStrideEntry ", $time,
fshow(hitMiss), " ", addr,
". Entry ", index, " state is ", fshow(se.state));
if (se.state == EMPTY) begin
@@ -1946,7 +1948,7 @@ module mkLLIPrefetcher(Prefetcher);
`endif
return m;
endmodule
(* synthesize *)
module mkL1DPrefetcher(PCPrefetcher);
`ifdef DATA_PREFETCHER_IN_L1
`ifdef DATA_PREFETCHER_BLOCK

2
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -297,7 +297,7 @@ deriving (Eq, FShow, Bits);
`endif
module mkCommitStage#(CommitInput inIfc)(CommitStage);
Bool verbose = False;
Bool verbose = True;
Integer verbosity = 1; // Bluespec: for lightweight verbosity trace

1
src_Core/RISCY_OOO/procs/lib/DirPredictor.bsv
View File

@@ -45,7 +45,6 @@ import Bht::*;
import GSelectPred::*;
import GSharePred::*;
import TourPred::*;
import TourPredSecure::*;
import Ras::*;
export DirPredTrainInfo(..);

40
src_Core/RISCY_OOO/procs/lib/EpochManager.bsv
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@@ -26,6 +26,7 @@ import Vector::*;
import Ehr::*;
import Types::*;
import ProcTypes::*;
import ConfigReg::*;
typedef struct {
Epoch curEp;
@@ -53,47 +54,44 @@ endinterface
(* synthesize *)
module mkEpochManager(EpochManager);
Reg#(Epoch) curr_epoch <- mkReg(0);
Reg#(Epoch) prev_checked_epoch <- mkReg(0);
Reg#(Epoch) curr_epoch <- mkConfigReg(0);
Reg#(Epoch) prev_checked_epoch <- mkConfigReg(0);
Epoch next_epoch = (curr_epoch== fromInteger(valueOf(NumEpochs)-1)) ? 0 : (curr_epoch+1);
// epochs in the core are within range [prev_checked_epoch, curr_epoch]
// prev_checked_epoch can be updated in a lazy way
Vector#(SupSize, Ehr#(2, Maybe#(Epoch))) updatePrevEn <- replicateM(mkEhr(Invalid));
Vector#(SupSize, RWire#(Epoch)) updatePrevEn <- replicateM(mkRWire);
(* fire_when_enabled, no_implicit_conditions *)
rule canon_prev_checked_epoch;
Vector#(SupSize, Maybe#(Epoch)) updates = readVEhr(1, updatePrevEn);
Vector#(SupSize, Maybe#(Epoch)) updates = ?;
for (Integer i = 0; i < valueof(SupSize); i = i + 1) updates[i] = updatePrevEn[i].wget();
// find the last update
if(find(isValid, reverse(updates)) matches tagged Valid .upd) begin
doAssert(isValid(upd), "must be valid");
prev_checked_epoch <= validValue(upd);
end
// reset EHR
for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
updatePrevEn[i][1] <= Invalid;
end
endrule
Vector#(SupSize, EM_updatePrevEpoch) updateIfc;
for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
updateIfc[i] = (interface EM_updatePrevEpoch;
method Action update(Epoch e);
updatePrevEn[i][0] <= Valid (e); // record update action
updatePrevEn[i].wset(e); // record update action
`ifdef BSIM
// sanity check
Epoch checkedEpoch = prev_checked_epoch;
for(Integer j = 0; j < i; j = j+1) begin
if(updatePrevEn[j][1] matches tagged Valid .ep) begin
checkedEpoch = ep;
end
end
if(checkedEpoch <= curr_epoch) begin
doAssert(checkedEpoch <= e && e <= curr_epoch, "e in [checkedEpoch, curr_epoch]");
end
else begin
doAssert(checkedEpoch <= e || e <= curr_epoch, "e in [checkedEpoch, max] + [0, curr_epoch]");
end
//Epoch checkedEpoch = prev_checked_epoch;
//for(Integer j = 0; j < i; j = j+1) begin
// if(updatePrevEn[j][1] matches tagged Valid .ep) begin
// checkedEpoch = ep;
// end
//end
//if(checkedEpoch <= curr_epoch) begin
// doAssert(checkedEpoch <= e && e <= curr_epoch, "e in [checkedEpoch, curr_epoch]");
//end
//else begin
// doAssert(checkedEpoch <= e || e <= curr_epoch, "e in [checkedEpoch, max] + [0, curr_epoch]");
//end
`endif
endmethod
endinterface);

48
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -48,6 +48,8 @@ import HasSpecBits::*;
import Vector::*;
import Assert::*;
import Ehr::*;
import ConfigReg::*;
import SpecialRegs::*;
import RevertingVirtualReg::*;
`ifdef RVFI_DII
import RVFI_DII_Types::*;
@@ -260,29 +262,29 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
Integer traceBundle_deqLSQ_port = valueof(fpuMulDivExeNum) + valueof(aluExeNum);
Integer traceBundle_enq_port = 1 + traceBundle_deqLSQ_port;
Reg#(CapMem) pc <- mkRegU;
Reg #(Bit #(32)) orig_inst <- mkRegU;
Reg#(IType) iType <- mkRegU;
Reg #(Maybe #(ArchRIndx)) rg_dst_reg <- mkRegU;
Reg#(CapMem) pc <- mkConfigRegU;
Reg #(Bit #(32)) orig_inst <- mkConfigRegU;
Reg#(IType) iType <- mkConfigRegU;
Reg #(Maybe #(ArchRIndx)) rg_dst_reg <- mkConfigRegU;
`ifdef INCLUDE_TANDEM_VERIF
Reg #(Data) rg_dst_data <- mkRegU;
Reg #(Data) rg_store_data <- mkRegU;
Reg #(ByteEn) rg_store_data_BE <- mkRegU;
Reg #(Data) rg_dst_data <- mkConfigRegU;
Reg #(Data) rg_store_data <- mkConfigRegU;
Reg #(ByteEn) rg_store_data_BE <- mkConfigRegU;
`endif
Reg#(Maybe#(CSR)) csr <- mkRegU;
Reg#(Maybe#(SCR)) scr <- mkRegU;
Reg#(Bool) claimed_phy_reg <- mkRegU;
Ehr#(TAdd#(2, aluExeNum), Maybe#(Trap)) trap <- mkEhr(?);
Ehr#(TAdd#(2, aluExeNum), PPCVAddrCSRData) ppc_vaddr_csrData <- mkEhr(?);
Ehr#(TAdd#(1, fpuMulDivExeNum), Bit#(5)) fflags <- mkEhr(?);
Reg#(Bool) will_dirty_fpu_state <- mkRegU;
Ehr#(TAdd#(3, TAdd#(fpuMulDivExeNum, aluExeNum)), RobInstState) rob_inst_state <- mkEhr(?);
Reg#(LdStQTag) lsqTag <- mkRegU;
Ehr#(2, Maybe#(LdKilledBy)) ldKilled <- mkEhr(?);
Ehr#(3, Bool) memAccessAtCommit <- mkEhr(?);
Ehr#(2, Bool) lsqAtCommitNotified <- mkEhr(?);
Ehr#(2, Bool) nonMMIOStDone <- mkEhr(?);
Reg#(Bool) epochIncremented <- mkRegU;
Reg#(Maybe#(CSR)) csr <- mkConfigRegU;
Reg#(Maybe#(SCR)) scr <- mkConfigRegU;
Reg#(Bool) claimed_phy_reg <- mkConfigRegU;
Ehr#(TAdd#(2, aluExeNum), Maybe#(Trap)) trap <- mkRegOR(?);
Ehr#(TAdd#(2, aluExeNum), PPCVAddrCSRData) ppc_vaddr_csrData <- mkRegOR(?);
Ehr#(TAdd#(1, fpuMulDivExeNum), Bit#(5)) fflags <- mkRegOR(?);
Reg#(Bool) will_dirty_fpu_state <- mkConfigRegU;
Ehr#(TAdd#(3, TAdd#(fpuMulDivExeNum, aluExeNum)), RobInstState) rob_inst_state <- mkRegOR(?);
Reg#(LdStQTag) lsqTag <- mkConfigRegU;
Ehr#(2, Maybe#(LdKilledBy)) ldKilled <- mkRegOR(?);
Ehr#(3, Bool) memAccessAtCommit <- mkRegOR(?);
Ehr#(2, Bool) lsqAtCommitNotified <- mkRegOR(?);
Ehr#(2, Bool) nonMMIOStDone <- mkRegOR(?);
Reg#(Bool) epochIncremented <- mkConfigRegU;
Ehr#(3, SpecBits) spec_bits <- mkEhr(?);
`ifdef RVFI_DII
Reg#(Dii_Parcel_Id) dii_pid <- mkRegU;
@@ -1131,8 +1133,8 @@ module mkSupReorderBuffer#(
for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
SupWaySel way = getDeqFifoWay(fromInteger(i)); // FIFO[way] is used by deq port i
Bool can_deq = can_deq_fifo[way] &&
deq_SB_wrongSpec && // ordering: < wrongSpec
all(id, readVReg(deq_SB_enq)); // ordering: < enq
deq_SB_wrongSpec /*&& // ordering: < wrongSpec
all(id, readVReg(deq_SB_enq))*/; // ordering: < enq
deqIfc[i] = (interface ROB_DeqPort;
method Bool canDeq = can_deq;
method Action deq if(can_deq);