From ada7d133e4c233e9613157b2b9df3001675d45ce Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Mon, 13 Mar 2023 14:51:59 +0000 Subject: [PATCH] Config for L1D Stride-4 prefetcher --- builds/Resources/Include_RISCY_Config.mk | 2 +- src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk index 009d5ee..bc9e745 100644 --- a/builds/Resources/Include_RISCY_Config.mk +++ b/builds/Resources/Include_RISCY_Config.mk @@ -47,7 +47,7 @@ CHECK_DEADLOCK ?= true RENAME_DEBUG ?= false INSTR_PREFETCHER_LOCATION ?= NONE INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW -DATA_PREFETCHER_LOCATION ?= L1LL +DATA_PREFETCHER_LOCATION ?= L1 DATA_PREFETCHER_TYPE ?= STRIDE # clk frequency depends on core size diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index ac85375..6c599f5 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -1186,7 +1186,7 @@ endmodule module mkBRAMStridePCPrefetcher(PCPrefetcher) provisos( NumAlias#(strideTableSize, 64), - NumAlias#(cLinesAheadToPrefetch, 3), // TODO fetch more if have repeatedly hit an entry, and if stride big + NumAlias#(cLinesAheadToPrefetch, 4), // TODO fetch more if have repeatedly hit an entry, and if stride big Alias#(strideTableIndexT, Bit#(TLog#(strideTableSize))) ); //Vector#(strideTableSize, Reg#(StrideEntry)) strideTable <- replicateM(mkReg(unpack(0)));