From aeae9b1f63b7ee325739817101d744a87b32e165 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Mon, 16 Sep 2024 16:00:11 +0100 Subject: [PATCH] Busy the system bus when performing writes This was probably removed for performance, but now that we have a faster workaround for loading kernels on the DE10, we should probably prioritise accurate error information instead. --- src_Core/Debug_Module/DM_System_Bus.bsv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index b04d252..e369cf8 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -342,6 +342,8 @@ module mkDM_System_Bus (DM_System_Bus_IFC); wuser: fabric_default_wuser_periph}; axiShim.slave.w.put(wrd); + rg_sb_state <= SB_WRITE_FINISH; + if (verbosity != 0) begin $display (" DM_System_Bus.fa_fabric_send_write_req:"); $display (" ", fshow (wra)); @@ -590,6 +592,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); let wrr <- get(axiShim.slave.b); if (wrr.bresp != OKAY) rg_sbcs_sberror <= DM_SBERROR_OTHER; + rg_sb_state <= SB_NOTBUSY; endrule // ================================================================