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enabled performance counters

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This commit is contained in:
Akilan Selvacoumar
2026-04-09 01:13:56 +01:00
parent ab1e2385f9
commit af459956b7
23 changed files with 605 additions and 605 deletions
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48
src_Core/RISCY_OOO/coherence/src/IBank.bsv
View File

@@ -60,11 +60,11 @@ import Performance::*;
import LatencyTimer::*;
import RandomReplace::*;
import Prefetcher::*;
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import BlueUtils::*;
import StatCounters::*;
`endif
// `endif
export ICRqStuck(..);
export IPRqStuck(..);
@@ -105,9 +105,9 @@ interface IBank#(
// performance
method Action setPerfStatus(Bool stats);
method Data getPerfData(L1IPerfType t);
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
method EventsL1I events;
`endif
// `endif
endinterface
module mkIBank#(
@@ -199,27 +199,27 @@ module mkIBank#(
LatencyTimer#(cRqNum, 10) latTimer <- mkLatencyTimer;
Count#(Bit#(32)) addedCRqs <- mkCount(0);
Count#(Bit#(32)) removedCRqs <- mkCount(0);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
Reg#(Bool) doStats <- mkConfigReg(True);
Count#(Data) ldCnt <- mkCount(0);
Count#(Data) ldMissCnt <- mkCount(0);
Count#(Data) ldMissLat <- mkCount(0);
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
Array #(Reg #(EventsL1I)) perf_events <- mkDRegOR (2, unpack (0));
`endif
// `endif
function Action incrReqCnt;
action
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
ldCnt.incr(1);
end
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
EventsL1I events = unpack (0);
events.evt_LD = 1;
perf_events[0] <= events;
`endif
// `endif
noAction;
endaction
endfunction
@@ -227,18 +227,18 @@ module mkIBank#(
function Action incrMissCnt(cRqIdxT idx);
action
let lat <- latTimer.done(idx);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
ldMissLat.incr(zeroExtend(lat));
ldMissCnt.incr(1);
end
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
EventsL1I events = unpack (0);
events.evt_LD_MISS_LAT = saturating_truncate(lat);
events.evt_LD_MISS = 1;
perf_events[1] <= events;
`endif
// `endif
noAction;
endaction
endfunction
@@ -906,26 +906,26 @@ module mkIBank#(
`endif
method Action setPerfStatus(Bool stats);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
doStats <= stats;
`else
noAction;
`endif
// `else
// noAction;
// `endif
endmethod
method Data getPerfData(L1IPerfType t);
return (case(t)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
L1ILdCnt: ldCnt;
L1ILdMissCnt: ldMissCnt;
L1ILdMissLat: ldMissLat;
`endif
// `endif
default: 0;
endcase);
endmethod
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
method EventsL1I events = perf_events[0];
`endif
// `endif
endmodule

52
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
View File

@@ -63,11 +63,11 @@ import Performance::*;
import LatencyTimer::*;
import RandomReplace::*;
import Prefetcher::*;
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import StatCounters::*;
import BlueUtils::*;
`endif
// `endif
export L1CRqStuck(..);
export L1PRqStuck(..);
@@ -111,9 +111,9 @@ interface L1Bank#(
// performance
method Action setPerfStatus(Bool stats);
method Data getPerfData(L1DPerfType t);
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
method EventsL1D events;
`endif
// `endif
endinterface
typedef struct {
@@ -207,7 +207,7 @@ module mkL1Bank#(
// performance
LatencyTimer#(cRqNum, 10) latTimer <- mkLatencyTimer; // max 1K cycle latency
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
Reg#(Bool) doStats <- mkConfigReg(False);
Count#(Data) ldCnt <- mkCount(0);
Count#(Data) stCnt <- mkCount(0);
@@ -218,13 +218,13 @@ module mkL1Bank#(
Count#(Data) ldMissLat <- mkCount(0);
Count#(Data) stMissLat <- mkCount(0);
Count#(Data) amoMissLat <- mkCount(0);
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
Array #(Reg #(EventsL1D)) perf_events <- mkDRegOR (2, unpack (0));
`endif
// `endif
function Action incrReqCnt(MemOp op);
action
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
case(op)
Ld: ldCnt.incr(1);
@@ -232,8 +232,8 @@ action
Lr, Sc, Amo: amoCnt.incr(1);
endcase
end
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
EventsL1D events = unpack (0);
case(op)
Ld: events.evt_LD = 1;
@@ -241,7 +241,7 @@ action
Lr, Sc, Amo: events.evt_AMO = 1;
endcase
perf_events[0] <= events;
`endif
// `endif
noAction;
endaction
endfunction
@@ -249,7 +249,7 @@ endfunction
function Action incrMissCnt(MemOp op, cRqIdxT idx);
action
let lat <- latTimer.done(idx);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
case(op)
Ld: begin
@@ -266,8 +266,8 @@ action
end
endcase
end
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
EventsL1D events = unpack (0);
case(op)
Ld: begin
@@ -284,7 +284,7 @@ action
end
endcase
perf_events[1] <= events;
`endif
// `endif
noAction;
endaction
endfunction
@@ -1233,16 +1233,16 @@ endfunction
`endif
method Action setPerfStatus(Bool stats);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
doStats <= stats;
`else
noAction;
`endif
// `else
// noAction;
// `endif
endmethod
method Data getPerfData(L1DPerfType t);
return (case(t)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
L1DLdCnt: ldCnt;
L1DStCnt: stCnt;
L1DAmoCnt: amoCnt;
@@ -1252,13 +1252,13 @@ endfunction
L1DLdMissLat: ldMissLat;
L1DStMissLat: stMissLat;
L1DAmoMissLat: amoMissLat;
`endif
// `endif
default: 0;
endcase);
endmethod
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
method EventsL1D events = perf_events[0];
`endif
// `endif
endmodule
@@ -1495,7 +1495,7 @@ module mkL1Cache#(
end
return fold(\+ , d);
endmethod
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
method EventsL1D events;
EventsL1D ret = unpack(0);
for(Integer i = 0; i < valueof(bankNum); i = i+1) begin
@@ -1503,5 +1503,5 @@ module mkL1Cache#(
end
return ret;
endmethod
`endif
// `endif
endmodule

72
src_Core/RISCY_OOO/coherence/src/LLBank.bsv
View File

@@ -55,11 +55,11 @@ import ConfigReg::*;
import RandomReplace::*;
import Prefetcher::*;
import ProcTypes::*;
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import StatCounters::*;
import BlueUtils::*;
`endif
// `endif
export LLCRqStuck(..);
export LLBank(..);
@@ -111,9 +111,9 @@ interface LLBank#(
// performance
method Action setPerfStatus(Bool stats);
method Data getPerfData(LLCPerfType t);
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
method EventsLL events;
`endif
// `endif
endinterface
typedef struct {
@@ -241,7 +241,7 @@ module mkLLBank#(
PrefetcherVector#(TDiv#(childNum, 2)) dataPrefetchers <- mkPrefetcherVector(mkLLDPrefetcher);
PrefetcherVector#(TDiv#(childNum, 2)) instrPrefetchers <- mkPrefetcherVector(mkLLIPrefetcher);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
Reg#(Bool) doStats <- mkConfigReg(True);
Count#(Data) dmaMemLdCnt <- mkCount(0);
Count#(Data) dmaMemLdLat <- mkCount(0);
@@ -257,14 +257,14 @@ module mkLLBank#(
Count#(Data) upRespDataCnt <- mkCount(0);
Count#(Data) dmaLdReqCnt <- mkCount(0);
Count#(Data) dmaStReqCnt <- mkCount(0);
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
Array #(Reg #(EventsLL)) perf_events <- mkDRegOR (2, unpack (0));
`endif
// `endif
function Action incrMissCnt(cRqIndexT idx, Bool isDma, Bool isInstructionAccess);
action
let lat <- latTimer.done(idx);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
if(isDma) begin
dmaMemLdCnt.incr(1);
@@ -279,13 +279,13 @@ action
normalMemLdLat.incr(zeroExtend(lat));
end
end
`endif
`ifdef PERFORMANCE_MONITORING
// `endif
// `ifdef PERFORMANCE_MONITORING
EventsLL events = unpack (0);
events.evt_LD_MISS_LAT = saturating_truncate(lat); // Don't support seperate DMA counts.
events.evt_LD_MISS = 1;
perf_events[1] <= events;
`endif
// `endif
endaction
endfunction
@@ -485,7 +485,7 @@ endfunction
);
endrule
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// perf stats: insert new cRq fails because of full MSHR
rule cRqTransfer_new_child_block(
!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Child) && doStats
@@ -504,7 +504,7 @@ endfunction
mshrBlocks.incr(1);
end
endrule
`endif
// `endif
// insert new cRq from DMA to MSHR and send to pipeline
rule cRqTransfer_new_dma(!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma));
@@ -536,7 +536,7 @@ endfunction
fshow(r), " ; ",
fshow(cRq)
);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
if(write) begin
dmaStReqCnt.incr(1);
@@ -545,10 +545,10 @@ endfunction
dmaLdReqCnt.incr(1);
end
end
`endif
// `endif
endrule
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// perf stats: insert new cRq fails because of full MSHR
rule cRqTransfer_new_dma_block(
!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma) && doStats
@@ -568,7 +568,7 @@ endfunction
mshrBlocks.incr(1);
end
endrule
`endif
// `endif
// send downgrade resp from child to pipeline
rule cRsTransfer;
@@ -577,14 +577,14 @@ endfunction
pipeline.send(CRs (cRs));
if (verbose)
$display("%t LL %m cRsTransfer: ", $time, fshow(cRs));
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
downRespCnt.incr(1);
if(isValid(cRs.data)) begin
downRespDataCnt.incr(1);
end
end
`endif
// `endif
endrule
rule discardPrefetchRqResult(rsToCIndexQ.notEmpty && cRqIsPrefetch[rsToCIndexQ.first.cRqId]);
@@ -596,14 +596,14 @@ endfunction
// mem resp for child req, will refill cache, send it to pipeline
(* descending_urgency = "mRsTransfer, cRsTransfer, discardPrefetchRqResult, cRqTransfer_retry, cRqTransfer_new_child, cRqTransfer_new_dma, createInstrPrefetchRq, createDataPrefetchRq" *)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// stop mshr block stats when other higher priority req is being sent to
// pipeline
(* preempts = "mRsTransfer, cRqTransfer_new_child_block" *)
(* preempts = "mRsTransfer, cRqTransfer_new_dma_block" *)
(* preempts = "cRsTransfer, cRqTransfer_new_child_block" *)
(* preempts = "cRsTransfer, cRqTransfer_new_dma_block" *)
`endif
// `endif
rule mRsTransfer(rsFromMQ.first.id.refill);
// get mem resp cRq index & data
rsFromMQ.deq;
@@ -742,11 +742,11 @@ endfunction
toMQ.enq(msg);
// don't deq info, do ld next time
doLdAfterReplace <= True;
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
EventsLL events = unpack (0);
events.evt_ST_MISS = 1;
perf_events[0] <= events;
`endif
// `endif
if (verbose)
$display("%t LL %m sendToM: rep then ld: rep: ", $time, fshow(msg));
end
@@ -832,14 +832,14 @@ endfunction
}));
// release MSHR entry
cRqMshr.sendRsToDmaC.releaseEntry(n);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
upRespCnt.incr(1);
if(isValid(rsData)) begin
upRespDataCnt.incr(1);
end
end
`endif
// `endif
endrule
// send downgrade req to child
@@ -930,11 +930,11 @@ endfunction
);
// change round-robin
whichCRq <= whichCRq == fromInteger(valueOf(cRqNum) - 1) ? 0 : whichCRq + 1;
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
downReqCnt.incr(1);
end
`endif
// `endif
endrule
// Final stage of pipeline: process all kinds of msg
@@ -1657,16 +1657,16 @@ endfunction
endinterface
method Action setPerfStatus(Bool stats);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
doStats <= stats;
`else
noAction;
`endif
// `else
// noAction;
// `endif
endmethod
method Data getPerfData(LLCPerfType t);
return (case(t)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
LLCDmaMemLdCnt: dmaMemLdCnt;
LLCDmaMemLdLat: dmaMemLdLat;
LLCNormalMemLdCnt: normalMemLdCnt;
@@ -1681,13 +1681,13 @@ endfunction
LLCUpRespDataCnt: upRespDataCnt;
LLCDmaLdReqCnt: dmaLdReqCnt;
LLCDmaStReqCnt: dmaStReqCnt;
`endif
// `endif
default: 0;
endcase);
endmethod
`ifdef PERFORMANCE_MONITORING
// `ifdef PERFORMANCE_MONITORING
method EventsLL events = perf_events[0];
`endif
// `endif
endmodule
// Scheduling notes

32
src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
View File

@@ -160,7 +160,7 @@ module mkSelfInvIBank#(
Fifo#(1, DebugICacheResp) cRqDoneQ <- mkBypassFifo;
`endif
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
Reg#(Bool) doStats <- mkConfigReg(False);
Count#(Data) ldCnt <- mkCount(0);
Count#(Data) ldMissCnt <- mkCount(0);
@@ -186,7 +186,7 @@ module mkSelfInvIBank#(
end
endaction
endfunction
`endif
// `endif
function tagT getTag(Addr a) = truncateLSB(a);
@@ -210,10 +210,10 @@ module mkSelfInvIBank#(
}));
// enq to indexQ for in order resp
cRqIndexQ.enq(n);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: cRq type
incrReqCnt;
`endif
// `endif
if (verbose)
$display("%t I %m cRqTransfer: ", $time,
fshow(n), " ; ",
@@ -267,10 +267,10 @@ module mkSelfInvIBank#(
fshow(slot), " ; ",
fshow(cRqToP)
);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: start miss timer
latTimer.start(n);
`endif
// `endif
endrule
// last stage of pipeline: process req
@@ -475,10 +475,10 @@ module mkSelfInvIBank#(
"pRs must be a hit"
);
cRqHit(cOwner, procRq);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: miss cRq
incrMissCnt(cOwner);
`endif
// `endif
end
else begin
doAssert(False, ("pRs owner must match some cRq"));
@@ -498,11 +498,11 @@ module mkSelfInvIBank#(
waitReconcileDone <= True;
if (verbose)
$display("%t I %m startReconcile", $time);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
reconcileCnt.incr(1);
end
`endif
// `endif
endrule
rule completeReconcile(needReconcile && waitReconcileDone && pipeline.reconcile_done);
needReconcile <= False;
@@ -573,21 +573,21 @@ module mkSelfInvIBank#(
endmethod
method Action setPerfStatus(Bool stats);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
doStats <= stats;
`else
noAction;
`endif
// `else
// noAction;
// `endif
endmethod
method Data getPerfData(L1IPerfType t);
return (case(t)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
L1ILdCnt: ldCnt;
L1ILdMissCnt: ldMissCnt;
L1ILdMissLat: ldMissLat;
L1IReconcileCnt: reconcileCnt;
`endif
// `endif
default: 0;
endcase);
endmethod

36
src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
View File

@@ -211,7 +211,7 @@ module mkSelfInvL1Bank#(
Reg#(Bool) waitReconcileDone <- mkReg(False);
// performance
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
Reg#(Bool) doStats <- mkConfigReg(False);
Count#(Data) ldCnt <- mkCount(0);
Count#(Data) stCnt <- mkCount(0);
@@ -260,7 +260,7 @@ module mkSelfInvL1Bank#(
end
endaction
endfunction
`endif
// `endif
function tagT getTag(Addr a) = truncateLSB(a);
@@ -296,10 +296,10 @@ module mkSelfInvL1Bank#(
addr: r.addr,
mshrIdx: n
}));
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: cRq type
incrReqCnt(r.op);
`endif
// `endif
if (verbose)
$display("%t L1 %m cRqTransfer_new: ", $time,
fshow(n), " ; ",
@@ -422,10 +422,10 @@ module mkSelfInvL1Bank#(
fshow(cRqToP)
);
doAssert(slot.cs == I, "we always self-inv before req to parent");
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: start miss timer
latTimer.start(n);
`endif
// `endif
endrule
// last stage of pipeline: process req
@@ -550,11 +550,11 @@ module mkSelfInvL1Bank#(
);
// release MSHR entry
cRqMshr.pipelineResp.releaseEntry(n);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats && needSelfInv) begin
selfInvCnt.incr(1);
end
`endif
// `endif
end
else begin
processAmo <= Valid (AmoHitInfo {
@@ -871,10 +871,10 @@ module mkSelfInvL1Bank#(
("pRs must be a hit")
);
cRqHit(cOwner, procRq, True);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: miss cRq
incrMissCnt(procRq.op, cOwner);
`endif
// `endif
end
else begin
doAssert(False, ("pRs owner must match some cRq"));
@@ -966,11 +966,11 @@ module mkSelfInvL1Bank#(
waitReconcileDone <= True;
if (verbose)
$display("%t L1 %m startReconcile", $time);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
reconcileCnt.incr(1);
end
`endif
// `endif
endrule
rule completeReconcile(needReconcile && waitReconcileDone && pipeline.reconcile_done);
needReconcile <= False;
@@ -1021,16 +1021,16 @@ module mkSelfInvL1Bank#(
endmethod
method Action setPerfStatus(Bool stats);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
doStats <= stats;
`else
noAction;
`endif
// `else
// noAction;
// `endif
endmethod
method Data getPerfData(L1DPerfType t);
return (case(t)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
L1DLdCnt: ldCnt;
L1DStCnt: stCnt;
L1DAmoCnt: amoCnt;
@@ -1042,7 +1042,7 @@ module mkSelfInvL1Bank#(
L1DAmoMissLat: amoMissLat;
L1DSelfInvCnt: selfInvCnt;
L1DReconcileCnt: reconcileCnt;
`endif
// `endif
default: 0;
endcase);
endmethod

60
src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
View File

@@ -213,7 +213,7 @@ module mkSelfInvLLBank#(
`endif
// performance
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
Reg#(Bool) doStats <- mkConfigReg(False);
Count#(Data) dmaMemLdCnt <- mkCount(0);
Count#(Data) dmaMemLdLat <- mkCount(0);
@@ -245,7 +245,7 @@ module mkSelfInvLLBank#(
end
endaction
endfunction
`endif
// `endif
function tagT getTag(Addr a) = truncateLSB(a);
@@ -373,7 +373,7 @@ module mkSelfInvLLBank#(
);
endrule
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// perf stats: insert new cRq fails because of full MSHR
rule cRqTransfer_new_child_block(
!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Child) && doStats
@@ -392,7 +392,7 @@ module mkSelfInvLLBank#(
mshrBlocks.incr(1);
end
endrule
`endif
// `endif
// insert new cRq from DMA to MSHR and send to pipeline
rule cRqTransfer_new_dma(!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma));
@@ -422,7 +422,7 @@ module mkSelfInvLLBank#(
fshow(r), " ; ",
fshow(cRq)
);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
if(write) begin
dmaStReqCnt.incr(1);
@@ -431,10 +431,10 @@ module mkSelfInvLLBank#(
dmaLdReqCnt.incr(1);
end
end
`endif
// `endif
endrule
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// perf stats: insert new cRq fails because of full MSHR
rule cRqTransfer_new_dma_block(
!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma) && doStats
@@ -454,7 +454,7 @@ module mkSelfInvLLBank#(
mshrBlocks.incr(1);
end
endrule
`endif
// `endif
// send downgrade resp from child to pipeline
rule cRsTransfer;
@@ -462,26 +462,26 @@ module mkSelfInvLLBank#(
cRsFromCT cRs = rsFromCQ.first;
pipeline.send(CRs (cRs));
$display("%t LL %m cRsTransfer: ", $time, fshow(cRs));
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
downRespCnt.incr(1);
if(isValid(cRs.data)) begin
downRespDataCnt.incr(1);
end
end
`endif
// `endif
endrule
// mem resp for child req, will refill cache, send it to pipeline
(* descending_urgency = "mRsTransfer, cRsTransfer, cRqTransfer_retry, cRqTransfer_new_child, cRqTransfer_new_dma" *)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// stop mshr block stats when other higher priority req is being sent to
// pipeline
(* preempts = "mRsTransfer, cRqTransfer_new_child_block" *)
(* preempts = "mRsTransfer, cRqTransfer_new_dma_block" *)
(* preempts = "cRsTransfer, cRqTransfer_new_child_block" *)
(* preempts = "cRsTransfer, cRqTransfer_new_dma_block" *)
`endif
// `endif
rule mRsTransfer(rsFromMQ.first.id.refill);
// get mem resp cRq index & data
rsFromMQ.deq;
@@ -504,10 +504,10 @@ module mkSelfInvLLBank#(
fshow(cRq), " ; ",
fshow(cSlot), " ; "
);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: normal miss lat and cnt
incrMissCnt(n, False);
`endif
// `endif
endrule
// this mem resp is just for a DMA req, won't go into pipeline to refill cache
@@ -518,10 +518,10 @@ module mkSelfInvLLBank#(
// save data into cRq mshr & send to DMA resp IndexQ
cRqMshr.mRsDeq.setData(mRs.id.mshrIdx, Valid (mRs.data));
rsLdToDmaIndexQ_mRsDeq.enq(mRs.id.mshrIdx);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: dma miss lat and cnt
incrMissCnt(mRs.id.mshrIdx, True);
`endif
// `endif
endrule
// send rd/wr to mem
@@ -558,10 +558,10 @@ module mkSelfInvLLBank#(
$display("%t LL %m sendToM: load only: ", $time, fshow(msg));
doAssert(!isValid(data), "cannot have data");
doAssert(!doLdAfterReplace, "doLdAfterReplace should be false");
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: start miss timer
latTimer.start(n);
`endif
// `endif
`ifdef DEBUG_DMA
if(cRq.id matches tagged Dma .dmaId) begin
dmaRdMissQ.enq(dmaId); // DMA read takes effect
@@ -603,10 +603,10 @@ module mkSelfInvLLBank#(
toMInfoQ.deq;
doLdAfterReplace <= False;
$display("%t LL %m sendToM: rep then ld: ld: ", $time, fshow(msg));
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
// performance counter: start miss timer
latTimer.start(n);
`endif
// `endif
end
else begin // do write back part
toMemT msg = Wb (WbMemRs {
@@ -698,14 +698,14 @@ module mkSelfInvLLBank#(
}));
// release MSHR entry
cRqMshr.sendRsToDmaC.releaseEntry(n);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
upRespCnt.incr(1);
if(isValid(rsData)) begin
upRespDataCnt.incr(1);
end
end
`endif
// `endif
endrule
// send downgrade req to child
@@ -787,11 +787,11 @@ module mkSelfInvLLBank#(
);
// change round-robin
whichCRq <= whichCRq == fromInteger(valueOf(cRqNum) - 1) ? 0 : whichCRq + 1;
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
if(doStats) begin
downReqCnt.incr(1);
end
`endif
// `endif
endrule
// Final stage of pipeline: process all kinds of msg
@@ -1417,16 +1417,16 @@ module mkSelfInvLLBank#(
endinterface
method Action setPerfStatus(Bool stats);
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
doStats <= stats;
`else
noAction;
`endif
// `else
// noAction;
// `endif
endmethod
method Data getPerfData(LLCPerfType t);
return (case(t)
`ifdef PERF_COUNT
// `ifdef PERF_COUNT
LLCDmaMemLdCnt: dmaMemLdCnt;
LLCDmaMemLdLat: dmaMemLdLat;
LLCNormalMemLdCnt: normalMemLdCnt;
@@ -1439,7 +1439,7 @@ module mkSelfInvLLBank#(
LLCUpRespDataCnt: upRespDataCnt;
LLCDmaLdReqCnt: dmaLdReqCnt;
LLCDmaStReqCnt: dmaStReqCnt;
`endif
// `endif
default: 0;
endcase);
endmethod