From aec3e404ed1c8219a28e42e9382ed60f23dabc1e Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Wed, 10 Nov 2021 08:05:07 +0000 Subject: [PATCH 1/7] Bumped RISCV HPM Events --- libs/RISCV_HPM_Events | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/RISCV_HPM_Events b/libs/RISCV_HPM_Events index ad8aafb..f422ffa 160000 --- a/libs/RISCV_HPM_Events +++ b/libs/RISCV_HPM_Events @@ -1 +1 @@ -Subproject commit ad8aafbbd0bc4f98fbd19d94e02982cae2e44329 +Subproject commit f422ffa0bad3233135d99daa9f8d2b6f1eb95ba1 From 4d1dc29f7953c95820ad3682e13f537275ddedfb Mon Sep 17 00:00:00 2001 From: Marno Date: Wed, 10 Nov 2021 11:48:11 +0000 Subject: [PATCH 2/7] Added ccopytype_bypass --- src_Core/RISCY_OOO/procs/lib/CapChecks.bsvi | 1 + src_Core/RISCY_OOO/procs/lib/Decode.bsv | 1 + src_Core/RISCY_OOO/procs/lib/Exec.bsv | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/src_Core/RISCY_OOO/procs/lib/CapChecks.bsvi b/src_Core/RISCY_OOO/procs/lib/CapChecks.bsvi index 018b513..c13ed2c 100644 --- a/src_Core/RISCY_OOO/procs/lib/CapChecks.bsvi +++ b/src_Core/RISCY_OOO/procs/lib/CapChecks.bsvi @@ -22,4 +22,5 @@ `CAP_CHECK_FIELD(src1_derivable,"src1_derivable") `CAP_CHECK_FIELD(cfromptr_bypass,"cfromptr_bypass") `CAP_CHECK_FIELD(ccseal_bypass,"ccseal_bypass") +`CAP_CHECK_FIELD(ccopytype_bypass,"ccopytype_bypass") `CAP_CHECK_FIELD(cap_exact,"cap_exact") diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv index 8287ad4..b9d84df 100755 --- a/src_Core/RISCY_OOO/procs/lib/Decode.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Decode.bsv @@ -1174,6 +1174,7 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); dInst.capChecks.check_low_src = Src1Type; dInst.capChecks.check_high_src = Src1Type; dInst.capChecks.check_inclusive = False; + dInst.capChecks.ccopytype_bypass = True; dInst.iType = Cap; regs.dst = Valid(tagged Gpr rd); diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv index ef8a315..c99d5a1 100755 --- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv @@ -424,6 +424,10 @@ function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, C capException = Invalid; boundsCheck = Invalid; end + if (dInst.capChecks.ccopytype_bypass && isValidCap(rVal1) && getKind(rVal1) == UNSEALED && !validAsType(rVal1, zeroExtend(getKind(rVal1).SEALED_WITH_TYPE))) begin + capException = Invalid; + boundsCheck = Invalid; + end cf.nextPc = setKind(cf.nextPc, UNSEALED); cf.mispredict = cf.nextPc != ppc; From 6ae92f786bda86c0f5724d2928815f6d58a36cdd Mon Sep 17 00:00:00 2001 From: Marno Date: Thu, 11 Nov 2021 11:36:45 +0000 Subject: [PATCH 3/7] Checking tag and seal on rVal2 and checking type on rVal1 in a way that does not use undefined behavior. --- src_Core/RISCY_OOO/procs/lib/Exec.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv index c99d5a1..e31e1e8 100755 --- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv @@ -424,7 +424,7 @@ function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, C capException = Invalid; boundsCheck = Invalid; end - if (dInst.capChecks.ccopytype_bypass && isValidCap(rVal1) && getKind(rVal1) == UNSEALED && !validAsType(rVal1, zeroExtend(getKind(rVal1).SEALED_WITH_TYPE))) begin + if (dInst.capChecks.ccopytype_bypass && isValidCap(rVal2) && getKind(rVal2) == UNSEALED && (getKind(rVal1) matches tagged SEALED_WITH_TYPE .t ? !validAsType(rVal2, zeroExtend(t)) : True)) begin capException = Invalid; boundsCheck = Invalid; end From 0f86f09b6a677728aa2026cc9300545c9b27c440 Mon Sep 17 00:00:00 2001 From: Marno Date: Thu, 11 Nov 2021 12:15:45 +0000 Subject: [PATCH 4/7] Updated copyright statement --- src_Core/RISCY_OOO/procs/lib/Exec.bsv | 1 + 1 file changed, 1 insertion(+) diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv index e31e1e8..d5e64cb 100755 --- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv @@ -5,6 +5,7 @@ // Copyright (c) 2020 Alexandre Joannou // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2021 Marno van der Maas // All rights reserved. // // This software was developed by SRI International and the University of From 59836cc9e529a04f2f5cb9c799ad003a401cfb83 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 25 Nov 2021 17:39:46 +0000 Subject: [PATCH 5/7] Hopefully optimise this function to have just one call to modifyOffset. --- src_Core/RISCY_OOO/procs/lib/Exec.bsv | 33 +++++++++++++++++++-------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv index d5e64cb..de79c83 100755 --- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv @@ -355,18 +355,31 @@ endfunction (* noinline *) function CapPipe brAddrCalc(CapPipe pc, CapPipe val, IType iType, Data imm, Bool taken, Bit #(32) orig_inst, Bool cap); CapPipe pcPlusN = addPc(pc, ((orig_inst [1:0] == 2'b11) ? 4 : 2)); - if (!cap) val = setOffset(pc, getAddr(val)).value; - CapPipe branchTarget = incOffset(pc, imm).value; - CapPipe jumpTarget = incOffset(val, imm).value; - jumpTarget = setAddrUnsafe(jumpTarget, {truncateLSB(getAddr(jumpTarget)), 1'b0}); - jumpTarget = setKind(jumpTarget, UNSEALED); // It is checked elsewhere that we have an unsealed cap already, or sentry if permitted - CapPipe targetAddr = (case (iType) - J, CJAL : branchTarget; - Jr,CCall,CJALR : jumpTarget; - Br : (taken? branchTarget : pcPlusN); + + //if (!cap) val = setOffset(pc, getAddr(val)).value; + //CapPipe branchTarget = incOffset(pc, imm).value; + //CapPipe jumpTarget = incOffset(val, imm).value; + + CapPipe nextPc = pc; + Data offset = imm; + Bool doInc = True; + if (iType==Jr || iType==CCall || iType ==CJALR) begin + if (cap) nextPc = val; + else begin + offset = getAddr(val) + imm; + doInc = False; + end + end + CapPipe targetAddr = modifyOffset(nextPc, offset, doInc).value; + // jumpTarget.address[0] = 1'b0; + targetAddr = setAddrUnsafe(targetAddr, {truncateLSB(getAddr(targetAddr)), 1'b0}); + targetAddr = setKind(targetAddr, UNSEALED); // It is checked elsewhere that we have an unsealed cap already, or sentry if permitted + + return (case (iType) + J, CJAL, Jr, CCall, CJALR: targetAddr; + Br : (taken ? targetAddr : pcPlusN); default : pcPlusN; endcase); - return targetAddr; endfunction /* (* noinline *) From 37074525e149ad7f5f5253278c5660173f00cb59 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 29 Nov 2021 10:38:23 +0000 Subject: [PATCH 6/7] removed unnecessary execute permissions for Decode.bsv, Exec.bsv, ProcTypes.bsv, ReorderBuffer.bsv, and AluExePipeline.bsv --- src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 0 src_Core/RISCY_OOO/procs/lib/Decode.bsv | 0 src_Core/RISCY_OOO/procs/lib/Exec.bsv | 0 src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv | 0 src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv | 0 5 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv mode change 100755 => 100644 src_Core/RISCY_OOO/procs/lib/Decode.bsv mode change 100755 => 100644 src_Core/RISCY_OOO/procs/lib/Exec.bsv mode change 100755 => 100644 src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv mode change 100755 => 100644 src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv old mode 100755 new mode 100644 diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv old mode 100755 new mode 100644 diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv old mode 100755 new mode 100644 diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv old mode 100755 new mode 100644 diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv old mode 100755 new mode 100644 From 34c6ee1894e4441d43df752c375beac7e8fa70f1 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Fri, 3 Dec 2021 12:36:40 +0000 Subject: [PATCH 7/7] Specifically give priority to wrong_spec when they conflict. This appears to yield 10% performance improvement as our default setup appears to choose a wrong priority. --- .../RISCY_OOO/procs/lib/ReorderBuffer.bsv | 9 ++-- src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv | 41 +++++++++---------- 2 files changed, 23 insertions(+), 27 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index 784f28c..1ca4aa7 100644 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -685,7 +685,7 @@ module mkSupReorderBuffer#( // these are handled in mkReorderBufferRowEhr // wrong speculation: make wrong speculation conflict with enq - Vector#(SupSize, RWire#(void)) wrongSpec_enq_conflict <- replicateM(mkRWire); + Vector#(SupSize, PulseWire) wrongSpec_enq_conflict <- replicateM(mkPulseWire); // SupSize number of FIFOs Vector#(SupSize, Vector#(SingleScalarSize, ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum))) row <- replicateM(replicateM(mkRobRow)); @@ -1051,12 +1051,11 @@ module mkSupReorderBuffer#( Bool can_enq = can_enq_fifo[way]; enqIfc[i] = (interface ROB_EnqPort; method Bool canEnq = can_enq; - method Action enq(ToReorderBuffer x) if(can_enq); + method Action enq(ToReorderBuffer x) if(can_enq + && !wrongSpec_enq_conflict[i]); // make it conflict with wrong speculation doAssert(getEnqPort(way) == fromInteger(i), "enq FIFO way matches enq port"); // record enq action, real action is applied later enqEn[i].wset(x); - // make it conflict with wrong speculation - wrongSpec_enq_conflict[i].wset(?); // ordering: sequence after many other methods deq_SB_enq[i] <= False; setExeAlu_SB_enq[i] <= False; @@ -1321,7 +1320,7 @@ module mkSupReorderBuffer#( deq_SB_wrongSpec <= False; // make it conflict with enq for(Integer i = 0; i < valueof(SupSize); i = i+1) begin - wrongSpec_enq_conflict[i].wset(?); + wrongSpec_enq_conflict[i].send; end endmethod endinterface diff --git a/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv b/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv index 332dccb..818a340 100644 --- a/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv +++ b/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv @@ -88,21 +88,21 @@ module mkSpecFifo#( Reg#(idxT) deqP = deqP_ehr[0]; // port 0 is for deq and canon_deqP // make incorrectSpeculation conflict with others - RWire#(void) dummyRWire = (interface RWire; - method Maybe#(void) wget = Invalid; - method Action wset(void x) = noAction; - endinterface); - RWire#(void) wrongSpec_enq_conflict = dummyRWire; - RWire#(void) wrongSpec_deq_conflict = dummyRWire; - RWire#(void) wrongSpec_canon_conflict = dummyRWire; + PulseWire dummyPulseWire = interface PulseWire; + method Bool _read = False; + method Action send = noAction; + endinterface; + PulseWire wrongSpec_enq_conflict = dummyPulseWire; + PulseWire wrongSpec_deq_conflict = dummyPulseWire; + PulseWire wrongSpec_canon_conflict = dummyPulseWire; if(sched.wrongSpec_conflict_enq) begin - wrongSpec_enq_conflict <- mkRWire; + wrongSpec_enq_conflict <- mkPulseWire; end if(sched.wrongSpec_conflict_deq) begin - wrongSpec_deq_conflict <- mkRWire; + wrongSpec_deq_conflict <- mkPulseWire; end if(sched.wrongSpec_conflict_canon) begin - wrongSpec_canon_conflict <- mkRWire; + wrongSpec_canon_conflict <- mkPulseWire; end function idxT getNextPtr(idxT p); @@ -110,11 +110,10 @@ module mkSpecFifo#( endfunction Bool empty_for_canon = all( \== (False) , readVEhr(sched.validDeqPort, valid) ); - rule canon_deqP(!valid[deqP][sched.validDeqPort] && (enqP != deqP || !empty_for_canon)); + rule canon_deqP(!valid[deqP][sched.validDeqPort] && (enqP != deqP || !empty_for_canon) + && !wrongSpec_canon_conflict); // make conflict with incorrect spec // element at deqP was killed, so increment deqP deqP <= getNextPtr(deqP); - // make conflict with incorrect spec - wrongSpec_canon_conflict.wset(?); endrule // calculate guard for enq, we can do aggressively or lazily @@ -144,22 +143,20 @@ module mkSpecFifo#( valid_for_enq = valid[enqP][sched.validEnqPort]; end - method Action enq(ToSpecFifo#(t) x) if (empty_for_enq || enqP != deqP_for_enq); + method Action enq(ToSpecFifo#(t) x) if ((empty_for_enq || enqP != deqP_for_enq) + && !wrongSpec_enq_conflict); // make conflict with incorrect spec // [sizhuo] I don't think valid bit needs to be checked here doAssert(!valid_for_enq, "enq entry cannot be valid"); enqP <= getNextPtr(enqP); valid[enqP][sched.validEnqPort] <= True; row[enqP] <= x.data; specBits[enqP][sched.sbEnqPort] <= x.spec_bits; - // make conflict with incorrect spec - wrongSpec_enq_conflict.wset(?); endmethod - method Action deq if (valid[deqP][sched.validDeqPort]); + method Action deq if (valid[deqP][sched.validDeqPort] + && !wrongSpec_deq_conflict); // make conflict with incorrect spec valid[deqP][sched.validDeqPort] <= False; deqP <= getNextPtr(deqP); - // make conflict with incorrect spec - wrongSpec_deq_conflict.wset(?); endmethod method ToSpecFifo#(t) first if (valid[deqP][sched.validDeqPort]); @@ -195,9 +192,9 @@ module mkSpecFifo#( Vector#(size, Integer) idxVec = genVector; joinActions(map(incorrectSpec, idxVec)); // make conflict with others - wrongSpec_enq_conflict.wset(?); - wrongSpec_canon_conflict.wset(?); - wrongSpec_deq_conflict.wset(?); + wrongSpec_enq_conflict.send; + wrongSpec_canon_conflict.send; + wrongSpec_deq_conflict.send; endmethod endinterface endmodule