diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 6c0ea47..ee84408 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -1362,7 +1362,7 @@ module mkCore#(CoreId coreId)(Core);
       Bit #(12) csr_addr = req.address;
       let data_out = csrf.rd (unpack (csr_addr));
 
-      let rsp = DM_CPU_Rsp {ok: True, data: data_out};
+      let rsp = DM_CPU_Rsp {ok: implementedCSR(csr_addr), data: data_out};
       f_csr_rsps.enq (rsp);
 
       if (show_DM_interactions)
diff --git a/src_Core/Debug_Module/DM_Abstract_Commands.bsv b/src_Core/Debug_Module/DM_Abstract_Commands.bsv
index 88fffb9..b090df2 100644
--- a/src_Core/Debug_Module/DM_Abstract_Commands.bsv
+++ b/src_Core/Debug_Module/DM_Abstract_Commands.bsv
@@ -298,7 +298,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	       if (verbosity != 0)
 		  $display ("%0d: DM_Abstract_Commands.rl_csr_write_finish hart %0d: ", cur_cycle, core, fshow (rsp));
 
-	       rg_abstractcs_cmderr <= (rsp.ok ? DM_ABSTRACTCS_CMDERR_NONE : DM_ABSTRACTCS_CMDERR_HALT_RESUME);
+	       rg_abstractcs_cmderr <= (rsp.ok ? DM_ABSTRACTCS_CMDERR_NONE : DM_ABSTRACTCS_CMDERR_EXCEPTION);
 	       rg_abstractcs_busy   <= False;
 	    endrule
 	 endrules
diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
index ba191ad..208a2e6 100644
--- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
@@ -258,6 +258,15 @@ function CSR unpackCSR(Bit#(12) addr);
     endcase);
 endfunction
 
+function Bool implementedCSR(Bit#(12) addr);
+    return (case(addr)
+`define CSR(n, v) v: True;
+`include "CSRs.bsvi"
+`undef CSR
+        default: False;
+    endcase);
+endfunction
+
 // values for MSPEC CSR
 Bit#(2) mSpecAll    = 0; // every inst can speculate
 Bit#(2) mSpecNonMem = 1; // only non-memory inst can speculate